LTC3407-4
更新时间:2024-09-18 07:32:53
品牌:Linear
描述:Dual Synchronous, 800mA, 2.25MHz Step-Down DC/DC Regulator
LTC3407-4 概述
Dual Synchronous, 800mA, 2.25MHz Step-Down DC/DC Regulator 双同步, 800毫安, 2.25MHz降压型DC / DC稳压器
LTC3407-4 数据手册
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PDF下载LTC3407-4
Dual Synchronous, 800mA,
2.25MHz Step-Down
DC/DC Regulator
U
DESCRIPTIO
FEATURES
The LTC®3407-4 is a dual, constant frequency, synchro-
nous step down DC/DC converter. Intended for low power
applications, it operates from 2.5V to 5.5V input voltage
range and has a constant 2.25MHz switching frequency,
allowing the use of tiny, low cost capacitors and inductors
with a profile ≤1mm. Each output voltage is adjustable
from 0.6V to 5V. Internal synchronous 0.35Ω, 1.2A power
switches provide high efficiency without the need for
external Schottky diodes.
■
High Efficiency: Up to 95%
■
Very Low Quiescent Current: Only 40µA
■
2.25MHz Constant Frequency Operation
■
High Switch Current: 1.2A on Each Channel
■
No Schottky Diodes Required
■
Low RDS(ON) Internal Switches: 0.35Ω
■
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
■
■
Low Dropout Operation: 100% Duty Cycle
A user selectable mode input is provided to allow the user
to trade-off noise ripple for low power efficiency. Burst
Mode® operation provides high efficiency at light loads,
while Pulse Skip Mode provides low noise ripple at light
loads.
■
Ultralow Shutdown Current: IQ < 1µA
■
Output Voltages from 5V down to 0.6V
■
Power-On Reset Output
■
Externally Synchronizable Oscillator
■
Small Thermally Enhanced MSOP and 3mm × 3mm
To further maximize battery life, the P-channel MOSFETs
are turned on continuously in dropout (100% duty cycle),
and both channels draw a total quiescent current of only
40µA. In shutdown, the device draws <1µA.
DFN Packages
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APPLICATIO S
■
PDAs/Palmtop PCs
■
Digital Cameras
The LTC3407-4 is identical to the LTC3407-2 except for
the reduced power-on reset delay time.
, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815,
6498466, 6611131
■
Cellular Phones
■
Portable Media Players
■
PC Cards
■
Wireless and DSL Modems
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TYPICAL APPLICATIO
LTC3407-4 Efficiency/Power Loss Curve
V
*
IN
2.5V TO 5.5V
100
90
80
70
60
50
40
30
20
10
0
1
R5
C1
10µF
100k
RUN2
MODE/SYNC
LTC3407-4
V
RUN1
POR
IN
RESET
0.1
L2
L1
2.2µH
2.2µH
V
V
OUT2
2.5V
800mA
OUT1
SW2
SW1
1.8V
C5, 22pF
C4, 22pF
800mA
0.01
0.001
0.0001
V
FB1
V
FB2
R4
887k
R2
604k
GND
C3
10µF
C2
10µF
R3
280k
R1
301k
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML
L1, L2: MURATA LQH32CN2R2M33
0.1
1
10
100
1000
3407 TA01
*V CONNECTED TO V FOR V ≤ 2.8V
OUT IN IN
LOAD CURRENT (mA)
34074 TA02
Figure 1. 2.5V/1.8V at 800mA Step-Down Regulators
34074f
1
LTC3407-4
W W U W
ABSOLUTE AXI U RATI GS (Note 1)
Ambient Operating Temperature
VIN Voltages.................................................–0.3V to 6V
VFB1, VFB2 Voltages......................... –0.3V to VIN + 0.3V
RUN1, RUN2 Voltages ................................ –0.3V to VIN
MODE/SYNC Voltage ..................................–0.3V to VIN
SW1, SW2 Voltage ......................... –0.3V to VIN + 0.3V
POR Voltage ................................................–0.3V to 6V
Range (Note 2) ....................................... –40°C to 85°C
Junction Temperature (Note 5)............................. 125°C
Storage Temperature Range ................. – 65°C to 125°C
Lead Temperature (Soldering, 10 sec)
LTC3407-4EMSE only ...................................... 300°C
Reflow Peak Body Temperature............................ 260°C
U
W
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
V
1
2
3
4
5
10
9
V
FB2
FB1
RUN1
V
1
2
3
4
5
10
9
V
FB2
FB1
RUN2
POR
RUN1
RUN2
POR
V
SW1
GND
11
8
11
IN
V
8
IN
7
6
SW2
MODE/
SYNC
SW1
GND
7
SW2
6
MODE/
SYNC
MSE PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 11) IS PGND, MUST BE CONNECTED TO GND
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 11) IS PGND, MUST BE CONNECTED TO GND
ORDER PART NUMBER
LTC3407EDD-4
Order Options Tape and Reel: Add #TR
DD PART MARKING
LCJD
ORDER PART NUMBER
LTC3407EMSE-4
MSE PART MARKING
LTCJC
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 3.6V, unless otherwise specified. (Note 2)
A
IN
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
V
V
IN
Operating Voltage Range
Feedback Pin Input Current
Feedback Voltage (Note 3)
●
●
2.5
I
30
nA
FB
V
FB
0°C ≤ T ≤ 85°C
0.588
0.585
0.6
0.6
0.612
0.612
V
V
A
–40°C ≤ T ≤ 85°C
●
A
∆V
∆V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 2.5V to 5.5V (Note 3)
0.3
0.5
0.5
%/V
%
LINE REG
IN
(Note 3)
LOAD REG
I
Input DC Supply Current (Note 4)
Active Mode
S
V
V
= V = 0.5V
700
40
0.1
950
60
1
µA
µA
µA
FB1
FB1
FB2
Sleep Mode
= V = 0.63V, MODE/SYNC = 3.6V
FB2
Shutdown
RUN = 0V, V = 5.5V, MODE/SYNC = 0V
IN
f
f
I
Oscillator Frequency
V
= 0.6V
FBX
●
1.8
2.25
2.25
1.2
2.7
MHz
MHz
A
OSC
SYNC
LIM
Synchronization Frequency
Peak Switch Current Limit
V
IN
= 3V, V = 0.5V, Duty Cycle <35%
0.95
1.6
FBX
R
Top Switch On-Resistance
Bottom Switch On-Resistance
(Note 6)
(Note 6)
0.35
0.30
0.45
0.45
Ω
Ω
DS(ON)
I
Switch Leakage Current
V
IN
= 5V, V
= 0V, V = 0V
FBX
0.01
1
µA
SW(LKG)
RUN
34074f
2
LTC3407-4
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 3.6V, unless otherwise specified. (Note 2)
A
IN
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POR
Power-On Reset Threshold
V
V
Ramping Up, MODE/SYNC = 0V
Ramping Down, MODE/SYNC = 0V
8.5
–8.5
%
%
FBX
FBX
Power-On Reset On-Resistance
Power-On Reset Delay
RUN Threshold
100
65536
1
200
Ω
Cycles
V
●
●
0.3
0
1.5
1
V
µA
V
RUN
I
RUN Leakage Current
MODE Threshold Low
MODE Threshold High
0.01
RUN
V
0.5
MODE
V
– 0.5
V
IN
V
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Pins of regulators should not exceed 6V
Note 3: The LTC3407-4 is tested in a proprietary test mode that connects
to the output of the error amplifier.
Note 4: Dynamic supply current is higher due to the internal gate charge
V
FB
being delivered at the switching frequency.
Note 2: The LTC3407E-4 is guaranteed to meet specified performance
from 0°C to 85°C. Specifications over the –40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: T is calculated from the ambient T and power dissipation P
D
J
A
according to the following formula: T = T + (P • θ ).
J
A
D
JA
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
U W
TYPICAL PERFOR A CE CHARACTERISTICS T = 25°C unless otherwise specified.
A
Load Step
Burst Mode Operation
Pulse Skipping Mode
SW
5V/DIV
SW
5V/DIV
V
OUT
200mV/DIV
V
I
OUT
L
V
OUT
20mV/DIV
500mA/DIV
20mV/DIV
I
LOAD
I
L
I
500mA/DIV
L
200mA/DIV
200mA/DIV
34073 G01
34073 G02
34074 G03
V
V
I
= 3.6V
2µs/DIV
V
V
I
= 3.6V
1µs/DIV
V
V
I
= 3.6V
10µs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 1.8V
= 100mA
= 20mA
= 80mA ~ 800mA
LOAD
LOAD
LOAD
34074f
3
LTC3407-4
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency Deviation
vs Supply Voltage
Oscillator Frequency vs
Efficiency vs Input Voltage
Temperature
100
95
90
85
80
75
70
65
60
55
50
10
8
2.5
2.4
2.3
2.2
2.1
2.0
V
IN
= 3.6V
LOAD = 100mA LOAD = 10mA
6
4
LOAD = 800mA
LOAD = 1mA
2
0
–2
–4
–6
–8
–10
V
= 1.8V
OUT
Burst Mode OPERATION
4
5
6
2
3
2
3
4
5
6
–50
25
50
75
100 125
–25
0
INPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
34074 G06
34074 G04
34074 G05
Reference Voltage vs
Temperature
R
vs Input Voltage
R
vs Temperature
DS(ON)
DS(ON)
0.615
0.610
0.605
0.600
0.595
0.590
0.585
550
500
450
400
350
300
250
200
150
100
500
450
400
350
300
250
200
V
= 2.7V
V
IN
= 3.6V
IN
V
= 3.6V
IN
V
= 4.2V
IN
MAIN
SWITCH
SYNCHRONOUS
SWITCH
MAIN SWITCH
SYNCHRONOUS SWITCH
3
2
50
TEMPERATURE (°C)
100 125 150
5
7
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
1
4
6
–50 –25
0
25
75
V
(V)
IN
34074 G09
34074 G08
34074 G07
Efficiency vs Load Current
Efficiency vs Load Current
Load Regulation
100
95
90
85
80
75
70
65
60
100
90
80
70
60
4
3
V
IN
= 2.7V
V
IN
= 3.6V
Burst Mode
OPERATION
2
V
IN
= 4.2V
Burst Mode
OPERATION
1
0
PULSE SKIP
MODE
PULSE SKIP
MODE
–1
–2
–3
–4
V
= 2.5V
OUT
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
V
= 3.6V, V
OUT
= 1.8V
V
= 3.6V, V
= 1.8V
OUT
IN
IN
NO LOAD ON OTHER CHANNEL
NO LOAD ON OTHER CHANNEL
10 100 1000
LOAD CURRENT (mA)
1
10 100
LOAD CURRENT (mA)
1000
1
1
10
100
1000
LOAD CURRENT (mA)
LTC1273/75/76 • F25
34074 G12
34074 G11
34074f
4
LTC3407-4
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
Efficiency vs Load Current
Line Regulation
100
90
100
90
80
70
60
0.8
0.6
V
I
A
= 1.8V
OUT
OUT
V
IN
= 3.6V
V
IN
= 2.7V
= 200mA
T
= 25°C
80
V
= 2.7V
IN
V
= 4.2V
0.4
IN
V
= 3.6V
IN
70
0.2
60
50
0
V
= 4.2V
IN
–0.2
–0.4
–0.6
–0.8
–1.0
40
30
20
V
= 1.2V
V
= 1.5V
OUT
OUT
10 Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
0
4
2
3
5
6
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
V
(V)
LOAD CURRENT (mA)
IN
34074 G13
34074 G15
34074 G14
U
U
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PI FU CTIO S
VFB1 (Pin 1): Output Feedback. Receives the feedback
voltage from the external resistive divider across the
output. Nominal voltage for this pin is 0.6V.
be syncronized to an external oscillator applied to this pin
and pulse skipping mode is automatically selected.
SW2 (Pin 7): Regulator 2 Switch Node Connection to the
Inductor. This pin swings from VIN to GND.
RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to VIN
enables regulator 1, while forcing it to GND causes regu-
lator 1 to shut down. This pin must be driven; do not float.
POR (Pin 8): Power-On Reset . This common-drain logic
output is pulled to GND when the output voltage is not
within±8.5%ofregulationandgoeshighafter216 ofclock
cycles when both channels are within regulation.
VIN (Pin3):MainPowerSupply.Mustbecloselydecoupled
to GND.
SW1 (Pin 4): Regulator 1 Switch Node Connection to the
RUN2 (Pin 9): Regulator 2 Enable. Forcing this pin to VIN
enables regulator 2, while forcing it to GND causes regu-
lator 2 to shut down. This pin must be driven; do not float.
Inductor. This pin swings from VIN to GND.
GND (Pin 5): Ground. Connect to the (–) terminal of COUT
and (–) terminal of CIN.
,
VFB2 (Pin 10): Output Feedback. Receives the feedback
voltage from the external resistive divider across the
output. Nominal voltage for this pin is 0.6V.
MODE/SYNC (Pin 6): Combination Mode Selection and
OscillatorSynchronization.Thispincontrolstheoperation
of the device. When tied to VIN or GND, Burst Mode
operation or pulse skipping mode is selected, respec-
tively. Do not float this pin. The oscillation frequency can
Exposed Pad (GND) (Pin 11): Power Ground. Connect to
the (–) terminal of COUT, and (–) terminal of CIN. Must be
connected to electrical ground on PCB.
34074f
5
LTC3407-4
W
BLOCK DIAGRA
REGULATOR 1
MODE/SYNC
6
BURST
CLAMP
V
IN
SLOPE
COMP
EN
–
+
+
–
0.6V
SLEEP
–
+
I
TH
5Ω
EA
I
COMP
0.35V
V
FB1
1
BURST
Q
S
R
RS
LATCH
Q
0.55V
–
+
SWITCHING
LOGIC
UV
OV
UVDET
OVDET
AND
BLANKING
CIRCUIT
ANTI
SHOOT-
THRU
4
SW1
+
–
0.65V
+
–
I
RCMP
SHUTDOWN
11 GND
V
IN
3
8
V
IN
PGOOD1
POR
2
9
RUN1
RUN2
POR
COUNTER
0.6V REF
OSC
OSC
5
7
GND
PGOOD2
REGULATOR 2 (IDENTICAL TO REGULATOR 1)
10
SW2
V
FB2
U
OPERATIO
Main Control Loop
The LTC3407-4 uses a constant frequency, current mode
architecture. The operating frequency is set at 2.25MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit
a variety of applications, the selectable Mode pin allows
the user to choose between low noise and high efficiency.
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the VFB voltage is below the the reference voltage.
The current into the inductor and the load increases until
the current limit is reached. The switch turns off and
energy stored in the inductor flows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.
The output voltage is set by an external divider returned to
the VFB pins. An error amplfier compares the divided
outputvoltagewithareferencevoltageof0.6Vandadjusts
the peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the POR output low if
the output voltage is not within ±8.5%. The POR output
will go high after 216 clock cycles (about 29ms in pulse
skipping mode) of achieving regulation.
The peak inductor current is controlled by the internally
compensated ITH voltage, which is the output of the error
amplifier.This amplifier compares the VFB pin to the 0.6V
reference. When the load current increases, the VFB volt-
age decreases slightly below the reference. This
34074f
6
LTC3407-4
U
OPERATIO
decrease causes the error amplifier to increase the ITH For lower ripple noise at low currents, the pulse skipping
voltageuntiltheaverageinductorcurrentmatchesthenew modecanbeused. Inthismode, theLTC3407-4continues
to switch at a constant frequency down to very low
currents, where it will begin skipping pulses. The effi-
ciency in pulse skip mode can be improved slightly by
connecting the SW node to the MODE/SYNC input which
reduces the clock frequency by approximately 30%.
load current.
The main control loop is shut down by pulling the RUN pin
to ground.
Low Current Operation
Two modes are available to control the operation of the
LTC3407-4 at low currents. Both modes automatically
switch from continuous operation to the selected mode
when the load current is low.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which is
the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being
equal to the input voltage minus the voltage drops across
the internal p-channel MOSFET and the inductor.
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3407-4
automatically switches into Burst Mode operation, in
which the PMOS switch operates intermittently based on
load demand with a fixed peak inductor current. By run-
ning cycles periodically, the switching losses which are
dominatedbythegatechargelossesofthepowerMOSFETs
are minimized. The main control loop is interrupted when
the output voltage reaches the desired regulated value. A
hysteretic voltage comparator trips when ITH is below
0.35V, shuttingofftheswitchandreducingthepower. The
output capacitor and the inductor supply the power to the
load until ITH exceeds 0.65V, turning on the switch and the
main control loop which starts another cycle.
An important design consideration is that the RDS(ON) of
the P-channel switch increases with decreasing input
supplyvoltage(SeeTypicalPerformanceCharacteristics).
Therefore, the user should calculate the power dissipation
when the LTC3407-4 is used at 100% duty cycle with low
input voltage (See Thermal Considerations in the Applica-
tions Information Section).
Low Supply Operation
To prevent unstable operation, the LTC3407-4 incorpo-
rates an Under-Voltage Lockout circuit which shuts down
the part when the input voltage drops below about 1.65V.
W U U
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APPLICATIO S I FOR ATIO
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.
A reasonable starting point for setting ripple current is
∆IL = 0.3 • ILIM, where ILIM is the peak switch current limit.
The largest ripple current ∆IL occurs at the maximum
input voltage. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
A general LTC3407-4 application circuit is shown in
Figure 2. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L. Once the inductor is chosen, CIN and COUT can
be selected.
Inductor Selection
Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current ∆IL decreases with
⎛
⎞
VOUT
fO • ∆IL
VOUT
V
IN(MAX)
higher inductance and increases with higher VIN or VOUT
:
L =
• 1–
⎜
⎟
⎝
⎠
⎛
⎞
VOUT
fO •L
VOUT
V
IN
∆IL =
• 1–
⎜
⎟
The inductor value will also have an effect on Burst Mode
⎝
⎠
operation. The transition from low current operation
34074f
7
LTC3407-4
U
W U U
APPLICATIO S I FOR ATIO
Table 1. Representative Surface Mount Inductors
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency to
increase.
PART
NUMBER
VALUE
(µH)
DCR
MAX DC
SIZE
3
(Ω MAX) CURRENT (A) W × L × H (mm )
Sumida
CDRH3D16
2.2
3.3
4.7
0.075
0.110
0.162
1.20
1.10
0.90
3.8 × 3.8 × 1.8
Sumida
CDRH2D11
1.5
2.2
0.068
0.170
0.900
0.780
3.2 × 3.2 × 1.2
4.4 × 5.8 × 1.2
2.5 × 3.2 × 2.0
2.5 × 3.2 × 2.0
4.5 × 5.4 × 1.2
Inductor Core Selection
Sumida
CMD4D11
2.2
3.3
0.116
0.174
0.950
0.770
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don’t radiate much energy, but gener-
ally cost more than powdered iron core inductors with
similar electrical characterisitics. The choice of which
style inductor to use often depends more on the price vs
size requirements and any radiated field/EMI require-
ments than on what the LTC3407-4 requires to operate.
Table 1 shows some typical surface mount inductors that
work well in LTC3407-4 applications.
Murata
LQH32CN
1.0
2.2
0.060
0.097
1.00
0.79
Toko
D312F
2.2
3.3
0.060
0.260
1.08
0.92
Panasonic
ELT5KT
3.3
4.7
0.17
0.20
1.00
0.95
Output Capacitor (COUT) Selection
The selection of COUT is driven by the required ESR to
minimizevoltagerippleandloadsteptransients.Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering. The output ripple (∆VOUT) is deter-
mined by:
Input Capacitor (CIN) Selection
In continuous mode, the input current of the converter is
a square wave with a duty cycle of approximately VOUT
/
VIN. To prevent large voltage transients, a low equivalent
series resistance (ESR) input capacitor sized for the maxi-
mum RMS current must be used. The maximum RMS
capacitor current is given by:
⎛
⎞
1
∆VOUT ≈ ∆IL ESR +
⎜
⎟
8fO COUT
⎝
⎠
where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.3 • ILIM the output ripple
willbelessthan100mVatmaximumVIN andfO =2.25MHz
with:
VOUT V – V
(
)
IN
OUT
IRMS ≈IMAX
V
IN
where the maximum average output current IMAX equals
the peak current minus half the peak-to-peak ripple cur-
rent, IMAX = ILIM – ∆IL/2.
ESRCOUT < 150mΩ
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case is commonly used to
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours life-
time. This makes it advisable to further derate the capaci-
tor, or choose a capacitor rated at a higher temperature
thanrequired. Severalcapacitorsmayalsobeparalleledto
meet the size or height requirements of the design. An
additional 0.1µF to 1µF ceramic capacitor is also recom-
mended on VIN for high frequency decoupling, when not
using an all ceramic capacitor solution.
Once the ESR requirements for COUT have been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Alumi-
numelectrolytic,specialpolymer,ceramicanddrytantulum
capacitorsareallavailableinsurfacemountpackages.The
OS-CONsemiconductordielectriccapacitoravailablefrom
Sanyo has the lowest ESR(size) product of any aluminum
electrolytic at a somewhat higher price. Special polymer
34074f
8
LTC3407-4
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APPLICATIO S I FOR ATIO
capacitors, such as Sanyo POSCAP, Panasonic Special
Polymer (SP), and Kemet A700, offer very low ESR, but
have a lower capacitance density than other types. Tanta-
lum capacitors have the highest capacitance density, but
they have a larger ESR and it is critical that the capacitors
are surge tested for use in switching power supplies. An
excellent choice is the AVX TPS series of surface mount
tantalums, available in case heights ranging from 2mm to
4mm. Aluminum electrolytic capacitors have a signifi-
cantly larger ESR, and are often used in extremely cost-
sensitiveapplicationsprovidedthatconsiderationisgiven
to ripple current ratings and long term reliability. Ceramic
capacitorshavethelowestESRandcost, butalsohavethe
lowest capacitance density, a high voltage and tempera-
ture coefficient, and exhibit audible piezoelectric effects.
In addition, the high Q of ceramic capacitors along with
trace inductance can lead to significant ringing.
requires the designer to check loop stability over the
operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used. A good selection of
ceramic capacitors is available from Taiyo Yuden, AVX,
Kemet, TDK, and Murata.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires,suchasfromawalladapter,aloadstepattheoutput
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, the ringing at the input can be large enough to
damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
untilthefeedbackloopraisestheswitchcurrentenoughto
support the load. The time required for the feedback loop
to respond is dependent on the compensation and the
output capacitor size. Typically, 3-4 cycles are required to
respond to a load step, but only in the first cycle does the
output drop linearly. The output droop, VDROOP, is usually
about 2-3 times the linear drop of the first cycle. Thus, a
good place to start is with the output capacitor size of
approximately:
In most cases, 0.1µF to 1µF of ceramic capacitors should
also be placed close to the LTC3407-4 in parallel with the
main capacitors for high frequency decoupling.
V
IN
2.5V TO 5.5V
C
IN
R5
RUN2
V
RUN1
POR
IN
BM*
POWER-ON
RESET
MODE/SYNC
PS*
LTC3407-4
L1
L2
C5
V
OUT2
SW2
SW1
V
OUT1
C4
V
V
FB2
FB1
R4
R2
GND
R1
C
OUT1
C
OUT2
R3
∆IOUT
fO •VDROOP
3407 F02
COUT ≈ 2.5
*MODE/SYNC = 0V: PULSE SKIP
MODE/SYNC = V : Burst Mode
IN
More capacitance may be required depending on the duty
cycle and load step requirements.
Figure 2. LTC3407-4 General Schematic
Ceramic Input and Output Capacitors
In most applications, the input capacitor is merely re-
quired to supply high frequency bypassing, since the
impedance to the supply is very low. A 10µF ceramic
capacitor is usually enough for these conditions.
Higher value, lower cost ceramic capacitors are now
becomingavailableinsmallercasesizes.Thesearetempt-
ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generatesaloop“zero”at5kHzto50kHzthatisinstrumen-
tal in giving acceptable loop phase margin. Ceramic ca-
pacitors remain capacitive to beyond 300kHz and usually
resonate with their ESL before ESR becomes effective.
Also, ceramic caps are prone to temperature effects which
Setting the Output Voltage
The LTC3407-4 develops a 0.6V reference voltage be-
tween the feedback pin, VFB, and the ground as shown in
Figure 2. The output voltage is set by a resistive divider
according to the following formula:
34074f
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LTC3407-4
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APPLICATIO S I FOR ATIO
Checking Transient Response
⎛
⎞
R2
R1
VOUT = 0.6V 1+
⎜
⎟
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD • ESR, where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT, generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability
problem.
⎝
⎠
Keeping the current small (<5µA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
To improve the frequency response, a feed-forward ca-
pacitor CF may also be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second-
order overshoot/DC ratio cannot be used to determine
phase margin. In addition, a feed-forward capacitor, CF,
can be added to improve the high frequency response, as
shown in Figure 2. Capacitor CF provides phase lead by
creating a high frequency zero with R2, which improves
the phase margin.
Power-On Reset
The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output
voltages are within ±8.5% of regulation, a timer is started
which releases POR after 216 clock cycles (about 29ms).
This delay can be significantly longer in Burst Mode
operation with low load currents, since the clock cycles
only occur during a burst and there could be milliseconds
of time between bursts. This can be bypassed by tying the
POR output to the MODE/SYNC input, to force pulse
skipping mode during a reset. In addition, if the output
voltage faults during Burst Mode sleep, POR could have a
slight delay for an undervoltage output condition and may
notrespondtoanovervoltageoutput. Thiscanbeavoided
by using pulse skipping mode instead. When either chan-
nel is shut down, the POR output is pulled low, since one
or both of the channels are not in regulation.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Applica-
tion Note 76.
In some applications, a more severe transient can be
caused by switching in loads with large (>1µF) input
capacitors.Thedischargedinputcapacitorsareeffectively
put in parallel with COUT, causing a rapid drop in VOUT. No
regulator can deliver enough current to prevent this prob-
Mode Selection & Frequency Synchronization
TheMODE/SYNCpinisamultipurposepinwhichprovides lem, if the switch connecting the load has low resistance
mode selection and frequency synchronization. Connect- and is driven quickly. The solution is to limit the turn-on
ing this pin to VIN enables Burst Mode operation, which speed of the load switch driver. A Hot SwapTM controller is
provides the best low current efficiency at the cost of a designedspecificallyforthispurposeandusuallyincorpo-
higheroutputvoltageripple.Connectingthispintoground rates current limiting, short-circuit protection, and soft-
selects pulse skipping mode, which provides the lowest starting.
output ripple, at the cost of low current efficiency.
Efficiency Considerations
The LTC3407-4 can also be synchronized to an external
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
2.25MHz clock signal (such as the SW pin on another
LTC3407-4) by the MODE/SYNC pin. During synchroniza-
tion, the mode is set to pulse skipping and the top switch
turn-on is synchronized to the rising edge of the external
clock.
Hot Swap is registered trademark of Linear Technology Corporation.
34074f
10
LTC3407-4
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APPLICATIO S I FOR ATIO
produce the most improvement. Percent efficiency can be
expressed as:
include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that CIN has adequate
charge storage and very low ESR at the switching fre-
quency. Other losses including diode conduction losses
during dead-time and inductor core losses generally ac-
count for less than 2% total additional loss.
%Efficiency = 100% - (L1 + L2 + L3 + ...)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC3407-4 circuits: 1)VIN quiescent current, 2)
switching losses, 3) I2R losses, 4) other losses.
Thermal Considerations
In a majority of applications, the LTC3407-4 does not
dissipate much heat due to its high efficiency. However, in
applications where the LTC3407-4 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will turn off and the SW node will
become high impedance.
1) The VIN current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET driver
andcontrolcurrents.VIN currentresultsinasmall(<0.1%)
loss that increases with VIN, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
fromswitchingthegatecapacitanceofthepowerMOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from VIN to
ground. The resulting dQ/dt is a current out of VIN that is
typically much larger than the DC bias current. In continu-
ousmode, IGATECHG =fO(QT +QB), whereQT andQB arethe
gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to VIN
and thus their effects will be more pronounced at higher
supply voltages.
3) I2R losses are calculated from the DC resistances of the
internal switches, RSW, and external inductor, RL. In
continuousmode,theaverageoutputcurrentflowsthrough
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
RDS(ON) and the duty cycle (DC) as follows:
To prevent the LTC3407-4 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
TRISE = PD • θJA
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
As an example, consider the case when the LTC3407-4 is
in dropout on both channels at an input voltage of 2.7V
with a load current of 800mA and an ambient temperature
of 70°C. From the Typical Performance Characteristics
graph of Switch Resistance, the RDS(ON) resistance of the
main switch is 0.425Ω. Therefore, power dissipated by
each channel is:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
PD = I2 • RDS(ON) = 272mW
4) Other ‘hidden’ losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
The MS package junction-to-ambient thermal resistance,
θJA, is 45°C/W. Therefore, the junction temperature of the
34074f
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LTC3407-4
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APPLICATIO S I FOR ATIO
Board Layout Considerations
regulator operating in a 70°C ambient temperature is
approximately:
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3407-4. These items are also illustrated graphically in
the layout diagram of Figure 3. Check the following in your
layout:
TJ = 2 • 0.272 • 45 + 70 = 94.5°C
which is below the absolute maximum junction tempera-
ture of 125°C.
Design Example
1. Does the capacitor CIN connect to the power VIN (Pin 3)
andGND(exposedpad)ascloseaspossible?Thiscapaci-
torprovidestheACcurrenttotheinternalpowerMOSFETs
and their drivers.
As a design example, consider using the LTC3407-4 in an
portable application with a Li-Ion battery. The battery
provides a VIN = 2.8V to 4.2V. The load requires a maxi-
mum of 800mA in active mode and 2mA in standby mode.
The output voltage is VOUT = 2.5V. Since the load still
needs power in standby, Burst Mode operation is selected
for good low load efficiency.
2. Are the COUT and L1 closely connected? The (–) plate of
COUT returns current to GND and the (–) plate of CIN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT and a ground sense line
terminatednearGND(exposedpad). Thefeedbacksignals
VFB should be routed away from noisy components and
traces, such as the SW line (Pins 4 and 7), and its trace
should be minimized.
First, calculate the inductor value for about 30% ripple
current at maximum VIN:
⎛
⎞
2.5V
2.25MHz • 300mA
2.5V
4.2V
L =
• 1–
= 1.5µH
⎜
⎟
⎝
⎠
4.KeepsensitivecomponentsawayfromtheSWpins.The
input capacitor CIN and the resistors R1 to R4 should be
routed away from the SW traces and the inductors.
Choosing a vendor’s closest inductor value of 2.2µH,
results in a maximum ripple current of:
5. Agroundplaneispreferred, butifnotavailable, keepthe
signal and power grounds segregated with small signal
components returning to the GND pin at one point and
2.5V
2.25MHz •2.2µH
2.5V
4.2V
⎛
⎝
⎞
∆IL =
• 1−
= 204mA
⎜
⎟
⎠
should not share the high current path of CIN or COUT
.
For cost reasons, a ceramic capacitor will be used. COUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. These copper areas should be con-
nected to VIN or GND.
800mA
COUT ≈ 2.5
= 7.1µF
2.25MHz •(5%•2.5V)
V
IN
C
IN
A good standard value is 10µF. Since the output imped-
ance of a Li-Ion battery is very low, CIN is typically 10µF.
RUN2
V
RUN1
POR
IN
MODE/SYNC
LTC3407-4
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2µA with the 0.6V feedback voltage makes R1~300k. A
close standard 1% resistor is 280k, and R2 is then 887k.
L1
C4
L2
V
OUT2
SW2
SW1
V
OUT1
C5
R4
V
FB1
V
FB2
R2
GND
R1
C
OUT1
C
R3
OUT2
ThePORpinisacommondrainoutputandrequiresapull-
up resistor. A 100k resistor is used for adequate speed.
3407 F03
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 1 shows the complete schematic for this design
example.
Figure 3. LTC3407-4 Layout Diagram (See Board Layout Checklist)
34074f
12
LTC3407-4
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TYPICAL APPLICATIO S
Low Ripple Buck Regulators Using Ceramic Capacitors
V
IN
Efficiency vs Load Current
2.5V TO 5.5V
R5
C1
100
95
90
85
80
75
70
65
60
55
50
100k
10µF
RUN2
V
RUN1
POR
IN
POWER-ON
RESET
V
= 1.8V
OUT
LTC3407-4
L2
L1
4.7µH
4.7µH
V
V
OUT1
OUT2
1.2V
1.8V
800mA
SW2
SW1
V
= 1.2V
OUT
800mA
C5, 22pF
C4, 22pF
V
V
FB1
FB2
R4
887k
R2
604k
MODE/SYNC GND
C3
10µF
C2
10µF
R3
442k
R1
604k
V
= 3.6V
IN
PULSE SKIP MODE
NO LOAD ON OTHER CHANNEL
3407 TA03
10
100
1000
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML
L1, L2: SUMIDA CDRH2D18/HP-4R7NC
LOAD CURRENT (mA)
34074 TA03b
1mm Height Core Supply
V
IN
Efficiency vs Load Current
3.6V TO 5.5V
R5
100k
C1*
10µF
100
95
RUN2
V
RUN1
IN
POWER-ON
RESET
V
= 3.3V
MODE/SYNC
POR
OUT
90
LTC3407-4
L2
2.2µH
L1
2.2µH
85
V
V
OUT1
OUT2
80
75
V
OUT
= 1.8V
1.8V
3.3V
800mA
SW2
SW1
800mA
C5, 100pF
C4, 22pF
70
65
60
55
50
V
V
FB1
FB2
R4
887k
R2
604k
GND
C2
C3
10µF
R3
196k
R1
301k
V
= 5V
IN
10µF
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
3407 TA07
1
10
100
1000
C1, C2, C3: TAIYO YUDEN JMK212BJ106MD-B
L1, L2: COILTRONICS LPO3310-222MX
LOAD CURRENT (mA)
34074 TA08
*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,
ADDITIONAL CAPACITANCE MAY BE REQUIRED.
34074f
13
LTC3407-4
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
6
0.38 ± 0.10
10
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PACKAGE
OUTLINE
(DD10) DFN 1103
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50
BSC
2.38 ±0.10
(2 SIDES)
2.38 ±0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
34074f
14
LTC3407-4
U
PACKAGE DESCRIPTIO
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1664)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 ± 0.102
(.081 ± .004)
1.83 ± 0.102
(.072 ± .004)
2.794 ± 0.102
(.110 ± .004)
0.889 ± 0.127
(.035 ± .005)
1
5.23
(.206)
MIN
2.083 ± 0.102 3.20 – 3.45
(.082 ± .004) (.126 – .136)
10
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
REF
10 9
8
7 6
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
1
2
3
4 5
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
MSOP (MSE) 0603
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
34074f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC3407-4
U
TYPICAL APPLICATIO
2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator
V
IN
2.8V TO 4.2V
R5
100k
C1
10µF
RUN2
V
RUN1
POR
IN
POWER-ON
RESET
MODE/SYNC
L2
15µH
L1
2.2µH
LTC3407-4
D1
V
V
OUT2
3.3V AT 100mA
OUT1
1.8V AT 800mA
SW2
SW1
C5, 22pF
C4, 33pF
M1
+
C6
22µF
V
V
FB2
FB1
R4
887k
R2
604k
GND
C3
4.7µF
C2
10µF
R3
196k
R1
301k
34074 TA04
C1, C2: TAIYO YUDEN JMK316BJ106ML
C3: MURATA GRM21BR60J475KA11B
C6: KEMET C1206C226K9PAC
L1: MURATA LQH32CN2R2M33
L2: TOKO A914BYW-150M (D52LC SERIES)
M1: SILICONIX Si2302DS
D1: PHILIPS PMEG2010
Efficiency vs Load Current
Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
90
80
70
60
50
40
30
2.8V
4.2V
3.6V
2.8V
4.2V
3.6V
V
= 1.8V
V
= 3.3V
OUT
OUT
Burst Mode OPERATION
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
NO LOAD ON OTHER CHANNEL
1
10
100
1000
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
34074 TA06
34074 TA05
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PART NUMBER
DESCRIPTION
COMMENTS
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I
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SD
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OUT)
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88% Efficiency, V : 2.7V to 5.5V, V
Q SD
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OUT
IN
OUT(MIN)
Inductorless Step-Down DC/DC Converter
I = 60µA, I < 1µA, DFN-12 Package
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LTC3407/LTC3407-2
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300mA (I ), 1.5MHz,
96% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 20µA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
Synchronous Step-Down DC/DC Converters
I
<1µA, ThinSOT Package
SD
600mA (I ), 1.5MHz,
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 20µA,
Q
OUT
IN
Synchronous Step-Down DC/DC Converters
I
<1µA, ThinSOT Package
SD
600mA/800mA, 1.5MHz
Dual Synchronous Step-Down DC/DC Converter
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40µA,
Q
IN
I
<1µA, MSE, DFN Package
SD
1.25A (I ), 4MHz,
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60µA,
Q
OUT
IN
Synchronous Step Down DC/DC Converter
I
<1µA, MSOP-10 Package
SD
LTC3412
2.5A (I ), 4MHz,
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60µA,
Q
OUT
IN
Synchronous Step Down DC/DC Converter
I
<1µA, TSSOP-16E Package
SD
LTC3414
4A (I ), 4MHz,
95% Efficiency, V : 2.25V to 5.5V, V
SD
= 0.8V, I = 64µA,
OUT(MIN) Q
OUT
IN
Synchronous Step Down DC/DC Converter
I
<1µA, TSSOP-28E Package
LTC3440
600mA (I ), 2MHz,
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 2.5V, I = 25µA,
OUT(MIN) Q
OUT
IN
Synchronous Buck-Boost DC/DC Converter
I
<1µA, MSOP-10 Package
34074f
LT 0406 • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LTC3407-4 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
LTC3407A | Linear | Dual Synchronous 600mA, 1.5MHz Step-Down DC/DC Regulator | 获取价格 | |
LTC3407A | ADI | 双输出同步 600mA、1.5MHz 降压型 DC/DC 稳压器 | 获取价格 | |
LTC3407A-2 | Linear | Dual Synchronous 800mA,2.25MHz Step-Down DC/DC Regulator | 获取价格 | |
LTC3407A-2 | ADI | 双通道同步、800mA、2.25MHz降压型DC/DC稳压器 | 获取价格 | |
LTC3407AB | Linear | 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter | 获取价格 | |
LTC3407AEDD | Linear | 暂无描述 | 获取价格 | |
LTC3407AEDD#PBF | Linear | LTC3407A - Dual Synchronous 600mA, 1.5MHz Step-Down DC/DC Regulator; Package: DFN; Pins: 10; Temperature Range: -40&deg;C to 85&deg;C | 获取价格 | |
LTC3407AEDD#TR | Linear | IC 1.25 A DUAL SWITCHING CONTROLLER, 1800 kHz SWITCHING FREQ-MAX, PDSO10, 3 X 3 MM, PLASTIC, MO-229WEED-2, DFN-10, Switching Regulator or Controller | 获取价格 | |
LTC3407AEDD#TRPBF | Linear | LTC3407A - Dual Synchronous 600mA, 1.5MHz Step-Down DC/DC Regulator; Package: DFN; Pins: 10; Temperature Range: -40&deg;C to 85&deg;C | 获取价格 | |
LTC3407AEDD-2 | Linear | Dual Synchronous 800mA,2.25MHz Step-Down DC/DC Regulator | 获取价格 |
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