LTC3409AIDD [Linear]
600mA Low VIN Buck Regulator in 3mm × 3mm DFN; 600毫安低输入电压降压型稳压器采用3mm × 3mm DFN封装
| 型号： | LTC3409AIDD |
| 厂家： | 
Linear |
| 描述： | 600mA Low VIN Buck Regulator in 3mm × 3mm DFN |
| 文件： | 总16页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3409A
600mA Low V Buck
IN
Regulator in 3mm × 3mm DFN
FEATURES
DESCRIPTION
TheLTC®3409Aisahighefficiency,monolithicsynchronous
buck regulator using a constant frequency, current mode
architecture. TheLTC3409AimprovesupontheLTC3409’s
light load regulation in Burst Mode operation. The output
voltage is adjusted via an external resistor divider.
n
1.6V to 5.5V Input Voltage Range
n
0.62V to 5.5V Output Voltage Range
n
Internal Soft-Start
n
Selectable 1.7MHz or 2.6MHz Constant Frequency
Operation
n
Internal Oscillator Can Be Synchronized to an
Fixed switching frequencies of 1.7MHz and 2.6MHz are
supported. Alternatively, an internal PLL will synchronize
to an external clock in the frequency range of 1MHz to
3MHz. This range of switching frequencies allows the
use of small surface mount inductors and capacitors,
including ceramics.
External Clock, 1MHz to 3MHz Range
n
High Efficiency: Up to 95%
65μA Quiescent Current, Burst Mode® Operation
n
n
600mA Output Current (V = 1.8V, V
750mA Peak Inductor Current
No Schottky Diode Required
Low Dropout Operation: 100% Duty Cycle
0.612V Reference Voltage
Stable with Ceramic Capacitors
= 1.2V)
IN
OUT
n
n
n
n
n
n
n
Supply current during Burst Mode operation is only
65μA dropping to <1μA in shutdown. The 1.6V to 5.5V
input voltage range makes the LTC3409A ideally suited
for single cell Li-Ion, Li-Metal and 2-cell alkaline, NiCd
or NiMH battery-powered applications. 100% duty cycle
capability provides low dropout operation, extending bat-
tery life in portable systems. Burst Mode operation can be
user-enabled, increasing efficiency at light loads, further
extending battery life.
Shutdown Mode Draws <1μA Supply Current
Current Mode Operation for Excellent Line and Load
Transient Response
n
n
Overtemperature Protection
Available in a Low Profile (0.75mm)
8-Lead (3mm × 3mm) DFN Package
The internal synchronous switch increases efficiency and
eliminatestheneedforanexternalSchottkydiode.Internal
soft-startofferscontrolledoutputvoltagerisetimeatstart-
up without the need for external components.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.
APPLICATIONS
n
Cellular Phones
n
Digital Cameras
n
MP3 Players
TYPICAL APPLICATION
Burst Mode Efficiency, 1.8VOUT
High Efficiency Step-Down Converter
100
90
80
70
60
50
40
30
20
10
0
1
2.5V , BURST
IN
LTC3409A
SW
2.2μH*
V
V
0.1
IN
1.8V TO 5.5V
OUT
1.8V
V
IN
10pF
4.7μF
22μF
s2
RUN
3.6V , BURST
IN
267k
137k
MODE
V
FB
0.01
0.001
0.0001
4.2V , BURST
IN
SYNC GND
POWER LOST
3.6V , BURST
IN
*SUMIDA CDRH2D18/LD
3409A TA01
0
1
10
100
1000
LOAD CURRENT (mA)
3409A TA01b
3409af
1
LTC3409A
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Input Supply Voltage................................... –0.3V to 6V
RUN, V , MODE, SYNC Voltages . –0.3V to (V + 0.3V)
FB
IN
V
1
2
3
4
8
7
6
5
SYNC
RUN
SW
FB
SW Voltage ................................... –0.3V to (V + 0.3V)
IN
GND
9
Operating Temperature Range (Note 2) ..–40°C to 85°C
Junction Temperature (Note 3) ........................... 125°C
Storage Temperature Range.................. –65°C to 125°C
V
IN
V
MODE
IN
DD PACKAGE
8-LEAD (3mm s 3mm) PLASTIC DFN
T
= 125°C, θ = 43°C/W
JMAX
JA
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3409AEDD#PBF
LTC3409AIDD#PBF
TAPE AND REEL
PART MARKING*
LFGY
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3409AEDD#TRPBF
LTC3409AIDD#TRPBF
–40°C to 85°C
–40°C to 85°C
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
LFGY
Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 2.2V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
Input Voltage Range
Regulated Feedback Voltage
1.6
5.5
V
IN
V
(Note 4) T = 25°C
0.604
0.600
0.598
0.612
0.612
0.612
0.620
0.624
0.626
V
V
V
FB
A
(Note 4) 0°C ≤ T ≤ 85°C
A
(Note 4) –40°C ≤ T ≤ 85°C
A
I
Feedback Current
V
= 0.612V
30
85
nA
VFB
FB
35
61
mV
ΔV
ΔV
ΔV
FBOVL
Overvoltage Lockout
ΔV
= ΔV
– V (Note 6)
OVL
FB
OVL
FBOVL FB
l
Reference Voltage Line Regulation 1.6V < V < 5.5V (Note 4)
0.04
0.05
0.4
0.5
%/V
%
IN
IN
1.9V ≤ V ≤ 3.6V, 0°C ≤ T ≤ 85°C (Note 4)
A
I
Peak Inductor Current
V
= 0.5V or V
= 90%
0.75
1
1.3
0.5
A
PK
FB
OUT
V
Output Voltage Load Regulation
V
OUT
= 1.8V, V
= 0V, 1mA < I < 210mA,
LOAD
0.2
%
LOADREG
MODE
0°C ≤ T ≤ 85°C (Note 8)
A
l
l
V
RUN Threshold
0.3
0.3
0.65
0.01
0.65
0.01
1.1
1
V
μA
V
RUN
RUN
I
RUN Leakage Current
MODE Threshold
V
= 0V or = 2.2V
RUN
V
1.1
1
MODE
MODE
I
MODE Leakage Current
V
MODE
= 0V or = 2.2V
μA
3409af
2
LTC3409A
The ● denotes specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are TA = 25°C. VIN = 2.2V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
0.65
0.01
MAX
1.1
1
UNITS
V
l
V
SYNC Threshold
SYNC Leakage Current
0.3
SYNCTH
SYNC
S
I
V
SYNC
= 0V or = 2.2V
μA
I
f
Input DC Bias Current
Active Mode
Sleep Mode
Shutdown
(Note 5)
V
V
V
= 90%, I
= 0A
LOAD
350
65
0.1
475
120
1
μA
μA
μA
OUT
OUT
RUN
LOAD
= 103%, I
= 0A
= 0V, V = 5.5V
IN
l
l
Nominal Oscillator Frequency
SYNC = GND
SYNC = V
0.9
1.8
1.7
2.6
2.2
3.2
MHz
MHz
OSC
IN
SYNC TH
SYNC Threshold
When SYNC Input is Toggling (Note 7)
0.63
1
V
MHz
MHz
ns
SYNC f
SYNC f
Minimum SYNC Pin Frequency
Maximum SYNC Pin Frequency
Minimum SYNC Pulse Width
Soft-Start Period
MIN
3
MAX
SYNC PW
100
1
t
ms
RUN↑
SS
SYNC t
SYNC Timeout
Delay from Removal of EXT CLK Until Fixed
Frequency Operation Begins (Note 7)
30
μs
O
R
R
R
R
of P-channel FET
of N-channel FET
I
I
= 100mA, Wafer Level
= 100mA, DD Package
0.33
0.35
Ω
Ω
PFET
NFET
LSW
DS(ON)
SW
SW
I
SW
I
SW
= 100mA, Wafer Level
= 100mA, DD Package
0.22
0.25
Ω
Ω
DS(ON)
I
SW Leakage
V
= 0V, V = 0V or 5V, V = 5V
0.1
3
μA
RUN
SW
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3409AE is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3409AI is guaranteed to meet
specified performance over the full –40°C to 85°C operating temperature
range.
This IC includes overtemperature protection that is intended to protect the
device during momentary overload conditions. Overtemperature protection
becomes active at a junction temperature greater than the maximum
operating junction temperature. Continuous operation above the specified
maximum operating junction temperature may impair device reliability.
Note 4: The LTC3409A is tested in a proprietary test mode that connects
V
to the output of the error amplifier.
FB
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: ΔV
is the amount V must exceed the regulated feedback
FB
OVL
Note 3: T is calculated from the ambient temperature T and power
J
A
voltage.
dissipation P according to the following formula:
D
Note 7: Determined by design, not production tested.
Note 8: Guaranteed by measurement at the wafer level and design,
LTC3409A: T = T + (P )(43°C/W)
J
A
D
characterization and correlation with statistical process controls.
3409af
3
LTC3409A
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C, from Typical Application on the front page except for the resistive divider resistor values)
Pulse-Skipping Efficiency/Power
Lost vs Load Current, VOUT = 1.8V
Efficiency vs Input Voltage,
VOUT = 1.2V, Burst Mode Operation
100
90
80
70
60
50
40
30
20
10
0
1
100
90
80
70
60
50
40
30
20
10
0
EFFICIENCY
V
= 3.6V
IN
V
= 4.2V
IN
0.1
V
= 2.5V
IN
V
= 4.2V
IN
0.01
0.001
V
= 3.6V
IN
V
= 2.5V
IN
I
I
I
= 0.1mA
= 1mA
= 10mA
I
I
= 100mA
= 600mA
OUT
OUT
OUT
OUT
OUT
POWER LOST
0
1
10
100
1000
1.6
2.6
3.6
4.6
5.5
LOAD CURRENT (mA)
INPUT VOLTAGE (V
)
IN
3409A G01
3409A G02
Efficiency vs Load Current,
VOUT = 1.2V
Efficiency vs Input Voltage
VOUT = 1.2V, Pulse-Skipping
Efficiency vs Load Current,
VOUT = 2.5V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
I
= 100mA
OUT
1.6V
IN
2.5V
2.7V
IN
IN
I
= 600mA
OUT
4.2V
IN
3.1V
IN
3.1V
IN
3.6V
IN
4.2V
3.6V
IN
I
= 10mA
= 1mA
OUT
2.5V
IN
1.6V
IN
I
OUT
OUT
2.7V
IN
IN
BURST
PULSE-SKIPPING
I
= 0.1mA
BURST
PULSE-SKIPPING
1
10
100
1000
1.5
2.5
INPUT VOLTAGE (V
3.5
4.5
)
5.5
0.1
1
10
LOAD CURRENT (mA)
100
1000
0.1
LOAD CURRENT (mA)
IN
3409A G03
3409A G04
3409A G05
Oscillator Frequency Shift
vs Input Voltage
Reference Voltage
vs Temperature
Oscillator Frequency
vs Temperature
0.616
0.615
0.614
0.613
0.612
0.611
0.610
0.609
0.608
6
4
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
V
= 2.7V
IN
f
LOW
1.7MHz
V
= 1.6V
IN
2
V
= 4.2V
IN
OSC 2.6MHz
0
f
HIGH
2.6MHz
–2
–4
–6
–8
–10
OSC 1.7MHz
V
= 4.2V
= 1.6V
25
IN
V
= 2.7V
IN
V
IN
50
1.5
3.5
INPUT VOLTAGE (V)
5.5
–50 –30 –10 10 30 50 70 90 110 125
–50 –25
0
75 100 125
2.5
4.5
TEMPERATURE (°C)
TEMPERATURE (°C)
3409A G06
3409A G08
3409A G07
3409af
4
LTC3409A
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C, from Typical Application on the front page except for the resistive divider resistor values)
Output Voltage
vs Load Current VIN = 1.6V
RDS(ON) vs Input Voltage
RDS(ON) vs Temperature
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
1.210
1.205
1.200
1.195
1.190
1.185
1.100
1.6V
IN
MAIN
1.2V , BURST
OUT
SWITCH
4.2V
IN
1.2V , PULSE-SKIPPING
OUT
2.7V
IN
1.6V
IN
2.7V
IN
SYNCHRONOUS
SWITCH
4.2V
IN
MAIN SWITCH
SYNCHRONOUS SWITCH
50
100 125
–50 –25
0
25
75
1
10
100
1000
1.5
5.5
2.5
3.5
4.5
LOAD CURRENT (mA)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3409A G09
3409A G11
3409A G10
Dynamic Supply Current
vs Temperature, VIN = 3.6V,
VOUT = 1.5V, No Load
Dynamic Input Current
vs Input Voltage
500
450
400
350
300
250
200
150
100
50
3500
3000
2500
2000
1500
1000
500
90
80
70
60
50
40
30
20
10
0
V
= 1.5V
= 0
OUT
I
OUT
BURST
PULSE-SKIPPING
V
= 1V
FB
V
= 1.5V
= 0
OUT
OUT
I
BURST
PULSE-SKIPPING
4.5
V
= 1V
2.5
FB
0
0
–50 –25
0
25
50
75 100 125
1.5
3.5
5.5
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3409A G13
3409A G12
Switch Leakage
vs Temperature VIN = 5.5V
Switch Leakage vs Input Voltage
6000
5000
4000
3000
45
40
35
30
25
20
15
10
5
MAIN SWITCH
MAIN SWITCH
2000
1000
0
SYNCHRONOUS SWITCH
SYNCHRONOUS
SWITCH
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
4
0
2
6
INPUT VOLTAGE (V)
3409A G14
3409A G15
3409af
5
LTC3409A
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C, from Typical Application on the front page except for the resistive divider resistor values)
Load Step 0mA to 600mA Pulse-
Skipping, VIN = 3.6V, VOUT = 1.8V
Start-Up from Shutdown, VIN = 3.6V,
VOUT = 1.8V, Load = 1kΩ
V
OUT
RUN
2V/DIV
100mV/DIV
V
I
OUT
LOAD
1V/DIV
500mA/DIV
INDUCTOR
CURRENT
200mA/DIV
INDUCTOR
CURRENT
500mA/DIV
3409A G16
3409A G17
200μs/DIV
20μs/DIV
Burst Mode Operation, ILOAD = 35mA,
VIN = 3.6V, VOUT = 1.8V
Load Step 50mA to 600mA Pulse-
Skipping, VIN = 3.6V, VOUT = 1.8V
V
V
OUT
20mV/DIV
OUT
50mV/DIV
I
V
LOAD
SWITCH
2V/DIV
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
3409A G18
3409A G19
20μs/DIV
4μs/DIV
Load Step 10mA to 600mA,
Burst Mode Operation, VIN = 3.6V,
VOUT = 1.8V
Load Step 50mA to 600mA,
Burst Mode Operation, VIN = 3.6V,
VOUT = 1.8V
V
OUT
V
OUT
50mV/DIV
100mV/DIV
I
LOAD
500mA/DIV
I
LOAD
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
3409A G20
3409A G21
20μs/DIV
20μs/DIV
3409af
6
LTC3409A
PIN FUNCTIONS
V
(Pin 1): Feedback Pin. Receives the feedback voltage
SYNC (Pin 8): External CLK Input/Fixed Switching Fre-
quency Selection. Forcing this pin above 1.1V for greater
than 30μs selects 2.6MHz switching frequency. Forcing
this pin below 0.3V for greater than 30μs selects 1.7MHz
switching frequency.
FB
from an external resistive divider across the output.
GND (Pin 2): Ground Pin.
V
(Pins 3, 4): Main Supply Pins. Must be closely de-
IN
coupled to GND, Pin 2 and Pin 9, with a 4.7μF or greater
External clock input, 1MHz to 3MHz frequency range.
When the SYNC pin is clocked in this frequency range
the SYNC threshold is nominally 0.63V. To allow for good
noise immunity, SYNC signal should swing at least 0.3V
below and above this nominal value (0.33V to 0.93V). Do
not leave SYNC floating.
ceramic capacitor.
MODE(Pin5):ModeSelectInput.Toselectpulse-skipping
mode, force this pin above 1.1V. Forcing this pin below
0.3V selects Burst Mode operation. Do not leave MODE
floating.
SW (Pin 6): Switch Node Connection to Inductor. This pin
connectstothedrainsoftheinternalmainandsynchronous
power MOSFET switches.
Exposed Pad (Pin 9): The Exposed Pad is ground. It must
besolderedtoPCBgroundtoprovidebothelectricalcontact
and optimum thermal performance.
RUN(Pin7):RunControlInput.Forcingthispinabove1.1V
enables the part. Forcing this pin below 0.3V shuts down
thedevice.Inshutdown,allfunctionsaredisableddrawing
<1μA supply current. Do not leave RUN floating.
FUNCTIONAL DIAGRAM
MODE
5
SLOPE
COMP
SYNC
0.65V
8
PLL
OSC
3, 4
V
IN
–
+
V
FB
EN
–
+
1
SLEEP
+
–
5Ω
0.612V
+
–
0.4V
I
COMP
EA
BURST
Q
S
SOFT-
START
R
Q
SWITCHING
LOGIC
AND
RS LATCH
V
ANTI-
SHOOT-
THRU
IN
BLANKING
CIRCUIT
SW
6
RUN
7
+
OV
REFERENCE
OVDET
0.675
–
+
–
SHUTDOWN
2, 9
I
RCMP
GND
3409A FD
3409af
7
LTC3409A
OPERATION
Main Control Loop
Burst Mode Operation
TheLTC3409Ausesaconstantfrequency,currentmodestep-
downarchitecture.Boththemain(P-channelMOSFET)and
synchronous (N-channel MOSFET) switches are internal.
During normal operation, the internal top power MOSFET
is turned on each cycle when the oscillator sets the RS
The LTC3409A is capable of Burst Mode operation in
which the internal power MOSFETs operate intermittently
based on load demand. To enable Burst Mode operation,
simply connect the MODE pin to GND. To disable Burst
Mode operation and enable PWM pulse-skipping mode,
latch, and turned off when the current comparator, I
,
connect the MODE pin to V or drive it with a logic high
COMP
IN
resets the RS latch. The peak inductor current at which
(V
>1.1V). In this mode, the efficiency is lower at
MODE
I
resetstheRSlatchiscontrolledbytheoutputoferror
lightloads,butbecomescomparabletoBurstModeopera-
tion when the output load exceeds 30mA. The advantage
of pulse-skipping mode is lower output ripple and less
interference to audio circuitry. When the converter is in
Burst Mode operation, the minimum peak current of the
inductor is set to approximately 200mA regardless of the
output load. Each burst event can last from a few cycles
at light loads to almost continuously cycling with short
sleep intervals at moderate loads. In between these burst
events, the power MOSFETs and any unneeded circuitry
are turned off, reducing the quiescent current to 65μA. In
this sleep state, the load current is being supplied solely
from the output capacitor. As the output voltage droops,
the EA amplifier’s output rises above the sleep threshold
signaling the BURST comparator to trip and turn the top
MOSFET on. This process repeats at a rate that is depen-
dent on the load demand.
COMP
amplifier EA. The V pin, described in the Pin Functions
FB
section, allows EA to receive an output feedback voltage
from an external resistive divider. When the load current
increases,itcausesaslightdecreaseinthefeedbackvoltage
relative to the 0.612V reference, which in turn, causes the
EA amplifier’s output voltage to increase until the average
inductor current matches the new load current. While the
top MOSFET is off, the bottom MOSFET is turned on until
either the inductor current starts to reverse, as indicated
bythecurrentreversalcomparatorI
of the next clock cycle.
,orthebeginning
RCMP
Comparator OVDET guards against transient overshoots
>10% by turning the main switch off and keeping it off
until the transient has ended.
3409af
8
LTC3409A
OPERATION
Burst Mode Operation Near Dropout
Slope Compensation
With a light load the part will transition from Burst Mode
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscil-
lations at high duty cycles. It is accomplished internally
by adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%.
operation to 100% duty cycle as (V to V ) approaches
IN
OUT
I
• (R
+ R
). When (V to V
INDUCTOR
)
LOAD
MAINSWITCH
IN
OUT
results in near 100% duty cycle the inductor up slope will
be quite shallow compared to the inductor down slope,
with low peak currents.
User Controlled Switching Frequency
The LTC3409A is a micropower part and the speed of the
comparatorcontrollingthesynchronousswitchmayallow
TheinternaloscillatoroftheLTC3409Acanbesynchronized
to a user-supplied external clock applied to the SYNC pin.
Alternately, when this pin is held at a fixed high or low
level for more than 30μs, the internal oscillator will revert
to fixed-frequency operation; where the frequency may
be selected as 1.7MHz (SYNC Low) or 2.6MHz (SYNC
High).
the inductor current to reverse in a low (V to V ) situa-
IN
OUT
tion,resultinginCCMoperation.TransitionfromCCMback
to Burst Mode operation will occur when (V to V ) is
IN
OUT
sufficient for the average inductor current to exceed the
load current. This occurs when the average positive cur-
rent in the inductor exceeds the average reverse current
caused by synchronous switch propagation delay. The
CCM to Burst Mode operation re-entry transition point will
Internal Soft-Start
be a function of V , V , I
, C
and the inductor
At start-up when the RUN pin is brought high, the internal
referenceislinearlyrampedfrom0Vto0.612Vin1ms.The
regulated feedback voltage will follow this ramp resulting
in the output voltage ramping from 0% to 100% in 1ms.
Thecurrentintheinductorduringsoft-startwillbedefined
by the combination of the current needed to charge the
output capacitance and the current provided to the load
as the output voltage ramps up. The start-up waveform,
shown in the Typical Performance Characteristics, shows
the output voltage start-up from 0V to 1.8V with a 1kΩ
IN OUT LOAD OUT
used in the application.
Short-Circuit Protection
WhentheoutputisshortedtogroundtheLTC3409Alimits
the synchronous switch current to 1.5A. If this limit is
exceeded, the top power MOSFET is inhibited from turn-
ing on until the current in the synchronous switch falls
below 1.5A.
Dropout Operation
load and V = 3.6V. The 1kΩ load results in an output of
IN
1.8mA at 1.8V.
As the input supply voltage decreases to a value ap-
proaching the output voltage, the duty cycle increases
toward the maximum on-time. Further reduction of the
supply voltage forces the main switch to remain on for
more than one cycle until it reaches 100% duty cycle.
The output voltage will then be determined by the input
voltage minus the voltage drop across the P-channel
MOSFET and the inductor.
3409af
9
LTC3409A
APPLICATIONS INFORMATION
Table 1. Representative Surface Mount Inductors
The basic LTC3409A application circuit is shown on the
first page of this data sheet. External component selec-
tion is driven by the load requirement and begins with the
MAX DC
PART NUMBER & VALUE MAX DCR CURRENT
SIZE
3
MANUFACTURER
(μH)
(mΩ)
(A)
W × L × H (mm )
selection of L followed by C and C
.
IN
OUT
Sumida
CDRH2D18/HP
1.7
44
1.85
3.2 × 3.2 × 2.0
Inductor Selection
Sumida
CDRH2D18/LD
2.2
3.3
41
54
0.85
0.75
3.2 × 3.2 × 2.0
3.2 × 3.2 × 1.2
2.5 × 3.2 × 2.0
2.6 × 2.8 × 1.0
2.6 × 2.8 × 1.2
2.8 × 2.8 × 1.1
2.8 × 2.8 × 1.35
For most applications, the value of the inductor will fall
in the range of 1μH to 10μH. Its value is chosen based
on the desired ripple current. Large value inductors
lower ripple current and small value inductors result in
Sumida
CDRH2D11
1.5
2.2
68
98
0.90
0.78
Murata
LQH32C_33
1.0
2.2
60
97
1.00
0.79
higher ripple currents. Higher V or V
also increases
TDK
VLF3010AT
1.5
2.2
78
120
1.20
1.00
IN
OUT
the ripple current as shown in Equation 1. A reasonable
TDK
VLF3012AT
1.5
2.2
68
100
1.20
1.00
starting point for setting ripple current is ΔI = 240mA
(40% of 600mA).
L
Wurth WE-TPC
T/TH 74402800
1.0
2.2
85
155
1.50
1.00
⎛
⎞
VOUT
VIN
1
f •L
ΔIL =
VOUT 1–
(1)
Wurth 74402900
2.2
3.3
110
135
1.15
0.95
⎜
⎝
⎟
⎠
The DC current rating of the inductor should be at least
equal to the maximum load current plus half the ripple
current to prevent core saturation. Thus, a 720mA rated
inductorshouldbeenoughformostapplications(600mA+
120mA). For better efficiency, choose a low DC resistance
inductor. The inductor value also has an effect on Burst
Modeoperation.Thetransitiontolowcurrentoperationbe-
gins when the inductor current peaks fall to approximately
C and C
Selection
IN
OUT
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle V /V . To prevent large
voltage transients, a low ESR input capacitor sized for the
maximumRMScurrentmustbeused.ThemaximumRMS
capacitor current is given by:
OUT IN
1/2
⎡
⎤
OUT
VOUT V – V
(
)
IN
⎣
⎦
200mA. Lower inductor values (higher ΔI ) will cause this
L
CIN RequiredIRMS ≅IOUT(MAX)
VIN
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
This formula has a maximum at V = 2V , where
IN
OUT
I
=I /2.Thissimpleworst-caseconditioniscommon-
RMS OUT
ly used for design because even significant deviations do
notoffermuchrelief.Notethatthecapacitormanufacturer’s
ripple current ratings are often based on 2000 hours of
life. This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Always consult the manufacturer if there is any
Inductor Core Selection
Different core materials and shapes will change the
size/current and price/current relationship of an induc-
tor. Toroid or shielded pot cores in ferrite or permalloy
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar electrical characteristics. The choice of which
style inductor to use often depends more on the price vs
sizerequirementsandanyradiatedfield/EMIrequirements
than on what the LTC3409A requires to operate. Table 1
shows some typical surface mount inductors that work
well in LTC3409A applications.
question. The selection of C
effective series resistance (ESR). Typically, once the ESR
requirement for C
rating generally far exceeds the I
is driven by the required
OUT
has been met, the RMS current
OUT
requirement.
RIPPLE(P-P)
3409af
10
LTC3409A
APPLICATIONS INFORMATION
Output Voltage Programming
The output ripple ΔV
is determined by:
OUT
The output voltage is set by a resistive divider according
to Equation 2:
⎛
⎞
1
ΔVOUT = ΔIL ESR+
⎜
⎝
⎟
8 • f •COUT
⎠
R1
R2
⎛
⎝
⎞
(2)
VOUT = 0.612V 1+
where f = operating frequency, C
= output capacitance
⎜
⎟
⎠
OUT
and ΔI = ripple current in the inductor. For a fixed output
L
voltage, the output ripple is highest at maximum input
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 1.
voltage since ΔI increases with input voltage. Aluminum
L
electrolytic and dry tantalum capacitors are both available
in surface mount configurations. In the case of tantalum,
it is critical that the capacitors are surge tested for use
in switching power supplies. An excellent choice is the
AVX TPS series of surface mount tantalum. These are
specially constructed and tested for low ESR so they give
the lowest ESR for a given volume. Other capacitor types
include Sanyo POSCAP, Kemet T510 and T495 series, and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
V
OUT
R1
V
FB
R2
LTC3409A
GND
3409A F01
Figure 1
Efficiency Considerations
Using Ceramic Input and Output Capacitors
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Higher value, lower cost ceramic capacitors are now avail-
able in smaller case sizes. Their high ripple current, high
voltage rating and low ESR make them ideal for switching
regulator applications. Because the LTC3409A’s control
loop does not depend on the output capacitor’s ESR for
stableoperation,ceramiccapacitorscanbeusedtoachieve
very low output ripple and small circuit size.
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
However, care must be taken when these capacitors are
usedattheinputandtheoutput.Whenaceramiccapacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC3409A circuits: V quiescent current
IN
2
and I R losses. The V quiescent current loss dominates
IN
induce ringing at the input, V . At best, this ringing can
IN
the efficiency loss at very low load currents whereas the
couple to the output and be mistaken as loop instability. At
2
I R loss dominates the efficiency loss at medium to high
worst, a sudden inrush of current through the long wires
load currents. In a typical efficiency plot, the efficiency
curve at very low load currents can be misleading since
the actual power lost is of no consequence as illustrated
in Figure 2.
can potentially cause a voltage spike at V , large enough
IN
to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
3409af
11
LTC3409A
APPLICATIONS INFORMATION
1.0000
Other losses including C and C
ESR dissipative
OUT
IN
V
= 1.8V
OUT
losses, and inductor core losses, generally account for
less than 2% total additional loss.
0.1000
0.0100
0.0010
0.0001
4.2V
IN
3.6V
Thermal Considerations
IN
2.5V
IN
In most applications the LTC3409A does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3409A is running at high ambient tem-
perature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
2.5V
IN
4.2V
IN
BURST
PULSE SKIP
3.6V
IN
0.1
1
10
100 1000
LOAD CURRENT (mA)
3409A F02
Figure 2. Power Loss
1. The V quiescent current is due to two components:
IN
To avoid the LTC3409A from exceeding the maximum
junction temperature, the user will need to do a thermal
analysis. The goal of the thermal analysis is to determine
whether the operating conditions exceed the maximum
junction temperature of the part. The temperature rise is
given by:
the DC bias current as given in the Electrical Charac-
teristics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate
is switched from high to low to high again, a packet
of charge, dQ, moves from V to ground. The result-
IN
T = (P )(θ )
R
D
JA
ing dQ/dt is the current out of V that is typically
IN
where P is the power dissipated by the regulator and θ
D
JA
larger than the DC bias current. In continuous mode,
is the thermal resistance from the junction of the die to
I
= f(Q + Q ) where Q and Q are the gate
GATECHG
T B T B
the ambient temperature.
charges of the internal top and bottom switches. Both
the DC bias and gate charge losses are proportional to
The junction temperature, T , is given by:
J
V and thus their effects will be more pronounced at
IN
T = T + T
R
J
A
higher supply voltages.
where T is the ambient temperature.
2
A
2. I R losses are calculated from the resistances of the
internal switches, R , and external inductor R . In
As an example, consider the LTC3409A in dropout at an
input voltage of 1.6V, a load current of 600mA and an
ambient temperature of 75°C. From the typical perfor-
SW
L
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
mance graph of switch resistance, the R
of the
DS(ON)
P-channel switch at 75°C is approximately 0.48Ω. There-
fore, power dissipated by the part is:
top and bottom MOSFET R
(DC) as follows:
and the duty cycle
DS(ON)
2
P = I
• R
= 172.8mW
D
LOAD
DS(ON)
R
= (R )(DC) + (R
DS(ON)TOP
)(1 – DC)
DS(ON)BOT
SW
FortheDD8package, theθ is43°C/W. Thus, thejunction
JA
TheR
forboththetopandbottomMOSFETscanbe
temperature of the regulator is:
DS(ON)
obtainedfromtheTypicalPerformanceCharacteristics.
T = 75°C + (0.1728)(43) = 82.4°C
J
2
Thus, to obtain I R losses, simply add R to R and
SW
L
which is well below the maximum junction temperature
of 125°C.
multiply the result by the square of the average output
current.
3409af
12
LTC3409A
APPLICATIONS INFORMATION
Notethatathighersupplyvoltages,thejunctiontemperature
2. Are the C
and L1 closely connected? The (–) plate of
OUT
is lower due to reduced switch resistance (R
).
C
returns current to GND and the (–) plate of C .
DS(ON)
OUT IN
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C and a ground sense line
Checking Transient Response
OUT
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
terminated near GND (Exposed Pad). The feedback
signals V should be routed away from noisy compo-
FB
nents and traces, such as the SW line (Pins 6), and its
a load step occurs, V
immediately shifts by an amount
trace should be minimized.
OUT
equal to (ΔI
• ESR), where ESR is the effective series
LOAD
4. TheSWtraceshouldbekeptassmallaspossible. Keep
sensitivecomponentsawayfromtheSWpins.Theinput
resistance of C . ΔI
also begins to charge or dis-
OUT
LOAD
charge C , which generates a feedback error signal. The
OUT
capacitor C and the resistors R1 and R2 should be
IN
regulator loop then acts to return V
value. During this recovery time V
to its steady state
can be monitored
OUT
OUT
routed away from the SW traces and the inductors.
for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point. They should not share the high current path of
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in paral-
C or C
.
IN
OUT
6. Floodallunusedareasonalllayerswithcopper.Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately
to V or GND (preferably).
IN
V
IN
(25 • C
). Thus, a 10μF capacitor charging to 3.3V
LOAD
would require a 250μs rise time, limiting the charging
current to about 130mA.
C
IN
V
V
IN
IN
LTC3409A
Board Layout Considerations
RUN SYNC
V
MODE
SW
FB
L1
C1
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3409A. These items are also illustrated graphically
in the layout diagram of Figure 3. Check the following in
your layout.
V
OUT
SGND GND
C
OUT
R1
R2
1. Does the capacitor C connect to the power V
3409A F03
IN
IN
(Pins 3, 4) and GND (Exposed Pad) as close as pos-
sible? This capacitor provides the AC current to the
internal power MOSFETs and their drivers.
Figure 3
3409af
13
LTC3409A
APPLICATIONS INFORMATION
Design Example
For best efficiency choose a 750mA or greater inductor
with less than 0.3Ω series resistance. C will require
IN
As a design example, assume the LTC3409A is used in a
an RMS current rating of at least 0.3A ≅ I
temperature.
/2 at
LOAD(MAX)
2-alkalinecellbattery-poweredapplication. TheV willbe
IN
operating from a maximum of 3.2V down to about 1.8V.
The load current requirement is a maximum of 600mA
but most of the time it will be in standby mode, requiring
only 2mA. Efficiency at both low and high load currents is
important, so the minimum frequency setting of 1.7MHz
is chosen. Output voltage is 1.5V. With this information
we can calculate L using Equation 3:
For the feedback resistors, choose R2 = 137k. R1 is then
calculated to be 200k from Equation 2. Figure 4 shows the
complete circuit along with its efficiency curve.
Table 2 below gives 1% resistor values for selected output
voltages.
V
R1
R2
OUT
⎛
⎞
VOUT
VIN
1
0.85V
1.2V
1.5V
1.8V
53.6k
137k
200k
267k
137k
143k
137k
137k
L =
VOUT 1–
(3)
⎜
⎝
⎟
f • ΔIL
⎠
Substituting V
= 1.5V, V = 3.2V, ΔI = 240mA and
IN L
OUT
f = 1.7MHz in Equation 2 gives:
1
1.5V
3.2V
⎛
⎝
⎞
L =
1.5V 1–
≅2.2µH
⎜
⎟
⎠
1.7MHz •240mA
Burst Mode Efficiency, 1.5VOUT
100
90
80
70
60
50
40
30
20
10
0
V
IN
1.8V
IN
1.8V TO 3.2V
R2
137k
C
IN
LTC3409A
SYNC
RUN
3.2V
IN
4.7μF
V
FB
L1
2.2μH
GND
V
OUT
2.5V
IN
1.5V
V
V
SW
IN
IN
0.6A
C
OUT
MODE
22μF
3409A F04
s2
R1
200k
L1: SUMIDA CDRH2D18/LD
C1
0.1
1
10
100
1000
10pF
LOAD CURRENT (mA)
3409A F04b
Figure 4
3409af
14
LTC3409A
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 0.05
3.5 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50
BSC
2.38 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
0.38 0.10
TYP
5
8
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD) DFN 1203
4
1
0.25 0.05
0.75 0.05
0.200 REF
0.50 BSC
2.38 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
3409af
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3409A
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
95% Efficiency, V : 1.6V to 5.5V, V
LTC3409
LTC3549
LTC3417A-2
LTC3410
LTC1878
LTC1879
LT3020
600mA (I ) Low V Step-Down DC/DC Converter
= 0.61V, I = 65μA,
Q
OUT
IN
IN
OUT(MIN)
OUT(MIN)
I
< 1μA, 8-Lead DFN Package
SD
250mA Low V Step-Down DC/DC Converter
93% Efficiency, V : 1.6V to 5.5V, V
= 0.61V, I = 50μA,
Q
IN
IN
I
< 1μA, 6-Lead DFN Package
SD
Dual 1.5A/1A 4MHz Step-Down DC/DC Regulator
95% Efficiency, Low Ripple, V : 2.25V to 5.5V, V
= 0.8V,
IN
OUT(MIN)
DFN and TSSOP Packages
300mA, 2.25MHz, Synchronous Step-Down Regulator in SC-70 96% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 26μA
Q
IN
OUT(MIN)
600mA (I ), 550kHz, Synchronous Step-Down
96% Efficiency, V : 2.7V to 6V, V
= 0.8V, I = 10μA,
OUT
IN
OUT(MIN) Q
DC/DC Converter
I
<1μA, MS8 Package
SD
1.20A (I ), 550kHz, Synchronous Step-Down
95% Efficiency, V : 2.7V to 10V, V
= 0.8V, I = 15μA,
OUT
IN
OUT(MIN) Q
DC/DC Converter
I
<1μA, 16-Lead TSSOP
SD
100mA, Low Voltage VLDO™
V : 0.9V to 10V, V
= 0.20V, Dropout Voltage = 0.15V,
= ADJ, DFN/MS8 Packages
IN
OUT(MIN)
I = 120μA, I <3μA, V
Q
SD
OUT
LTC3025
LTC3404
LTC3405A
100mA, Low Voltage VLDO
V : 0.9V to 5.5V, V
= 0.40V, Dropout Voltage = 0.05V,
IN
OUT(MIN)
I = 54μA, I <1μA, V = ADJ, DFN Package
OUT
Q
SD
600mA (I ), 1.4MHz, Synchronous Step-Down
96% Efficiency, V : 2.7V to 6V, V
= 0.8V, I = 10μA,
OUT(MIN) Q
OUT
IN
DC/DC Converter
I
<1μA, MS8 Package
SD
300mA (I ), 1.5MHz, Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 20μA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
DC/DC Converter
I
<1μA, ThinSOT™ Package
SD
LTC3406A/
LTC3406AB
600mA (I ), 1.5MHz, Synchronous Step-Down
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 20μA,
Q
OUT
IN
DC/DC Converter
I
<1μA, ThinSOT Package
SD
LTC3407A/
LTC3407A-2
Dual, 600mA/800mA (I ), 1.5MHz/2.25MHz,
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40μA,
Q
OUT
IN
Synchronous Step-Down DC/DC Converter
I
<1μA, 10-Lead MSE Package
SD
LTC3411A
1.25A (I ), 4MHz, Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60μA,
Q
OUT
IN
DC/DC Converter
I
<1μA, 10-Lead MS Package
SD
VLDO and ThinSOT are trademarks of Linear Technology Corporation.
3409af
LT 0509 • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明