LTC3409EDD#PBF [Linear]
LTC3409 - 600mA Low VIN Buck Regulator in 3mm x 3mm DFN; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LTC3409EDD#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3409 - 600mA Low VIN Buck Regulator in 3mm x 3mm DFN; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总16页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3409
600mA Low V Buck
IN
Regulator in 3mm × 3mm DFN
FEATURES
DESCRIPTION
TheLTC®3409isahighefficiency,monolithicsynchronous
buck regulator using a constant frequency, current mode
architecture. The output voltage is adjusted via an external
resistor divider.
■
1.6V to 5.5V Input Voltage Range
■
Internal Soft-Start
■
Selectable 1.7MHz or 2.6MHz Constant Frequency
Operation
■
Internal Oscillator can be Synchronizable to an
Fixed switching frequencies of 1.7MHz and 2.6MHz are
supported. Alternatively, an internal PLL will synchronize
to an external clock in the frequency range of 1MHz to
3MHz. This range of switching frequencies allows the
use of small surface mount inductors and capacitors,
including ceramics.
External Clock, 1MHz to 3MHz Range
■
High Efficiency: Up to 95%
■
Very Low Quiescent Current: Only 65μA During
Burst Mode® Operation
■
600mA Output Current (V = 1.8V, V
750mA Peak Inductor Current
No Schottky Diode Required
Low Dropout Operation: 100% Duty Cycle
0.613V Reference Voltage
Stable with Ceramic Capacitors
Shutdown Mode Draws <1μA Supply Current
Current Mode Operation for Excellent Line and Load
Transient Response
= 1.2V)
OUT
IN
■
■
■
■
■
■
■
Supply current during Burst Mode operation is only
65μA dropping to <1μA in shutdown. The 1.6V to 5.5V
input voltage range makes the LTC3409 ideally suited
for single cell Li-Ion, Li-Metal and 2-cell alkaline, NiCd
or NiMH battery-powered applications. 100% duty cycle
capability provides low dropout operation, extending bat-
tery life in portable systems. Burst Mode operation can be
user-enabled, increasing efficiency at light loads, further
extending battery life.
■
■
Overtemperature Protection
Available in a Low Profile (0.75mm) 8-Lead
(3mm × 3mm) DFN Package
The internal synchronous switch increases efficiency and
eliminatestheneedforanexternalSchottkydiode.Internal
soft-startofferscontrolledoutputvoltagerisetimeatstart-
up without the need for external components.
, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815,
6498466, 6611131.
APPLICATIONS
■
Cellular Phones
■
Digital Cameras
■
MP3 Players
Burst Mode Efficiency, 1.8VOUT
TYPICAL APPLICATION
100
90
80
70
60
50
40
30
20
10
0
1.0
2.5V , BURST
IN
High Efficiency Step-Down Converter
0.1
4.2V , BURST
IN
3.6V , BURST
IN
LTC3409
SW
2.2μH*
10pF
V
V
OUT
1.8V
IN
1.8V TO 5.5V
V
IN
0.01
0.001
0.0001
4.7μF
CER
10μF
CER
RUN
MODE
V
FB
POWER LOST
3.6V , BURST
255k
IN
133k
SYNC GND
*SUMIDA CDRH2D18/LD
3409 TA01
0.1
1
10
100
1000
3409 TA01b
LOAD CURRENT (mA)
3409fc
1
LTC3409
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Input Supply Voltage................................... –0.3V to 6V
RUN, V , MODE, SYNC Voltages . –0.3V to (V + 0.3V)
V
1
2
3
4
8
7
6
5
SYNC
RUN
SW
FB
FB
IN
GND
SW Voltage ................................... –0.3V to (V + 0.3V)
IN
9
V
IN
Operating Temperature Range (Note 2) .. –40°C to 85°C
Junction Temperature (Note 3) ........................... 125°C
Storage Temperature Range.................. –65°C to 125°C
V
MODE
IN
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
T
JMAX
= 125°C, θ = 43°C/W
JA
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3409EDD#PBF
LTC3409IDD#PBF
TAPE AND REEL
PART MARKING*
LBNM
PACKAGE DESCRIPTION
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
TEMPERATURE RANGE
–40°C to 85°C
–40°C to 85°C
LTC3409EDD#TRPBF
LTC3409IDD#TRPBF
LBNM
Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 2.2V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
0.65
0.01
0.65
0.01
0.65
0.01
MAX
1.1
1
UNITS
V
●
●
●
V
RUN Threshold
0.3
RUN
RUN
I
RUN Leakage Current
MODE Threshold
V
V
V
= 0V or = 2.2V
μA
V
RUN
V
0.3
0.3
1.1
1
MODE
MODE
I
MODE Leakage Current
SYNC Threshold
= 0V or = 2.2V
= 0V or = 2.2V
μA
V
MODE
V
1.1
1
SYNCTH
SYNC
I
SYNC Leakage Current
Regulated Feedback Voltage
μA
SYNC
V
FB
(Note 4) T = 25°C
0.6007
0.5992
0.5977
0.6130
0.6130
0.6130
0.6252
0.6268
0.6283
V
V
V
A
(Note 4) 0°C ≤ T ≤ 85°C
A
●
●
(Note 4) –40°C ≤ T ≤ 85°C
A
I
Feedback Current
30
85
nA
mV
%/V
%/V
A
VFB
ΔV
ΔV
ΔV
ΔV
Overvoltage Lockout
ΔV
OVL
= ΔV
– V (Note 6)
35
61
0.04
0.04
1
OVL
FB
FBOVL
FBOVL
FB
Reference Voltage Line Regulation 1.6V < V < 5.5V (Note 4)
0.4
0.4
1.3
IN
Output Voltage Line Regulation
Peak Inductor Current
I = 100mA, 1.6V < V < 5.5V
OUT IN
OUT
I
V
FB
= 0.5V or V = 90%
OUT
0.75
1.6
PK
V
V
Output Voltage Load Regulation
Input Voltage Range
V
OUT
= 1.2V, Pulse Skip Mode, 0 < I < 600mA
LOAD
0.5
%
LOADREG
IN
●
5.5
V
3409fc
2
LTC3409
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 2.2V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
S
Input DC Bias Current
Active Mode
(Note 5)
V
V
V
= 90%, I
= 0A
LOAD
350
65
0.1
475
120
1
μA
μA
μA
OUT
OUT
RUN
LOAD
Sleep Mode
= 103%, I
= 0V, V = 5.5V
= 0A
Shutdown
IN
●
●
f
Nominal Oscillator Frequency
SYNC = GND
SYNC = V
0.9
1.8
1.7
2.6
2.1
3.0
MHz
MHz
OSC
IN
SYNC TH
SYNC Threshold
When SYNC Input is Toggling (Note 7)
0.63
1
V
MHz
MHz
ns
SYNC f
SYNC f
Minimum SYNC Pin Frequency
Maximum SYNC Pin Frequency
Minimum SYNC Pulse Width
Soft-Start Period
MIN
3
MAX
SYNC PW
100
1
t
SS
RUN↑
ms
SYNC t
SYNC Timeout
Delay from Removal of EXT CLK Until Fixed
Frequency Operation Begins (Note 7)
30
μs
O
R
R
R
R
of P-Channel FET
of N-Channel FET
I
I
= 100mA, Wafer Level
= 100mA, DD Package
0.33
0.35
Ω
Ω
PFET
NFET
LSW
DS(ON)
SW
SW
I
SW
I
SW
= 100mA, Wafer Level
= 100mA, DD Package
0.22
0.25
Ω
Ω
DS(ON)
I
SW Leakage
V
= 0V, V = 0V or 5V, V = 5V
0.1
3
μA
RUN
SW
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3409E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3409I is guaranteed to meet
specified performance over the full –40°C to 85°C operating temperature
range.
This IC includes overtemperature protection that is intended to protect the
device during momentary overload conditions. Overtemperature protection
becomes active at a junction temperature greater than the maximum
operating junction temperature. Continuous operation above the specified
maximum operating junction temperature may impair device reliability.
Note 4: The LTC3409 is tested in a proprietary test mode that connects V
FB
to the output of the error amplifier.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: ΔV
is the amount V must exceed the regulated feedback
FB
OVL
Note 3: T is calculated from the ambient temperature T and power
J
A
voltage.
dissipation P according to the following formula:
D
Note 7: Determined by design, not production tested.
LTC3409: T = T + (P )(43°C/W)
J
A
D
3409fc
3
LTC3409
TYPICAL PERFORMANCE CHARACTERISTICS
(From Typical Application on the front page except for the resistive divider resistor values)
Efficiency/Power Lost
vs Load Current, VOUT = 1.8V
Efficiency vs Input Voltage
VOUT = 1.2V, Burst Mode Operation
Efficiency vs Input Voltage
VOUT = 1.2V, Pulse Skip
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
1.0
100
90
80
70
60
50
40
30
20
10
0
1
2
I
= 600mA
OUT
0.1
I
= 800mA
OUT
5
4
6
3
I
= 100mA
OUT
8
0.01
0.001
0.0001
I
= 10mA
OUT
10
7
I
= 1mA
12
OUT
11
9
I
I
I
= 0.1mA
= 1mA
I
I
I
= 100mA
= 600mA
= 800mA
OUT
OUT
OUT
OUT
OUT
OUT
I
= 0.1mA
OUT
= 10mA
0.1
1
10
100
1000
1.5
3.5
INPUT VOLTAGE (V)
4.5
2.5
5.5
1.5
3.5
INPUT VOLTAGE (V)
4.5
2.5
5.5
3409 G01
LOAD CURRENT (mA)
3409 G02
3409 G03
1: 2.5V , BURST
7: POWER LOST, 2.5V , BURST
IN
IN
2: 3.6V , BURST
8: POWER LOST, 2.5V , PULSE SKIP
IN
IN
3: 4.2V , BURST
9: POWER LOST, 3.6V , BURST
IN
IN
4: 2.5V , PULSE SKIP 10: POWER LOST, 3.6V , PULSE SKIP
IN
IN
IN
IN
5: 3.6V , PULSE SKIP 11: POWER LOST, 4.2V , BURST
IN
6: 4.2V , PULSE SKIP 12: POWER LOST, 4.2V , PULSE SKIP
IN
Efficiency vs Load Current
VOUT = 2.5V
Efficiency vs Load Current
VOUT = 1.2V
Reference Voltage
vs Temperature
100
90
80
70
60
50
40
30
20
10
0
0.618
0.617
0.616
0.615
0.614
0.613
0.612
0.611
0.610
0.609
0.608
100
90
80
70
60
50
40
30
20
10
0
BURST
BURST
1.6V
IN
2.7V
IN
2.5V
IN
4.2V
IN
3.1V
2.5V
3.6V
IN
IN
3.1V
IN
3.6V
IN
IN
4.2V
2.7V
IN
IN
1.6V
PULSE SKIP
IN
PULSE SKIP
–50 –30 –10 10 30 50 70 90 110 130 150
0.1
1
10
100
1000
0.1
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
TEMPERATURE (°C)
3409 G05
3409 G04
3409 G06
3409fc
4
LTC3409
TYPICAL PERFORMANCE CHARACTERISTICS
(From Typical Application on the front page except for the resistive divider resistor values)
Oscillator Frequency
vs Temperature
Oscillator Frequency Shift
vs Input Voltage
Output Voltage vs Load Current
VIN = 1.6V
6
4
1.22
1.21
1.20
1.19
2.70
2.60
2.50
2.40
2.30
2.20
2.10
2.00
1.90
1.80
1.70
1.60
1.50
1.40
1.30
1.20
V
= 2.7V
IN
f
LOW
1.7MHz
V
= 1.6V
IN
2
V
= 4.2V
IN
1.2V
OUT
OSC 2.6MHz
0
BURST
f
HIGH
2.6MHz
–2
–4
–6
–8
–10
OSC 1.7MHz
1.2V
PULSE
SKIP
OUT
V
= 4.2V
= 1.6V
25
IN
V
= 2.7V
IN
V
IN
1.18
3.5
50
1.5
2.5
4.5
5.5
–50 –25
0
75 100 125
0
100 200 300 400 500 600 700 800 900
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3409 G08
3409 G07
3409 G09
Dynamic Input Current
vs Input Voltage
RDS(ON) vs Input Voltage
RDS(ON) vs Input Temperature
6000
5000
4000
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
80
70
60
50
40
30
20
10
0
BURST/SLEEP
MAIN SWITCH
1.6V
V
= 1.5V
OUT
OUT
I
= 0
MAIN
SWITCH
V
= V
FB
IN
4.2V
2.7V
1.6V
3000
2000
V
= 1.5V
OUT
2.7V
4.2V
SYNCHRONOUS
SWITCH
I
= 0
OUT
PULSE
1000
0
SKIP
V
4
= 0
4.5
FB
SYNCHRONOUS SWITCH
1.5
2
2.5
3
3.5
5
5.5
6
1.5
5.5
–50
25
50
75
100 125
2.5
3.5
4.5
–25
0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3409 G12
3409 G10
3409 G11
Dynamic Supply Current vs
Temperature, VIN = 3.6V,
VOUT = 1.5V, 0 Load
Switch Leakage vs Temperature
VIN = 5.5V
Switch Leakage vs Input Voltage
500
450
400
350
300
250
200
150
100
50
6000
5000
4000
3000
45
V
IN
= 5.5V
40
35
30
25
20
15
10
5
PULSE SKIP
MAIN SWITCH
MAIN SWITCH
2000
1000
0
SYNCHRONOUS SWITCH
BURST
SYNCHRONOUS
SWITCH
0
0
–50
0
25
50
75 100 125
–25
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
0
4
8
2
6
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3409 G13
3409 G14
3409 G15
3409fc
5
LTC3409
TYPICAL PERFORMANCE CHARACTERISTICS
(From Typical Application on the front page except for the resistive divider resistor values)
Load Step 0mA to 600mA
Pulse Skip
Start-Up from Shutdown
RUN
2V/DIV
V
OUT
100mV/DIV
V
OUT
1V/DIV
I
LOAD
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
3409 G16
3409 G17
200μs/DIV
20μs/DIV
Burst Mode Operation
ILOAD = 35mA
Load Step 50mA to 600mA
Pulse Skip
V
OUT
V
OUT
20mV/DIV
100mV/DIV
V
SWITCH
2V/DIV
I
LOAD
500mA/DIV
INDUCTOR
CURRENT
200mA/DIV
INDUCTOR
CURRENT
500mA/DIV
3409 G19
3409 G18
2μs/DIV
20μs/DIV
Load Step 0mA to 600mA
Burst Mode Operation
Load Step 50mA to 600mA
Burst Mode Operation
V
OUT
V
OUT
100mV/DIV
100mV/DIV
I
I
LOAD
LOAD
500mA/DIV
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
INDUCTOR
CURRENT
500mA/DIV
3409 G20
3409 G21
20μs/DIV
20μs/DIV
3409fc
6
LTC3409
PIN FUNCTIONS
SYNC (Pin 8): External CLK Input/Fixed Switching Fre-
quency Selection. Forcing this pin above 1.1V for greater
than 30μs selects 2.6MHz switching frequency. Forcing
this pin below 0.3V for greater than 30μs selects 1.7MHz
switching frequency.
V
(Pin 1): Feedback Pin. Receives the feedback voltage
FB
from an external resistive divider across the output.
GND (Pin 2): Ground Pin.
V
(Pins 3, 4): Main Supply Pins. Must be closely de-
IN
coupled to GND, Pin 2 and Pin 9, with a 4.7μF or greater
External clock input, 1MHz to 3MHz frequency range.
When the SYNC pin is clocked in this frequency range
the SYNC threshold is nominally 0.63V. To allow for good
noise immunity, SYNC signal should swing at least 0.3V
below and above this nominal value (0.33V to 0.93V). Do
not leave SYNC floating.
ceramic capacitor.
MODE(Pin5):ModeSelectInput. Toselectpulseskipping
mode, force this pin above 1.1V. Forcing this pin below
0.3V selects Burst Mode operation. Do not leave MODE
floating.
SW (Pin 6): Switch Node Connection to Inductor. This pin
connectstothedrainsoftheinternalmainandsynchronous
power MOSFET switches.
Exposed Pad (Pin 9): The Exposed Pad is ground. It must
besolderedtoPCBgroundtoprovidebothelectricalcontact
and optimum thermal performance.
RUN(Pin7):RunControlInput.Forcingthispinabove1.1V
enables the part. Forcing this pin below 0.3V shuts down
thedevice.Inshutdown,allfunctionsaredisableddrawing
<1μA supply current. Do not leave RUN floating.
3409fc
7
LTC3409
FUNCTIONAL DIAGRAM
MODE
5
SLOPE
COMP
SYNC
0.65V
8
PLL
OSC
V
IN
–
+
3, 4
V
FB
EN
–
+
1
SLEEP
+
–
5Ω
0.613V
+
–
0.4V
I
COMP
EA
BURST
Q
Q
S
SOFT-
START
R
SWITCHING
LOGIC
AND
RS LATCH
V
ANTI-
SHOOT-
THRU
IN
BLANKING
CIRCUIT
SW
6
RUN
7
+
OV
REFERENCE
OVDET
0.675
–
+
–
SHUTDOWN
I
RCMP
2
GND
3409 FD
OPERATION
Main Control Loop
bythecurrentreversalcomparatorI
of the next clock cycle.
,orthebeginning
RCMP
TheLTC3409usesaconstantfrequency,currentmodestep-
downarchitecture.Boththemain(P-channelMOSFET)and
synchronous (N-channel MOSFET) switches are internal.
During normal operation, the internal top power MOSFET
is turned on each cycle when the oscillator sets the RS
latch, and turned off when the current comparator, I
resets the RS latch. The peak inductor current at which
Comparator OVDET guards against transient overshoots
>10% by turning the main switch off and keeping it off
until the transient has ended.
Burst Mode Operation
,
COMP
The LTC3409 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
connect the MODE pin to GND. To disable Burst Mode
operation and enable PWM pulse skipping mode, connect
I
resetstheRSlatchiscontrolledbytheoutputoferror
COMP
amplifier EA. The V pin, described in the Pin Functions
FB
section, allows EA to receive an output feedback voltage
from an external resistive divider. When the load current
increases,itcausesaslightdecreaseinthefeedbackvoltage
relative to the 0.613V reference, which in turn, causes the
EA amplifier’s output voltage to increase until the average
inductor current matches the new load current. While the
top MOSFET is off, the bottom MOSFET is turned on until
either the inductor current starts to reverse, as indicated
the MODE pin to V or drive it with a logic high (V
IN
MODE
>1.1V). In this mode, the efficiency is lower at light loads,
but becomes comparable to Burst Mode operation when
the output load exceeds 30mA. The advantage of pulse
skipping mode is lower output ripple and less interference
3409fc
8
LTC3409
OPERATION
to audio circuitry. When the converter is in Burst Mode
operation, the minimum peak current of the inductor is
settoapproximately200mAregardlessoftheoutputload.
Each burst event can last from a few cycles at light loads
to almost continuously cycling with short sleep intervals
at moderate loads. In between these burst events, the
power MOSFETs and any unneeded circuitry are turned
off, reducing the quiescent current to 65μA. In this sleep
state, the load current is being supplied solely from the
output capacitor. As the output voltage droops, the EA
amplifier’soutputrisesabovethesleepthresholdsignaling
the BURST comparator to trip and turn the top MOSFET
on. This process repeats at a rate that is dependent on
the load demand.
Slope Compensation
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscil-
lations at high duty cycles. It is accomplished internally
by adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%.
User Controlled Switching Frequency
TheinternaloscillatoroftheLTC3409canbesynchronized
to a user-supplied external clock applied to the SYNC pin.
Alternately, when this pin is held at a fixed High or Low
level for more than 30μs, the internal oscillator will revert
to fixed-frequency operation; where the frequency may
be selected as 1.7MHz (SYNC Low) or 2.6MHz (SYNC
High).
Short-Circuit Protection
When the output is shorted to ground the LTC3409 limits
the synchronous switch current to 1.5A. If this limit is
exceeded, the top power MOSFET is inhibited from turn-
ing on until the current in the synchronous switch falls
below 1.5A.
Internal Soft-Start
At start-up when the RUN pin is brought high, the internal
referenceislinearlyrampedfrom0Vto0.613Vin1ms.The
regulated feedback voltage will follow this ramp resulting
in the output voltage ramping from 0% to 100% in 1ms.
Thecurrentintheinductorduringsoft-startwillbedefined
by the combination of the current needed to charge the
output capacitance and the current provided to the load
as the output voltage ramps up. The start-up waveform,
shown in the Typical Performance Characteristics, shows
the output voltage start-up from 0V to 1.5V with a 2.5Ω
Dropout Operation
As the input supply voltage decreases to a value ap-
proaching the output voltage, the duty cycle increases
toward the maximum on-time. Further reduction of the
supply voltage forces the main switch to remain on for
more than one cycle.
load and V = 2.2V. The 2.5Ω load results in an output
IN
of 600mA at 1.5V.
3409fc
9
LTC3409
APPLICATIONS INFORMATION
Table 1. Representative Surface Mount Inductors
The basic LTC3409 application circuit is shown on the first
page of this data sheet. External component selection is
driven by the load requirement and begins with the selec-
PART
NUMBER
VALUE
(μH)
DCR
MAX DC
SIZE
3
(Ω MAX) CURRENT (A) W × L × H (mm )
Sumida
CDRH2D18/LD
2.2
3.3
0.041
0.054
0.85
0.75
3.2 × 3.2 × 2.0
3.2 × 3.2 × 1.2
4.4 × 5.8 × 1.2
2.5 × 3.2 × 2.0
2.5 × 3.2 × 2.0
4.5 × 5.4 × 1.2
tion of L followed by C and C
.
IN
OUT
Sumida
CDRH2D11
1.5
2.2
0.068
0.170
0.90
0.78
Inductor Selection
For most applications, the value of the inductor will fall
in the range of 1μH to 10μH. Its value is chosen based
on the desired ripple current. Large value inductors
lower ripple current and small value inductors result in
Sumida
CMD4D11
2.2
3.3
0.116
0.174
0.950
0.770
Murata
LQH32CN
1.0
2.2
0.060
0.097
1.00
0.79
Toko
D312F
2.2
3.3
0.060
0.260
1.08
0.92
higher ripple currents. Higher V or V
also increases
IN
OUT
the ripple current as shown in Equation 1. A reasonable
Panasonic
ELT5KT
3.3
4.7
0.17
0.20
1.00
0.95
starting point for setting ripple current is ΔI = 240mA
(40% of 600mA).
L
ꢁ
ꢃ
ꢂ
OUT ꢄ
VIN
ꢅ
V
1
f •L
C and C
Selection
IN
OUT
ꢀIL =
VOUT 1–
ꢆ
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle V /V . To prevent large
(1)
OUT IN
The DC current rating of the inductor should be at least
equal to the maximum load current plus half the ripple
current to prevent core saturation. Thus, a 720mA rated
inductorshouldbeenoughformostapplications(600mA+
120mA). For better efficiency, choose a low DC resistance
inductor. The inductor value also has an effect on Burst
Modeoperation.Thetransitiontolowcurrentoperationbe-
gins when the inductor current peaks fall to approximately
voltage transients, a low ESR input capacitor sized for the
maximumRMScurrentmustbeused.ThemaximumRMS
capacitor current is given by:
1/2
⎡
⎤
VOUT V – V
(
)
IN
OUT
⎣
⎦
CIN RequiredIRMS ꢀIOUT(MAX)
VIN
This formula has a maximum at V = 2V , where
IN
OUT
200mA. Lower inductor values (higher ΔI ) will cause this
L
I
=I /2.Thissimpleworst-caseconditioniscommon-
RMS OUT
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
ly used for design because even significant deviations do
notoffermuchrelief.Notethatthecapacitormanufacturer’s
ripple current ratings are often based on 2000 hours of
life. This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Always consult the manufacturer if there is any
Inductor Core Selection
Different core materials and shapes will change the
size/current and price/current relationship of an induc-
tor. Toroid or shielded pot cores in ferrite or permalloy
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar electrical characteristics. The choice of which
style inductor to use often depends more on the price vs
sizerequirementsandanyradiatedfield/EMIrequirements
than on what the LTC3409 requires to operate. Table 1
shows some typical surface mount inductors that work
well in LTC3409 applications.
question. The selection of C
is driven by the required
OUT
effective series resistance (ESR). Typically, once the ESR
requirement for C
has been met, the RMS current
OUT
rating generally far exceeds the I
requirement.
RIPPLE(P-P)
The output ripple DV
is determined by:
OUT
ꢁ
ꢄ
1
ꢀVOUT = ꢀIL ESR+
ꢃ
ꢆ
8 • f •C
ꢂ
OUT ꢅ
3409fc
10
LTC3409
APPLICATIONS INFORMATION
where f = operating frequency, C
= output capacitance
Output Voltage Programming
OUT
and ΔI = ripple current in the inductor. For a fixed output
L
The output voltage is set by a resistive divider according
to the following formula:
voltage, the output ripple is highest at maximum input
voltage since ΔI increases with input voltage. Aluminum
L
R1
R2
ꢀ
ꢁ
ꢃ
ꢄ
electrolytic and dry tantalum capacitors are both available
in surface mount configurations. In the case of tantalum,
it is critical that the capacitors are surge tested for use
in switching power supplies. An excellent choice is the
AVX TPS series of surface mount tantalum. These are
specially constructed and tested for low ESR so they give
the lowest ESR for a given volume. Other capacitor types
include Sanyo POSCAP, Kemet T510 and T495 series, and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
VOUT = 0.613V 1+
ꢂ
ꢅ
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 1.
V
OUT
R1
V
FB
R2
LTC3409
GND
3409 F01
Using Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now avail-
able in smaller case sizes. Their high ripple current, high
voltage rating and low ESR make them ideal for switching
regulatorapplications.BecausetheLTC3409’scontrolloop
does not depend on the output capacitor’s ESR for stable
operation, ceramic capacitors can be used to achieve very
low output ripple and small circuit size.
Figure 1
Efficiency Considerations
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
However, care must be taken when these capacitors are
usedattheinputandtheoutput.Whenaceramiccapacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
induce ringing at the input, V . At best, this ringing can
IN
couple to the output and be mistaken as loop instability. At
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
worst, a sudden inrush of current through the long wires
can potentially cause a voltage spike at V , large enough
IN
the losses in LTC3409 circuits: V quiescent current and
IN
to damage the part.
2
I R losses. The V quiescent current loss dominates
IN
the efficiency loss at very low load currents whereas the
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
2
I R loss dominates the efficiency loss at medium to high
load currents. In a typical efficiency plot, the efficiency
curve at very low load currents can be misleading since
the actual power lost is of no consequence as illustrated
in Figure 2.
3409fc
11
LTC3409
APPLICATIONS INFORMATION
1
OtherlossesincludingC andC ESRdissipativelosses
IN
OUT
BURST
PULSE SKIP
and inductor core losses generally account for less than
2% total additional loss.
0.1
Thermal Considerations
2.5V
IN
0.01
3.6V
IN
InmostapplicationstheLTC3409doesnotdissipatemuch
heatduetoitshighefficiency.But,inapplicationswherethe
LTC3409 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperatureofthepart.Ifthejunctiontemperaturereaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
4.2V
IN
0.001
4.2V
IN
3.6V
IN
2.5V
IN
0.0001
0.1
1
10
100
1000
LOAD CURRENT (mA)
3409 F02
Figure 2
1. The V quiescent current is due to two components:
To avoid the LTC3409 from exceeding the maximum
junction temperature, the user will need to do a thermal
analysis. The goal of the thermal analysis is to determine
whether the operating conditions exceed the maximum
junction temperature of the part. The temperature rise is
given by:
IN
the DC bias current as given in the Electrical Charac-
teristics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate
is switched from high to low to high again, a packet
T = (P )(θ )
R
D
JA
of charge, dQ, moves from V to ground. The result-
IN
where P is the power dissipated by the regulator and θ
ing dQ/dt is the current out of V that is typically
D
JA
IN
is the thermal resistance from the junction of the die to
larger than the DC bias current. In continuous mode,
the ambient temperature.
I
= f(Q + Q ) where Q and Q are the gate
GATECHG
T B T B
charges of the internal top and bottom switches. Both
The junction temperature, T , is given by:
J
the DC bias and gate charge losses are proportional to
T = T + T
R
J
A
V and thus their effects will be more pronounced at
IN
higher supply voltages.
where T is the ambient temperature.
A
2
2. I R losses are calculated from the resistances of the
As an example, consider the LTC3409 in dropout at an
input voltage of 1.6V, a load current of 600mA and an
ambient temperature of 75°C. From the typical perfor-
internal switches, R , and external inductor R . In
SW
L
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
mance graph of switch resistance, the R
of the
DS(ON)
P-channel switch at 75°C is approximately 0.48Ω. There-
fore, power dissipated by the part is:
top and bottom MOSFET R
(DC) as follows:
and the duty cycle
DS(ON)
2
P = I
• R
= 172.8mW
D
LOAD
DS(ON)
FortheDD8package, theθ is43°C/W. Thus, thejunction
JA
R
= (R )(DC) + (R
DS(ON)TOP
)(1 – DC)
DS(ON)BOT
SW
temperature of the regulator is:
TheR
forboththetopandbottomMOSFETscanbe
DS(ON)
T = 75°C + (0.1728)(43) = 82.4°C
J
obtainedfromtheTypicalPerformanceCharacteristics.
2
Thus, to obtain I R losses, simply add R to R and
which is well below the maximum junction temperature
of 125°C.
SW
L
multiply the result by the square of the average output
current.
3409fc
12
LTC3409
APPLICATIONS INFORMATION
Notethatathighersupplyvoltages,thejunctiontemperature
2. Are the C
and L1 closely connected? The (–) plate of
OUT
is lower due to reduced switch resistance (R
).
C
returns current to GND and the (–) plate of C .
DS(ON)
OUT IN
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C and a ground sense line
Checking Transient Response
OUT
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
terminated near GND (Exposed Pad). The feedback
signals V should be routed away from noisy compo-
FB
nents and traces, such as the SW line (Pins 6), and its
a load step occurs, V
immediately shifts by an amount
trace should be minimized.
OUT
equal to (ΔI
• ESR), where ESR is the effective series
LOAD
4. Keep sensitive components away from the SW pins.
resistance of C . ΔI
also begins to charge or dis-
OUT
LOAD
The input capacitor C and the resistors R1 and R2
IN
charge C , which generates a feedback error signal. The
OUT
should be routed away from the SW traces and the
regulator loop then acts to return V
value. During this recovery time V
to its steady state
can be monitored
OUT
OUT
inductors.
for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point. They should not share the high current path of
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in paral-
C or C
.
IN
OUT
6. Floodallunusedareasonalllayerswithcopper.Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately
to V or GND.
IN
V
IN
(25 • C
). Thus, a 10μF capacitor charging to 3.3V
LOAD
would require a 250μs rise time, limiting the charging
current to about 130mA.
C
IN
V
V
IN
IN
LTC3409
Board Layout Considerations
RUN SYNC
V
FB
MODE
SW
L1
C1
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3409. These items are also illustrated graphically
in the layout diagram of Figure 3. Check the following in
your layout.
V
OUT
SGND GND
C
OUT
R1
R2
1. Does the capacitor C connect to the power V
3409 F03
IN
IN
(Pins 3, 4) and GND (Exposed Pad) as close as pos-
sible? This capacitor provides the AC current to the
internal power MOSFETs and their drivers.
Figure 3
3409fc
13
LTC3409
APPLICATIONS INFORMATION
Design Example
For best efficiency choose a 750mA or greater inductor
with less than 0.3Ω series resistance. C will require
IN
As a design example, assume the LTC3409 is used in a
an RMS current rating of at least 0.3A ≅ I
temperature.
/2 at
LOAD(MAX)
2-alkalinecellbattery-poweredapplication. TheV willbe
IN
operating from a maximum of 3.2V down to about 1.8V.
The load current requirement is a maximum of 600mA
but most of the time it will be in standby mode, requiring
only 2mA. Efficiency at both low and high load currents
is important. Output voltage is 1.5V. With this information
we can calculate L using Equation 2:
For the feedback resistors, choose R2 = 133k. R1 can then
be calculated from Equation 2 at 191K. Figure 4 shows the
complete circuit along with its efficiency curve.
Table 2 below gives 1% resistor values for selected output
voltages.
ꢁ
ꢃ
ꢂ
OUT ꢄ
VIN
ꢅ
V
1
V
R1
R2
OUT
L =
VOUT 1–
ꢆ
f • ꢀIL
0.85V
1.2V
1.5V
1.8V
51.1k
127k
191k
255k
133k
133k
133k
133k
(2)
Substituting V
= 1.5V, V = 3.2V, ΔI = 240mA and
f = 1.7MHz in Equation 2 gives:
OUT
IN
L
⎛
⎜
⎝
⎞
⎟
⎟
1
1.5
3.2
⎜
L=
1.5 1–
ꢀ2.2μH
⎜
⎟
⎠
1.7MHz •240mA
Burst Mode Efficiency, 1.5VOUT
100
90
80
70
60
50
40
30
20
10
0
V
IN
1.8V
IN
1.6V TO 5.5V
R2
133k
C
IN
LTC3409
3.1V
IN
4.7μF
V
SYNC
RUN
FB
L1
2.2μH
2.5V
IN
GND
V
OUT
1.5V
V
V
SW
IN
IN
C
10μF
CER
0.6A
OUT
MODE
R1
191k
3409 F04
L1: SUMIDA CDRH2D18/LD
C1
10pF
0.1
1
10
100
1000
LOAD CURRENT (mA)
3409 F04b
Figure 4
3409fc
14
LTC3409
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 ±0.05
3.5 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
0.38 ± 0.10
TYP
5
8
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 1203
4
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
3409fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent
15
LTC3409
TYPICAL APPLICATION
2-Cell to 1.2V/600mA Regulator for High Efficiency and Low Profile
LTC3409
SW
2.2μH*
22pF
3, 4
7
6
1
V
V
OUT
1.2V
IN
1.8V TO 3V
V
IN
C
10μF
CER
C
4.7μF
CER
OUT
IN
RUN
5
MODE
SYNC
V
FB
287k
8
301k
GND SGND
9
2
C
OUT
: TDK C1608X5R0J475M
IN
C
: TDK C1608X5R0G106M
*SUMIDA CDRH2D09NP-2R2NC
3409 TA02a
Efficiency
Load Step
95
90
85
80
75
70
65
60
55
50
V
V
= 1.8V
V
IN
OUT
OUT
= 1.2V
100mV/DIV
AC-COUPLED
f = 1.7MHz
f = 2.6MHz
I
L
500mA/DIV
I
LOAD
500mA/DIV
3409 TA02c
V
V
LOAD
= 1.8V
20μs/DIV
IN
= 1.2V
OUT
I
= 200mA TO 600mA
0.01
0.001
OUTPUT CURRENT (mA)
0.0001
0.1
1
3409 TA02b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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<1μA, 10-Lead MSE Package
SD
LTC3411
1.25A (I ), 4MHz, Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
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OUT
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I
<1μA, 10-Lead MS Package
SD
VLDO and ThinSOT are trademarks of Linear Technology Corporation.
3409fc
LT 0309 REV C • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
© LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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