LTC3410-1.875 [Linear]
2.25MHz, 300mA Synchronous Step-Down Regulator in SC70; 2.25MHz的， 300毫安同步降压型稳压器， SC70
| 型号： | LTC3410-1.875 |
| 厂家： | 
Linear |
| 描述： | 2.25MHz, 300mA Synchronous Step-Down Regulator in SC70 |
| 文件： | 总16页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3410-1.875
2.25MHz, 300mA
Synchronous Step-Down
Regulator in SC70
U
DESCRIPTIO
FEATURES
■
High Efficiency: Up to 93%
The LTC®3410-1.875 is a high efficiency monolithic syn-
chronous buck regulator using a constant frequency,
current mode architecture. Supply current during opera-
tionisonly26µA, droppingto<1µAinshutdown. The2.5V
to 5.5V input voltage range makes the LTC3410-1.875
ideally suited for single Li-Ion battery-powered applica-
tions. 100% duty cycle provides low dropout operation,
extending battery life in portable systems.
■
Very Low Quiescent Current: Only 26µA
■
Low Output Voltage Ripple
■
300mA Output Current at VIN = 3V
■
380mA Minimum Peak Switch Current
2.5V to 5.5V Input Voltage Range
2.25MHz Constant Frequency Operation
No Schottky Diode Required
■
■
■
■
■
■
■
Stable with Ceramic Capacitors
Shutdown Mode Draws <1µA Supply Current
±2% Output Voltage Accuracy
Current Mode Operation for Excellent Line and
Load Transient Response
Overtemperature Protected
Available in Low Profile SC70 Package
Switching frequency is internally set at 2.25MHz, allowing
the use of small surface mount inductors and capacitors.
The LTC3410-1.875 is specifically designed to work well
with ceramic output capacitors, achieving very low output
voltage ripple and a small PCB footprint.
■
■
The internal synchronous switch increases efficiency and
eliminates the need for an external Schottky diode. The
LTC3410-1.875 is available in a tiny, low profile SC70
package.
U
APPLICATIO S
■
Cellular Telephones
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5481178, 5994885, 6127815, 6304066, 6498466, 6580258, 6611131.
■
Wireless and DSL Modems
■
Digital Cameras
■
MP3 Players
■
Portable Instruments
U
TYPICAL APPLICATIO
Efficiency and Power Loss vs
Output Current
1
100
90
80
70
60
50
40
30
20
10
0
2.7V
EFFICIENCY
V
4.7µH
IN
V
IN
V
OUT
2.7V
V
SW
4.2V
IN
1.875V
0.1
C
TO 5.5V
IN
C
OUT
LTC3410-1.875
4.7µF
3.6V
4.7µF
CER
RUN
3.6V
CER
V
OUT
0.01
0.001
0.0001
GND
2.7V
POWER LOSS
34101875 TA01
V
IN
4.2V
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
34101875 TA02
34101875f
1
LTC3410-1.875
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
Input Supply Voltage .................................. –0.3V to 6V
RUN, VOUT Voltages................................... –0.3V to VIN
SW Voltage (DC) ......................... –0.3V to (VIN + 0.3V)
P-Channel Switch Source Current (DC) ............. 500mA
N-Channel Switch Sink Current (DC) ................. 500mA
Peak SW Sink and Source Current .................... 630mA
Operating Temperature Range (Note 2) .. –40°C to 85°C
Junction Temperature (Notes 3, 5) ...................... 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
TOP VIEW
ORDER PART
NUMBER
RUN 1
GND 2
SW 3
6 V
OUT
5 GND
LTC3410ESC6-1.875
SC6 PART MARKING
LCFQ
4 V
IN
SC6 PACKAGE
6-LEAD PLASTIC SC70
TJMAX = 125°C, θJA = 250°C/ W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
IN
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
V
= 3.6V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
3.3
MAX
UNITS
µA
I
I
Output Voltage Feedback Current
Peak Inductor Current
●
6
VOUT
PK
V
= 3V, V
= 1.64V, Duty Cycle < 35%
380
500
mA
V
IN
OUT
V
Regulated Output Voltage
Output Voltage Line Regulation
Output Voltage Load Regulation
Input Voltage Range
●
●
1.837
1.875
0.04
0.5
1.913
0.4
OUT
∆V
V
= 2.5V to 5.5V
%/V
%
OUT
LOADREG
IN
IN
V
V
V
I
= 50mA to 250mA
LOAD
●
2.5
5.5
2.3
V
Undervoltage Lockout Threshold
V
V
Rising
Falling
2
1.94
V
V
UVLO
IN
IN
I
f
Input DC Bias Current
Burst Mode® Operation
Shutdown
(Note 4)
S
V
V
= 1.945V, I
= 0V
= 0A
LOAD
26
0.1
35
1
µA
µA
OUT
RUN
Oscillator Frequency
V
V
= 1.875V
= 0V
●
1.8
0.3
2.25
310
2.7
MHz
kHz
OSC
OUT
OUT
R
R
R
R
of P-Channel FET
of N-Channel FET
I
I
= 100mA
0.75
0.55
± 0.01
1
0.9
0.7
±1
1.5
±1
Ω
Ω
PFET
NFET
LSW
DS(ON)
SW
SW
= –100mA
DS(ON)
I
SW Leakage
V
= 0V, V = 0V or 5V, V = 5V
µA
V
RUN
SW
IN
V
RUN Threshold
RUN Leakage Current
●
●
RUN
RUN
I
± 0.01
µA
Burst Mode is a registered trademark of Linear Technology Corporation.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and
lifetime.
dissipation P according to the following formula:
D
LTC3410-1.875: T = T + (P )(250°C/W)
J
A
D
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 2: The LTC3410E-1.875 is guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 5: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: T is calculated from the ambient temperature T and power
J
A
34101875f
2
LTC3410-1.875
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(From Figure 1)
Efficiency vs Input Voltage
Efficiency vs Output Current
100
90
80
70
60
50
40
30
100
I
= 100mA
OUT
90
80
70
60
50
40
30
20
I
= 10mA
OUT
I
= 250mA
OUT
I
= 1mA
OUT
I
OUT
= 0.1mA
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
10
0
0.1
4.5
INPUT VOLTAGE (V)
5.5
2.5
3
3.5
4
5
1
10
100
1000
OUTPUT CURRENT (mA)
34101875 G02
34101875 G01
Output Voltage
vs Temperature
Oscillator Frequency
vs Temperature
1.911
1.899
1.887
1.875
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
V
= 3.6V
V
= 3.6V
IN
IN
1.863
1.851
1.839
1.8
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
125
50
75 100
TEMPERATURE (°C)
34101875 G03
34101875 G04
Oscillator Frequency
vs Supply Voltage
Output Voltage vs Load Current
1.900
1.895
1.890
1.885
1.880
1.875
1.870
1.865
1.860
1.855
1.850
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
0
100
200
300
400
2
6
3
4
5
LOAD CURRENT (mA)
SUPPLY VOLTAGE (V)
34101875 G06
34101875 G05
34101875f
3
LTC3410-1.875
TYPICAL PERFOR A CE CHARACTERISTICS
U W
(From Figure 1)
R
) vs Input Voltage
DS(ON
R
vs Temperature
DS(ON)
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.2
1.0
V
= 4.2V
IN
V
= 3.6V
IN
V
= 2.7V
IN
MAIN SWITCH
0.8
0.6
0.4
V
= 4.2V
IN
SYNCHRONOUS SWITCH
V
= 3.6V
IN
V
= 2.7V
IN
0.2
0
MAIN SWITCH
SYNCHRONOUS SWITCH
1
3
4
5
6
7
2
–50 –30 –10 10 30 50 70 90 110 130
INPUT VOLTAGE (V)
TEMPERATURE (°C)
34101875 G07
34101875 G08
Dynamic Supply Current
vs Temperature
Dynamic Supply Current vs V
IN
50
40
30
20
10
0
50
I
0A
LOAD =
40
30
20
10
0
1
2
3
4
5
6
–50 –25
0
25
50
75 100 125
V
(V)
TEMPERATURE (°C)
IN
34101875 G09
34101875 G10
Switch Leakage vs Temperature
Switch Leakage vs Input Voltage
110
100
90
80
70
60
50
40
30
20
10
0
600
550
500
450
400
350
300
250
200
150
V
= 5.5V
IN
RUN = 0V
SYNCHRONOUS
SWITCH
MAIN
SWITCH
MAIN
SWITCH
SYNCHRONOUS
SWITCH
100
50
0
0
2
3
4
5
6
–50
0
25
50
75 100 125
1
–25
INPUT VOLTAGE (V)
TEMPERATURE (°C)
34101875 G12
34101875 G11
34101875f
4
LTC3410-1.875
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TYPICAL PERFOR A CE CHARACTERISTICS
(From Figure 1)
Burst Mode Operation
Start-Up from Shutdown
SW
5V/DIV
RUN
2V/DIV
V
OUT
50mV/DIV
AC COUPLED
V
OUT
1V/DIV
I
L
I
L
100mA/DIV
200mA/DIV
2µs/DIV
200µs/DIV
34101875 G13
34101875 G14
V
LOAD
= 3.6V
IN
V
LOAD
= 3.6V
IN
I
= 10mA
I
= 300mA
Start-Up from Shutdown
Load Step
V
OUT
RUN
2V/DIV
100mV/DIV
AC-COUPLED
V
I
OUT
L
1V/DIV
200mA/DIV
I
LOAD
I
L
200mA/DIV
200mA/DIV
10µs/DIV
= 0mA TO 300mA
200µs/DIV
34101875 G16
34101875 G15
V
LOAD
= 3.6V
IN
V
LOAD
= 3.6V
IN
I
= 0A
I
Load Step
V
OUT
100mV/DIV
AC-COUPLED
I
L
200mA/DIV
I
LOAD
200mA/DIV
10µs/DIV
= 15mA TO 300mA
34101875 G17
V
LOAD
= 3.6V
IN
I
34101875f
5
LTC3410-1.875
U
U
U
PI FU CTIO S
RUN (Pin 1): Run Control Input. Forcing this pin above
1.5V enables the part. Forcing this pin below 0.3V shuts
down the device. In shutdown, all functions are disabled
drawing <1µA supply current. Do not leave RUN floating.
VIN (Pin 4): Main Supply Pin. Must be closely decoupled
to GND, Pin 2, with a 2.2µF or greater ceramic capacitor.
V
OUT (Pin 6): Output Voltage Feedback. An internal resis-
tive divider divides the output voltage down for compari-
son to the internal 0.8V reference voltage.
GND (Pins 2, 5): Ground Pin.
SW (Pin 3): Switch Node Connection to Inductor. This pin
connects to the drains of the internal main and synchro-
nous power MOSFET switches.
U
U
W
FU CTIO AL DIAGRA
SLOPE
COMP
0.65V
OSC
OSC
V
4
IN
FREQ
–
+
SHIFT
V
OUT
EN
6
–
+
SLEEP
R1
5Ω
+
–
+
–
322.5k
0.8V
0.4V
I
COMP
V
EA
BURST
FB
R2
240k
Q
Q
S
R
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
RS LATCH
V
IN
ANTI-
SHOOT-
THRU
RUN
1
SW
3
0.8V REF
+
–
SHUTDOWN
5
2
I
RCMP
GND
34101875 BD
34101875f
6
LTC3410-1.875
U
OPERATIO
(Refer to Functional Diagram)
Main Control Loop
Short-Circuit Protection
The LTC3410-1.875 uses a constant frequency, current Whentheoutputisshortedtoground,thefrequencyofthe
mode step-down architecture. Both the main (P-channel oscillator is reduced to about 310kHz, 1/7 the nominal
MOSFET)andsynchronous(N-channelMOSFET)switches frequency. This frequency foldback ensures that the in-
are internal. During normal operation, the internal top ductorcurrenthasmoretimetodecay,therebypreventing
power MOSFET is turned on each cycle when the oscillator runaway. The oscillator’s frequency will progressively
sets the RS latch, and turned off when the current com- increase to 2.25MHz when VOUT rises above 0V.
parator, ICOMP, resets the RS latch. The peak inductor
Slope Compensation and Inductor Peak Current
current at which ICOMP resets the RS latch, is controlled by
the output of error amplifier EA. The VOUT pin, described in
the Pin Functions section, allows EA to receive an output
feedback voltage from the internal resistive divider. When
the load current increases, it causes a slight decrease in
the feedback voltage relative to the 0.8V reference, which
in turn, causes the EA amplifier’s output voltage to in-
crease until the average inductor current matches the new
load current. While the top MOSFET is off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by the current reversal
comparatorIRCMP,orthebeginningofthenextclockcycle.
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. Normally, this
results in a reduction of maximum inductor peak current
for duty cycles >40%. However, the LTC3410-1.875 uses
a patented scheme that counteracts this compensating
ramp, which allows the maximum inductor peak current
to remain unaffected throughout all duty cycles.
Burst Mode Operation
The LTC3410-1.875 is capable of Burst Mode operation in
which the internal power MOSFETs operate intermittently
based on load demand.
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 70mA re-
gardless of the output load. Each burst event can last from
a few cycles at light loads to almost continuously cycling
with short sleep intervals at moderate loads. In between
theseburstevents,thepowerMOSFETsandanyunneeded
circuitry are turned off, reducing the quiescent current to
26µA. In this sleep state, the load current is being supplied
solely from the output capacitor. As the output voltage
droops, the EA amplifier’s output rises above the sleep
thresholdsignalingtheBURSTcomparatortotripandturn
the top MOSFET on. This process repeats at a rate that is
dependent on the load demand.
34101875f
7
LTC3410-1.875
W U U
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APPLICATIO S I FOR ATIO
The basic LTC3410-1.875 application circuit is shown in
Figure 1. External component selection is driven by the
load requirement and begins with the selection of L fol-
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Tor-
oid or shielded pot cores in ferrite or permalloy materials
are small and do not radiate much energy, but generally
cost more than powdered iron core inductors with similar
electrical characteristics. The choice of which style induc-
tor to use often depends more on the price vs size require-
ments and any radiated field/EMI requirements than on
what the LTC3410-1.875 requires to operate. Table 1
shows some typical surface mount inductors that work
well in LTC3410-1.875 applications.
lowed by CIN and COUT
.
4.7µH
V
IN
V
OUT
1.875V
2.7V
V
SW
IN
C
TO 5.5V
IN
C
OUT
LTC3410-1.875
RUN
4.7µF
4.7µF
CER
CER
V
OUT
GND
34101875 F01
Figure 1. High Efficiency Step-Down Converter
Table 1. Representative Surface Mount Inductors
MAX DC
MANUFACTURER PART NUMBER
VALUE CURRENT DCR HEIGHT
Inductor Selection
Taiyo Yuden
CB2016T2R2M
CB2012T2R2M
LBC2016T3R3M
2.2µH 510mA 0.13Ω 1.6mm
2.2µH 530mA 0.33Ω 1.25mm
3.3µH 410mA 0.27Ω 1.6mm
For most applications, the value of the inductor will fall in
the range of 2.2µH to 4.7µH. Its value is chosen based on
the desired ripple current. Large value inductors lower
ripple current and small value inductors result in higher
ripple currents. Higher VIN or VOUT also increases the ripple
current as shown in equation 1. A reasonable starting point
for setting ripple current is ∆IL = 120mA (40% of 300mA).
Panasonic
Sumida
ELT5KT4R7M
CDRH2D18/LD
4.7µH 950mA 0.2Ω 1.2mm
4.7µH 630mA 0.086Ω 2mm
Murata
LQH32CN4R7M23 4.7µH 450mA 0.2Ω 2mm
Taiyo Yuden
NR30102R2M
NR30104R7M
2.2µH 1100mA 0.1Ω 1mm
4.7µH 750mA 0.19Ω 1mm
FDK
FDKMIPF2520D
FDKMIPF2520D
FDKMIPF2520D
4.7µH 1100mA 0.11Ω 1mm
3.3µH 1200mA 0.1Ω 1mm
2.2µH 1300mA 0.08Ω 1mm
⎛
⎝
⎞
VOUT
1
∆IL =
VOUT 1−
(1)
⎜
⎟
⎠
f L
( )( )
V
IN
The DC current rating of the inductor should be at least
equal to the maximum load current plus half the ripple
current to prevent core saturation. Thus, a 360mA rated
inductor should be enough for most applications (300mA
+ 60mA). For better efficiency, choose a low DC-resistance
inductor.
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
100mA. Lower inductor values (higher ∆IL) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
34101875f
8
LTC3410-1.875
W U U
APPLICATIO S I FOR ATIO
U
CIN and COUT Selection
Using Ceramic Input and Output Capacitors
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle VOUT/VIN. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
forswitchingregulatorapplications.BecausetheLTC3410-
1.875’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
1/2
V
V − V
OUT
(
)
]
[
OUT IN
CIN requiredIRMS ≅IOMAX
V
IN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is com-
monlyusedfordesignbecauseevensignificantdeviations
do not offer much relief. Note that the capacitor
manufacturer’s ripple current ratings are often based on
2000hoursoflife.Thismakesitadvisabletofurtherderate
the capacitor, or choose a capacitor rated at a higher
temperature than required. Always consult the manufac-
turer if there is any question.
However, care must be taken when ceramic capacitors are
usedattheinputandtheoutput.Whenaceramiccapacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, VIN. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, a sudden inrush of current through the long wires
can potentially cause a voltage spike at VIN, large enough
to damage the part.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment for COUT has been met, the RMS current rating
generally far exceeds the IRIPPLE(P-P) requirement. The
output ripple ∆VOUT is determined by:
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
The recommended capacitance value to use is 4.7µF for
both the input and output capacitors.
⎛
1
⎞
∆VOUT ≅ ∆I ESR +
⎜
⎟
⎠
L
⎝
8fCOUT
where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. For a fixed output
voltage, the output ripple is highest at maximum input
voltage since ∆IL increases with input voltage.
If tantalum capacitors are used, it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surface mount tantalum. These are specially constructed
and tested for low ESR so they give the lowest ESR for a
given volume. Other capacitor types include Sanyo
POSCAP, KemetT510andT495series, andSprague593D
and 595D series. Consult the manufacturer for other
specific recommendations.
34101875f
9
LTC3410-1.875
W U U
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APPLICATIO S I FOR ATIO
switched from high to low to high again, a packet of
charge, dQ, moves from VIN to ground. The resulting
dQ/dtisthecurrentoutofVIN thatistypicallylargerthan
the DC bias current. In continuous mode,
IGATECHG = f(QT + QB) where QT and QB are the
gate charges of the internal top and bottom
switches. Both the DC bias and gate charge
losses are proportional to VIN and thus their effects will
be more pronounced at higher supply voltages.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
oftenusefultoanalyzeindividuallossestodeterminewhat
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3410-1.875 circuits: VIN quiescent current
and I2R losses. The VIN quiescent current loss dominates
the efficiency loss at very low load currents whereas the
I2R loss dominates the efficiency loss at medium to high
load currents. In a typical efficiency plot, the efficiency
curveatverylowloadcurrentscanbemisleadingsincethe
actual power lost is of no consequence as illustrated in
Figure 2.
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I2R losses, simply add RSW
toRL andmultiplytheresultbythesquareoftheaverage
output current.
1. The VIN quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
1
V
= 3.6V
IN
0.1
0.01
0.001
0.0001
0.00001
0.1
1
10
100
1000
LOAD CURRENT (mA)
34101875 F02
Figure 2. Power Loss vs Load Current
34101875f
10
LTC3410-1.875
W U U
APPLICATIO S I FOR ATIO
U
Thermal Considerations
For the SC70 package, the θJA is 250°C/W. Thus, the
junction temperature of the regulator is:
In most applications the LTC3410-1.875 does not dissi-
pate much heat due to its high efficiency. But, in applica-
tionswheretheLTC3410-1.875isrunningathighambient
temperature with low supply voltage, the heat dissipated
may exceed the maximum junction temperature of the
part. If the junction temperature reaches approximately
150°C,bothpowerswitcheswillbeturnedoffandtheSW
node will become high impedance.
TJ = 70°C + (0.0864)(250) = 91.6°C
which is well below the maximum junction temperature
of 125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (RDS(ON)).
Checking Transient Response
To prevent the LTC3410-1.875 from exceeding the maxi-
mum junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD • ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or dis-
charge COUT, which generates a feedback error signal. The
regulator loop then acts to return VOUT to its steady-state
value. DuringthisrecoverytimeVOUT canbemonitoredfor
overshoot or ringing that would indicate a stability prob-
lem. For a detailed explanation of switching control loop
theory, see Application Note 76.
TR = (PD)(θJA)
where PD is the power dissipated by the regulator and
θJAis the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, TJ, is given by:
TJ = TA + TR
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The dis-
charged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • CLOAD).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
where TA is the ambient temperature.
As an example, consider the LTC3410-1.875 with an input
voltage of 2.7V, a load current of 300mA and an ambient
temperature of 70°C. From the typical performance
graph of switch resistance, the RDS(ON) of the
P-channel switch at 70°C is approximately 1.05Ω and
the RDS(ON) of the N-channel synchronous switch is ap-
proximately 0.75Ω. The series resistance looking into the
SW pin is:
RSW = 1.05Ω (0.69) + 0.75Ω (0.31) = 0.96Ω
Therefore, power dissipated by the part is:
PD = ILOAD2 • RDS(ON) = 86.4mW
34101875f
11
LTC3410-1.875
W U U
U
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
and high load currents is important. With this informa-
tion we can calculate L using Equation (1),
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3410-1.875. These items are also illustrated graphi-
callyin Figures3and4. Checkthefollowinginyourlayout:
⎛
⎞
1
VOUT
L=
VOUT 1−
(3)
⎜
⎟
⎠
f ∆I
V
⎝
L
IN
Substituting VOUT = 1.875V, VIN = 4.2V, ∆IL = 100mA
1. The power traces, consisting of the GND trace, the SW
trace and the VIN trace should be kept short, direct and
wide.
and f = 2.25MHz in Equation (3) gives:
1.875V
2.25MHz(100mA)
1.875V
4.2V
⎛
⎞
2. Does the (+) plate of CIN connect to VIN as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
L =
1−
= 4.6µH
⎜
⎝
⎟
⎠
A 4.7µH inductor works well for this application. For best
efficiency choose a 360mA or greater inductor with less
than 0.3Ω series resistance.
3. Keep the (–) plates of CIN and COUT as close as possible.
Design Example
CIN will require an RMS current rating of at least 0.125A ≅
Asadesignexample, assumetheLTC3410-1.875isused
in a single lithium-ion battery-powered cellular phone
application. The VIN will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.3A but most of the time it will be in
standbymode, requiringonly2mA. Efficiencyatbothlow
I
LOAD(MAX)/2 at temperature and COUT will require an ESR
of less than 0.5Ω. In most cases, a ceramic capacitor will
satisfy this requirement.
Figure 5 shows the complete circuit along with its
efficiency curve.
V
V
IN
OUT
1
VIA TO V
RUN
IN
LTC3410-1.875
2
3
6
4
GND
V
OUT
PIN 1
–
+
L1
C
V
OUT
OUT
LTC3410-
1.875
SW
V
IN
L1
5
SW
C
IN
V
IN
C
C
IN
OUT
34101875 F03
34101875 F04
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 3. LTC3410-1.875 Layout Diagram
Figure 4. LTC3410-1.875 Suggested Layout
34101875f
12
LTC3410-1.875
W U U
APPLICATIO S I FOR ATIO
U
4.7µH*
V
IN
3
6
4
1
V
OUT
2.7V
V
SW
IN
1.875V
†
†
TO 4.2V
C
IN
C
OUT
LTC3410-1.875
4.7µF
CER
4.7µF
RUN
CER
V
OUT
GND
2, 5
†TAIYO YUDEN JMK212BJ475
*MURATA LQH32CN4R7M23
34101875 F05a
Figure 5a
100
90
80
70
60
50
40
30
20
EFFICIENCY, V = 2.7V
IN
EFFICIENCY, V = 3.6V
IN
10
EFFICIENCY, V = 4.2V
IN
0
0.1
1
10
100
1000
LOAD (mA)
34101875 F05b
Figure 5b
V
OUT
100mV/DIV
AC COUPLED
I
L
200mA/DIV
I
LOAD
200mA/DIV
20µs/DIV
34101875 F05C
V
LOAD
= 3.6V
IN
I
= 100mA TO 300mA
Figure 5c
34101875f
13
LTC3410-1.875
U
TYPICAL APPLICATIO
Using Low Profile Components, <1mm Height
4.7µH*
V
IN
3
6
4
1
V
OUT
2.7V
V
SW
IN
1.875V
†
TO 4.2V
†
C
OUT
C
LTC3410-1.875
IN
4.7µF
4.7µF
RUN
CER
V
OUT
GND
2, 5
† TAIYO YUDEN JMK212BJ475
*FDK MIPF2520D
34101875 TA03
Low Profile Efficiency
100
90
80
70
60
50
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
0.1
1
10
100
1000
LOAD (mA)
34101875 TA04
Load Step
V
OUT
100mV/DIV
AC COUPLED
I
L
200mA/DIV
I
LOAD
200mA/DIV
20µs/DIV
34101875 TA05
V
LOAD
= 3.6V
IN
I
= 100mA TO 300mA
34101875f
14
LTC3410-1.875
U
PACKAGE DESCRIPTIO
SC6 Package
6-Lead Plastic SC70
(Reference LTC DWG # 05-08-1638)
0.47
MAX
0.65
REF
1.80 – 2.20
(NOTE 4)
1.00 REF
INDEX AREA
(NOTE 6)
1.15 – 1.35
(NOTE 4)
1.80 – 2.40
2.8 BSC 1.8 REF
PIN 1
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.15 – 0.30
6 PLCS (NOTE 3)
0.65 BSC
0.10 – 0.40
0.80 – 1.00
0.00 – 0.10
REF
1.00 MAX
GAUGE PLANE
0.15 BSC
0.26 – 0.46
SC6 SC70 1205 REV B
0.10 – 0.18
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. DETAILS OF THE PIN 1 INDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE INDEX AREA
7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70
8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB
34101875f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC3410-1.875
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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600mA (I ), 1.5MHz, Synchronous Step-Down
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96% Efficiency, V = 2.5V to 5.5V, V = Dynamically Adjustable,
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I = 20µA, I = <1µA, DFN Package
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OUT
IN
LTC3404
600mA (I ), 1.4MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, V = 2.7V to 6V, V
= 0.8V, I = 10µA,
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LTC3405/LTC3405A
LTC3406/LTC3406B
LTC3409
300mA (I ), 1.5MHz, Synchronous Step-Down
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96% Efficiency, V = 2.5V to 5.5V, V
= 0.8V, I = 20µA,
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600mA (I ), 1.5MHz, Synchronous Step-Down
96% Efficiency, V = 2.5V to 5.5V, V
= 0.6V, I = 20µA,
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DD8 Package
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95% Efficiency, V = 2.5V to 5.5V, V
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LTC3412
2.5A (I ), 4MHz, Synchronous Step-Down
95% Efficiency, V = 2.5V to 5.5V, V
= 0.8V, I = 60µA,
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LTC3440
600mA (I ), 2MHz, Synchronous Buck-Boost
95% Efficiency, V = 2.5V to 5.5V, V
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= <1µA, MS Package
SD
34101875f
LT 0306 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
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© LINEAR TECHNOLOGY CORPORATION 2005
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