LTC3411EDD#TRPBF [Linear]
LTC3411 - 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C;
| 型号： | LTC3411EDD#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3411 - 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C 转换器 |
| 文件： | 总20页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3411
1.25A, 4MHz, Synchronous
Step-Down DC/DC Converter
U
FEATURES
DESCRIPTIO
■
Small 10-Lead MSOP or DFN Package
The LTC®3411 is a constant frequency, synchronous,
step- down DC/DC converter. Intended for medium power
applications,itoperatesfroma2.63Vto5.5Vinputvoltage
range and has a user configurable operating frequency up
to 4MHz, allowing the use of tiny, low cost capacitors and
inductors 2mm or less in height. The output voltage is
adjustable from 0.8V to 5V. Internal sychronous 0.11Ω
power switches with 1.6A peak current ratings provide
high efficiency. The LTC3411’s current mode architecture
and external compensation allow the transient response
to be optimized over a wide range of loads and output
capacitors.
■
Uses Tiny Capacitors and Inductor
■
High Frequency Operation: Up to 4MHz
■
High Switch Current: 1.6A
■
Low RDS(ON) Internal Switches: 0.110Ω
■
High Efficiency: Up to 95%
Stable with Ceramic Capacitors
■
■
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
■
■
Low Dropout Operation: 100% Duty Cycle
■
Low Shutdown Current: IQ ≤ 1µA
■
Low Quiescent Current: 60µA
The LTC3411 can be configured for automatic power
saving Burst Mode operation to reduce gate charge losses
when the load current drops below the level required for
continuous operation. For reduced noise and RF interfer-
ence, the SYNC/MODE pin can be configured to skip
pulses or provide forced continuous operation.
■
Output Voltages from 0.8V to 5V
Selectable Burst Mode® Operation
■
■
Sychronizable to External Clock
U
APPLICATIO S
■
Notebook Computers
To further maximize battery life, the P-channel MOSFET is
turned on continuously in dropout (100% duty cycle) with
a low quiescent current of 60µA. In shutdown, the device
draws <1µA.
■
Digital Cameras
■
Cellular Phones
Handheld Instruments
Board Mounted Power Supplies
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
U
TYPICAL APPLICATIO
V
IN
Efficiency vs Load Current
2.63V TO 5.5V
100
C1
22µF
95
90
V
SYNC/MODE
PGOOD
PV
IN
IN
IN
L1
SV
2.2µH
V
OUT
2.5V/1.25A
SW
LTC3411
C2
22µF
I
TH
SHDN/R
887k
85
80
75
70
V
T
FB
13k
1000pF
SGND
PGND
324k
412k
V
V
O
= 3.3V
= 2.5V
= 1MHz
IN
OUT
f
NOTE: IN DROPOUT, THE OUTPUT TRACKS
THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)
3411 F01
Burst Mode OPERATION
1
10
100
1000
LOAD CURRENT (mA)
3411 TA01
Figure 1. Step-Down 2.5V/1.25A Regulator
sn3411 3411fs
1
LTC3411
W W U W
ABSOLUTE AXI U RATI GS (Note 1)
PVIN, SVIN Voltages .....................................–0.3V to 6V
VFB, ITH, SHDN/RT Voltages .......... –0.3V to (VIN + 0.3V)
SYNC/MODE Voltage .................... –0.3V to (VIN + 0.3V)
SW Voltage ................................... –0.3V to (VIN + 0.3V)
PGOOD Voltage ...........................................–0.3V to 6V
Operating Ambient Temperature Range
Junction Temperature (Notes 5, 8) ....................... 125°C
Storage Temperature Range
DD Package ...................................... –65°C to 125°C
MS Package .................................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
(Note 2) .................................................. –40°C to 85°C
U
W
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
SHDN/R
1
2
3
4
5
10
9
I
TH
T
SHDN/R
SYNC/MODE
SGND
1
2
3
4
5
10
9
I
TH
T
SYNC/MODE
SGND
V
FB
V
FB
LTC3411EDD
LTC3411EMS
8
PGOOD
8
PGOOD
SW
PGND
7
6
SV
SW
7
SV
IN
IN
PV
IN
PGND
6
PV
IN
MS PACKAGE
10-LEAD PLASTIC MSOP
DD PART MARKING
LADT
MS PART MARKING
LTQT
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W, θJC = 3°C/W
(EXPOSED PAD MUST BE SOLDERED TO PCB)
TJMAX = 125°C, θJA = 120°C/W, θJC = 10°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, RT = 324k unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
2.625
TYP
MAX
5.5
±0.1
0.816
0.2
UNITS
V
µA
V
%/V
%
%
V
Operating Voltage Range
Feedback Pin Input Current
Feedback Voltage
Reference Voltage Line Regulation
Output Voltage Load Regulation
IN
I
(Note 3)
(Note 3)
FB
V
●
0.784
0.8
0.04
0.02
–0.02
FB
∆V
∆V
V
= 2.7V to 5V
LINEREG
IN
I
I
= 0.36, (Note 3)
= 0.84, (Note 3)
●
●
0.2
–0.2
LOADREG
TH
TH
g
Error Amplifier Transconductance
I
Pin Load = ±5µA (Note 3)
800
µS
m(EA)
TH
I
Input DC Supply Current (Note 4)
Active Mode
S
V
V
V
= 0.75V, SYNC/MODE = 3.3V
240
62
0.1
350
100
1
µA
µA
µA
FB
Sleep Mode
= 3.3V, V = 1V
FB
SYNC/MODE
Shutdown
= 3.3V
SHDN/RT
V
Shutdown Threshold High
Active Oscillator Resistor
V
IN
– 0.6 V – 0.4
V
Ω
SHDN/RT
IN
324k
1M
f
Oscillator Frequency
R = 324k
0.85
1
1.15
4
4
MHz
MHz
MHz
A
OSC
T
(Note 7)
(Note 7)
f
I
Synchronization Frequency
Peak Switch Current Limit
0.4
1.6
SYNC
LIM
I
= 1.3
2
TH
R
Top Switch On-Resistance (Note 6)
Bottom Switch On-Resistance (Note 6)
Switch Leakage Current
V
V
V
V
= 3.3V
= 3.3V
= 6V, V
0.11
0.11
0.01
2.5
0.15
0.15
1
Ω
DS(ON)
IN
IN
IN
IN
Ω
I
= 0V, V = 0V
µA
V
SW(LKG)
ITH/RUN
FB
V
Undervoltage Lockout Threshold
Ramping Down
2.375
2.625
UVLO
sn3411 3411fs
2
LTC3411
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, RT = 324k unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PGOOD
Power Good Threshold
V
V
Ramping Up, SHDN/R = 1V
6.8
–7.6
%
%
FB
FB
T
Ramping Down, SHDN/R = 1V
T
R
PGOOD
Power Good Pull-Down On-Resistance
118
200
Ω
Note 5: T is calculated from the ambient T and power dissipation P
according to the following formula:
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
J
A
D
LTC3411EDD: T = T + (P • 43°C/W)
Note 2: The LTC3411E is guaranteed to meet specified performance from
0°C to 70°C. Specifications over the –40°C to 85°C operating ambient
termperature range are assured by design, characterization and correlation
with statistical process controls.
J
A
D
LTC3411EMS: T = T + (P • 120°C/W)
J
A
D
Note 6: Switch on-resistance is guaranteed by correlation to wafer level
measurements.
Note 3: The LTC3411 is tested in a feedback loop which servos V to the
Note 7: 4MHz operation is guaranteed by design but not production tested
and is subject to duty cycle limitations (see Applications Information).
FB
midpoint for the error amplifier (V = 0.6V).
ITH
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
U
U
U
PI FU CTIO S
SHDN/RT (Pin 1): Combination Shutdown and Timing
Resistor Pin. The oscillator frequency is programmed by
connecting a resistor from this pin to ground. Forcing this
pin to SVIN causes the device to be shut down. In shut-
down all functions are disabled.
PGND (Pin 5): Main Power Ground Pin. Connect to the
(–) terminal of COUT, and (–) terminal of CIN.
PVIN (Pin 6): Main Supply Pin. Must be closely decoupled
to PGND.
SVIN (Pin 7): The Signal Power Pin. All active circuitry is
powered from this pin. Must be closely decoupled to
SGND. SVIN must be greater than or equal to PVIN.
SYNC/MODE (Pin 2): Combination Mode Selection and
Oscillator Synchronization Pin. This pin controls the op-
eration of the device. When tied to SVIN or SGND, Burst
Mode operation or pulse skipping mode is selected, re-
spectively. If this pin is held at half of SVIN, the forced
continuous mode is selected. The oscillation frequency
can be syncronized to an external oscillator applied to this
pin. When synchronized to an external clock pulse skip
mode is selected.
PGOOD (Pin 8): The Power Good Pin. This common drain
logic output is pulled to SGND when the output voltage is
not within ±7.5% of regulation.
VFB (Pin 9): Receives the feedback voltage from the
external resistive divider across the output. Nominal volt-
age for this pin is 0.8V.
SGND (Pin 3): The Signal Ground Pin. All small signal
components and compensation components should be
connected to this ground (see Board Layout Consider-
ations).
ITH (Pin 10): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.5V.
SW (Pin 4): The Switch Node Connection to the Inductor.
This pin swings from PVIN to PGND.
sn3411 3411fs
3
LTC3411
U
U
U
PI FU CTIO S
NOMINAL (V)
TYP MAX
ABSOLUTE MAX (V)
MIN MAX
SV + 0.3
PIN
1
NAME
DESCRIPTION
MIN
–0.3
0
SHDN/R
Shutdown/Timing Resistor
Mode Select/Sychronization Pin
Signal Ground
0.8
SV
IN
SV
IN
–0.3
–0.3
T
IN
2
SYNC/MODE
SGND
SV + 0.3
IN
3
0
4
SW
Switch Node
0
PV
IN
–0.3
PV + 0.3
IN
5
PGND
Main Power Ground
0
6
PV
SV
Main Power Supply
–0.3
2.5
0
5.5
5.5
SV
–0.3
–0.3
–0.3
–0.3
–0.3
SV + 0.3
IN
IN
IN
7
Signal Power Supply
Power Good Pin
6
6
8
PGOOD
IN
9
V
FB
Output Feedback Pin
Error Amplifier Compensation and Run Pin
0
0.8
1.0
1.5
SV + 0.3
IN
10
I
0
SV + 0.3
IN
TH
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Burst Mode Operation
Pulse Skipping Mode
Forced Continuous Mode
VOUT
10mV/
DIV
VOUT
10mV/
DIV
VOUT
10mV/
DIV
IL1
100mA/
DIV
IL1
100mA/
DIV
IL1
100mA/
DIV
VIN = 3.3V
2µs/DIV
3411 G01.eps
VIN = 3.3V
2µs/DIV
3411 G02.eps
VIN = 3.3V
2µs/DIV
3411 G03.eps
VOUT = 2.5V
ILOAD = 50mA
VOUT = 2.5V
ILOAD = 50mA
VOUT = 2.5V
ILOAD = 50mA
CIRCUIT OF FIGURE 7
CIRCUIT OF FIGURE 7
CIRCUIT OF FIGURE 7
Efficiency vs Load Current
Efficiency vs VIN
Load Step
100
100
95
90
85
80
75
70
65
60
I
= 400mA
Burst Mode
OPERATION
OUT
95
90
85
80
75
70
65
60
VOUT
100mV/
DIV
I
= 1.25A
OUT
PULSE SKIP
FORCED CONTINUOUS
IL1
0.5A/
DIV
V
V
= 3.3V
IN
OUT
VIN = 3.3V
40µs/DIV
3411 G06.eps
V
= 2.5V
= 2.5V
OUT
VOUT = 2.5V
CIRCUIT OF FIGURE 7
CIRCUIT OF FIGURE 7
100 1000 10000
LOAD CURRENT (mA)
ILOAD = 0.25mA TO 1.25A
CIRCUIT OF FIGURE 7
1
10
2.5
3.5
4.5
(V)
5.5
V
IN
3411 G04
3411 G05
sn3411 3411fs
4
LTC3411
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Load Regulation
Line Regulation
Frequency vs VIN
0.4
0.3
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
10
8
V
V
= 3.3V
V
T
= 1.8V
V
= 1.8V
OUT
IN
OUT
OUT
A
= 2.5V
= 25°C
I
= 1.25A
OUT
Burst Mode
OPERATION
T
= 25°C
A
6
0.2
4
PULSE SKIP
0.1
2
0
FORCED
0
CONTINUOUS
–0.1
–0.2
–0.3
–0.4
–0.5
–2
–4
–6
–8
–10
I
= 1.25A
OUT
I
= 400mA
5
OUT
1
10
100
1000
10000
2
3
4
(V)
6
2
3
4
5
6
LOAD CURRENT (mA)
V
V
IN
(V)
IN
3411 G07
3411 G08
3411 G09
Frequency Variation
vs Temperature
Efficiency vs Frequency
RDS(ON) vs VIN
10
8
100
95
120
115
110
105
100
95
V
= 3.3V
T
= 25°C
IN
A
V
= 2.5V
OUT
OUT
A
I
= 500mA
= 25°C
6
T
4
SYNCHRONOUS SWITCH
2
0
–2
–4
–6
–8
–10
MAIN SWITCH
90
85
90
2.5
0
1
2
3
4
–50 –25
0
25
50
75 100 125
3
3.5
4
4.5
(V)
5
5.5
6
FREQUENCY (MHz)
TEMPERATURE (°C)
V
IN
3411 G10
3411 G12
3411 G11
sn3411 3411fs
5
LTC3411
W
BLOCK DIAGRA
SV
IN
SGND
3
I
PV
IN
TH
7
10
6
0.8V
PMOS CURRENT
COMPARATOR
VOLTAGE
REFERENCE
I
TH
LIMIT
BCLAMP
+
–
+
–
B
–
+
9
V
FB
ERROR
AMPLIFIER
V
B
BURST
COMPARATOR
+
–
0.74V
HYSTERESIS = 80mV
SLOPE
COMPENSATION
4
SW
OSCILLATOR
+
–
LOGIC
0.86V
+
PGOOD
8
–
NMOS
COMPARATOR
–
+
5
PGND
REVERSE
COMPARATOR
1
2
SYNC/MODE
SHDN/R
3411 BD
T
sn3411 3411fs
6
LTC3411
U
OPERATIO
The LTC3411 uses a constant frequency, current mode
architecture. The operating frequency is determined by
the value of the RT resistor or can be synchronized to an
external oscillator. To suit a variety of applications, the
selectable Mode pin, allows the user to trade-off noise for
efficiency.
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3411
automaticallyswitchesintoBurstModeoperationinwhich
the PMOS switch operates intermittently based on load
demand. By running cycles periodically, the switching
losses which are dominated by the gate charge losses of
thepowerMOSFETsareminimized. Themaincontrolloop
is interrupted when the output voltage reaches the desired
regulated value. The hysteretic voltage comparator B trips
when ITH is below 0.24V, shutting off the switch and
reducingthepower. Theoutputcapacitorandtheinductor
supply the power to the load until ITH/RUN exceeds 0.31V,
turning on the switch and the main control loop which
starts another cycle.
The output voltage is set by an external divider returned to
theVFB pin. Anerroramplfiercomparesthedividedoutput
voltage with a reference voltage of 0.8V and adjusts the
peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the PGOOD output low
if the output voltage is not within ±7.5%.
Main Control Loop
For lower output voltage ripple at low currents, pulse
skipping mode can be used. In this mode, the LTC3411
continues to switch at a constant frequency down to very
lowcurrents,whereitwilleventuallybeginskippingpulses.
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the VFB voltage is below the the reference voltage.
The current into the inductor and the load increases until
the current limit is reached. The switch turns off and
energy stored in the inductor flows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.
Finally, in forced continuous mode, the inductor current is
constantly cycled which creates a fixed output voltage
ripple at all output current levels. This feature is desirable
in telecommunications since the noise is at a constant
frequency and is thus easy to filter out. Another advantage
of this mode is that the regulator is capable of both
sourcing current into a load and sinking some current
from the output.
The peak inductor current is controlled by the voltage on
the ITH pin, which is the output of the error amplifier.This
amplifier compares the VFB pin to the 0.8V reference.
When the load current increases, the VFB voltage de-
creasesslightlybelowthereference.Thisdecreasecauses
the error amplifier to increase the ITH voltage until the
average inductor current matches the new load current.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which is
the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being
equal to the input voltage minus the voltage drops across
the internal P-channel MOSFET and the inductor.
ThemaincontrolloopisshutdownbypullingtheSHDN/RT
pin to SVIN. A digital soft-start is enabled after shutdown,
which will slowly ramp the peak inductor current up over
1024 clock cycles or until the output reaches regulation,
whicheverisfirst.Soft-startcanbelengthenedbyramping
the voltage on the ITH pin (see Applications Information
section).
Low Supply Operation
TheLTC3411incorporatesanundervoltagelockoutcircuit
which shuts down the part when the input voltage drops
below about 2.5V to prevent unstable operation.
Low Current Operation
Three modes are available to control the operation of the
LTC3411 at low currents. All three modes automatically
switch from continuous operation to to the selected mode
when the load current is low.
sn3411 3411fs
7
LTC3411
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APPLICATIO S I FOR ATIO
A general LTC3411 application circuit is shown in
Figure 5. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L1. Once L1 is chosen, CIN and COUT can be
selected.
A reasonable starting point for setting ripple current is
∆IL = 0.3•ILIM, whereILIM isthepeakswitchcurrentlimit.
The largest ripple current ∆IL occurs at the maximum
input voltage. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
Operating Frequency
VOUT
fO• ∆IL
VOUT
VIN(MAX)
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
L =
• 1−
The inductor value will also have an effect on Burst Mode
operation.Thetransitionfromlowcurrentoperationbegins
whenthepeakinductorcurrentfallsbelowalevelsetbythe
burst clamp. Lower inductor values result in higher ripple
current which causes this to occur at lower load currents.
This causes a dip in efficiency in the upper range of low
current operation. In Burst Mode operation, lower induc-
tance values will cause the burst frequency to increase.
Theoperatingfrequency, fO, oftheLTC3411isdetermined
by an external resistor that is connected between the RT
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timingcapacitorwithintheoscillatorandcanbecalculated
by using the following equation:
4.5
T
= 25°C
A
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
−1.08
RT = 9.78•1011
( O)
f
Ω
( )
or can be selected using Figure 2.
Themaximumusableoperatingfrequencyislimitedbythe
minimum on-time and the duty cycle. This can be calcu-
lated as:
fO(MAX) ≈ 6.67 • (VOUT / VIN(MAX)) (MHz)
0
0
500
1500
1000
R
(kΩ)
The minimum frequency is limited by leakage and noise
coupling due to the large resistance of RT.
T
3411 F02
Figure 2. Frequency vs RT
Inductor Selection
Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current ∆IL decreases with
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Tor-
oid or shielded pot cores in ferrite or permalloy materials
aresmallanddon’tradiatemuchenergy, butgenerallycost
more than powdered iron core inductors with similar
electrical characteristics. The choice of which style induc-
tor to use often depends more on the price vs size require-
ments and any radiated field/EMI requirements than on
higher inductance and increases with higher VIN or VOUT
:
VOUT
fO•L
VOUT
VIN
∆IL =
• 1−
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.
whattheLTC3411requirestooperate.Table1showssome
sn3411 3411fs
8
LTC3411
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APPLICATIO S I FOR ATIO
typical surface mount inductors that work well in LTC3411
series resistance (ESR) input capacitor sized for the maxi-
mum RMS current must be used. The maximum RMS
capacitor current is given by:
applications.
Table 1. Representative Surface Mount Inductors
MANU-
FACTURER PART NUMBER
MAX DC
VOUT (V − VOUT
)
VALUE CURRENT DCR HEIGHT
IN
IRMS ≈ IMAX
Toko
A914BYW-2R2M-D52LC 2.2µH
2.05A 49mΩ 2mm
V
IN
Toko
A915AY-2ROM-D53LC
D01608C-222
2µH
3.3A
2.3A
22mΩ 3mm
70mΩ 3mm
where the maximum average output current IMAX equals
the peak current minus half the peak-to-peak ripple cur-
rent, IMAX = ILIM – ∆IL/2.
Coilcraft
Coilcraft
Sumida
Sumida
2.2µH
2.2µH
2.2µH
2.2µH
2.2µH
2.2µH
2.2µH
LP01704-222M
CDRH4D282R2
CDC5D232R2
2.4A 120mΩ 1mm
2.04A 23mΩ 3mm
2.16A 30mΩ 2.5mm
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst case is commonly used
to design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours life-
time. This makes it advisable to further derate the capaci-
tor, or choose a capacitor rated at a higher temperature
thanrequired. Severalcapacitorsmayalsobeparalleledto
meet the size or height requirements of the design. An
additional 0.1µF to 1µF ceramic capacitor is also recom-
mended on VIN for high frequency decoupling, when not
using an all ceramic capacitor solution.
Taiyo Yuden N06DB2R2M
Taiyo Yuden N05DB2R2M
3.2A
2.9A
3.2A
29mΩ 3.2mm
32mΩ 2.8mm
24mΩ 5mm
Murata
LQN6C2R2M04
Catch Diode Selection
Although unnecessary in most applications, a small im-
provement in efficiency can be obtained in a few applica-
tionsbyincludingtheoptionaldiodeD1showninFigure 5,
which conducts when the synchronous switch is off.
When using Burst Mode operation or pulse skip mode, the
synchronous switch is turned off at a low current and the
remaining current will be carried by the optional diode. It
is important to adequately specify the diode peak current
and average power dissipation so as not to exceed the
diode ratings. The main problem with Schottky diodes is
that their parasitic capacitance reduces the efficiency,
usually negating the possible benefits for LTC3411 cir-
cuits. Another problem that a Schottky diode can intro-
duceishigherleakagecurrentathightemperatures,which
could reduce the low current efficiency.
Output Capacitor (COUT) Selection
The selection of COUT is driven by the required ESR to
minimizevoltagerippleandloadsteptransients.Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering. The output ripple (∆VOUT) is deter-
mined by:
1
∆VOUT ≈ ∆IL ESR +
8fOCOUT
Remember to keep lead lengths short and observe proper
grounding (see Board Layout Considerations) to avoid
ringing and increased dissipation when using a catch
diode.
where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.3 • ILIM the output ripple
will be less than 100mV at maximum VIN and fO = 1MHz
with:
Input Capacitor (CIN) Selection
In continuous mode, the input current of the converter is
a square wave with a duty cycle of approximately VOUT
/
ESRCOUT < 150mΩ
VIN. To prevent large voltage transients, a low equivalent
sn3411 3411fs
9
LTC3411
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APPLICATIO S I FOR ATIO
Once the ESR requirements for COUT have been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement, except for an all ceramic solution.
pacitors remain capacitive to beyond 300kHz and ususally
resonate with their ESL before ESR becomes effective.
Also, ceramic caps are prone to temperature effects which
requires the designer to check loop stability over the
operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used. A good selection of
ceramiccapacitorsisavailablefromTaiyoYuden,TDKand
Murata.
In surface mount applications, multiple capacitors may
havetobeparalleledtomeetthecapacitance, ESRorRMS
current handling requirement of the application. Alumi-
numelectrolytic,specialpolymer,ceramicanddrytantulum
capacitors are all available in surface mount packages.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR(size) product of any
aluminumelectrolyticatasomewhathigherprice. Special
polymer capacitors, such as Sanyo POSCAP, offer very
low ESR, but have a lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
density, but it has a larger ESR and it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surface mount tantalums, avalable in case heights rang-
ing from 2mm to 4mm. Aluminum electrolytic capacitors
have a significantly larger ESR, and is often used in
extremely cost-sensitive applications provided that con-
sideration is given to ripple current ratings and long term
reliability. Ceramic capacitors have the lowest ESR and
cost but also have the lowest capacitance density, a high
voltage and temperature coefficient and exhibit audible
piezoelectric effects. In addition, the high Q of ceramic
capacitors along with trace inductance can lead to signifi-
cant ringing. Other capacitor types include the Panasonic
specialty polymer (SP) capacitors.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires,suchasfromawalladapter,aloadstepattheoutput
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, the ringing at the input can be large enough to
damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
untilthefeedbackloopraisestheswitchcurrentenoughto
support the load. The time required for the feedback loop
to respond is dependent on the compensation compo-
nentsandtheoutputcapacitorsize. Typically, 3to4cycles
are required to respond to a load step, but only in the first
cycle does the output drop linearly. The output droop,
VDROOP, is usually about 2 to 3 times the linear drop of the
first cycle. Thus, a good place to start is with the output
capacitor size of approximately:
In most cases, 0.1µF to 1µF of ceramic capacitors should
also be placed close to the LTC3411 in parallel with the
main capacitors for high frequency decoupling.
∆IOUT
COUT ≈ 2.5
fO •VDROOP
Ceramic Input and Output Capacitors
More capacitance may be required depending on the duty
cycle and load step requirements.
Higher value, lower cost ceramic capacitors are now
becomingavailableinsmallercasesizes.Thesearetempt-
ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generatesaloop“zero”at5kHzto50kHzthatisinstrumen-
tal in giving acceptable loop phase margin. Ceramic ca-
In most applications, the input capacitor is merely re-
quired to supply high frequency bypassing, since the
impedance to the supply is very low. A 10µF ceramic
capacitor is usually enough for these conditions.
sn3411 3411fs
10
LTC3411
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APPLICATIO S I FOR ATIO
Setting the Output Voltage
theinternalpeakinductorcurrent. Powersupplysequenc-
ing can also be accomplished using this pin. The LTC3411
has an internal digital soft-start which steps up a clamp on
The LTC3411 develops a 0.8V reference voltage between
the feedback pin, VFB, and the signal ground as shown in
Figure 5. The output voltage is set by a resistive divider
according to the following formula:
ITH over 1024 clock cycles, as can be seen in Figure 4.
The soft-start time can be increased by ramping the
voltage on ITH during start-up as shown in Figure 3(c). As
the voltage on ITH ramps through its operating range the
internal peak current limit is also ramped at a proportional
linear rate.
R2
VOUT ≈ 0.8V 1+
R1
Keeping the current small (<5µA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
Mode Selection and Frequency Synchronization
TheSYNC/MODEpinisamultipurposepinwhichprovides
mode selection and frequency synchronization. Connect-
ing this pin to VIN enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higheroutputvoltageripple. Whenthispinisconnectedto
ground, pulse skipping operation is selected which pro-
vides the lowest output voltage and current ripple at the
costoflowcurrentefficiency. Applyingavoltagewithin1V
of the supplies, results in forced continuous mode, which
createsafixedoutputrippleandiscapableofsinkingsome
current (about 1/2∆IL). Since the switching noise is con-
stantinthismode,itisalsotheeasiesttofilterout.Inmany
cases, the output voltage can be simply connected to the
SYNC/MODE pin, giving the forced continuous mode,
except at startup.
To improve the frequency response, a feed-forward ca-
pacitor CF may also be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
Shutdown and Soft-Start
The SHDN/RT pin is a dual purpose pin that sets the
oscillator frequency and provides a means to shut down
the LTC3411. This pin can be interfaced with control logic
in several ways, as shown in Figure 3(a) and Figure 3(b).
The ITH pin is primarily for loop compensation, but it can
also be used to increase the soft-start time. Soft start
reduces surge currents from VIN by gradually increasing
SHDN/R
SHDN/R
SV
IN
T
T
R
T
R
T
1M
VIN
2V/DIV
RUN
RUN
3411 F03a
3411 F03b
VOUT
2V/DIV
(3a)
(3b)
RUN OR V
I
TH
IN
IL
500mA/DIV
R1
R
C
D1
C1
C
C
3411 F03c
VIN = 3.3V
VOUT = 2.5V
RL = 1.4Ω
200µs/DIV
3411 F04.eps
(3c)
Figure 3. SHDN/RT Pin Interfacing and External Soft-Start
Figure 4. Digital Soft-Start
sn3411 3411fs
11
LTC3411
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The LTC3411 can also be synchronized to an external
clocksignalbytheSYNC/MODEpin.Theinternaloscillator
frequency should be set to 20% lower than the external
clock frequency to ensure adequate slope compensation,
since slope compensation is derived from the internal
oscillator. During synchronization, the mode is set to
pulse skipping and the top switch turn on is synchronized
to the rising edge of the external clock.
because the various types and values determine the loop
feedbackfactorgainandphase. Anoutputcurrentpulseof
20% to 100% of full load current having a rise time of 1µs
to10µswillproduceoutputvoltageandITH pinwaveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT
immediately shifts by an amount equal to ∆ILOAD • ESR,
Checking Transient Response
where ESR is the effective series resistance of COUT
.
The OPTI-LOOP compensation allows the transient re-
sponse to be optimized for a wide range of loads and
output capacitors. The availability of the ITH pin not only
allows optimization of the control loop behavior but also
provides a DC coupled and AC filtered closed loop re-
sponsetestpoint.TheDCstep,risetimeandsettlingatthis
test point truly reflects the closed loop response. Assum-
ing a predominantly second order system, phase margin
and/ordampingfactorcanbeestimatedusingthepercent-
age of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin.
∆ILOAD also begins to charge or discharge COUT generat-
ing a feedback error signal used by the regulator to return
VOUT to its steady-state value. During this recovery time,
VOUT canbemonitoredforovershootorringingthatwould
indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C. If
R is increased by the same factor that C is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor CF can
be added to improve the high frequency response, as
shown in Figure 5. Capacitor CF provides phase lead by
creatingahighfrequencyzerowithR2whichimprovesthe
phase margin.
The ITH external components shown in the Figure 1 circuit
will provide an adequate starting point for most applica-
tions. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
V
IN
2.5V
+
TO 5.5V
R5
R6
C6
C
IN
SV
PV
PGOOD
SW
PGOOD
IN
IN
C8
V
OUT
PGND
PGND
L1
C
OPTIONAL
D1
+
LTC3411
SYNC/MODE
F
SGND
C
C5
OUT
I
V
FB
TH
PGND
PGND
R2
R
SGND PGND SHDN/R
C
T
R1
C
SGND
ITH
R
T
C
C
SGND
SGND
GND
SGND SGND
3411 F05
Figure 5. LTC3411 General Schematic
sn3411 3411fs
12
LTC3411
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APPLICATIO S I FOR ATIO
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Linear
Technology Application Note 76.
1) The VIN current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
andcontrolcurrents.VIN currentresultsinasmall(<0.1%)
loss that increases with VIN, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
fromswitchingthegatecapacitanceofthepowerMOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from VIN to
ground. The resulting dQ/dt is a current out of VIN that is
typically much larger than the DC bias current. In continu-
ous mode, IGATECHG = fO(QT + QB), where QT and QB are
the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to VIN
and thus their effects will be more pronounced at higher
supply voltages.
3)I2RLossesarecalculatedfromtheDCresistancesofthe
internal switches, RSW, and external inductor, RL. In
continuous mode, the average output current flowing
through inductor L but is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET RDS(ON) and the duty cycle (DC) as
follows:
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage VIN drops toward VOUT, the load step capa-
bility does decrease due to the decreasing voltage across
the inductor. Applications that require large load step
capability near dropout should use a different topology
such as SEPIC, Zeta or single inductor, positive buck/
boost.
In some applications, a more severe transient can be
caused by switching in loads with large (>1uF) input
capacitors.Thedischargedinputcapacitorsareeffectively
put in parallel with COUT, causing a rapid drop in VOUT. No
regulator can deliver enough current to prevent this prob-
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A hot swap controller is
designedspecificallyforthispurposeandusuallyincorpo-
rates current limiting, short-circuit protection, and soft-
starting.
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
Efficiency Considerations
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
I2R losses = IOUT2(RSW + RL)
4)Other“hidden”lossessuchascoppertraceandinternal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that CIN has adequate
charge storage and very low ESR at the switching fre-
quency. Other losses including diode conduction losses
during dead-time and inductor core losses generally ac-
count for less than 2% total additional loss.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3411 circuits: 1) LTC3411 VIN current,
2) switching losses, 3) I2R losses, 4) other losses.
sn3411 3411fs
13
LTC3411
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APPLICATIO S I FOR ATIO
Thermal Considerations
assume that the actual junction temperature will not
exceed the absolute maximum junction temperature of
125°C.
In a majority of applications, the LTC3411 does not
dissipate much heat due to its high efficiency. However, in
applications where the LTC3411 is running at high ambi-
ent temperature with low supply voltage and high duty
cycles, suchasindropout, theheatdissipatedmayexceed
the maximum junction temperature of the part. If the
junction temperature reaches approximately 150°C, both
power switches will be turned off and the SW node will
become high impedance.
Design Example
As a design example, consider using the LTC3411 in a
portable application with a Li-Ion battery. The battery
provides a VIN = 2.5V to 4.2V. The load requires a maxi-
mumof1Ainactivemodeand10mAinstandbymode.The
output voltage is VOUT = 2.5V. Since the load still needs
power in standby, Burst Mode operation is selected for
good low load efficiency.
To avoid the LTC3411 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
First, calculate the timing resistor:
−1.08
R = 9.78•1011 1MHz
= 323.8k
(
)
T
Use a standard value of 324k. Next, calculate the inductor
value for about 30% ripple current at maximum VIN:
T
RISE = PD • θJA
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
2.5V
1MHz •510mA
2.5V
4.2V
L =
• 1−
= 2µH
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
Choosing the closest inductor from a vendor of 2.2µH,
results in a maximum ripple current of:
As an example, consider the case when the LTC3411 is in
dropout at an input voltage of 3.3V with a load current of
1A. From the Typical Performance Characteristics graph
of Switch Resistance, the RDS(ON) resistance of the
P-channel switch is 0.11Ω. Therefore, power dissipated
by the part is:
2.5V
1MHz •2.2µ
2.5V
4.2V
∆IL =
• 1−
= 460mA
For cost reasons, a ceramic capacitor will be used. COUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
PD = I2 • RDS(ON) = 110mW
1A
COUT ≈ 2.5
= 20µF
The MS10 package junction-to-ambient thermal resis-
tance, θJA, will be in the range of 100°C/W to 120°C/W.
Therefore, the junction temperature of the regulator oper-
ating in a 70°C ambient temperature is approximately:
1MHz •(5%•2.5V)
The closest standard value is 22µF. Since the output
impedance of a Li-Ion battery is very low, CIN is typically
10µF. In noisy environments, decoupling SVIN from PVIN
with an R6/C8 filter of 1Ω/0.1µF may help, but is typically
not needed.
TJ = 0.11 • 120 + 70 = 83.2°C
Remembering that the above junction temperature is
obtained from an RDS(ON) at 25°C, we might recalculate
the junction temperature based on a higher RDS(ON) since
it increases with temperature. However, we can safely
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
sn3411 3411fs
14
LTC3411
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APPLICATIO S I FOR ATIO
current in these resistors should be kept small. Choosing
2µA with the 0.8V feedback voltage makes R1~400k. A
close standard 1% resistor is 412k and R2 is then 887k.
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
2. Are the COUT and L1 closely connected? The (–) plate of
COUT returns current to PGND and the (–) plate of CIN.
The compensation should be optimized for these compo-
nents by examining the load step response but a good
place to start for the LTC3411 is with a 13kΩ and 1000pF
filter. The output capacitor may need to be increased
depending on the actual undershoot during a load step.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT and a ground line terminated
near SGND (Pin 3). The feedback signal VFB should be
routed away from noisy components and traces, such as
the SW line (Pin 4), and its trace should be minimized.
The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate
speed.
4. Keep sensitive components away from the SW pin. The
input capacitor CIN, the compensation capacitor CC and
CITH and all the resistors R1, R2, RT, and RC should be
routed away from the SW trace and the inductor L1.
Figure 1 shows the complete schematic for this design
example.
5. Agroundplaneispreferred, butifnotavailable, keepthe
signal and power grounds segregated with small signal
components returning to the SGND pin at one point which
is then connected to the PGND pin.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3411. These items are also illustrated graphically in
the layout diagram of Figure 6. Check the following in your
layout:
6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. These copper areas should be con-
nected to one of the input supplies: PVIN, PGND, SVIN or
SGND.
1. Does the capacitor CIN connect to the power VIN (Pin 6)
and power GND (Pin 5) as close as possible? This
C
IN
V
IN
C
OUT
V
PV
SV
PGND
SW
IN
L1
IN
OUT
R5
LTC3411
SGND
V
IN
PGOOD
PGOOD
V
SYNC/MODE
SHDN/R
FB
PS
BM
C4
R2
I
TH
T
R1
R3
R
T
C3
3411 F06
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 6. LTC3411 Layout Diagram (See Board Layout Checklist)
sn3411 3411fs
15
LTC3411
U
TYPICAL APPLICATIO S
V
IN
2.63V TO
5.5V
C1
22µF
R5
100k
PGOOD
PGND
PV
IN
L1
SV
PGOOD
SW
IN
2.2µH
V
OUT
RS1
1M
1.8V/2.5V/3.3V
AT 1.25A
LTC3411
BM
PS
R2 887K
SYNC/MODE
V
FC
FB
I
SHDN/R
T
RS2
1M
TH
3.3V
2.5V
1.8V
C2
22µF
SGND
PGND
C4 22pF
R3
13k
R4
324k
R1A
280k
R1B
412k
R1C
698k
C3
1000pF
3411 F07a
SGND
SGND
GND
SGND
PGND
NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)
Figure 7. General Purpose Buck Regulator Using Ceramic Capacitors
Efficiency vs Load Current
100
Burst Mode
OPERATION (BM)
95
90
PULSE SKIP
(PS)
FORCED
85
80
75
70
65
60
CONTINUOUS (FC)
V
V
O
= 3.3V
= 2.5V
= 1MHz
IN
OUT
f
1
10
100
1000
10000
LOAD CURRENT (mA)
3411 F07b
sn3411 3411fs
16
LTC3411
U
TYPICAL APPLICATIO S
Single Inductor, Positive, Buck-Boost Converter
C1
22µF
V
IN
2.63V
TO 5V
L1
3.3µH
D1
PV
SV
PGND
SW
IN
IN
V
OUT
3.3V/
100k
PGOOD
400mA
C2
22µF
×2
+
LTC3411
SGND
C4
47µF
M1
V
IN
PGOOD
V
SYNC/MODE
SHDN/R
FB
R1
280k
I
TH
T
R3
13k
R4
324k
R2
887k
C3
1000pF
C7
10pF
3411 TA02
C1, C2: TAIYO YUDEN JMK325BJ226MM
C4: SANYO POSCAP 6TPA47M
D1: ON MBRM120L
L1: TOKO A915AY-3R3M (D53LC SERIES)
M1: SILICONIX Si2302DS
Efficiency vs Load Current
85
80
75
70
65
60
55
f
= 1MHz
V
= 4V
IN
O
V
= 2.5V
IN
V
= 3V
IN
V
= 3.5V
IN
10
100k
LOAD CURRENT (mA)
1000
3411 TA03
sn3411 3411fs
17
LTC3411
U
TYPICAL APPLICATIO S
All Ceramic 2-Cell to 3.3V and 1.8V Converters
V
= 2V TO 3V
IN
L1
4.7µH
D1
V
OUT
3.3V
120mA/1A
C5
LTC3402
22µF
V
SW
OUT
IN
1M
SHDN
V
+
SV
PV
IN
IN
2
L2
CELLS
MODE/SYNC FB
SYNC/MODE
PGOOD
2.2µH
V
OUT
SW
1.8V/1.2A
LTC3411
604k
PGOOD
V
C
C2
C6
22µF
I
TH
C1
887k
1000pF
10pF
44µF
10µF
R
T
GND
SHDN/R
V
(2 × 22µF)
T
FB
13k
SGND
PGND
49.9k
47k
412k
324k
1000pF
3411 TA06
C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
C5, C6: TAIYO YUDEN JMK325BJ226MM
D1: ON SEMICONDUCTOR MBRM120LT3
L1: TOKO A916CY-4R7M
L2: TOKO A914BYW-2R2M (D52LC SERIES)
0 = FIXED FREQ
1 = Burst Mode OPERATION
Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
3.3V
1.8V
V
IN
= 2.4V
Burst Mode OPERATION
10
100
1000
10000
LOAD CURRENT (mA)
3211 TA07
sn3411 3411fs
18
LTC3411
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
0.38 ± 0.10
TYP
6
10
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 5)
PACKAGE
OUTLINE
(DD10) DFN 0403
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50
BSC
2.38 ±0.10
(2 SIDES)
2.38 ±0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MS10 Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
0.497 ± 0.076
(.0196 ± .003)
10 9
8
7 6
REF
5.23
3.2 – 3.45
(.206)
(.126 – .136)
MIN
3.00 ± 0.102
(.118 ± .004)
NOTE 4
DETAIL “A”
0° – 6° TYP
4.88 ± 0.10
(.192 ± .004)
0.254
(.010)
GAUGE PLANE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
1
2
3
4 5
0.53 ± 0.01
(.021 ± .006)
RECOMMENDED SOLDER PAD LAYOUT
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
NOTE:
0.17 – 0.27
(.007 – .011)
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
0.13 ± 0.05
(.005 ± .002)
MSOP (MS) 0402
0.50
(.0197)
TYP
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
sn3411 3411fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC3411
U
TYPICAL APPLICATIO
2mm Height, 2MHz, Li-Ion to 1.8V Converter
V
IN
2.63V
R5
TO 4.2V
+
C6
1µF
C1
33µF
100k
PV
SV
PGOOD
SW
PGOOD
C4 22pF
IN
V
OUT
1.8V
IN
L1
1µH
AT 1.25A
+
LTC3411
SYNC/MODE
C2
33µF
C5
1µF
I
TH
V
FB
R2
887k
R1
698k
R3
15k
C3
470pF
C7
47pF
SGND PGND SHDN/R
T
R4
154k
3411 TA04
C1, C2: AVX TPSB336K006R0600
C4, C5: TAIYO YUDEN LMK212BJ105MG
L1: COILCRAFT DO1606T-102
Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
55
50
2.5V
3.6V
4.2V
V
O
= 1.8V
OUT
= 2MHz
f
1
10
100
1000
10000
LOAD CURRENT (mA)
3411 TA05
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I : 280µA, I : <1µA, TSSOP16E
Q SD
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90% Efficiency, V : 5.5V to 60V, V : 1.20V,
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IN
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Q
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600mA (I ) 2MHz Synchronous Buck-Boost DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V : 2.5V,
OUT(MIN)
OUT
IN
I : 25µA, I : <1µA, 10-Lead MS
Q
SD
ThinSOT is a trademark of Linear Technology Corporation.
sn3411 3411fs
LT/TP 0503 2K • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
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