LTC3411EMS#TR [Linear]
LTC3411 - 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C;
| 型号： | LTC3411EMS#TR |
| 厂家： | 
Linear |
| 描述： | LTC3411 - 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总24页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3411
1.25A, 4MHz, Synchronous
Step-Down DC/DC Converter
FEATURES
DESCRIPTION
The LTC®3411 is a constant frequency, synchronous,
step- down DC/DC converter. Intended for medium power
applications,itoperatesfroma2.63Vto5.5Vinputvoltage
range and has a user configurable operating frequency
up to 4MHz, allowing the use of tiny, low cost capacitors
and inductors 2mm or less in height. The output voltage
is adjustable from 0.8V to 5V. Internal sychronous 0.11Ω
power switches with 1.6A peak current ratings provide
high efficiency. The LTC3411’s current mode architecture
and external compensation allow the transient response
to be optimized over a wide range of loads and output
capacitors.
n
Small 10-Lead MSOP or DFN Package
n
Uses Tiny Capacitors and Inductor
n
High Frequency Operation: Up to 4MHz
High Switch Current: 1.6A
n
n
Low R
Internal Switches: 0.110Ω
DS(ON)
n
n
n
High Efficiency: Up to 95%
Stable with Ceramic Capacitors
Current Mode Operation for Excellent Line
and Load Transient Response
n
n
n
n
n
n
n
Short-Circuit Protected
Low Dropout Operation: 100% Duty Cycle
Low Shutdown Current: I ≤ 1μA
Q
Low Quiescent Current: 60μA
Output Voltages from 0.8V to 5V
Selectable Burst Mode® Operation
Synchronizable to External Clock
The LTC3411 can be configured for automatic power sav-
ing Burst Mode operation to reduce gate charge losses
when the load current drops below the level required for
continuous operation. For reduced noise and RF interfer-
ence,theSYNC/MODEpincanbeconfiguredtoskippulses
or provide forced continuous operation.
APPLICATIONS
n
Notebook Computers
To further maximize battery life, the P-channel MOSFET
is turned on continuously in dropout (100% duty cycle)
with a low quiescent current of 60μA. In shutdown, the
device draws <1μA.
n
Digital Cameras
n
Cellular Phones
Handheld Instruments
Board Mounted Power Supplies
n
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
TYPICAL APPLICATION
V
IN
Efficiency vs Load Current
2.63V TO 5.5V
100
C1
22μF
95
90
V
SYNC/MODE
PGOOD
PV
IN
IN
IN
L1
SV
2.2μH
V
OUT
SW
2.5V/1.25A
LTC3411
C2
22μF
I
TH
887k
85
80
75
70
SHDN/R
V
FB
T
13k
1000pF
SGND
PGND
324k
412k
V
V
O
= 3.3V
= 2.5V
= 1MHz
IN
OUT
f
NOTE: IN DROPOUT, THE OUTPUT TRACKS
THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)
3411 F01
Burst Mode OPERATION
1
10
100
1000
LOAD CURRENT (mA)
3411 TA01
Figure 1. Step-Down 2.5V/1.25A Regulator
3411fb
1
LTC3411
ABSOLUTE MAXIMUM RATINGS (Note 1)
PV , SV Voltages ..................................... –0.3V to 6V
Junction Temperature (Notes 5, 8) ....................... 125°C
IN
IN
V , I , SHDN/R Voltages ..........–0.3V to (V + 0.3V)
Storage Temperature Range
FB TH
T
IN
SYNC/MODE Voltage .....................–0.3V to (V + 0.3V)
DD Package ....................................... –65°C to 125°C
MS Package...................................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
IN
SW Voltage ..................................–0.3V to (V + 0.3V)
IN
PGOOD Voltage ........................................... –0.3V to 6V
Operating Temperature Range (Note 2)
LTC3411E............................................. –40°C to 85°C
LTC3411I............................................ –40°C to 125°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
SHDN/R
1
2
3
4
5
10
9
I
TH
T
SHDN/R
SYNC/MODE
SGND
1
2
3
4
5
10
9
I
TH
T
SYNC/MODE
SGND
V
FB
V
FB
8
PGOOD
8
PGOOD
SW
PGND
7
6
SV
SW
7
SV
IN
IN
PV
IN
PGND
6
PV
IN
MS PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
T
JMAX
= 125°C, θ = 120°C/W, θ = 45°C/W
JA JC
T
= 125°C, θ = 43°C/W, θ = 8°C/W
JA JC
JMAX
(EXPOSED PAD MUST BE SOLDERED TO SGND)
ORDER INFORMATION
LEAD FREE FINISH
LTC3411EDD#PBF
LTC3411IDD#PBF
LTC3411EMS#PBF
LTC3411IMS#PBF
LEAD BASED FINISH
LTC3411EDD
TAPE AND REEL
PART MARKING*
LADT
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC3411EDD#TRPBF
LTC3411IDD#TRPBF
LTC3411EMS#TRPBF
LTC3411IMS#TRPBF
TAPE AND REEL
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LADT
–40°C to 125°C
–40°C to 85°C
LTQT
LTQT
10-Lead Plastic MSOP
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 85°C
PART MARKING*
LADT
PACKAGE DESCRIPTION
LTC3411EDD#TR
LTC3411IDD#TR
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LTC3411IDD
LADT
–40°C to 125°C
–40°C to 85°C
LTC3411EMS
LTC3411EMS#TR
LTC3411IMS#TR
LTQT
LTC3411IMS
LTQT
10-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3411fb
2
LTC3411
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, RT = 324k unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
V
V
Operating Voltage Range
Feedback Pin Input Current
Feedback Voltage
2.625
IN
I
FB
0.1
μA
l
V
(Note 3)
0.784
0.8
0.816
0.2
V
FB
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
IN
= 2.7V to 5V
0.04
%/V
ΔV
ΔV
LINEREG
l
l
I
= 0.36, (Note 3)
= 0.84, (Note 3)
0.02
–0.02
0.2
–0.2
%
%
TH
TH
LOADREG
I
I
g
Error Amplifier Transconductance
Pin Load = 5μA (Note 3)
800
μS
m(EA)
TH
I
Input DC Supply Current (Note 4)
Active Mode
S
V
V
V
= 0.75V, SYNC/MODE = 3.3V
240
62
0.1
350
100
1
μA
μA
μA
FB
Sleep Mode
= 3.3V, V = 1V
FB
SYNC/MODE
Shutdown
= 3.3V
SHDN/RT
V
Shutdown Threshold High
Active Oscillator Resistor
V
IN
– 0.6
V – 0.4
IN
1M
V
Ω
SHDN/RT
324k
f
Oscillator Frequency
R = 324k
0.85
1
1.15
4
MHz
MHz
OSC
T
(Note 7)
f
I
Synchronization Frequency
Peak Switch Current Limit
(Note 7)
0.4
1.6
4
MHz
A
SYNC
I
TH
= 1.3
2
LIM
R
Top Switch On-Resistance (Note 6)
Bottom Switch On-Resistance (Note 6)
Switch Leakage Current
V
V
V
V
= 3.3V
= 3.3V
= 6V, V
0.11
0.11
0.01
2.5
0.15
0.15
1
Ω
DS(ON)
IN
IN
IN
IN
Ω
I
= 0V, V = 0V
μA
V
SW(LKG)
ITH/RUN
FB
V
Undervoltage Lockout Threshold
Power Good Threshold
Ramping Down
2.375
2.625
UVLO
PGOOD
V
FB
V
FB
Ramping Up, SHDN/R = 1V
Ramping Down, SHDN/R = 1V
6.8
–7.6
%
%
T
T
R
PGOOD
Power Good Pull-Down On-Resistance
118
200
Ω
Note 5: T is calculated from the ambient T and power dissipation P
according to the following formula:
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
J
A
D
LTC3411DD: T = T + (P • 43°C/W)
J
A
D
LTC3411MS: T = T + (P • 120°C/W)
J
A
D
Note 2: The LTC3411E is guaranteed to meet specified performance from
0°C to 85°C. Specifications over the –40°C to 85°C operating termperature
range are assured by design, characterization and correlation with
statistical process controls. The LTC3411I is guaranteed to meet specified
performance over the full –40°C to 125°C operating temperature range.
Note 6: Switch on-resistance is guaranteed by correlation to wafer level
measurements.
Note 7: 4MHz operation is guaranteed by design but not production tested
and is subject to duty cycle limitations (see Applications Information).
Note 8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: The LTC3411 is tested in a feedback loop which servos V to the
FB
midpoint for the error amplifier (V = 0.6V).
ITH
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
3411fb
3
LTC3411
PIN FUNCTIONS
PGND (Pin 5): Main Power Ground Pin. Connect to the
SHDN/R (Pin 1): Combination Shutdown and Timing
T
(–) terminal of C , and (–) terminal of C .
Resistor Pin. The oscillator frequency is programmed by
OUT
IN
connecting a resistor from this pin to ground. Forcing
PV (Pin 6): Main Supply Pin. Must be closely decoupled
IN
this pin to SV causes the device to be shut down. In
IN
to PGND.
shutdown all functions are disabled.
SV (Pin 7): The Signal Power Pin. All active circuitry
IN
SYNC/MODE (Pin 2): Combination Mode Selection and
is powered from this pin. Must be closely decoupled to
Oscillator Synchronization Pin. This pin controls the op-
SGND. SV must be greater than or equal to PV .
IN
IN
eration of the device. When tied to SV or SGND, Burst
IN
PGOOD (Pin 8): The Power Good Pin. This common drain
logic output is pulled to SGND when the output voltage is
not within 7.5% of regulation.
Mode operation or pulse skipping mode is selected,
respectively. If this pin is held at half of SV , the forced
IN
continuous mode is selected. The oscillation frequency
can be syncronized to an external oscillator applied to
this pin. When synchronized to an external clock pulse
skip mode is selected.
V
(Pin 9): Receives the feedback voltage from the ex-
FB
ternal resistive divider across the output. Nominal voltage
for this pin is 0.8V.
SGND (Pin 3): The Signal Ground Pin. All small signal
components and compensation components should be
connected to this ground (see Board Layout Consider-
ations).
I
(Pin 10): Error Amplifier Compensation Point. The
TH
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.5V.
SW (Pin 4): The Switch Node Connection to the Inductor.
This pin swings from PV to PGND.
IN
3411fb
4
LTC3411
PIN FUNCTIONS
NOMINAL (V)
ABSOLUTE MAX (V)
PIN
1
NAME
SHDN/R
DESCRIPTION
MIN
–0.3
0
TYP
MAX
MIN
–0.3
–0.3
MAX
SV + 0.3
Shutdown/Timing Resistor
0.8
SV
IN
SV
IN
T
IN
2
SYNC/MODE Mode Select/Sychronization Pin
SV + 0.3
IN
3
SGND
SW
Signal Ground
0
0
4
Switch Node
0
PV
–0.3
PV + 0.3
IN
IN
5
PGND
Main Power Ground
Main Power Supply
Signal Power Supply
Power Good Pin
6
PV
IN
SV
IN
–0.3
2.5
0
5.5
5.5
SV
–0.3
–0.3
–0.3
–0.3
–0.3
SV + 0.3
IN
7
6
6
8
PGOOD
IN
9
V
Output Feedback Pin
Error Amplifier Compensation and Run Pin
0
0.8
1.0
1.5
SV + 0.3
IN
FB
10
I
0
SV + 0.3
IN
TH
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Operation
Pulse Skipping Mode
Forced Continuous Mode
V
V
OUT
OUT
V
OUT
10mV/DIV
10mV/DIV
10mV/DIV
I
I
L1
L1
I
L1
100mA/DIV
100mA/DIV
100mA/DIV
3411 G01
3411 G02
3411 G03
V
V
LOAD
= 3.3V
V
V
LOAD
= 3.3V
V
V
LOAD
= 3.3V
IN
2μs/DIV
2μs/DIV
2μs/DIV
IN
IN
= 2.5V
= 2.5V
= 2.5V
OUT
OUT
OUT
I
= 50mA
I
= 50mA
I
= 50mA
CIRCUIT OF FIGURE 7
CIRCUIT OF FIGURE 7
CIRCUIT OF FIGURE 7
Efficiency vs Load Current
Efficiency vs VIN
Load Step
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
I
= 400mA
Burst Mode
OPERATION
OUT
V
OUT
100mV/DIV
I
= 1.25A
OUT
PULSE SKIP
FORCED CONTINUOUS
I
L1
0.5A/DIV
3411 G06
V
V
= 3.3V
IN
OUT
V
V
= 3.3V
40μs/DIV
IN
V
= 2.5V
= 2.5V
OUT
= 2.5V
OUT
CIRCUIT OF FIGURE 7
CIRCUIT OF FIGURE 7
100 1000 10000
LOAD CURRENT (mA)
I
= 0.25A TO 1.25A
LOAD
CIRCUIT OF FIGURE 7
1
10
2.5
3.5
4.5
(V)
5.5
V
IN
3411 G04
3411 G05
3411fb
5
LTC3411
TYPICAL PERFORMANCE CHARACTERISTICS
Load Regulation
Line Regulation
Frequency vs VIN
10
8
0.4
0.3
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
I
A
= 1.8V
V
V
= 3.3V
V
T
= 1.8V
OUT
OUT
IN
OUT
OUT
A
= 1.25A
= 2.5V
= 25°C
Burst Mode
OPERATION
T
= 25°C
6
0.2
4
PULSE SKIP
0.1
2
0
FORCED
CONTINUOUS
0
–0.1
–0.2
–0.3
–0.4
–0.5
–2
–4
–6
–8
–10
I
= 1.25A
OUT
I
= 400mA
5
OUT
2
3
4
5
6
1
10
100
1000
10000
2
3
4
(V)
6
V
(V)
LOAD CURRENT (mA)
V
IN
IN
3411 G09
3411 G07
3411 G08
Frequency Variation
vs Temperature
Efficiency vs Frequency
RDS(ON) vs VIN
10
8
100
95
120
115
110
105
100
95
V
V
= 3.3V
T
= 25°C
IN
A
= 2.5V
OUT
OUT
I
= 500mA
6
T
= 25°C
A
4
SYNCHRONOUS SWITCH
2
0
–2
–4
–6
–8
–10
MAIN SWITCH
90
90
2.5
85
–50 –25
0
25
50
75 100 125
0
1
2
3
4
3
3.5
4
4.5
(V)
5
5.5
6
TEMPERATURE (°C)
FREQUENCY (MHz)
V
IN
3411 G10
3411 G12
3411 G11
3411fb
6
LTC3411
BLOCK DIAGRAM
SV
SGND
3
I
PV
IN
IN
TH
7
10
6
0.8V
PMOS CURRENT
COMPARATOR
VOLTAGE
REFERENCE
I
TH
LIMIT
BCLAMP
+
–
+
–
B
–
+
9
V
FB
ERROR
AMPLIFIER
V
B
BURST
COMPARATOR
+
–
0.74V
HYSTERESIS = 80mV
SLOPE
COMPENSATION
4
SW
OSCILLATOR
+
–
LOGIC
0.86V
+
PGOOD
8
–
NMOS
COMPARATOR
–
+
5
PGND
REVERSE
COMPARATOR
1
2
SYNC/MODE
SHDN/R
3411 BD
T
3411fb
7
LTC3411
OPERATION
The LTC3411 uses a constant frequency, current mode
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3411
automaticallyswitchesintoBurstModeoperationinwhich
the PMOS switch operates intermittently based on load
demand. By running cycles periodically, the switching
losses which are dominated by the gate charge losses of
the power MOSFETs are minimized. The main control loop
is interrupted when the output voltage reaches the desired
regulated value. The hysteretic voltage comparator B
architecture. The operating frequency is determined by
the value of the R resistor or can be synchronized to an
T
external oscillator. To suit a variety of applications, the
selectable Mode pin, allows the user to trade-off noise
for efficiency.
The output voltage is set by an external divider returned
to the V pin. An error amplfier compares the divided
FB
outputvoltagewithareferencevoltageof0.8Vandadjusts
the peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the PGOOD output
low if the output voltage is not within 7.5%.
trips when I is below 0.24V, shutting off the switch and
TH
reducing the power. The output capacitor and the inductor
supply the power to the load until I /RUN exceeds 0.31V,
TH
turning on the switch and the main control loop which
starts another cycle.
Main Control Loop
For lower output voltage ripple at low currents, pulse
skipping mode can be used. In this mode, the LTC3411
continues to switch at a constant frequency down to
very low currents, where it will eventually begin skipping
pulses.
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET)isturnedonatthebeginningofaclockcyclewhen
the V voltage is below the reference voltage. The current
FB
into the inductor and the load increases until the current
limit is reached. The switch turns off and energy stored in
the inductor flows through the bottom switch (N-channel
MOSFET) into the load until the next clock cycle.
Finally, in forced continuous mode, the inductor current
is constantly cycled which creates a fixed output voltage
ripple at all output current levels. This feature is desirable
in telecommunications since the noise is at a constant
frequency and is thus easy to filter out. Another advan-
tage of this mode is that the regulator is capable of both
sourcing current into a load and sinking some current
from the output.
The peak inductor current is controlled by the voltage
on the I pin, which is the output of the error amplifier.
TH
This amplifier compares the V pin to the 0.8V reference.
FB
Whentheloadcurrentincreases,theV voltagedecreases
FB
slightly below the reference. This decrease causes the
error amplifier to increase the I voltage until the average
TH
inductor current matches the new load current.
Dropout Operation
ThemaincontrolloopisshutdownbypullingtheSHDN/R
T
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which
is the dropout condition. In dropout, the PMOS switch is
turnedoncontinuouslywiththeoutputvoltagebeingequal
to the input voltage minus the voltage drops across the
internal P-channel MOSFET and the inductor.
pin to SV . A digital soft-start is enabled after shutdown,
IN
which will slowly ramp the peak inductor current up over
1024 clock cycles or until the output reaches regulation,
whicheverisfirst.Soft-startcanbelengthenedbyramping
the voltage on the I pin (see Applications Information
TH
section).
Low Supply Operation
Low Current Operation
TheLTC3411incorporatesanundervoltagelockoutcircuit
which shuts down the part when the input voltage drops
below about 2.5V to prevent unstable operation.
Three modes are available to control the operation of the
LTC3411 at low currents. All three modes automatically
switch from continuous operation to the selected mode
when the load current is low.
3411fb
8
LTC3411
APPLICATIONS INFORMATION
AgeneralLTC3411applicationcircuitisshowninFigure 5.
Externalcomponentselectionisdrivenbytheloadrequire-
ment, and begins with the selection of the inductor L1.
The minimum frequency is limited by leakage and noise
coupling due to the large resistance of R .
T
Inductor Selection
Once L1 is chosen, C and C
can be selected.
IN
OUT
Although the inductor does not influence the operat-
ing frequency, the inductor value has a direct effect on
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
ripple current. The inductor ripple current ΔI decreases
L
with higher inductance and increases with higher V or
IN
V
OUT
:
⎛
⎞
VOUT
fO•L
VOUT
VIN
ΔIL =
• 1−
⎜
⎟
⎠
⎝
Accepting larger values of ΔI allows the use of low induc-
L
The operating frequency, f , of the LTC3411 is determined
by an external resistor that is connected between the R
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timingcapacitorwithintheoscillatorandcanbecalculated
by using the following equation:
O
tances, but results in higher output voltage ripple, greater
T
core losses, and lower output current capability.
Areasonablestartingpointforsettingripplecurrentis40%
ofmaximumoutputcurrent, orΔI = 0.4• 1.25A = 500mA.
L
ThelargestripplecurrentΔI occursatthemaximuminput
L
voltage. To guarantee that the ripple current stays below a
specified maximum, the inductor value should be chosen
according to the following equation:
−1.08
RT = 9.78•1011
( O)
f
Ω
( )
or can be selected using Figure 2.
⎛
⎞
VOUT
fO• ΔIL
VOUT
VIN(MAX)
L =
• 1−
The maximum usable operating frequency is limited by
the minimum on-time and the duty cycle. This can be
calculated as:
⎜
⎟
⎝
⎠
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
f
≈ 6.67 • (V
/ V ) (MHz)
IN(MAX)
O(MAX)
OUT
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
T
= 25°C
A
0
0
500
1500
1000
R
(kΩ)
T
3411 F02
Figure 2. Frequency vs RT
3411fb
9
LTC3411
APPLICATIONS INFORMATION
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
Catch Diode Selection
Although unnecessary in most applications, a small
improvement in efficiency can be obtained in a few ap-
plications by including the optional diode D1 shown in
Figure 5, which conducts when the synchronous switch is
off. WhenusingBurstModeoperationorpulseskipmode,
the synchronous switch is turned off at a low current and
the remaining current will be carried by the optional diode.
It is important to adequately specify the diode peak cur-
rent and average power dissipation so as not to exceed
the diode ratings. The main problem with Schottky diodes
is that their parasitic capacitance reduces the efficiency,
usuallynegatingthepossiblebenefitsforLTC3411circuits.
Another problem that a Schottky diode can introduce is
higher leakage current at high temperatures, which could
reduce the low current efficiency.
Inductor Core Selection
Different core materials and shapes will change the
size/current and price/current relationship of an induc-
tor. Toroid or shielded pot cores in ferrite or permalloy
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar electrical characteristics. The choice of which
style inductor to use often depends more on the price vs
sizerequirementsandanyradiatedfield/EMIrequirements
than on what the LTC3411 requires to operate. Table 1
shows some typical surface mount inductors that work
well in LTC3411 applications.
Remember to keep lead lengths short and observe proper
grounding(seeBoardLayoutConsiderations)toavoidring-
ing and increased dissipation when using a catch diode.
Table 1. Representative Surface Mount Inductors
MANU-
FACTURER PART NUMBER
MAX DC
VALUE CURRENT DCR HEIGHT
Input Capacitor (C ) Selection
IN
Toko
A914BYW-2R2M-D52LC 2.2μH 2.05A 49mΩ 2mm
In continuous mode, the input current of the converter is a
square wave with a duty cycle of approximately V /V .
Topreventlargevoltagetransients, alowequivalentseries
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
Toko
A915AY-2ROM-D53LC
D01608C-222
2μH
3.3A
2.3A
22mΩ 3mm
70mΩ 3mm
OUT IN
Coilcraft
Coilcraft
Sumida
Sumida
2.2μH
2.2μH
LP01704-222M
CDRH4D282R2
CDC5D232R2
2.4A 120mΩ 1mm
2.2μH 2.04A 23mΩ 3mm
2.2μH 2.16A 30mΩ 2.5mm
Taiyo Yuden N06DB2R2M
Taiyo Yuden N05DB2R2M
2.2μH
2.2μH
2.2μH
3.2A
2.9A
3.2A
29mΩ 3.2mm
32mΩ 2.8mm
24mΩ 5mm
VOUT (V − VOUT
)
IN
IRMS ≈ IMAX
Murata
LQN6C2R2M04
V
IN
3411fb
10
LTC3411
APPLICATIONS INFORMATION
where the maximum average output current I
equals
Once the ESR requirements for C
have been met, the
MAX
OUT
the peak current minus half the peak-to-peak ripple cur-
rent, I = I – ΔI /2.
RMS current rating generally far exceeds the I
RIPPLE(P-P)
requirement, except for an all ceramic solution.
MAX
LIM
L
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst case is commonly used
to design because even significant deviations do not offer
muchrelief.Notethatcapacitormanufacturer’sripplecur-
rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet the size or height requirements of the design. An
additional 0.1μF to 1μF ceramic capacitor is also recom-
mended on VIN for high frequency decoupling, when not
using an all ceramic capacitor solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
currenthandlingrequirementoftheapplication.Aluminum
electrolytic, special polymer, ceramic and dry tantulum
capacitors are all available in surface mount packages.
The OS-CON semiconductor dielectric capacitor avail-
able from Sanyo has the lowest ESR(size) product of any
aluminum electrolytic at a somewhat higher price. Special
polymer capacitors, such as Sanyo POSCAP, offer very
low ESR, but have a lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
density, but it has a larger ESR and it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surfacemounttantalums,avalableincaseheightsranging
from2mmto4mm.Aluminumelectrolyticcapacitorshave
a significantly larger ESR, and is often used in extremely
cost-sensitive applications provided that consideration
is given to ripple current ratings and long term reliability.
Ceramic capacitors have the lowest ESR and cost but also
have the lowest capacitance density, a high voltage and
temperature coefficient and exhibit audible piezoelectric
effects. In addition, the high Q of ceramic capacitors along
withtraceinductancecanleadtosignificant ringing. Other
capacitor types include the Panasonic specialty polymer
(SP) capacitors.
Output Capacitor (C ) Selection
OUT
The selection of C
is driven by the required ESR to
OUT
minimizevoltagerippleandloadsteptransients. Typically,
once the ESR requirement is satisfied, the capacitance
is adequate for filtering. The output ripple (ΔV ) is
OUT
determined by:
⎛
⎞
1
ΔVOUT ≈ ΔIL ESR +
⎜
⎟
8fOCOUT
⎝
⎠
where f = operating frequency, C
= output capacitance
OUT
and ΔI = ripple current in the inductor. The output ripple
L
is highest at maximum input voltage since ΔI increases
L
with input voltage. With ΔI = 0.3 • I the output ripple
L
LIM
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3411 in parallel with the
main capacitors for high frequency decoupling.
will be less than 100mV at maximum V and f = 1MHz
IN
O
with:
ESRC
< 150mΩ
OUT
3411fb
11
LTC3411
APPLICATIONS INFORMATION
Ceramic Input and Output Capacitors
cycles are required to respond to a load step, but only in
the first cycle does the output drop linearly. The output
Higher value, lower cost ceramic capacitors are now be-
comingavailableinsmallercasesizes. Thesearetempting
for switching regulator use because of their very low ESR.
Unfortunately, the ESR is so low that it can cause loop
stabilityproblems.SolidtantalumcapacitorESRgenerates
aloop“zero”at5kHzto50kHzthatisinstrumentalingiving
acceptableloopphasemargin. Ceramiccapacitorsremain
capacitive to beyond 300kHz and ususally resonate with
their ESL before ESR becomes effective. Also, ceramic
caps are prone to temperature effects which requires the
designer to check loop stability over the operating tem-
perature range. To minimize their large temperature and
voltage coefficients, only X5R or X7R ceramic capacitors
should be used. A good selection of ceramic capacitors
is available from Taiyo Yuden, TDK and Murata.
droop, V
, is usually about 2 to 3 times the linear
DROOP
drop of the first cycle. Thus, a good place to start is with
the output capacitor size of approximately:
ΔIOUT
COUT ≈ 2.5
fO •VDROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
Inmostapplications,theinputcapacitorismerelyrequired
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Setting the Output Voltage
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, suchasfromawalladapter, aloadstepattheoutput
The LTC3411 develops a 0.8V reference voltage between
the feedback pin, V , and the signal ground as shown in
FB
Figure 5. The output voltage is set by a resistive divider
according to the following formula:
can induce ringing at the V pin. At best, this ringing can
IN
R2
R1
⎛
⎝
⎞
⎟
⎠
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
VOUT ≈ 0.8V 1+
⎜
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation com-
ponents and the output capacitor size. Typically, 3 to 4
Toimprovethefrequencyresponse,afeed-forwardcapaci-
tor C may also be used. Great care should be taken to
F
route the V line away from noise sources, such as the
FB
inductor or the SW line.
3411fb
12
LTC3411
APPLICATIONS INFORMATION
Shutdown and Soft-Start
of low current efficiency. Applying a voltage between 1V
and SV – 1, results in forced continuous mode, which
IN
The SHDN/R pin is a dual purpose pin that sets the oscil-
T
creates a fixed output ripple and is capable of sinking
lator frequency and provides a means to shut down the
LTC3411. This pin can be interfaced with control logic in
several ways, as shown in Figure 3(a) and Figure 3(b).
some current (about 1/2ΔI ). Since the switching noise is
L
constant in this mode, it is also the easiest to filter out. In
manycases,theoutputvoltagecanbesimplyconnectedto
the SYNC/MODE pin, giving the forced continuous mode,
except at startup.
The I pin is primarily for loop compensation, but it can
TH
also be used to increase the soft-start time. Soft start
reduces surge currents from V by gradually increasing
IN
TheLTC3411canalsobesynchronizedtoanexternalclock
signal by the SYNC/MODE pin. The internal oscillator fre-
quency should be set to 20% lower than the external clock
frequency to ensure adequate slope compensation, since
slope compensation is derived from the internal oscillator.
During synchronization, the mode is set to pulse skipping
and the top switch turn on is synchronized to the rising
edge of the external clock.
the peak inductor current. Power supply sequencing can
also be accomplished using this pin. The LTC3411 has an
internal digital soft-start which steps up a clamp on I
over 1024 clock cycles, as can be seen in Figure 4.
TH
The soft-start time can be increased by ramping the volt-
age on I during start-up as shown in Figure 3(c). As
TH
the voltage on I ramps through its operating range the
TH
internal peak current limit is also ramped at a proportional
Checking Transient Response
linear rate.
The OPTI-LOOP compensation allows the transient re-
sponse to be optimized for a wide range of loads and
Mode Selection and Frequency Synchronization
TheSYNC/MODEpinisamultipurposepinwhichprovides
mode selection and frequency synchronization. Connect-
output capacitors. The availability of the I pin not only
TH
allows optimization of the control loop behavior but also
providesaDCcoupledandACfilteredclosedloopresponse
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantlysecondordersystem,phasemarginand/or
damping factor can be estimated using the percentage of
ing this pin to V enables Burst Mode operation, which
IN
provides the best low current efficiency at the cost of a
higheroutputvoltageripple. Whenthispinisconnectedto
ground,pulseskippingoperationisselectedwhichprovides
the lowest output voltage and current ripple at the cost
SHDN/R
SHDN/R
SV
IN
T
T
T
T
R
R
1M
V
IN
RUN
2V/DIV
RUN
3411 F03a
V
3411 F03b
OUT
2V/DIV
(3a)
(3b)
RUN OR V
I
I
L1
IN
TH
500mA/DIV
3411 F04
R1
R
C
V
V
R
= 3.3V
= 2.5V
= 1.4Ω
200μs/DIV
IN
OUT
L
D1
C1
C
C
Figure 4. Digital Soft-Start
3411 F03c
(3c)
Figure 3. SHDN/RT Pin Interfacing and External Soft-Start
3411fb
13
LTC3411
APPLICATIONS INFORMATION
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capacitor
The I external components shown in the Figure 1 circuit
TH
will provide an adequate starting point for most applica-
tions. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedbackfactorgainandphase. Anoutputcurrentpulseof
20% to 100% of full load current having a rise time of 1μs
C can be added to improve the high frequency response,
F
as shown in Figure 5. Capacitor C provides phase lead by
F
creating a high frequency zero with R2 which improves
the phase margin.
to10μswillproduceoutputvoltageandI pinwaveforms
Theoutputvoltagesettlingbehaviorisrelatedtothestability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
TH
that will give a sense of the overall loop stability without
breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
im-
OUT
•ESR,where
mediatelyshiftsbyanamountequaltoΔI
LOAD
ESR is the effective series resistance of C . ΔI
also
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
OUT
LOAD
begins to charge or discharge C
generating a feedback
OUT
error signal used by the regulator to return V
to its
can
inputvoltageV dropstowardV ,theloadstepcapability
OUT
IN OUT
steady-state value. During this recovery time, V
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta or single inductor, positive buck/boost.
OUT
be monitored for overshoot or ringing that would indicate
a stability problem.
V
IN
2.5V
+
TO 5.5V
R5
R6
C6
C
IN
SV
PV
PGOOD
SW
PGOOD
IN
IN
C8
V
OUT
PGND
PGND
L1
D1
C
+
LTC3411
SYNC/MODE
F
SGND
OPTIONAL
C
C5
OUT
I
V
FB
TH
PGND
PGND
R2
R
SGND PGND SHDN/R
C
T
R1
C
SGND
ITH
R
T
C
C
SGND
SGND
GND
SGND SGND
3411 F05
Figure 5. LTC3411 General Schematic
3411fb
14
LTC3411
APPLICATIONS INFORMATION
Insomeapplications,amoreseveretransientcanbecaused
by switching in loads with large (>1uF) input capacitors.
Thedischargedinputcapacitorsareeffectivelyputinparal-
lel with C , causing a rapid drop in V . No regulator
the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V
IN
and thus their effects will be more pronounced at higher
supply voltages.
OUT
OUT
can deliver enough current to prevent this problem, if the
switchconnectingtheloadhaslowresistanceandisdriven
quickly.Thesolutionistolimittheturn-onspeedoftheload
switchdriver.Ahotswapcontrollerisdesignedspecifically
for this purpose and usually incorporates current limiting,
short-circuit protection, and soft-starting.
2
3) I R Losses are calculated from the DC resistances of
the internal switches, R , and external inductor, RL. In
SW
continuous mode, the average output current flowing
through inductor L is “chopped” between the internal top
and bottom switches. Thus, the series resistance look-
ing into the SW pin is a function of both top and bottom
MOSFET R
and the duty cycle (DC) as follows:
DS(ON)
Efficiency Considerations
R
= (R
TOP)(DC) + (R
BOT)(1 – DC)
DS(ON)
SW
DS(ON)
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
The R
for both the top and bottom MOSFETs can
DS(ON)
be obtained from the Typical Performance Characteristics
2
curves. Thus, to obtain I R losses:
2
2
I R losses = I
(R + RL)
SW
OUT
4)Other“hidden”lossessuchascoppertraceandinternal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
can be minimized by making sure that C has adequate
IN
chargestorageandverylowESRattheswitchingfrequency.
Other losses including diode conduction losses during
dead-time and inductor core losses generally account for
less than 2% total additional loss.
the losses in LTC3411 circuits: 1) LTC3411 V current,
IN
2
2) switching losses, 3) I R losses, 4) other losses.
1) The V current is the DC supply current given in the
IN
electrical characteristics which excludes MOSFET driver
andcontrolcurrents.V currentresultsinasmall(<0.1%)
Thermal Considerations
IN
loss that increases with V , even at no load.
IN
In a majority of applications, the LTC3411 does not dis-
sipate much heat due to its high efficiency. However, in
applicationswheretheLTC3411isrunningathighambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
fromswitchingthegatecapacitanceofthepowerMOSFETs.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from V to
IN
ground. The resulting dQ/dt is a current out of V that is
IN
typically much larger than the DC bias current. In continu-
ous mode, I
= f (QT + QB), where QT and QB are
GATECHG
O
3411fb
15
LTC3411
APPLICATIONS INFORMATION
To avoid the LTC3411 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
Design Example
As a design example, consider using the LTC3411 in a por-
tableapplicationwithaLi-Ionbattery.Thebatteryprovides
a V = 2.5V to 4.2V. The load requires a maximum of 1A
IN
in active mode and 10mA in standby mode. The output
voltage is V
= 2.5V. Since the load still needs power in
OUT
T
RISE
= P • θ
JA
standby, Burst Mode operation is selected for good low
D
load efficiency.
where P is the power dissipated by the regulator and θ
D
JA
is the thermal resistance from the junction of the die to
First, calculate the timing resistor:
the ambient temperature.
−1.08
R = 9.78•1011 1MHz
= 323.8k
(
)
T
The junction temperature, T , is given by:
J
Use a standard value of 324k. Next, calculate the inductor
value with 40% ripple current which is 500mA:
T = T
+ T
AMBIENT
J
RISE
As an example, consider the case when the LTC3411 is
in dropout at an input voltage of 3.3V with a load current
of 1A. From the Typical Performance Characteristics
⎛
⎞
2.5V
1MHz •500mA
2.5V
4.2V
L =
• 1−
= 2μH
⎜
⎝
⎟
⎠
graph of Switch Resistance, the R
resistance of the
DS(ON)
Choosing the closest inductor from a vendor of 2.2μH,
results in a maximum ripple current of:
P-channel switch is 0.11Ω. Therefore, power dissipated
by the part is:
2
P = I • R
= 110mW
2.5V
1MHz •2.2μ
2.5V
4.2V
⎛
⎝
⎞
⎟
⎠
D
DS(ON)
ΔIL =
• 1−
= 460mA
⎜
TheMS10packagejunction-to-ambientthermalresistance,
θ ,willbeintherangeof100°C/Wto120°C/W.Therefore,
JA
For cost reasons, a ceramic capacitor will be used. C
OUT
the junction temperature of the regulator operating in a
selection is then based on load step droop instead of ESR
70°C ambient temperature is approximately:
requirements. For a 5% output droop:
T = 0.11 • 120 + 70 = 83.2°C
J
1A
COUT ≈ 2.5
= 20μF
Remembering that the above junction temperature is
obtained from an R
the junction temperature based on a higher R
it increases with temperature. However, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
1MHz •(5%•2.5V)
at 25°C, we might recalculate
DS(ON)
since
The closest standard value is 22μF. Since the output
DS(ON)
impedance of a Li-Ion battery is very low, C is typically
IN
IN
10μF. In noisy environments, decoupling SV from PV
IN
with an R6/C8 filter of 1Ω/0.1μF may help, but is typically
not needed.
3411fb
16
LTC3411
APPLICATIONS INFORMATION
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2μA with the 0.8V feedback voltage makes R1~400k. A
close standard 1% resistor is 412k and R2 is then 887k.
1. Does the capacitor C connect to the power V (Pin 6)
IN IN
andpowerGND(Pin5)ascloseaspossible?Thiscapacitor
provides the AC current to the internal power MOSFETs
and their drivers.
2. Are the C
and L1 closely connected? The (–) plate of
OUT
The compensation should be optimized for these compo-
nentsbyexaminingtheloadstepresponsebutagoodplace
to start for the LTC3411 is with a 13kΩ and 1000pF filter.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
C
returns current to PGND and the (–) plate of C .
OUT IN
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
and a ground line terminated
OUT
near SGND (Pin 3). The feedback signal V should be
FB
routed away from noisy components and traces, such as
the SW line (Pin 4), and its trace should be minimized.
The PGOOD pin is a common drain output and requires
a pull-up resistor. A 100k resistor is used for adequate
speed.
4. Keep sensitive components away from the SW pin. The
input capacitor C , the compensation capacitor C and
IN
C
Figure 1 shows the complete schematic for this design
example.
C
and all the resistors R1, R2, R , and R should be
ITH T C
routed away from the SW trace and the inductor L1.
5. A ground plane is preferred, but if not available, keep
thesignalandpowergroundssegregatedwithsmallsignal
components returning to the SGND pin at one point which
is then connected to the PGND pin.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3411. These items are also illustrated graphically
in the layout diagram of Figure 6. Check the following in
your layout:
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
one of the input supplies: PV , PGND, SV or SGND.
IN
IN
C
IN
V
IN
C
OUT
V
PV
SV
PGND
SW
IN
IN
L1
OUT
R5
LTC3411
SGND
V
IN
PGOOD
PGOOD
V
SYNC/MODE
SHDN/R
FB
PS
BM
C4
R2
I
TH
T
R1
R3
R
T
C3
3411 F06
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 6. LTC3411 Layout Diagram (See Board Layout Checklist)
3411fb
17
LTC3411
TYPICAL APPLICATIONS
V
IN
2.63V TO
5.5V
C1
22μF
R5
100k
PGOOD
PGND
PV
IN
L1
SV
PGOOD
SW
IN
2.2μH
V
OUT
RS1
1M
1.8V/2.5V/3.3V
AT 1.25A
LTC3411
BM
PS
R2 887K
SYNC/MODE
V
FC
FB
I
SHDN/R
T
RS2
1M
TH
3.3V
2.5V
1.8V
C2
22μF
SGND
PGND
C4 22pF
R3
13k
R4
324k
R1A
280k
R1B
412k
R1C
698k
C3
1000pF
3411 F07a
SGND
SGND
GND
SGND
PGND
NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)
Figure 7. General Purpose Buck Regulator Using Ceramic Capacitors
Efficiency vs Load Current
100
Burst Mode
OPERATION (BM)
95
90
PULSE SKIP
(PS)
FORCED
85
80
75
70
65
60
CONTINUOUS (FC)
V
V
O
= 3.3V
= 2.5V
= 1MHz
IN
OUT
f
1
10
100
1000
10000
LOAD CURRENT (mA)
3411 F07b
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18
LTC3411
TYPICAL APPLICATIONS
Single Inductor, Positive, Buck-Boost Converter
C1
22μF
V
IN
2.63V
TO 5V
L1
3.3μH
D1
PV
SV
PGND
SW
IN
IN
V
OUT
3.3V/
100k
PGOOD
400mA
C2
22μF
s2
+
LTC3411
SGND
C4
47μF
M1
V
IN
PGOOD
V
SYNC/MODE
SHDN/R
FB
R1
280k
I
TH
T
R3
13k
R4
324k
R2
887k
C3
1000pF
C7
10pF
3411 TA02
C1, C2: TAIYO YUDEN JMK325BJ226MM
C4: SANYO POSCAP 6TPA47M
D1: ON MBRM120L
L1: TOKO A915AY-3R3M (D53LC SERIES)
M1: SILICONIX Si2302DS
Efficiency vs Load Current
85
80
75
70
65
60
55
f
= 1MHz
V
= 4V
IN
O
V
= 2.5V
IN
V
= 3V
IN
V
= 3.5V
IN
10
100
LOAD CURRENT (mA)
1000
3411 TA03
3411fb
19
LTC3411
TYPICAL APPLICATIONS
All Ceramic 2-Cell to 3.3V and 1.8V Converters
V
= 2V TO 3V
IN
L1
4.7μH
D1
V
OUT
3.3V
120mA/1A
C5
LTC3402
22μF
V
SW
OUT
IN
1M
SHDN
V
+
SV
PV
IN
IN
2
L2
CELLS
MODE/SYNC FB
SYNC/MODE
PGOOD
2.2μH
V
OUT
SW
1.8V/1.2A
LTC3411
604k
PGOOD
V
C
C2
C6
22μF
I
C1
TH
887k
1000pF
10pF
44mF
10μF
R
T
GND
SHDN/R
V
(2 s 22mF)
T
FB
13k
SGND
PGND
49.9k
47k
412k
324k
1000pF
3411 TA06
C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
C5, C6: TAIYO YUDEN JMK325BJ226MM
D1: ON SEMICONDUCTOR MBRM120LT3
L1: TOKO A916CY-4R7M
L2: TOKO A914BYW-2R2M (D52LC SERIES)
0 = FIXED FREQ
1 = Burst Mode OPERATION
Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
3.3V
1.8V
V
IN
= 2.4V
Burst Mode OPERATION
10
100
1000
10000
LOAD CURRENT (mA)
3211 TA07
3411fb
20
LTC3411
TYPICAL APPLICATION
2mm Height, 2MHz, Li-Ion to 1.8V Converter
V
IN
2.63V
R5
TO 4.2V
+
C6
1μF
C1
33μF
100k
PV
SV
PGOOD
SW
PGOOD
C4 22pF
IN
V
OUT
1.8V
IN
L1
1μH
AT 1.25A
+
LTC3411
SYNC/MODE
C2
33μF
C5
1μF
I
V
FB
TH
R2
887k
R1
698k
R3
15k
C3
470pF
C7
47pF
SGND PGND SHDN/R
T
R4
154k
3411 TA04
C1, C2: AVX TPSB336K006R0600
C4, C5: TAIYO YUDEN LMK212BJ105MG
L1: COILCRAFT DO1606T-102
Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
55
50
2.5V
3.6V
4.2V
V
O
= 1.8V
= 2MHz
OUT
f
1
10
100
1000
10000
LOAD CURRENT (mA)
3411 TA05
3411fb
21
LTC3411
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
6
0.38 p 0.10
10
0.675 p 0.05
3.50 p 0.05
2.15 p 0.05 (2 SIDES)
1.65 p 0.05
3.00 p 0.10 1.65 p 0.10
(4 SIDES)
(2 SIDES)
PIN 1
PACKAGE
OUTLINE
TOP MARK
(SEE NOTE 6)
(DD) DFN 1103
5
1
0.25 p 0.05
0.50 BSC
0.75 p 0.05
0.200 REF
0.25 p 0.05
0.50
BSC
2.38 p 0.10
(2 SIDES)
2.38 p 0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3411fb
22
LTC3411
PACKAGE DESCRIPTION
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 p 0.127
(.035 p .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 p 0.102
(.118 p .004)
(NOTE 3)
0.497 p 0.076
(.0196 p .003)
REF
0.50
0.305 p 0.038
(.0120 p .0015)
TYP
(.0197)
10 9
8
7 6
BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
GAUGE PLANE
1
2
3
4 5
0.53 p 0.152
(.021 p .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 p 0.0508
(.004 p .002)
0.50
(.0197)
BSC
MSOP (MS) 0307 REV E
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3411fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC3411
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
90% Efficiency, V : 3.6V to 25V, V
LT1616
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LTC1879
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95% Efficiency, V : 2.7V to 10V, V
IN
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Q
SD
LTC3405/LTC3405A
LTC3406/LTC3406B
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300mA (I ) 1.5MHz Synchronous Step-Down DC/DC Converters
95% Efficiency, V : 2.7V to 6V, V
: 0.8V,
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OUT(MIN)
I : 20μA, I : <1μA, ThinSOT
Q
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600mA (I ) 1.5MHz Synchronous Step-Down DC/DC Converters
95% Efficiency, V : 2.5V to 5.5V, V
: 0.6V,
OUT(MIN)
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I : 20μA, I : <1μA, ThinSOT
Q
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2.5A (I ) 4MHz Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
: 0.8V,
OUT(MIN)
OUT
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I : 60μA, I : <1μA, TSSOP16E
Q
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LTC3413
3A (I
Sink/Source) 2MHz Monolithic Synchronous Regulator for
90% Efficiency, V : 2.25V to 5.5V, V
Q SD
: V /2,
OUT
IN
OUT(MIN) REF
DDR/QDR Memory Termination
60V, 2.75A (I ) 200kHz High Efficiency Step-Down DC/DC Converter 90% Efficiency, V : 5.5V to 60V, V : 1.20V,
OUT(MIN)
I : 280μA, I : <1μA, TSSOP16E
LTC3430
OUT
IN
I : 2.5mA, I : 25μA, TSSOP16E
Q
SD
LTC3440
600mA (I ) 2MHz Synchronous Buck-Boost DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
: 2.5V,
OUT(MIN)
OUT
IN
I : 25μA, I : <1μA, 10-Lead MS
Q
SD
ThinSOT is a trademark of Linear Technology Corporation.
3411fb
LT 1108 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2002
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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