LTC3412AEFE-TR [Linear]
3A, 4MHz, Monolithic Synchronous Step-Down Regulator; 3A ，为4MHz ，单片同步降压型稳压器
| 型号： | LTC3412AEFE-TR |
| 厂家： | 
Linear |
| 描述： | 3A, 4MHz, Monolithic Synchronous Step-Down Regulator |
| 文件： | 总20页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3412A
3A, 4MHz, Monolithic
Synchronous Step-Down Regulator
U
DESCRIPTIO
FEATURES
The LTC®341±A is a high efficiency monolithic synchro-
nous, step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from
an input voltage range of ±.±5ꢁ to 5.5ꢁ and provides a
regulated output voltage from 0.8ꢁ to 5ꢁ while deliver-
ing up to 3A of output current. The internal synchronous
powerswitchwith77mΩon-resistanceincreasesefficiency
and eliminates the need for an external Schottky diode.
Switching frequency is set by an external resistor or can
be synchronized to an external clock. 1002 duty cycle
provides low dropout operation extending battery life in
portable systems. ꢀPTI-LꢀꢀP® compensation allows the
transient response to be optimized over a wide range of
loads and output capacitors.
■
High Efficiency: Up to 95%
■
3A Output Current
■
Low Quiescent Current: 64μA
■
Low R
Internal Switch: 77mΩ
DS(ON)
■
■
■
■
■
2.25V to 5.5V Input Voltage Range
Programmable Frequency: 300KHz to 4MHz
±±2 ꢀutput ꢁoltage Accuracy
0.8ꢁ Reference Allows Low ꢀutput ꢁoltage
Selectable Forced Continuous/Burst Mode® ꢀperation
with Adjustable Burst Clamp
Synchronizable Switching Frequency
Low Dropout ꢀperation: 1002 Duty Cycle
Power Good ꢀutput ꢁoltage Monitor
ꢀvertemperature Protected
■
■
■
■
■
Available in 16-Lead Exposed Pad TSSꢀP and
QFN Packages
The LTC341±A can be configured for either Burst Mode
operationorforcedcontinuousoperation.Forcedcontinu-
ous operation reduces noise and RF interference while
BurstModeoperationprovideshighefficiencybyreducing
gate charge losses at light loads. In Burst Mode operation,
external control of the burst clamp level allows the output
voltage ripple to be adjusted according to the application
requirements.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode and ꢀPTI-LꢀꢀP are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6580±58, 6304066, 61±7815, 6498466,
6611131, 67±4174.
U
APPLICATIO S
■
Point-of-Load Regulation
■
Notebook Computers
■
Portable Instruments
Distributed Power Systems
■
U
TYPICAL APPLICATIO
±±μF
ꢁ
Efficiency and Power Loss
IN
3.3ꢁ
100
95
90
85
80
75
70
65
60
55
50
100000
10000
1000
100
Pꢁ Sꢁ
IN
IN
EFFICIENCY
RT
±.±M
PGꢀꢀD
LTC341±A
0.47μH
±94k
ꢁ
ꢀUT
SW
±.5ꢁ AT 3A
ꢀUT
C
RUN/SS
PGND
100μF
×±
1±.1k
1000pF
I
TH
SGND
ꢁ
FB
SYNC/MꢀDE
PꢀWER LꢀSS
8±0pF
10
69.8k
39±k
115k
341±A F01a
1
0.01
0.1
1
10
LꢀAD CURRENT (A)
341±A F01b
Figure 1. 2.5V/3A Step-Down Regulator
3412afc
1
LTC3412A
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
Input Supply ꢁoltage....................................–0.3ꢁ to 6ꢁ
ꢀperating Ambient Temperature Range
I , RUN/SS, ꢁ , PGꢀꢀD,
(Note ±) ...............................................–40°C to 85°C
Junction Temperature (Note 5) ............................. 1±5°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
TH
FB
SYNC/MꢀDE ꢁoltages....................................–0.3 to ꢁ
IN
SW ꢁoltages ..................................–0.3ꢁ to (ꢁ + 0.3ꢁ)
IN
U
U
U
PI CO FIGURATIO
TꢀP ꢁIEW
TꢀP ꢁIEW
1
Pꢁ
IN
16
15
14
13
1±
11
10
9
Sꢁ
IN
±
SW
PGꢀꢀD
16 15 14 13
3
SW
I
TH
RUN/SS
SGND
1
±
3
4
1± PGꢀꢀD
4
PGND
PGND
SW
ꢁ
11 Sꢁ
IN
FB
17
17
5
Pꢁ
IN
Pꢁ
10
R
T
IN
SW
SW
9
6
SYNC/MꢀDE
5
6
7
8
7
SW
RUN/SS
8
Pꢁ
IN
SGND
FE PACKAGE
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
= 1±5°C, θ = 34°C/W, = 1°C/W
16-LEAD PLASTIC TSSꢀP
T
T
JMAX
= 1±5°C, θ = 38°C/W, θ = 10°C/W
JA JC
JMAX
JA
JC
EXPꢀSED PAD (PIN 17) IS SGND MUST BE SꢀLDERED Tꢀ PCB
EXPꢀSED PAD (PIN 17) IS GND, MUST BE CꢀNNECTED Tꢀ PCB
U
W
U
ORDER I FOR ATIO
LEAD FREE FINISH
LTC341±AEFE#PBF
LTC341±AIFE#PBF
LTC341±AEUF#PBF
LTC341±AIUF#PBF
LEAD BASED FINISH
LTC341±AEFE
TAPE AND REEL
PART MARKING*
341±AEFE
341±AIFE
341±A
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC341±AEFE#TRPBF
LTC341±AIFE#TRPBF
LTC341±AEUF#TRPBF
LTC341±AIUF#TRPBF
TAPE AND REEL
16-Lead Plastic TSSꢀP
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
TEMPERATURE RANGE
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
16-Lead Plastic TSSꢀP
16-Lead (4mm × 4mm) Plastic QFN
16-Lead (4mm × 4mm) Plastic QFN
PACKAGE DESCRIPTION
341±A
PART MARKING*
341±AEFE
341±AIFE
341±A
LTC341±AEFE#TR
LTC341±AIFE#TR
16-Lead Plastic TSSꢀP
LTC341±AIFE
16-Lead Plastic TSSꢀP
LTC341±AEUF
LTC341±AEUF#TR
LTC341±AIUF#TR
16-Lead (4mm × 4mm) Plastic QFN
16-Lead (4mm × 4mm) Plastic QFN
LTC341±AIUF
341±A
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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2
LTC3412A
The ● denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
±.±5
TYP
MAX
5.5
UNITS
ꢁ
Sꢁ
ꢁ
Signal Input ꢁoltage Range
Regulated Feedback ꢁoltage
ꢁoltage Feedback Leakage Current
Reference ꢁoltage Line Regulation
ꢀutput ꢁoltage Load Regulation
IN
(Note 3)
0.784
0.800
0.1
0.816
0.±
ꢁ
●
●
FB
I
μA
FB
Δꢁ
FB
ꢁ
IN
= ±.7ꢁ to 5.5ꢁ (Note 3)
0.04
0.±
2ꢁ
ꢁ
Measured in Servo Loop, ꢁ = 0.36ꢁ
Measured in Servo Loop, ꢁ = 0.84ꢁ
0.0±
0.±
2
2
●
●
LꢀADREG
ITH
ITH
–0.0±
–0.±
Δꢁ
Power Good Range
±7.5
1±0
±9
2
Ω
PGꢀꢀD
R
Power Good Pull-Down Resistance
±00
PGꢀꢀD
I
Q
Input DC Bias Current
Active Current
Sleep
(Note 4)
ꢁ
ꢁ
ꢁ
= 0.78ꢁ, ꢁ = 1ꢁ
±50
64
0.0±
330
80
1
μA
μA
μA
FB
FB
RUN
ITH
= 1ꢁ, ꢁ = 0ꢁ
ITH
Shutdown
= 0ꢁ, ꢁ
= 0ꢁ
MꢀDE
f
f
Switching Frequency
R
= ±94kΩ
0.88
0.3
1
1.1
4
MHz
MHz
ꢀSC
ꢀSC
Switching Frequency Range
(Note 6)
SYNC Capture Range
(Note 6)
0.3
4
MHz
mΩ
mΩ
A
SYNC
R
R
R
R
of P-Channel FET
of N-Channel FET
I
I
= 1A (Note 7)
77
65
6
110
90
PFET
NFET
DS(ꢀN)
DS(ꢀN)
SW
= –1A (Note 7)
SW
I
Peak Current Limit
4.5
LIMIT
ꢁ
Undervoltage Lockout Threshold
SW Leakage Current
RUN Threshold
1.75
±
±.±5
1
ꢁ
UꢁLꢀ
LSW
I
ꢁ
RUN
= 0ꢁ, ꢁ = 5.5ꢁ
0.1
0.65
μA
ꢁ
IN
ꢁ
0.5
0.8
1
RUN
RUN
I
RUN/SS Leakage Current
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LTC341±A is tested in a feedback loop that adjusts ꢁ to
FB
achieve a specified error amplifier output voltage (I ).
TH
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 2: The LTC341±AE is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC341±AI is guaranteed to
meet performance specifications over the full –40°C to 85°C operating
temperature range.
Note 5: T is calculated from the ambient temperature T and power
J
A
dissipation as follows: LTC341±AFE: T = T + P (38°C/W)
J
A
D
LTC341±AUF: T = T + P (34°C/W)
J
A
D
Note 6: 4MHz operation is guaranteed by design and not production tested.
Note 7: Switch on resistance is guaranteed by design and test condition in
the UF package and by final test correlation in the FE package.
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LTC3412A
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current, Burst
Efficiency vs Load Current,
Forced Continuous Operation
Efficiency vs Load Current
Mode Operation
100
90
80
70
60
50
40
30
±0
10
0
100
95
90
85
80
75
70
65
60
55
50
100
90
80
70
60
50
40
30
±0
10
0
ꢁ
IN
= 3.3ꢁ
ꢁ
IN
= 3.3ꢁ
Burst Mode
ꢀPERATIꢀN
ꢁ
IN
= 5ꢁ
ꢁ
= 5ꢁ
IN
FꢀRCED
CꢀNTINUꢀUS
ꢁ
ꢁ
= 3.3ꢁ
IN
ꢀUT
ꢁ
= ±.5ꢁ
ꢁ
= ±.5ꢁ
ꢀUT
= ±.5ꢁ
ꢀUT
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
0.01
0.1
1
10
0.01
0.1
1
10
0.01
0.1
1 10
LꢀAD CURRENT (A)
LꢀAD CURRENT (A)
LꢀAD CURRENT (A)
341±A Gꢀ1
341±A Gꢀ±
341±A Gꢀ3
Load Regulation
Efficiency vs Input Voltage
Efficiency vs Frequency
0
–0.1
–0.±
–0.3
–0.4
–0.5
–0.6
94
9±
90
88
86
84
8±
80
96
95
94
93
9±
91
90
89
88
87
FIGURE 4 CIRCUIT
= 3.3ꢁ
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
= 3.3ꢁ
ꢁ
IN
ꢁ
IN
1μH
0.±±μH
0.47μH
1A
0.1A
3A
3.0
3.5
INPUT ꢁꢀLTAGE (ꢁ)
4.5
5.0
0
0.5
1.0
1.5
±.0
±.5
3.0
±.5
4.0
0
0.5
1.5 ±.0 ±.5 3.0
FREQUENCY (MHz)
4.0
1.0
3.5
LꢀAD CURRENT (A)
341±A Gꢀ6
341±A Gꢀ4
341±A Gꢀ5
Load Step Transient Burst Mode
Operation
Burst Mode Operation
Output Voltage Ripple
BURST
MꢀDE
±0mꢁ/DIꢁ
ꢁ
ꢀUT
±0mꢁ/DIꢁ
ꢁ
ꢀUT
100mꢁ/DIꢁ
PULSE
SKIPPING
±0mꢁ/DIꢁ
INDUCTꢀR
CURRENT
1A/DIꢁ
FꢀRCED
CꢀNTINUꢀUS
±0mꢁ/DIꢁ
INDUCTꢀR
CURRENT
±A/DIꢁ
FIGURE 4 CIRCUIT
ꢁ
ꢁ
= 3.3ꢁ
ꢁ
ꢁ
= 3.3ꢁ
5μs/DIꢁ
5μs/DIꢁ
40μs/DIꢁ
IN
ꢀUT
IN
ꢀUT
= ±.5ꢁ
= ±.5ꢁ
FIGURE 4 CIRCUIT
F = 1MHz
341±A Gꢀ7
341±A Gꢀ8
341±A Gꢀ9
LꢀAD STEP = 50mA Tꢀ ±A
FIGURE 4 CIRCUIT
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4
LTC3412A
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Load Step Transient Forced
Continuous
Start-Up Transient
VREF vs Temperature
0.7975
0.7970
0.7965
0.7960
0.7955
0.7950
0.7945
0.7940
0.7935
0.7930
ꢁ
= 3.3ꢁ
IN
ꢁ
ꢀUT
±ꢁ/DIꢁ
ꢁ
ꢀUT
100mꢁ/DIꢁ
RUN/SS
±ꢁ/DIꢁ
INDUCTꢀR
CURRENT
±A/DIꢁ
INDUCTꢀR
CURRENT
±A/DIꢁ
115
–45 –±5
15 35 55
TEMPERATURE (°C)
95
ꢁ
ꢁ
= 3.3ꢁ
ꢀUT
F = 1MHz
40μs/DIꢁ
ꢁ
ꢁ
= 3.3ꢁ
1ms/DIꢁ
–5
75
IN
IN
=±.5ꢁ
=±.5ꢁ
ꢀUT
LꢀAD STEP = ±A
341±A G10
341±A G11
341±A G1±
LꢀAD STEP = 0A Tꢀ 3A
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
Switch Leakage Current vs
Input Voltage
Switch On-Resistance vs
Temperature
Switch On-Resistance vs
Input Voltage
50
100
95
90
85
80
75
70
65
60
55
50
1±0
100
80
60
40
±0
0
ꢁ
IN
= 3.3ꢁ
45
40
35
30
±5
±0
15
10
5
PFET
NFET
PFET
NFET
PFET
NFET
4.5 5.0
INPUT ꢁꢀLTAGE (ꢁ)
0
±.5
3.0
4.0
5.5
3.5
–40
40
TEMPERATURE (°C)
80 100
1±0
–±0
0
±0
60
±.5
3.0
3.5
4.0
4.5
5.0
INPUT ꢁꢀLTAGE (ꢁ)
341±A G15
341±A G14
341±A G13
Frequency vs ROSC
Frequency vs Input Voltage
Frequency vs Temperature
5000
4500
4000
3500
3000
±500
±000
1500
1000
500
1060
1050
1040
1030
10±0
1010
1000
990
10±0
1015
1010
1005
1000
995
ꢁ
= 3.3ꢁ
ꢀSC
ꢁ
IN
= 3.3ꢁ
R
ꢀSC
= ±94k
IN
R
= ±94k
990
985
980
975
0
970
±.5
3.0
3.5
4.0
4.5
5.0
5.5
40 140 ±40 340 440 540 640 740 840 940
(kΩ)
–40
40
TEMPERATURE (°C)
80 100
1±0
–±0
0
±0
60
INPUT ꢁꢀLTAGE (ꢁ)
R
ꢀSC
341±A G17
341±A G16
341±A G18
3412afc
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LTC3412A
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Quiescent Current vs
Temperature
Minimum Peak Inductor Current vs
Burst Clamp Voltage
Quiescent Current vs
Input Voltage
350
300
±50
±00
150
100
50
350
300
±50
±00
150
100
50
4000
3500
3000
±500
±000
1500
1000
500
ꢁ
IN
= 3.3ꢁ
ACTIꢁE
ACTIꢁE
SLEEP
80
SLEEP
0
0
0
0.6
–±0
0
±0 40 60
100 1±0
0.1
0.±
0.3
0.4
0.5
0.7
–40
±.5
3.5
4.0
4.5
5.0
5.5
3.0
ꢁ
(ꢁ)
INPUT ꢁꢀLTAGE (ꢁ)
TEMPERATURE (°C)
BURST
341±A G±1
341±A G±0
341±A G19
Peak Current vs Input Voltage
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
4.75
±.±5
±.75
3.±5
3.75
4.±5
INPUT ꢁꢀLTAGE (ꢁ)
341±A G±±
3412afc
6
LTC3412A
U
U
PI FU CTIO S
(FE Package/UHF Package)
RUN/SS (Pin 7/Pin 1): Run Control and Soft-Start Input.
Forcing this pin below 0.5ꢁ shuts down the LTC341±A.
In shutdown all functions are disabled drawing < 1μA of
supply current. A capacitor to ground from this pin sets
the ramp time to full output current.
SV (Pin 1/Pin 11): Signal Input Supply. Decouple this
IN
pin to SGND with a capacitor.
PGOOD (Pin 2/Pin 12): Power Good ꢀutput. ꢀpen-drain
logic output that is pulled to ground when the output volt-
age is not within ±7.52 of regulation point.
SGND (Pin 8/Pin 2): Signal Ground. All small-signal com-
ponents, compensationcomponentsandtheexposedpad
onthebottomsideoftheICshouldconnecttothisground,
which in turn connects to PGND at one point.
I
(Pin 3/Pin 13): Error Amplifier Compensation Point.
TH
The current comparator threshold increases with this
control voltage. Nominal voltage range for this pin is from
0.±ꢁ to 1.4ꢁ with 0.4ꢁ corresponding to the zero-sense
voltage (zero current).
PV (Pins9,16/Pins3,10):PowerInputSupply.Decouple
IN
this pin to PGND with a capacitor.
V
(Pin 4/Pin 14): Feedback Pin. Receives the feedback
FB
SW (Pins 10, 11, 14, 15/Pins 4, 5, 8, 9): Switch Node
ConnectiontotheInductor. Thispinconnectstothedrains
of the internal main and synchronous power MꢀSFET
switches.
voltage from a resistive divider connected across the
output.
R (Pin 5/Pin 15): ꢀscillator Resistor Input. Connecting
T
a resistor to ground from this pin sets the switching
frequency.
PGND (Pins 12, 13/Pins 6, 7): Power Ground. Connect
this pin close to the (–) terminal of C and C
.
ꢀUT
IN
SYNC/MODE (Pin 6/Pin 16): Mode Select and External
Exposed Pad (Pin 17/Pin 17): Signal Ground. Must be
solderedtoPCBforelectricalconnectionandratedthermal
performance.
Clock Synchronization Input. To select forced continuous,
tie to Sꢁ . Connecting this pin to a voltage between 0ꢁ
IN
and 1ꢁ selects Burst Mode operation with the burst clamp
set to the pin voltage.
3412afc
7
LTC3412A
U
U
W
FUNCTIONAL BLOCK DIAGRA
Pꢁ
IN
Sꢁ
SGND
8
I
TH
3
IN
1
9
16
SLꢀPE
CꢀMPENSATIꢀN
RECꢀꢁERY
PMꢀS CURRENT
CꢀMPARATꢀR
ꢁꢀLTAGE
REFERENCE
0.8ꢁ
BCLAMP
+
–
+
–
–
+
P-CH
4
ꢁ
FB
ERRꢀR
AMPLIFIER
BURST
CꢀMPARATꢀR
+
–
SYNC/MꢀDE
+
–
0.74ꢁ
10
SLꢀPE
11
14
15
CꢀMPENSATIꢀN
ꢀSCILLATꢀR
SW
+
–
N-CH
RUN/SS
PGꢀꢀD
7
±
RUN
0.86ꢁ
LꢀGIC
+
–
NMꢀS
CURRENT
CꢀMPARATꢀR
–
+
REꢁERSE
CURRENT
CꢀMPARATꢀR
1±
13
PGND
5
6
341± FBD
R
T
SYNC/MꢀDE
U
OPERATIO
Main Control Loop
comparing the feedback signal from a resistor divider on
the ꢁ pin with an internal 0.8ꢁ reference. When the load
FB
TheLTC341±Aisamonolithic,constant-frequency,current-
mode step-down DC/DC converter. During normal opera-
tion, the internal top power switch (P-channel MꢀSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MꢀSFET. The peak inductor
current at which the current comparator shuts off the top
current increases, it causes a reduction in the feedback
voltage relative to the reference. The error amplifier raises
the I voltage until the average inductor current matches
TH
the new load current. When the top power MꢀSFET shuts
off, the synchronous power switch (N-channel MꢀSFET)
turns on until either the bottom current limit is reached or
the beginning of the next clock cycle. The bottom current
limit is set at –1.3A for forced continuous mode and 0A
for Burst Mode operation.
power switch is controlled by the voltage on the I pin.
TH
The error amplifier adjusts the voltage on the I pin by
TH
3412afc
8
LTC3412A
U
OPERATIO
The operating frequency is externally set by an external
resistor connected between the RT pin and ground. The
practical switching frequency can range from 300kHz to
4MHz.
switched back on. This process repeats at a rate that is
dependent on the load demand.
Pulse Skipping operation is implemented by connecting
the SYNC/MꢀDE pin to ground. This forces the burst
clamp level to be at 0ꢁ. As the load current decreases, the
peak inductor current will be determined by the voltage
ꢀvervoltage and undervoltage comparators will pull the
PGꢀꢀD output low if the output voltage comes out of
regulation by ± 7.52. In an overvoltage condition, the top
powerMꢀSFETisturnedoffandthebottompowerMꢀSFET
isswitchedonuntileithertheovervoltageconditionclears
or the bottom MꢀSFET’s current limit is reached.
on the I pin until the I voltage drops below 400mꢁ. At
TH
TH
this point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
demand is less than the average of the minimum on-time
inductor current, switching cycles will be skipped to keep
the output voltage in regulation.
Forced Continuous Mode
Connecting the SYNC/MꢀDE pin to Sꢁ will disable Burst
IN
Frequency Synchronization
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficientthanBurstModeoperation,butmaybedesirablein
some applications where it is necessary to keep switching
harmonics out of a signal band. The output voltage ripple
is minimized in this mode.
The internal oscillator of the LTC341±A can be synchro-
nized to an external clock connected to the SYNC/MꢀDE
pin. The frequency of the external clock can be in the
range of 300kHz to 4MHz. For this application, the oscil-
lator timing resistor should be chosen to correspond to
a frequency that is ±52 lower than the synchronization
frequency. During synchronization, the burst clamp is set
to 0ꢁ, and each switching cycle begins at the falling edge
of the clock signal.
Burst Mode Operation
Connecting the SYNC/MꢀDE pin to a voltage in the range
of 0ꢁ to 1ꢁ enables Burst Mode operation. In Burst Mode
operation, the internal power MꢀSFETs operate intermit-
tently at light loads. This increases efficiency by minimiz-
ing switching losses. During Burst Mode operation, the
minimum peak inductor current is externally set by the
Dropout Operation
Whentheinputsupplyvoltagedecreasestowardtheoutput
voltage, the duty cycle increases toward the maximum
on-time. Further reduction of the supply voltage forces
the main switch to remain on for more than one cycle
eventually reaching 1002 duty cycle. The output voltage
will then be determined by the input voltage minus the
voltage drop across the internal P-channel MꢀSFET and
the inductor.
voltage on the SYNC/MꢀDE pin and the voltage on the I
TH
pin is monitored by the burst comparator to determine
when sleep mode is enabled and disabled. When the
average inductor current is greater than the load current,
the voltage on the I pin drops. As the I voltage falls
TH
TH
below 150mꢁ, the burst comparator trips and enables
sleep mode. During sleep mode, the top power MꢀSFET
is held off and the I pin is disconnected from the output
Low Supply Operation
TH
of the error amplifier. The majority of the internal circuitry
is also turned off to reduce the quiescent current to 64μA
while the load current is solely supplied by the output
The LTC341±A is designed to operate down to an input
supply voltage of ±.±5ꢁ. ꢀne important consideration
at low input supply voltages is that the R
of the
DS(ꢀN)
capacitor. When the output voltage drops, the I pin is
TH
P-channel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC341±A is used at 1002 duty cycle with low input volt-
ages to ensure that thermal limits are not exceeded.
reconnected to the output of the error amplifier and the
top power MꢀSFET along with all the internal circuitry is
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Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC341±A imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 110ns; therefore, the minimum duty cycle is
equal to 100 • 110ns • f(Hz).
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 502. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 402. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC341±A, however,
slope compensation recovery is implemented to keep the
maximum inductor peak current constant throughout the
range of duty cycles. This keeps the maximum output
current relatively constant regardless of duty cycle.
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔI increases with higher ꢁ or ꢁ
and
L
IN
ꢀUT
decreases with higher inductance.
ꢁ
OUT ꢄ ꢁ
OUT ꢄ
V
V
ꢀIL =
1–
ꢃ
ꢆ ꢃ
ꢆ
fL
V
ꢂ
ꢅ ꢂ
ꢅ
IN
Short-Circuit Protection
Having a lower ripple current reduces the core losses in
the inductor, the ESR losses in the output capacitors, and
the output voltage ripple. Highest efficiency operation is
achieved at low frequency with small ripple current. This,
however, requires a large inductor.
When the output is shorted to ground, the inductor cur-
rent decays very slowly during a single switching cycle.
To prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases larger than 4.4A, the top
power MꢀSFET will be held off and switching cycles will
be skipped until the inductor current is reduced.
A reasonable starting point for selecting the ripple current
is ΔI = 0.4(I
). The largest ripple current occurs at the
L
MAX
highest ꢁ . To guarantee that the ripple current stays
IN
The basic LTC341±A application circuit is shown in Fig-
ure 1. External component selection is determined by the
maximum load current and begins with the selection of
the operating frequency and inductor value followed by
below a specified maximum, the inductor value should
be chosen according to the following equation:
ꢁ
ꢄ ꢁ
ꢄ
VOUT
fꢀI
VOUT
L =
1–
ꢃ
ꢆ ꢃ
ꢆ
V
C and C
.
ꢂ
ꢅ ꢂ
ꢅ
IN
ꢀUT
L(MAX)
IN(MAX)
Operating Frequency
The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
when the peak inductor current falls below a level set by
the burst clamp. Lower inductor values result in higher
ripple current which causes this to occur at lower load
currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
ꢀperation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency of the LTC341±A is determined
by an external resistor that is connected between pin R
andground.Thevalueoftheresistorsetstherampcurrent
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation:
Inductor Core Selection
T
ꢀnce the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
3.08 •1011
ROSC
=
Ω –10kΩ
( )
f
will increase.
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APPLICATIO S I FOR ATIO
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Differentcorematerialsandshapeswillchangethesize/cur-
rent and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price verus size requirements and
any radiated field/EMI requirements. New designs for
surface mount inductors are available from Coiltronics,
Coilcraft, Toko, and Sumida.
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response as described in a later section.
The output ripple, Δꢁ , is determined by:
ꢀUT
ꢂ
ꢅ
ꢇ
1
ꢀVOUT ꢁ ꢀIL ESR+
ꢄ
8fC
ꢃ
OUT ꢆ
The output ripple is highest at maximum input voltage
since ΔI increases with input voltage. Multiple capacitors
L
placed in parallel may be needed to meet the ESR and
RMScurrenthandlingrequirements.Drytantalum,special
polymer,aluminumelectrolytic,andceramiccapacitorsare
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR, but can be used in cost-sensitive
applications provided that consideration is given to ripple
currentratingsandlongtermreliability.Ceramiccapacitors
have excellent low ESR characteristics but can have a high
voltage coefficient and audible piezoelectric effects. The
high Q of ceramic capacitors with trace inductance can
also lead to significant ringing.
C and C
Selection
IN
OUT
Theinputcapacitance,C ,isneededtofilterthetrapezoidal
IN
wave current at the source of the top MꢀSFET. To prevent
large voltage transients from occurring, a low ESR input
capacitor sized for the maximum RMS current should be
used. The maximum RMS current is given by:
VOUT
V
VOUT
IN
Using Ceramic Input and Output Capacitors
IRMS =IOUT(MAX)
–1
V
IN
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
thepowerissuppliedbyawalladapterthroughlongwires,
a load step at the output can induce ringing at the input,
This formula has a maximum at ꢁ = ±ꢁ , where
IN
ꢀUT
I
= I
. This simple worst-case condition is com-
RMS
ꢀUT/±
monlyusedfordesignbecauseevensignificantdeviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
±000 hours of life which makes it advisable to further
deratethecapacitor,orchooseacapacitorratedatahigher
temperature than required. Several capacitors may also
be paralleled to meet size or height requirements in the
design. For low input voltage applications, sufficient bulk
input capacitance is needed to minimize transient effects
during output load changes.
ꢁ . At best, this ringing can couple to the output and be
IN
mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at ꢁ large enough to damage the part.
IN
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
The selection of C
is determined by the effective series
ꢀUT
resistance(ESR)thatisrequiredtominimizevoltageripple
and load step transients as well as the amount of bulk
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Output Voltage Programming
The value for I
is determined by the desired amount
BURST
of output voltage ripple. As the value of I
increases,
BURST
The output voltage is set by an external resistive divider
according to the following equation:
the sleep period between pulses and the output voltage
ripple increase. The burst clamp voltage, ꢁ
, can be
BURST
R2
R1
ꢀ
ꢁ
ꢃ
ꢄ
set by a resistor divider from the ꢁ pin to the SGND pin
FB
VOUT = 0.8V 1+
ꢂ
ꢅ
as shown in Figure 1.
Pulse skipping, which is a compromise between low out-
put voltage ripple and efficiency, can be implemented by
The resistive divider allows pin ꢁ to sense a fraction of
FB
the output voltage as shown in Figure ±.
connectingpinSYNC/MꢀDEtoground. ThissetsI
to
BURST
0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator. The
lowest output voltage ripple is achieved while still operat-
ing discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
while maintaining the output voltage in regulation.
V
OUT
R2
V
FB
LTC3412A
SGND
R1
341±A F0±
Frequency Synchronization
Figure 2. Setting the Output Voltage
The LTC341±A’s internal oscillator can be synchronized
to an external clock signal. During synchronization, the
top MꢀSFET turn-on is locked to the falling edge of the
externalfrequencysource.Thesynchronizationfrequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set
by the external resistor. Because slope compensation
is generated by the oscillator’s RC circuit, the external
frequency should be set ±52 higher than the frequency
set by the external resistor to ensure that adequate slope
compensation is present.
Burst Clamp Programming
If the voltage on the SYNC/MꢀDE pin is less than ꢁ by
IN
1ꢁ, Burst Mode operation is enabled. During Burst Mode
ꢀperation, the voltage on the SYNC/MꢀDE pin determines
the burst clamp level, which sets the minimum peak
inductor current, I . To select the burst clamp level,
BURST
use the graph of Minimum Peak Inductor Current vs Burst
Clamp ꢁoltage in the Typical Performance Characteristics
section.
ꢁ
is the voltage on the SYNC/MꢀDE pin. I
BURST
BURST
Soft-Start
can only be programmed in the range of 0A to 6A. For
The RUN/SS pin provides a means to shut down the
LTC341±A as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5ꢁ places the LTC341±A in a low
values of ꢁ
values of ꢁ
greater than 1ꢁ, I
less than 0.4ꢁ, I
is set at 6A. For
is set at 0A. As
BURST
BURST
BURST
BURST
the output load current drops, the peak inductor currents
decrease to keep the output voltage in regulation. When
the output load current demands a peak inductor current
that is less than I
inductor current to remain equal to I
further reductions in the load current. Since the average
inductor current is greater than the output load current,
the voltage on the I pin will decrease. When the I
voltage drops to 150mꢁ, sleep mode is enabled in which
both power MꢀSFETs are shut off along with most of the
circuitry to minimize power consumption. All circuitry is
turned back on and the power MꢀSFETs begin switching
again when the output voltage drops out of regulation.
quiescent current shutdown state (I < 1μA).
Q
The LTC341±A contains an internal soft-start clamp that
, the burst clamp will force the peak
gradually raises the clamp on I after the RUN/SS pin is
BURST
TH
regardless of
pulled above ±ꢁ. The full current range becomes available
BURST
on I after 10±4 switching cycles. If a longer soft-start
TH
period is desired, the clamp on I can be set externally
TH
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
TH
TH
ꢀ
ꢃ
V
IN
t
SS =RSS CSS ln
(SECONDS)
ꢂ
ꢅ
V –1.8V
ꢁ
ꢄ
IN
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APPLICATIO S I FOR ATIO
Efficiency Considerations
±
curves. To obtain I R losses, simply add R to R and
SW L
multiply the result by the square of the average output
current.
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 1002. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
ꢀtherlossesincludingC andC ESRdissipativelosses
IN
ꢀUT
and inductor core losses generally account for less than
±2 of the total loss.
Efficiency = 1002 – (L1 + L± + L3 + ...)
Thermal Considerations
where L1, L±, etc. are the individual losses as a percent-
age of input power.
In most applications, the LTC341±A does not dissipate
much heat due to its high efficiency.
Although all dissipative elements in the circuit produce
However, in applications where the LTC341±A is running
at high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
mayexceedthemaximumjunctiontemperatureofthepart.
If the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
losses, two main sources usually account for most of the
±
losses: ꢁ quiescent current and I R losses.
IN
Theꢁ quiescentcurrentlossdominatestheefficiencyloss
IN
±
at very low load currents whereas the I R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
of no consequence.
ToavoidtheLTC341±Afromexceedingthemaximumjunc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
1. The ꢁ quiescent current is due to two components:
IN
the DC bias current as given in the electrical characteris-
tics and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MꢀSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
t = (P )(θ )
r
D
JA
where P is the power dissipated by the regulator and θ
D
JA
is the thermal resistance from the junction of the die to
the ambient temperature. For the 16-lead exposed TSSꢀP
from ꢁ to ground. The resulting dQ/dt is the current out
IN
of ꢁ that is typically larger than the DC bias current. In
IN
package, the θ is 38°C/W. For the 16-lead QFN package
continuous mode, I
= f(QT + QB) where QT and
JA
GATECHG
the θ is 34°C/W.
QB are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
JA
The junction temperature, T , is given by:
J
proportional to ꢁ ; thus, their effects will be more pro-
IN
T = T + t
r
nounced at higher supply voltages.
J
A
±
where T is the ambient temperature.
±. I R losses are calculated from the resistances of the
A
internal switches, R , and external inductor R . In con-
SW
L
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
To maximize the thermal performance of the LTC341±A,
the exposed pad should be soldered to a ground plane.
tinuous mode the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
).
DS(ꢀN)
MꢀSFET R
and the duty cycle (DC) as follows:
DS(ꢀN)
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
R
= (R
TꢀP)(DC) + (R
BꢀT)(1 – DC)
DS(ꢀN)
SW
DS(ꢀN)
The R
for both the top and bottom MꢀSFETs can
DS(ꢀN)
several cycles to respond to a step in load current.
be obtained from the Typical Performance Characteristics
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APPLICATIO S I FOR ATIO
When a load step occurs, ꢁ
amount equal to ΔI
immediately shifts by an
Decoupling the Pꢁ and Sꢁ pins with two ±±μF capaci-
ꢀUT
IN
IN
, where ESR is the effective
LꢀAD(ESR)
tors is adequate for most applications.
series resistance of C . ΔI
also begins to charge or
ꢀUT LꢀAD
generatingafeedbackerrorsignalusedby
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R±, and R3. The
voltage on pin MꢀDE will be set to 0.50ꢁ by the resistor
divider consisting of R± and R3. According to the graph
of Minimum Peak Inductor Current vs Burst Clamp ꢁolt-
age in the Typical Performance Characteristics section, a
burst clamp voltage of 0.5ꢁ will set the minimum inductor
dischargeC
ꢀUT
theregulatortoreturnꢁ toitssteady-statevalue.During
ꢀUT
this recovery time, ꢁ
can be monitored for overshoot
ꢀUT
or ringing that would indicate a stability problem. The I
TH
pin external components and output capacitor shown in
Figure 1 will provide adequate compensation for most
applications.
current, I , to approximately 1.1A.
BURST
Design Example
If we set the sum of R± and R3 to 185k, then the following
equations can be solved:
As a design example, consider using the LTC341±A in an
application with the following specifications:
R2 + R3 = 185k
R2 0.8V
R3 0.50V
ꢁ = 3.3ꢁ, ꢁ
= ±.5ꢁ, I
= 3A,
ꢀUT(MAX)
IN
ꢀUT(MIN)
ꢀUT
1+
=
I
= 100mA, f = 1MHz.
The two equations shown above result in the following
values for R± and R3: R± = 69.8k , R3 = 115k. The value
of R1 can now be determined by solving the following
equation.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
3.08•1011
R1
2.5V
ROSC
=
– 10k = 298k
1+
=
1•106
Use a standard value of ±94k. Next, calculate the inductor
value for about 402 ripple current at maximum ꢁ :
185k 0.8V
R1= 392k
IN
A value of 39±k will be selected for R1. Figure 4 shows
the complete schematic for this design example.
ꢀ
ꢃ
2.5V
(1MHz)(1.2A)
2.5V
3.3V
ꢀ
ꢁ
ꢃ
ꢄ
L =
1–
= 0.51μH
ꢂ
ꢅ
ꢂ
ꢅ
ꢁ
ꢄ
PC Board Layout Checklist
Using a 0.47μH inductor results in a maximum ripple
current of:
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC341±A. Check the following in your layout:
ꢁ
ꢃ
ꢄ
ꢆ
2.5V
ꢂ (1MHz)(0.47μH)ꢅ
2.5V
3.3V
ꢁ
ꢂ
ꢄ
ꢅ
ꢀIL =
1–
=1.29A
ꢃ
ꢆ
1. A ground plane is recommended. If a ground plane
layer is not used, the signal and power grounds should
be segregated with all small signal components returning
to the SGND pin at one point which is then connected to
the PGND pin close to the LTC341±A.
C
will be selected based on the ESR that is required to
ꢀUT
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100μF ceramic capacitors will be used.
C
should be sized for a maximum current rating of:
IN
±.Connectthe(+)terminaloftheinputcapacitor(s),C ,as
IN
2.5V
3.3V
3.3V
2.5V
ꢀ
ꢁ
ꢃ
ꢄ
close as possible to the Pꢁ pin. This capacitor provides
IRMS =(3A)
–1=1.29ARMS
IN
ꢂ
ꢅ
the AC current into the internal power MꢀSFETs.
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APPLICATIO S I FOR ATIO
3. Keep the switching node, SW, away from all sensitive
small signal nodes.
5. Connect the ꢁ pin directly to the feedback resistors.
FB
The resistor divider must be connected between ꢁ
and SGND.
ꢀUT
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. You can connect the copper areas to any DC
net (Pꢁ , Sꢁ , ꢁ , PGND, SGND, or any other DC rail
IN
IN ꢀUT
in your system).
Bottom
Top
Figure 3. LTC3412A Layout Diagram
ꢁ
IN
3.3ꢁ
C
±±pF X5R
R1 39±k
FF
C
**
IN3
100μF
1
16
Sꢁ
Pꢁ
IN
IN
R
C
IN1
PG
100k
±±μF
±
3
15
14
13
1±
11
10
9
PGꢀꢀD
PGꢀꢀD
SW
SW
R
ITH
17.4k
C
ITH
330pF X7R
I
TH
C
47pF
C
LTC341±A
EFE
L1*
0.47μH
PGND
PGND
SW
ꢁ
±.5ꢁ
3A
4
5
ꢀUT
ꢁ
FB
R±
69.8k
R3
115k
R
T
R
±94k
ꢀSC
SYNC/MꢀDE
6
7
R
SS
C
**
ꢀUT
±.±M
100μF
RUN
SW
C
×±
SS
1000pF X7R
8
SGND
Pꢁ
IN
C
IN±
±±μF
GND
X5R 6.3ꢁ
341± F04
*ꢁISHAY IHLP-±5±5CZ-01
**TDK 453±X5R0J107M
Figure 4. 3.3V to 2.5V, 3A Regulator at 1MHz, Burst Mode Operation
3412afc
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LTC3412A
U
TYPICAL APPLICATIO S
1.2V, 3A, 1.5MHz 1mm Height Regulator Using All Ceramic Capacitors
ꢁ
IN
3.3ꢁ
C1 ±±pF X5R
R1 95.3k
11
10
Sꢁ
Pꢁ
IN
IN
C
IN1
R
PG
10μF
100k
1±
13
9
8
7
6
5
4
3
X5R 6.3ꢁ
PGꢀꢀD
PGꢀꢀD
SW
SW
R
ITH
6.34k
C
ITH
1000pF X7R
I
TH
C
±±pF
C
LTC341±A
EUF
L1*
PGND
PGND
SW
0.47μH
ꢁ
1.±ꢁ
3A
14
15
ꢀUT
ꢁ
FB
R±
187k
R
T
R
196k
ꢀSC
16
1
C
±±μF
X3
**
ꢀUT
R
SS
SYNC/MꢀDE
RUN
±.±M
SW
C
SS
1000pF X7R
±
SGND
Pꢁ
IN
C
IN±
10μF
X5R 6.3ꢁ
GND
341± TA01
*CꢀꢀPER SD10-R47
**TAIYꢀ YUDEN AMK±1±BJ±±6MD-B
1.8V, 3A Step-Down Regulator at 1MHz, Burst Mode Operation
ꢁ
IN
±.5ꢁ
C1 47pF X5R
C
**
IN3
100μF
R1 ±3±k
1
16
Sꢁ
Pꢁ
IN
IN
C
IN1
R
PG
±±μF
100k
X5R 6.3ꢁ
±
3
15
14
13
1±
11
10
9
PGꢀꢀD
PGꢀꢀD
SW
SW
R
C
ITH
8±0pF X7R ITH
15k
I
TH
C±
47pF
LTC341±A
EFE
L1
PGND
PGND
SW
0.47μH*
ꢁ
1.8ꢁ
3A
4
5
ꢀUT
ꢁ
FB
R±
69.8k
R3
115k
R
T
R
±94k
ꢀSC
C
**
ꢀUT
6
7
R
100μF
SS
SYNC/MꢀDE
RUN
±.±M
×3
SW
C
SS
1000pF X7R
8
SGND
Pꢁ
IN
C
IN±
±±μF
X5R 6.3ꢁ
GND
341± TA0±
*ꢁISHAY IHLP-±5±5CZ-01
**TDK C453±X5R0J107M
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16
LTC3412A
U
TYPICAL APPLICATIO S
3.3V, 3A Step-Down Regulator at 2MHz, Forced Continuous Mode Operation
ꢁ
IN
5ꢁ
C
**
IN3
C1 ±±pF X5R
R1 634k
100μF
1
16
Sꢁ
Pꢁ
IN
IN
C
IN1
R
PG
±±μF
100k
±
3
4
15
14
13
1±
11
10
9
X5R 6.3ꢁ
PGꢀꢀD
PGꢀꢀD
SW
SW
R
ITH
7.5k
C
8±0pF X7R
ITH
I
TH
C
47pF
C
LTC341±A
EFE
L1*
PGND
PGND
SW
0.47μH
ꢁ
3.3ꢁ
3A
ꢀUT
ꢁ
FB
R±
±00k
5
R
T
R
137k
ꢀSC
6
7
C
**
ꢀUT
SYNC/MꢀDE
RUN
100μF
×±
SW
C
R
SS
SS
1000pF X7R
±.±M
8
SGND
Pꢁ
IN
C
IN±
±±μF
X5R 6.3ꢁ
GND
341± TA03
*ꢁISHAY IHLP-±5±5CZ-01
**TDK C453±X5R0J107M
2.5V, 3A Step-Down Regulator Synchronized to 1.8MHz
ꢁ
IN
3.3ꢁ
C1 ±±pF X5R
R1 39±k
1
16
Sꢁ
Pꢁ
IN
IN
C
IN1
R
PG
±±μF
100k
±
3
15
14
13
1±
11
10
9
X5R 6.3ꢁ
PGꢀꢀD
PGꢀꢀD
SW
SW
R
ITH
6.49k
C
±±0pF X7R
ITH
I
TH
LTC341±A
EFE
C
C
±±pF
L1*
PGND
PGND
SW
0.47μH
ꢁ
1.5ꢁ
3A
4
5
ꢀUT
ꢁ
FB
R± 16±k
18±k
R
T
R
ꢀSC
+
6
7
C
**
1.8MHz
ꢀUT
R
SS
SYNC/MꢀDE
RUN
150μF
EXT CLꢀCK
±.±M
SW
C
SS
1000pF X7R
8
SGND
Pꢁ
IN
C
IN±
±±μF
X5R 6.3ꢁ
GND
341± TA04
*CꢀꢀPER SD±0-R47
**SANYꢀ PꢀSCAP 4TPE150MAZB
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17
LTC3412A
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
4.90 – 5.10*
(.193 – .±01)
±.74
(.108)
±.74
(.108)
16 1514 13 1± 1110
9
6.60 ±0.10
4.50 ±0.10
±.74
(.108)
6.40
(.±5±)
BSC
SEE NꢀTE 4
±.74
(.108)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
±
3
4
6
RECꢀMMENDED SꢀLDER PAD LAYꢀUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.±5
REF
0° – 8°
0.65
(.0±56)
BSC
0.09 – 0.±0
(.0035 – .0079)
0.50 – 0.75
(.0±0 – .030)
0.05 – 0.15
(.00± – .006)
0.195 – 0.30
FE16 (BA) TSSꢀP 0±04
(.0077 – .0118)
TYP
NꢀTE:
1. CꢀNTRꢀLLING DIMENSIꢀN: MILLIMETERS 4. RECꢀMMENDED MINIMUM PCB METAL SIZE
FꢀR EXPꢀSED PAD ATTACHMENT
*DIMENSIꢀNS Dꢀ NꢀT INCLUDE MꢀLD FLASH. MꢀLD FLASH
SHALL NꢀT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
±. DIMENSIꢀNS ARE IN
3. DRAWING NꢀT Tꢀ SCALE
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18
LTC3412A
PACKAGE DESCRIPTIO
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-169±)
0.7± ±0.05
4.35 ± 0.05
±.90 ± 0.05
±.15 ± 0.05
(4 SIDES)
PACKAGE ꢀUTLINE
0.30 ±0.05
0.65 BSC
RECꢀMMENDED SꢀLDER PAD PITCH AND DIMENSIꢀNS
BꢀTTꢀM ꢁIEW—EXPꢀSED PAD
PIN 1 NꢀTCH R = 0.±0 TYP
ꢀR 0.35 × 45° CHAMFER
0.75 ± 0.05
R = 0.115
TYP
4.00 ± 0.10
(4 SIDES)
15
16
0.55 ± 0.±0
PIN 1
TꢀP MARK
(NꢀTE 6)
1
±
±.15 ± 0.10
(4-SIDES)
(UF16) QFN 10-04
0.±00 REF
0.30 ± 0.05
0.65 BSC
0.00 – 0.05
NꢀTE:
1. DRAWING CꢀNFꢀRMS Tꢀ JEDEC PACKAGE ꢀUTLINE Mꢀ-±±0 ꢁARIATIꢀN (WGGC)
±. DRAWING NꢀT Tꢀ SCALE
3. ALL DIMENSIꢀNS ARE IN MILLIMETERS
4. DIMENSIꢀNS ꢀF EXPꢀSED PAD ꢀN BꢀTTꢀM ꢀF PACKAGE Dꢀ NꢀT INCLUDE
MꢀLD FLASH. MꢀLD FLASH, IF PRESENT, SHALL NꢀT EXCEED 0.15mm ꢀN ANY SIDE
5. EXPꢀSED PAD SHALL BE SꢀLDER PLATED
6. SHADED AREA IS ꢀNLY A REFERENCE FꢀR PIN 1 LꢀCATIꢀN
ꢀN THE TꢀP AND BꢀTTꢀM ꢀF PACKAGE
3412afc
InformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3412A
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1878
600mA (I ), 550kHz, Synchronous Step-Down DC/DC Converter 962 Efficiency, ꢁ : ±.7ꢁ to 6ꢁ, ꢁ
= 0.8ꢁ, I = 10μA
Q
ꢀUT
IN
ꢀUT(MIN)
ꢀUT(MIN)
ꢀUT(MIN)
ꢀUT(MIN)
I
<1μA, MS8 Package
SD
LTC1879
1.±0A (I ), 550kHz, Synchronous Step-Down DC/DC Converter
952 Efficiency, ꢁ : ±.7ꢁ to 10ꢁ, ꢁ
SD
= 0.8ꢁ, I = 15μA,
Q
ꢀUT
IN
I
<1μA, TSSꢀP16 Package
LT1934/LT1934-1
LTC3404
300mA (I ), Constant ꢀff-Time, High Efficiency Step-Down
902 Efficiency, ꢁ : 3.±ꢁ to 34ꢁ, ꢁ
SD
= 1.±5ꢁ, I = 14μA,
Q
ꢀUT
IN
DC/DC Converter
I
<1μA, ThinSꢀT™ Package
600mA (I ), 1.4MHz, Synchronous Step-Down DC/DC Converter 952 Efficiency, ꢁ : ±.7ꢁ to 6ꢁ, ꢁ
= 0.8ꢁ, I = 10μA,
Q
ꢀUT
IN
I
SD
<1μA, MS8 Package
LTC3405/LTC3405A 300mA (I ), 1.5MHz, Synchronous Step-Down DC/DC Converter 952 Efficiency, ꢁ : ±.5ꢁ to 5.5ꢁ, ꢁ
= 0.8ꢁ, I = ±0μA,
Q
ꢀUT
IN
ꢀUT(MIN)
ꢀUT(MIN)
ꢀUT(MIN)
I
<1μA, ThinSꢀT Package
SD
LTC3406/LTC3406B 600mA (I ), 1.5MHz, Synchronous Step-Down DC/DC Converter 962 Efficiency, ꢁ : ±.5ꢁ to 5.5ꢁ, ꢁ
= 0.6ꢁ, I = ±0μA,
Q
ꢀUT
IN
I
SD
<1μA, ThinSꢀT Package
LTC3407
LTC3411
LTC341±
LTC3413
LTC3414
LTC3416
LTC3418
LT3430
Dual 600mA (I ), 1.5MHz, Synchronous Step-Down
952 Efficiency, ꢁ : ±.5ꢁ to 5.5ꢁ, ꢁ
SD
= 0.6ꢁ, I = 40μA,
Q
ꢀUT
IN
DC/DC Converter
I
<1μA, MS10E and 3mm × 3mm DFN Packages
1.±5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
952 Efficiency, ꢁ : ±.5ꢁ to 5.5ꢁ, ꢁ
SD
= 0.8ꢁ, I = 60μA,
Q
ꢀUT
IN
ꢀUT(MIN)
ꢀUT(MIN)
I
<1μA, MS10 and 3mm × 3mm DFN Packages
±.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
952 Efficiency, ꢁ : ±.5ꢁ to 5.5ꢁ, ꢁ
= 0.8ꢁ, I = 60μA,
Q
ꢀUT
IN
I
SD
<1μA, TSSꢀP16E Package
3A (I
Sink/Source), ±MHz, Monolithic Synchronous Regulator
902 Efficiency, ꢁ : ±.±5ꢁ to 5.5ꢁ, ꢁ
= ꢁ
,
REF/±
ꢀUT
IN
ꢀUT(MIN)
for DDR/QDR Memory Termination
I = ±80μA, I <1μA, TSSꢀP16E Package
Q SD
4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
952 Efficiency, ꢁ : ±.±5ꢁ to 5.5ꢁ, ꢁ
= 0.8ꢁ, I = 64μA,
Q
ꢀUT
IN
ꢀUT(MIN)
ꢀUT(MIN)
ꢀUT(MIN)
I
<1μA, TSSꢀP±0E Package
SD
4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
952 Efficiency, ꢁ : ±.±5ꢁ to 5.5ꢁ, ꢁ
= 0.8ꢁ, I = 64μA,
Q
ꢀUT
IN
I
SD
<1μA, TSSꢀP±0E Package
8A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
952 Efficiency, ꢁ : ±.±5ꢁ to 5.5ꢁ, ꢁ
= 0.8ꢁ, I = 380μA,
Q
ꢀUT
IN
I
<1μA, QFN Package
SD
60ꢁ, ±.75A (I ), ±00kHz, High Efficiency Step-Down
902 Efficiency, ꢁ : 5.5ꢁ to 60ꢁ, ꢁ
= 1.±0ꢁ, I = ±.5mA,
ꢀUT
IN
ꢀUT(MIN) Q
DC/DC Converter
I
±5μA, TSSꢀP16E Package
SD
LTC3440
LTC3441
LTC3548
600mA (I ), ±MHz, Synchronous Buck-Boost DC/DC Converter
952 Efficiency, ꢁ : ±.5ꢁ to 5.5ꢁ, ꢁ : ±.5ꢁ to 5.5ꢁ, I = ±5μA,
SD
ꢀUT
IN
ꢀUT
Q
I
<1μA, DFN Package
1.±A (I ), 1MHz, Synchronous Buck-Boost DC/DC Converter
952 Efficiency, ꢁ : ±.4ꢁ to 5.5ꢁ, ꢁ : ±.4ꢁ to 5.±5ꢁ, I = ±5μA,
ꢀUT
IN
ꢀUT
Q
I
<1μA, DFN Package
SD
400mA/800mA Dual Synchronous Step-Down DC/DC Converter
952 Efficiency, ꢁ : ±.5ꢁ to 5.5ꢁ, ꢁ
SD
= 0.6ꢁ, I <40μA,
IN
ꢀUT(MIN)
Q
I
<1μA, MS8E and DFN Packages
ThinSꢀT is a trademark of Linear Technology Corporation.
3412afc
LT 0708 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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