LTC3412AIFE#PBF [Linear]
LTC3412A - 3A, 4MHz, Monolithic Synchronous Step-Down Regulator; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC3412AIFE#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3412A - 3A, 4MHz, Monolithic Synchronous Step-Down Regulator; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总20页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3412A
3A, 4MHz, Monolithic
Synchronous
Step-Down Regulator
FEATURES
DESCRIPTION
The LTC®3412A is a high efficiency monolithic synchro-
nous, step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from
an input voltage range of 2.25ꢂ to 5.5ꢂ and provides a
regulated output voltage from 0.8ꢂ to 5ꢂ while deliver-
ing up to 3A of output current. The internal synchronous
powerswitchwith77mΩon-resistanceincreasesefficiency
and eliminates the need for an external Schottky diode.
Switching frequency is set by an external resistor or can
be synchronized to an external clock. 100ꢀ duty cycle
provides low dropout operation extending battery life in
portable systems. ꢁPTI-LꢁꢁP® compensation allows the
transient response to be optimized over a wide range of
loads and output capacitors.
n
ꢀ High Efficiency: Up to 95%
n
ꢀ 3A Output Current
n
ꢀ Low Quiescent Current: 64µA
n
ꢀ Low R
Internal Switch: 77mΩ
DS(ON)
n
n
n
n
n
ꢀ 2.25V to 5.5V Input Voltage Range
ꢀ Programmable Frequency: 300kHz to 4MHz
ꢀ 2ꢀ ꢁutput ꢂoltage Accuracy
ꢀ 0.8ꢂ Reference Allows Low ꢁutput ꢂoltage
®
ꢀ Selectable Forced Continuous/Burst Mode ꢁperation
with Adjustable Burst Clamp
n
n
n
n
n
ꢀ Synchronizable Switching Frequency
ꢀ Low Dropout ꢁperation: 100ꢀ Duty Cycle
ꢀ Power Good ꢁutput ꢂoltage Monitor
ꢀ ꢁvertemperature Protected
ꢀ Available in 16-Lead Exposed Pad TSSꢁP and
QFN Packages
The LTC3412A can be configured for either Burst Mode
operationorforcedcontinuousoperation.Forcedcontinu-
ous operation reduces noise and RF interference while
BurstModeoperationprovideshighefficiencybyreducing
gate charge losses at light loads. In Burst Mode operation,
external control of the burst clamp level allows the output
voltage ripple to be adjusted according to the application
requirements.
APPLICATIONS
n
ꢀ Point-of-Load Regulation
n
ꢀ Notebook Computers
n
ꢀ Portable Instruments
n
ꢀ Distributed Power Systems
L, LT, LTC, LTM, Burst Mode, ꢁPTI-LꢁꢁP, Linear Technology and the Linear logo are registered
trademarks and ThinSꢁT is a trademark of Analog Devices, Inc. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 5481178, 6580258,
6304066, 6127815, 6498466, 6611131, 6724174.
TYPICAL APPLICATION
22µF
V
Efficiency and Power Loss
IN
3.3V
100
95
90
85
80
75
70
65
60
55
50
100000
10000
1000
100
PV SV
IN
IN
EFFICIENCY
RT
2.2M
PGOOD
LTC3412A
0.47µH
294k
V
OUT
SW
2.5V AT 3A
OUT
C
RUN/SS
PGND
SGND
100µF
×2
12.1k
1000pF
I
TH
SYNC/MODE
V
FB
POWER LOSS
820pF
10
69.8k
392k
115k
3412A F01a
1
0.01
0.1
1
10
LOAD CURRENT (A)
3412A F01b
Figure 1. 2.5V/3A Step-Down Regulator
3412aff
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For more information www.linear.com/LTC3412A
LTC3412A
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply ꢂoltage....................................–0.3ꢂ to 6ꢂ
ꢁperating Junction Temperature Range (Notes 2, 5)
E-, I-Grades .......................................–40°C to 125°C
MP-Grade ..........................................–55°C to 125°C
Storage Temperature Range....................–65°C to150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
I , RUN/SS, ꢂ , PGꢁꢁD,
TH
FB
SYNC/MꢁDE ꢂoltages....................................–0.3 to ꢂ
IN
SW ꢂoltages ..................................–0.3ꢂ to (ꢂ + 0.3ꢂ)
IN
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
PV
IN
16
15
14
13
12
11
10
9
SV
IN
SW
PGOOD
16 15 14 13
SW
I
TH
RUN/SS
SGND
1
2
3
4
12 PGOOD
PGND
PGND
SW
V
FB
17
11 SV
IN
IN
R
T
17
PV
IN
PV
10
9
SYNC/MODE
RUN/SS
SW
SW
SW
5
6
7
8
PV
IN
SGND
FE PACKAGE
16-LEAD PLASTIC TSSOP
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
= 125°C, θ = 37°C/W, θ = 5°C/W
T
= 125°C, θ = 38°C/W, θ = 10°C/W
JMAX
JA JC
EXPꢁSED PAD (PIN 17) IS SGND, MUST BE SꢁLDERED Tꢁ PCB
T
JMAX
JA
JC
EXPꢁSED PAD (PIN 17) IS GND, MUST BE CꢁNNECTED Tꢁ PCB
ORDER INFORMATION http://www.linear.com/product/LTC3412A#orderinfo
LEAD FREE FINISH
LTC3412AEFE#PBF
LTC3412AIFE#PBF
LTC3412AEUF#PBF
LTC3412AIUF#PBF
LEAD BASED FINISH
LTC3412AEFE
TAPE AND REEL
PART MARKING*
3412AEFE
3412AIFE
3412A
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
LTC3412AEFE#TRPBF
LTC3412AIFE#TRPBF
LTC3412AEUF#TRPBF
LTC3412AIUF#TRPBF
TAPE AND REEL
16-Lead Plastic TSSꢁP
16-Lead Plastic TSSꢁP
16-Lead (4mm × 4mm) Plastic QFN
16-Lead (4mm × 4mm) Plastic QFN
PACKAGE DESCRIPTION
3412A
PART MARKING*
3412AEFE
3412AIFE
3412AMPFE
3412A
LTC3412AEFE#TR
LTC3412AIFE#TR
16-Lead Plastic TSSꢁP
LTC3412AIFE
16-Lead Plastic TSSꢁP
LTC3412AMPFE
LTC3412AEUF
LTC3412AMPFE#TR
LTC3412AEUF#TR
LTC3412AIUF#TR
16-Lead Plastic TSSꢁP
16-Lead (4mm × 4mm) Plastic QFN
16-Lead (4mm × 4mm) Plastic QFN
LTC3412AIUF
3412A
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
3412aff
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For more information www.linear.com/LTC3412A
LTC3412A
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA ≈ TJ = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Sꢂ
Signal Input ꢂoltage Range
Regulated Feedback ꢂoltage
2.25
5.5
ꢂ
IN
ꢂ
FB
(Note 3)
E-, I-Grades
MP-Grade
l
l
0.784
0.780
0.800
0.800
0.816
0.816
ꢂ
ꢂ
I
ꢂoltage Feedback Leakage Current
Reference ꢂoltage Line Regulation
ꢁutput ꢂoltage Load Regulation
0.1
0.2
0.2
µA
FB
l
∆ꢂ
ꢂ
= 2.7ꢂ to 5.5ꢂ (Note 3)
0.04
ꢀꢂ
FB
IN
l
l
ꢂ
Measured in Servo Loop, ꢂ = 0.36ꢂ
Measured in Servo Loop, ꢂ = 0.84ꢂ
0.02
–0.02
0.2
–0.2
ꢀ
ꢀ
LꢁADREG
ITH
ITH
∆ꢂ
Power Good Range
7.5
9
ꢀ
Ω
PGꢁꢁD
R
Power Good Pull-Down Resistance
120
200
PGꢁꢁD
I
Input DC Bias Current
Active Current
Sleep
(Note 4)
Q
ꢂ
ꢂ
ꢂ
= 0.78ꢂ, ꢂ = 1ꢂ
250
64
0.02
330
80
1
µA
µA
µA
FB
FB
RUN
ITH
= 1ꢂ, ꢂ = 0ꢂ
ITH
= 0ꢂ
MꢁDE
Shutdown
= 0ꢂ, ꢂ
f
f
Switching Frequency
R
= 294kΩ
0.88
0.3
1
1.1
4
MHz
MHz
ꢁSC
ꢁSC
Switching Frequency Range
(Note 6)
SYNC Capture Range
(Note 6)
0.3
4
MHz
mΩ
mΩ
A
SYNC
R
R
R
DS(ꢁN)
R
DS(ꢁN)
of P-Channel FET
of N-Channel FET
I
I
= 1A (Note 7)
77
65
6
110
90
PFET
NFET
SW
= –1A (Note 7)
SW
I
Peak Current Limit
4.5
LIMIT
ꢂ
Undervoltage Lockout Threshold
SW Leakage Current
RUN Threshold
1.75
2
2.25
1
ꢂ
UꢂLꢁ
LSW
I
ꢂ
RUN
= 0ꢂ, ꢂ = 5.5ꢂ
0.1
0.65
µA
ꢂ
IN
ꢂ
0.5
0.8
1
RUN
RUN
I
RUN/SS Leakage Current
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LTC3412A is tested in a feedback loop that adjusts ꢂ to
FB
achieve a specified error amplifier output voltage (I ).
TH
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 2: The LTC3412AE is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3412AI is guaranteed
to meet performance specifications over the –40°C to 125°C operating
junction temperature range. The LTC3412AMP is guaranteed and tested to
meet performance specifications over the full –55°C to 125°C operating
junction temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 5: T is calculated from the ambient temperature T and power
J
A
dissipation as follows: LTC3412AFE: T = T + P (38°C/W)
J
A
D
LTC3412AUF: T = T + P (34°C/W)
J
A
D
Note 6: 4MHz operation is guaranteed by design and not production tested.
Note 7: Switch on resistance is guaranteed by design and test condition in
the UF package and by final test correlation in the FE package.
3412aff
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For more information www.linear.com/LTC3412A
LTC3412A
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current,
Burst Mode Operation
Efficiency vs Load Current,
Forced Continuous Operation
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
100
90
80
70
60
50
40
30
20
10
0
V
= 3.3V
V
= 3.3V
IN
IN
Burst Mode
OPERATION
V
= 5V
V
= 5V
IN
IN
FORCED
CONTINUOUS
V
V
= 3.3V
IN
OUT
V
= 2.5V
V
OUT
= 2.5V
= 2.5V
OUT
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
0.01
0.1
1
10
0.01
0.1
1
10
0.01
0.1
1 10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
3412A GO1
3412A GO2
3412A GO3
Efficiency vs Input Voltage
Efficiency vs Frequency
Load Regulation
96
95
94
93
92
91
90
89
88
87
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
94
92
90
88
86
84
82
80
FIGURE 4 CIRCUIT
= 3.3V
FIGURE 4 CIRCUIT
= 3.3V
FIGURE 4 CIRCUIT
V
IN
V
IN
1µH
0.22µH
0.47µH
1A
0.1A
3A
0
0.5
1.5 2.0 2.5 3.0
FREQUENCY (MHz)
4.0
0
1.0
1.5
2.0
2.5
3.0
1.0
3.5
0.5
3.0
3.5
INPUT VOLTAGE (V)
4.0
4.5
5.0
2.5
LOAD CURRENT (A)
3412A GO5
3412A GO6
3412A GO4
Load Step Transient Burst Mode
Operation
Burst Mode Operation
Output Voltage Ripple
BURST
MODE
20mV/DIV
V
OUT
20mV/DIV
V
OUT
100mV/DIV
PULSE
SKIPPING
20mV/DIV
INDUCTOR
CURRENT
1A/DIV
FORCED
CONTINUOUS
20mV/DIV
INDUCTOR
CURRENT
2A/DIV
FIGURE 4 CIRCUIT
V
V
= 3.3V
V
V
= 3.3V
5µs/DIV
5µs/DIV
40µs/DIV
IN
OUT
IN
OUT
= 2.5V
= 2.5V
FIGURE 4 CIRCUIT
F = 1MHz
3412A GO7
3412A GO8
3412A GO9
LOAD STEP = 50mA TO 2A
FIGURE 4 CIRCUIT
3412aff
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For more information www.linear.com/LTC3412A
LTC3412A
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step Transient Forced
Continuous
Start-Up Transient
VREF vs Temperature
0.7975
0.7970
0.7965
0.7960
0.7955
0.7950
0.7945
0.7940
0.7935
0.7930
V
= 3.3V
IN
V
OUT
2V/DIV
V
OUT
100mV/DIV
RUN/SS
2V/DIV
INDUCTOR
CURRENT
2A/DIV
INDUCTOR
CURRENT
2A/DIV
115
–45 –25
15 35 55
TEMPERATURE (°C)
95
V
V
= 3.3V
OUT
f = 1MHz
40µs/DIV
V
V
= 3.3V
1ms/DIV
–5
75
IN
IN
=2.5V
=2.5V
OUT
LOAD STEP = 2A
3412A G10
3412A G11
3412A G12
LOAD STEP = 0A TO 3A
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
Switch On-Resistance
vs Input Voltage
Switch On-Resistance
vs Temperature
Switch Leakage Current
vs Input Voltage
100
95
90
85
80
75
70
65
60
55
50
50
45
40
35
30
25
20
15
10
5
120
100
80
60
40
20
0
V
= 3.3V
IN
PFET
NFET
PFET
NFET
PFET
NFET
0
2.5
3.0
3.5
4.0
4.5
5.0
–40
40
TEMPERATURE (°C)
80 100
120
–20
0
20
60
2.5
3.0
4.0
4.5
5.0
5.5
3.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3412A G13
3412A G14
3412A G15
Frequency vs ROSC
Frequency vs Input Voltage
Frequency vs Temperature
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
1060
1050
1040
1030
1020
1010
1000
990
1020
1015
1010
1005
1000
995
V = 3.3V
IN
V
= 3.3V
R
OSC
= 294k
IN
R
= 294k
OSC
990
985
980
975
0
970
2.5
3.0
3.5
4.0
4.5
5.0
5.5
40 140 240 340 440 540 640 740 840 940
(kΩ)
–40
40
TEMPERATURE (°C)
80 100
120
–20
0
20
60
INPUT VOLTAGE (V)
R
OSC
3412A G17
3412A G16
3412A G18
3412aff
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For more information www.linear.com/LTC3412A
LTC3412A
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current
vs Input Voltage
Quiescent Current vs Temperature
350
300
250
200
150
100
50
350
300
250
200
150
100
50
V
= 3.3V
IN
ACTIVE
ACTIVE
SLEEP
SLEEP
4.5
0
0
–40 –20
0
20 40 60 80 100 120
2.5
3.5
4.0
5.0
5.5
3.0
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3412A G20
3412A G19
Minimum Peak Inductor Current
vs Burst Clamp Voltage
Peak Current vs Input Voltage
4000
3500
3000
2500
2000
1500
1000
500
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
0
0.6
0.1
0.2
0.3
0.4
0.5
0.7
4.75
2.25
2.75
3.25
3.75
4.25
V
(V)
INPUT VOLTAGE (V)
BURST
3412A G22
3412A G21
3412aff
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For more information www.linear.com/LTC3412A
LTC3412A
PIN FUNCTIONS (FE/UHF)
SV (Pin 1/Pin 11): Signal Input Supply. Decouple this
RUN/SS (Pin 7/Pin 1): Run Control and Soft-Start Input.
Forcing this pin below 0.5ꢂ shuts down the LTC3412A.
In shutdown all functions are disabled drawing <1µA of
supply current. A capacitor to ground from this pin sets
the ramp time to full output current.
IN
pin to SGND with a capacitor.
PGOOD (Pin 2/Pin 12): Power Good ꢁutput. ꢁpen-drain
logic output that is pulled to ground when the output volt-
age is not within 7.5ꢀ of regulation point.
SGND (Pin 8/Pin 2): Signal Ground. All small-signal com-
ponents, compensationcomponentsandtheexposedpad
onthebottomsideoftheICshouldconnecttothisground,
which in turn connects to PGND at one point.
I
(Pin 3/Pin 13): Error Amplifier Compensation Point.
TH
The current comparator threshold increases with this
control voltage. Nominal voltage range for this pin is from
0.2ꢂ to 1.4ꢂ with 0.4ꢂ corresponding to the zero-sense
voltage (zero current).
PV (Pins9,16/Pins3,10):PowerInputSupply.Decouple
IN
this pin to PGND with a capacitor.
V
(Pin 4/Pin 14): Feedback Pin. Receives the feedback
FB
voltage from a resistive divider connected across the
SW (Pins 10, 11, 14, 15/Pins 4, 5, 8, 9): Switch Node
ConnectiontotheInductor. Thispinconnectstothedrains
of the internal main and synchronous power MꢁSFET
switches.
output.
R (Pin 5/Pin 15): ꢁscillator Resistor Input. Connecting
T
a resistor to ground from this pin sets the switching
frequency.
PGND (Pins 12, 13/Pins 6, 7): Power Ground. Connect
this pin close to the (–) terminal of C and C
.
IN
ꢁUT
SYNC/MODE (Pin 6/Pin 16): Mode Select and External
Clock Synchronization Input. To select forced continuous,
Exposed Pad (Pin 17/Pin 17): Signal Ground. Must be
solderedtoPCBforelectricalconnectionandratedthermal
performance.
tie to Sꢂ . Connecting this pin to a voltage between 0ꢂ
IN
and 1ꢂ selects Burst Mode operation with the burst clamp
set to the pin voltage.
3412aff
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For more information www.linear.com/LTC3412A
LTC3412A
FUNCTIONAL BLOCK DIAGRAM
PV
IN
SV
SGND
I
TH
3
IN
1
8
9
16
SLOPE
COMPENSATION
RECOVERY
PMOS CURRENT
COMPARATOR
VOLTAGE
REFERENCE
0.8V
BCLAMP
+
–
+
–
–
+
P-CH
4
V
FB
ERROR
AMPLIFIER
BURST
COMPARATOR
+
–
SYNC/MODE
+
–
0.74V
10
SLOPE
11
14
15
COMPENSATION
OSCILLATOR
SW
+
–
N-CH
RUN/SS
PGOOD
7
2
RUN
0.86V
LOGIC
+
–
NMOS
CURRENT
COMPARATOR
–
+
REVERSE
CURRENT
COMPARATOR
12
13
PGND
5
6
3412 FBD
R
SYNC/MODE
T
OPERATION
Main Control Loop
comparing the feedback signal from a resistor divider on
the ꢂ pin with an internal 0.8ꢂ reference. When the load
FB
TheLTC3412Aisamonolithic,constant-frequency,current
mode step-down DC/DC converter. During normal opera-
tion, the internal top power switch (P-channel MꢁSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MꢁSFET. The peak inductor
current at which the current comparator shuts off the top
current increases, it causes a reduction in the feedback
voltage relative to the reference. The error amplifier raises
the I voltage until the average inductor current matches
TH
the new load current. When the top power MꢁSFET shuts
off, the synchronous power switch (N-channel MꢁSFET)
turns on until either the bottom current limit is reached or
the beginning of the next clock cycle. The bottom current
limit is set at –1.3A for forced continuous mode and 0A
for Burst Mode operation.
power switch is controlled by the voltage on the I pin.
The error amplifier adjusts the voltage on the I pin by
TH
TH
3412aff
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For more information www.linear.com/LTC3412A
LTC3412A
OPERATION
The operating frequency is externally set by an external
Pulse-skipping operation is implemented by connecting
the SYNC/MꢁDE pin to ground. This forces the burst
clamp level to be at 0ꢂ. As the load current decreases, the
peak inductor current will be determined by the voltage
resistor connected between the R pin and ground. The
T
practical switching frequency can range from 300kHz to
4MHz.
on the I pin until the I voltage drops below 400mꢂ. At
TH
TH
ꢁvervoltage and undervoltage comparators will pull the
PGꢁꢁD output low if the output voltage comes out of
regulation by 7.5ꢀ. In an overvoltage condition, the top
powerMꢁSFETisturnedoffandthebottompowerMꢁSFET
isswitchedonuntileithertheovervoltageconditionclears
or the bottom MꢁSFET’s current limit is reached.
this point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
demand is less than the average of the minimum on-time
inductor current, switching cycles will be skipped to keep
the output voltage in regulation.
Frequency Synchronization
Forced Continuous Mode
The internal oscillator of the LTC3412A can be synchro-
nized to an external clock connected to the SYNC/MꢁDE
pin. The frequency of the external clock can be in the
range of 300kHz to 4MHz. For this application, the oscil-
lator timing resistor should be chosen to correspond to
a frequency that is 25ꢀ lower than the synchronization
frequency. During synchronization, the burst clamp is set
to 0ꢂ, and each switching cycle begins at the falling edge
of the clock signal.
Connecting the SYNC/MꢁDE pin to Sꢂ will disable Burst
IN
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficientthanBurstModeoperation,butmaybedesirablein
some applications where it is necessary to keep switching
harmonics out of a signal band. The output voltage ripple
is minimized in this mode.
Burst Mode Operation
Connecting the SYNC/MꢁDE pin to a voltage in the range
of 0ꢂ to 1ꢂ enables Burst Mode operation. In Burst Mode
operation, the internal power MꢁSFETs operate intermit-
tently at light loads. This increases efficiency by minimiz-
ing switching losses. During Burst Mode operation, the
minimum peak inductor current is externally set by the
Dropout Operation
Whentheinputsupplyvoltagedecreasestowardtheoutput
voltage, the duty cycle increases toward the maximum
on-time. Further reduction of the supply voltage forces
the main switch to remain on for more than one cycle
eventually reaching 100ꢀ duty cycle. The output voltage
will then be determined by the input voltage minus the
voltage drop across the internal P-channel MꢁSFET and
the inductor.
voltage on the SYNC/MꢁDE pin and the voltage on the I
TH
pin is monitored by the burst comparator to determine
when sleep mode is enabled and disabled. When the
average inductor current is greater than the load current,
the voltage on the I pin drops. As the I voltage falls
TH
TH
Low Supply Operation
below 150mꢂ, the burst comparator trips and enables
The LTC3412A is designed to operate down to an input
supplyvoltageof2.25ꢂ.ꢁneimportantconsiderationatlow
input supply voltages is that the R
andN-channelpowerswitchesincreases. Theusershould
calculatethepowerdissipationwhentheLTC3412Aisused
at 100ꢀ duty cycle with low input voltages to ensure that
thermal limits are not exceeded.
sleep mode. During sleep mode, the top power MꢁSFET
is held off and the I pin is disconnected from the output
TH
of the P-channel
of the error amplifier. The majority of the internal circuitry
is also turned off to reduce the quiescent current to 64µA
while the load current is solely supplied by the output
DS(ꢁN)
capacitor. When the output voltage drops, the I pin is
TH
reconnected to the output of the error amplifier and the
top power MꢁSFET along with all the internal circuitry is
switched back on. This process repeats at a rate that is
dependent on the load demand.
3412aff
9
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LTC3412A
APPLICATIONS INFORMATION
Slope Compensation and Inductor Peak Current
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3412A imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 110ns; therefore, the minimum duty cycle is
equal to 100 • 110ns • f(Hz).
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50ꢀ. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40ꢀ. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3412A, however,
slope compensation recovery is implemented to keep the
maximum inductor peak current constant throughout the
range of duty cycles. This keeps the maximum output
current relatively constant regardless of duty cycle.
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ∆I increases with higher ꢂ or ꢂ
and
L
IN
ꢁUT
decreases with higher inductance.
⎛
OUT ⎞ ⎛
⎞
V
VOUT
ΔIL =
1–
⎜
⎟ ⎜
⎟
fL
V
⎝
⎠ ⎝
⎠
IN
Short-Circuit Protection
Having a lower ripple current reduces the core losses in
the inductor, the ESR losses in the output capacitors, and
the output voltage ripple. Highest efficiency operation is
achieved at low frequency with small ripple current. This,
however, requires a large inductor.
When the output is shorted to ground, the inductor cur-
rent decays very slowly during a single switching cycle.
To prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases larger than 4.4A, the top
power MꢁSFET will be held off and switching cycles will
be skipped until the inductor current is reduced.
A reasonable starting point for selecting the ripple current
is ∆I = 0.4(I
). The largest ripple current occurs at the
MAX
L
highest ꢂ . To guarantee that the ripple current stays
IN
The basic LTC3412A application circuit is shown in Fig-
ure 1. External component selection is determined by the
maximum load current and begins with the selection of
the operating frequency and inductor value followed by
below a specified maximum, the inductor value should
be chosen according to the following equation:
⎛
⎞ ⎛
⎞
VOUT
fΔI
VOUT
L =
1–
⎜
⎟ ⎜
⎟
C and C
.
IN
ꢁUT
V
⎝
⎠ ⎝
⎠
L(MAX)
IN(MAX)
Operating Frequency
The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
when the peak inductor current falls below a level set by
the burst clamp. Lower inductor values result in higher
ripple current which causes this to occur at lower load
currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
Selectionoftheoperatingfrequencyisatrade-offbetween
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
ꢁperation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency of the LTC3412A is determined
by an external resistor that is connected between pin R
andground.Thevalueoftheresistorsetstherampcurrent
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation:
T
Inductor Core Selection
ꢁnce the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
3.08 •1011
ROSC
=
Ω –10kΩ
( )
f
will increase.
3412aff
10
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LTC3412A
APPLICATIONS INFORMATION
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response as described in a later section.
The output ripple, ∆ꢂ , is determined by:
ꢁUT
⎛
⎞
1
ΔVOUT ≤ ΔIL ESR+
⎜
⎟
8fCOUT
⎝
⎠
The output ripple is highest at maximum input voltage
Differentcorematerialsandshapeswillchangethesize/cur-
rent and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price verus size requirements and
any radiated field/EMI requirements. New designs for
surface mount inductors are available from Coiltronics,
Coilcraft, Toko and Sumida.
since ∆I increases with input voltage. Multiple capacitors
L
placed in parallel may be needed to meet the ESR and
RMScurrenthandlingrequirements.Drytantalum,special
polymer,aluminumelectrolytic,andceramiccapacitorsare
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR, but can be used in cost-sensitive
applications provided that consideration is given to ripple
currentratingsandlong-termreliability.Ceramiccapacitors
have excellent low ESR characteristics but can have a high
voltage coefficient and audible piezoelectric effects. The
high Q of ceramic capacitors with trace inductance can
also lead to significant ringing.
C and C
Selection
IN
OUT
Theinputcapacitance,C ,isneededtofilterthetrapezoidal
IN
wave current at the source of the top MꢁSFET. To prevent
large voltage transients from occurring, a low ESR input
capacitor sized for the maximum RMS current should be
used. The maximum RMS current is given by:
VOUT
V
VOUT
Using Ceramic Input and Output Capacitors
IN
I
RMS =IOUT(MAX)
–1
V
IN
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
thepowerissuppliedbyawalladapterthroughlongwires,
a load step at the output can induce ringing at the input,
This formula has a maximum at ꢂ = 2ꢂ , where
IN
ꢁUT
I
= I
. This simple worst-case condition is com-
RMS
ꢁUT/2
monlyusedfordesignbecauseevensignificantdeviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further
deratethecapacitor,orchooseacapacitorratedatahigher
temperature than required. Several capacitors may also
be paralleled to meet size or height requirements in the
design. For low input voltage applications, sufficient bulk
input capacitance is needed to minimize transient effects
during output load changes.
ꢂ . At best, this ringing can couple to the output and be
IN
mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at ꢂ large enough to damage the part.
IN
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
The selection of C
is determined by the effective series
ꢁUT
resistance(ESR)thatisrequiredtominimizevoltageripple
and load step transients as well as the amount of bulk
3412aff
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LTC3412A
APPLICATIONS INFORMATION
Output Voltage Programming
The value for I
is determined by the desired amount
BURST
of output voltage ripple. As the value of I
increases,
BURST
The output voltage is set by an external resistive divider
according to the following equation:
the sleep period between pulses and the output voltage
ripple increase. The burst clamp voltage, ꢂ
, can be
BURST
R2
R1
⎛
⎝
⎞
⎠
set by a resistor divider from the ꢂ pin to the SGND pin
FB
VOUT = 0.8V 1+
⎜
⎟
as shown in Figure 1.
Pulse skipping, which is a compromise between low out-
put voltage ripple and efficiency, can be implemented by
The resistive divider allows pin ꢂ to sense a fraction of
FB
the output voltage as shown in Figure 2.
connectingpinSYNC/MꢁDEtoground. ThissetsI
to
BURST
0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator. The
lowest output voltage ripple is achieved while still operat-
ing discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
while maintaining the output voltage in regulation.
V
OUT
R2
V
FB
LTC3412A
SGND
R1
3412A F02
Frequency Synchronization
Figure 2. Setting the Output Voltage
The LTC3412A’s internal oscillator can be synchronized
to an external clock signal. During synchronization, the
top MꢁSFET turn-on is locked to the falling edge of the
externalfrequencysource.Thesynchronizationfrequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set
by the external resistor. Because slope compensation
is generated by the oscillator’s RC circuit, the external
frequency should be set 25ꢀ higher than the frequency
set by the external resistor to ensure that adequate slope
compensation is present.
Burst Clamp Programming
If the voltage on the SYNC/MꢁDE pin is less than ꢂ by
IN
1ꢂ, Burst Mode operation is enabled. During Burst Mode
ꢁperation, the voltage on the SYNC/MꢁDE pin determines
the burst clamp level, which sets the minimum peak
inductor current, I
. To select the burst clamp level,
BURST
use the graph of Minimum Peak Inductor Current vs Burst
Clamp ꢂoltage in the Typical Performance Characteristics
section.
ꢂ
is the voltage on the SYNC/MꢁDE pin. I
BURST
BURST
Soft-Start
can only be programmed in the range of 0A to 6A. For
The RUN/SS pin provides a means to shut down the
LTC3412A as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5ꢂ places the LTC3412A in a low
values of ꢂ
values of ꢂ
greater than 1ꢂ, I
less than 0.4ꢂ, I
is set at 6A. For
is set at 0A. As
BURST
BURST
BURST
BURST
the output load current drops, the peak inductor currents
decrease to keep the output voltage in regulation. When
the output load current demands a peak inductor current
that is less than I
inductor current to remain equal to I
further reductions in the load current. Since the average
inductor current is greater than the output load current,
the voltage on the I pin will decrease. When the I
voltage drops to 150mꢂ, sleep mode is enabled in which
both power MꢁSFETs are shut off along with most of the
circuitry to minimize power consumption. All circuitry is
turned back on and the power MꢁSFETs begin switching
again when the output voltage drops out of regulation.
quiescent current shutdown state (I < 1µA).
Q
The LTC3412A contains an internal soft-start clamp that
, the burst clamp will force the peak
gradually raises the clamp on I after the RUN/SS pin is
BURST
TH
regardless of
pulled above 2ꢂ. The full current range becomes available
BURST
on I after 1024 switching cycles. If a longer soft-start
TH
period is desired, the clamp on I can be set externally
TH
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
TH
TH
⎛
⎞
V
IN
t
SS =RSS CSS ln
(SECONDS)
⎜
⎟
V –1.8V
⎝
⎠
IN
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LTC3412A
APPLICATIONS INFORMATION
Efficiency Considerations
The R
for both the top and bottom MꢁSFETs can be
DS(ꢁN)
obtained from the Typical Performance Characteristics
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100ꢀ. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
2
curves.ToobtainI Rlosses,simplyaddR toR andmul-
tiplytheresultbythesquareoftheaverageoutputcurrent.
SW
L
ꢁtherlossesincludingC andC ESRdissipativelosses
and inductor core losses generally account for less than
2ꢀ of the total loss.
IN
ꢁUT
Efficiency = 100ꢀ – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Thermal Considerations
In most applications, the LTC3412A does not dissipate
much heat due to its high efficiency.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
However, in applications where the LTC3412A is running
at high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
mayexceedthemaximumjunctiontemperatureofthepart.
If the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
2
losses: ꢂ quiescent current and I R losses.
IN
Theꢂ quiescentcurrentlossdominatestheefficiencyloss
IN
2
at very low load currents whereas the I R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
of no consequence.
To avoid the LTC3412A from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whetherthepowerdissipatedexceedsthemaximumjunction
temperature of the part. The temperature rise is given by:
1.Theꢂ quiescentcurrentisduetotwocomponents: the
IN
DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
fromswitchingthegatecapacitanceoftheinternalpower
MꢁSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
t = (P )(θ )
r
D
JA
where P is the power dissipated by the regulator and θ
D
JA
is the thermal resistance from the junction of the die to
the ambient temperature. For the 16-lead exposed TSSꢁP
from ꢂ to ground. The resulting dQ/dt is the current
IN
out of ꢂ that is typically larger than the DC bias cur-
IN
package, the θ is 38°C/W. For the 16-lead QFN package
rent. In continuous mode, I
= f(QT + QB) where
JA
GATECHG
the θ is 34°C/W.
QT and QB are the gate charges of the internal top and
bottom switches. Both the DC bias and gate charge
JA
The junction temperature, T , is given by:
J
losses are proportional to ꢂ ; thus, their effects will
IN
T = T + t
r
J
A
be more pronounced at higher supply voltages.
where T is the ambient temperature.
2
A
2. I R losses are calculated from the resistances of the
internal switches, R , and external inductor R . In
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
To maximize the thermal performance of the LTC3412A,
the Exposed Pad should be soldered to a ground plane.
SW
L
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
).
DS(ꢁN)
Checking Transient Response
top and bottom MꢁSFET R
(DC) as follows:
and the duty cycle
DS(ꢁN)
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current.
R
SW
= (R TꢁP)(DC) + (R BꢁT)(1 – DC)
DS(ꢁN) DS(ꢁN)
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LTC3412A
APPLICATIONS INFORMATION
When a load step occurs, ꢂ
immediately shifts by an
Decoupling the Pꢂ and Sꢂ pins with two 22µF capaci-
IN IN
ꢁUT
amount equal to ∆I
, where ESR is the effective
tors is adequate for most applications.
LꢁAD(ESR)
series resistance of C . ∆I
also begins to charge or
ꢁUT
LꢁAD
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R2 and R3. The
voltage on pin MꢁDE will be set to 0.50ꢂ by the resistor
divider consisting of R2 and R3. According to the graph
of Minimum Peak Inductor Current vs Burst Clamp ꢂolt-
age in the Typical Performance Characteristics section, a
burst clamp voltage of 0.5ꢂ will set the minimum inductor
dischargeC
generatingafeedbackerrorsignalusedby
ꢁUT
theregulatortoreturnꢂ toitssteady-statevalue.During
ꢁUT
this recovery time, ꢂ
can be monitored for overshoot
ꢁUT
or ringing that would indicate a stability problem. The I
TH
pin external components and output capacitor shown in
Figure 1 will provide adequate compensation for most
applications.
current, I
, to approximately 1.1A.
BURST
Design Example
If we set the sum of R2 and R3 to 185k, then the following
equations can be solved:
As a design example, consider using the LTC3412A in an
application with the following specifications:
R2 + R3 = 185k
R2 0.8V
R3 0.50V
ꢂ = 3.3ꢂ, ꢂ
ꢁUT(MIN)
= 2.5ꢂ, I
= 3A,
ꢁUT(MAX)
IN
ꢁUT
1+
=
I
= 100mA, f = 1MHz.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
The two equations shown above result in the following
values for R2 and R3: R2 = 69.8k , R3 = 115k. The value
of R1 can now be determined by solving the following
equation.
First, calculate the timing resistor:
3.08•1011
1•106
R1
2.5V
ROSC
=
– 10k = 298k
1+
=
185k 0.8V
R1= 392k
Use a standard value of 294k. Next, calculate the inductor
value for about 40ꢀ ripple current at maximum ꢂ :
A value of 392k will be selected for R1. Figure 4 shows
the complete schematic for this design example.
IN
⎛
⎞
2.5V
(1MHz)(1.2A)
2.5V
3.3V
⎛
⎝
⎞
⎠
L =
1–
= 0.51µH
⎜
⎟
⎜
⎟
⎝
⎠
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3412A. Check the following in your layout:
Using a 0.47µH inductor results in a maximum ripple
current of:
⎛
⎜
⎞
⎟
2.5V
⎝ (1MHz)(0.47µH)⎠
2.5V
3.3V
⎛
⎝
⎞
⎠
1. Agroundplaneisrecommended.Ifagroundplanelayer
is not used, the signal and power grounds should be
segregated with all small signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3412A.
ΔIL =
1–
=1.29A
⎜
⎟
C
will be selected based on the ESR that is required to
ꢁUT
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100µF ceramic capacitors will be used.
2. Connectthe(+)terminaloftheinputcapacitor(s),C ,as
IN
C should be sized for a maximum current rating of:
IN
closeaspossibletothePꢂ pin.Thiscapacitorprovides
IN
the AC current into the internal power MꢁSFETs.
2.5V
3.3V
3.3V
2.5V
⎛
⎝
⎞
⎠
IRMS =(3A)
–1=1.29ARMS
⎜
⎟
3412aff
14
For more information www.linear.com/LTC3412A
LTC3412A
APPLICATIONS INFORMATION
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
5. Connect the ꢂ pin directly to the feedback resistors.
FB
The resistor divider must be connected between ꢂ
and SGND.
ꢁUT
4. Floodallunusedareasonalllayerswithcopper.Flooding
with copper will reduce the temperature rise of power
components. You can connect the copper areas to any
DC net (Pꢂ , Sꢂ , ꢂ , PGND, SGND, or any other
IN
IN ꢁUT
DC rail in your system).
Top
Bottom
Figure 3. LTC3412A Layout Diagram
V
IN
3.3V
C
FF
22pF X5R
R1 392k
C
**
IN3
100µF
1
16
SV
IN
PV
IN
R
C
IN1
PG
100k
22µF
2
3
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
ITH
17.4k
C
330pF X7R
ITH
I
TH
C
47pF
C
LTC3412A
EFE
L1*
0.47µH
PGND
PGND
SW
V
2.5V
3A
4
5
OUT
V
FB
R2
69.8k
R3
115k
R
T
R
294k
OSC
SYNC/MODE
6
7
R
SS
C
**
OUT
2.2M
100µF
RUN
SW
C
×2
SS
1000pF X7R
8
SGND
PV
IN
C
IN2
22µF
GND
X5R 6.3V
3412 F04
*VISHAY IHLP-2525CZ-01
**TDK 4532X5R0J107M
Figure 4. 3.3V to 2.5V, 3A Regulator at 1MHz, Burst Mode Operation
3412aff
15
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LTC3412A
TYPICAL APPLICATIONS
1.2V, 3A, 1.5MHz 1mm Height Regulator Using All Ceramic Capacitors
V
IN
3.3V
C1 22pF X5R
R1 95.3k
11
10
SV
IN
PV
IN
C
IN1
R
PG
10µF
100k
12
13
9
8
7
6
5
4
3
X5R 6.3V
PGOOD
PGOOD
SW
SW
R
ITH
6.34k
C
ITH
1000pF X7R
I
TH
C
22pF
C
LTC3412A
EUF
L1*
PGND
PGND
SW
0.47µH
V
1.2V
3A
14
15
OUT
V
FB
R2
187k
R
T
R
196k
OSC
16
1
C
22µF
X3
**
OUT
R
SS
SYNC/MODE
RUN
2.2M
SW
C
SS
1000pF X7R
2
SGND
PV
IN
C
IN2
10µF
X5R 6.3V
GND
3412 TA01
*COOPER SD10-R47
**TAIYO YUDEN AMK212BJ226MD-B
1.8V, 3A Step-Down Regulator at 1MHz, Burst Mode Operation
V
IN
2.5V
C1 47pF X5R
C
**
IN3
100µF
R1 232k
1
16
SV
IN
PV
IN
C
IN1
R
PG
22µF
100k
X5R 6.3V
2
3
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
C
820pF X7R ITH
15k
ITH
I
TH
C2
47pF
LTC3412A
EFE
L1
PGND
PGND
SW
0.47µH*
V
1.8V
3A
4
5
OUT
V
FB
R2
69.8k
R3
115k
R
T
R
294k
OSC
C
**
OUT
6
7
R
100µF
SS
SYNC/MODE
RUN
2.2M
×3
SW
C
SS
1000pF X7R
8
SGND
PV
IN
C
IN2
22µF
X5R 6.3V
GND
3412 TA02
*VISHAY IHLP-2525CZ-01
**TDK C4532X5R0J107M
3412aff
16
For more information www.linear.com/LTC3412A
LTC3412A
TYPICAL APPLICATIONS
3.3V, 3A Step-Down Regulator at 2MHz, Forced Continuous Mode Operation
V
IN
5V
C
**
IN3
C1 22pF X5R
R1 634k
100µF
1
16
SV
IN
PV
IN
C
IN1
R
PG
22µF
100k
2
3
4
15
14
13
12
11
10
9
X5R 6.3V
PGOOD
PGOOD
SW
SW
R
ITH
7.5k
C
820pF X7R
ITH
I
TH
C
47pF
C
LTC3412A
EFE
L1*
PGND
PGND
SW
0.47µH
V
3.3V
3A
OUT
V
FB
R2
200k
5
R
T
R
137k
OSC
6
7
C
**
OUT
SYNC/MODE
RUN
100µF
×2
SW
C
R
SS
SS
1000pF X7R
2.2M
8
SGND
PV
IN
C
IN2
22µF
X5R 6.3V
GND
3412 TA03
*VISHAY IHLP-2525CZ-01
**TDK C4532X5R0J107M
2.5V, 3A Step-Down Regulator Synchronized to 1.8MHz
V
IN
3.3V
C1 22pF X5R
R1 392k
1
16
SV
IN
PV
IN
C
IN1
R
PG
22µF
100k
2
3
15
14
13
12
11
10
9
X5R 6.3V
PGOOD
PGOOD
SW
SW
R
ITH
6.49k
C
220pF X7R
ITH
I
TH
LTC3412A
EFE
C
22pF
C
L1*
PGND
PGND
SW
0.47µH
V
1.5V
3A
4
5
OUT
V
FB
R2 162k
182k
R
T
R
OSC
+
6
7
C
**
1.8MHz
OUT
R
SS
SYNC/MODE
RUN
150µF
EXT CLOCK
2.2M
SW
C
SS
1000pF X7R
8
SGND
PV
IN
C
IN2
22µF
X5R 6.3V
GND
3412 TA04
*COOPER SD20-R47
**SANYO POSCAP 4TPE150MAZB
3412aff
17
For more information www.linear.com/LTC3412A
LTC3412A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3412A#packaging for the most recent package drawings.
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation BA
4.90 – 5.10*
(.193 – .201)
2.74
(.108)
2.74
(.108)
16 1514 13 12 1110
9
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
6.40
(.252)
BSC
SEE NOTE 4
2.74
(.108)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BA) TSSOP REV L 0117
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692 Rev Ø)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.35 × 45° CHAMFER
0.75 ±0.05
4.00 ±0.10
(4 SIDES)
R = 0.115
TYP
15
16
0.72 ±0.05
0.55 ±0.20
PIN 1
TOP MARK
(NOTE 6)
1
2
4.35 ±0.05
2.90 ±0.05
2.15 ±0.05
(4 SIDES)
2.15 ±0.10
(4-SIDES)
PACKAGE
OUTLINE
(UF16) QFN 10-04
0.200 REF
0.30 ±0.05
0.65 BSC
0.30 ±0.05
0.65 BSC
0.00 – 0.05
NOTE:
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3412aff
18
For more information www.linear.com/LTC3412A
LTC3412A
REVISION HISTORY (Revision history begins at Rev E)
REV
DATE
DESCRIPTION
PAGE NUMBER
E
03/10 Changed Temperature Range for E- and I-Grades to –40°C to 125°C in Absolute Maximum Ratings and ꢁrder
Information Sections
2
Changed from T = 25°C to T ≈ T = 25°C in the Electrical Characteristics Heading
3
3
2
A
A
J
Updated Note 2
05/17 Add Storage Temperature to Absolute Maximum Ratings
F
3412aff
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3412A
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1878
600mA (I ), 550kHz, Synchronous Step-Down DC/DC Converter 96ꢀ Efficiency, ꢂ : 2.7ꢂ to 6ꢂ, ꢂ
= 0.8ꢂ, I = 10µA
ꢁUT(MIN) Q
ꢁUT
IN
I
<1µA, MS8 Package
SD
LTC1879
1.20A (I ), 550kHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, ꢂ : 2.7ꢂ to 10ꢂ, ꢂ
SD
= 0.8ꢂ, I = 15µA,
Q
ꢁUT
IN
ꢁUT(MIN)
ꢁUT(MIN)
I
<1µA, TSSꢁP16 Package
LT1934/LT1934-1
LTC3404
300mA (I ), Constant ꢁff-Time, High Efficiency Step-Down
90ꢀ Efficiency, ꢂ : 3.2ꢂ to 34ꢂ, ꢂ
= 1.25ꢂ, I = 14µA,
Q
ꢁUT
IN
DC/DC Converter
I
<1µA, ThinSꢁT™ Package
SD
600mA (I ), 1.4MHz, Synchronous Step-Down DC/DC Converter 95ꢀ Efficiency, ꢂ : 2.7ꢂ to 6ꢂ, ꢂ
= 0.8ꢂ, I = 10µA,
Q
ꢁUT
IN
ꢁUT(MIN)
I
<1µA, MS8 Package
SD
LTC3405/LTC3405A 300mA (I ), 1.5MHz, Synchronous Step-Down DC/DC Converter 95ꢀ Efficiency, ꢂ : 2.5ꢂ to 5.5ꢂ, ꢂ
= 0.8ꢂ, I = 20µA,
Q
ꢁUT
IN
ꢁUT(MIN)
ꢁUT(MIN)
ꢁUT(MIN)
I
<1µA, ThinSꢁT Package
SD
LTC3406/LTC3406B 600mA (I ), 1.5MHz, Synchronous Step-Down DC/DC Converter 96ꢀ Efficiency, ꢂ : 2.5ꢂ to 5.5ꢂ, ꢂ
= 0.6ꢂ, I = 20µA,
Q
ꢁUT
IN
I
<1µA, ThinSꢁT Package
SD
LTC3407
LTC3411
LTC3412
LTC3413
LTC3414
LTC3416
LTC3418
LT3430
Dual 600mA (I ), 1.5MHz, Synchronous Step-Down
95ꢀ Efficiency, ꢂ : 2.5ꢂ to 5.5ꢂ, ꢂ
= 0.6ꢂ, I = 40µA,
Q
ꢁUT
IN
DC/DC Converter
I
<1µA, MS10E and 3mm × 3mm DFN Packages
SD
1.25A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, ꢂ : 2.5ꢂ to 5.5ꢂ, ꢂ
= 0.8ꢂ, I = 60µA,
Q
ꢁUT
IN
ꢁUT(MIN)
ꢁUT(MIN)
I
<1µA, MS10 and 3mm × 3mm DFN Packages
SD
2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, ꢂ : 2.5ꢂ to 5.5ꢂ, ꢂ
= 0.8ꢂ, I = 60µA,
Q
ꢁUT
IN
I
<1µA, TSSꢁP16E Package
SD
3A (I
Sink/Source), 2MHz, Monolithic Synchronous Regulator
90ꢀ Efficiency, ꢂ : 2.25ꢂ to 5.5ꢂ, ꢂ
= ꢂ
,
ꢁUT
IN
ꢁUT(MIN)
REF/2
for DDR/QDR Memory Termination
I = 280µA, I <1µA, TSSꢁP16E Package
Q SD
4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, ꢂ : 2.25ꢂ to 5.5ꢂ, ꢂ
= 0.8ꢂ, I =
Q
ꢁUT
IN
ꢁUT(MIN)
ꢁUT(MIN)
ꢁUT(MIN)
64µA, I <1µA, TSSꢁP20E Package
SD
4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, ꢂ : 2.25ꢂ to 5.5ꢂ, ꢂ
= 0.8ꢂ, I =
Q
ꢁUT
IN
64µA, I <1µA, TSSꢁP20E Package
SD
8A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, ꢂ : 2.25ꢂ to 5.5ꢂ, ꢂ
= 0.8ꢂ, I =
Q
ꢁUT
IN
380µA, I <1µA, QFN Package
SD
60ꢂ, 2.75A (I ), 200kHz, High Efficiency Step-Down
90ꢀ Efficiency, ꢂ : 5.5ꢂ to 60ꢂ, ꢂ
= 1.20ꢂ, I =
ꢁUT
IN
ꢁUT(MIN) Q
DC/DC Converter
2.5mA, I 25µA, TSSꢁP16E Package
SD
LTC3440
LTC3441
LTC3548
600mA (I ), 2MHz, Synchronous Buck-Boost DC/DC Converter
95ꢀ Efficiency, ꢂ : 2.5ꢂ to 5.5ꢂ, ꢂ : 2.5ꢂ to 5.5ꢂ, I =
IN ꢁUT Q
ꢁUT
25µA, I <1µA, DFN Package
SD
1.2A (I ), 1MHz, Synchronous Buck-Boost DC/DC Converter
95ꢀ Efficiency, ꢂ : 2.4ꢂ to 5.5ꢂ, ꢂ : 2.4ꢂ to 5.25ꢂ, I =
IN ꢁUT Q
ꢁUT
25µA, I <1µA, DFN Package
SD
400mA/800mA Dual Synchronous Step-Down DC/DC Converter
95ꢀ Efficiency, ꢂ : 2.5ꢂ to 5.5ꢂ, ꢂ
SD
= 0.6ꢂ, I <40µA,
ꢁUT(MIN) Q
IN
I
<1µA, MS8E and DFN Packages
3412aff
LT 0517 REV F • PRINTED IN USA
www.linear.com/LTC3412A
20
LINEAR TECHNOLOGY CORPORATION 2005
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