LTC3417AEFE#TRPBF [Linear]
LTC3417A - Dual Synchronous 1.5A/1A 4MHz Step-Down DC/DC Regulator; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C;
| 型号： | LTC3417AEFE#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3417A - Dual Synchronous 1.5A/1A 4MHz Step-Down DC/DC Regulator; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C 稳压器 |
| 文件： | 总20页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3417
Dual Synchronous
1.4A/800mA 4MHz
Step-Down DC/DC Regulator
U
FEATURES
DESCRIPTIO
The LTC®3417 is a dual constant frequency, synchronous
step-down DC/DC converter. Intended for medium power
applications,itoperatesfroma2.25Vto5.5Vinputvoltage
range and has a constant programmable switching fre-
quency, allowing the use of tiny, low cost capacitors and
inductors 2mm or less in height. Each output voltage is
adjustable from 0.8V to 5V. Internal synchronous low
RDS(ON) power switches provide high efficiency without
the need for external Schottky diodes.
■
High Efficiency: Up to 95%
■
1.4A/800mA Guaranteed Minimum Output Current
■
No Schottky Diodes Required
■
Programmable Frequency Operation: 1.5MHz or
Adjustable From 0.6MHz to 4MHz
■
Low RDS(ON) Internal Switches
■
Short-Circuit Protected
■
VIN: 2.25V to 5.5V
■
Current Mode Operation for Excellent Line and Load
Transient Response
A user selectable mode input allows the user to trade off
ripple voltage for light load efficiency. Burst Mode® opera-
tion provides high efficiency at light loads, while Pulse
Skipmodeprovideslowripplenoiseatlightloads.Aphase
mode pin allows the second channel to operate in-phase
or 180° out-of-phase with respect to channel 1. Out-of-
phase operation produces lower RMS current on VIN and
thus lower RMS derating on the input capacitor.
■
125µA Quiescent Current in Sleep Mode
■
Ultralow Shutdown Current: IQ < 1µA
■
Low Dropout Operation: 100% Duty Cycle
■
Power Good Output
■
Phase Pin Selects 2nd Channel Phase Relationship
with Respect to 1st Channel
■
Internal Soft-Start with Individual Run Pin Control
■
Available in Small Thermally Enhanced
(5mm × 3mm) DUFN and 20-Lead TSSOP Packages
To further maximize battery life, the P-channel MOSFETs
are turned on continuously in dropout (100% duty cycle)
and both channels draw a total quiescent current of only
125µA. In shutdown, the device draws <1µA.
APPLICATIO S
■
PDAs/Palmtop PCs
■
Digital Cameras
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466,
6611131, 6144194
■
Cellular Phones
■
PC Cards
■
Wireless and DSL Modems
U
OUT2 Efficiency
TYPICAL APPLICATIO
(Burst Mode Operation)
V
IN
100
95
90
85
80
75
70
10
REFER TO FIGURE 4
2.5V TO 5.5V
10µF
V
IN
1
FREQ
SW1
EFFICIENCY
1.5µH
2.2µH
V
V
OUT2
OUT1
1.8V
1.4A
SW2
2.5V
0.1
22pF
511k
22pF
866k
800mA
RUN2
V
IN
V
RUN1
IN
LTC3417
GND
0.01
0.001
0.0001
V
V
FB2
FB1
POWER LOSS
22µF
412k
10µF
412k
V
V
= 3.6V
= 2.5V
I
I
IN
OUT
TH2
TH1
5.9k
2200pF
2.87k
FREQ = 1MHz
0.001
0.01
0.1
1
6800pF
LOAD CURRENT (A)
3417 TA01
3417 TA01a
3417fb
1
LTC3417
ABSOLUTE AXI U RATI GS
VIN1, VIN2 Voltages ..................................... –0.3V to 6V
MODE, SW1, SW2, RUN1,
RUN2, VFB1, VFB2, PHASE, FREQ,
ITH1, ITH2 Voltages ............. –0.3V to (VIN1/VIN2 + 0.3V)
VIN1 – VIN2, VIN2 – VIN1 ......................................... 0.3V
PGOOD Voltage .......................................... –0.3V to 6V
W W
U W
(Note 1)
Operating Ambient Temperature Range
(Note 2) .................................................. –40°C to 85°C
Junction Temperature (Notes 7, 8) ...................... 125°C
Storage Temperature Range
DFN Package ................................... –65°C to 125°C
TSSOP Package............................... –65°C to 150°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
TOP VIEW
NUMBER
GNDD
RUN1
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
GNDD
PGND1
SW1
RUN1
1
2
3
4
5
6
7
8
16 PGND1
15 SW1
LTC3417EDHC
LTC3417EFE
V
V
IN1
IN1
I
14 PHASE
13 GNDA
12 FREQ
11 PGOOD
10 SW2
I
PHASE
GNDA
FREQ
TH1
TH1
V
V
FB1
FB1
17
21
V
V
FB2
FB2
I
I
PGOOD
SW2
TH2
TH2
RUN2
RUN2
DHC PART MARKING
3417
V
9
MODE
V
MODE
PGND2
IN2
IN2
PGND2 10
DHC PACKAGE
16-LEAD (3mm × 5mm) PLASTIC DFN
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 43°C/ W
EXPOSED PAD (PIN 17) IS PGND2/GNDD
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 38°C/ W
EXPOSED PAD (PIN 21) IS PGND2/GNDD
MUST BE SOLDERED TO PCB
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C.
A
V
= 3.6V unless otherwise specified. (Note 2)
IN
SYMBOL
, V
PARAMETER
CONDITIONS
= V
MIN
TYP
MAX
5.5
UNITS
V
V
Operating Voltage Range
Feedback Pin Input Current
Feedback Voltage
V
●
●
2.25
IN1 IN2
IN1
IN2
I
, I
(Note 3)
(Note 3)
± 0.1
0.816
0.2
µA
V
FB1 FB2
V
, V
0.784
0.8
FB1 FB2
∆V
Reference Voltage Line Regulation. %/V is the
V
= 2.25V to 5V (Note 3)
IN
0.04
%/V
LINEREG
LOADREG
m(EA)
Percentage Change in V
with a Change in V
OUT
IN
V
Output Voltage Load Regulation
I
I
, I
= 0.36V (Note 3)
= 0.84V (Note 3)
0.02
–0.02
0.2
–0.2
%
%
TH1 TH2
, I
TH1 TH2
g
Error Amplifier Transconductance
I
, I
= ±5µA (Note 3)
1400
µS
TH1 TH2(PINLOAD)
3417fb
2
LTC3417
ELECTRICAL CHARACTERISTICS
The
IN
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C.
A
V
= 3.6V unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Input DC Supply Current (Note 4)
Active Mode
S
V
V
= V = 0.75V, V
= V ,
400
600
µA
FB1
FB2
MODE
IN
= V
= V
RUN1
RUN2
IN
Half Active Mode (V
Half Active Mode (V
= 0V, 1.4A Only)
V
V
= 0.75V, V
= 0.75V, V
= V , V
= V
= V
260
260
125
400
400
250
µA
µA
µA
RUN2
RUN1
FB1
FB2
MODE
IN RUN1
IN
IN
= 0V, 800mA Only)
= V , V
IN RUN2
MODE
Both Channels in Sleep Mode
V
V
= V = 1V, V
= V ,
MODE IN
FB1
FB2
= V
= V
RUN1
RUN2
RUN2
IN
IN
Shutdown
V
RUN1
= V
= 0V
0.1
1
µA
f
Oscillator Frequency
V
V
V
= V
1.2
0.85
1.5
1
1.8
1.25
4
MHz
MHz
MHz
OSC
FREQ
: R = 143k
FREQ
FREQ
T
: Resistor (Note 6)
I
I
Peak Switch Current Limit on SW1 (1.4A)
Peak Switch Current Limit on SW2 (800mA)
1.8
1
2.25
1.2
A
A
LIM1
LIM2
R
SW1 Top Switch On-Resistance (1.4A)
SW1 Bottom Switch On-Resistance
V
IN1
V
IN1
= 3.6V (Note 5)
= 3.6V (Note 5)
0.088
0.084
Ω
Ω
DS(ON)1
R
SW2 Top Switch On-Resistance (800mA)
SW2 Bottom Switch On-Resistance
V
IN2
V
IN2
= 3.6V (Note 5)
= 3.6V (Note 5)
0.16
0.15
Ω
Ω
DS(ON)2
I
I
Switch Leakage Current SW1 (1.4A)
Switch Leakage Current SW2 (800mA)
Undervoltage Lockout Threshold
V
V
= 6V, V
= 6V, V
= 0V, V
= 0V, V
= 0V
0.01
0.01
1
1
µA
µA
V
V
SW1(LKG)
SW2(LKG)
IN1
IN2
ITH1
ITH2
RUN1
= 0V
RUN2
V
V , V Ramping Down
IN1 IN2
1.9
1.95
2.07
2.12
2.2
2.25
UVLO
V
, V Ramping Up
IN1 IN2
T
Threshold for Power Good. Percentage
V
FB1
V
FB1
or V Ramping Up, V
= 0V
–6
–6
%
%
PGOOD
FB2
MODE
Deviation from V Steady State
or V Ramping Down, V
= 0V
FB
FB2
MODE
(Typically 0.8V)
R
Power Good Pull-Down On-Resistance
RUN1, RUN2 Threshold
160
300
1.5
Ω
V
PGOOD
V
V
, V
0.3
0.85
RUN1 RUN2
PHASE
PHASE Threshold High-CMOS Levels
PHASE Threshold Low-CMOS Levels
V
–0.5
V
IN
0.5
1
V
I
I
, I
, I
,
RUN1, RUN2, PHASE and MODE
Leakage Current
V
IN
= 6V, PV = 3V
0.01
µA
RUN1 RUN2
IN
PHASE MODE
VTL
MODE Threshold Voltage Low
MODE Threshold Voltage High
FREQ Threshold Voltage High
0.5
V
V
V
MODE
VTH
VTH
V
V
–0.5
–0.5
MODE
FREQ
IN
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: Switch on-resistance is guaranteed by design and test correlation
on the DHC package and by final test correlation on the FE package.
Note 6: Variable frequency operation with resistor is guaranteed by design
but not production tested and is subject to duty cycle limitations.
Note 2: The LTC3417 is guaranteed to meet specified performance from
0°C to 85°C. Specifications over the –40°C to 85°C operating ambient
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 7: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: The LTC3417 is tested in feedback loop which servos V to the
FB1
midpoint for the error amplifier (V
= 0.6V) and V to the midpoint for
ITH1
FB2
Note 8: T is calculated from the ambient temperature, T , and power
J
A
the error amplifier (V
= 0.6V).
ITH2
dissipation, P , according to the following formula:
D
Note 4: Total supply current is higher due to the internal gate charge being
delivered at the switching frequency.
LTC3417EDHC: T = T + (P • 43°C/W)
J
A
D
LTC3417EFE: T = T + (P • 38°C/W)
J
A
D
3417fb
3
LTC3417
U W
TYPICAL PERFOR A CE CHARACTERISTICS
OUT1 Pulse Skipping
OUT1 Forced Continuous
Mode Operation
OUT1 Burst Mode Operation
Mode Operation
V
V
V
OUT
20mV/DIV
OUT
OUT
20mV/DIV
20mV/DIV
I
I
I
L
L
L
250mA/DIV
250mA/DIV
250mA/DIV
3417 G01
3417 G02
3417 G03
V
V
LOAD
= 3.6V
2µs/DIV
V
V
LOAD
= 3.6V
2µs/DIV
V
= 3.6V
IN
2µs/DIV
IN
IN
= 1.8V
= 1.8V
V
= 1.8V
OUT
OUT
OUT
I
= 100mA
I
= 100mA
I
= 100mA
LOAD
REFER TO FIGURE 4
REFER TO FIGURE 4
REFER TO FIGURE 4
OUT2 Pulse Skipping
Mode Operation
OUT2 Forced Continuous
Mode Operation
OUT2 Burst Mode Operation
V
V
V
OUT
20mV/DIV
OUT
OUT
20mV/DIV
20mV/DIV
I
I
I
L
L
L
250mA/DIV
250mA/DIV
250mA/DIV
3417 G04
3417 G05
3417 G06
V
V
LOAD
= 3.6V
2µs/DIV
V
V
LOAD
= 3.6V
2µs/DIV
V
= 3.6V
IN
2µs/DIV
IN
IN
= 2.5V
= 2.5V
V
= 2.5V
OUT
OUT
OUT
I
= 60mA
I
= 60mA
I
= 60mA
LOAD
REFER TO FIGURE 4
REFER TO FIGURE 4
REFER TO FIGURE 4
OUT1 Efficiency vs VIN
(Burst Mode Operation)
OUT1 Efficiency vs Load Current
OUT2 Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
100
V
V
= 2.5V
V
V
= 3.6V
V
OUT
= 1.8V
IN
OUT
IN
OUT
= 1.8V
= 2.5V
95
90
85
I
= 460mA
LOAD
I
= 1.4A
LOAD
Burst Mode
OPERATION
PULSE SKIP
FORCED
Burst Mode
OPERATION
PULSE SKIP
FORCED
80
75
70
CONTINUOUS
REFER TO FIGURE 4
CONTINUOUS
REFER TO FIGURE 4
REFER TO FIGURE 4
4.5 5.5
0.001
0.01
0.1
1
0.001
0.01
0.1
1
10
2
2.5
3
3.5
4
5
LOAD CURRENT (A)
LOAD CURRENT (A)
V
IN
(V)
3417 G07
3417 G08
3417 G09
3417fb
4
LTC3417
U W
TYPICAL PERFOR A CE CHARACTERISTICS
OUT2 Efficiency vs V
IN
Load Step OUT1
Load Step OUT2
(Pulse Skipping Mode)
100
95
I
= 250mA
LOAD
V
V
OUT2
100mV/DIV
OUT1
100mV/DIV
I
= 800mA
LOAD
90
85
I
I
OUT2
500mA/DIV
OUT1
500mA/DIV
80
75
70
3417 G11
3417 G12
V
V
I
= 3.6V
100µs/DIV
V
V
I
= 3.6V
100µs/DIV
IN
OUT
IN
OUT
V
= 2.5V
OUT
= 1.8V
= 2.5V
REFER TO FIGURE 4
= 0.25A to 1.4A
= 0.25A to 0.8A
LOAD
LOAD
4
4.5 5.5
5
2
2.5
3
3.5
REFER TO FIGURE 4
REFER TO FIGURE 4
V
(V)
IN
3417 G10
Efficiency vs Frequency OUT1
Efficiency vs Frequency OUT2
R
vs V OUT1
DS(ON) IN
94
92
90
0.105
0.100
0.095
0.090
0.085
0.080
T
= 27°C
A
T
27°C
A =
V
V
= 3.6V
IN
= 1.8V
= 300mA
85
OUT
OUT
I
P-CHANNEL SWITCH
90
88
80
75
86
84
82
70
65
60
T
= 27°C
A
V
V
= 3.6V
IN
= 2.5V
= 100mA
OUT
OUT
N-CHANNEL SWITCH
2.5 3.5
I
0
1
2
3
4
5
0
1
2
3
4
2
3
4
4.5
5
5.5
FREQUENCY (MHz)
FREQUENCY (MHz)
V
(V)
IN
3417 G13
3417 G14
3417 G15
R
vs V OUT2
Frequency vs V
IN
Frequency vs Temperature
DS(ON)
IN
15
10
5
0.20
0.19
0.18
0.17
6
4
T
= 27°C
A
FREQ = V
IN
2
FREQ = 143k TO GROUND
P-CHANNEL SWITCH
0
0
–2
–4
–6
–8
–10
FREQ = 143k TO GROUND
–5
–10
–15
0.16
0.15
0.14
FREQ = V
IN
N-CHANNEL SWITCH
50
TEMPERATURE (˚C)
100 125
–50 –25
0
25
75
4
5
5.5
2
3.5
V
5
5.5
2
2.5
3
3.5
V
4.5
2.5
3
4
4.5
(V)
(V)
IN
IN
3417 G17
3417 G18
3417 G16
3417fb
5
LTC3417
U
U
U
PI FU CTIO S (DFN/TSSOP)
RUN1 (Pin 1/Pin 2): Enable for 1.4A Regulator. When at
Logic 1, 1.4A regulator is running. When at 0V, 1.4A
regulator is off. When both RUN1 and RUN2 are at 0V, the
part is in shutdown.
SW2 (Pin 10/Pin 13): Switch Node Connection to the
Inductor for the 800mA Regulator. This pin swings from
VIN2 to PGND2.
PGOOD (Pin 11/Pin 14): Power Good Pin. This common
drain-logic output is pulled to GND when the output
voltage of either regulator is –6% of regulation. If either
RUN1 or RUN2 is low (the respective regulator is in sleep
mode and therefore the output voltage is low), then
PGOOD reflects the regulation of the running regulator.
VIN1 (Pin 2/Pin 3): Supply Pin for P-Channel Switch of
1.4A Regulator.
ITH1 (Pin 3/Pin 4): Error Amplifier Compensation Point for
1.4A Regulator. The current comparator threshold in-
creases with this control voltage. Nominal voltage range
for this pin is 0V to 1.5V.
FREQ (Pin 12/Pin 15): Frequency Set Pin. When FREQ is
at VIN, internal oscillator runs at 1.5MHz. When a resistor
isconnectedfromthispintoground,theinternaloscillator
frequency can be varied from 0.6MHz to 4MHz.
VFB1 (Pin 4/Pin 5): Receives the feedback voltage from
external resistive divider across the 1.4A regulator output.
Nominal voltage for this pin is 0.8V.
GNDA (Pin 13/Pin 16): Analog Ground Pin for Internal
Analog Circuitry.
VFB2 (Pin 5/Pin 6): Receives the feedback voltage from
external resistive divider across the 800mA regulator
output. Nominal voltage for this pin is 0.8V.
PHASE (Pin 14/Pin 17): Selects 800mA regulator switch-
ing phase with respect to 1.4A regulator switching. Set to
VIN, the 1.4A regulator and the 800mA regulator are in
phase. When PHASE is at 0V, the 1.4A regulator and the
800mAregulatorareswitching180degreesout-of-phase.
ITH2 (Pin 6/Pin 7): Error Amplifier Compensation Point for
800mA regulator. The current comparator threshold in-
creases with this control voltage. Nominal voltage range
for this pin is 0V to 1.5V.
SW1 (Pin 15/Pin 18): Switch Node Connection to the
Inductorforthe1.4ARegulator. ThispinswingsfromVIN1
to PGND1.
RUN2 (Pin 7/Pin 8): Enable for 800mA Regulator. When
at Logic 1, 800mA regulator is running. When at 0V,
800mA regulator is off. When both RUN1 and RUN2 are at
0V, the part is in shutdown.
PGND1 (Pin 16/Pin 19): Ground for SW1 N-Channel
Driver.
VIN2 (Pin 8/Pin 9): Supply Pin for P-Channel Switch of
800mA Regulator and Supply for Analog Circuitry.
PGND2, GNDD (Pins 1,10,11,20): TSSOP Package Only.
Ground for SW2 N-channel driver and digital ground for
circuit.
MODE (Pin 9/Pin 12): Mode Selection Pin. This pin
controls the operation of the device. When the voltage on
the MODE pin is >(VIN – 0.5V), Burst Mode operation is
selected. When the voltage on the MODE pin is <0.5V,
pulse skipping mode is selected. When the MODE pin is
held at VIN/2, forced continuous mode is selected.
Exposed Pad (Pin 17/Pin 21): PGND2, GNDD. Ground for
SW2 N-channel driver and digital ground for circuit. The
Exposed Pad must be soldered to PCB ground.
3417fb
6
LTC3417
U
U W
FU CTIO AL DIAGRA
1.4A REGULATOR
I
V
IN1
TH1
I
TH
LIMIT
+
–
+
+
–
V
FB1
–
V
B
SLOPE
COMPENSATION
+
–
0.752V
ANTI-SHOOT-
THROUGH
SW1
+
+
–
LOGIC
–
0.848V
–
+
PGND1
PGOOD
RUN1
VOLTAGE
REFERENCE
V
IN2
RUN2
MODE
PHASE
FREQ
OSCILLATOR
PGND2
+
–
–
+
0.848V
–
+
LOGIC
–
+
SW2
ANTI-SHOOT-
THROUGH
0.752V
SLOPE
COMPENSATION
–
+
–
V
V
B
–
+
FB2
+
I
TH
LIMIT
I
V
IN2
TH2
800mA REGULATOR
3417 BD
3417fb
7
LTC3417
U
OPERATIO
The LTC3417 uses a constant frequency, current mode
architecture. Both channels share the same clock fre-
quency. The PHASE pin sets whether the channels are
runningin-phaseoroutofphase. Theoperatingfrequency
is determined by connecting the FREQ pin to VIN for
1.5MHz operation or by connecting a resistor from FREQ
to ground for a frequency from 0.6MHz to 4MHz. To suit
a variety of applications, the MODE pin allows the user to
trade off noise for efficiency.
Low Current Operation
Three modes are available to control the operation of the
LTC3417 at low currents. Each of the three modes auto-
matically switch from continuous operation to the se-
lected mode when the load current is low.
To optimize efficiency, Burst Mode operation can be
selected. When the load is relatively light, the LTC3417
automaticallyswitchesintoBurstModeoperationinwhich
the PMOS switches operate intermittently based on load
demand. By running cycles periodically, the switching
losses, which are dominated by the gate charge losses of
the power MOSFETs, are minimized. The main control
loop is interrupted when the output voltage reaches the
desired regulated value. The hysteresis voltage compara-
tor trips when ITH is below 0.24V, shutting off the switch
and reducing the power. The output capacitor and the
inductor supply the power to the load until ITH exceeds
0.31V, turning on the switch and the main control loop
which starts another cycle.
The output voltages are set by external dividers returned
to the VFB1 and VFB2 pins. An error amplifier compares the
dividedoutputvoltagewithareferencevoltageof0.8Vand
adjusts the peak inductor current accordingly. Undervolt-
age comparators will pull the PGOOD output low when
either output voltage is 6% below its targeted value.
Main Control Loop
For each regulator, during normal operation, the P-chan-
nel MOSFET power switch is turned on at the beginning of
a clock cycle when the VFB voltage is below the reference
voltage. The current into the inductor and the load in-
creases until the current limit is reached. The switch turns
off and energy stored in the inductor flows through the
bottom N-channel MOSFET switch into the load until the
next clock cycle.
For lower output voltage ripple at low currents, pulse
skipping mode can be used. In this mode, the LTC3417
continues to switch at constant frequency down to very
low currents, where it will begin skipping pulses used to
control the power MOSFETs.
Finally, in forced continuous mode, the inductor current is
constantly cycled creating a fixed output voltage ripple at
all output current levels. This feature is desirable in tele-
communications since the noise is a constant frequency
and is thus easy to filter out. Another advantage of this
mode is that the regulator is capable of both sourcing
current into a load and sinking some current from the
output.
The peak inductor current is controlled by the voltage on
the ITH pin, which is the output of the error amplifier. This
amplifier compares the VFB pin to the 0.8V reference.
WhentheloadcurrentincreasestheVFB voltagedecreases
slightly below the reference. This decrease causes the
error amplifier to increase the ITH voltage until the average
inductor current matches the new load current.
The main control loop is shut down by pulling the RUN pin
to ground. A digital soft-start is enabled after shutdown,
which will slowly ramp the peak inductor current up over
1024 clock cycles.
ThemodeselectionfortheLTC3417issetusingtheMODE
pin. The MODE pin sets the mode for both the 800mA and
the 1.4A step-down DC/DC converters.
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LTC3417
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OPERATIO
Dropout Operation
Low Supply Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100%. In this
dropout condition, the PMOS switch is turned on continu-
ously with the output voltage being equal to the input
voltage minus the voltage drops across the internal P-
channel MOSFET and inductor.
TheLTC3417incorporatesanundervoltagelockoutcircuit
which shuts down the part when the input voltage drops
below about 2.07V to prevent unstable operation.
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APPLICATIO S I FOR ATIO
160
140
120
100
A general LTC3417 application circuit is shown in
Figure 4. External component selection is driven by the
load requirement, and begins with the selection of the
inductors L1 and L2. Once L1 and L2 are chosen, CIN,
COUT1 and COUT2 can be selected.
80
60
Operating Frequency
40
20
0
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
FREQUENCY (MHz)
3417 F01
Figure 1. Frequency vs R
T
Theoperatingfrequency, fO, oftheLTC3417isdetermined
by pulling the FREQ pin to VIN for 1.5MHz operation or by
connecting an external resistor from FREQ to ground. The
value of the resistor sets the ramp current that is used to
charge and discharge an internal timing capacitor within
the oscillator and can be calculated by using the following
equation:
⎛
⎞
VOUT
fO(MAX) ≈ 6.67
MHz
(
)
⎜
⎟
V
⎝
⎠
IN(MAX)
The minimum frequency is limited by leakage and noise
coupling due to the large resistance of RT.
Inductor Selection
1.61•1011
Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current, ∆IL, decreases with
RT =
Ω –16.586kΩ
( )
fO
higher inductance and increases with higher VIN or VOUT
.
for 0.6MHz ≤ fO ≤ 4MHz. Alternatively, use Figure 1 to
select the value for RT.
VOUT
fO •L ⎝
⎛
⎜
VOUT
V
IN
⎞
∆IL =
1–
The maximum operating frequency is also constrained by
the minimum on-time and duty cycle. This can be calcu-
lated as:
⎟
⎠
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses and lower output current capability.
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APPLICATIO S I FOR ATIO
A reasonable starting point for setting ripple current is
∆IL = 0.35ILOAD(MAX), where ILOAD(MAX) is the maximum
current output. The largest ripple, ∆IL, occurs at the
maximum input voltage. To guarantee that the ripple
current stays below a specified maximum, the inductor
value should be chosen according to the following equa-
tion:
radiatedfield/EMIrequirementsthanonwhattheLTC3417
requires to operate. Table 1 shows some typical surface
mount inductors that work well in LTC3417 applications.
Input Capacitor (CIN) Selection
Incontinuousmode, theinputcurrentoftheconvertercan
be approximated by the sum of two square waves with
duty cycles of approximately VOUT1/VIN and VOUT2/VIN. To
prevent large voltage transients, a low equivalent series
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. Some capacitors have a de-
rating spec for maximum RMS current. If the capacitor
being used has this requirement, it is necessary to calcu-
late the maximum RMS current. The RMS current calcu-
lation is different if the part is used in “in phase” or “out of
phase”.
⎛
⎞
VOUT
fO • ∆IL
VOUT
V
IN(MAX)
L =
1–
⎜
⎟
⎝
⎠
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation be-
gins when the peak inductor current falls below a level set
by the burst clamp. Lower inductor values result in higher
ripple current which causes this to occur at lower load
currents. This causes a dip in efficiency in the upper range
of low current operation. In Burst Mode operation, lower
inductor values will cause the burst frequency to increase.
For “in phase”, there are two different equations:
V
OUT1 > VOUT2
IRMS = 2 •I1 •I2 •D2(1–D1)+ I2 (D2 –D22)+ I1 (D1–D1 )
VOUT2 > VOUT1
:
2
2
2
Inductor Core Selection
Different core materials and shapes will change the size/
current relationship of an inductor. Toroid or shielded pot
cores in ferrite or permalloy materials are small and don’t
radiate much energy, but generally cost more than pow-
dered iron core inductors with similar electrical character-
istics. The choice of which style inductor to use often
depends more on the price vs size requirements of any
:
2
2
2
IRMS = 2 •I1 •I2 •D1(1–D2)+ I2 (D2 –D22)+ I1 (D1–D1 )
where:
VOUT1
V
IN
VOUT2
V
IN
D1=
and D2 =
Table 1
MANUFACTURER
L1 on OUT1
Toko
PART NUMBER
VALUE (µH)
MAX DC CURRENT (A)
DCR
DIMENSIONS L × W × H (mm)
A920CY-1R5M-D62CB
A918CY-1R5M-D62LCB
1.5
1.5
2.8
2.9
0.014 6 × 6 × 2.5
0.018 6 × 6 × 2
Coilcraft
Sumida
DO1608C-152ML
1.5
2.6
0.06
6.6 × 4.5 × 2.9
CDRH4D22/HP 1R5
CDRH2D18/HP 1R7
1.5
1.7
3.9
1.8
0.031 5 × 5 × 2.4
0.035 3.2 × 3.2 × 2
Midcom
L2 on OUT2
Toko
DUP-1813-1R4R
1.4
5.5
0.033 4.3 × 4.8 × 3.5
A915AY-2R0M-D53LC
DO1608C-222ML
2.0
2.2
3.9
2.3
0.027 5 × 5 × 3
Coilcraft
Sumida
0.07
6.6 × 4.5 × 2.9
CDRH3D16/HP 2R2
CDRH2D18/HP 2R2
2.2
2.2
1.75
1.6
0.047 4 × 4 × 1.8
0.035 3.2 × 3.2 × 2
Midcom
DUP-1813-2R2R
2.2
3.9
0.047 4.3 × 4.8 × 3.5
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When D1 = D2 then the equation simplifies to:
Output Capacitor (COUT1 and COUT2) Selection
The selection of COUT1 and COUT2 is driven by the required
ESR to minimize voltage ripple and load step transients.
Typically, once the ESR requirement is satisfied, the
capacitance is adequate for filtering. The output ripple
(∆VOUT) is determined by:
IRMS = I + I D 1–D
(
)
(
)
1
2
or
VOUT V – V
(
)
IN
OUT
IRMS = I + I
(
)
1
2
V
IN
⎛
⎝
1
⎞
∆VOUT ≈ ∆I ESR
+
⎜
⎟
⎠
L
COUT
8 • fO •COUT
where the maximum average output currents I1 and I2
equal the respective peak currents minus half the peak-to-
peak ripple currents:
wherefO=operatingfrequency,COUT=outputcapacitance
and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage, since ∆IL increases
with input voltage. With ∆IL = 0.35ILOAD(MAX), the output
ripple will be less than 100mV at maximum VIN and fO =
1MHz with:
∆IL1
2
∆IL2
2
I1 = ILIM1
I2 = ILIM2
–
–
ESRCOUT < 150mΩ
These formula have a maximum at VIN = 2VOUT, where
IRMS = (I1 + I2)/2. This simple worst case is commonly
used to determine the highest IRMS
Once the ESR requirements for COUT have been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement, except for an all ceramic solution.
.
For “out of phase” operation, the ripple current can be
lower than the “in phase” current.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Alumi-
num electrolytic, special polymer, ceramic and dry tanta-
lum capacitors are all available in surface mount pack-
ages. The OS-CON semiconductor dielectric capacitor
available from Sanyo has the lowest ESR(size) product of
any aluminum electrolytic at a somewhat higher price.
Special polymer capacitors, such as Sanyo POSCAP, offer
very low ESR, but have a lower capacitance density than
other types. Tantalum capacitors have the highest capaci-
tance density, but it has a larger ESR and it is critical that
the capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surface tantalums, available in case heights ranging from
2mm to 4mm. Aluminum electrolytic capacitors have a
significantly larger ESR, and are often used in extremely
cost-sensitive applications provided that consideration is
In the “out of phase” case, the maximum IRMS does not
occurwhenVOUT1=VOUT2. Themaximumtypicallyoccurs
when VOUT1 – VIN/2 = VOUT2 or when VOUT2 – VIN/2 =
VOUT1. As a good rule of thumb, the amount of worst case
ripple is about 75% of the worst case ripple in the “in
phase” mode. Also note that when VOUT1 = VOUT2 = VIN/2
and I1 = I2, the ripple is zero.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours lifetime. This makes it
advisable to further derate the capacitor, or choose a
capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet the size
or height requirements of the design. An additional 0.1µF
to 1µF ceramic capacitor is also recommended on VIN for
high frequency decoupling, when not using an all ceramic
capacitor solution.
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instantaneously supply the current to support the load
untilthefeedbackloopraisestheswitchcurrentenoughto
support the load. The time required for the feedback loop
to respond is dependent on the compensation compo-
nentsandtheoutputcapacitorsize. Typically, 3to4cycles
are required to respond to a load step, but only in the first
cycle does the output drop linearly. The output droop,
given to ripple current ratings and long term reliability.
Ceramic capacitors have the lowest ESR and cost but also
have the lowest capacitance density, high voltage and
temperature coefficient and exhibit audible piezoelectric
effects. In addition, the high Q of ceramic capacitors along
with trace inductance can lead to significant ringing. Other
capacitor types include the Panasonic specialty polymer
(SP) capacitors.
V
DROOP,isusuallyabout2to3timesthelineardroopofthe
first cycle. Thus, a good place to start is with the output
capacitor size of approximately:
In most cases, 0.1µF to 1µF of ceramic capacitors should
also be placed close to the LTC3417 in parallel with the
main capacitors for high frequency decoupling.
∆IOUT
COUT ≈ 2.5
fO • VDROOP
Ceramic Input and Output Capacitors
More capacitance may be required depending on the duty
cycle and load step requirements.
Higher value, lower cost ceramic capacitors are now
becomingavailableinsmallercasesizes.Thesearetempt-
ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generatesaloop“zero”at5kHzto50kHzthatisinstrumen-
tal in giving acceptable loop phase margin. Ceramic ca-
pacitors remain capacitive to beyond 300kHz and usually
resonate with their ESL before ESR becomes effective.
Also, ceramic capacitors are prone to temperature effects
which require the designer to check loop stability over the
operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used. A good selection of
ceramiccapacitorsisavailablefromTaiyoYuden,TDKand
Murata.
In most applications, the input capacitor is merely re-
quired to supply high frequency bypassing, since the
impedance to the supply is very low. A 10µF ceramic
capacitor is usually enough for these conditions.
Setting the Output Voltage
The LTC3417 develops a 0.8V reference voltage between
the feedback pins, VFB1 and VFB2, and the signal ground as
shown in Figure 4. The output voltages are set by two
resistive dividers according to the following formulas:
R1
R2
⎛
⎝
⎞
⎟
⎠
VOUT1 ≈ 0.8V 1+
⎜
R3
R4
⎛
⎝
⎞
⎟
⎠
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires,suchasfromawalladapter,aloadstepattheoutput
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, the ringing at the input can be large enough to
damage the part.
VOUT2 ≈ 0.8V 1+
⎜
Keeping the current small (<5µA) in these resistors maxi-
mizes efficiency, but making the current too small may
allow stray capacitance to cause noise problems and
reduce the phase margin of the error amp loop.
To improve the frequency response, a feed-forward ca-
pacitor, CF, may also be used. Great care should be taken
toroutetheVFB nodeawayfromnoisesources,suchasthe
inductor or the SW line.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must fulfill a charge storage require-
ment. During a load step, the output capacitor must
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tors. The availability of the ITH pin not only allows optimi-
zation of the control loop behavior, but also provides a DC
coupled and AC filtered closed-loop response test point.
The DC step, rise time, and settling at this test point truly
reflects the closed-loop response. Assuming a predomi-
nantly second order system, phase margin and/or damp-
ing factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated using the percentage of overshoot seen at this
pin or by examining the rise time at this pin.
V
RUN
2V/DIV
V
OUT
1V/DIV
I
L
1A/DIV
V
V
R
= 3.6V
= 1.8V
= 0.9Ω
200µs/DIV
IN
OUT
L
Figure 2. Digital Soft-Start Out1
The ITH external components shown in the Figure 4 circuit
will provide an adequate starting point for most applica-
tions. TheseriesRCfiltersetsthedominantpole-zeroloop
compensation. The values can be modified slightly (from
0.5to2timestheirsuggestedvalues)tooptimizetransient
response once the final PC layout is done and the particu-
lar output capacitor type and value have been determined.
The output capacitors need to be selected because of
various types and values determine the loop feedback
factor gain and phase. An output current pulse of 20% to
100% of full load current having a rise time of 1µs to 10µs
willproduceoutputvoltageandITH pinwaveformsthatwill
give a sense of overall loop stability without breaking the
feedback loop.
Soft-Start
Soft-start reduces surge currents from VIN by gradually
increasing the peak inductor current. Power supply se-
quencing can also be accomplished by controlling the ITH
pin. The LTC3417 has an internal digital soft-start for each
regulator output, which steps up a clamp on ITH over 1024
clock cycles, as can be seen in Figures 2 and 3. As the
voltage on ITH ramps through its operating range, the
internal peak current limit is also ramped at a proportional
linear rate.
Mode Selection
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT
The MODE pin provides mode selection. Connecting this
pin to VIN enables Burst Mode operation for both regula-
tors, which provides the best low current efficiency at the
cost of a higher output voltage ripple. When MODE is
connected to ground, pulse skipping operation is selected
for both regulators, which provides the lowest output
voltage and current ripple at the cost of low current
efficiency. Applying a voltage that is more than 1V from
either supply results in forced continuous mode for both
regulators, which creates a fixed output ripple and allows
the sinking of some current (about 1/2∆IL). Since the
switching noise is constant in this mode, it is also the
easiest to filter out. In many cases, the output voltage can
besimplyconnectedtotheMODEpin, selectingtheforced
continuous mode except at start-up.
immediatelyshiftsbyanamountequalto∆ILOAD•ESRCOUT
,
where ESRCOUT is the effective series resistance of COUT
.
∆ILOAD also begins to charge or discharge COUT generat-
ing a feedback error signal used by the regulator to return
VOUT to its steady-state value. During this recovery time,
V
RUN
2V/DIV
V
OUT
1V/DIV
I
L
0.5A/DIV
V
V
= 3.6V
= 2.5V
= 2Ω
200µs/DIV
Checking Transient Response
IN
OUT
L
R
TheITH pincompensationallowsthetransientresponseto
be optimized for a wide range of loads and output capaci-
Figure 3. Digital Soft-Start Out2
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VOUT canbemonitoredforovershootorringingthatwould
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A Hot SwapTM controller is
designedspecificallyforthispurposeandusuallyincorpo-
rates current limiting, short-circuit protection, and soft-
starting.
indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phasemargin.ThegainoftheloopincreaseswithRITH and
the bandwidth of the loop increases with decreasing CITH
.
Efficiency Considerations
If RITH is increased by the same factor that CITH is de-
creased, the zero frequency will be kept the same, thereby
keeping the phase the same in the most critical frequency
range of the feedback loop. In addition, feedforward ca-
pacitors, C1 and C2, can be added to improve the high
frequency response, as shown in Figure 4. Capacitor C1
providesphaseleadbycreatingahighfrequencyzerowith
R1 which improves the phase margin for the 1.4A SW1
channel. Capacitor C2 provides phase lead by creating a
high frequency zero with R3 which improves the phase
margin for the 800mA SW2 channel.
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100. It
is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
% Efficiency = 100% – (P1+ P2 + P3 +…)
whereP1,P2,etc.aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources account for most of the losses
in LTC3417 circuits: 1) LTC3417 IS current, 2) switching
losses, 3) I2R losses, 4) other losses.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Linear
Technology Application Note 76.
1) The IS current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. IS current results in a small (<0.1%)
loss that increases with VIN, even at no load.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage VIN drops toward VOUT, the load step capa-
bility does decrease due to the decreasing voltage across
the inductor. Applications that require large load step
capability near dropout should use a different topology
such as SEPIC, Zeta, or single inductor, positive buck
boost.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
fromswitchingthegatecapacitanceofthepowerMOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge moves from VIN to ground.
The resulting charge over the switching period is a current
out of VIN that is typically much larger than the DC bias
current.ThegatechargelossesareproportionaltoVIN and
thus their effects will be more pronounced at higher
supply voltages.
In some applications, a more severe transient can be
caused by switching in loads with large (>1µF) input
capacitors.Thedischargedinputcapacitorsareeffectively
put in parallel with COUT, causing a rapid drop in VOUT. No
regulator can deliver enough current to prevent this prob-
Hot Swap is a trademark of Linear Technology Corporation.
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3) I2R losses are calculated from the DC resistances of the
internal switches, RSW, and the external inductor, RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the internal top
and bottom switches. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows:
To prevent the LTC3417 from exceeding its maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
TRISE = PD • θJA
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
I2R losses = IOUT2(RSW + RL)
where RL is the resistance of the inductor.
As an example, consider the case when the LTC3417 is in
dropout in both regulators at an input voltage of 3.3V with
load currents of 1.4A and 800mA. From the Typical
Performance Characteristics graph of Switch Resistance,
the RDS(ON) resistance of the 1.4A P-channel switch is
0.09Ω and the RDS(ON) of the 800mA P-channel switch is
0.163Ω. The power dissipated by the part is:
4)Other“hidden”lossessuchascoppertraceandinternal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that CIN has adequate
charge storage and very low ESRCOUT at the switching
frequency.Otherlossesincludingdiodeconductionlosses
during dead-time and inductor core losses generally ac-
count for less than 2% total additional loss.
PD = I12 • RDS(ON)1 + I22 • RDS(ON)2
PD = 1.42 • 0.09 + 0.82 • 0.163
PD = 281mW
The DFN package junction-to-ambient thermal resistance,
θJA, is about 43°C/W. Therefore, the junction temperature
of the regulator operating in a 70°C ambient temperature
is approximately:
Thermal Considerations
The LTC3417 requires the package Exposed Pad (PGND2/
GNDD pin) to be well soldered to the PC board. This gives
the DFN and TSSOP packages exceptional thermal prop-
erties, compared to similar packages of this size, making
it difficult in normal operation to exceed the maximum
junction temperature of the part. In a majority of applica-
tions, theLTC3417doesnotdissipatemuchheatduetoits
high efficiency. However, in applications where the
LTC3417 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperatureofthepart.Ifthejunctiontemperaturereaches
approximately 150°C, both switches in both regulators
will be turned off and the SW nodes will become high
impedance.
TJ = 0.281 • 43 + 70
TJ = 82.1°C
Remembering that the above junction temperature is
obtained from an RDS(ON) at 25°C, we might recalculate
the junction temperature based on a higher RDS(ON) since
it increases with temperature. However, we can safely
assume that the actual junction temperature will not
exceed the absolute maximum junction temperature of
125°C.
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Design Example
COUT selection is based on load step droop instead of ESR
requirements. For a 5% output droop:
As a design example, consider using the LTC3417 in a
portable application with a Li-Ion battery. The battery
providesaVINfrom2.5Vto4.2V.Oneoutputrequires1.8V
at 1.3A in active mode, and 1mA in standby mode. The
other output requires 2.5V at 700mA in active mode, and
500µA in standby mode. Since both loads still need power
in standby, Burst Mode operation is selected for good low
load efficiency (MODE = VIN).
1.3A
COUT1 = 2.5•
COUT2 = 2.5•
= 24µF
= 9.3µF
1.5MHz 5%•1.8V
(
)
0.7A
1.5MHz 5%• 2.5V
(
)
The closest standard values are 22µF and 10µF.
First, determine what frequency should be used. Higher
frequency results in a lower inductor value for a given ∆IL
(∆IL is estimated as 0.35ILOAD(MAX)). Reasonable values
for wire wound surface mount inductors are usually in the
range of 1µH to 10µH.
Theoutputvoltagescannowbeprogrammedbychoosing
the values of R1, R2, R3, and R4. To maintain high
efficiency, the current in these resistors should be kept
small. Choosing 2µA with the 0.8V feedback voltages
makes R2 and R4 equal to 400k. A close standard 1%
resistor is 412k. This then makes R1 = 515k. A close
standard 1% is 511k. Similarily, with R4 at 412k, R3 is
equal to 875k. A close 1% resistor is 866k.
CONVERTER OUTPUT
I
∆I
L
LOAD(MAX)
SW1
SW2
1.4A
490mA
280mA
800mA
The compensation should be optimized for these compo-
nents by examining the load step response, but a good
place to start for the LTC3417 is with a 5.9kΩ and 2200pF
filter on ITH1 and 2.87k and 6800pF on ITH2. The output
capacitor may need to be increased depending on the
actual undershoot during a load step.
Using the 1.5MHz frequency setting (FREQ = VIN), we get
the following equations for L1 and L2:
1.8V
1.8V
4.2V
⎛
⎞
L1=
1–
= 1.4µH
= 2.4µH
⎜
⎝
⎟
⎠
1.5MHz • 490mA
The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate
speed. Figure 4 shows a complete schematic for this
design.
Use 1.5µH.
2.5V
1.5MHz • 280mA
Use 2.2µH.
2.5V
4.2V
⎛
⎝
⎞
⎠
L2 =
1–
⎜
⎟
3417fb
16
LTC3417
U
W U U
APPLICATIO S I FOR ATIO
V
IN
2.25V TO 5.5V
C
C
C
R7
100k
IN
IN1
IN2
10µF
0.1µF
0.1µF
V
V
IN1 IN2
L1
1.5µH
L2
2.2µH
MODE
PGOOD
V
V
OUT2
OUT1
1.8V
2.5V
SW1
SW2
C1 22pF
C2 22pF
R3 866k
1.4A
800mA
V
V
RUN1
RUN2
IN
IN
LTC3417
R1 511k
V
FB1
V
FB2
C
C
OUT2
10µF
R2
412k
R4
412k
OUT1
22µF
V
IN
PHASE
FREQ
I
I
TH2
TH1
EXPOSED
GNDA PAD GNDD
R5
5.9k
R6
2.87k
C3
2200pF
C4
6800pF
3417 F04
L1: MIDCOM DUS-5121-1R5R
: KEMET C1210C226K8PAC
L2: MIDCOM DUS-5121-2R2R
C , C : KEMET C1206C106K4PAC
OUT2 IN
C
OUT1
OUT1 Efficiency vs Load Current
100
10
V
V
= 3.6V
IN
OUT
= 1.8V
FREQ = 1MHz
95
90
REFER TO FIGURE 4
1
EFFICIENCY
0.1
0.01
0.001
85
80
POWER LOSS
75
70
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
3417 F04a
Figure 4. 1.8V at 1.4A/2.5V at 800mA Step-Down Regulators
3417fb
17
LTC3417
U
W U U
APPLICATIO S I FOR ATIO
Board Layout Considerations
must be connected between the (+) plate of COUT2 and
a ground line terminated near GNDA. The feedback
signalsVFB1 andVFB2 shouldberoutedawayfromnoise
components and traces, such as the SW lines, and its
trace should be minimized.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3417. These items are also illustrated graphically in
the layout diagram of Figure 5. Check the following in your
layout.
4. Keep sensitive components away from the SW pins.
The input capacitor CIN, the compensation capacitors
CC1, CC2, CITH1 and CITH2 and all resistors R1, R2, R3,
R4,RITH1andRITH2 shouldberoutedawayfromtheSW
traces and the inductors L1 and L2.
1
. Does the capacitor CIN connect to the power VIN1
(Pin 2), VIN2 (Pin 8), and PGND2/GNDD (Pin 17) as
close as possible (DFN package)? It may be necessary
tosplitCINintotwocapacitors.Thiscapacitorprovides
the AC current to the internal power MOSFETs and
their drivers.
5. Agroundplaneispreferred,butifnotavailable,keepthe
signal and power grounds segregated with small signal
components returning to the GNDA pin at one point
which is then connected to the PGND2/GNDD pin.
2. AretheCOUT1,L1 andCOUT2,L2 closelyconnected?The
(–) plate of COUT1 returns current to PGND1, and the
(–) plate of COUT2 returns current to the PGND2/GNDD
and the (–) plate of CIN.
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. These copper areas should be
connected to one of the input supplies.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT1 and a ground line
terminated near GNDA. The resistor divider, R3 and R4,
V
IN
V
V
IN1
IN2
C
C
C
IN1
0.1µF
IN
IN2
10µF
0.1µF
PGND2/
EXPOSED PAD
PGND1
GNDA
SW2
C
V
C
V
OUT2
OUT2
OUT1
OUT1
L2
L1
SW1
C
C2
C
C1
R3
R4
R1
R2
LTC3417
V
V
FB1
FB2
STAR TO
GNDA
STAR TO
GNDA
R
R
ITH2
ITH1
R7
I
I
TH2
TH1
C
C
ITH1
ITH2
R8
V
IN
PGOOD
FREQ
V
RUN2
RUN1
MODE
IN
PHASE
GNDD
Figure 5
3417fb
18
LTC3417
U
PACKAGE DESCRIPTIO
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
R = 0.115
TYP
0.40 ± 0.10
5.00 ±0.10
(2 SIDES)
9
16
R = 0.20
TYP
0.65 ±0.05
3.50 ±0.05
1.65 ±0.05
3.00 ±0.10 1.65 ± 0.10
PACKAGE
OUTLINE
2.20 ±0.05 (2 SIDES)
(2 SIDES)
(2 SIDES)
PIN 1
PIN 1
NOTCH
TOP MARK
(DHC16) DFN 1103
(SEE NOTE 6)
8
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50 BSC
0.50 BSC
4.40 ±0.10
4.40 ±0.05
(2 SIDES)
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
4.95
(.195)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
2.74
(.108)
SEE NOTE 4
(.252)
BSC
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP 0204
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3417fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC3417
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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3A (I
Sink/Source), 2MHz, Monolithic Synchronous
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OUT
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600mA (I ), 2MHz, Synchronous Buck-Boost DC/DC
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< 1µA, MS/DFN Packages
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600mA (I ), 2MHz, Synchronous Buck-Boost DC/DC
95% Efficiency, V : 2.5V to 5.5V, V
= 2.4V, I = 25µA,
Q
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< 1µA, DFN Package
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1.2A (I ), 600kHz, Synchronous Buck-Boost DC/DC
95% Efficiency, V : 2.4V to 5.5V, V
= 2.4V, I = 28µA,
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< 1µA, MS Package
SD
1.5MHz/2.25MHz, 600mA Synchronous Step-Down DC/DC
Converter with LDO Mode
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 32µA,
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IN
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< 1µA, DFN/MS8E
SD
Dual 800mA and 400mA (I ), 2.25MHz, Synchronous
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40µA,
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ThinSOT is a trademark of Linear Technology Corporation.
3417fb
LT 0506 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
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