LTC3417AEFE-1#TRPBF [Linear]
LTC3417A-1 - Dual Synchronous 1.5A/1A 4MHz Step-Down DC/DC Regulator with POR; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C;
| 型号： | LTC3417AEFE-1#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3417A-1 - Dual Synchronous 1.5A/1A 4MHz Step-Down DC/DC Regulator with POR; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C 稳压器 |
| 文件： | 总20页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3417A-1
Dual Synchronous
1.5A/1A 4MHz Step-Down
DC/DC Regulator with POR
DESCRIPTION
FEATURES
The LTC®3417A-1 is a dual constant frequency, synchro-
nous step-down DC/DC converter. Intended for medium
power applications, it operates from a 2.25V to 5.5V input
voltagerangeandhasaconstantprogrammableswitching
frequency, allowing the use of tiny, low cost capacitors
and inductors 2mm or less in height. Each output voltage
is adjustable from 0.8V to 5V. Internal synchronous, low
n
High Efficiency: Up to 95%
n
1.5A/1A Guaranteed Minimum Output Current
n
Synchronizable to External Clock
n
Power-On-Reset Output
No Schottky Diodes Required
n
n
Programmable Frequency Operation: 1.5MHz or
Adjustable From 0.6MHz to 4MHz
Low Ripple (< 35mV ) BurstMode® Operation
n
R
power switches provide high efficiency without
DS(ON)
P-P
n
the need for external Schottky diodes.
Low R
Internal Switches
DS(ON)
Short-Circuit Protected
n
n
n
The open drain POR pin goes low when either output
voltage falls 6% below regulation. The output will remain
low 150ms longer than the duration of the out of regula-
tion condition.
V : 2.25V to 5.5V
IN
Current Mode Operation for Excellent Line and Load
Transient Response
n
n
n
n
125μA Quiescent Current in Sleep Mode
A user selectable mode input allows the user to trade
off ripple voltage for light load efficiency. Burst Mode
operation provides high efficiency at light loads, while
pulse skip mode provides low ripple noise at light loads.
A phase mode pin allows the second channel to operate
in-phase or 180° out-of-phase with respect to channel 1.
Out-of-phase operation produces lower RMS current on
Ultralow Shutdown Current: I < 1μA
Q
Low Dropout Operation: 100% Duty Cycle
Phase Pin Selects 2nd Channel Phase Relationship
with Respect to 1st Channel
n
n
Internal Soft-Start with Individual Run Pin Control
Available in Small Thermally Enhanced
(3mm × 5mm) DFN and 20-Lead TSSOP Packages
V and thus lower stress on the input capacitor.
IN
APPLICATIONS
To further maximize battery life, the P-channel MOSFETs
are turned on continuously in dropout (100% duty cycle)
and both channels draw a total quiescent current of only
100μA. In shutdown, the device draws <1μA.
L, LT, LTC and LTM and Burst Mode are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by U.S.
Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6144194.
n
GPS/Navigation Systems
n
Automotive Instrumentation
n
PC Cards
Industrial Power Supplies
General Purpose Point of Load DC/DC
n
n
OUT2 Efficiency
TYPICAL APPLICATION
(Burst Mode Operation)
V
100
95
90
85
80
75
70
10
IN
REFER TO FIGURE 4
2.5V TO 5.5V
10μF
100k
V
IN
1
RESET
POR
FREQ
SW1
EFFICIENCY
1.5μH
2.2μH
V
V
2.5V
1A
OUT1
1.8V
1.5A
OUT2
SW2
22pF
511k
22pF
0.1
RUN2
V
RUN1
V
IN
IN
LTC3417A-1
866k
0.01
0.001
0.0001
V
FB2
V
I
POWER LOSS
FB1
47μF
412k
5.9k
22μF
412k
V
V
= 3.6V
OUT
FREQ = 1MHz
I
IN
TH2
TH1
= 2.5V
2.87k
6800pF
GND
0.001
0.01
0.1
1
2200pF
LOAD CURRENT (A)
3417A-1 TA01
3417A-1 TA01a
3417a1fa
1
LTC3417A-1
(Note 1)
ABSOLUTE MAXIMUM RATINGS
POR Voltage................................................ –0.3V to 6V
V
, V Voltages...................................... –0.3V to 6V
IN1 IN2
Operating Temperature Range (Note 2)
SYNC/MODE, SW1, SW2, RUN1,
RUN2, V , V , PHASE, FREQ,
LTC3417AE-1 ...................................... –40°C to 85°C
LTC3417AI-1 ..................................... –40°C to 125°C
Junction Temperature (Notes 7, 8) ...................... 125°C
Storage Temperature Range................... –65°C to 150°C
FB1 FB2
I
, I
Voltages........ –0.3V to ((V or V ) + 0.3V)
– V , V – V .......................................... 0.3V
TH1 TH2 IN1 IN2
V
IN1
IN2 IN2 IN1
PIN CONFIGURATION
TOP VIEW
TOP VIEW
GNDD
RUN1
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
GNDD
PGND1
SW1
RUN1
1
2
3
4
5
6
7
8
16 PGND1
15 SW1
14 PHASE
13 GNDA
12 FREQ
11 POR
V
V
IN1
IN1
I
PHASE
GNDA
FREQ
I
TH1
TH1
V
V
FB1
FB1
21
17
V
V
FB2
FB2
I
POR
I
TH2
TH2
RUN2
SW2
RUN2
10 SW2
V
SYNC/MODE
PGND2
V
9
SYNC/MODE
IN2
IN2
PGND2 10
DHC PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
FE PACKAGE
20-LEAD PLASTIC TSSOP
T
= 125°C, θ = 43°C/ W
JA
JMAX
EXPOSED PAD (PIN 17) IS PGND2/GNDD
MUST BE SOLDERED TO PCB
T
= 125°C, θ = 38°C/ W
JA
JMAX
EXPOSED PAD (PIN 21) IS PGND2/GNDD
MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC3417AEDHC-1#PBF
LTC3417AIDHC-1#PBF
LTC3417AEFE-1#PBF
LTC3417AIFE-1#PBF
LTC3417AEDHC-1#TRPBF
LTC3417AIDHC-1#TRPBF
LTC3417AEFE-1#TRPBF
LTC3417AIFE-1#TRPBF
3417A1
16-Lead (3mm × 5mm) Plastic DFN
16-Lead (3mm × 5mm) Plastic DFN
20-Lead Plastic TSSOP
3417A1
–40°C to 125°C
–40°C to 85°C
LTC3417AFE-1
LTC3417AFE-1
20-Lead Plastic TSSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise specified (Note 2).
SYMBOL
, V
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
V
Operating Voltage Range
Feedback Pin Input Current
V
IN1
= V
IN2
2.25
5.5
V
μA
IN1 IN2
I
, I
V = 6V Pin Under Test = 3V
IN
± 0.1
FB1 FB2
3417a1fa
2
LTC3417A-1
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise specified (Note 2).
SYMBOL
, V
PARAMETER
CONDITIONS
MIN
TYP
0.8
MAX UNITS
l
V
Feedback Voltage
(Note 3)
0.784
0.816
0.2
V
FB1 FB2
ΔV
Reference Voltage Line Regulation. %/V
V
= 2.25V to 5V (Note 3)
IN
0.02
%/V
LINEREG
is the Percentage Change in V
with a
OUT
Change in V
IN
ΔV
LOADREG
Output Voltage Load Regulation
I
, I
TH1 TH2
= 0.36V (Note 3)
= 0.84V (Note 3)
0.02
–0.02
0.2
–0.2
%
%
I
, I
TH1 TH2
g
Error Amplifier Transconductance
I
, I = 5μA (Note 3)
1400
400
μS
m(EA)
TH1 TH2(PINLOAD)
I
Input DC Supply Current (Note 4)
Active Mode
S
V
V
= V = 0.75V, V
= V ,
600
μA
FB1
FB2
SYNC/MODE
IN
= V
= V
IN
RUN1
RUN2
I
S
Half Active Mode (V
Half Active Mode (V
= 0V, 1.5A Only)
= 0V, 1A Only)
V
V
= 0.75V, V
= 0.75V, V
= V , V
= V
= V
260
260
125
400
400
250
μA
μA
μA
RUN2
FB1
FB2
SYNC/MODE
SYNC/MODE
IN RUN1
IN
= V , V
RUN1
IN RUN2
IN
Both Channels in Sleep Mode
V
V
= V = 1V, V
= V , V
IN RUN1
=
FB1
FB2
SYNCMODE
= V
RUN2
IN
Shutdown
V
= V
= 0V
0.01
1
μA
RUN1
RUN2
IN
f
Oscillator Frequency
V
V
V
= V
1.2
0.85
1.5
1
1.8
1.25
4
MHz
MHz
MHz
OSC
FREQ
FREQ
FREQ
: R = 143k
T
: Resistor (Note 6)
I
I
Peak Switch Current Limit on SW1 (1.5A)
Peak Switch Current Limit on SW2 (1A)
2.1
1.4
2.5
1.7
A
A
LIM1
LIM2
R
SW1 Top Switch On-Resistance (1.5A)
SW1 Bottom Switch On-Resistance
V
V
= 3.6V (Note 5)
= 3.6V (Note 5)
0.088
0.084
Ω
Ω
DS(ON)1
DS(ON)2
IN1
IN1
R
SW2 Top Switch On-Resistance (1A)
SW2 Bottom Switch On-Resistance
V
V
= 3.6V (Note 5)
= 3.6V (Note 5)
0.16
0.15
Ω
Ω
IN2
IN2
I
I
Switch Leakage Current SW1 (1.5A)
Switch Leakage Current SW2 (1A)
Undervoltage Lockout Threshold
V
V
= 6V, V
= 0V
= 0V
0.01
0.01
1
1
μA
μA
SW1(LKG)
IN1
IN2
RUN1
RUN2
= 6V, V
SW2(LKG)
V
V
V
, V Ramping Down
IN1 IN2
IN1 IN2
1.9
1.95
2.07
2.12
2.2
2.25
V
V
UVLO
, V Ramping Up
V
Power-On-Reset Threshold
V
or V Ramping Up
–6
–8
%
%
Ω
TH(POR)
FB1
FB1
FB2
Percentage Deviation of V Voltage from
FB
V
or V Ramping Down
FB2
Steady State Value (Typically 0.8V)
R
Power-On-Reset Pull Down On-Resistance
120
300
POR
t
Power-On-Reset De-Assertion Delay from FREQ = V
Fault Removal
212,992
Clock
Cycles
POR
IN
FREQ Tied to GND Through 143k Resistor
294,912
0.85
Clock
Cycles
V
V
V
RUN1, RUN2 Threshold
0.3
1.5
V
RUN1, RUN2
PHASE Threshold High-CMOS Levels
PHASE Threshold Low-CMOS Levels
V
IN
–0.5
V
V
PHASE
0.5
1
I
I
I
I
RUN1, RUN2, PHASE and SYNC/MODE
Leakage Current
V
= 6V, Pin Under Test = 3V
IN
0.01
μA
RUN1, RUN2, PHASE,
SYNC/MODE
VTL
SYNC/MODE Threshold Voltage Low
SYNC/MODE Threshold Voltage High
FREQ Threshold Voltage High
0.5
V
V
V
SYNC/MODE
VTH
VTH
V
V
–0.5
–0.5
SYNC/MODE
IN
FREQ
IN
3417a1fa
3
LTC3417A-1
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: Switch on-resistance is guaranteed by design and test correlation
on the DHC package and by final test correlation on the FE package.
Note 6: Variable frequency operation with resistor is guaranteed by design
but not production tested and is subject to duty cycle limitations.
Note 2: The LTC3417AE-1 is guaranteed to meet specified performance
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
ambient temperature range are assured by design, characterization
and correlation with statistical process controls. The LTC3417AI-1 is
guaranteed to meet performance specifications over the –40°C to 125°C
operating temperature range.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 8: T is calculated from the ambient temperature, T , and power
J
A
Note 3: The LTC3417A-1 is tested in feedback loop which servos V to
FB1
dissipation, P , according to the following formula:
D
the midpoint for the error amplifier (V
= 0.6V) and V to the midpoint
ITH1
FB2
LTC3417AEDHC-1: T = T + (P • 43°C/W)
J
A
D
for the error amplifier (V
= 0.6V).
ITH2
LTC3417AEFE-1: T = T + (P • 38°C/W)
J
A
D
Note 4: Total supply current is higher due to the internal gate charge being
delivered at the switching frequency.
TYPICAL PERFORMANCE CHARACTERISTICS
OUT1 Pulse Skipping
Mode Operation
OUT1 Forced Continuous
Mode Operation
OUT1 Burst Mode Operation
V
V
V
OUT
OUT
OUT
20mV/DIV
20mV/DIV
20mV/DIV
I
I
I
L
L
L
250mA/DIV
250mA/DIV
250mA/DIV
3417A-1 G01
3417A-1 G03
3417A-1 G02
V
V
I
= 3.6V
2μs/DIV
V
V
I
= 3.6V
2μs/DIV
V
V
I
= 3.6V
2μs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 1.8V
= 100mA
= 100mA
= 100mA
LOAD
LOAD
LOAD
REFER TO FIGURE 4
REFER TO FIGURE 4
REFER TO FIGURE 4
OUT2 Pulse Skipping
Mode Operation
OUT2 Forced Continuous
Mode Operation
OUT2 Burst Mode Operation
V
V
V
OUT
20mV/DIV
OUT
OUT
20mV/DIV
20mV/DIV
I
I
I
L
L
L
250mA/DIV
250mA/DIV
250mA/DIV
3417A-1 G04
3417A-1 G05
3417A-1 G06
V
V
LOAD
= 3.6V
2μs/DIV
V
V
LOAD
= 3.6V
2μs/DIV
V
V
LOAD
= 3.6V
IN
2μs/DIV
IN
IN
= 2.5V
= 2.5V
= 2.5V
OUT
OUT
OUT
I
= 60mA
I
= 60mA
I
= 60mA
REFER TO FIGURE 4
REFER TO FIGURE 4
REFER TO FIGURE 4
3417a1fa
4
LTC3417A-1
TYPICAL PERFORMANCE CHARACTERISTICS
OUT1 Efficiency vs VIN
(Burst Mode Operation)
OUT1 Efficiency vs Load Current
OUT2 Efficiency vs Load Current
100
95
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
V
= 1.8V
V
V
= 2.5V
V
V
= 3.6V
OUT
IN
OUT
IN
OUT
= 1.8V
= 2.5V
I
= 460mA
LOAD
90
I
= 1.4A
LOAD
85
Burst Mode
OPERATION
PULSE SKIP
FORCED
Burst Mode
OPERATION
PULSE SKIP
FORCED
80
75
70
CONTINUOUS
REFER TO FIGURE 4
CONTINUOUS
REFER TO FIGURE 4
REFER TO FIGURE 4
4
5
2
2.5
3
3.5
4.5
5.5
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
V
(V)
LOAD CURRENT (A)
LOAD CURRENT (A)
IN
3417A-1 G09
3417A-1 G07
3417A-1 G08
OUT2 Efficiency vs VIN
(Pulse Skipping Mode)
Load Step OUT1
Load Step OUT2
100
95
I
= 250mA
LOAD
V
V
OUT1
OUT2
100mV/DIV
100mV/DIV
I
= 800mA
LOAD
90
85
I
I
OUT1
OUT2
500mA/DIV
500mA/DIV
80
75
70
3417A-1 G11
3417A-1 G12
V
V
I
= 3.6V
100μs/DIV
V
V
I
= 3.6V
100μs/DIV
IN
OUT
IN
OUT
V
= 2.5V
OUT
= 1.8V
= 0.25A to 1.4A
= 2.5V
REFER TO FIGURE 4
= 0.25A to 0.8A
LOAD
LOAD
REFER TO FIGURE 4
4
4.5
5
2
2.5
3
3.5
REFER TO FIGURE 4
V
(V)
IN
3417A-1 G10
Efficiency vs Frequency OUT1
Efficiency vs Frequency OUT2
RDS(ON) vs VIN OUT1
0.105
0.100
0.095
0.090
0.085
0.080
94
92
90
85
T
= 27°C
T
27°C
A =
A
V
V
= 3.6V
IN
= 1.8V
OUT
OUT
I
= 300mA
P-CHANNEL SWITCH
90
88
80
75
86
84
82
70
65
60
T
= 27°C
= 3.6V
A
IN
V
V
= 2.5V
OUT
OUT
N-CHANNEL SWITCH
I
= 100mA
0
1
2
3
4
5
2
2.5
3
3.5
V
4
4.5
5
5.5
0
1
2
3
FREQUENCY (MHz)
(V)
FREQUENCY (MHz)
IN
3417A-1 G13
3417A-1 G15
3417A-1 G14
3417a1fa
5
LTC3417A-1
TYPICAL PERFORMANCE CHARACTERISTICS
RDS(ON) vs VIN OUT2
Frequency vs VIN
Frequency vs Temperature
0.20
0.19
0.18
0.17
15
10
5
6
4
T
= 27°C
A
FREQ = V
IN
2
FREQ = 143k TO GROUND
P-CHANNEL SWITCH
0
0
–2
–4
–6
–8
–10
FREQ = 143k TO GROUND
0.16
0.15
0.14
–5
–10
–15
FREQ = V
IN
N-CHANNEL SWITCH
4
5
5.5
50
TEMPERATURE (°C)
100 125
2
2.5
3
3.5
V
4.5
–50
25
75
–25
0
3.5
2
2.5
3
4
4.5
5
5.5
(V)
V
(V)
IN
IN
3417A-1 G16
3417A-1 G18
3417A-1 G17
PIN FUNCTIONS (DFN/TSSOP)
RUN1 (Pin 1/Pin 2): Enable for 1.5A Regulator. When
at Logic 1, 1.5A regulator is running. When at 0V, 1.5A
regulator is off. When both RUN1 and RUN2 are at 0V, the
part is in shutdown.
SYNC/MODE(Pin9/Pin12):CombinationModeSelection
andOscillatorSynchronizationPin.Thispincontrolstheop-
erationofthedevice.WhenthevoltageontheSYNC/MODE
pin is >(V – 0.5V), Burst Mode operation is selected.
IN
When the voltage on the SYNC/MODE pin is <0.5V, pulse
V
(Pin 2/Pin 3): Supply Pin for P-Channel Switch of
IN1
skipping mode is selected. When the SYNC/MODE pin is
1.5A Regulator.
held at V /2, forced continuous mode is selected. The
IN
I
(Pin 3/Pin 4): Error Amplifier Compensation Point
oscillation frequency can be synchronized to an external
oscillator applied to this pin. When synchronized to an
external clock, pulse skip mode is selected.
TH1
for 1.5A Regulator. The current comparator threshold
increases with this control voltage. Nominal voltage range
for this pin is 0V to 1.5V.
SW2 (Pin 10/Pin 13): Switch Node Connection to the
V
(Pin 4/Pin 5): Receives the feedback voltage from
Inductor for the 1A Regulator. This pin swings from V
FB1
IN2
external resistive divider across the 1.5A regulator output.
to PGND2.
Nominal voltage for this pin is 0.8V.
POR (Pin 11/Pin 14): The Power-On-Reset Pin. This
open drain-logic output is pulled to GND when the output
voltage of either regulator falls 8% below regulation and
goes high approximately 150ms after both regulators are
above –6% of regulation. If either RUN1 or RUN2 is low
(the respective regulator is in sleep mode and therefore
theoutputvoltageislow), thenPORreflectstheregulation
of the running regulator.
V
(Pin 5/Pin 6): Receives the feedback voltage from
FB2
external resistive divider across the 1A regulator output.
Nominal voltage for this pin is 0.8V.
I
(Pin 6/Pin 7): Error Amplifier Compensation Point for
TH2
1A regulator. The current comparator threshold increases
with this control voltage. Nominal voltage range for this
pin is 0V to 1.5V.
FREQ (Pin 12/Pin 15): Frequency Set Pin. When FREQ is
RUN2 (Pin 7/Pin 8): Enable for 1A Regulator. When at
Logic 1, 1A regulator is running. When at 0V, 1A regula-
tor is off. When both RUN1 and RUN2 are at 0V, the part
is in shutdown.
at V , internal oscillator runs at 1.5MHz. When a resistor
IN
isconnectedfromthispintoground,theinternaloscillator
frequency can be varied from 0.6MHz to 4MHz.
GNDA (Pin 13/Pin 16): Analog Ground Pin for Internal
V
(Pin 8/Pin 9): Supply Pin for P-Channel Switch of 1A
IN2
Analog Circuitry.
Regulator and Supply for Analog Circuitry.
3417a1fa
6
LTC3417A-1
PIN FUNCTIONS
PHASE (Pin 14/Pin 17): Selects 1A regulator switching
PGND1 (Pin 16/Pin 19): Ground for SW1 N-Channel Driver.
phase with respect to 1.5A regulator switching. Set to
PGND2, GNDD (Pins 1,10,11,20): TSSOP Package Only.
Ground for SW2 N-channel driver and digital ground for
circuit.
V , the 1.5A regulator and the 1A regulator are in phase.
IN
When PHASE is at 0V, the 1.5A regulator and the 1A
regulator are switching 180 degrees out-of-phase. Do
not float this pin.
Exposed Pad (Pin 17/Pin 21): PGND2, GNDD. Ground for
SW2 N-channel driver and digital ground for circuit. The
Exposed Pad must be soldered to PCB ground.
SW1 (Pin 15/Pin 18): Switch Node Connection to the
Inductor for the 1.5A Regulator. This pin swings from
V
to PGND1.
IN1
FUNCTIONAL DIAGRAM
I
V
1.5A REGULATOR
TH1
IN1
I
TH
LIMIT
+
–
–
+
+
–
V
FB1
V
B
SLOPE
COMPENSATION
+
–
0.752V
ANTI-SHOOT-
THROUGH
SW1
+
+
–
LOGIC
–
0.848V
–
+
PGND1
RUN1
RUN2
POR
VOLTAGE
REFERENCE
V
IN2
DELAY
PHASE
SYNC/MODE
OSCILLATOR
FREQ
PGND2
+
–
–
+
0.848V
–
+
LOGIC
–
+
SW2
ANTI-SHOOT-
THROUGH
0.752V
SLOPE
COMPENSATION
–
+
–
V
FB2
–
+
V
B
+
I
TH
LIMIT
I
V
IN2
TH2
1A REGULATOR
3417A-1 BD
3417a1fa
7
LTC3417A-1
OPERATION
The LTC3417A-1 uses a constant frequency, current
mode architecture. Both channels share the same clock
frequency. The PHASE pin sets whether the channels are
runningin-phaseoroutofphase. Theoperatingfrequency
Low Current Operation
Three modes are available to control the operation of the
LTC3417A-1 at low currents. Each of the three modes
automatically switch from continuous operation to the
selected mode when the load current is low.
is determined by connecting the FREQ pin to V for
IN
1.5MHz operation or by connecting a resistor from FREQ
to ground for a frequency from 0.6MHz to 4MHz. To suit
a variety of applications, the SYNC/MODE pin allows the
user to trade off noise for efficiency.
To optimize efficiency, Burst Mode operation can be se-
lected. When the load is relatively light, the LTC3417A-1
automaticallyswitchesintoBurstModeoperationinwhich
the PMOS switches operate intermittently based on load
demand. By running cycles periodically, the switching
losses, which are dominated by the gate charge losses
of the power MOSFETs, are minimized. The main control
loop is interrupted when the output voltage reaches the
desiredregulatedvalue.Thehysteresisvoltagecomparator
The output voltages are set by external dividers returned
to the V and V pins. An error amplifier compares the
FB1
FB2
dividedoutputvoltagewithareferencevoltageof0.8Vand
adjuststhepeakinductorcurrentaccordingly.Undervoltage
comparatorswillpullthePORoutputlowwheneitheroutput
voltage is 8% below its targeted value. The POR output
will go high after 212,992 cycles (when FREQ is high) or
294,912 cycles (when FREQ is tied to ground through an
external resistor), or about 150ms, after both regulators
are above -6% of the target output voltage.
trips when I is below 0.24V, shutting off the switch and
TH
reducing the power. The output capacitor and the induc-
tor supply the power to the load until I exceeds 0.31V,
TH
turning on the switch and the main control loop which
starts another cycle.
Main Control Loop
For lower output voltage ripple at low currents, pulse skip-
ping mode can be used. In this mode, the LTC3417A-1
continues to switch at constant frequency down to very
low currents, where it will begin skipping pulses used to
control the power MOSFETs.
For each regulator, during normal operation, the P-chan-
nel MOSFET power switch is turned on at the beginning
of a clock cycle when the V voltage is below the refer-
ence voltage. The current into the inductor and the load
increases until the current limit is reached. The switch
turns off and energy stored in the inductor flows through
the bottom N-channel MOSFET switch into the load until
the next clock cycle.
FB
Finally, in forced continuous mode, the inductor current is
constantlycycledcreatingafixedoutputvoltagerippleatall
output current levels. This feature is desirable in telecom-
munications since the noise is a constant frequency and is
thus easy to filter out. Another advantage of this mode is
that the regulator is capable of both sourcing current into
a load and sinking some current from the output.
The peak inductor current is controlled by the voltage
on the I pin, which is the output of the error amplifier.
TH
This amplifier compares the V pin to the 0.8V reference.
FB
WhentheloadcurrentincreasestheV voltagedecreases
The mode selection for the LTC3417A-1 is set using the
SYNC/MODE pin. The SYNC/MODE pin sets the mode for
both the1A and the 1.5A step-down DC/DC converters.
FB
slightly below the reference. This decrease causes the er-
ror amplifier to increase the I voltage until the average
TH
inductor current matches the new load current.
The main control loop is shut down by pulling the RUN pin
to ground. A digital soft-start is enabled after shutdown,
which will slowly ramp the peak inductor current up over
1024 clock cycles.
3417a1fa
8
LTC3417A-1
OPERATION
Dropout Operation
Low Supply Operation
Whentheinputsupplyvoltagedecreasestowardtheoutput
voltage, the duty cycle increases to 100%. In this dropout
condition,thePMOSswitchisturnedoncontinuouslywith
the output voltage being equal to the input voltage minus
the voltage drops across the internal P-channel MOSFET
and inductor.
The LTC3417A-1 incorporates an undervoltage lockout
circuit which shuts down the part when the input voltage
drops below about 2.07V to prevent unstable operation.
APPLICATIONS INFORMATION
160
140
120
100
A general LTC3417A-1 application circuit is shown in
Figure 4. External component selection is driven by the
load requirement, and begins with the selection of the
inductors L1 and L2. Once L1 and L2 are chosen, C ,
IN
80
60
C
OUT1
and C
can be selected.
OUT2
40
20
0
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
FREQUENCY (MHz)
3417A-1 F01
Figure 1. Frequency vs RT
ꢁ
ꢄ
VOUT
fO(MAX) ꢀ6.67
MHz
(
)
ꢃ
ꢆ
The operating frequency, f , of the LTC3417A-1 is deter-
mined by pulling the FREQ pin to V for 1.5MHz opera-
V
O
ꢂ
ꢅ
IN(MAX)
IN
tion or by connecting an external resistor from FREQ to
ground. The value of the resistor sets the ramp current
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation:
The minimum frequency is limited by leakage and noise
coupling due to the large resistance of R .
T
Inductor Selection
Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
1.61•1011
RT ≈
Ω –16.586kΩ
( )
current. The inductor ripple current, ΔI , decreases with
L
fO
higher inductance and increases with higher V or
IN
V
.
OUT
for 0.6MHz ≤ f ≤ 4MHz. Alternatively, use Figure 1 to
O
select the value for R .
T
OUT ꢁ
OUT ꢄ
V
VIN
ꢅ
V
ꢀIL =
1–
The maximum operating frequency is also constrained
by the minimum on-time and duty cycle. This can be
calculated as:
ꢃ
ꢆ
f •L
ꢂ
O
Accepting larger values of ΔI allows the use of low induc-
L
tances, but results in higher output voltage ripple, greater
core losses and lower output current capability.
3417a1fa
9
LTC3417A-1
APPLICATIONS INFORMATION
A reasonable starting point for setting ripple current is
ΔIL = 0.35ILOAD(MAX), where ILOAD(MAX) is the maximum
currentoutput. Thelargestripple, ΔIL, occursatthemaxi-
mum input voltage. To guarantee that the ripple current
stays below a specified maximum, the inductor value
should be chosen according to the following equation:
typical surface mount inductors that work well in
LTC3417A-1 applications.
Input Capacitor (C ) Selection
IN
Incontinuousmode, theinputcurrentoftheconvertercan
be approximated by the sum of two square waves with
duty cycles of approximately V
/V and V
/V . To
OUT2 IN
ꢁ
ꢄ
OUT1 IN
VOUT
fO • ꢀIL
VOUT
L =
1–
prevent large voltage transients, a low equivalent series
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. Some capacitors have a
de-rating spec for maximum RMS current. If the capaci-
tor being used has this requirement, it is necessary to
calculate the maximum RMS current. The RMS current
calculation is different if the part is used in “in phase” or
“out of phase”.
ꢃ
ꢆ
V
ꢂ
ꢅ
IN(MAX)
The inductor value will also have an effect on Burst Mode
operation.Thetransitionfromlowcurrentoperationbegins
whenthepeakinductorcurrentfallsbelowalevelsetbythe
burst clamp. Lower inductor values result in higher ripple
current which causes this to occur at lower load currents.
This causes a dip in efficiency in the upper range of low
currentoperation.InBurstModeoperation,lowerinductor
values will cause the burst frequency to increase.
For “in phase”, there are two different equations:
V
> V
:
OUT1
OUT2
Inductor Core Selection
2
2
I
RMS = 2•I1 •I2 •D2(1–D1)+I2 (D2 – D22)+I12(D1– D1 )
Different core materials and shapes will change the size/
current relationship of an inductor. Toroid or shielded
pot cores in ferrite or permalloy materials are small and
don’t radiate much energy, but generally cost more than
powdered iron core inductors with similar electrical
characteristics. The choice of which style inductor to use
often depends more on the price vs size requirements
of any radiated field/EMI requirements than on what the
LTC3417A-1 requires to operate. Table 1 shows some
V
> V
:
OUT1
OUT2
2
2
I
RMS = 2•I1 •I2 •D1(1–D2)+I2 (D2 – D22)+I12(D1– D1 )
where:
VOUT1
VOUT2
D1=
and D2 =
V
V
IN
IN
Table 1
MANUFACTURER
L1 on OT1
Toko
PART NUMBER
VALUE (μH)
MAX DC CURRENT (A)
DCR
DIMENSIONS L × W × H (mm)
A920CY-1R5M-D62CB
A918CY-1R5M-D62LCB
1.5
1.5
2.8
2.9
0.014
0.018
6 × 6 × 2.5
6 × 6 × 2
Coilcraft
Sumida
Midcom
L2 on OUT2
Toko
D01608C-152ML
CDRH4D22/HP 1R5
DUP-1813-1R4R
1.5
1.5
1.4
2.6
3.9
5.5
0.06
0.031
0.033
6.6 × 4.5 × 2.9
5 × 5 × 2.4
4.3 × 4.8 × 3.5
A915AY-2ROM-D53LC
D01608C-222ML
2.0
2.2
3.9
2.3
0.027
0.07
5 × 5 × 3
Coilcraft
Sumida
6.6 × 4.5 × 2.9
CDRH3D16/HP 2R2
2.2
2.2
1.75
1.6
0.047
0.035
4 × 4 × 1.8
3.2 × 3.2 × 2
Midcom
DUP-1813-2R2R
2.2
3.9
0.047
4.3 × 4.8 × 3.5
3417a1fa
10
LTC3417A-1
APPLICATIONS INFORMATION
When D1 = D2 then the equation simplifies to:
Typically, once the ESR requirement is satisfied, the
capacitance is adequate for filtering. The output ripple
IRMS = I +I
D 1–D
(
)
(
)
1
2
(ΔV ) is determined by:
OUT
ꢂ
ꢅ
1
or
ꢀVOUT ꢁ ꢀIL ESRCOUT
+
ꢄ
ꢇ
8 • fO •C
ꢃ
OUT ꢆ
VOUT V – V
(
)
IN
OUT
IRMS = I +I
(
)
1
2
VIN
wheref =operatingfrequency, C =outputcapacitance
O OUT
and ΔI = ripple current in the inductor. The output ripple
L
where the maximum average output currents I and I
equal the respective peak currents minus half the peak-
to-peak ripple currents:
is highest at maximum input voltage, since ΔI increases
1
2
L
with input voltage. With ΔI = 0.35I
, the output
IN
L
LOAD(MAX)
ripple will be less than 100mV at maximum V and f =
O
1MHz with:
ΔIL1
I1 =ILIM1
I2 =ILIM2
–
2
ESR
< 150mΩ
COUT
ΔIL2
Once the ESR requirements for C
have been met, the
–
OUT
2
RMS current rating generally far exceeds the I
RIPPLE(P-P)
requirement, except for an all ceramic solution.
These formula have a maximum at V = 2V , where
IN
OUT
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
currenthandlingrequirementoftheapplication.Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitorsareallavailableinsurfacemountpackages.The
OS-CONsemiconductordielectriccapacitoravailablefrom
Sanyo has the lowest ESR(size) product of any aluminum
electrolytic at a somewhat higher price. Special polymer
capacitors,suchasSanyoPOSCAP,offerverylowESR,but
havealowercapacitancedensitythanothertypes.Tantalum
capacitors have the highest capacitance density, but it has
a larger ESR and it is critical that the capacitors are surge
tested for use in switching power supplies. An excellent
choiceistheAVXTPSseriesofsurfacetantalums,available
in case heights ranging from 2mm to 4mm. Aluminum
electrolytic capacitors have a significantly larger ESR, and
are often used in extremely cost-sensitive applications
provided that consideration is given to ripple current
ratings and long term reliability. Ceramic capacitors have
the lowest ESR and cost but also have the lowest capaci-
tance density, high voltage and temperature coefficient
and exhibit audible piezoelectric effects. In addition, the
high Q of ceramic capacitors along with trace inductance
can lead to significant ringing. Other capacitor types
include the Panasonic specialty polymer (SP) capacitors.
I
= (I + I )/2. This simple worst case is commonly
RMS
1 2
used to determine the highest I
.
RMS
For “out of phase” operation, the ripple current can be
lower than the “in phase” current.
In the “out of phase” case, the maximum I
does not
RMS
occur when V
= V
IN
. The maximum typically oc-
OUT2
OUT1
OUT1
OUT2
– V /2 = V
curs when V
or when V
– V /2
OUT2 IN
= V
. As a good rule of thumb, the amount of worst
OUT1
case ripple is about 75% of the worst case ripple in the
“in phase” mode. Also note that when V = V
=
OUT2
OUT1
V /2 and I = I , the ripple is zero.
IN
1
2
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours lifetime. This makes
it advisable to further derate the capacitor, or choose a
capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet the
size or height requirements of the design. An additional
0.1μF to 1μF ceramic capacitor is also recommended on
V for high frequency decoupling, when not using an all
IN
ceramic capacitor solution.
Output Capacitor (C
and C
) Selection
OUT2
OUT1
The selection of C
ESR to minimize voltage ripple and load step transients.
and C
is driven by the required
OUT2
OUT1
3417a1fa
11
LTC3417A-1
APPLICATIONS INFORMATION
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3417A-1 in parallel with
the main capacitors for high frequency decoupling.
More capacitance may be required depending on the duty
cycle and load step requirements.
Inmostapplications,theinputcapacitorismerelyrequired
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Because the
LTC3417 control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size. When choosing the input and output
ceramic capacitors, choose the X5R or X7R dielectric
formulations. These dielectrics have the best temperature
and voltage characteristics of all the ceramics for a given
value and size.
Setting the Output Voltage
TheLTC3417A-1developsa0.8Vreferencevoltagebetween
the feedback pins, V and V , and the signal ground
FB1
FB2
as shown in Figure 4. The output voltages are set by two
resistive dividers according to the following formulas:
R1
R2
ꢁ
ꢂ
ꢄ
ꢅ
VOUT1 ꢀ0.8V 1+
ꢃ
ꢆ
R3
R4
ꢁ
ꢂ
ꢄ
ꢅ
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, suchasfromawalladapter, aloadstepattheoutput
VOUT2 ꢀ0.8V 1+
ꢃ
ꢆ
Keeping the current small (<5μA) in these resistors
maximizes efficiency, but making the current too small
may allow stray capacitance to cause noise problems and
reduce the phase margin of the error amp loop.
can induce ringing at the V pin. At best, this ringing can
IN
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
To improve the frequency response, a feed-forward ca-
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must fulfill a charge storage re-
quirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation com-
ponents and the output capacitor size. Typically, 3 to 4
cycles are required to respond to a load step, but only in
the first cycle does the output drop linearly. The output
pacitor, C , may also be used. Great care should be taken
F
to route the V node away from noise sources, such as
FB
the inductor or the SW line.
Power-On Reset
ThePORpinisanopen-drainoutputwhichpullslowwhen
either regulator is out of regulation. When both output
voltages are above –6% of regulation, a timer is started
which allows the POR output to go high after 212,992
clock cycles (when FREQ is tied to V ) or 294,912 clock
IN
droop, V
, is usually about 2 to 3 times the linear
cycles (when FREQ is tied to ground through an external
resistor). This results in a delay of approximately 150ms
when the oscillator is set to 2MHz. When either channel
is shut down, the POR output reflects the condition of the
running regulator.
DROOP
droop of the first cycle. Thus, a good place to start is with
the output capacitor size of approximately:
ΔIOUT
fO • VDROOP
COUT ≈2.5
3417a1fa
12
LTC3417A-1
APPLICATIONS INFORMATION
The LTC3417A-1 can be synchronized to an external clock
signal by the SYNC/MODE pin. The internal oscillator fre-
quency should be set to 20% lower than the external clock
frequency to ensure adequate slope compensation, since
slope compensation is derived from the internal oscillator.
During synchronization, the mode is set to pulse skipping
and the top switch turn-on is synchronized to the rising
edge of the external clock.
V
RUN
2V/DIV
V
OUT
1V/DIV
I
L
1A/DIV
3417A-1 F02
V
V
R
= 3.6V
= 1.8V
= 0.9ꢀ
200μs/DIV
IN
OUT
L
When using an external clock, with the PHASE pin low, the
switching of the two channels occur at the edges of the
external clock. A 50% duty cycle will therefore produce
180° out-of-phase operation.
Figure 2. Digital Soft-Start OUT1
Soft-Start
Checking Transient Response
Soft-start reduces surge currents from V by gradu-
IN
The I pin compensation allows the transient response
TH
ally increasing the peak inductor current. Power supply
to be optimized for a wide range of loads and output
sequencing can also be accomplished by controlling the
capacitors. The availability of the I pin not only allows
TH
I
pin. The LTC3417A-1 has an internal digital soft-start
TH
optimization of the control loop behavior, but also pro-
vides a DC coupled and AC filited closed-loop response
test point. The DC step, rise time, and settling at this test
point truly reflects the closed-loop response. Assuming a
predominantlysecondordersystem,phasemarginand/or
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated using the percentage of overshoot seen at this
pin or by examining the rise time at this pin.
for each regulator output, which steps up a clamp on
TH
I
over 1024 clock cycles, as can be seen in Figures 2
and 3. As the voltage on I ramps through its operating
TH
range, the internal peak current limit is also ramped at a
proportional linear rate.
Mode Selection
TheSYNC/MODEpinisamultipurposepinwhichprovides
mode selection and frequency synchronization. Connect-
ing this pin to V enables Burst Mode operation for both
IN
regulators, which provides the best low current efficiency
at the cost of a higher output voltage ripple. When SYNC/
MODE is connected to ground, pulse skipping operation
is selected for both regulators, which provides the low-
est output voltage and current ripple at the cost of low
current efficiency. Applying a voltage that is more than
1V from either supply results in forced continuous mode
for both regulators, which creates a fixed output ripple
V
RUN
2V/DIV
V
OUT
1V/DIV
I
L
0.5A/DIV
3417A-1 F03
V
V
R
= 3.6V
= 2.5V
= 2ꢀ
200μs/DIV
IN
OUT
L
and allows the sinking of some current (about 1/2ΔI ).
L
Since the switching noise is constant in this mode, it is
also the easiest to filter out. In many cases, the output
voltage can be simply connected to the SYNC/MODE pin,
selecting the forced continuous mode except at start-up.
Figure 3. Digital Soft-Start OUT2
3417a1fa
13
LTC3417A-1
APPLICATIONS INFORMATION
The I external components shown in the Figure 4 circuit
Theoutputvoltagesettlingbehaviorisrelatedtothestability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
TH
will provide an adequate starting point for most applica-
tions. The series RC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because of various types and values determine the loop
feedback factor gain and phase. An output current pulse
of 20% to 100% of full load current having a rise time
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
inputvoltageV dropstowardV ,theloadstepcapability
IN
OUT
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta, or single inductor, positive buck boost.
of 1μs to 10μs will produce output voltage and I pin
TH
waveforms that will give a sense of overall loop stability
without breaking the feedback loop.
In some applications, a more severe transient can be
caused by switching in loads with large (>1μF) input ca-
pacitors. The discharged input capacitors are effectively
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
im-
OUT
• ESR
mediately shifts by an amount equal to ΔI
,
LOAD
COUT
put in parallel with C , causing a rapid drop in V . No
OUT
OUT
where ESR
is the effective series resistance of C
also begins to charge or discharge C
.
COUT
OUT
regulator can deliver enough current to prevent this prob-
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A Hot Swap™ controller
is designed specifically for this purpose and usually in-
corporates current limiting, short-circuit protection, and
soft- starting.
ΔI
generat-
LOAD
OUT
ing a feedback error signal used by the regulator to return
V
V
to its steady-state value. During this recovery time,
canbemonitoredforovershootorringingthatwould
OUT
OUT
indicate a stability problem.
The initial output voltage step may not be within the band-
width of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
Efficiency Considerations
margin. The gain of the loop increases with R and the
ITH
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
bandwidth of the loop increases with decreasing C . If
ITH
R
isincreasedbythesamefactorthatC isdecreased,
ITH
ITH
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, feedforward capacitors,
C1 and C2, can be added to improve the high frequency
response, as shown in Figure 4. Capacitor C1 provides
phase lead by creating a high frequency zero with R1
which improves the phase margin for the 1.5A SW1 chan-
nel. Capacitor C2 provides phase lead by creating a high
frequency zero with R3 which improves the phase margin
for the 1A SW2 channel.
% Efficiency = 100% – (P1+ P2 + P3 +…)
where P1, P2, etc. are the individual losses as a percent-
age of input power.
Hot Swap is a trademark of Linear Technology Corporation.
3417a1fa
14
LTC3417A-1
APPLICATIONS INFORMATION
Although all dissipative elements in the circuit produce
the switching frequency. Other losses including diode
conduction losses during dead-time and inductor core
lossesgenerallyaccountforlessthan2%totaladditional
loss.
losses, four main sources account for most of the losses
in LTC3417A-1 circuits: 1) LTC3417A-1 I current, 2)
S
2
switching losses, 3) I R losses, 4) other losses.
1) TheI currentistheDCsupplycurrentgivenintheelec-
S
Thermal Considerations
tricalcharacteristicswhichexcludesMOSFETdriverand
The LTC3417A-1 requires the package Exposed Pad
(PGND2/GNDD pin) to be well soldered to the PC board.
This gives the DFN and TSSOP packages exceptional
thermal properties, compared to similar packages of this
size, making it difficult in normal operation to exceed the
maximum junction temperature of the part. In a majority
of applications, the LTC3417A-1 does not dissipate much
heat due to its high efficiency. However, in applications
where the LTC3417A-1 is running at high ambient tem-
perature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both switches
in both regulators will be turned off and the SW nodes will
become high impedance.
control currents. I current results in a small (<0.1%)
S
loss that increases with V , even at no load.
IN
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge moves from
V to ground. The resulting charge over the switching
IN
periodisacurrentoutofV thatistypicallymuchlarger
IN
than the DC bias current. The gate charge losses are
proportional to V and thus their effects will be more
IN
pronounced at higher supply voltages.
2
3) I R losses are calculated from the DC resistances of the
internal switches, R , and the external inductor, R . In
SW
L
continuous mode, the average output current flowing
through inductor L is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
To prevent the LTC3417A-1 from exceeding its maximum
junctiontemperature,theuserwillneedtodosomethermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
bottom MOSFET R
follows:
and the duty cycle (DC) as
DS(ON)
R
= (R
TOP)(DC) + (R BOT)(1 – DC)
DS(ON) DS(ON)
SW
T
= P • θ
D JA
RISE
TheR
forboththetopandbottomMOSFETscanbe
DS(ON)
where P is the power dissipated by the regulator and θ
D
JA
obtained from the Typical Performance Characteristics
is the thermal resistance from the junction of the die to
2
curves. Thus, to obtain I R losses:
the ambient temperature.
2
2
I R losses = I
(R + R )
SW L
OUT
The junction temperature, T , is given by:
J
where R is the resistance of the inductor.
L
T = T
J
+ T
AMBIENT
RISE
4) Other“hidden”lossessuchascoppertraceandinternal
batteryresistancescanaccountforadditionalefficiency
degradations in portable systems. It is very important
to include these “system” level losses in the design
of a system. The internal battery and fuse resistance
As an example, consider the case when the LTC3417A-1
is in dropout in both regulators at an input voltage of 3.3V
with load currents of 1.5A and 1A. From the Typical Per-
formance Characteristics graph of Switch Resistance, the
R
resistance of the 1.5A P-channel switch is 0.09Ω
DS(ON)
losses can be minimized by making sure that C has
IN
and the R
of the 1A P-channel switch is 0.163Ω.
DS(ON)
adequate charge storage and very low ESR
at
COUT
3417a1fa
15
LTC3417A-1
APPLICATIONS INFORMATION
The power dissipated by the part is:
Using the 1.5MHz frequency setting (FREQ = V ), we get
IN
the following equations for L1 and L2:
2
2
PD = I • R
+ I • R
1
DS(ON)1
2
DS(ON)2
2
2
1.8V
1.5MHz •525mA
Use 1.5μH.
2.5V
1.5MHz •350mA
Use 2.2μH.
1.8V
4.2V
ꢀ
ꢁ
ꢃ
ꢄ
PD = 1.5 • 0.09 + 1 • 0.163
PD = 366mW
L1=
1–
=1.3μH
=1.9μH
ꢂ
ꢅ
The DFN package junction-to-ambient thermal resistance,
2.5V
4.2V
ꢀ
ꢃ
θ , is about 43°C/W. Therefore, the junction temperature
JA
L2=
1–
ꢂ
ꢅ
ꢁ
ꢄ
of the regulator operating in a 70°C ambient temperature
is approximately:
T = 0.366 • 43 + 70
J
T = 85.7°C
J
C
selection is based on load step droop instead of ESR
OUT
Remembering that the above junction temperature is
obtained from an R
the junction temperature based on a higher R
it increases with temperature. However, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
requirements. For a 2.5% output droop:
at 25°C, we might recalculate
DS(ON)
1.5A
C
OUT1 = 2.5•
OUT2 = 2.5•
= 28μF
=13μF
since
DS(ON)
1.5MHz 5%•1.8V
(
)
1A
C
1.5MHz 5%•2.5V
(
)
Design Example
The closest standard values are 47μF and 22μF.
As a design example, consider using the LTC3417A-1 in
a portable application with a Li-Ion battery. The battery
The output voltages can now be programmed by choos-
ing the values of R1, R2, R3, and R4. To maintain high
efficiency, the current in these resistors should be kept
small.Choosing2μAwiththe0.8Vfeedbackvoltagesmakes
R2 and R4 equal to 400k. A close standard 1% resistor is
412k. This then makes R1 = 515k. A close standard 1%
is 511k. Similarily, with R4 at 412k, R3 is equal to 875k.
A close 1% resistor is 866k.
provides a V from 2.8V to 4.2V. One load requires 1.8V
IN
at 1.5A in active mode, and 1mA in standby mode. The
other load requires 2.5V at 1A in active mode, and 500μA
in standby mode. Since both loads still need power in
standby, Burst Mode operation is selected for good low
load efficiency (SYNC/MODE = V ).
IN
First, determine what frequency should be used. Higher
The compensation should be optimized for these compo-
nents by examining the load step response, but a good
place to start for the LTC3417A-1 is with a 5.9kΩ and
frequency results in a lower inductor value for a given ΔI
L
(ΔI is estimated as 0.35I
). Reasonable values
L
LOAD(MAX)
for wire wound surface mount inductors are usually in the
2200pF filter on I
and 2.87k and 6800pF on I . The
TH1
TH2
range of 1μH to 10μH.
output capacitor may need to be increased depending on
the actual undershoot during a load step.
CONVERTER OUTPUT
I
ΔI
L
LOAD(MAX)
SW1
SW2
1.5A
525mA
350mA
The POR pin is an open drain output and requires a pull-
up resistor. A 100k resistor is used for adequate speed.
Figure 4 shows a complete schematic for this design.
1A
3417a1fa
16
LTC3417A-1
APPLICATIONS INFORMATION
V
IN
2.25V TO 5.5V
C
C
C
R7
100k
IN
IN1
IN2
10μF
0.1μF
0.1μF
V
V
IN1 IN2
SYNC/MODE
SW1
POR
RESET
V
V
2.5V
1A
OUT1
1.8V
OUT2
SW2
L1
L2
2.2μH
C2 22pF
1.5A
C1 22pF
1.5μH
V
V
V
RUN1
RUN2
IN
IN
IN
LTC3417A-1
R1 511k
R3 866k
V
V
FB2
FB1
C
C
OUT2
22μF
R2
412k
R4
412k
OUT1
PHASE
FREQ
47μF
I
I
TH2
TH1
EXPOSED
GNDA PAD GNDD
R5
5.9k
R6
2.87k
C3
2200pF
C4
6800pF
3417A-1 F04
L1: MIDCOM DUS-5121-1R5R
: KEMET C1210C226K8PAC
L2: MIDCOM DUS-5121-2R2R
C , C : KEMET C1206C106K4PAC
OUT2 IN
C
OUT1
OUT1 Efficiency vs Load Current
100
10
V
V
= 3.6V
IN
OUT
= 1.8V
FREQ = 1MHz
95
90
REFER TO FIGURE 4
1
EFFICIENCY
0.1
0.01
0.001
85
80
POWER LOSS
75
70
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
3417A-1 F04a
Figure 4. 1.8V at 1.5A/2.5V at 1A Step-Down Regulators
3417a1fa
17
LTC3417A-1
APPLICATIONS INFORMATION
Board Layout Considerations
must be connected between the (+) plate of C
and
OUT2
a ground line terminated near GNDA. The feedback
signalsV andV shouldberoutedawayfromnoise
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3417A-1. These items are also illustrated graphically
in the layout diagram of Figure 5. Check the following in
your layout.
FB1
FB2
components and traces, such as the SW lines, and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor C , the compensation capacitors
IN
ITH2
1
. Does the capacitor C connect to the power V
IN IN1
(Pin 2), V (Pin 8), and PGND2/GNDD (Pin 17) as
C , C , C
and C
ITH2
and all resistors R1, R2, R3,
C1 C2 ITH1
IN2
R4, R
and R
should be routed away from the
ITH1
close as possible (DFN package)? It may be necessary
SW traces and the inductors L1 and L2.
tosplitC intotwocapacitors.Thiscapacitorprovides
IN
the AC current to the internal power MOSFETs and
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GNDA pin at one
point which is then connected to the PGND2/GNDD
pin.
their drivers.
2. AretheC
,L andC
,L closelyconnected?The
OUT1
(–) plate of C
1
OUT2 2
returns current to PGND1, and the
OUT1
(–) plate of C
and the (–) plate of C .
returns current to the PGND2/GNDD
OUT2
6. Floodallunusedareasonalllayerswithcopper.Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to one of the input supplies.
IN
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
and a ground line ter-
OUT1
minated near GNDA. The resistor divider, R3 and R4,
V
IN
V
V
IN1
IN2
C
C
C
IN1
0.1μF
IN
IN2
10μF
0.1μF
PGND2/
EXPOSED PAD
PGND1
GNDA
SW2
C
V
C
V
OUT2
OUT1
OUT1
L2
L1
SW1
OUT2
C
C
C1
C2
R3
R4
R1
R2
LTC3417A-1
V
V
FB1
FB2
STAR TO
GNDA
R
R
ITH2
ITH1
R7
STAR TO
GNDA
I
I
TH2
TH1
C
C
ITH1
ITH2
R8
V
IN
POR
FREQ
V
IN
RUN2
RUN1
PHASE
SYNC/MODE
GNDD
3417A-1 F05
Figure 5. Layout Guideline
3417a1fa
18
LTC3417A-1
PACKAGE DESCRIPTION
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
R = 0.115
0.40 ± 0.10
5.00 ± 0.10
(2 SIDES)
TYP
16
9
R = 0.20
TYP
0.65 ± 0.05
3.50 ± 0.05
1.65 ± 0.05
3.00 ± 0.10 1.65 ± 0.10
PACKAGE
OUTLINE
2.20 ± 0.05 (2 SIDES)
(2 SIDES)
(2 SIDES)
PIN 1
PIN 1
TOP MARK
NOTCH
(DHC16) DFN 1103
(SEE NOTE 6)
8
1
0.25 ± 0.05
0.50 BSC
0.75 ± 0.05
0.200 REF
0.25 ± 0.05
0.50 BSC
4.40 ± 0.10
4.40 ± 0.05
(2 SIDES)
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
4.95
(.195)
20 1918 17 16 15 14 1312 11
6.60 ± 0.10
2.74
(.108)
4.50 ± 0.10
6.40
2.74
(.108)
SEE NOTE 4
(.252)
BSC
0.45 ± 0.05
1.05 ± 0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP 0204
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3417a1fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3417A-1
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ThinSOT is a trademark of Linear Technology Corporation.
3417a1fa
LT 0808 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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