LTC3445EUF#TRPBF [Linear]
LTC3445 - I<sup>2</sup>C Controllable Buck Regulator with Two LDOs in a 4mm x 4mm QFN; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC3445EUF#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3445 - I<sup>2</sup>C Controllable Buck Regulator with Two LDOs in a 4mm x 4mm QFN; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C 稳压器 |
| 文件： | 总24页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3445
2
I C Controllable
Buck Regulator with Two LDOs
in a 4mm × 4mm QFN
U
FEATURES
DESCRIPTIO
Buck Regulator
The LTC®3445 contains a high efficiency monolithic syn-
chronous current mode buck regulator, two LDO regula-
tors, a PowerPathTM controller and an I2CTM interface.
■
High Efficiency: Up to 93%
■
600mA Output Current (VCC1 = 3V, VOUT = 1.3V)
■
Programmable Output Voltage: 0.85V to 1.55V
Thebuckregulatorhasa6-bitprogrammableoutputrange
of 0.85V to 1.55V. Also, the buck regulator uses either a
constant (1.5MHz) or a spread spectrum switching fre-
quency. Using the spread spectrum option allows for a
lower noise regulated output as well as low noise at the
input. In addition, the regulated output voltage slew rate is
programmable via the I2C interface.
■
2.5V to 5.5V Input Voltage Range
1.5MHz Constant Frequency or Spread Spectrum
Option
Soft-Start
■
■
LDOs
■
Two LDO Regulators: 0.3V Dropout at 50mA
PowerPath Controller
The LTC3445 contains two LDO voltage regulators. The
regulator output voltages are externally resistor program-
mable. Each LDO is capable of delivering up to 50mA.
■
Dynamically Regulates VCC BATT
I2C
■
Standard (100kHz) or Fast Mode (400kHz)
24-Lead (4mm × 4mm) QFN Package
The LTC3445 contains control circuitry (PowerPath) for
automatic back-up battery selection. VBACKUP is typically
a coin cell.
■
U
APPLICATIO S
Typicalsupplycurrentduringoperationisonly360µAand
drops to 27µA in shutdown. The 2.5V to 5.5V input
voltage range makes the LTC3445 ideal for single Li-Ion
battery-powered applications. Automatic Burst Mode®
operation increases efficiency at light loads, further ex-
tending battery life.
■
Intel’s Microprocessor Supply (PXA27X)
■
Portable Instruments
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
PowerPath is a trademark of Linear Technology Corporation.
I2C is a trademark of Philips Electronics N.V.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466,
6611131, Spread Spectrum patent pending.
U
TYPICAL APPLICATIO
V
CC
Efficiency and Power Loss
V
BACKUP
vs Load Current, V
= 3.6V
CC1
4.7µF
CER
20k
V
V
V
CC1
CC1
CC2
100
90
80
70
60
50
40
30
20
10
0
1000
100
10
V
V
BATTFAULT
nBATT_FAULT
TRACK
V
BACKUP
EFFICIENCY
3V
COIN
CELL
3V
TYP
V
BATT
BACKUP
CC
+
4.7µF
DAC MIN
DAC MAX
CER
2.2µH
0.85V
TO 1.55V
PWR_EN
RUN
SDA
SCL
SW
FB
4.7µF
CER
2
DAC MAX
LTC3445
I C BUS
DAC MIN
1.3V
1.1V
LDO1
V
CC
10µF
CER
705k
503k
604k
604k
POWER LOSS
1.0
V
OR GND
ADD7
ADD6
CC1
CC1
LDO1FB
LDO2
20k
V
OR GND
nV _FAULT
CC
PGOOD
10µF
CER
0.1
1000
0.1
1
10
100
LDO2FB
GND
3445 TA01
LOAD CURRENT (mA)
3445 TA01b
3445fa
1
LTC3445
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
(Note 1)
VCC1, VCC2, SDA, SCL Voltages .................. –0.3V to 6V
RUN, VTRACK, VBACKUP, PGOOD, ADD7,
ADD6, FB, VCC BATT,
PACKAGE/ORDER I FOR ATIO
TOP VIEW
24 23 22 21 20 19
BATTFAULT Voltages.............................. –0.3V to VCC1
SW Voltage ................................ –0.3V to (VCC1 + 0.3V)
LDO1FB, LDO2FB Voltages ..................... –0.3V to VCC2
LDO1, LDO2 Voltages ................ –0.3V to (VCC2 + 0.3V)
LDO1, LDO2 Source Current ............................... 50mA
V
1
2
3
4
5
6
18
17
16
V
BATT
TRACK
CC
V
FB
BACKUP
V
NC
CC1
25
PGOOD
ADD7
SDA
15 RUN
SW
14
13 NC
V
CC BATT Source Current ...................................... 8mA
P-Channel Switch Source Current (DC) ............. 800mA
N-Channel Switch Sink Current (DC) ................. 800mA
Peak SW Sink and Source Current ........................ 1.3A
LDO1, LDO2, VCC BATT Output Short-Circuit
Duration.......................................................... Indefinite
Operating Temperature Range (Note 2) ...–40°C to 85°C
Junction Temperature (Note 3)............................ 125°C
Storage Temperature Range ................. –65°C to 125°C
7
8
9 10 11 12
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W, θJC = 2.6°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
ORDER PART NUMBER
LTC3445EUF
UF PART MARKING
3445
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V
= V
CC2
= 3.6V, unless otherwise noted.
A
CC1
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
V
V
V
Input Voltage Range
●
●
●
2.5
0.3
3
CC1, CC2
RUN
Run Threshold
1
1.5
V
PGOOD
Reports Undervoltage of any Regulator
DC Bias Current (Shutdown)
PGOOD = 0.4V
RUN = 0
mA
µA
I
27
50
S
DC Bias Current (Buck, LDO1, LDO2 Disabled) RUN = V
105
150
µA
CC1
Buck Regulator
R
FB
Feedback Resistance
340
kΩ
V
V
V
Regulated Output Voltage
I
= 100mA, Burst Mode Operation
OUT
●
●
●
0.824
1.504
13.1
0.850
0.875
1.597
16.1
V
OUT(MIN)
Disabled
Regulated Output Voltage
I
= 100mA, Burst Mode Operation
1.55
V
OUT(MAX)
OUT(STEP)
OUT
Disabled
Output Voltage Step Size (0 to 48)
Output Voltage Slew Rate = 00
Output Voltage Slew Rate = 01
Output Voltage Slew Rate = 10
Output Voltage Slew Rate = 11
Peak Inductor Current
I
I
I
I
I
= 100mA
14.7
11.3
7.5
3.8
0.9
1
mV
mV/µs
mV/µs
mV/µs
mV/µs
A
OUT
OUT
OUT
OUT
OUT
= 100mA, V
= 100mA, V
= 100mA, V
= 100mA, V
= 0.85V to 1.55V
= 0.85V to 1.55V
= 0.85V to 1.55V
= 0.85V to 1.55V
OUT
OUT
OUT
OUT
I
V
= 3V, V = 0.5V or V = 90%,
OUT
0.75
1.25
PK
CC1
FB
Duty Cycle < 35%
V
Output Voltage Load Regulation
0.5
%
LOADREG
3445fa
2
LTC3445
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V
= V
CC2
= 3.6V, unless otherwise noted.
A
CC1
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Additional Input DC Bias Current For Buck (Note 4)
S
Active Mode
Sleep Mode
V
V
= 90%, I
= 0A
220
6
µA
µA
OUT
OUT
LOAD
= 103%, I
= 0A
LOAD
f
Nominal Oscillator Frequency
V
V
= 100%
= 0V
●
1.2
1.5
300
1.8
MHz
kHz
OSC
OUT
OUT
R
R
R
R
of P-Channel FET
of N-Channel FET
I
I
= 100mA
0.45
0.325
1
Ω
Ω
PFET
NFET
LSW
DS(ON)
DS(ON)
SW
SW
= –100mA
I
SW Leakage
V
= 0V, V = 0V or 5V, V = 5V
CC1
µA
RUN
SW
LDO1
I
Additional DC Bias for LDO1
Regulated Output Voltage
23
1
30
µA
S
V
2.5V < V < 5.5V, 1mA < I
< 50mA
0.582
V
–
V
OUT
IN
LOAD
CC2
0.3
Line Regulation
∆V
CC2
= 2.5V to 5.5V, I
= 1mA, V = 1.2V
OUT
5
mV
mV
V
LOAD
Load Regulation
Dropout Voltage
LDO Feedback Voltage
V
= 2.5V, ∆I
= 1mA to 50mA, V = 1.2V
OUT
15
CC2
LOAD
I
I
= 50mA
= 0mA
0.3
0.6
LOAD
LOAD
V
●
0.582
0.582
0.618
30
V
FB
LDO2
I
Additional DC Bias for LDO2
Regulated Output Voltage
23
1
µA
S
V
2.5V < V < 5.5V, 1mA < I
< 50mA
V
–
V
OUT
IN
LOAD
CC2
0.3
Line Regulation
∆V
CC2
= 2.5V to 5.5V, I
= 1mA, V = 1.2V
OUT
5
mV
mV
V
LOAD
Load Regulation
Dropout Voltage
LDO Feedback Voltage
V
= 2.5V, ∆I
= 1mA to 50mA, V = 1.2V
OUT
15
CC2
LOAD
I
I
= 50mA
= 0mA
0.3
0.6
LOAD
LOAD
V
●
0.582
0.618
V
FB
PowerPath Controller
V
Tracked Input Voltage
3
–0.2
2
V
–
V
V
TRACK
CC1
0.2
V
V
–
Tracked Output Voltage at V BATT
3V < V
< V – 0.2V
CC1
0
0.2
TRACK
CC
TRACK
BATT
CC
V
Backup Battery Voltage
5.5
6.5
3.1
V
µA
V
BACKUP
BACKUP
I
Backup Battery Bias Current
V
V
V
= V
= 0V, V = 2.5V
BACKUP
4
3
CC1
TRACK
V
BATT
V
BATT Output
= 0V, V
= 4V, I = 8mA
VCCBAT
2.85
CC
CC
TRACK
CC1
I
Max V BATT Output Current
= 2.5V
CC1
8
mA
V
VCCBATT
CC
BATTFAULT
V
V
High Level (Good)
Low Level (Bad)
Where BATTFAULT Goes High
Where BATTFAULT Goes Low
2.65
2.4
2.8
2.5
0.3
2.9
2.6
CC1
CC1
V
Hysteresis
V
= 0V to 4.2V, 4.2 to 0V
V
CC1
2
I C Interface
2
f
t
Maximum I C Operating Frequency
(Note 5)
(Note 5)
400
1.3
kHz
I2C(MAX)
BUF
Bus Free Time Between Stop and Start
Condition
µs
t
Hold Time After (Repeated)
Start Condition
(Note 5)
600
ns
HD(RSTA)
3445fa
3
LTC3445
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V
= V
CC2
= 3.6V, unless otherwise noted.
A
CC1
SYMBOL
PARAMETER
CONDITIONS
(Note 5)
MIN
TYP
MAX
600
600
0
UNITS
ns
t
t
t
t
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time, Input
SU(RSTA)
SU(STOP)
HD(DIN)
(Note 5)
ns
(Note 5)
ns
Data Setup Time
(Note 5)
100
ns
SU(DAT)
V
V
SCL and SDA Logic Input Threshold
SCL and SDA Logic Input Hysteresis
1.8
50
V
THR
(Note 5)
mV
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
HYS
I
I
I
I
I
I
I
I
I
I
I
I
V
V
Leakage
V
V
V
V
V
V
V
V
V
V
V
V
= 3.6V
= 3.6V
= 3.6V
= 3.6V
= 3.6V
= 3.6V
1.44
2.2
1
LVTRACK
LVBACKUP
LADD7
LADD6
LSCL
TRACK
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
FB1
Leakage
●
●
●
●
●
●
●
●
●
●
●
BACKUP
ADD7 Leakage
1
ADD6 Leakage
1
SCL Leakage
1
SCL Leakage
1
LSDA
LDO1 Leakage
= 3.6V, RUN = 0
= 3.6V, RUN = 0
= 3.6V, RUN = 0
= 3.6V, RUN = 0
= 3.6V
1
LLDO1
LDO2 Leakage
1
LLDO2
LDO1FB Leakage
LDO2FB Leakage
BATTFAULT Leakage
LDO Feedback Input Current
1
LLDO1FB
LLDO2FB
LBATTFAULT
FB1,2
1
1
= 0.6V
1
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 3: T is calculated from the ambient temperature, T , and power
J
A
dissipation, P , according to the following formula:
D
Note 2: The LTC3445EUF is guaranteed to meet performance specifica-
tions from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
T = T + P • 37°C/W
J A D
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 5: Determined by design, not production tested.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
V
vs DAC
V
Step Size vs DAC
OUT
OUT
500
400
300
200
100
0
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.002
0
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0mA
600mA
100mA
ALL ON
BUCK
ONE LDO
TWO LDOs
RUN = HIGH
RUN = LOW
–0.002
40 50
10 20 30
DAC VALUE
0
60 70 80
4
2.4 2.8 3.2 3.6
4.4 4.8 5.2 5.6
40 50
DAC VALUE
0
10 20 30
60 70 80
SUPPLY VOLTAGE (V)
3445 G03
3445 G01
3445 G02
3445fa
4
LTC3445
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Buck Output Voltage
vs Load Current
Buck Efficiency and Power Loss
Buck Efficiency and Power Loss
vs Load Current, V = 4.2V
vs Load Current, V
= 2.5V
CC1
CC1
100
90
80
70
60
50
40
30
20
10
0
1000
100
10
100
90
80
70
60
50
40
30
20
10
0
1000
100
10
0.900
0.850
0.800
0.750
0.700
DAC = MIN
EFFICIENCY
DAC MIN
EFFICIENCY
DAC MIN
DAC MAX
DAC MAX
DAC MAX
POWER LOSS
POWER LOSS
1.0
1.0
DAC MAX
DAC MIN
DAC MIN
10
0.1
1000
0.1
1000
0.1
1
100
0.1
1
10
100
–100
100
500
700
900
300
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3445 G04
3445 G05
3445 G06
Buck Output Voltage
vs Load Current
I
vs Temperature (RUN = V
)
I
vs Temperature (RUN = 0V)
VCC2
CC1
VCC2
1.580
1.560
1.540
1.520
1.500
1.480
1.460
1.2
1.0
1.2
1.0
V
= 2.5V
= 3.6V
= 4.2V
= 5.5V
V
= 2.5V
= 3.6V
= 4.2V
= 5.5V
DAC = MAX
CC2
CC2
CC2
CC2
CC2
CC2
CC2
CC2
V
V
V
V
V
V
0.8
0.6
0.8
0.6
0.4
0.2
0
0.4
0.2
0
–100
100
300
500
700
900
–50
–10
30
70
110
150
–50
–10
30
70
110
150
TEMPERATURE (°C)
TEMPERATURE (°C)
LOAD CURRENT (mA)
3445 G07
3445 G08
3445 G09
Synchronous Switch R
vs Temperature
Main Switch R
DS(ON)
DS(ON)
R
vs Input Voltage
vs Temperature
DS(ON)
600
550
500
450
400
350
300
250
700
600
500
800
700
600
V
CC1
V
CC1
V
CC1
V
CC1
= 2.5V
= 3.6V
= 4.2V
= 5.5V
V
V
V
V
= 2.5V
= 3.6V
= 4.2V
= 5.5V
CC1
CC1
CC1
CC1
MAIN SWITCH
400
300
200
500
400
300
SYNCHRONOUS SWITCH
2.2 2.6
3
3.4 3.8 4.2 4.6
INPUT VOLTAGE (V)
5
5.4 5.8
–20
0
20
80 100
140
–20
0
20
–40
40 60
120
–40
40 60
120
80 100 140
TEMPERATURE (°C)
TEMPERATURE (°C)
3445 G10
3445 G11
3445 G12
3445fa
5
LTC3445
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Buck (DAC = Min)
100mA to 300mA Load Step
Buck (DAC = Max)
100mA to 400mA Load Step
Slew Rates DAC Min to DAC Max
BUCK
VOLTAGE
50mV/DIV
BUCK
VOLTAGE
50mV/DIV
200mV/DIV
LOAD
CURRENT
100mA/DIV
LOAD
CURRENT
100mA/DIV
100µs/DIV
3445 G13
20µs/DIV
3445 G14
20µs/DIV
3445 G15
Buck Switching Frequency
Buck Switching Frequency
vs Temperature
Soft-Start (DAC = Min and Max)
4.7Ω Load
vs V
CC1
1.60
1.56
1.52
1.48
1.560
1.540
1.520
1.500
1.480
1.460
1.440
BUCK
OUTPUTS
500mV/DIV
1.44
1.40
200µs/DIV
3445 G18
2.5
3.5
4.5
5.5
75 100
–50 –25
0
25 50
125 150
V
(V)
TEMPERATURE (°C)
CC1
3445 G16
3445 G17
PowerPath LDO Load Step
1mA to 5.5mA
V
BATT vs V
V
BATT vs V
TRACK
CC
CC1
CC
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
= V
= 2V
V
V
= 5.5V
BACKUP
V
0mA
5mA
BATT
TRACK
BACKUP
CC1
CC
= 2V
VCC BATT
20mV/DIV
V
BATT
CC
LOAD
CURRENT
10mA/DIV
V
TRACK
V
CC1
200µs/DIV
3445 G21
0
0
V
RAMP (V)
V
RAMP (V)
CC1
TRACK
3445 G19
3445 G20
3445fa
6
LTC3445
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LDO Reference Voltage
vs Load Current
LDO Reference Voltage
vs Temperature
LDO Output Voltage vs V
CC2
0.604
0.602
0.600
0.598
0.596
0.594
0.592
0.590
0.498
0.608
0.606
0.604
0.602
0.600
0.598
0.596
1.202
1.201
1.200
1.199
0mA
10mA
50mA
V
CC2
= 2.5V
1.198
1.197
V
CC2
= 5.5V
1.196
1.195
1.194
3.1
3.7
4.9
2.5
5.5
4.3
(V)
40
LOAD CURRENT (mA)
–25
0
50 75 100 125 150
25
TEMPERATURE (°C)
0
10 20 30
50 60 70 80
–50
V
CC2
3445 G24
3445 G23
3445 G22
LDO Output Voltage
vs Load Current
LDO Output Voltage
vs Load Current
1.204
2.590
2.588
2.586
2.584
2.582
2.580
2.578
2.576
2.574
1.202
1.200
1.198
1.196
1.194
V
V
= 5.5V
= 2.5V
CC2
CC2
V
= 5.5V
CC2
V
= 3.6V
CC2
0
20
30
40
50
60
10
0
10 20 30 40 50 60 70 80
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3445 G26
3445 G25
LDO Dropout Voltage
vs Load Current
LDO Load Step (10mA to 40mA)
200
160
120
80
–50°C
25°C
150°C
LDO
OUTPUT
20mV/DIV
LOAD
CURRENT
20mA/DIV
40
40µs/DIV
3445 G29
0
0
10
20
30
40
50
LOAD CURRENT (mA)
3445 G28
3445fa
7
LTC3445
U
U
U
PI FU CTIO S
NC (Pin 13): Not Connected.
VTRACK (Pin 1): Supply Sense that VCC BATT Tracks when
above 3V. Must be ≤ VCC1
.
SW (Pin 14): Buck Regulator Switch.
V
BACKUP (Pin 2): Back-Up Battery Input.
RUN (Pin 15): Chip Enable. 1.5V enables the part. Forcing
this pin below 0.3V shuts down the device. In shutdown,
all functions are disabled, drawing <35µA supply current.
VCC1 (Pins3, 10):PowerSupply(2.5Vto5.5V). BothVCC1
pins must be connected externally to the 2.5V to 5.5V
supply.
Do not leave RUN floating. Must be ≤ VCC1
.
NC (Pin 16): Not Connected.
PGOOD (Pin 4): Fault Report (Undervoltage). Open-drain
driver sinks current whenever LDO1, LDO2 or buck out-
puts are low.
ADD7 (Pin 5): I2C Strappable Address (Bit 7)—VCC1 or
ground.
SDA (Pin 6): I2C Data Input.
NC (Pin 7): Not Connected.
SCL (Pin 8): I2C Clock Input.
ADD6 (Pin 9): I2C Strappable Address (Bit 6)—VCC1 or
ground.
FB (Pin 17): Buck Regulator Feedback.
V
CC BATT (Pin 18): VCC BATT PowerPath Output.
BATTFAULT (Pin 19): Open-Drain Output. It is low when
VCC1 is low.
LDO1FB (Pin 20): LDO1 Regulator Sense.
LDO1 (Pin 21): LDO1 Regulator Output.
VCC2 (Pin 22): LDO Regulator Supply Voltage.
LDO2 (Pin 23): LDO2 Regulator Output.
LDO2FB (Pin 24): LDO2 Regulator Sense.
GND (Pin 11): Buck NFET Ground.
NC (Pin 12): Not Connected.
Exposed Pad (Pin 25): Ground. Must be soldered to PCB
ground for electrical contact and optimum thermal
performance.
3445fa
8
LTC3445
U
U
W
FU CTIO AL DIAGRA S
V
CC
C
IN1
3
10
V
CC1
V
CC1
POWER FOR ALL EXCEPT
LDOs AND BUCK PFET
RUN
SDA
BUCK/LDO
ENABLE
BURST
PWR_EN
15
6
2
I C
SCL
8
V
REF
DAC
BUCK REGULATOR
SW
ADD7
ADD6
L1
STRAPPABLE
STRAPPABLE
V
V
OR GND
OR GND
5
CC1
SW
FB
SLEW
CONTROL
SOFT-START
V
REF
14
17
9
CC1
V
OUT
OSC ADJUST FB
GND
CONTROL
0.6V
V
CC
C1
GND
SPREAD
SPECTRUM
11
PGOOD
POWER
GOOD
4
V
CC2
22
V
CC
POWER FOR LDOs
LDO1
EXPOSED PAD
LDO1 OUT
25
21
20
REF
REF
OUT
LD01FB
R1
FB
C11
R2
LDO2
LDO2 OUT
LD02FB
23
24
OUT
FB
R3
C21
R4
V
CC1
POWER
SWITCH
DRIVER
V
V
TRACK
PowerPath
LDO
PowerPath
CONTROL
1
2
V
BACKUP
POWER
SWITCH
V
V
BATT
BACKUP
BACKUP
CC
18
19
3V
COIN
CELL
+
BATTFAULT
3445 F01
Figure 1
3445fa
9
LTC3445
U
U
W
FU CTIO AL DIAGRA S
V
CC1
V
FB
PEAK CURRENT LEVEL REFERENCE
EA
R
V
S
REF
I
COMP
OSC
S
R
Q
QB
PFET
NFET
L
L
LOGIC
SW
BURST
I
RCOMP
3445 F02
Figure 2. Buck Regulator Detail
3445fa
10
LTC3445
W U
W
TI I G DIAGRA
SDA
t
t
t
SU(DAT)
SU(STA)
t
BUF
t
t
t
HD(DAT)
HD(STA)
SUSTO
LOW
3445 TD
SCL
t
HIGH
t
HD(STA)
t
t
f
r
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
2
I C Fast Mode Timing Specifications (for Reference)
SYMBOL
PARAMETER
MIN
0
TYP
MAX
UNITS
kHz
µs
2
f
t
t
t
t
t
t
t
t
t
t
Maximum I C Operating Frequency
400
I2C(MAX)
BUF
Bus Free Time Between Stop and Start Condition
Hold Time After (Repeated) Start Condition
Repeated Start Condition Setup Time
Stop Condition Setup Time
1.3
0.6
0.6
0.6
0
µs
HD(RSTA)
SU(RSTA)
SU(STOP)
HD(DAT)
SU(DAT)
LOW
µs
µs
Data Hold Time
0.9
ns
Data Setup Time
100
1.3
0.6
0
ns
Clock Low Period
µs
Clock High Period
µs
HIGH
Pulse Width of Spikes Suppressed by Input Filter
Clock, Data Fall Time (Note 1)
50
ns
SP
20 + 0.1
300
ns
f
• C
B
tr
Clock, Data Rise Time (Note 1)
20 + 0.1
• C
300
ns
B
Note 1: C = Capacitance of one bus line.
B
U
(refer to Figure 1)
OPERATIO
BUCK REGULATOR
the RS latch is controlled by the output of error amplifier
EA. When the load current increases, it causes a slight
decreaseinthefeedbackvoltage, FB, relativetoaninternal
reference voltage, which in turn, causes the EA’s output
voltage to increase until the average inductor current
matches the new load current. While the top MOSFET is
off, the bottom MOSFET is turned on until either the
inductor current starts to reverse, as indicated by the
currentreversalcomparatorIRCMP, orthebeginningofthe
next clock cycle.
Main Control Loop
The LTC3445 uses a constant or spread spectrum fre-
quency, current mode step-down architecture (Figure 2).
Both the main (P-channel MOSFET) and synchronous
(N-channelMOSFET)switchesareinternal.Duringnormal
operation, the internal top power MOSFET is turned on
each cycle when the oscillator sets the RS latch, and
turned off when the current comparator, ICOMP, resets the
RS latch. The peak inductor current at which ICOMP resets
3445fa
11
LTC3445
U
(refer to Figure 1)
OPERATIO
Burst Mode Operation
1400
1300
1200
1100
1000
900
TheLTC3445iscapableofBurstModeoperation, inwhich
the internal power MOSFETs operate intermittently based
on load demand.
DAC (MIN)
DAC (MAX)
In Burst Mode operation, the peak current of the inductor
issettoapproximately200mAregardlessoftheoutputload.
Each burst event can last from a few cycles at light loads
to almost continuous cycling with short sleep intervals at
moderate loads. In between these burst events, the power
MOSFETsandanynonessentialcircuitryareturnedoff,re-
ducingthebuckregulator’squiescentcurrentto6µA.Inthis
sleep state, the load current is being supplied solely from
theoutputcapacitor.Astheoutputvoltagedroops,theEA’s
outputrisesabovethesleepthreshold,signalingtheBURST
comparator to trip and turn the top MOSFET on. This pro-
cessrepeatsataratethatisdependentontheloaddemand.
800
700
600
500
400
2.5
3
4.5
5
5.5
3.5
4
V
(V)
CC1
3445 F03
Figure 3. Buck Maximum Peak Current vs V
CC1
Spread Spectrum
The LTC3445 has a spread spectrum mode that can be
enabled via two register bits. In the spread spectrum
mode, the switching frequency is dithered about a center
frequencyof1.5MHz.Spreadspectrumlowersnoiseatthe
regulated output and at the input.
Short-Circuit Protection
Whentheoutputisshortedtoground, thefrequencyofthe
oscillator is reduced to about 300kHz. This frequency
foldback ensures that the inductor current has more time
to decay, thereby preventing current runaway. The
oscillator’sfrequencywillprogressivelyincreaseto1.5MHz
when VOUT rises above 0V.
Figure 4 shows the noise reduction capabilities of the
LTC3445inspreadspectrummode. Thepercentspreadof
the frequency is controlled by two bits in register 5.
00 = 0% Spread
01 = 7.4% Spread
10 = 14.8% Spread
11 = 22.4% Spread
Low Supply Operation
The LTC3445 will operate with input supply voltages as
low as 2.5V, but the maximum allowable output current is
reduced at this low voltage. Figure 3 shows the reduction
in the typical maximum output current as a function of
input voltage for various output voltages.
DAC
The buck output voltage is controlled by programming a
6-bit DAC register (REG0[5:0]) and GO bit (REG2[0]). The
output voltage range is 0.85V to 1.55V in ~15mV steps.
The DAC setting range is from 0 to 48. Any settings above
48 will default to the 48 settings value. When the desired
DACsettingisloaded,theGObitneedstobechangedfrom
0 to 1. Once the GO bit transition occurs, VOUT will begin
to change to the DAC setting loaded at that instant.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quencyarchitecturesbypreventingsubharmonicoscilla-
tions at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current sig-
nalatdutycyclesinexcessof40%. Normally, thisresults
inareductionofmaximuminductorpeakcurrentforduty
cycles>40%.However,theLTC3445usesapatent-pend-
ing scheme that counteracts this compensating ramp,
which allows the maximum inductor peak current to re-
main unaffected throughout all duty cycles.
Slew Rate
A 2-bit register is used to control the rate of change of
VOUT between DAC settings. The slew rate is controlled
by stepping VOUT to its new setting using a series of
3445fa
12
LTC3445
U
(refer to Figure 1)
OPERATIO
SPR = 00 (Spread Spectrum OFF)
SPR = 10
NOISE
10dBm/DIV
NOISE
10dBm/DIV
START FREQ: 100kHz, RBW: 10kHz, STOP FREQ: 30MHz
START FREQ: 100kHz, RBW: 10kHz, STOP FREQ: 30MHz
SPR = 01
SPR = 11
NOISE
10dBm/DIV
NOISE
10dBm/DIV
START FREQ: 100kHz, RBW: 10kHz, STOP FREQ: 30MHz
START FREQ: 100kHz, RBW: 10kHz, STOP FREQ: 30MHz
Figure 4. LTC3445 Output Noise Spectrum
micro-steps. The table below shows the register settings
and corresponding slew rates.
0.6V. The current in R1 and R2 is then equal to 0.6V/R2.
The regulated voltage is equal to:
VOUT = (0.6V/R2) • (R1+R2)
REG1 [1:0]
SLEW RATE (mV/µs)
00
01
10
11
11.3
7.5
3.8
0.9
Frequency Compensation
The LT3445 is frequency compensated by an internal
dominant pole. An output capacitor of 2µF to 10µF is
usually large enough to provide good stability. In order to
insure stability, a feedforward capacitor may be needed
between the output pin and the feedback pin. This cancels
the pole formed by the stray capacitance in large value
feedback resistors. Also, a feedback capacitor minimizes
noise pickup and improves ripple rejection.
It should be noted that during DAC transistions, PGOOD
fault reporting is disabled.
LDO OPERATION
Adjustable Operation
The LTC3445 contains two 50mA LDOs with an output
voltage range of 0.6V to (VCC2 – 0.3V). The output voltage
is set by the ratio of two external resistors as shown in
Figure 1. Each LDO servos the output voltage (Pin LDOx)
in order to maintain a feedback voltage (Pin LDOxFB) of
PowerPath OPERATION
The output of the PowerPath (VCC BATT) is controlled by
acombinationofthreeinputs:mainbattery(VCC1),VTRACK
,
and VBACKUP
.
3445fa
13
LTC3445
U
(refer to Figure 1)
OPERATIO
When VCC1 rises above 2.8V, the PowerPath’s LDO is
enabled and set to the lesser of 3V or VCC1. Once VTRACK
is 3V or higher, it controls the PowerPath’s LDO output
(VCC BATT) voltage to within 200mV of VTRACK. Note that
VTRACK needs to be less than or equal to VCC1. When
VTRACK falls below 3V, VCC1 is used to regulate the
PowerPath’s LDO (VCC BATT) to 3V. When VCC1 falls
below 2.4V, the PowerPath LDO is disconnected and
VBACKUP is connected to VCC BATT.
General I2C Bus/SMBus Description
I2C Bus and SMBus are reasonably similar examples of
2-wire, bidirectional, serial communications busses. Call-
ing them 2-wire is not strictly accurate, as there is an
implied third wire, which is the ground line. Large ground
drops or spikes between the grounds of different parts on
the bus can interrupt or disrupt communications, as the
signals on the two wires are both inherently referenced to
a ground which is expected to be common to all parts on
the bus. Both bus types have one data line and one clock
linewhichareexternallypulledtoahighvoltagewhenthey
are not being controlled by a device on the bus. The
devices on the bus can only pull the data and clock lines
low, which makes it simple to detect if more than one
device is trying to control the bus; eventually, a device will
release a line and it will not pull high because another
device is still holding it low. Pull-ups for the data and clock
lines are usually provided by external discrete resistors,
but external current sources can also be used. Since there
arenodedicatedlinestousetotellagivendeviceifanother
device is trying to communicate with it, each device must
have a unique address to which it will respond. The first
partofanycommunicationistosendoutanaddressonthe
bus and wait to see if another device responds to it. After
a response is detected, meaningful data can be exchanged
between the parts.
ThePowerPath’sfaultdetectioncircuitusesanopen-drain
driver (BATTFAULT) to report when the main battery is
disconnected.
Figure 5 shows the different states of the PowerPath
circuits. Typically, VBACKUP is a coin cell; however, other
types of back up power supplies may be used.
BATTFAULT = 1
4.2V
3.6V
3V
2.8V
V
BACKUP
2.4V
0V
V
V
TRACK
CC1
3445 F05
Figure 5
I2C OPERATION
Typically, one device will control the clock line at least
most of the time and will normally be sending data to the
other parts and polling them to send data back to it, and
this device is called the master. There can certainly be
more than one master, since there is an effective protocol
to resolve bus contentions, and non-master (slave) de-
vices can also control the clock to delay rising edges and
give themselves more time to complete calculations or
communications (clock stretching). Slave devices need to
• Simple 2-wire interface
• Multiple devices on same bus
• Idle bus must have SDA and SCL lines high
• LTC3445 is read/write
• Master controls bus
• Devices listen for unique address that precedes data
SDA
SCL
1-7
8
9
1-7
DATA
8
9
1-7
DATA
8
9
S
P
START
CONDITION
ADDRESS
R/W
ACK
ACK
ACK
STOP
CONDITION
3445 F06
2
Figure 6. Typical 2-Wire Serial I C Waveforms
3445fa
14
LTC3445
U
(refer to Figure 1)
OPERATIO
be able to control the data line to acknowledge communi-
cations from the master, and some devices will need to
able to send data back to the master; they will be in control
ofthedatalinewhiletheyaredoingso. Manyslavedevices
will have no need to stretch the clock signal and will have
no ability to pull the clock line low, which is the case with
the LTC3445.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high.Abusmastersignalsthebeginningofatransmission
with a START condition by transitioning SDA from high to
low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
Data is exchanged in the form of bytes, which are 8-bit
packets. Any byte needs to be acknowledged by the slave
(data line pulled low) or not acknowledged by the master
(datalinelefthigh), socommunicationsarebrokenupinto
9-bit segments, one byte followed by one bit for acknowl-
edging. For example, sending out an address consists of
7 bits of device address, 1 bit that signals whether a read
or write operation will be performed, and then 1 more bit
to allow the slave to acknowledge. There is no theoretical
limit to how many total bytes can be exchanged in a given
transmission.
I2C and SMBus are very similar specifications, SMBus
having been derived from I2C. In general, SMBus is
targeted to low power devices (particularly battery-pow-
ered ones) and emphasizes low power consumption,
while I2C is targeted to higher speed systems where the
power consumption of the bus is not so critical. I2C has
three different specifications for three different maximum
speeds, these being standard mode (100kHz max), fast
mode (400kHz max) and HS mode (3.4MHz max). Stan-
dardandfastmodearenotradicallydifferent,butHSmode
isverydifferentfromahardwareandsoftwareperspective
and requires an initiating command at standard or fast
speed before data can start transferring at HS speed.
SMBus simply specifies a 100kHz maximum speed.
Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. An acknowledge signal (LOW
active) as generated by the slave lets the master know that
the latest byte of information was received. The acknowl-
edge-related clock pulse is generated by the master. The
transmitter master releases the SDA line (HIGH) during
the acknowledge clock pulse. The slave receiver must pull
down the SDA line during the acknowledge clock pulse so
that it remains stable LOW during the HIGH period of this
clock pulse.
When a slave receiver doesn’t acknowledge the slave
address (for example, it’s unable to receive because it’s
performingsomereal-timefunction),thedatalinemustbe
left HIGH by the slave. The master can then generate a
STOP condition to abort the transfer.
Ifaslavereceiverdoesacknowledgetheslaveaddressbut,
some time later in the transfer cannot receive any more
data bytes, the master must again abort the transfer. This
is indicated by the slave generating the not acknowledge
on the first byte to follow. The slave leaves the data line
HIGH and the master generates the STOP condition. The
WRITE BYTE PROTOCOL
1
7
1
1
8
1
8
1
1
START AA01011
WR
ACK
XXXXXAAA
ACK
DDDDDDDD
ACK
STOP
SLAVE
ADDRESS
S
0
REGISTER
ADDRESS
S
0
DATA
BYTE
S
0
0
READ BYTE PROTOCOL
1
7
1
1
8
1
1
7
1
1
1
8
1
1
START AA01011
WR
ACK
XXXXXAAA
ACK
START AA01011
RD
ACK
DDDDDDDD
ACK
STOP
3445 G07
SLAVE
S
0
REGISTER
ADDRESS
S
0
SLAVE
S
0
DATA
BYTE
M
1
ADDRESS
ADDRESS
0
Figure 7
3445fa
15
LTC3445
U
(refer to Figure 1)
OPERATIO
data line is also left high by the slave and master after a
slave has transmitted a byte of data to the master in a read
operation,butthisisanot-acknowledgethatindicatesthat
the data transfer is successful.
Commands Supported
The LTC3445 supports read byte and write byte com-
mands. For the ACK bits, an S indicates that the slave is
pulling the data line low and an M indicates that the master
is effectively acknowledging by leaving the data line high.
2
1 C Register Definitions
(POR = 00 for all registers)
Data Transfer Timing for Write Commands
REG 0
REG 1
In order to help assure that bad data is not written into the
part, data from a write command is only stored after a
valid acknowledge has been performed. The part will
detectthatSDAislowontherisingedgeofSCLthatmarks
theendoftheperiodinwhichtheLTC3445acknowledges
the data write and then latch the data during the following
SCL low period.
7
6
5
4
3
2
1
0
0 (Logic Low)
0 (Logic Low)
Buck DAC5
Buck DAC4
Buck DAC3
Buck DAC2
Buck DAC1
Buck DAC0
7
6
5
4
3
2
1
0
0 (Logic Low)
0 (Logic Low)
0 (Logic Low)
0 (Logic Low)
0 (Logic Low)
0 (Logic Low)
Slew Rate 1
Slew Rate 0
REG 2
REG 3
REG 5
7
6
5
4
3
2
1
0
0 (Logic Low)
7
6
5
4
3
2
1
0
PGOOD Blank Disable
0 (Logic Low)
0 (Logic Low)
0 (Logic Low)
BURST Mode
LDO2 Disable
LDO1 Disable
Buck Disable
7
6
5
4
3
2
1
0
0 (Logic Low)
% SPR1
0 (Logic Low)
0 (Logic Low)
% SPR0
STATUS—Buck Thermal Shutdown
STATUS—Buck PGOODb
STATUS—LDO2 PGOODb
STATUS—LDO1 PGOODb
Buck Update (GO Bit)
(Logic Low)
(Logic Low)
(Logic Low)
(Logic Low)
(Logic Low)
3445fa
16
LTC3445
W U U
APPLICATIO S I FOR ATIO
U
BUCK REGULATOR
requirements and any radiated field/EMI requirements
than on what the LTC3445 requires to operate. Table 1
shows some typical surface mount inductors that work
well in LTC3445 applications.
ThebasicLTC3445applicationcircuitisshownonthefirst
page of this data sheet. External component selection is
driven by the load requirement and begins with the selec-
Table 1
tion of L followed by CIN and COUT
.
MANUFACTURER
PART NUMBER
VALUE
(µH) (mΩ MAX)
DCR
MAX DC
(A)
SIZE
L × W × H (mm )
3
Inductor Selection
Sumida CDRH3D16/
HP2R2
2.2
72
1.2
4.0 × 4.0 × 1.8
For most applications, the value of the inductor will fall in
therangeof1µHto4.7µH. Itsvalueischosenbasedonthe
desired ripple current. Large value inductors lower ripple
current and small value inductors result in higher ripple
currents. Higher VCC1 or lower VOUT also increases the
ripple current as shown in Equation 1. A reasonable
starting point for setting ripple current is ∆IL = 240mA
(40% of 600mA).
Sumida CR434R7
4.7
2.2
109
12
1.15
5.5
4.0 × 4.5 × 3.5
7.3 × 6.8 × 3.2
TDK TDK7030T-
2R2M5R4
Coilcraft D03316P-222 2.2
12
7
12.45 × 9.4 × 5.21
CIN and COUT Selection
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle VOUT/VCC1. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
1
⎛
⎝
VOUT
VCC1
⎞
∆IL =
VOUT 1–
⎜
⎟
⎠
(1)
f L
( )( )
The DC current rating of the inductor should be at least
equal to the maximum load current plus half the ripple
current to prevent core saturation. Thus, a 720mA rated
inductor should be enough for most applications (600mA
+ 120mA). For better efficiency, choose a low DC-resis-
tance inductor.
1/2
]
V
OUT
VCC1 – VOUT
(
)
[
CIN required IRMS ≅ IOMAX
(2)
VCC1
This formula has a maximum at VCC1 = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
usedfordesignbecauseevensignificantdeviationsdonot
offer much relief. Note that the capacitor manufacturer’s
ripplecurrentratingsareoftenbasedon2000hoursoflife.
This makes it advisable to further derate the capacitor, or
choose a capacitor rated at a higher temperature than
required. Always consult the manufacturer if there is any
question.
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
200mA. Lower inductor values (higher ∆IL) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment for COUT has been met, the RMS current rating
generally far exceeds the IRIPPLE(P-P) requirement. The
output ripple ∆VOUT is determined by:
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don’t radiate much energy, but gener-
ally cost more than powdered iron core inductors with
similarelectricalcharacteristics. Thechoiceofwhichstyle
inductor to use often depends more on the price vs size
⎛
1
⎞
∆VOUT ≅ ∆I ESR +
⎜
⎟
⎠
L
(3)
⎝
8fCOUT
3445fa
17
LTC3445
W U U
U
APPLICATIO S I FOR ATIO
where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. For a fixed output
voltage, the output ripple is highest at maximum input
voltage since ∆IL increases with input voltage.
that any DAC settings above 48 defaults to the 48 setting.
The DAC controls the VOUT range of 0.85V to 1.55V in
~15mV steps. The default value for VOUT is 1.35V and is
reset to this value whenever VCC1 comes up.
Aluminum electrolytic and dry tantalum capacitors are
bothavailableinsurfacemountconfigurations.Inthecase
oftantalum,itiscriticalthatthecapacitorsaresurgetested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalum. These are
specially constructed and tested for low ESR so they give
the lowest ESR for a given volume. Other capacitor types
include Sanyo POSCAP, Kemet T510 and T495 series, and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
When the DAC’s value is changed, LTC3445 controls
VOUT’s slew rate via a 2-bit RATE register. The RATE
register can be updated via the I2C interface. The slew rate
canbesettoapproximately0.9mV/µs,3.8mV/µs,7.5mV/µs
or 11.3mV/µs. The default value for RATE is 10mV/µs and
is reset to this value whenever VCC1 comes up.
The DAC and RATE values are not lost whenever the RUN
pin is deasserted.
Once the DAC and RATE registers are programmed, a GO
bit transition is required for the buck to update. This is
accomplished by changing the GO bit (REG2[0]) from
logic low to a logic high.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. Because the
LTC3445’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
oftenusefultoanalyzeindividuallossestodeterminewhat
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
However, care must be taken when ceramic capacitors are
usedattheinputandtheoutput.Whenaceramiccapacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, VCC1. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, a sudden inrush of current through the long wires
can potentially cause a voltage spike at VCC1, large enough
to damage the part.
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3445 buck regulator circuits: VCC1 quiescent
current and I2R losses. The VCC1 quiescent current loss
dominates the efficiency loss at very low load currents
whereas the I2R loss dominates the efficiency loss at
medium to high load currents. In a typical efficiency plot,
the efficiency curve at very low load currents can be
misleading since the actual power lost is of no conse-
quence as illustrated in Figure 8.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
1. The VCC1 quiescent current is due to two components:
the DC bias current as given in the Electrical Character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
Buck Output Voltage Programming
The LTC3445 has an internal resistor divider network tied
to the FB pin. The output voltage is controlled by a DAC
(6-bit register) whose setting is controlled by the I2C
interface. The effective DAC bit range is from 0 to 48. Note
3445fa
18
LTC3445
W U U
U
APPLICATIO S I FOR ATIO
1000
100
10
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD • ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT, which generates a feedback error signal.
DAC MAX
DAC MIN
1
The regulator loop then acts to return VOUT to its steady-
state value. During this recovery time VOUT can be moni-
toredforovershootorringingthatwouldindicateastability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
0.1
0.1
1
10
100
1000
LOAD CURRENT (mA)
3445 F08
Figure 8. Power Loss vs Load Current, V
= 3.6V
CC1
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • CLOAD).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from VCC1 to ground. The resulting
dQ/dt is the current out of VCC1 that is typically larger
thantheDCbiascurrent. Incontinuousmode, IGATECHG
=f(QT +QB)whereQT andQB arethegatechargesofthe
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to VCC1 and thus
their effects will be more pronounced at higher supply
voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
LDO REGULATORS
The LDOs in the LTC3445 are 50mA low dropout regula-
tors with low quiescent and shutdown currents. Each
device is capable of supplying 50mA at a dropout voltage
of 300mV. The LDOs are current limited to greater than
50mA but less than 75mA. The output voltages of the
LDOs are set with external resistive dividers according to
the following formula:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
beobtainedfromtheTypicalPerformanceCharateristics
curves. Thus, to obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.
VLDOOUT1 = 0.6(1 + R1/R2)
VLDOOUT2 = 0.6(1 + R3/R4)
(4)
(5)
Output Capacitance and Transient Response
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for
less than 2% total additional loss.
The LTC3445 LDOs are designed to be stable with a wide
range of output capacitors. A minimum output capacitor
of 2.2µF with an ESR of 3Ω or less is recommended to
3445fa
19
LTC3445
W U U
U
APPLICATIO S I FOR ATIO
prevent oscillations. The LTC3445 LDOs are micropower
devices and output transient response will be a function of
output capacitance. Larger values of output capacitance
decrease the peak deviations and provide improved tran-
sient response for larger load current changes.
is used to detect an absent or low VCC1. If VBACKUP is not
present,theLTC3445willbeunabletopulltheBATTFAULT
pin low to signal a VCC1 fault condition.
Output Capacitance and Transient Response
The LDO used LTC3445 PowerPath is designed to be
stable with a wide range of output capacitors. A minimum
output capacitor of 2.2µF with an ESR of 3Ω or less is
recommended to prevent oscillations. The LTC3445
PowerPath LDO is a micropower device and output tran-
sient response will be a function of output capacitance.
Larger values of output capacitance decrease the peak
deviations and provide improved transient response for
larger load current changes.
PowerPath CONTROLLER
The PowerPath circuitry in the LTC3445 is used to provide
backup power from VBACKUP to the VCC BATT pin when
VCC1 is low or disconnected. When VCC1 is below 2.8V, the
PowerPath routes VBACKUP, typically a coin cell, to the VCC
BATT pin. While VBACKUP is selected there is no current
limiting except for a small (<5Ω) resistance from the
VBACKUP inputtotheVCC BATToutput. TheLTC3445sinks
lessthan6.5µAfromVBACKUP whenitisselectedandsinks
less than 0.1µA from VBACKUP when it is not selected.
THERMAL CONSIDERATIONS
When VCC1 exceeds 2.8V, VBACKUP is disconnected from
VCC BATT and an internal LDO regulates the VCC BATT
voltage to the minimum of VCC1 or typically 3V. The
internal LDO is current limited to less than 50mA, but
greater than 10mA. Capacitance on the VCC BATT pin
should be at least 2µF with an ESR less than 3Ω.
In most applications the LTC3445 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3445 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance. The remaining regulators will also turn off.
VBACKUP will be routed to the VCC BATT output when the
main battery voltage falls below 2.4V. As the main battery,
VCC1, voltage drops from 3V to 2.4V, the LDO will be in
dropout, VCC BATT will follow VCC1 down, rebounding to
VBACKUP when VCC1 falls below 2.4V. If VCC1 is removed
quickly, the capacitor on VCC BATT will limit the VCC BATT
droop until VBACKUP is switched in.
To ensure the LTC3445 doesn’t exceed the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
The VTRACK input offers the capability of the VCC BATT
voltage to follow the voltage on VTRACK up to VCC1. In
effect, VTRACK overrides the internal reference of the LDO,
resulting in the LDO output (VCC BATT) having a gain of 1
relative to VTRACK once VTRACK exceeds a typical value of
3V. VCC BATT will follow VTRACK to within 200mV provid-
ing VTRACK does not exceed the dropout voltage of the
TR = θJA • (PDBUCK + PDLDO1 + PDLDO2 + PDPowerPath
)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
LDO, which is powered by VCC1
.
The junction temperature, TJ, is given by:
TJ = TA + TR
VBACKUP should be present prior to VCC1 being connected.
VBACKUP provides power to the BATTFAULT driver which
where TA is the ambient temperature.
3445fa
20
LTC3445
W U U
APPLICATIO S I FOR ATIO
U
As an example, consider the LTC3445 in dropout at an
input voltage of 2.7V, an ambient temperature of 70°C, a
buck load current of 600mA, LDO1 set to 1.3V with a load
of 25mA, LDO2 set to 1.1V with a load of 15mA, and the
PowerPath regulator at 2.5V with a load of 6µA. From the
typicalperformancegraphofswitchresistance,theRDS(ON)
of the P-channel switch at 70°C is approximately 0.52Ω.
Therefore, power dissipated by the part is:
PC BOARD LAYOUT CHECKLIST
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3445. These items are also illustrated graphically in
Figures 9 and 10. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace, the VCC1 trace and the VCC2 trace should be kept
short, direct and wide.
PD(BUCK) = ILOAD 2 • RDS(ON) = 180mW
2. Does the FB pin connect directly to the output voltage
reference? Ensure that there is no load current running
from the reference voltage and the FB pin.
P
P
D(LDO1) = (2.7 – 1.3)V • 0.025A = 35mW
D(LDO2) = (2.7 – 1.1)V • 0.015A = 24mW
PD(PowerPath) = (2.7 – 2.5)V • 6µA = 1.2µW
3. Does the (+) plate of CIN1 connect to VCC1 as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
PD(TOTAL) = 0.239W
For the QFN24 package, the θJA is 37°C/W. Thus, the
junction temperature of the regulator is:
4. Keep the switching node, SW, away from the sensitive
FB node.
TJ = 70°C + (0.239)(37) = 78.8°C
5. Keep the (–) plates of CIN and COUT as close as possible.
which is well below the maximum junction temperature of
125°C. Note that at higher supply voltages, the junction
temperature is lower due to reduced switch resistance
(RDS(ON)).
FB
17
VIA TO
OUT
FB
17
FB
NC
16
NC
16
GND
RUN
25
GND
25
15
RUN
15
RUN
SW
14
SW
14
SW
NC
13
NC
13
L1
L1
V
GND
11
NC
12
CC1
10
V
GND
11
NC
12
CC1
10
VIA TO
FB
C
C
OUT
IN
C
C
OUT
IN
V
OUT
3445 f10
V
GND
OUT
CC1
3445 F09
BOLD LINES INDICATE HIGH CURRENT PATH
V
CC1
Figure 9
Figure 10
3445fa
21
LTC3445
W U U
U
APPLICATIO S I FOR ATIO
DESIGN EXAMPLE
The buck regulator’s maximum load requirement for this
application is 300mA. Although the default start-up volt-
age for the buck regulator is 1.35V, ripple current is
greatestwhentheoutputvoltageisprogrammedto0.85V.
For ripple currents of 200mA and the main battery at 4.2V,
the required inductor value is 2.2µH (Equation 1). For best
efficiency choose a 400mA or greater inductor with less
than 0.3Ω series resistance. Choosing a 10µF output
capacitor with an ESR of 0.25Ω will generate a ripple
voltage of 52mV (Equation 3). In most cases, a ceramic
capacitor’s ESR will be less than 0.25Ω further reducing
the output ripple (see Figure 11). Note that as VCC1
decreases or VOUT increases, the ripple current and ripple
voltage will decrease. The input capacitor, CIN, will require
an RMS current rating of at least 0.150A ≅ ILOAD(MAX)/2 at
temperature (Equation 2).
As a design example, assume the LTC3445 is used in a
single lithium-ion battery-powered Intel PXA270 micro-
processor application. The battery will be operating from
a maximum of 4.2V down to about 2.7V. Also, the battery
will be connected to all three power pins on the LTC3445.
The desired LDO outputs are 1.3V with a 23mA load and
1.1V with a 14mA load. Since both LDO’s are the same, we
will select LDO1 for the 1.3V output and LDO2 for the 1.1V
output. Using Equations 4 and 5, and choosing R2 and R4
to be 604k, the values for R1 and R2 are 705k and 503k
respectively. Also, selecting a 10µF output capacitor pro-
vides adequate stability and transient reponses.
ThePXA270’sVCCBATTrequirementcanbereadilyhandled
by the LTC3445’s PowerPath control circuits. By simply
connecting a coin cell battery to VBACKUP, the PowerPath
control circuits regulate VCC BATT within the PXA270’s
requirements.
3V_TYP
LTC3406
BUCK
SYS_EN
INTEL PXA270
V
_IO
CC
3V
COIN CELL
V
CC
nBATT_FAULT
20k
V
V
BACKUP
TRACK
20k
nV _FAULT
CC
PGOOD
RUN
BATTFAULT
3V
PWR_EN
V
BATT
V
V
_BATT
_CORE
CC
CC
CC
SUMIDA
CDRH3D16/HP2R2
2.2µH
0.85V TO
1.55V
V
CC
V
SW
FB
CC1
10µF
CER
10µF
CER
2.5V TO 5.5V
LITHIUM ION
V
CC1
V
CC2
LTC3445
1.3V
ADD7
ADD6
LDO1
V
_PLL
CC
705k
604k
10µF
CER
LDO1FB
2
I C BUS
3k
3k
1.1V
SCL
SDA
LDO2
V
CC
_SRAM
503k
604k
3445 F11
10µF
CER
LDO2FB
Figure 11. Design Example
3445fa
22
LTC3445
U
PACKAGE DESCRIPTIO
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.45 ± 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
(4 SIDES)
R = 0.115
TYP
0.75 ± 0.05
4.00 ± 0.10
(4 SIDES)
23 24
PIN 1
TOP MARK
(NOTE 6)
0.38 ± 0.10
1
2
2.45 ± 0.10
(4-SIDES)
(UF24) QFN 1103
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3445fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC3445
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 1.8V to 20V, V
LT1761
100mA, Low Noise Micropower, LDO
= 1.22V, Dropout Voltage = 0.30V,
I = 20µA, I < 1µA, V = Adj, 1.5V, 1.8V, 2V, 2.5V, 2.8V, 3V,
OUT
IN
OUT(MIN)
Q
SD
3.3V, 5V, ThinSOTTM Package. Low Noise < 20µV
with 1µF Ceramic Capacitors
, Stable
RMS(P-P)
LT1762
LT1763
LTC1844
150mA, Low Noise Micropower, LDO
500mA, Low Noise Micropower, LDO
150mA, Very Low Dropout LDO
V : 1.8V to 20V, V
= 1.22V, Dropout Voltage = 0.30V,
I = 25µA, I < 1µA, V = Adj, 2.5V, 3V, 3.3V, 5V, MS8
OUT
IN
OUT(MIN)
Q
SD
Package. Low Noise < 20µV
RMS(P-P)
V : 1.8V to 20V, V
= 1.22V, Dropout Voltage = 0.30V,
I = 30µA, I < 1µA, V = 1.5V, 1.8V, 2.5V, 3V, 3.3V, 5V, S8
OUT
IN
OUT(MIN)
Q
SD
Package. Low Noise < 20µV
RMS(P-P)
V : 6.5V to 1.6V, V
= 1.25V, Dropout Voltage = 0.08V,
I = 40µA, I < 1µA, V = Adj, 1.5V, 1.8V, 2.5V, 2.8V, 3.3V,
OUT
IN
OUT(MIN)
Q
SD
ThinSOT Package. Low Noise < 30µV
Ceramic Capacitors
, Stable with 1µF
RMS(P-P)
LT1962
300mA, Low Noise Micropower, LDO
V : 1.8V to 20V, V
= 1.22V, Dropout Voltage = 0.27V,
IN
OUT(MIN)
I = 30µA, I < 1µA, V = 1.5V, 1.8V, 2.5V, 3V, 3.3V, 5V, MS8
Q
SD
OUT
Package. Low Noise < 20µV
RMS(P-P)
LT3020
Low V (0.9V) Low V
(0.2V) VLDOTM
V : 0.9V to 10V, V = 0.20V, Dropout Voltage = 0.15V,
IN OUT(MIN)
IN
OUT
I = 120µA, I < 1µA, V
= Adj, DFN Package
Q
SD
OUT
LTC3405/LTC3405A
LTC3406/LTC3406B
LTC3407
300mA (I ), 1.5MHz Synchronous Step-Down
DC/DC Converter
V : 2.5V to 5.5V, V
Package
= 0.8V, I = 20µA, I < 1µA, ThinSOT
OUT
IN
OUT(MIN) Q SD
600mA (I ), 1.5MHz Synchronous Step-Down
V : 2.5V to 5.5V, V
Package
= 0.6V, I = 20µA, I < 1µA, ThinSOT
Q SD
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
DC/DC Converter
Dual 600mA, 1.5MHz Synchronous Step-Down
DC/DC Converter
V : 2.5V to 5.5V, V
= 0.6V, I = 40µA, I < 1µA, MS10E
Q SD
IN
Package
LTC3411
1.25A (I ), 4MHz Synchronous Step-Down
V : 2.5V to 5.5V, V
= 0.8V, I = 60µA, I < 1µA, MS10
Q SD
OUT
IN
DC/DC Converter
Package
LTC3412
2.5A (I ), 4MHz Synchronous Step-Down
V : 2.5V to 5.5V, V
IN
= 0.8V, I = 60µA, I < 1µA,
Q SD
OUT
DC/DC Converter
TSSOP16E Package
LTC3455
Dual DC/DC Converter with USB Power Manager and
Li-Ion Battery Charger
V : 3V to 5.5V, Seamless Transition Between Input Sources and
Li-Ion Battery, USB, 5V Wall Adapter, QFN24 Package
IN
LTC4055
USB Power Manager and Li-Ion Battery Charger
Standalone Charger, Automatic Switchover when Input Supply
is Removed
LTC4411/LTC4412
PowerPath Controllers in ThinSOT
More Efficient than Diode ORing
ThinSOT and VLDO are trademarks of Linear Technology Corporation.
3445fa
LT/LT 0705 REV A • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
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