LTC3499BEDD#PBF [Linear]
LTC3499 - 750mA Synchronous Step-Up DC/DC Converters with Reverse-Battery Protection; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C;![LTC3499BEDD#PBF](http://pdffile.icpdf.com/pdf1/p00129/img/icpdf/LTC34_712617_icpdf.jpg)
型号: | LTC3499BEDD#PBF |
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描述: | LTC3499 - 750mA Synchronous Step-Up DC/DC Converters with Reverse-Battery Protection; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C 转换器 电池 |
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LTC3499/LTC3499B
750mA Synchronous
Step-Up DC/DC Converters
with Reverse-Battery Protection
U
FEATURES
DESCRIPTIO
The LTC®3499/LTC3499B are synchronous, fixed fre-
quency step-up DC/DC power converters with integrated
reverse battery protection that protect and disconnect the
devicesandloadwhenthebatterypolarityisreversedwhile
delivering high efficiency in a small (3mm × 3mm) DFN
package.Trueoutputdisconnecteliminatesinrushcurrent
and allows zero load current in shutdown.
■
Reverse-Battery Protection for DC/DC Converter
and Load
■
High Efficiency: Up to 94%
■
Generates 5V at 175mA from a 1.8V Input
■
Operates from 1.8V to 5.5V Input Supply
■
2V to 6V Adjustable Output Voltage
■
Inrush Current Controlled During Start-Up
■
Output Disconnnect in Shutdown
The devices feature an input voltage range of 1.8V to 5.5V
enabling operation from two alkaline or NiMH batteries.
The switching frequency is internally set at 1.2MHz allow-
ingtheuseoftinysurfacemountinductorsandcapacitors.
A minimal number of external components are required to
generate output voltages ranging from 2V to 6V. The
LTC3499 features automatic Burst Mode operation to
increase efficiency at light loads, while the LTC3499B
features continuous switching at light loads.
■
Low Noise 1.2MHz PWM Operation
■
Tiny External Components
Automatic Burst Mode® Operation (LTC3499)
■
■
Continuous Switching at Light Loads (LTC3499B)
Overvoltage Protection
8-Lead (3mm × 3mm × 0.75mm) DFN
■
■
and MSOP Packages
U
APPLICATIO S
The soft-start time is externally programmable through a
smallcapacitor.Anti-ringcircuitryreducesEMIemissions
by damping the inductor in discontinuous mode. The
devicesfeature<1µAshutdownsupplycurrent, integrated
overvoltage protection and are available in both 8-pin
(3mm × 3mm) DFN and 8-pin MSOP packages.
■
Medical Equipment
■
Digital Cameras
■
MP3 Players
Handheld Instruments
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
Battery Current vs V
IN
Two AA Cells to 5V Synchronous Boost Converter
1.0
0.5
SHDN = 0V
= 0V
V
OUT
4.7µH
V
IN
1.8V TO 3.2V
+
V
2.2µF
SW
OUT
FB
IN
LTC3499
V
OUT
0
V
5V
ON OFF
SHDN
VC
175mA
1M
10µF
–0.5
–1.0
100k
330pF
SS
GND
324k
0.01µF
–6
–4
–2
0
2
4
6
3499 TA01
V
AND SW VOLTAGE (V)
IN
3499 TA01b
3499f
1
LTC3499/LTC3499B
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
FB, SS to GND ............................................ – 0.3V to 7V
Operating Temperature Range
VIN to GND..................................................... – 7V to 7V
VOUT to GND ............................................... – 0.3V to 7V
SW to VOUT .................................................... – 7V to 1V
SW to GND
DC .............................................................. –7V to 7V
Pulsed < 100ns .......................................... –7V to 8V
SHDN to GND ................................................ – 7V to 7V
(Notes 3, 4) ........................................ –40°C to 85°C
Storage Temperature Range ................ – 65°C to 125°C
Lead Temperature (Soldering, 10 sec)
MSOP .............................................................. 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
SHDN
1
2
3
4
8
7
6
5
VC
FB
SHDN
1
2
3
4
8
7
6
5
VC
FB
V
OUT
SS
V
IN
9
V
SW
IN
SW
V
OUT
GND
GND
SS
MS8 PACKAGE
8-LEAD PLASTIC MSOP
DD PACKAGE
8-LEAD PLASTIC DFN
T
= 125°C, θ = 160°C/W
JA
JMAX
TJMAX = 125°C, θJA = 45°C
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER PART NUMBER
DD PART MARKING
ORDER PART NUMBER
MS8 PART MARKING
LTC3499EMS8
LTC3499BEMS8
LTC3499EDD
LTC3499BEDD
LBRB
LCDZ
LTBRC
LTCFB
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications that apply over the full operating temperature
range, otherwise specifications are at T = 25°C. V = 2.4V, V
= 5V, SHDN = 2.4V, T = T unless otherwise noted.
A J
A
IN
OUT
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
Minimum Start-Up Voltage
●
●
●
1.6
1.8
6
V
V
IN
Output Voltage Adjust Range
FB Voltage
2
OUT
FB
1.195
1.220
3
1.245
50
V
I
I
I
I
FB Input Current
V
= 1.22V
FB
nA
µA
µA
FB
V
V
Quiescent Current
No Output Load
SHDN = 0V, V
●
300
0.1
600
1
VIN
IN
IN
Quiescent Current in Shutdown
= 0V
OUT
SD
Quiescent Current – Burst Mode Operation
V
V
Current at 2.4V (LTC3499 Only)
20
1.5
µA
µA
BURST
IN
Current at 5V (LTC3499 Only)
OUT
3499f
2
LTC3499/LTC3499B
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications that apply over the full operating temperature
range, otherwise specifications are at T = 25°C. V = 2.4V, V
= 5V, SHDN = 2.4V, T = T unless otherwise noted.
A
IN
OUT
A
J
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
0.1
0.1
MAX
UNITS
µA
I
I
NMOS Switch Leakage
PMOS Switch Leakage
V
V
= 6V
5
5
NMOS
PMOS
SW
= 6V, V = 0V
µA
OUT
SW
R
NMOS
NMOS Switch On Resistance
V
V
= 3.3V
= 5V
0.45
0.4
Ω
Ω
OUT
OUT
R
PMOS
PMOS Switch On Resistance
V
V
= 3.3V
= 5V
0.58
0.45
Ω
Ω
OUT
OUT
I
t
NMOS Current Limit
●
0.75
80
1
A
ns
LIM
DLY, ILIM
Current Limit Delay to Output
Maximum Duty Cycle
Note 2
60
85
D
D
●
●
●
%
MAX
Minimum Duty Cycle
0
%
MIN
f
Frequency Accuracy
1.2
40
–5
5
1.4
MHz
µmhos
µA
OSC
G
Error Amplifier Transconductance
Error Amplifier Source Current
Error Amplifier Sink Current
SS Current Source
mEA
SOURCE
SINK
SS
I
I
I
µA
V
= 1V
–3
6.8
400
µA
SS
V
V
V
V
Overvoltage Threshold
Overvoltage Hysteresis
V
OV
OUT
OUT
mV
OV(HYST)
Shutdown
V
V
SHDN Input Low
SHDN Input High
SHDN Input Current
●
●
0.2
1
V
V
SHDN(LOW)
SHDN(HIGH)
Measured at SW
1.2
I
µA
SD
Reverse Battery
I
I
I
V
V
Reverse-Battery Current
V
V
V
= 0V, V = V
= V = –6V
●
●
●
5
µA
µA
µA
VOUT,REVBATT
VIN,REVBATT
OUT
OUT
OUT
OUT
IN
SHDN
SHDN
SHDN
SW
and V Reverse-Battery Current
= 0V, V = V
= V = –6V
–5
–5
IN
SW
IN
SW
SHDN Reverse-Battery Current
= 0V, V = V
= V = –6V
SW
SHDN,REVBATT
IN
Note 4: These ICs include overtemperature protection that is intended to
protect the devices during momentary overload conditions. Junction
temperatures will exceed 125°C when overtemperature protection is
active. Continuous operation above the specified maximum operating
temperature range may impair device reliability.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Specification is guaranteed by design and not 100% tested in
production.
Note 3:The LTC3499E/LTC3499BE are guaranteed to meet device
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature are assured by design, characterization and
correlation with statistical process controls.
3499f
3
LTC3499/LTC3499B
U W
TYPICAL PERFOR A CE CHARACTERISTICS
T = 25°C unless noted.
A
2-Cell to 5V Efficiency
vs Load Current (LTC3499 Only)
Li-Ion to 5V Efficiency
vs Load Current (LTC3499 Only)
2-Cell to 5V Efficiency
vs Load Current (LTC3499B Only)
100
90
80
70
60
50
40
30
20
10
0
100
90
100000
10000
100
90
100000
10000
1000
100
EFFICIENCY
EFFICIENCY
80
80
70
1000
100
70
60
50
40
30
POWER LOSS
POWER LOSS
60
50
40
10
1
10
V
V
V
= 3.2V
= 2.4V
= 1.8V
V
IN
V
IN
V
IN
= 3.2V
= 2.4V
= 1.8V
V
V
V
= 4.2V
= 3.6V
= 3V
IN
IN
IN
IN
IN
IN
1
0.1
0.1
0.1
1
10
100
1000
0.1
1
10
100
1000
1
10
LOAD CURRENT (mA)
1000
0.1
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3499 G17
3499 G01
3499 G03
Burst Mode Output Current
Threshold vs Input Voltage
(LTC3499 Only)
Current Limit Accuracy
vs Temperature
2-Cell to 3.3V Efficiency
vs Load Current (LTC3499 Only)
1.04
1.03
1.02
60
100
100000
V
= 5V
OUT
50
40
30
20
10
0
90
10000
EFFICIENCY
80
70
1000
100
1.01
1.00
0.99
0.98
0.97
0.96
60
50
40
10
1
POWER LOSS
V
IN
V
IN
V
IN
= 3V
= 2.4V
= 1.8V
0.1
–25
0
50
1.8
2.8
3.3
3.8
4.3
4.8
–50
75
100
25
2.3
0.1
1
10
100
1000
INPUT VOLTAGE (V)
TEMPERATURE (°C)
LOAD CURRENT (mA)
3499 G04
3499 G05
3499 G02
Burst Mode Quiescent Current
vs Temperature (LTC3499 Only)
Maximum Output Current
No Load Input Current vs V
(LTC3499 Only)
IN
Capability vs V
IN
200
800
700
600
500
400
300
200
100
0
30
25
20
15
10
5
V
> V
OUT
IN
V
> V
180
160
140
120
100
80
IN
OUT
V
= 3.3V
OUT
V
OUT
= 3.3V
V
= 5V
OUT
V
= 5V
OUT
60
40
20
0
0
1.5
2.5
3.5
(V)
4.5
5.5
3.5
(V)
1.5
2.5
4.5
5.5
–50
0
25
50
75
100
–25
V
TEMPERATURE (°C)
V
IN
IN
3499 G07
3499 G06
3499 G08
3499f
4
LTC3499/LTC3499B
U W
TYPICAL PERFOR A CE CHARACTERISTICS
T = 25°C unless noted.
A
Oscillator Frequency
vs Temperature
V and SW Reverse-Battery
IN
FB Voltage vs Temperature
Current vs V and SW Voltage
IN
1.0
0.5
1.2225
1.2220
1.2215
1.2210
1.2205
1.2200
1.2195
1.2190
1.2185
1.4
1.3
1.2
1.1
SHDN = 0V
OUT
V
= 0V
0
–0.5
–1.0
1.0
–25
0
50
–50
75
100
25
–6
–4
–2
0
2
4
6
–50 –25
0
25
50
75
100
TEMPERATURE (°C)
V
AND SW VOLTAGE (V)
TEMPERATURE (°C)
IN
3499 G09
3499 G08
3499 G11
Fixed Frequency Discontinous
Mode Operation
Burst Mode Operation
(LTC3499 Only)
Load Transient 50mA to 200mA
SW
2V/DIV
V
OUT
200mV/DIV
V
OUT
50mV/DIV
200mA
50mA
I
LOAD
100mA/DIV
I
L
I
100mA/DIV
L
50mA/DIV
3499 G13
3499 G14
3499 G12
V
V
= 2.4V
200µs/DIV
IN
V
V
= 2.4V
= 5V
200ns/DIV
V
V
= 2.4V
= 5V
20µs/DIV
IN
OUT
L = 4.7µH
IN
OUT
L = 4.7µH
= 5V
OUT
LOAD
I
= 50mA to 200mA
R
= 100k
Z
C
C
V
= 10µF
OUT
FF
OUT
C = 680pF
F
= 10pF (FEEDFORWARD CAPACITOR FROM
C
= 10µF
OUT
L = 4.7µH
TO FB)
Fixed Frequency Operation
Soft-Start into 25Ω Load
V
IN
2V/DIV
SS
2V/DIV
SW
2V/DIV
V
OUT
2V/DIV
I
L
100mA/DIV
I
L
200mA/DIV
34991G15
3499 G16
V
= 2.4V
OUT
1ms/DIV
V
V
= 2.4V
OUT
L = 4.7µH
200ns/DIV
IN
IN
V
= 5V
= 5V
L = 4.7µH
C
C
= 0.01µF
SS
= 10µF
OUT
3499f
5
LTC3499/LTC3499B
U
U
U
PI FU CTIO S
SHDN (Pin 1):Shutdown Input for IC. Connect to a voltage
greater than 1.2V to enable and a voltage less than 0.2V to
disable the LTC3499/LTC3499B.
VOUT (Pin 6): Power Supply Output. Connect a low ESR
output filter capacitor from this pin to the ground plane.
FB(Pin7): FBInputtoErrorAmplifier. Connectaresistor
divider tap from VOUT to this pin to set the output voltage.
The output voltage can be adjusted between 2V and 6V.
Referring to the Functional Block Diagram, the output
voltage is given by:
VIN (Pin 2): Input Supply Voltage. The valid operating
voltage is between 1.8V to 5.5V. VIN has reverse battery
protection. Since the LTC3499/LTC3499B use VIN as the
main bias source, bypass with a low ESR ceramic capaci-
tor of at least 2.2µF.
⎡
⎤
R1
R2
⎛
⎞
SW (Pin 3): Switch Pin. Connect an inductor from VIN to
this pin with a value between 2.2µH and 10µH. Keep PCB
trace lengths as short and wide as possible to minimize
EMI and voltage overshoot. If the inductor current falls to
zero or SHDN is low an internal 250Ω antiringing switch is
connected from VIN to SW to minimize EMI.
VOUT = 1.22• 1+
⎢
⎜
⎝
⎟ ⎥
⎠
⎣
⎦
VC (Pin 8): Error Amplifier Output. A frequency compen-
sation network is connected from this pin to GND to
compensate the boost converter loop. See Closing the
Feedthrough Loop section for guidelines.
GND (Pin 4): Signal and Power Ground for the IC.
Exposed Pad—DD Only (Pin 9): Ground. Must be sol-
dered to the PCB power ground plane for electrical con-
nection and rated thermal performance.
SS (Pin 5): Soft-Start Input. Connect a capacitor from SS
to ground to control the inrush current at start-up. An
internal 3µA current source charges this pin. SS will be
discharged if SHDN is pulled low, thermal shutdown
occurs or VIN is below the minimum operating voltage.
3499f
6
LTC3499/LTC3499B
U
U
W
FU CTIO AL BLOCK DIAGRA
C
IN
+
V
IN
1.8V TO 5.5V
L
2
3
V
SW
IN
REVERSE-BATTERY COMPARATOR
ANTI-RING
250Ω
+
1 = CLOSED
1 = CLOSED
0.7V
–
–
–
+
+
V
SELECT
OV COMPARATOR
1 = OFF
V
OUT
6
7
V
OUT
+
–
ERROR AMPLIFIER
C
FF
(OPTIONAL)
1.22V
+
–
R1
R2
6.8V
ENABLE
FB
PWM
C
OUT
THERMAL SD
SLEEP
LOGIC
AND
DRIVERS
VC
I
ZERO
8
5
C
C1
C
C2
RZ
1.2MHz
OSCILLATOR
SLOPE
COMPENSATION
Σ
3µA
SS
5k
+
–
C
SS
PWM COMPARATOR
ENABLE
TSD
Burst Mode
CONTROL
(LTC3499 ONLY)
+
–
SLEEP
CURRENT LIMIT COMPARATOR
REFERENCE
1A
TYP
–
SHDN
1
BIAS
ENABLE
UVLO
+
0.8V
SD
34991 F01
GND
4
Figure 1. Functional Block Diagram
3499f
7
LTC3499/LTC3499B
U
OPERATIO
TheLTC3499/LTC3499Bprovidehighefficiency,lownoise
power for boost applications with output voltages up to
6V. Operation can be best understood by referring to the
Functional Block Diagram in Figure 1. The synchronous
boost converters are housed in either an 8-lead (3mm ×
3mm) DFN or MSOP package and operates at a fixed
1.2MHz. With a 1.6V typical minimum VIN voltage these
devices are well suited for applications using two or three
alkaline or nickel-metal hydride (NiMH) cells or one
Lithium-Ion(Li+)cell. The LTC3499/LTC3499Bhaveinte-
grated circuitry which protects the battery, IC, and cir-
cuitry powered by the device in the event that the input
batteries are connected backwards (reverse battery pro-
tection). The true output disconnect feature eliminates
inrush current and allows VOUT to be zero volts during
shutdown. The current mode architecture simplifies loop
compensationwithexcellentloadtransientresponse.The
low RDS(ON), low gate charge synchronous switches
eliminatetheneedforanexternalSchottkydioderectifier,
and provide efficient high frequency pulse width modula-
tion(PWM).BurstModequiescentcurrenttotheLTC3499
is only 20µA from VIN, maximizing battery life. The
LTC3499B does not have Burst Mode operation and the
device continues switching at constant frequency. This
resultsintheabsenceoflowfrequencyoutputrippleatthe
expense of light load efficiency.
In the event of a commanded shutdown or thermal
shutdown (TSD), CSS is discharged through a nominal
5kΩ impedance to GND. Once the condition is removed
and SS is discharged near ground, a soft-start will auto-
matically be re-initiated.
Error Amplifier
A transconductance amplifier generates an error voltage
from the difference between the positive input internally
connected to the 1.22V reference and the negative input
connected to FB. A simple compensation network is
placed from VC to ground. Internal clamps limit the
minimumandmaximumerroramplifieroutputvoltagefor
improved large signal transient response. A voltage di-
vider from VOUT to GND programs the output voltage via
FB from 2V to 6V and is defined by the following equation:
⎡
⎤
R1
R2
⎛
⎞
VOUT = 1.22• 1+
⎢
⎜
⎝
⎟ ⎥
⎠
⎣
⎦
Current Sensing
Losslesscurrentsensingconvertsthepeakcurrentsignal
into a voltage which is summed with the internal slope
compensation. This summed signal is compared to the
error amplifier output to provide a peak current control
command for the PWM. Peak switch current is limited to
750mA minimum.
LOW NOISE FIXED FREQUENCY OPERATION
Shutdown
Antiringing Control
The antiringing control connects a resistor across the
inductor to damp the ringing on SW in discontinuous
conduction mode. The LC resonant ringing (L = inductor,
CSW = capacitance on SW) is low energy, but can cause
EMI radiation if antiringing control is not present.
The LTC3499/LTC3499B are shut down by pulling SHDN
below 0.2V, and activated by pulling the pin above 1.2V.
SHDN can be driven above VIN or VOUT as long as it is
limited to less than the absolute maximum rating.
Soft-Start
Zero Current Comparator
Thesoft-starttimeisprogrammedwithanexternalcapaci-
tor to ground on SS. An internal current source charges
the capacitor, CSS, with a nominal 3µA. The voltage on SS
is used to clamp the voltage on VC. The soft-start time is
given by
The zero current comparator monitors the inductor cur-
rent to the output and shuts off the synchronous rectifier
once this current reduces to approximately 40mA, pre-
venting negative inductor current.
t(msec) = CSS (µF) • 200
3499f
8
LTC3499/LTC3499B
U
OPERATIO
Reverse-Battery Protection
sleep if the output load remains less than the sleep
threshold. The frequency of this intermittent PWM (or
burst)operationisproportionaltoloadcurrent.Therefore,
as the load current drops further below the burst thresh-
old, the LTC3499 operates in PWM mode less frequently.
When the load current increases above the burst thresh-
old, the LC3499 will resume continuous PWM operation
seamlessly.
Pluggingthebatteryinbackwardsposesasevereproblem
to most power converters. At a minimum the battery will
be quickly discharged. Almost all ICs have an inherent
diode from VIN (cathode) to ground (anode) which con-
ducts appreciable current when VIN drops more than 0.7V
below ground. Under this condition the integrated circuit
will most likely be damaged due to the excessive current
draw. There exists the possibility for the battery and
circuitry powered by the device to also be damaged. The
LTC3499/LTC3499B have integrated circuitry which al-
lows negligible current flow under a reverse-battery con-
dition,protectingthebattery,deviceandcircuitryattached
totheoutput. Agraphofthereverse-batterycurrentdrawn
is shown in the Typical Performance Characteristics.
Referring to the Functional Block Diagram, an optional
capacitor, CFF, between VOUT and FB in some circum-
stances can reduce peak-to-peak VOUT ripple and input
quiescent current during Burst Mode operation. Typical
values for CFF range from 10pF to 220pF.
Output Disconnect and Inrush Current Limiting
TheLTC3499/LTC3499Baredesignedtoallowtrueoutput
disconnect by eliminating body diode conduction of the
internalP-channelMOSFETtransistor.ThisallowsVOUT to
go to zero volts during shutdown without drawing any
current from the input source. It also provides for inrush
current limiting at turn-on, minimizing surge current seen
by the input supply.
Discrete methods of reverse battery protection put addi-
tional dissipative elements in the high current path reduc-
ing efficiency while increasing component count to
implement protection. The LTC3499/LTC3499B do not
suffer from either of these drawbacks.
Burst Mode Operation (LTC3499 only)
Portable devices frequently spend extended time in low
power or stand-by mode, only drawing high power when
specificfunctionsareenabled. Inordertoimprovebattery
life in these types of products, high power converter
efficiency needs to be maintained over a wide output
power range. In addition to its high efficiency at moderate
and heavy loads, the LTC3499 includes automatic Burst
Mode operation that improves efficiency of the power
converter at light loads. Burst Mode operation is initiated
if the output load current falls below an internally pro-
grammed threshold (see Typical Performance graph,
Output Load Burst Mode Threshold vs VIN). Once initiated
theBurstModeoperationcircuitryshutsdownmostofthe
circuitry in the LTC3499, only keeping alive the circuitry
required to monitor the output voltage.
VIN > VOUT Operation
The LTC3499/LTC3499B will maintain voltage regulation
when the input voltage is above the output voltage. This
is achieved by terminating the switching on the synchro-
nous P-channel MOSFET and applying VIN statically on
the gate. This will ensure the volts • seconds of the
inductor will reverse during the time current is flowing to
the output. Since this mode will dissipate more power in
the IC, the maximum output current is limited in order to
maintain an acceptable junction temperature:
125 – TA
IOUT(MAX)
≅
θJA • V + 1.5 – V
(
)
(
)
IN
OUT
where TA = ambient temperature and θJA is the package
thermal resistance (45°C/W for the DD8 and 160°C/W for
the MS8).
This state is referred to as sleep. In sleep, the LTC3499
only draws 20µA from the input supply, greatly enhancing
efficiency. When the output has drooped approximately
1% from its nominal regulation point, the LTC3499 wakes
up and commences normal PWM operation. The output
capacitor will recharge causing the LTC3499 to re-enter
For example at VIN = 4.5V, VOUT = 3.3V and TA = 85°C in
the DD8 package, the maximum output current is 330mA.
3499f
9
LTC3499/LTC3499B
U
W U U
APPLICATIO S I FOR ATIO
PCB LAYOUT GUIDELINES
such as ferrite, to reduce core losses. The inductor should
have low ESR (equivalent series resistance) to reduce the
I2R power losses, and must be able to handle the peak
inductor current without saturating. To minimize radiated
noise, use a toroidal or shielded inductor. See Table 1 for
some suggested inductor suppliers.
The high speed operation of the LTC3499/LTC3499B
demand careful attention to board layout. Advertised
performance will not be achieved with careless layout.
Figure 2 shows the recommended component placement.
Alargecopperareawillhelptolowerthechiptemperature.
Traces carrying high current (SW, VOUT, GND) are kept
short. The lead length to the battery should be kept as
short as possible. The VIN and VOUT ceramic capacitors
should be placed as close to the IC pins as possible.
Table 1. Inductor Vendor Information
PART NUMBER
SUPPLIER
WEB SITE
MSS5131 and
Coilcraft
www.coilcraft.com
MOS6020 Series
SLF7028 and
TDK
www.component.tdk.com
SLF7045 Series
C
C2
EXPOSED PAD FOR DD8
LQH55D Series
Murata
Sumida
www.murata.com
www.sumida.com
C
C1
RZ
R2
CDRH4D28 and
CDRH4D28 Series
VC
1
2
3
4
8
7
6
5
SHDN
D53LC and
D62CB Series
Toko
www.tokoam.com
V
IN
FB
V
DT0703 Series
CoEV
FDK
www.coev.net
www.fdk.com
9
R1
C
C
L
+
IN
MJPF2520 Series
V
BATT
OUT
SW
SS
Output Capacitor Selection
OUT
GND
C
SS
The output voltage ripple has three components to it. The
bulk value of the capacitor is set to reduce the ripple due
to charge into the capacitor each cycle. The maximum
ripple voltage due to charge is given by:
34991 F02
Figure 2: Recommended Component Placement
V
IN
VRBULK = IP •
COMPONENT SELECTION
Inductor Selection
C
(
OUT • VOUT • f
)
where IP = peak inductor current and f = switching fre-
quency.
The LTC3499/LTC3499B allow the use of small surface
mountinductorsandchipinductorsduetothefast1.2MHz
switching frequency. A minimum inductance value of
2.2µH is required. Larger values of inductance will allow
greater output current capability by reducing the inductor
ripple current. Increasing the inductance above 10µH will
increase total solution area while providing minimal im-
provement in output current capability.
The ESR (equivalent series resistance) is usually the most
dominant factor for ripple in most power converters. The
ripple due to capacitor ESR is simply given by:
VRCESR = IP • CESR
where CESR = capacitor equivalent series resistance
The ESL (equivalent series inductance) is also an impor-
tant factor for high frequency converters. Using small
surface mount ceramic capacitors, placed as close as
possible to VOUT, will minimize ESL.
The inductor current ripple is typically set to 20% to 40%
of the maximum inductor current. For high efficiency,
choose an inductor with high frequency core material,
3499f
10
LTC3499/LTC3499B
U
W
U U
APPLICATIO S I FOR ATIO
Low ESR capacitors should be used to minimize output
voltage ripple. A 4.7µF to 10µF output capacitor is suffi-
cient for most applications and should be placed as close
to VOUT as possible. Larger values may be used to obtain
even lower output ripple and improve transient response.
X5R and X7R dielectric materials are preferred for their
ability to maintain capacitance over wide voltage and
temperature ranges.
Closing the Feedback Loop
The LTC3499/LTC3499B utilize current mode control,
with internal slope compensation. Current mode control
eliminates the 2nd order filter due to the inductor and
output capacitor exhibited in voltage mode controllers,
thus simplifying it to a single pole filter response. The
productofthemodulatorcontroltooutputDCgainandthe
error amp open loop gain gives the DC gain of the system:
Input Capacitor Selection
VREF
The input filter capacitor reduces peak currents drawn
from the input source and reduces input switching noise.
Ceramiccapacitorsareagoodchoiceforinputdecoupling
due to their low ESR and ability to withstand reverse
voltage (i.e. non-polar nature). The capacitor should be
located as close as possible to the device. In most appli-
cations a 2.2µF input capacitor is sufficient. Larger values
may be used without limitations. Table 2 shows a list of
several ceramic capacitor manufacturers.
GDC = GCONTROL •GEA
•
VOUT •GCURRENT_SENSE
V
IOUT
IN
GCONTROL = 2 •
,
1
GEA ~ 1000, GCURRENT_SENSE
=
RDS ON
(
)
The output filter pole is given by:
IOUT
Table 2. Capacitor Vendor Information
SUPPLIER
AVX
WEB SITE
fFILTER_POLE
=
www.avxcorp.com
www.murata.com
www.component.tdk.com
www.t-yuden.com
π • VOUT •COUT
(
)
Murata
TDK
where COUT is the output filter capacitor.
The output filter zero is given by:
Taiyo Yuden
Thermal Considerations
1
fFILTER_ZERO
=
For the LTC3499/LTC3499B to deliver full output power, it
is imperative that a good thermal path be provided to
dissipate the heat generated within the package. For the
DFN package, this can be accomplished by taking advan-
tage of the large thermal pad on the underside of the
device. It is recommended that multiple vias in the printed
circuit board be used to conduct heat away from the part
and into a copper plane with as much area as possible. If
the junction temperature continues to rise, the part will go
into thermal shutdown where switching will stop until the
temperature drops.
2 • π •RESR •COUT
(
)
where RESR is the capacitor equivalent series resistance.
A troublesome feature of the boost regulator topology is
the right half plane (RHP) zero, given by:
2
V
IN
fRPHZ
=
2 • π •IOUT • VOUT •L
(
)
3499f
11
LTC3499/LTC3499B
U
W U U
APPLICATIO S I FOR ATIO
V
There is a resultant gain increase with a phase lag which
makes it difficult to compensate the loop. At heavy loads
the right half plane zero can occur at a relatively low
frequency. The loop gain is typically rolled off before the
RHP zero frequency.
OUT
6
ERROR AMPLIFIER
R1
R2
1.22V
+
–
FB
7
The typical error amp compensation is shown in Figure 3,
following the equations for the loop dynamics:
VC
8
1
RZ
fPOLE1
~
C
C2
2 • π •10e6 •C
C
C1
(
)
C1
3499 F03
which is extremely close to DC.
Figure 3: Typical Error Amplifier Compensation
1
fZERO1
=
=
2 • π •R •C
(
)
Z
C1
1
fPOLE2
2 • π •R •C
(
)
Z
C2
3499f
12
LTC3499/LTC3499B
U
TYPICAL APPLICATIO S
Lithium-Ion to 5V Efficiency
Lithium-Ion to 5V, 350mA
100
90
100000
L
4.7µH
10000
V
IN
C
+
IN
EFFICIENCY
Li-Ion
2.2µF
V
IN
SW
OUT
FB
80
3.1V TO 4.2V
X5R
1000
LTC3499
V
70
60
50
40
30
OUT
V
5V
POWER LOSS
100
ON OFF
SHDN
VC
350mA
1M
C
OUT
10
10µF
100k
X5R
SS
GND
V
V
V
= 4.2V
= 3.6V
= 3V
324k
IN
IN
IN
1
330pF
0.01µF
0.1
C
C
: TAIYO YUDEN X5R JMK212BJ225MD
IN
OUT
1
10
LOAD CURRENT (mA)
1000
0.1
100
: TAIYO YUDEN X5R JMK212BJ106MD
3499 F04a
L: COILCRAFT MSS5131-472MLB
3499 G03
Two Cells to 5V Efficiency
Two Cells to 5V, 175mA
100
90
100000
10000
L
4.7µH
V
IN
C
+
IN
2 AA CELLS
2.2µF
V
IN
SW
OUT
FB
EFFICIENCY
1.8V TO 3.2V
X5R
80
70
1000
100
LTC3499
V
OUT
V
5V
ON OFF
SHDN
VC
175mA
1M
POWER LOSS
C
OUT
60
50
40
10
1
10µF
100k
X5R
SS
GND
V
IN
V
IN
V
IN
= 3.2V
= 2.4V
= 1.8V
324k
330pF
0.01µF
0.1
C
C
: TAIYO YUDEN X5R JMK212BJ225MD
IN
OUT
0.1
1
10
100
1000
: TAIYO YUDEN X5R JMK212BJ106MD
LOAD CURRENT (mA)
3499 F05a
L: COILCRAFT MSS5131-472MLB
3499 G01
3499f
13
LTC3499/LTC3499B
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 ±0.05
3.5 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
0.38 ± 0.10
TYP
5
8
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 1203
4
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
3499f
14
LTC3499/LTC3499B
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
0.52
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
TYP
(.0205)
REF
(NOTE 3)
8
7 6
5
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 ± 0.152
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
0.127 ± 0.076
(.009 – .015)
(.005 ± .003)
0.65
(.0256)
BSC
TYP
MSOP (MS8) 0204
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3499f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC3499/LTC3499B
U
TYPICAL APPLICATIO
Two Cells to 3.3V Efficiency
Two Cells to 3.3V, 250mA
100
90
100000
10000
L
4.7µH
C
V
+
IN
IN
EFFICIENCY
2.2µF
V
IN
2 AA CELLS
SW
OUT
FB
X5R
1.8V TO 3.2V
80
70
1000
100
LTC3499
V
OUT
V
3.3V
ON OFF
SHDN
VC
250mA
1M
C
OUT
60
50
40
10
1
10µF
POWER LOSS
100k
X5R
SS
GND
332k
V
IN
V
IN
V
IN
= 3V
= 2.4V
= 1.8V
330pF
0.01µF
0.1
C
C
: TAIYO YUDEN X5R JMK212BJ225MD
IN
OUT
0.1
1
10
100
1000
: TAIYO YUDEN X5R JMK212BJ106MD
3499 F06a
LOAD CURRENT (mA)
L: COILCRAFT MSS5131-472MB
3499 G02
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COMMENTS
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5A (I ), 8MHz, 4-Phase Synchronous Step-Up DC/DC
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= 5.25V, I = 12µA,
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< 1µA, 32-Lead QFN Package
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500mA (I ), 1.25MHz, Synchronous Step-Up DC/DC
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3499f
LT 0106 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
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