LTC3521EUF#TRPBF [Linear]
LTC3521 - 1A Buck-Boost DC/DC and Dual 600mA Buck DC/DC Converters; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC3521EUF#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3521 - 1A Buck-Boost DC/DC and Dual 600mA Buck DC/DC Converters; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总22页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3521
1A Buck-Boost DC/DC
and Dual 600mA Buck
DC/DC Converters
FeaTures
DescripTion
TheLTC®3521combinesa1Abuck-boostDC/DCconverter
anddual600mAsynchronousbuckDC/DCconverters.The
1.1MHz switching frequency minimizes the solution foot-
printwhilemaintaininghighefficiency.Allthreeconverters
feature soft-start and internal compensation to minimize
the solution footprint and simplify the design process.
n
Three High Efficiency DC/DC Converters:
Buck-Boost (V : 1.8V to 5.25V, I : 1A)
OUT
OUT
Dual Buck (V : 0.6V to V , I : 600mA)
OUT
IN OUT
n
n
n
1.8V to 5.5V Input Voltage Range
Pin-Selectable Burst Mode® Operation
30µA Total Quiescent Current in Burst Mode
Operation
The buck converters are current mode controlled and
utilize an internal synchronous rectifier to improve ef-
ficiency. The buck converters support 100% duty cycle
operation to extend battery life. If the PWM pin is held
low, the buck converters automatically transition from
Burst Mode operation to PWM mode at high loads. With
the PWM pin held high, the buck converters remain in low
noise, 1.1MHz PWM mode.
n
n
n
n
n
Independent Power Good Indicator Outputs
Integrated Soft-Start
Thermal and Overcurrent Protection
<2µA Current in Shutdown
Small 4mm × 4mm QFN and Thermally Enhanced
TSSOP Packages
applicaTions
Thebuck-boostconverterfeaturescontinuousconduction
operation to maximize efficiency and minimize noise. At
light loads, the buck-boost converter can be operated in
Burst Mode operation to improve efficiency and reduce
no-load standby current.
n
Bar Code Readers
n
Medical Instruments
n
Handy Terminals
n
PDAs, Handheld PCs
n
GPS Receivers
The LTC3521 provides a <2μA shutdown mode, over-
temperature shutdown and current limit protection
on all converters. The LTC3521 is available in a 24-pin
0.75mm × 4mm × 4mm QFN package, and a 20-pin ther-
mally enhanced TSSOP package.
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks
and PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U. S. Patents, including 6404251, 6166527.
Typical applicaTion
Efficiency vs VIN
V
IN
100
98
+
2.4V TO 4.2V
4.7µF
4.7µH
Li-Ion
V
= 3.3V
4.7µH
4.7µH
PV
SW1A
V
IN
PV
OUT1
= 500mA
V
IN1
IN2
OUT2
96
94
92
90
88
86
84
82
80
78
76
74
72
70
I
OUT
SW2
1.8V
600mA
137k
10µF
10µF
SW1B
V
OUT1
3.3V
FB2
V
I
= 1.2V
V
I
= 1.8V
OUT3
= 200mA
V
OUT2
= 200mA
OUT1
800mA
(1A, V > 3.0V)
68.1k
OUT
OUT
22µF
1.0M
LTC3521
IN
FB1
V
OUT3
SW3
FB3
1.2V
SHDN1
SHDN2
SHDN3
PWM
221k
ON
600mA
OFF
100k
100k
PGOOD1
PGOOD2
PGOOD3
PWM
BURST
PGND1A
PGND1B GND PGND2
4.4
2.4
3.4
5.4
3521 TA01a
V
(V)
3521 TA01b
IN
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For more information www.linear.com/LTC3521
LTC3521
absoluTe MaxiMuM raTings (Note 1)
PV , PV , V Voltage............................. –0.3V to 6V
Voltage, All Other Pins ................................. –0.3V to 6V
Operating Junction Temperature Range
IN1
IN2 IN
SW1A, SW1B, SW2, SW3 Voltage
DC............................................................ –0.3V to 6V
Pulsed < 100ns............................................–1V to 7V
(Notes 2, 5)............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
pin conFiguraTion
TOP VIEW
TOP VIEW
FB3
FB2
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
PV
IN2
SW2
24 23 22 21 20 19
SHDN2
PGOOD3
PGOOD2
PGOOD1
PGND2
SW3
SHDN2
PGOOD3
PGOOD2
PGOOD1
1
2
3
4
5
6
18 PGND2
SW3
V
17
16
V
21
PGND1A
OUT1
OUT1
25
PGND1A
SW1A
SW1B
15 SW1A
SW1B
V
V
14
13 NC
IN
IN
GND
PV
GND
IN1
PWM
SHDN1
SHDN3
7
8
9 10 11 12
FB1 10
FE PACKAGE
20-LEAD PLASTIC TSSOP
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
= 125°C, θ = 37°C/W
T
= 150°C, θ = 40°C/W (NOTE 4)
JMAX
JA
–
UNDERSIDE METAL INTERNALLY CONNECTED TO V (PCB CONNECTION OPTIONAL)
EXPOSED PAD (PIN 21) IS PGND1A AND MUST BE SOLDERED TO PCB GROUND
T
JMAX
JA
EXPOSED PAD (PIN 25) IS PGND1A AND MUST BE SOLDERED TO PCB GROUND
orDer inForMaTion
LEAD FREE FINISH
LTC3521EFE#PBF
LTC3521IFE#PBF
LTC3521EUF#PBF
LTC3521IUF#PBF
TAPE AND REEL
PART MARKING*
LTC3521FE
LTC3521FE
3521
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LTC3521EFE#TRPBF
LTC3521IFE#TRPBF
LTC3521EUF#TRPBF
LTC3521IUF#TRPBF
20-Lead Plastic TSSOP
20-Lead Plastic TSSOP
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
3521
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3521fb
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For more information www.linear.com/LTC3521
LTC3521
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN, PVIN1, PVIN2 = 3.6V, VOUT1 = 3.3V, unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
2
UNITS
V
l
l
Input Voltage
1.8
Quiescent Current—Shutdown
Burst Mode Quiescent Current
Oscillator Frequency
V
V
= V
= V = 0V (Note 6)
SHDN3
0.01
30
µA
µA
MHz
V
SHDN1
SHDN2
= 0.66V, V = 0.66V, V = 0.66V, V = 0V
PWM
FB1
FB2
FB3
l
l
l
0.85
1.4
1.1
1.35
SHDN1, SHDN2, SHDN3, PWM Input High Voltage
SHDN1, SHDN2, SHDN3, PWM Input Low Voltage
Power Good Outputs Low Voltage
Power Good Outputs Leakage Current
Buck Converters
0.4
0.2
10
V
I
= I
= I = 1mA
PGOOD3
0.1
0.1
V
PGOOD1
PGOOD2
V
= V
= V = 5.5V
PGOOD3
µA
PGOOD1
PGOOD2
PMOS Switch Resistance
NMOS Switch Resistance
NMOS Switch Leakage Current
PMOS Switch Leakage Current
Feedback Voltage
0.205
0.170
0.1
Ω
Ω
V
V
= V
= V
= 5.5V, V = 5.5V
5
10
µA
µA
V
SW2
SW3
SW3
IN
= 0V, V = 5.5V
0.1
SW2
IN
l
(Note 4)
= V = 0.6V
0.585
0.6
0.612
50
Feedback Input Current
PMOS Current Limit
V
FB2
1
nA
mA
%
FB3
l
l
l
(Note 3)
750
100
1050
Maximum Duty Cycle
V
V
V
V
= V = 0.55V
FB2 FB3
Minimum Duty Cycle
= V = 0.66V
0
%
FB2
FB3
PGOOD Threshold
Falling
–12
1.8
–9
2
–6
%
FB2,3
FB2,3
Power Good Hysteresis
Buck-Boost Converter
Returning Good
%
l
Output Voltage
5.25
V
Ω
PMOS Switch Resistance
NMOS Switch Resistance
NMOS Switch Leakage Current
PMOS Switch Leakage Current
Feedback Voltage
0.110
0.085
0.1
Ω
V
V
= V
= V
= 5.5V, V = 5.5V
5
10
µA
µA
V
SW1A
SW1B
SW1B
IN
= 0V, V = 5.5V
0.1
SW1A
IN
l
l
(Note 4)
= 0.6V
0.585
1.65
85
0.6
0.612
50
Feedback Input Current
Average Current Limit
V
FB1
1
nA
A
(Note 3)
(Note 3)
2.1
Reverse Current Limit
375
94
mA
%
%
%
%
l
l
Maximum Duty Cycle
V
FB1
V
FB1
V
FB1
V
FB1
= 0.55V
Minimum Duty Cycle
= 0.66V
Falling
0
PGOOD Threshold
–12
–9
3
–6
Power Good Hysteresis
Returning Good
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
tions from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3521I is guaranteed
over the full –40°C to 125°C operating junction temperature range. The
maximum ambient temperature is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
Note 2: The LTC3521 is tested under pulsed load conditions such that
T
J
≈
T . The LTC3521E is guaranteed to meet performance specifica-
A
impedance and other environmental factors.
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For more information www.linear.com/LTC3521
LTC3521
elecTrical characTerisTics
Note 3: Current measurements are performed when the LTC3521 is not
switching. The current limit values in operation will be somewhat higher
due to the propagation delay of the comparators.
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 4: The LTC3521 is tested in a proprietary test mode that connects
each FB pin to the output of the respective error amplifier.
Note 6: Shutdown current is measured on the V pin and does not include
PMOS switch leakage.
IN
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
Buck-Boost Efficiency vs Load
Current, Li-Ion to 3.3V
Buck Efficiency vs Load Current,
Li-Ion to 2.5V
140
120
100
80
100
90
100
90
V
V
= 2.7V
= 4.2V
PWM MODE
V
V
= 3.6V
= 4.2V
IN
IN
IN
IN
140
120
100
80
PWM MODE
80
70
60
80
70
60
Burst Mode
OPERATION
50
40
50
40
Burst Mode
OPERATION
60
60
30
20
10
0
30
20
10
0
40
40
Burst Mode
POWER LOSS
20
Burst Mode
20
POWER LOSS
0
0
0.1
1
100
1000
10
0.1
1
100
LOAD CURRENT (mA)
1000
10
LOAD CURRENT (mA)
3521 G01
3521 G02
Buck Efficiency vs Load Current,
Li-Ion to 1.8V
Buck Burst Mode Current
Threshold vs VIN
100
90
60
50
V
V
= 2.7V
= 4.2V
IN
IN
140
120
100
80
60
40
20
0
PWM MODE
Burst Mode
OPERATION
80
70
60
V
= 1.2V
OUT
40
30
20
50
40
V
= 1.8V
= 2.5V
30
20
10
0
OUT
Burst Mode
POWER LOSS
10
0
V
OUT
2
0.1
1
100
1000
10
2.5
3
3.5
(V)
4
4.5
5.5
1.5
5
LOAD CURRENT (mA)
V
IN
3521 G03
3521 G04
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For more information www.linear.com/LTC3521
LTC3521
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
Buck-Boost Switches RDS(ON)
vs Temperature
Buck Switches RDS(ON)
vs Temperature
Switching Frequency
vs Temperature
160
140
120
100
80
350
300
250
200
150
100
50
1.0
0.8
V
V
= 3.6V
V
= 3.6V
IN
OUT1
IN
= 3.3V
0.6
PMOS
NMOS
PMOS
(SWITCHES A AND D)
0.4
0.2
NMOS
(SWITCHES B AND C)
0
–0.2
–0.4
–0.6
–0.8
–1.0
60
40
20
0
0
0
20 40 60 80
TEMPERATURE (°C)
–40 –20
0
20 40 60 80 100 120
–40 –20
100 120
–50 –30 –10 10 30 50 70 90 110
TEMPERATURE (°C)
TEMPERATURE (°C)
3521 G05
3521 G06
3521 G07
Buck-Boost Feedback Voltage
vs Temperature
Buck Feedback Voltage
vs Temperature
Switching Frequency vs VIN
0.2
0.1
2.0
1.5
0.2
0.1
1.0
0
0
0.5
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
0
–0.5
–1.0
–1.5
–2.0
–0.5
0
20 40 60 80
TEMPERATURE (°C)
–40 –20
100 120
2.8 3.3 3.8 4.3 4.8
(V)
–25
0
25
50
75 100 125
1.8 2.3
5.3
–50
V
TEMPERATURE (°C)
IN
3521 G10
3521 G09
3521 G08
Burst Mode Quiescent Current
vs VIN
Buck-Boost Maximum Load Current
vs VIN, Burst Mode Operation
Buck-Boost Maximum Load
Current vs VIN, PWM Mode
33
31
90
80
70
60
50
40
30
20
10
0
ALL THREE CONVERTERS ENABLED
L = 4.7µH
1500
1300
1100
900
V
= 3V
OUT
V
= 3.3V
OUT
V
= 5V
OUT
29
27
25
V
= 5V
OUT
700
500
300
100
2.8 3.3 3.8 4.3 4.8
(V)
1.8 2.3
5.3
2.8 3.3 3.8 4.3 4.8
(V)
1.8 2.3
5.3
2.8 3.3 3.8 4.3 4.8
(V)
1.8 2.3
5.3
V
V
V
IN
IN
IN
3521 G13
3521 G11
3521 G12
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For more information www.linear.com/LTC3521
LTC3521
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
Buck-Boost Load Step,
0mA to 750mA
No Load Quiescent Current
vs VIN
60
V
= 3.6V, V
= 3.3V
OUT
IN
L = 4.7µH
= 22µF
C
OUT
V
OUT
55
50
45
40
100mV/DIV
INDUCTOR
CURRENT
500mA/DIV
3521 G15
100µs/DIV
2.8 3.3 3.8 4.3 4.8
(V)
1.8 2.3
5.3
V
IN
3521 G14
Buck-Boost Burst Mode Operation
to PWM Transition
Buck Load Step, Burst Mode,
10mA to 400mA
Buck Load Step, PWM Mode,
10mA to 400mA
V
OUT
V
OUT
100mV/DIV
100mV/DIV
INDUCTOR
CURRENT
200mA/DIV
V
INDUCTOR
CURRENT
200mA/DIV
OUT
INDUCTOR
CURRENT
200mA/DIV
20mV/DIV
3521 G18
3521 G17
3521 G16
100µs/DIV
100µs/DIV
50µs/DIV
L = 4.7µH
= 22µF
V
V
= 3.6V
OUT
L = 4.7µH
= 10µF
V
V
= 3.6V
OUT
L = 4.7µH
= 10µF
V
V
= 3.6V
OUT
IN
IN
IN
= 1.8V
C
OUT
= 1.8V
C
OUT
= 3.3V
C
OUT
Buck-Boost Current Limit
vs Temperature
Buck-Boost Peak Current Limit
vs Temperature
Buck Current Limit
vs Temperature
2150
2100
2050
2000
1950
3350
3300
3250
3200
1150
1100
1050
1000
950
900
–25
0
25
50
75 100 125
–25
0
25
50
75 100 125
–25
0
25
50
75 100 125
–50
–50
–50
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3521 G19
3521 G20
3521 G21
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LTC3521
pin FuncTions (FE/UF Packages)
V (Pin 7/Pin 5): Low Current Power Supply Connection
FB3 (Pin 1/Pin 23): Feedback Voltage for the Buck Con-
IN
Used to Power the Internal Circuitry of the LTC3521. This
pin should be bypassed by a 4.7µF, or larger, ceramic
capacitor. The bypass capacitor should be placed as close
to the pin as possible and should have a short return path
verter Derived from a Resistor Divider Connected to the
Buck V
Output Voltage. The buck output voltage is
OUT3
given by the following equation, where R1 is a resistor
between FB3 and ground, and R2 is a resistor between
FB3 and the buck output voltage:
to ground. Pins V , PV , and PV must be connected
IN
IN1
IN2
together in the application circuit.
⎛
⎞
⎟
⎠
R2
R1
VOUT3 = 0.6V 1+
⎜
GND(Pin8/Pin6):SmallSignalGround.Thispinisusedas
agroundreferencefortheinternalcircuitryoftheLTC3521.
⎝
FB2 (Pin 2/Pin 24): Feedback Voltage for the Buck Con-
PWM (Pin 9/Pin 7): Logic Input Used to Choose Between
Burst Mode Operation and PWM Mode for All Three Con-
verters. This pin cannot be left floating.
verter Derived from a Resistor Divider Connected to the
Buck V
Output Voltage. The buck output voltage is
OUT2
given by the following equation, where R1 is a resistor
between FB2 and ground, and R2 is a resistor between
FB2 and the buck output voltage:
PWM = Low: Burst Mode operation is enabled on all
three converters. The buck converters will operate in
Burst Mode operation at light current but will automati-
cally transition to PWM operation at high currents. The
buck converters can supply maximum output current
(600mA) in this mode. The buck-boost converter will
operate in variable frequency mode and can only supply
a reduced load current (typically 50mA).
⎛
⎞
⎟
⎠
R2
R1
VOUT2 = 0.6V 1+
⎜
⎝
SHDN2 (Pin 3/Pin 1): Forcing this pin above 1.4V enables
the buck converter output at SW2. Forcing this pin below
0.4V disables the buck converter. This pin cannot be left
floating.
PWM = High: All three converters are forced into PWM
mode operation. The buck converters will remain at
constant-frequency operation until their minimum on-
time is reached. The buck-boost converter will remain
in PWM mode at all load currents.
PGOOD3 (Pin 4/Pin 2): This pin is an open-drain output
which pulls low under any of the following conditions:
V
buck output voltage is out of regulation, the part is
OUT3
in overtemperature shutdown, the part is in undervoltage
lockout, or the SHDN3 pin is pulled low.
FB1 (Pin 10/Pin 8): Feedback Voltage for the Buck-Boost
Converter Derived from a Resistor Divider on the Buck-
Boost Output Voltage. The buck-boost output voltage is
given by the following equation, where R1 is a resistor
between FB1 and ground, and R2 is a resistor between
FB1 and the buck output voltage:
PGOOD2 (Pin 5/Pin 3): This pin is an open-drain output
which pulls low under any of the following conditions:
V
buck output voltage is out of regulation, the part is
OUT2
in overtemperature shutdown, the part is in undervoltage
lockout, or the SHDN2 pin is pulled low.
PGOOD1 (Pin 6/Pin 4): This pin is an open-drain output
⎛
⎞
⎟
⎠
R2
R1
VOUT1 = 0.6V 1+
⎜
which pulls low under any of the following conditions:
⎝
V
buck-boost output voltage is out of regulation, the
OUT1
SHDN3 (Pin 11/Pin 9): Forcing this pin above 1.4V en-
ables the buck converter output at SW3. Forcing this pin
below 0.4V disables the buck converter. This pin cannot
be left floating.
part is in overtemperature shutdown, the part is in un-
dervoltage lockout, the buck-boost converter is in current
limit, or the SHDN1 pin is pulled low. See the Operation
section of this data sheet for details on the functionality
of this pin in PWM mode.
SHDN1 (Pin 12/Pin 10): Forcing this pin above 1.4V
enables the buck-boost converter. Forcing this pin below
0.4V disables the buck-boost converter. This pin cannot
be left floating.
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LTC3521
pin FuncTions (FE/UF Packages)
PV (Pin13/Pin11):Highcurrentpowersupplyconnec-
PGND2 (Pin 18/Pin 18): High Current Ground Connection
forBothBuckConverters.ThePCBtraceconnectingthispin
to ground should be made as short and wide as possible.
IN1
tion used to supply switch A of the buck-boost converter.
This pin should be bypassed by a 4.7µF, or larger, ceramic
cap. The bypass capacitor should be placed as close to
the pin as possible and should have a short return path
SW2 (Pin 19/Pin 20): Buck Converter Switch Node. This
pin must be connected to the opposite side of the inductor
to ground. Pins V , PV , and PV must be connected
IN
IN1
IN2
connected to V
.
OUT2
together in the application circuit.
NC (Pin 19, UF Package Only): No Internal Connection.
NC (Pin 13, UF Package Only): No Internal Connection.
PV (Pin20/Pin22):HighCurrentPowerSupplyConnec-
IN2
SW1B (Pin 14/Pin 14): Buck-Boost Switch Node. This pin
must be connected to one side of the buck-boost inductor.
tion Used to Supply the Buck Converter Power Switches.
This pin should be bypassed by a 10µF or larger ceramic
cap. The bypass capacitor should be placed as close to
the pin as possible and should have a short return path
SW1A (Pin 15/Pin 15): Buck-Boost Switch Node. This pin
must be connected to one side of the buck-boost inductor.
to ground. Pins V , PV , and PV must be connected
IN
IN1
IN2
V
(Pin 16/Pin 16): Buck-Boost Output Voltage Node.
OUT1
together in the application circuit.
This pin should be connected to a low ESR ceramic ca-
pacitor. The capacitor should be placed as close to the
IC as possible and should have a short return to ground.
PGND1A (Exposed Pad Pin 21/Pin 21, Exposed Pad
Pin 25): High Current Ground Connection for the Buck-
Boost Switch B. The PCB trace connecting this pin to
ground should be made as short and wide as possible.
SW3 (Pin 17/Pin 17): Buck converter Switch Node. This
pin must be connected to the opposite side of the inductor
PGND1B(Pin12,UFPackageOnly):HighCurrentGround
Connection for the Buck-Boost Switch C. The PCB trace
connecting this pin to ground should be made as short
and wide as possible.
connected to V
.
OUT3
3521fb
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LTC3521
block DiagraM (UF Package)
11
PV
15
14
16
SW1A SW1B
V
FILTER
IN1
OUT1
PGOOD1
4
FORWARD
I
+
0.546V
+
–
LIMIT
A
D
2.1A
–
+
–
REVERSE I
INTERNAL
LIMIT
V
CC
0.375A
0A
B
C
V
IN
5
PV
OUT
+
–
I
ZERO
PGND1A PGND1B
BUCK-BOOST
PWM
GATE
DRIVES
FB1
–
+
+
8
0.6V
LOGIC
SOFT-START
RAMP
SHDN1
SHDN3
PWM
10
9
7
1
SHDN2
PV
IN2
PV
OSCILLATOR
UVLO
IN2
PV
IN2
22
SW2
SW3
GATE
DRIVES
GATE
DRIVES
20
17
BUCK
PWM
LOGIC
BUCK
PWM
LOGIC
PGND2
0A
PGND2
+
–
+
–
ZERO CROSSING
ZERO CROSSING
I
0A
I
+
1.05A
+
1.05A
LIMIT
LIMIT
–
+
–
+
SLOPE
COMPENSATION
SLOPE
COMPENSATION
g
g
m
m
+
–
+
–
FB2
–
–
+
+
FB3
24
23
+
+
0.60V
0.60V
1.2V
SOFT-START
RAMP
SOFT-START
RAMP
BANDGAP
REFERENCE
AND OT
0.6V
PGOOD2
PGOOD3
–
+
–
+
3
0.546V
0.25V
SHUTDOWN
2
0.546V
0.546V
GND
6
PGND1A
21
PGND1B
12
PGND2
18
3521 BD
3521fb
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LTC3521
operaTion
The LTC3521 combines dual synchronous buck DC/DC
converters and a 4-switch buck-boost DC/DC converter
in a 4mm × 4mm QFN package and a 20-pin thermally
enhanced TSSOP package. The buck-boost converter
utilizes a proprietary switching algorithm which allows its
output voltage to be regulated above, below or equal to
the input voltage. The buck converters provide a high ef-
ficiencylowervoltageoutputandsupport100%dutycycle
operation to extend battery life. In Burst Mode operation,
the total quiescent current for the LTC3521 is reduced to
30μA. All three converters are synchronized to the same
internal 1.1MHz oscillator.
Dropout Operation
As the input voltage decreases to a value approaching the
output regulation voltage, the duty cycle increases toward
the maximum on-time. Further reduction of the supply
voltage will force the main switch to remain on for more
than one cycle until 100% duty cycle operation is reached
where the main switch remains on continuously. In this
dropout state, the output will be determined by the input
voltage less the resistive voltage drop across the main
switch and series resistance of the inductor.
Slope Compensation
Currentmodecontrolrequirestheuseofslopecompensa-
tion to prevent subharmonic oscillations in the inductor
current at high duty cycle operation. This is accomplished
internally on the LTC3521 through the addition of a com-
pensatingramptothecurrentsensesignal.Insomecurrent
mode ICs, current limiting is performed by clamping the
error amplifier voltage to a fixed maximum. This leads to a
reduced output current capability at low step-down ratios.
In contrast, the LTC3521 performs current limiting prior
to addition of the slope compensation ramp and therefore
achieves a peak inductor current limit that is independent
of duty cycle.
BUCK CONVERTER OPERATION
PWM Mode Operation
When the PWM pin is held high, the LTC3521 buck con-
verters use a constant-frequency, current mode control
architecture. Both the main (P-channel MOSFET) and
synchronous rectifier (N-channel MOSFET) switches
are internal. At the start of each oscillator cycle, the
P-channel switch is turned on and remains on until the
currentwaveformwithsuperimposedslopecompensation
ramp exceeds the error amplifier output. At this point,
the synchronous rectifier is turned on and remains on
until the inductor current falls to zero or a new switching
cycle is initiated. As a result, the buck converters operate
with discontinuous inductor current at light loads, which
improvesefficiency.Atextremelylightloads,theminimum
on-time of the main switch will be reached and the buck
converters will begin turning off for multiple cycles in
order to maintain regulation.
Short-Circuit Protection
When the output is shorted to ground, the error amplifier
will saturate high and the P-channel MOSFET switch will
turn on at the start of each cycle and remain on until the
current limit trips. During this minimum on-time, the in-
ductor current will increase rapidly and will decrease very
slowly during the remainder of the period due to the very
small reverse voltage produced by a hard output short.
To eliminate the possibility of inductor current runaway in
this situation, the buck converter switching frequency is
reducedto250kHzwhenthevoltageonthebuckFBpinfalls
below 0.25V. The buck soft-start circuit is reset when the
buck FB pin falls below 0.25V to provide a smooth restart
once the short-circuit condition at the output voltage is
no longer present. Additionally, the PMOS current limit
is decreased from 1050mA to 700mA when the voltage
on the buck FB pin falls below 0.25V.
Burst Mode Operation
When the PWM pin is forced low, the buck converters will
automatically transition between Burst Mode operation
at sufficiently light loads (below approximately 15mA)
and PWM mode at heavier loads. Burst Mode entry is
determined by the peak inductor current. Therefore,
the load current at which Burst Mode operation will be
entered depends on the input voltage, the output voltage
and the inductor value. Typical curves for Burst Mode
entry threshold are provided in the Typical Performance
Characteristics section of this data sheet. In dropout and
neardropoutconditions,BurstModeoperationisdisabled.
3521fb
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LTC3521
operaTion
Soft-Start
BUCK-BOOST CONVERTER OPERATION
PWM Mode Operation
The buck converters have an internal voltage mode
soft-start circuit with a nominal duration of 800μs. The
converters remain in regulation during soft-start and will
therefore respond to output load transients which occur
during this time. In addition, the output voltage rise time
has minimal dependency on the size of the output capaci-
tor or load current.
When the PWM pin is held high, the LTC3521 buck-boost
converter operates in a constant-frequency PWM mode
with voltage mode control. A proprietary switching algo-
rithm allows the converter to switch between buck, buck-
boost and boost modes without discontinuity in inductor
current or loop characteristics. The switch topology for
the buck-boost converter is shown in Figure 1.
Error Amplifier and Compensation
When the input voltage is significantly greater than the
output voltage, the buck-boost converter operates in
buck mode. Switch D turns on continuously and switch
C remains off. Switches A and B are pulse width modu-
lated to produce the required duty cycle to support the
output regulation voltage. As the input voltage decreases,
switch A remains on for a larger portion of the switching
cycle. When the duty cycle reaches approximately 85%,
the switch pair AC begins turning on for a small fraction
of the switching period. As the input voltage decreases
further, theACswitchpairremainsonforlongerdurations
and the duration of the BD phase decreases proportion-
ally. As the input voltage drops below the output voltage,
the AC phase will eventually increase to the point that
there is no longer any BD phase. At this point, switch A
remains on continuously while switch pair CD is pulse
width modulated to obtain the desired output voltage. At
this point, the converteris operating solely in boostmode.
The LTC3521 buck converters utilize an internal transcon-
ductance error amplifier. Compensation of the feedback
loop is performed internally to reduce the size of the
application circuit and simplify the design process. The
compensation network has been designed to allow use of
a wide range of output capacitors while simultaneously
ensuring rapid response to load transients.
PGOOD Comparators
The PGOOD2 and PGOOD3 pins are open-drain outputs
which indicate the status of the buck converters. If
the buck output voltage falls 9% below the regulation
voltage, the respective PGOOD open-drain output will
pull low. The output voltage must rise 2% above the
falling threshold before the pull-down will turn off. In
addition, there is a 60μs typical deglitching delay in
the flag in order to prevent false trips due to voltage
transients on load steps. The respective PGOOD output
will also pull low during overtemperature shutdown,
undervoltage lockout or if the respective buck con-
verter SHDN pin is pulled low to indicate these fault
conditions.
This switching algorithm provides a seamless transition
between operating modes and eliminates discontinuities
in average inductor current, inductor current ripple and
loop transfer function throughout all three operational
L
PV
SW1A
SW1B
V
OUT1
IN1
A
D
B
C
LTC3521
PGND1A
PGND1B
3521 F01
Figure 1. Buck-Boost Switch Topology
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LTC3521
operaTion
modes. These advantages result in increased efficiency
and stability in comparison to the traditional 4-switch
buck-boost converter.
this case, the increased bandwidth created by decreasing
R2 is used to counteract the reduced converter bandwidth
caused by the large output capacitor.
Error Amplifier and Compensation
Current Limit Operation
The buck-boost converter utilizes a voltage mode error
amplifierwithaninternalcompensationnetworkasshown
in Figure 2.
The buck-boost converter has two current limit circuits.
The primary current limit is an average current limit circuit
which injects an amount of current into the feedback node
which is proportional to the extent that the switch A cur-
rent exceeds the current limit value. Due to the high gain
of this loop, the injected current forces the error amplifier
outputtodecreaseuntiltheaveragecurrentthroughswitch
A decreases approximately to the current limit value. The
averagecurrentlimitutilizestheerroramplifierinanactive
state and thereby provides a smooth recovery with little
overshootoncethecurrentlimitfaultconditionisremoved.
Since the current limit is based on the average current
through switch A, the peak inductor current in current
limit will have a dependency on the duty cycle (i.e., on the
input and output voltages in the overcurrent condition).
LTC3521
PV
OUT
V
OUT
+
–
R2
R1
0.6V
FB1
GND
3521 F02
Figure 2. Buck-Boost Error Amplifier and Compensation
The speed of the average current limit circuit is limited by
thedynamicsoftheerroramplifier.Onahardoutputshort,
it would be possible for the inductor current to increase
substantially beyond current limit before the average cur-
rent limit circuit would react. For this reason, there is a
second current limit circuit which turns off switch A if the
current ever exceeds approximately 165% of the average
current limit value. This provides additional protection in
the case of an instantaneous hard output short.
Notice that resistor R2 of the external resistor divider
networkplaysanintegralroleindeterminingthefrequency
response of the compensation network. The ratio of R2 to
R1 must be set to program the desired output voltage but
this still allows the value of R2 to be adjusted to optimize
thetransientresponseoftheconverter.Increasingthevalue
of R2 generally leads to greater stability at the expense of
reduced transient response speed. Increasing the value of
R2canyieldsubstantialtransientresponseimprovementin
caseswherethephasemarginhasbeenreducedduetothe
use of a small value output capacitor or a large inductance
(particularly with large boost step-up ratios). Conversely,
decreasing the value of R2 increases the loop bandwidth
which can improve the speed of the converter’s transient
response. This can be useful in improving the transient
response if a large valued output capacitor is utilized. In
Reverse Current Limit
The reverse current comparator on switch D monitors
the inductor current entering PV . When this current
OUT
exceeds 375mA (typical), switch D will be turned off for
the remainder of the switching cycle.
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LTC3521
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Burst Mode Operation
voltage through the action of the voltage mode error am-
plifier. Since the soft-start is voltage mode, the feedback
voltage will track the output voltage correctly during
soft-start, and the PGOOD1 output will correctly indicate
the point at which the buck-boost attains regulation at the
end of soft-start. Therefore, the PGOOD1 output can be
utilized for sequencing purposes. Once in regulation, the
feedback voltage will no longer track the output voltage,
and the PGOOD1 pin will not directly respond to a loss
of regulation in the output. However, the only means by
which a loss of regulation can occur is if the current limit
has been reached, thereby preventing the buck-boost
converter from delivering the required output current.
In such cases, the occurrence of current limit will cause
the PGOOD1 flag to fall indicating a fault state. There can
be cases, however, when the buck-boost converter is
continuously in current limit, causing the PGOOD1 output
to pull low, while the output voltage still remains slightly
above the PGOOD1 comparator trip point.
With the PWM pin held low, the buck-boost converter
operatesutilizingavariablefrequencyswitchingalgorithm
designed to improve efficiency at light load and reduce
the standby current at zero load. In Burst Mode operation,
the inductor is charged with fixed peak amplitude current
pulses. These current pulses are repeated as often as
necessary to maintain the output regulation voltage. The
maximum output current which can be supplied in Burst
Mode operation is dependent upon the input and output
voltage as given by the following formula:
0.1• V
IN
IOUT(MAX),BURST
=
A
( )
V + V
IN
OUT
In Burst Mode operation, the error amplifier is not used
but is instead placed in a low current standby mode to
reduce supply current and improve light load efficiency.
Soft-Start
ThePGOOD1outputalsopullslowduringovertemperature
shutdown, undervoltage lockout or if the SHDN1 pin is
pulled low.
The buck-boost converter has an internal voltage mode
soft-start circuit with a nominal duration of 600μs. The
converter remains in regulation during soft-start and will
therefore respond to output load transients that occur
during this time. In addition, the output voltage rise time
has minimal dependency on the size of the output capaci-
tor or load. During soft-start, the buck-boost converter is
forced into PWM operation regardless of the state of the
PWM pin.
COMMON FUNCTIONS
Thermal Shutdown
If the die temperature exceeds 150°C, all three converters
will be disabled. All power devices will be turned off and
all switch nodes will be high impedance. The soft-start
circuits for all three converters are reset during thermal
shutdown to provide a smooth recovery once the over-
temperature condition is eliminated. All three converters
will restart (if enabled) when the die temperature drops
to approximately 140°C.
PGOOD Comparator
The PGOOD1 pin is an open-drain output which indicates
the status of the buck-boost converter. In Burst Mode
operation (PWM = Low), the PGOOD1 open-drain output
will pull low when the feedback voltage falls 9% below the
regulationvoltage.Thereisapproximately3%hysteresisin
this threshold when the output voltage is returning good.
In addition, there is a 60μs typical deglitching delay to
prevent false trips due to short duration voltage transients
in response to load steps.
Undervoltage Lockout
If the supply voltage decreases below 1.7V (typical) then
all three converters will be disabled and all power devices
will be turned off. The soft-start circuits for all three con-
verters are reset during undervoltage lockout to provide
a smooth restart once the input voltage rises above the
undervoltage lockout threshold.
In PWM mode, operation of the PGOOD1 comparator is
complicated by the fact that the feedback pin voltage is
driven to the reference voltage independent of the output
3521fb
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LTC3521
applicaTions inForMaTion
The basic LTC3521 application circuit is shown as the
Typical Application on the front page of this data sheet.
The external component selection is determined by the
desired output voltages, output currents and ripple volt-
age requirements of each particular application. Basic
guidelines and considerations for the design process are
provided in this section.
Table 1 depicts the recommended inductance for several
common output voltages.
Table 1. Buck Recommended Inductance
MINIMUM
INDUCTANCE
MAXIMUM
INDUCTANCE
OUTPUT VOLTAGE
0.6V
1.2V
1.8V
2.5V
1.5μH
2.2μH
3.3μH
4.7μH
2.2μH
4.7μH
6.8μH
8.2μH
Buck Inductor Selection
The choice of buck inductor value influences both the ef-
ficiency and the magnitude of the output voltage ripple.
Larger inductance values will reduce inductor current
ripple and lead to lower output voltage ripple. For a fixed
DC resistance, a larger value inductor will yield higher
efficiency by lowering the peak current closer to the av-
erage. However, a larger inductor within the same family
will generally have a greater series resistance, thereby
offsetting this efficiency advantage.
Buck Output Capacitor Selection
A low ESR output capacitor should be utilized at the buck
output in order to minimize voltage ripple. Multilayer ce-
ramic capacitors are an excellent choice as they have low
ESR and are available in small footprints. In addition to
controlling the ripple magnitude, the value of the output
capacitor also sets the loop crossover frequency and can,
therefore, impact loop stability. There is both a minimum
andmaximumcapacitancevaluerequiredtoensurestabil-
ity of the loop. If the output capacitance is too small, the
loop crossover frequency will increase to the point where
the switching delay and the high frequency parasitic poles
of the error amplifier will degrade the phase margin. In
addition, the wider bandwidth produced by a small output
capacitor will make the loop more susceptible to switch-
ing noise. At the other extreme, if the output capacitor
is too large, the crossover frequency can decrease too
far below the compensation zero and lead to a degraded
phase margin. Table 2 provides a guideline for the range
of allowable values of low ESR output capacitors. Larger
value output capacitors can be accommodated provided
they have sufficient ESR to stabilize the loop.
Givenadesiredpeak-to-peakcurrentripple,ΔI ,therequired
L
inductance can be calculated via the following expression,
where f represents the switching frequency in MHz:
⎛
⎞
⎟
⎠
1
fΔIL
VOUT
L =
VOUT 1–
µH
( )
⎜
V
⎝
IN
A reasonable choice for ripple current is ΔI = 240mA
L
which represents 40% of the maximum 600mA load
current. The DC current rating of the inductor should be
at least equal to the maximum load current, plus half the
ripple current, in order to prevent core saturation and loss
of efficiency during operation. To optimize efficiency, the
inductor should have a low series resistance.
In particularly space-restricted applications, it may be
advantageous to use a much smaller value inductor at
the expense of larger ripple current. In such cases, the
converter will operate in discontinuous conduction for a
wider range of output loads and efficiency will be reduced.
In addition, there is a minimum inductor value required
to maintain stability of the current loop (given the fixed
internal slope compensation). Specifically, if the buck
converter is going to be utilized at duty cycles over 40%,
Table 2. Buck Output Capacitor Range
V
OUT
C
MIN
C
MAX
0.6V
0.8V
1.2V
1.8V
2.7V
3.3V
15μF
15μF
10μF
10μF
10μF
6.8μF
300μF
230μF
150μF
90μF
70μF
50μF
the inductance value must be at least L , as given by
MIN
the following equation:
L
MIN
= 2.5 • V
(µH)
OUT
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Buck Input Capacitor Selection
Buck-Boost Output Voltage Programming
ThePV pinprovidescurrenttothebuckconverterpower
The buck-boost output voltage is set by a resistive divider
according to the following formula:
IN2
switch and is the supply pin for the IC’s internal circuitry.
It is recommended that a low ESR ceramic capacitor with
a value of at least 4.7µF be used to bypass this pin. The
capacitor should be placed as close to the pin as possible
and have a short return to ground.
⎛
⎞
⎟
⎠
R2
R1
VOUT1 = 0.6V 1+
⎜
⎝
The external divider is connected to the output, as shown
in Figure 4. The buck-boost converter utilizes voltage
mode control and the value of R2 plays an integral role
in the dynamics of the feedback loop. In general, a larger
value for R2 will increase stability and reduce the speed of
the transient response. A smaller value of R2 will reduce
stabilitybutincreasethetransientresponsespeed.Agood
starting point is to choose R2 = 1MΩ, then calculate the
required value of R1 to set the desired output voltage ac-
cording to the above formula. If a large output capacitor
is used, the bandwidth of the converter is reduced. In
such cases R2 can be reduced to improve the transient
response. If a large inductor or small output capacitor is
utilized, the loop will be less stable and the phase margin
can be improved by increasing the value of R2.
Buck Output Voltage Programming
The output voltage is set by a resistive divider, according
to the following formula:
⎛
⎞
⎟
⎠
R2
R1
VOUT2,3 = 0.6V 1+
⎜
⎝
The external divider is connected to the output, as shown
in Figure 3. It is recommended that a feedforward capaci-
tor, C , be placed in parallel with resistor R2 to improve
FF
the noise immunity of the feedback node. Table 3 provides
the recommended resistor and feedforward capacitor
combinations for common output voltage options.
Table 3. Buck Resistor Divider Values
V
R1
R2
0
C
FF
Buck-Boost Inductor Selection
OUT
0.6V
0.8V
1.0V
1.2V
1.5V
1.8V
2.7V
3.3V
–
–
To achieve high efficiency, a low ESR inductor should
be utilized for the buck-boost converter. The inductor
must have a saturation rating greater than the worst
case average inductor current plus half the ripple current.
The peak-to-peak inductor current ripple will be larger in
buck and boost mode than in the buck-boost region. The
peak-to-peak inductor current ripple for each mode can
200k
118k
100k
78.7k
68.1k
63.4k
60.4k
69.8k
80.6k
102k
121k
137k
226k
274k
22pF
22pF
22pF
22pF
22pF
33pF
33pF
0.6V ≤ V
≤ 5.25V
0.6V ≤ V
≤ 5.25V
1.8V ≤ V
≤ 5.25V
OUT2
OUT3
OUT1
R2
R2
R1
R2
FB1
FB2
FB3
LTC3521
LTC3521
R1
R1
GND
GND
3521 F04
3521 F03
Figure 3. Setting the Buck Output Voltage
Figure 4. Setting the Buck-Boost Output Voltage
3521fb
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LTC3521
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be calculated from the following formulas, where f is the
frequency in MHz and L is the inductance in μH:
Since the output current is discontinuous in boost mode,
the ripple in this mode will generally be much larger than
the magnitude of the ripple in buck mode. In addition to
controlling the ripple magnitude, the value of the output
capacitoralsoaffectsthelocationoftheresonantfrequency
in the open loop converter transfer function. If the output
capacitor is too small, the bandwidth of the converter will
extendhighenoughtodegradethephasemargin.To prevent
this from happening, it is recommended that a minimum
valueof10μFbeusedforthebuck-boostoutputcapacitor.
VOUT V – V
1
fL
(
)
IN
OUT
ΔIL,P-P,BUCK
=
•
V
IN
V
V
VOUT
– V
IN
OUT
1
fL
(
)
IN
ΔIL,P-P,BOOST
=
•
In addition to affecting output current ripple, the size of
the inductor can also affect the stability of the feedback
loop. In boost mode, the converter transfer function has
a right half plane zero at a frequency that is inversely
proportional to the value of the inductor. As a result, a
large inductor can move this zero to a frequency that is
low enough to degrade the phase margin of the feedback
loop. It is recommended that the chosen inductor value be
less than 10μH if the buck-boost converter is to be used
in the boost region.
Buck-Boost Input Capacitor Selection
Thesupplycurrenttothebuck-boostconverterisprovided
bythePV pin.ItisrecommendedthatalowESRceramic
IN1
capacitor with a value of at least 4.7μF be located as close
to this pin as possible.
Inductor Style and Core Material
Different inductor core materials and styles have an
impact on the size and price of an inductor at any given
peak current rating. Toroid or shielded pot cores in ferrite
or permalloy materials are small and reduce emissions,
but generally cost more than powdered iron core induc-
tors with similar electrical characteristics. The choice of
inductor style depends upon the price, sizing, and EMI
requirements of a particular application. Table 4 provides
a sampling of inductors that are well suited to many
LTC3521 application circuits.
Buck-Boost Output Capacitor Selection
A low ESR output capacitor should be utilized at the buck-
boost converter output in order to minimize output volt-
age ripple. Multilayer ceramic capacitors are an excellent
choice as they have low ESR and are available in small
footprints. The capacitor should be chosen large enough
to reduce the output voltage ripple to acceptable levels.
Neglecting the capacitor ESR and ESL, the peak-to-peak
output voltage ripple can be calculated by the following
formulas, where f is the frequency in MHz, C
is the
LOAD
OUT
Table 4. Representative Surface Mount Inductors
capacitance in μF, L is the inductance in μH and I
is
MANU-
FACTURER
MAX
PART NUMBER
VALUE CURRENT DCR HEIGHT
the output current in amps:
Taiyo Yuden NP03SB4R7M
NP03SB6R8M
4.7μH
6.8μH
5μH
1.2A
1A
0.047Ω 1.8mm
0.084Ω 1.8mm
0.024Ω 4.1mm
0.085Ω 2.92mm
0.026Ω 3mm
ILOAD
COUT • VOUT • f
V
– V
IN
OUT
(
)
ΔV
=
P-P,BOOST
Coilcraft
MSS7341-502NL
DT1608C-472ML
SD7030-5R0-R
SD20-6R2-R
2.3A
1.2A
2.4A
V – V
V
1
(
)
4.7µH
5µH
IN
OUT OUT
ΔV
=
•
P-P,BUCK
8 •L •COUT • f2
Cooper-
V
IN
Bussmann
6.2µH
1.12A 0.072Ω 2mm
Sumida
CDR6D23MNNP-4R2 4.2µH
2.6A
1A
0.052Ω 2.5mm
0.081Ω 1.8mm
CDRH4D16FB/ND-
6R8N
6.8µH
3521fb
16
For more information www.linear.com/LTC3521
LTC3521
applicaTions inForMaTion
Capacitor Vendor Information
PCB Layout Considerations
BoththeinputandoutputcapacitorsusedwiththeLTC3521
must be low ESR and designed to handle the large AC cur-
rents generated by switching converters. The vendors in
Table 5 provide capacitors that are well suited to LTC3521
application circuits.
The LTC3521 switches large currents at high frequencies.
Special care should be given to the PCB layout to ensure
stable, noise-free operation. Figure 5 depicts the recom-
mended PCB layout to be utilized for the LTC3521. A few
key guidelines follow:
1. Allcirculatinghighcurrentpathsshouldbekeptasshort
as possible. This can be accomplished by keeping the
routes to all bold components in Figure 5 as short and
as wide as possible. Capacitor ground connections
should via down to the ground plane in the shortest
Table 5. Capacitor Vendor Information
REPRESENTATIVE PART
MANUFACTURER WEB SITE
NUMBERS
Taiyo Yuden
www.t-yuden.com JMK212BJ106K 10μF, 6.3V
JMK212BJ226K 22μF, 6.3V
TDK
www.component.
tdk.com
C2012X5R0J106K 10μF, 6.3V
route possible. The bypass capacitors on PV and
IN1
PV should be placed as close to the IC as possible
IN2
Murata
www.murata.com
GRM21BR60J106K 10μF, 6.3V
GRM32ER61C226K 22μF, 16V
and should have the shortest possible paths to ground.
2. Thesmall-signalgroundpad(GND)shouldhaveasingle
point connection to the power ground. A convenient
way to achieve this is to short the pin directly to the
Exposed Pad as shown in Figure 5.
AVX
www.avxcorp.com SM055C106KHN480 10μF
Minimizing solution size is usually a priority. Please be
aware that ceramic capacitors can exhibit a significant
reduction in effective capacitance when a bias is applied.
The capacitors exhibiting the highest reduction are those
packaged in the smallest case size.
3. The components shown in bold, and their connections,
should all be placed over a complete ground plane.
4. To prevent large circulating currents from disrupting
theoutputvoltagesensing, thegroundforeachresistor
divider should be returned directly to the small signal
ground pin (GND).
5. Use of vias in the die attach pad will enhance the ther-
mal environment of the converter, especially if the vias
extend to a ground plane region on the exposed bottom
surface of the PCB.
3521fb
17
For more information www.linear.com/LTC3521
LTC3521
applicaTions inForMaTion
KELVIN TO
PAD
V
OUT
BUCK
V
OUT
VIA TO
GROUND PLANE
MINIMIZE
TRACE
LENGTH
MINIMIZE
TRACE
LENGTH
KELVIN TO
PAD
V
SHDN2
PGND2
(18)
OUT
(1)
BUCK
V
OUT
PGOOD3
(2)
SW3
(17)
BUCK-BOOST
OUT
PGOOD2
(3)
V
OUT1
(16)
V
KELVIN TO
PAD
PGOOD1
(4)
SW1A
(15)
V
OUT
V
SW1B
(14)
IN
(5)
GND
(6)
NC
(13)
DIRECT TIE
BACK TO
GND PIN
MINIMIZE
TRACE
LENGTH
3521 F05
UNINTERRUPTED GROUND PLANE MUST EXIST UNDER ALL COMPONENTS
SHOWN IN BOLD, AND UNDER TRACES CONNECTING TO THOSE COMPONENTS
Figure 5. LTC3521 Recommended PCB Layout
3521fb
18
For more information www.linear.com/LTC3521
LTC3521
Typical applicaTion
Dual Supercapacitor to 3.3V at 200mA, 1.8V at 50mA and 1.2V at
100mA Backup Power Supply
V
IN
+
+
1.8V TO 5.5V
C4
4.7µF
L1
4.7µH
L2
4.7µH
1F
1F
PV
SW1A
PV
IN2
SW2
V
V
IN1
IN
OUT2
1.8V
C2
10µF
R3
137k
50mA
SW1B
V
OUT1
3.3V
FB2
V
OUT1
R4
200mA
C1
22µF
R1
68.1k
LTC3521
L3
4.7µH
1.0M
FB1
V
OUT3
R2
221k
SW3
1.2V
SHDN1
SHDN2
SHDN3
ON
C3
10µF
R5
100k
100mA
OFF
FB3
PGOOD1
R6
100k
PWM
PWM
PGND1A
PGOOD2
PGOOD3
BURST
PGND1B GND PGND2
3521 TA02a
Converter Output Voltages
Efficiency vs VIN
100
96
92
88
84
80
76
72
V
IN
2V/DIV
V
OUT
= 3.3V
OUT1
I
= 200mA
V
OUT1
2V/DIV
V
V
I
= 1.2V
OUT3
OUT2
2V/DIV
= 100mA
OUT
V
OUT3
2V/DIV
V
OUT
= 1.8V
= 50mA
OUT2
I
3521 TA02b
50µs/DIV
1.8
2.8
3.8
(V)
4.8
V
IN
3521 TA02c
3521fb
19
For more information www.linear.com/LTC3521
LTC3521
package DescripTion
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev J)
Exposed Pad Variation CB
6.40 – 6.60*
3.86
(.152)
(.252 – .260)
3.86
(.152)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE20 (CB) TSSOP REV J 1012
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
PIN ꢀ NOTCH
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
BOTTOM VIEW—EXPOSED PAD
R = 0.ꢀꢀ5
0.75 0.05
4.00 0.ꢀ0
(4 SIDES)
TYP
23 24
0.70 0.05
PIN ꢀ
TOP MARK
(NOTE 6)
0.40 0.ꢀ0
ꢀ
2
4.50 0.05
3.ꢀ0 0.05
2.45 0.05
(4 SIDES)
2.45 0.ꢀ0
(4-SIDES)
PACKAGE
OUTLINE
(UF24) QFN 0ꢀ05 REV
B
0.200 REF
0.25 0.05
0.25 0.05
0.50 BSC
0.00 – 0.05
0.50 BSC
NOTE:
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3521fb
20
For more information www.linear.com/LTC3521
LTC3521
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
11/10 Addition of PGND1A reflected throughout data sheet
Addition of V to Typical Applications
1, 19, 22
IN
Revised Note 2
3
Changes to Block Diagram
9
11, 13
9
Change to Operation Soft-Start section
08/13 Corrected pin numbers on Block Diagram UF package
B
3521fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
21
LTC3521
Typical applicaTion
Li-Ion to 3.3V at 800mA, 1.8V at 600mA and 1.2V at
600mA with Sequenced Start-Up
Sequenced Start-Up Waveforms
V
IN
2.4V TO
4.2V
+
L1
L2
V
4.7µF
Li-Ion
OUT2
4.7µH
4.7µH
PV
SW1A
SW1B
V
PV
2V/DIV
V
IN1 IN
IN2
OUT2
SW2
1.8V
V
OUT3
C2
600mA
R3
2V/DIV
L3
4.7µH
10µF
137k
V
OUT3
1.2V
FB2
V
OUT1
SW3
R4
2V/DIV
600mA
C3
R5
68.1k
LTC3521
10µF
100k
V
OUT1
FB3
3.3V
SHDN2, 5V/DIV
PGOOD2, 5V/DIV
PGOOD3, 5V/DIV
R6
V
800mA
OUT1
FB1
499k
C1
22µF
100k
(1A, V > 3.0V)
R1
IN
1.0M
3521 TA03b
R2
500µs/DIV
PGOOD3
SHDN1
PGOOD1
PWM
PGND1A
PGND1B
221k
SHDN2
PGOOD2
SHDN3
R5
499k
PGOOD1
ON
PWM
OFF
BURST
GND PGND2
3521 TA03a
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LTC3100
700mA I , 1.5MHz, Synchronous Step-Up, 250mA
94% Efficiency, V : 0.7V to 5V, V
SD
= 5.25V, I = 15µA,
OUT(MAX) Q
SW
IN
Synchronous Step-Down DC/DC Converter and 100mA LDO
I
< 1µA, 3mm × 3mm QFN-16 Package
LTC3101
LTC3409
Wide V , Multioutput DC/DC Converter and PowerPath™
95% Efficiency, V : 1.8V to 5.5V, I = 38µA, Standby I = 15µA,
IN
IN
Q
Q
Controller, 800mA Buck-Boost, Dual 350mA Buck
Converters, 50mA Always-On LDO
4mm × 4mm QFN-24 Package
600mA I , 1.7MHz/2.6MHz, Synchronous Step-Down DC/ 96% Efficiency, V : 1.6V to 5.5V, V
= 0.6V, I = 65µA,
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MAX)
OUT(MAX)
Q
DC Converter
I
< 1µA, DFN Package
SD
LTC3441/LTC3442/
LTC3443
1.2A I , 2MHz, Synchronous Buck-Boost DC/DC
95% Efficiency, V : 2.4V to 5.5V, V
: 2.4V to 5.25V,
OUT
IN
Converter
I = 50µA, I < 1µA, DFN Package
Q SD
LTC3520
1A 2MHz, Synchronous Buck-Boost and 600mA Buck
Converter
95% Efficiency, V : 2.2V to 5.5V, V
= 5.25V, I = 55µA,
Q
IN
I
< 1µA, 4mm × 4mm QFN-24 Package
SD
LTC3522
400mA 2MHz, Synchronous Buck-Boost and 200mA Buck
Converter
95% Efficiency, V : 2.4V to 5.5V, V
= 5.25V, I = 25µA,
Q
IN
I
< 1µA, 3mm × 3mm QFN-16 Package
SD
LTC3531/LTC3531-3/ 200mA I , 1.5MHz, Synchronous Buck-Boost DC/DC
95% Efficiency, V : 1.8V to 5.5V, V
SD
: 2V to 5V, I = 16µA,
OUT
IN
OUT(MIN)
Q
LTC3531-3.3
Converter
I
< 1µA, ThinSOT and DFN Packages
LTC3532
500mA I , 2MHz, Synchronous Buck-Boost DC/DC
95% Efficiency, V : 2.4V to 5.5V, V
: 2.4V to 5.25V,
OUT
IN
OUT(MIN)
Converter
I = 35µA, I < 1µA, MS10 and DFN Packages
Q SD
LTC3547
Dual 300mA I , 2.25MHz, Synchronous Step-Down DC/
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40µA,
OUT(MIN) Q
OUT
IN
DC Converter
I
< 1µA, DFN-8 Package
SD
3521fb
LT 0813 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
22
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3521
●
●
LINEAR TECHNOLOGY CORPORATION 2010
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