LTC3548EKD-1-PBF_技术文档

LTC3548-1

Dual Synchronous, Fixed

Output 2.25MHz Step-Down

DC/DC Regulator

FEATURES

DESCRIPTION

TheLTC^®3548-1isadual,ﬁxedoutput,constantfrequency,

synchronousstep-downDC/DCconverter.Intendedforlow

power applications, it operates from 2.5V to 5.5V input

voltage range and has a constant 2.25MHz switching

frequency, allowing the use of tiny, low cost capacitors

and inductors with a proﬁle ≤1mm. The output voltage

for channel 1 is ﬁxed at 1.8V and for channel 2 is ﬁxed

at 1.575V. Internal synchronous 0.35Ω, 1.2A/0.7A power

switches provide high efﬁciency without the need for ex-

ternal Schottky diodes. Burst Mode^®operation provides

high efﬁciency at light loads.

n

High Efﬁciency: Up to 95%

n

1.8V at 800mA/1.575V at 400mA

n

Very Low Quiescent Current: Only 40μA

n

2.25MHz Constant Frequency Operation

n

High Switch Current: 1.2A and 0.7A

n

No Schottky Diodes Required

n

V : 2.5V to 5.5V

IN

n

Current Mode Operation for Excellent Line

and Load Transient Response

Short-Circuit Protected

n

Low Dropout Operation: 100% Duty Cycle

n

Ultralow Shutdown Current: I < 1μA

Q

To further maximize battery runtime, the P-channel

MOSFETs are turned on continuously in dropout (100%

duty cycle), and both channels draw a total quiescent cur-

rent of only 40μA. In shutdown, the device draws <1μA.

n

Small Thermally Enhanced 3mm × 3mm

DFN Packages

APPLICATIONS

The LTC3548-1 is available in both thin (0.75mm) and

ultra-thin (0.55mm) 3mm × 3mm DFN packages.

n

PDAs/Palmtop PCs

n

L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation

All other trademarks are the property of their respective owners. Protected by U.S. Patents

including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.

Digital Cameras

n

Cellular Phones

n

Portable Media Players

n

PC Cards

n

Wireless and DSL Modems

TYPICAL APPLICATION

LTC3548-1 Efﬁciency Curve/Power Loss

100

95

90

85

80

75

70

65

60

1000

100

10

V

IN

2.7V TO 5.5V

C

10μF

CER

IN

V

RUN1 RUN2

LTC3548-1

IN

V

= 1.8V

OUT1

4.7μH

2.2μH

V

OUT1

OUT2

1.575V

400mA

1.8V

SW2

SW1

V

= 1.575V

OUT2

800mA

V

OUT1

C

OUT2

C

OUT1

OUT2

10μF

CER

C

FF1

330pF

FF2

330pF

10μF

CER

V

1

FB2

FB1

3548-1 F01

GND

CHANNEL 1

CHANNEL 2

0.1

1000

1

10

100

Figure 1. 1.8V/1.575V at 800mA/400mA Step-Down Regulators

LOAD CURRENT (mA)

35481 F01b

35481fb

1

LTC3548-1

ABSOLUTE MAXIMUM RATINGS

(Note 1)

V Voltages.................................................–0.3V to 6V

Ambient Operating Temperature Range

IN

V

, V , V

, V

,

(Note 2)....................................................–40°C to 85°C

Junction Temperature (Note 5) ............................. 125°C

Storage Temperature Range...................– 65°C to 125°C

FB1 FB2 OUT1 OUT2

RUN1, RUN2 Voltages ..................... –0.3V to V + 0.3V

IN

SW1, SW2 Voltage........................... –0.3V to V + 0.3V

IN

PIN CONFIGURATION

TOP VIEW

V

OUT1

V

1

2

3

4

5

10

9

V

1

2

3

4

5

10

9

V

FB1

FB2

OUT2

FB1

FB2

V

OUT1

OUT2

IN

RUN1

SW2

11

8

V

8

RUN1

SW2

IN

SW1

GND

7

SW1

GND

7

RUN2

6

RUN2

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

KD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC UTDFN

T

= 125°C, θ = 43°C/W, θ = 10°C/W

JA JC

T

= 125°C, θ = 40°C/W, θ = 3°C/W

JMAX

JA

JC

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND

(SOLDERED TO A 4-LAYER BOARD)

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND

(SOLDERED TO A 4-LAYER BOARD)

ORDER INFORMATION

LEAD FREE FINISH

LTC3548EDD-1#PBF

LTC3548EKD-1#PBF

TAPE AND REEL

PART MARKING

LBZC

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3548EDD-1#TRPBF

LTC3548EKD-1#TRPBF

10-Lead (3mm × 3mm) Plastic DFN

10-Lead (3mm × 3mm) Plastic UTDFN

–40°C to 85°C

CXVT

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

35481fb

2

LTC3548-1

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 3.6V, unless otherwise speciﬁed. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Operating Voltage Range

Output Voltage

●

2.5

5.5

V

IN

0°C ≤ T ≤ 85°C (Note 3)

1.764

1.755

1.8

1.836

V

OUT1

A

–40°C ≤ T ≤ 85°C (Note 3)

A

V

OUT2

Output Voltage

0°C ≤ T ≤ 85°C (Note 3)

1.544

1.536

1.575 1.607

V

A

–40°C ≤ T ≤ 85°C (Note 3)

A

ΔV

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

= 2.5V to 5.5V (Note 3)

0.3

0.5

%/V

%

LINE REG

IN

(Note 3)

LOAD REG

I

S

Input DC Supply Current

Active Mode

V

= 1.5V, V

= 1.9V, V

= 1.3V

700

40

0.1

950

60

1

μA

OUT1

OUT2

Sleep Mode

= 1.65V

Shutdown

RUN = 0V, V = 5.5V

IN

f

I

Oscillator Frequency

V

= 1.8V, V = 1.575V

OUT2

●

1.8

2.25

2.7

MHz

OSC

OUT1

Peak Switch Current Limit Channel 1

Peak Switch Current Limit Channel 2

V

IN

V

IN

= 3V, Duty Cycle <35%

0.95

0.6

1.2

0.7

1.6

0.9

A

LIM

R

Top Switch On-Resistance

Bottom Switch On-Resistance

(Note 6)

0.35

0.30

0.45

Ω

DS(ON)

I

Switch Leakage Current

RUN Threshold

V

IN

= 5V, V

= 0V, V

= V = 0

OUT2

0.01

1

1.5

1

μA

V

SW(LKG)

RUN

OUT1

V

●

0.3

RUN

I

RUN Leakage Current

0.01

μA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: The LTC3548-1 is tested in a proprietary test mode that connects

the output of the error ampliﬁer to an outside servo-loop.

Note 4: Dynamic supply current is higher due to the internal gate charge

being delivered at the switching frequency.

Note 2: The LTC3548-1 is guaranteed to meet speciﬁed performance

from 0°C to 85°C. Speciﬁcations over the –40°C and 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

Note 5: T is calculated from the ambient T and power dissipation P

D

J

A

according to the following formula: T = T + (P • θ ).

J

A

D

JA

Note 6: The DFN switch on-resistance is guaranteed by correlation to

wafer level measurements.

T_A= 25°C unless otherwise speciﬁed.

TYPICAL PERFORMANCE CHARACTERISTICS

Burst Mode Operation

Load Step

V

OUT2

200mV/DIV

SW

5V/DIV

V

OUT1

200mV/DIV

I

L

I

200mA/DIV

L

I

L

500mA/DIV

200mA/DIV

I

LOAD

I

LOAD

40mA TO

400mA

80mA TO

800mA

V

OUT1

20mV/DIV

200mA/DIV

500mA/DIV

3548-1 G03

3548-1 G02

3548-1 G01

V

I

= 3.6V

20μs/DIV

V

I

= 3.6V

20μs/DIV

V

I

= 3.6V

2μs/DIV

IN

OUT2

IN

OUT1

IN

OUT1

= 1.575V

= 40mA TO 400mA

= 1.8V

= 80mA TO 800mA

= 1.8V

= 60mA

LOAD

CHANNEL 2; CIRCUIT OF FIGURE 3

CHANNEL 1; CIRCUIT OF FIGURE 3

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3

LTC3548-1

TYPICAL PERFORMANCE CHARACTERISTICS T_A= 25°C unless otherwise speciﬁed.

Oscillator Frequency

vs Temperature

Oscillator Frequency

vs Input Voltage

Efﬁciency vs Input Voltage

2.5

2.4

2.3

2.2

2.1

2.0

10

8

100

95

90

85

80

75

70

65

60

V

= 3.6V

IN

I

= 100mA

OUT

6

4

2

0

I

= 800mA

OUT

I

= 10mA

OUT

–2

–4

–6

–8

–10

I

= 1mA

OUT

4

4.5

2

2.5

3

3.5

5

5.5

6

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

4

5

6

2

3

INPUT VOLTAGE (V)

3548-1 G04

3548-1 G05

3548-1 G06

Output Voltage Error

vs Temperature

R_DS(ON)vs Input Voltage

R_DS(ON)vs Junction Temperature

1

0.8

500

450

400

350

300

250

200

550

500

450

400

350

300

250

200

150

100

V

= 3.6V

V

= 2.7V

IN

V

= 3.6V

IN

0.6

V

= 4.2V

IN

0.4

MAIN

SWITCH

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

SYNCHRONOUS

SWITCH

MAIN SWITCH

SYNCHRONOUS SWITCH

3

5

7

1

2

4

6

50

100 125 150

–50

0

25

50

75 100 125

–50 –25

0

25

75

–25

TEMPERATURE (°C)

INPUT VOLTAGE (V)

JUNCTION TEMPERATURE (°C)

3548-1 G08

3548-1 G07

3548-1 G09

Efﬁciency vs Load Current

Load Regulation

Line Regulation

100

95

90

85

80

75

70

65

60

2.0

1.5

0.5

0.4

0.3

V

= 1.8V

1.0

OUT1

0.2

V

= 1.8V

V

= 1.8V

OUT1

0.5

0.1

V

= 1.575V

OUT2

V

= 1.575V

OUT2

0

V

= 1.575V

OUT2

–0.1

–0.2

–0.3

–0.4

–0.5

–1.0

–1.5

–2.0

1

10

100

1000

1

10

100

1000

2.5

3

4

4.5

5

5.5

3.5

LOAD CURRENT (mA)

3548-1 G11

3548-1 G12

3548-1 G15

35481fb

4

LTC3548-1

TYPICAL PERFORMANCE CHARACTERISTICS T_A= 25°C unless otherwise speciﬁed.

Efﬁciency vs Load Current

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

V

= 3.6V

V

= 2.7V

IN

V

= 3.6V

V

= 2.7V

IN

V

= 4.2V

IN

V

= 4.2V

IN

V

= 1.575V

V

= 1.8V

OUT2

OUT1

NO LOAD ON OTHER CHANNEL

CIRCUIT OF FIGURE 3

NO LOAD ON OTHER CHANNEL

CIRCUIT OF FIGURE 3

1

10

100

1000

1

10

100

1000

LOAD CURRENT (mA)

3548-1 G17

3548-1 G16

PIN FUNCTIONS

FB1

feedback voltage from internal resistive divider across the

output. Normal voltage for this pin is 0.6V.

V

(Pin 1): Output Feedback for Channel 1. Receives the

SW2 (Pin 7): Regulator 2 Switch Node Connection to the

Inductor. This pin swings from V to GND.

IN

RUN1(Pin8):Regulator1Enable.ForcingthispintoV en-

IN

V

(Pin 2): Output Voltage Feedback Pin for Channel 1.

ablesregulator1,whileforcingittoGNDcausesregulator1

OUT1

Aninternalresistivedividerdividestheoutputvoltagedown

to shut down. This pin must be driven; do not ﬂoat.

for comparison to the internal reference voltage.

V

(Pin 9): Output Voltage Feedback Pin for Channel 2.

OUT2

V (Pin3):InputPowerSupply.Mustbecloselydecoupled

Aninternalresistivedividerdividestheoutputvoltagedown

IN

to GND.

for comparison to the internal reference voltage.

SW1 (Pin 4): Regulator 1 Switch Node Connection to the

V

(Pin 10): Output Feedback for Channel 2. Receives

FB2

Inductor. This pin swings from V to GND.

the feedback voltage from internal resistive divider across

the output. Normal voltage for this pin is 0.6V.

IN

GND (Pin 5): Ground. Connect to the (–) terminal of C

OUT

and (–) terminal of C (see Figure 4).

Exposed Pad (GND) (Pin 11): Ground. Connect to the

IN

(–) terminal of C , and (–) terminal of C . Must be con-

OUT

IN

RUN2(Pin6):Regulator2Enable.ForcingthispintoV en-

IN

nected to electrical ground on PCB (see Figure 4).

ablesregulator2,whileforcingittoGNDcausesregulator2

to shut down. This pin must be driven; do not ﬂoat.

35481fb

5

LTC3548-1

BLOCK DIAGRAM

REGULATOR 1

V

IN

BURST

CLAMP

V

IN

SLOPE

COMP

EN

BURST

–

+

0.6V

SLEEP

–

+

I

TH

5ꢀ

EA

I

COMP

0.35V

–

V

2

1

OUT1

S

R

Q

V

FB

R1

RS

LATCH

V

FB1

Q

0.55V

–

+

R3

SWITCHING

LOGIC

UV

OV

UVDET

OVDET

AND

BLANKING

CIRCUIT

ANTI

SHOOT-

THRU

4

SW1

+

–

0.65V

+

–

I

RCMP

SHUTDOWN

11 GND

V

IN

3

5

V

IN

8

6

RUN1

RUN2

0.6V REF

OSC

GND

SW2

REGULATOR 2 (IDENTICAL TO REGULATOR 1)

9

V

OUT2

R1 = 240k, R3 = 120k FOR REGULATOR 1

R1 = 195k, R3 = 120k FOR REGULATOR 2

7

10

V

FB2

3548-1 BD

35481fb

6

LTC3548-1

OPERATION

The LTC3548-1 uses a constant frequency, current mode

architecture. The operating frequency is set at 2.25MHz.

Both channels share the same clock and run in-phase.

Low Current Operation

When the load is relatively light, the LTC3548-1 auto-

matically switches into Burst Mode operation, in which

the PMOS switch operates intermittently based on load

demand with a ﬁxed peak inductor current. By running

cycles periodically, the switching losses which are domi-

nated by the gate charge losses of the power MOSFETs

are minimized. The main control loop is interrupted when

the output voltage reaches the desired regulated value. A

The output voltage is set by an internal divider. An error

amplﬁer compares the divided output voltage with a

reference voltage of 0.6V and adjusts the peak inductor

current accordingly.

Main Control Loop

voltagecomparatortripswhenI isbelow0.35V,shutting

TH

Duringnormaloperation,thetoppowerswitch(P-channel

MOSFET) is turned on at the beginning of a clock cycle

off the switch and reducing the power. The output capaci-

tor and the inductor supply the power to the load until I

TH

when the V

voltage is below the regulated voltage. The

OUT

exceeds 0.65V, turning on the switch and the main control

current ﬂows into the inductor and the load increases until

current limit is reached. The switch turns off and energy

stored in the inductor ﬂows through the bottom switch

(N-channel MOSFET) into the load until the next

clock cycle.

loop which starts another cycle.

Dropout Operation

When the input supply voltage decreases toward the

output voltage, the duty cycle increases to 100% which

is the dropout condition. In dropout, the PMOS switch is

turnedoncontinuouslywiththeoutputvoltagebeingequal

to the input voltage minus the voltage drops across the

internal p-channel MOSFET and the inductor.

The peak inductor current is controlled by the internally

compensated I voltage, which is the output of the error

TH

ampliﬁer.ThisampliﬁercomparesthefeedbackvoltageV

FB

to the 0.6V reference (see Block Diagram). When the load

currentincreases,theV voltagedecreasesslightlybelow

FB

the reference. This decrease causes the error ampliﬁer to

An important design consideration is that the R

DS(ON)

increase the I voltage until the average inductor current

of the P-channel switch increases with decreasing input

supply voltage (see Typical Performance Characteristics).

Therefore, the user should calculate the power dissipation

when the LTC3548-1 is used at 100% duty cycle with low

input voltage (see Thermal Considerations in the Applica-

tions Information section).

TH

matches the new load current.

The main control loop is shut down by pulling the RUN

pin to ground.

Low Supply Operation

Topreventunstableoperation,theLTC3548-1incorporates

an undervoltage lockout circuit which shuts down the part

when the input voltage drops below about 1.65V.

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7

LTC3548-1

APPLICATIONS INFORMATION

A general LTC3548-1 application circuit is shown in

Figure 2. External component selection is driven by the

load requirement, and begins with the selection of the

higher ripple current which causes this to occur at lower

load currents. This causes a dip in efﬁciency in the upper

range of low current operation. In Burst Mode operation,

lower inductance values will cause the burst frequency

to increase.

inductor L. Once the inductor is chosen, C and C

IN

OUT

can be selected.

Inductor Core Selection

V

IN

2.7V TO 5.5V

C

10μF

CER

IN

Different core materials and shapes will change the size/

currentandprice/currentrelationshipofaninductor.Toroid

or shielded pot cores in ferrite or permalloy materials are

small and don’t radiate much energy, but generally cost

more than powdered iron core inductors with similar elec-

trical characterisitics. The choice of which style inductor

to use often depends more on the price vs size require-

ments and any radiated ﬁeld/EMI requirements than on

what the LTC3548-1 requires to operate. Table 1 shows

some typical surface mount inductors that work well in

LTC3548-1 applications.

V

RUN1 RUN2

LTC3548-1

IN

4.7μH

2.2μH

V

OUT1

1.8V

800mA

OUT2

1.575V

400mA

SW2

SW1

V

OUT1

C

OUT2

FB2

C

OUT1

OUT2

10μF

CER

C

FF2

330pF

FF1

330pF

10μF

CER

V

FB1

3548-1 F01

GND

Figure 2. LTC3548-1 General Schematic

Inductor Selection

Table 1. Representative Surface Mount Inductors

Althoughtheinductordoesnotinﬂuencetheoperatingfre-

quency, the inductor value has a direct effect on ripple cur-

PART

NUMBER

VALUE

(μH)

DCR

MAX DC

SIZE

3

(Ω MAX) CURRENT (A) W × L × H (mm )

rent. The inductor ripple current ΔI decreases with higher

L

Sumida

CDRH3D16

2.2

3.3

4.7

0.075

0.110

0.162

1.20

1.10

0.90

3.8 × 3.8 × 1.8

inductance and increases with higher V or V

:

IN

OUT

ꢁ

ꢃ

ꢂ

_OUTꢄ

V

V_OUT

f_O•L

Sumida

CMD4D06

2.2

4.7

0.089

0.166

0.95

0.75

4.1 × 3.2 × 0.8

4.4 × 5.8 × 1.2

2.5 × 3.2 × 2.0

4.5 × 5.4 × 1.2

ꢀI_L=

• 1–

ꢆ

V

ꢅ

IN

Sumida

CMD4D11

2.2

3.3

0.116

0.174

0.950

0.770

Accepting larger values of ΔI allows the use of low induc-

L

Murata

LQH32CN

1.0

2.2

0.060

0.097

1.00

0.79

tances, but results in higher output voltage ripple, greater

core losses, and lower output current capability.

Toko

D312F

2.2

3.3

0.060

0.260

1.08

0.92

A reasonable starting point for setting ripple current is

ΔI =0.3•I

, whereI

is0.8Aforchannel1

L

OUT(MAX)

Panasonic

ELT5KT

3.3

4.7

0.17

0.20

1.00

0.95

and 400mA for channel 2. The largest ripple current ΔI

L

occurs at the maximum input voltage. To guarantee that

the ripple current stays below a speciﬁed maximum, the

inductor value should be chosen according to the follow-

ing equation:

Input Capacitor (C ) Selection

IN

In continuous mode, the input current of the converter is a

square wave with a duty cycle of approximately V /V .

ꢁ

ꢄ

OUT IN

V_OUT

f_O• ꢀI_L

V_OUT

L =

• 1–

Topreventlargevoltagetransients, alowequivalentseries

resistance (ESR) input capacitor sized for the maximum

RMS current must be used. The maximum RMS capacitor

current is given by:

ꢃ

ꢆ

V

ꢂ

ꢅ

IN(MAX)

The inductor value will also have an effect on Burst Mode

operation. The transition from low current operation

begins when the peak inductor current falls below a level

set by the burst clamp. Lower inductor values result in

V_OUTV – V

(

)

IN

OUT

I_RMS≈I_MAX

V

IN

35481fb

8

LTC3548-1

APPLICATIONS INFORMATION

where the maximum average output current I

equals

of any aluminum electrolytic at a somewhat higher price.

Special polymer capacitors, such as Sanyo POSCAP,

Panasonic Special Polymer (SP), and Kemet A700, of-

fer very low ESR, but have a lower capacitance density

than other types. Tantalum capacitors have the highest

capacitance density, but they have a larger ESR and it

is critical that the capacitors are surge tested for use in

switching power supplies. An excellent choice is the AVX

TPS series of surface mount tantalums, available in case

heightsrangingfrom2mmto4mm.Aluminumelectrolytic

capacitors have a signiﬁcantly larger ESR, and are often

usedinextremelycost-sensitiveapplicationsprovidedthat

consideration is given to ripple current ratings and long

term reliability. Ceramic capacitors have the lowest ESR

and cost, but also have the lowest capacitance density,

a high voltage and temperature coefﬁcient, and exhibit

audible piezoelectric effects. In addition, the high Q of

ceramic capacitors along with trace inductance can lead

to signiﬁcant ringing.

MAX

the peak current minus half the peak-to-peak ripple cur-

rent, I = I – ΔI /2.

MAX

LIM

L

This formula has a maximum at V = 2V , where I

RMS

IN

OUT

= I /2. This simple worst-case is commonly used to

OUT

design because even signiﬁcant deviations do not offer

much relief. Note that capacitor manufacturer’s ripple cur-

rent ratings are often based on only 2000 hours lifetime.

This makes it advisable to further derate the capacitor,

or choose a capacitor rated at a higher temperature than

required.Severalcapacitorsmayalsobeparalleledtomeet

thesizeorheightrequirementsofthedesign.Anadditional

0.1μF to 1μF ceramic capacitor is also recommended on

V for high frequency decoupling, when not using an all

IN

ceramic capacitor solution.

Output Capacitor (C ) Selection

OUT

The selection of C

is driven by the required ESR to

OUT

minimizevoltagerippleandloadsteptransients. Typically,

once the ESR requirement is satisﬁed, the capacitance

In most cases, 0.1μF to 1μF of ceramic capacitors should

also be placed close to the LTC3548-1 in parallel with the

main capacitors for high frequency decoupling.

is adequate for ﬁltering. The output ripple (ΔV ) is

OUT

determined by:

ꢂ

ꢅ

1

Ceramic Input and Output Capacitors

ꢀV_OUTꢁ ꢀI_LESR+

ꢄ

ꢇ

8f_OC

ꢃ

_OUTꢆ

Higher value, lower cost ceramic capacitors are now be-

comingavailableinsmallercasesizes. Thesearetempting

for switching regulator use because of their very low ESR.

Unfortunately, the ESR is so low that it can cause loop

stabilityproblems.SolidtantalumcapacitorESRgenerates

aloop“zero”at5kHzto50kHzthatisinstrumentalingiving

acceptableloopphasemargin. Ceramiccapacitorsremain

capacitivetobeyond300kHzandusuallyresonatewiththeir

ESLbeforeESRbecomeseffective. Also, ceramiccapsare

prone to temperature effects which requires the designer

to check loop stability over the operating temperature

range. To minimize their large temperature and voltage

coefﬁcients, only X5R or X7R ceramic capacitors should

beused.Agoodselectionofceramiccapacitorsisavailable

from Taiyo Yuden, AVX, Kemet, TDK, and Murata.

wheref =operatingfrequency,C

=outputcapacitance

O

OUT

and ΔI = ripple current in the inductor. The output ripple

L

is highest at maximum input voltage since ΔI increases

L

with input voltage. With ΔI = 0.3 • I

the output

L

OUT(MAX)

ripple will be less than 100mV at maximum V and

IN

f = 2.25MHz with:

O

ESR

< 150mΩ

COUT

Once the ESR requirements for C

have been met, the

OUT

RMS current rating generally far exceeds the I

RIPPLE(P-P)

requirement, except for an all ceramic solution.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the capacitance, ESR or

RMS current handling requirement of the application.

Aluminum electrolytic, special polymer, ceramic and dry

tantulum capacitors are all available in surface mount

packages.TheOS-CONsemiconductordielectriccapacitor

available from Sanyo has the lowest ESR(size) product

Great care must be taken when using only ceramic input

and output capacitors. When a ceramic capacitor is used

at the input and the power is being supplied through long

wires, suchasfromawalladapter, aloadstepattheoutput

35481fb

9

LTC3548-1

APPLICATIONS INFORMATION

can induce ringing at the V pin. At best, this ringing can

margin.Inaddition,afeed-forwardcapacitor,C ,isadded

IN

FF

couple to the output and be mistaken as loop instability.

At worst, the ringing at the input can be large enough to

damage the part.

externallytoimprovethehighfrequencyresponse.Capaci-

tor C provides phase lead by creating a high frequency

FF

zero with R1, which improves the phase margin.

Since the ESR of a ceramic capacitor is so low, the input

and output capacitor must instead fulﬁll a charge storage

requirement.Duringaloadstep,theoutputcapacitormust

instantaneously supply the current to support the load

until the feedback loop raises the switch current enough

to support the load. The time required for the feedback

loop to respond is dependent on the compensation and

theoutputcapacitorsize. Typically, 3-4cyclesarerequired

to respond to a load step, but only in the ﬁrst cycle does

Theoutputvoltagesettlingbehaviorisrelatedtothestability

of the closed-loop system and will demonstrate the actual

overall supply performance. For a detailed explanation of

optimizing the compensation components, including a re-

view of control loop theory, refer to Application Note 76.

In some applications, a more severe transient can be

caused by switching loads with large (>1μF) load input

capacitors. The discharged load input capacitors are ef-

fectively put in parallel with C , causing a rapid drop in

OUT

the output drop linearly. The output droop, V

, is

DROOP

V

OUT

. No regulator can deliver enough current to prevent

usually about 2-3 times the linear drop of the ﬁrst cycle.

Thus, a good place to start is with the output capacitor

size of approximately:

this problem, if the switch connecting the load has low

resistance and is driven quickly. The solution is to limit

the turn-on speed of the load switch driver. A Hot Swap™

controller is designed speciﬁcally for this purpose and

usuallyincorporatescurrentlimiting, short-circuitprotec-

tion, and soft-starting.

ΔI_OUT

f_O• V_DROOP

C_OUT≈2.5

More capacitance may be required depending on the duty

cycle and load step requirements.

Efﬁciency Considerations

Inmostapplications,theinputcapacitorismerelyrequired

to supply high frequency bypassing, since the impedance

to the supply is very low. A 10μF ceramic capacitor is

usually enough for these conditions.

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

Checking Transient Response

The regulator loop response can be checked by look-

ing at the load transient response. Switching regulators

take several cycles to respond to a step in load current.

% Efﬁciency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

When a load step occurs, V

immediately shifts by an

OUT

amount equal to ΔI

• ESR, where ESR is the effective

LOAD

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of

series resistance of C . ΔI

also begins to charge

OUT

LOAD

or discharge C , generating a feedback error signal

OUT

the losses in LTC3548-1 circuits: 1)V quiescent current,

IN

used by the regulator to return V

value. During this recovery time, V

to its steady-state

can be monitored

2

OUT

2) switching losses, 3) I R losses, 4) other losses.

1) The V current is the DC supply current given in the

for overshoot or ringing that would indicate a stability

problem.

IN

ElectricalCharacteristicswhichexcludesMOSFETdriver

and control currents. V current results in a small

IN

The initial output voltage step may not be within the band-

width of the feedback loop, so the standard second-order

overshoot/DC ratio cannot be used to determine phase

(<0.1%) loss that increases with V , even at no load.

IN

Hot Swap is a trademark of Linear Technology Corporation.

35481fb

10

LTC3548-1

APPLICATIONS INFORMATION

2) The switching current is the sum of the MOSFET driver

and control currents. The MOSFET driver current re-

sults from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

duty cycles, such as in dropout, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 150°C,

both power switches will turn off and the SW node will

become high impedance.

from V to ground. The resulting dQ/dt is a current

IN

To prevent the LTC3548-1 from exceeding the maximum

junctiontemperature,theuserwillneedtodosomethermal

analysis. The goal of the thermal analysis is to determine

whether the power dissipated exceeds the maximum

junction temperature of the part. The temperature rise is

given by:

out of V that is typically much larger than the DC bias

IN

current. In continuous mode, I

= f (Q + Q ),

GATECHG

O T B

where Q and Q are the gate charges of the internal

T

B

top and bottom MOSFET switches. The gate charge

losses are proportional to V and thus their effects

IN

will be more pronounced at higher supply voltages.

T

= P • θ

D JA

2

RISE

3) I R losses are calculated from the DC resistances of

where P is the power dissipated by the regulator and θ

the internal switches, R , and external inductor, R .

D

JA

SW

L

is the thermal resistance from the junction of the die to

In continuous mode, the average output current ﬂows

throughinductorL,butis“chopped”betweentheinternal

top and bottom switches. Thus, the series resistance

looking into the SW pin is a function of both top and

the ambient temperature.

The junction temperature, T , is given by:

J

T = T

J

+ T

AMBIENT

bottom MOSFET R

follows:

and the duty cycle (D) as

RISE

DS(ON)

As an example, consider the case when the LTC3548-1 is

at an input voltage of 2.7V with a load current of 400mA

and 800mA and an ambient temperature of 70°C. From

the Typical Performance Characteristics graph of Switch

R

= (R

)(D) + (R

)(1 – D)

SW

DS(ON)TOP

DS(ON)BOT

TheR

forboththetopandbottomMOSFETscanbe

DS(ON)

obtained from the Typical Performance Characteristics

Resistance, the R

resistance of the main switch is

DS(ON)

2

curves. Thus, to obtain I R losses:

0.425Ω. Therefore, power dissipated by each channel is:

2

I R losses = I

(R + R )

SW L

2

OUT

P = I • R

= 272mW and 68mW

D

DS(ON)

4) Other“hidden”lossessuchascoppertraceandinternal

batteryresistancescanaccountforadditionalefﬁciency

degradations in portable systems. It is very important

to include these “system” level losses in the design of a

system. The internal battery and fuse resistance losses

The DFN package junction-to-ambient thermal resistance,

JA

the regulator operating in a 70°C ambient temperature is

approximately:

θ , is 40°C/W. Therefore, the junction temperature of

T = (0.272 + 0.068) • 40 + 70 = 83.6°C

J

can be minimized by making sure that C has adequate

IN

charge storage and very low ESR at the switching fre-

quency.Otherlossesincludingdiodeconductionlosses

during dead-time and inductor core losses generally

account for less than 2% total additional loss.

which is below the absolute maximum junction tempera-

ture of 125°C.

Design Example

As a design example, consider using the LTC3548-1 in

an portable application with a Li-Ion battery. The battery

Thermal Considerations

In a majority of applications, the LTC3548-1 does not

dissipate much heat due to its high efﬁciency. However,

in applications where the LTC3548-1 is running at high

ambient temperature with low supply voltage and high

providesaV =2.8Vto4.2V.Theloadrequiresamaximum

IN

of 800mA in active mode and 2mA in standby mode. The

output voltage is V

= 1.8V.

OUT

35481fb

11

LTC3548-1

APPLICATIONS INFORMATION

First, calculate the inductor value for about 30% ripple

Board Layout Considerations

current at maximum V :

IN

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

theLTC3548-1.Theseitemsarealsoillustratedgraphically

in the layout diagram of Figure 4. Check the following in

your layout:

1.8V

L =

1.8V

4.2V

ꢀ

ꢁ

ꢃ

ꢄ

• 1–

=1.9μH

ꢂ

ꢅ

2.25MHz •240mA

Choosing a vendor’s closest inductor value of 2.2μH,

results in a maximum ripple current of:

1. Does the capacitor C connect to the power V (Pin 3)

IN

and GND (exposed pad) as close as possible? This

capacitor provides the AC current to the internal power

MOSFETs and their drivers.

1.8V

2.25MHz •2.2μ

1.8V

4.2V

ꢂ

ꢃ

ꢅ

ꢆ

ꢀI_L=

• 1ꢁ

= 207mA

ꢄ

ꢇ

For cost reasons, a ceramic capacitor will be used. C

OUT

2. The feedback lines from V

should be routed away

OUT

selection is then based on load step droop instead of ESR

from noisy traces such as the SW line and its trace

should be minimized.

requirements. For a 5% output droop:

800mA

2.25MHz •(5%•1.8V)

3. Are the C

and L1 closely connected? The (–) plate of

OUT

C_OUT≈1.8

= 7.1μF

C

returns current to GND and the (–) plate of C .

OUT

IN

4. Keep sensitive components away from the SW pins.

Agoodstandardvalueis10μF.Sincetheoutputimpedance

The input capacitor C should be routed away from

IN

of a Li-lon battery is very low, C is typically 10μF.

IN

the SW traces and the inductors.

Figure 3 shows the complete schematic for this design

example.

5. Agroundplaneispreferred,butifnotavailable,keepthe

signal and power grounds segregated with small signal

components returning to the GND pin at one point and

should not share the high current path of C or C

.

IN

OUT

6. Floodallunusedareasonalllayerswithcopper.Flooding

with copper will reduce the temperature rise of power

components. These copper areas should be connected

to V or GND.

IN

V

IN

2.7V TO 5.5V

C

IN

10μF

CER

V

IN

RUN1 RUN2

LTC3548-1

4.7μH

2.2μH

V

OUT1

OUT2

1.8V

1.575V

400mA

SW2

SW1

800mA

V

OUT1

C

10μF

CER

OUT2

C

OUT1

OUT2

C

FF1

330pF

FF2

10μF

330pF

CER

V

FB2

FB1

3548-1 F01

GND

Figure 3. LTC3548-1 Typical Application

35481fb

12

LTC3548-1

APPLICATIONS INFORMATION

V

OUT2

L2

C

FF

C

OUT2

GND

C

FF

C

IN

C

OUT1

VIA TO V

OUT1

L1

V

OUT1

V

IN

3548-1 F04

GND

Figure 4. LTC3548-1 Layout Diagram

Efﬁciency vs Load Current

100

95

90

85

80

75

70

65

60

V

= 1.8V

OUT1

V

= 1.575V

OUT2

1

10

100

1000

LOAD CURRENT (mA)

3548-1 G11

35481fb

13

LTC3548-1

TYPICAL APPLICATIONS

1mm Proﬁle Core and I/O Supplies

V

IN

2.7V TO 5.5V

C1

10μF

V

IN

RUN1 RUN2

LTC3548-1

CER

L1

L2

4.7μH

2.2μH

V

OUT1

OUT2

1.8V

1.575V

400mA

SW2

SW1

800mA

V

OUT1

C3

10μF

CER

OUT2

FB2

C2

C

FF1

330pF

FF2

10μF

CER

330pF

V

FB1

3548-1 TA07

GND

C1, C2: MURATA GRM219R60J106KE19

C3: MURATA GRM219R60J475KE19

L1: COILTRONICS LPO3310-222MX

L2: COILTRONICS LPO3310-472MX

*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,

ADDITIONAL CAPACITANCE MAY BE REQUIRED.

Efﬁciency vs Load Current

100

95

90

V

= 1.8V

OUT1

85

80

75

70

65

60

V

= 1.575V

OUT2

1

10

100

1000

LOAD CURRENT (mA)

3548-1 G11

35481fb

14

LTC3548-1

PACKAGE DESCRIPTION

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

R = 0.115

0.38 0.10

TYP

6

10

0.675 0.05

3.50 0.05

2.15 0.05 (2 SIDES)

1.65 0.05

3.00 0.10

(4 SIDES)

1.65 0.10

(2 SIDES)

PIN 1

PACKAGE

OUTLINE

TOP MARK

(SEE NOTE 6)

(DD) DFN 1103

5

1

0.25 0.05

0.50 BSC

0.75 0.05

0.200 REF

0.25 0.05

0.50

BSC

2.38 0.10

(2 SIDES)

2.38 0.05

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

KD Package

10-Lead Plastic UTDFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1739 Rev Ø)

0.40 ± 0.10

2.00 REF

3.00 ±0.10

6

10

R = 0.05

TYP

0.675 ±0.05

2.38 ±0.05

2.38 ±0.10

3.50 ±0.05

2.15 ±0.05

3.00 ±0.10

0.55 ±0.05

1.65 ±0.05

1.65 ± 0.10

PIN 1

TOP MARK

PACKAGE

OUTLINE

(SEE NOTE 6)

(KD10) UTDFN 1106 REV Ø

5

1

0.25 ± 0.05

0.50 BSC

0.25 ± 0.05

0.125 REF

R = 0.115

0.50 BSC

TYP

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE VARIATION OF (TBI).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

35481fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LTC3548-1

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

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Dual Synchronous Step-Down DC/DC Converter

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= 0.8V, I = 60μA,

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I

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<1μA, MSOP-10 Package

LTC3412

2.5A (I ), 4MHz,

95% Efﬁciency, V : 2.5V to 5.5V, V

= 0.8V, I = 60μA,

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OUT

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Synchronous Step Down DC/DC Converter

I

SD

<1μA, TSSOP-16E Package

LTC3414

4A (I ), 4MHz,

95% Efﬁciency, V : 2.25V to 5.5V, V

SD

= 0.8V, I = 64μA,

OUT(MIN) Q

OUT

IN

Synchronous Step Down DC/DC Converter

I

<1μA, TSSOP-28E Package

LTC3440

600mA (I ), 2MHz,

95% Efﬁciency, V : 2.5V to 5.5V, V

SD

= 2.5V, I = 25μA,

Q

OUT

IN

OUT(MIN)

Synchronous Buck-Boost DC/DC Converter

I

<1μA, MSOP-10 Package

LTC3548

400mA/800mA (I ), 2.25MHz, Dual Synchronous

95% Efﬁciency, V : 2.5V to 5.5V, V

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= 0.6V, I = 40μA,

Q

OUT

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I

<1μA, MSE, DFN-10 Packages

35481fb

LT 0608 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3548EKD-1-PBF
厂家：	Linear
描述：	Dual Synchronous, Fixed Output 2.25MHz Step-Down DC/DC Regulator 双同步，固定输出的2.25MHz降压型DC / DC稳压器稳压器
文件：	总16页 (文件大小：920K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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