LTC3549EDCB#TR [Linear]
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Linear 
LTC3549
250mA Low V Buck
IN
Regulator in 2mm × 3mm DFN
U
DESCRIPTIO
FEATURES
TheLTC®3549isahighefficiency,monolithicsynchronous
buck regulator using a constant-frequency, current mode
architecture. The output voltage is adjusted via an external
resistor divider.
■
1.6V to 5.5V Input Voltage Range
■
Internal Soft-Start
Low Ripple Burst Mode® Operation
■
Output Ripple: <20mV
P-P
I : 50µA
Q
A fixed switching frequency of 2.25MHz is supported.
This switching frequency allows the use of small surface
mount inductors and capacitors, including ceramics.
■
■
■
■
■
■
■
■
■
■
2.25MHz Constant-Frequency Operation
High Efficiency: Up to 93%
250mA Output Current (V = 1.8V, V
= 1.2V)
OUT
IN
Supply current during Burst Mode operation is only 50µA
dropping to < 1µA in shutdown. The 1.6V to 5.5V input
voltage range makes the LTC3549 ideally suited for single
cell Li-Ion, Li-Metal and 2-cell alkaline, NiCd or NiMH
battery-powered applications. 100% duty cycle capabil-
ity provides low dropout operation, extending battery
life in portable systems. Burst Mode operation can be
user-enabled, increasing efficiency at light loads, further
extending battery life.
450mA Peak Inductor Current
No Schottky Diode Required
Low Dropout Operation: 100% Duty Cycle
0.611V Reference Voltage
Stable with Ceramic Capacitors
Shutdown Mode Draws <1µA Supply Current
Current Mode Operation for Excellent Line and Load
Transient Response
Overtemperature Protection
Available in a Low Profile (0.75mm) 6-Lead
(2mm x 3mm) DFN Package
■
■
The internal synchronous switch increases efficiency and
eliminatestheneedforanexternalSchottkydiode.Internal
soft-startofferscontrolledoutputvoltagerisetimeatstart-
up without the need for external components.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.
U
APPLICATIO S
■
2 AA-Cell Applications
■
Cellular Phones
■
Digital Cameras
MP3 Players
■
U
TYPICAL APPLICATIO
Burst Mode Efficiency, V
= 1.5V
OUT
100
90
80
70
60
50
40
30
20
10
0
1
High Efficiency Step-Down Converter
0.1
3.3µH*
LTC3549
V
OUT
SW
V
IN
1.5V
22pF
200k
V
IN
1.8V TO
5.5V
4.7µF
CER
4.7µF
CER
RUN
0.01
0.001
0.0001
MODE
V
FB
137k
V
= 1.8V
= 2.5V
= 3.1V
IN
IN
IN
V
GND
V
POWER LOST
3549 TA01
*TDK VLF3012AT-3R3MR87
AT V = 2.5V
IN
0.1
1
10
100
1k
LOAD CURRENT (mA)
3549 TA02
3549f
1
LTC3549
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Input Supply Voltage................................... –0.3V to 6V
RUN, V , MODE Voltages .............–0.3V to (V + 0.3V)
FB
IN
IN
6
5
7
4
SW Voltage < 100ns Pulse.............–0.3V to (V + 0.3V)
Operating Temperature Range (Note 2) ... –40°C to 85°C
Junction Temperature (Note 3) ........................... 125°C
Storage Temperature Range.................. –65°C to 125°C
1
2
3
DCB PACKAGE
6-LEAD (2mm × 3mm) PLASTIC DFN
T
JMAX
= 125°C, θ = 64°C/W
JA
EXPOSED PAD (PIN 7) IS GND
MUST BE SOLDERED TO PCB
ORDER PART NUMBER
DCB PART MARKING
LBZR
LTC3549EDCB
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C, V = 2.2V.
A
IN
SYMBOL
PARAMETER
CONDITIONS
MIN
1.6
TYP
MAX
5.5
1.1
1
UNITS
●
●
V
V
Input Voltage Range
RUN Threshold
V
V
IN
0.3
0.7
RUN
RUN
I
RUN Leakage Current
MODE Threshold
V
V
= 0 or 2.2V
0.01
0.65
0.01
µA
V
RUN
●
●
V
0.3
1.1
1
MODE
MODE
I
MODE Leakage Current
Regulated Feedback Voltage
= 0 or 2.2V
µA
MODE
V
FB
T = 25°C (Note 4)
0.599
0.597
0.596
0.611
0.611
0.611
0.623
0.623
0.626
V
V
V
A
0°C ≤ T ≤ 85°C (Note 4)
A
–40°C ≤ T ≤ 85°C (Note 4)
A
●
●
I
Feedback Current
30
80
nA
mV
%/V
%/V
A
VFB
ΔV
ΔV
ΔV
ΔV
FBOVL
Overvoltage Lockout
ΔV
= ΔV
– V (Note 6)
40
60
OVL
FB
OVL
FBOVL
FB
Reference Voltage Line Regulation
Output Voltage Line Regulation
Peak Inductor Current
1.6V < V < 5.5V (Note 4)
0.04
0.04
0.45
0.5
0.4
0.4
0.6
IN
I
= 100mA, 1.6V < V < 5.5V (Note 7)
IN
OUT
OUT
I
PK
V
FB
= 0.5V or V = 90%
OUT
0.3
V
Output Voltage Load Regulation
Pulse Skip Mode, V
50mA < I
= 1.2V,
%
LOADREG
OUT
< 250mA (Note 7)
LOAD
3549f
2
LTC3549
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C, V = 2.2V.
A
IN
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Input DC Bias Current
Active Mode
(Note 5)
S
V
V
V
= 90%, I
= 0A
LOAD
300
50
0.1
475
95
5
µA
µA
µA
OUT
OUT
RUN
LOAD
Sleep Mode
= 103%, I
= 0V, V = 5.5V
= 0A
Shutdown
IN
●
f
t
Nominal Oscillator Frequency
Soft-Start Period
1.8
2.25
1
2.7
MHz
ms
OSC
RUN↑
SS
R
R
of P-Channel FET
I
I
= 100mA, Wafer Level
0.5
Ω
Ω
PFET
NFET
LSW
DS(ON)
SW
SW
= 100mA, DD Package (Note 7)
0.56
R
R
of N-Channel FET
I
SW
I
SW
= 100mA, Wafer Level
= 100mA, DD Package (Note 7)
0.35
0.4
Ω
Ω
DS(ON)
I
SW Leakage
V
= 0V, V = 0V or 5.5V, V = 5.5V
0.1
1
µA
RUN
SW
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Voltage on any pin may not exceed 6V.
becomes active at a junction temperature greater than the maximum
operating junction temperature. Continuous operation above the specified
maximum operating junction temperature may impair device reliability.
Note 4: The LTC3549 is tested in a proprietary test mode that connects V
FB
Note 2: The LTC3549E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
to the output of the error amplifier.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: ΔV
is the amount V must exceed the regulated feedback
FB
OVL
Note 3: T is calculated from the ambient temperature T and power
J
A
voltage.
dissipation P according to the following formula:
D
Note 7: Determined by design, not production tested.
LTC3549: T = T + (P )(64°C/W)
J
A
D
This IC includes overtemperature protection that is intended to protect the
device during momentary overload conditions. Overtemperature protection
3549f
3
LTC3549
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(From Typical Application on the front page, except for the resistive divider resistor values)
Efficiency/Power Loss vs Load Efficiency/Power Loss vs Load
Efficiency vs Input Voltage
Current, V = 1.5V, Burst Mode Current, V = 1.5V, Pulse Skip
V
= 1.2V, Burst Mode Operation
OUT
OUT
OUT
100
90
80
70
60
50
40
30
20
10
0
1
100
90
80
70
60
50
40
30
20
10
0
1
100
90
80
70
60
50
40
30
20
10
0
0.1
0.1
0.01
0.001
0.0001
0.01
0.001
0.0001
I
:
OUT
0.1mA
1mA
10mA
100mA
300mA
EFFICIENCY
POWER LOSS
V
V
V
= 1.8V
= 2.5V
= 3.1V
V
V
V
= 1.8V
= 2.5V
= 3.1V
IN
IN
IN
IN
IN
IN
0.1
1
10
100
1000
0.1
1
10
100
1000
1.5
2.5
3.5
4.5
5.5
LOAD CURRENT (mA)
3549 G01a
LOAD CURRENT (mA)
3549 G01b
INPUT VOLTAGE (V)
3549 G02
EFFICIENCY
POWER LOSS
V
IN
V
IN
V
IN
= 1.8V
= 2.5V
= 3.1V
V
V
V
= 1.8V
= 2.5V
= 3.1V
IN
IN
IN
Efficiency vs Input Voltage
OUT
Efficiency vs Load Current
= 1.8V, Burst Mode
Efficiency vs Load Current
OUT
V
= 1.2V, Pulse Skip
V
V
= 1.8V, Pulse Skip
OUT
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
1
L = 4.7µH
L = 4.7µH
0.1
0.01
EFFICIENCY
V
V
V
= 2.5V
= 3.6V
= 4.2V
IN
IN
IN
0.001
EFFICIENCY
V
V
V
= 2.5V
= 3.6V
= 4.2V
IN
IN
IN
POWER LOSS
= 3.6V
V
IN
0.0001
1000
1.5
2.5
3.5
4.5
5.5
0.1
1
10
100
1000
0.1
1
10
100
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3549 G04b
3549 G03
3549 G04a
I
:
OUT
0.1mA
1mA
10mA
100mA
300mA
Efficiency vs Load Current
= 1.2V, Burst Mode
Efficiency vs Load Current
V = 1.2V, Pulse Skip
OUT
Reference Voltage
vs Temperature
V
OUT
0.6132
0.6111
0.6090
0.6069
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
V
V
= 1.6V
= 2.5V
= 3.1V
V
V
V
= 1.6V
= 2.2V
= 4.2V
IN
IN
IN
IN
IN
IN
V
V
V
= 1.6V
= 2.5V
= 3.1V
IN
IN
IN
–50 –25
0
25
50
75 100 125
0.1
1
10
100
1000
0.1
1
10
100
1000
TEMPERATURE (ºC)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3549 G06
3549f
3549 G05b
3549 G05a
4
LTC3549
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(From Typical Application on the front page, except for the resistive divider resistor values)
Oscillator Frequency
vs Temperature
Oscillator Frequency Shift
vs Input Voltage
Output Voltage vs Load Current
V
= 1.6V, V
= 1.2V
IN
OUT
1.205
1.204
1.203
1.202
1.201
1.200
1.199
2.5
2.0
2.35
2.30
V
= 2.7V
IN
V
= 1.6V
IN
1.5
2.25
2.20
1.0
0.5
BURST
V
= 4.2V
IN
0
2.15
2.10
2.05
–0.5
–1.0
–1.5
V
OUT
PULSE SKIP
–50 –25
0
25
50
75 100 125
1.5
3.5
5.5
0
200
100
LOAD CURRENT (mA)
300
2.5
4.5
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3549 G07
3549 G08
3549 G09
Dynamic Input Current
R
vs Input Voltage
R
vs Temperature
V
OUT
= 1.5V, 247kΩ Load
DS(ON)
DS(ON)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.95
0.85
0.75
0.65
0.55
0.45
0.35
0.25
0.15
10000
1000
100
70
Burst Mode
OPERATION
60
50
40
30
20
10
0
MAIN SWITCH
SYNCHRONOUS SWITCH
PULSE SKIP MODE
3.5
1.5
2.5
4.5
5.5
–50 –25
0
25
50
75 100 125
2.0 2.5
3.5
4.5 5.0 5.5
4.0 6.0
1.5
3.0
TEMPERATURE (°C)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3549 G11
3549 G10
3549 G12
MAIN SWITCH
SYNCHRONOUS SWITCH
V
IN
V
IN
V
IN
= 1.6V
= 2.7V
= 4.2V
V
V
V
= 1.6V
= 2.7V
= 4.2V
IN
IN
IN
Dynamic Supply Current vs
Switch Leakage vs Temperature
= 5.5V
Temperature, V = 3.6V,
IN
V
Switch Leakage vs Input Voltage
V
= 1.5V, No Load
IN
OUT
350
300
250
200
150
100
50
250
200
150
100
50
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
PULSE SKIP
SYNCHRONOUS SWITCH
MAIN SWITCH
MAIN SWITCH
BURST
SYNCHRONOUS
SWITCH
0
0
4
–50 –25
0
25
50
75 100 125
0
2
6
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3549 G13
3549 G15
3549 G14
3549f
5
LTC3549
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(From Typical Application on the front page, except for the resistive divider resistor values)
Start-Up from Shutdown
Burst Mode Operation
Burst Mode Operation
= 20mA
I
LOAD
V
OUT
20mV/DIV
AC COUPLED
V
OUT
V
SWITCH
2V/DIV
500mV/DIV
V
RUN
1V/DIV
I
L
100mA/DIV
I
L
3549 G19
3549 G16
50mA/DIV
1µs/DIV
200µs/DIV
V
= 2.5V
V
V
= 3.6V
OUT
1kΩ Load
IN
IN
V
= 1.2V
= 1.2V
OUT
LOAD
I
= 2OmA
Load Step 0mA to 250mA
Pulse Skip
Load Step 25mA to 250mA
Pulse Skip
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC COUPLED
AC COUPLED
I
I
LOAD
LOAD
200mA/DIV
200mA/DIV
I
L
I
L
200mA/DIV
200mA/DIV
3549 G17
3549 G18
20µs/DIV
20µs/DIV
V
V
= 2.2V
OUT
V
V
= 2.2V
OUT
IN
IN
= 1.2V
= 1.2V
Load Step 0mA to 250mA
Burst Mode Operation
Load Step 25mA to 250mA
Burst Mode Operation
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC COUPLED
AC COUPLED
I
I
LOAD
200mA/DIV
LOAD
200mA/DIV
I
L
I
L
200mA/DIV
200mA/DIV
3549 G20
3549 G21
20µs/DIV
20µs/DIV
V
V
= 2.2V
OUT
V
V
= 2.2V
IN
= 1.2V
OUT
IN
= 1.2V
3549f
6
LTC3549
U
U
U
PI FU CTIO S
V (Pin 1): Main Supply Pin. Must be closely decoupled
RUN(Pin5):RunControlInput.Forcingthispinabove1.1V
enables the part. Forcing this pin below 0.3V shuts down
thedevice.Inshutdown,allfunctionsaredisableddrawing
<1µA supply current. Do not leave RUN floating.
IN
to GND, Pins 2 and 7, with a 4.7µF or greater ceramic
capacitor.
GND (Pin 2): N/C. Ground this pin.
V
(Pin 6): Feedback Pin. Receives the feedback voltage
FB
SW (Pin 3): Switch Node Connection to Inductor. This pin
connectstothedrainsoftheinternalmainandsynchronous
power MOSFET switches.
from an external resistive divider across the output.
GND (Pin 7): Exposed Pad. The Exposed Pad is ground. It
must be soldered to PCB ground to provide both electrical
contact and optimum thermal performance.
MODE (Pin 4): Mode Select Input. To select pulse-skip-
ping mode, force this pin above 1.1V. Forcing this pin
below 0.3V selects Burst Mode operation. Do not leave
MODE floating.
U
U W
FU CTIO AL DIAGRA
MODE
4
SLOPE
COMP
0.65V
OSCILLATOR
OSC
V
IN
1
–
+
V
FB
EN
–
+
6
SLEEP
+
–
5Ω
0.611V
+
–
0.4V
I
COMP
EA
BURST
Q
Q
S
SOFT-
START
R
SWITCHING
LOGIC
AND
RS LATCH
V
ANTI-
SHOOT-
THRU
IN
BLANKING
CIRCUIT
SW
3
2
RUN
5
+
OV
REFERENCE
OVDET
0.671
–
+
–
SHUTDOWN
I
RCMP
GND
GND
7
3549 FD
3549f
7
LTC3549
U
OPERATIO
Main Control Loop
state, the load current is being supplied solely from the
output capacitor. As the output voltage droops, the EA
amplifier’soutputrisesabovethesleepthresholdsignaling
the BURST comparator to trip and turn the top MOSFET
on. This process repeats at a rate that is dependent on
the load demand.
The LTC3549 uses a constant-frequency, current mode
step-down architecture. Both the main (P-channel
MOSFET)andsynchronous(N-channelMOSFET)switches
are internal. During normal operation, the internal top
power MOSFET is turned on each cycle when the oscil-
lator sets the RS latch, and turned off when the current
Short-Circuit Protection
comparator, I
, resets the RS latch. The peak inductor
COMP
COMP
current at which I
WhentheoutputisshortedtogroundtheLTC3549limitsthe
synchronousswitchcurrentto0.45A.Ifthislimitisexceeded,
the top power MOSFET is inhibited from turning on until
the current in the synchronous switch falls below 0.45A.
resets the RS latch is controlled by
the output of error amplifier EA. The V pin, described in
FB
the Pin Functions section, allows EA to receive an output
feedback voltage from an external resistive divider. When
the load current increases, it causes a slight decrease in
the feedback voltage relative to the 0.611V reference,
which in turn, causes the EA amplifier’s output voltage to
increase until the average inductor current matches the
new load current. While the top MOSFET is off, the bottom
MOSFETisturnedonuntileithertheinductorcurrentstarts
toreverse,asindicatedbythecurrentreversalcomparator
Dropout Operation
Astheinputsupplyvoltagedecreasestoavalueapproach-
ing the output voltage, the duty cycle increases toward the
maximumon-time.Furtherreductionofthesupplyvoltage
forcesthemainswitchtoremainonformorethanonecycle
until it reaches 100% duty cycle. The output voltage will
then be determined by the input voltage minus the voltage
drop across the P-channel MOSFET and the inductor.
I , or the beginning of the next clock cycle.
RCMP
Comparator OVDET guards against transient overshoots
>10% by turning the main switch off and keeping it off
until the transient has ended.
Another important detail to remember is that at low input
supply voltages, the R
of the P-channel switch
DS(ON)
increases (see Typical Performance Characteristics).
Therefore, the user should calculate the power dissipation
when the LTC3549 is used at 100% duty cycle with low
input voltage (see Thermal Considerations in the Applica-
tions Information section).
Burst Mode Operation
The LTC3549 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
connect the MODE pin to GND. To disable Burst Mode
operationandenablePWMpulse-skippingmode, connect
Slope Compensation
the MODE pin to V or drive it with a logic high (V
>
IN
MODE
Slope compensation provides stability in constant-fre-
quency architectures by preventing subharmonic oscil-
lations at high duty cycles. It is accomplished internally
by adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%.
1.1V). In this mode, the efficiency is lower at light loads,
but becomes comparable to Burst Mode operation when
the output load exceeds 50mA. The advantage of pulse-
skipping mode is lower output ripple and less interference
to audio circuitry. When the converter is in Burst Mode
operation, the minimum peak current of the inductor is
settoapproximately100mAregardlessoftheoutputload.
Each burst event can last from a few cycles at light loads
to almost continuously cycling with short sleep intervals
at moderate loads. In between these burst events, the
power MOSFETs and any unneeded circuitry are turned
off, reducing the quiescent current to 50µA. In this sleep
Internal Soft-Start
At start-up when the RUN pin is brought high, the internal
referenceislinearlyrampedfrom0Vto0.611Vin1ms.The
regulated feedback voltage will follow this ramp, resulting
in the output voltage ramping from 0% to 100% in 1ms.
The average current in the inductor during soft-start will
3549f
8
LTC3549
OPERATION
be defined by the combination of the current needed to
charge the output capacitance and the current provided
to the load as the output voltage ramps up. The start-up
waveform, shown in the Typical Performance Character-
istics, shows the output voltage start-up from 0V to 1.2V
with a 1kΩ load and V = 3.6V.
IN
U
W U U
APPLICATIO S I FOR ATIO
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar electrical characteristics. The choice of which
style inductor to use often depends more on the price vs
sizerequirementsandanyradiatedfield/EMIrequirements
than on what the LTC3549 requires to operate. Table 1
shows some typical surface mount inductors that work
well in LTC3549 applications.
The basic LTC3549 application circuit is shown on the first
page of this data sheet. External component selection is
drivenbytheloadrequirementandbeginswiththeselection
of L followed by C and C
.
IN
OUT
Inductor Selection
For most applications, the value of the inductor will fall
in the range of 1µH to 10µH. Its value is chosen based
on the desired ripple current. Large value inductors
lower ripple current and small value inductors result in
Table 1. Representative Surface Mount Inductors
MAX DC
higher ripple currents. Higher V or V
also increases
IN
OUT
MANU-
VALUE CURRENT
HEIGHT
(mm)
the ripple current as shown in Equation 1. A reasonable
FACTURER
PART NUMBER
(µH)
(A)
DCR
starting point for setting ripple current is ΔI = 100mA
(40% of 250mA).
Taiyo
Yuden
LB2016T2R2M
LB2012T2R2M
LB2016T3R3M
LB2016T4R7M
2.2
2.2
3.3
4.7
315
240
280
210
0.13
0.23
0.2
1.6
1.25
1.6
L
0.25
1.6
⎛
⎜
⎝
⎞
⎟
⎠
VOUT
f •L
VOUT
VIN
∆IL =
1–
Panasonic
Murata
TDK
ELT5KT4R7M
4.7
4.7
950
450
0.2
0.2
1.2
2
(1)
LQH32CN4R7M34
The DC current rating of the inductor should be at least
equal to the maximum load current plus half the ripple
current to prevent core saturation. Thus, a 300mA rated
inductor should be enough for most applications (250mA
+ 50mA). For better efficiency, choose a low DC resistance
inductor. The inductor value also has an effect on Burst
Modeoperation.Thetransitiontolowcurrentoperationbe-
gins when the inductor current peaks fall to approximately
VLF3012AT2R2M1R0 2.2
VLF3012AT3R3MR87 3.3
VLF3012AT4R7MR74 4.7
VLF3010AT2R2M1R0 2.2
VLF3010AT3R3MR87 3.3
VLF3010AT4R7MR70 4.7
1
0.088
0.11
0.16
0.10
0.15
0.24
1.2
1.2
1.2
1.0
1.0
1.0
0.87
0.74
1
0.87
0.74
C and C
IN
Selection
OUT
Incontinuousmode, thesourcecurrentofthetopMOSFET
100mA. Lower inductor values (higher ΔI ) will cause this
L
is a square wave of duty cycle V /V . To prevent large
OUT IN
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
voltage transients, a low ESR input capacitor sized for the
maximumRMScurrentmustbeused. ThemaximumRMS
capacitor current is given by:
1/2
]
V
V – V
OUT
(
)
[
OUT IN
CIN RequiredIRMS ≅ IOUT(MAX)
Inductor Core Selection
V
IN
Different core materials and shapes will change the
size/current and price/current relationship of an induc-
tor. Toroid or shielded pot cores in ferrite or permalloy
This formula has a maximum at V = 2V , where
RMS OUT
monly used for design because even significant devia-
IN
OUT
I
= I /2. This simple worst-case condition is com-
3549f
9
LTC3549
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APPLICATIO S I FOR ATIO
tions do not offer much relief. Note that the capacitor
manufacturer’s ripple current ratings are often based
on 2000 hours of life. This makes it advisable to further
derate the capacitor, or choose a capacitor rated at a
higher temperature than required. Always consult the
manufacturer if there is any question. The selection of
value, lower cost ceramic capacitors are now available in
smaller case sizes. Their high ripple current, high voltage
ratingandlowESRmakethemidealforswitchingregulator
applications.BecausetheLTC3549’scontrolloopdoesnot
dependontheoutputcapacitor’sESRforstableoperation,
ceramic capacitors can be used to achieve very low output
ripple and small circuit size.
C
is driven by the required effective series resistance
OUT
(ESR). Typically, once the ESR requirement for C
has
OUT
However, care must be taken when these capacitors are
usedattheinputandtheoutput.Whenaceramiccapacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
been met, the RMS current rating generally far exceeds
the I requirement. The output ripple ΔV
RIPPLE(P-P)
OUT
is determined by:
⎛
⎝
1
⎞
induce ringing at the input, V . At best, this ringing can
IN
∆VOUT = ∆I ESR +
⎜
⎟
⎠
L
8 • f •COUT
couple to the output and be mistaken as loop instability. At
worst, a sudden inrush of current through the long wires
where f = operating frequency, C
= output capacitance
OUT
can potentially cause a voltage spike at V , large enough
IN
and ΔI = ripple current in the inductor. For a fixed output
L
to damage the part.
voltage, the output ripple is highest at maximum input
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
voltage since ΔI increases with input voltage. Aluminum
L
electrolytic and dry tantalum capacitors are both available
in surface mount configurations. In the case of tantalum,
it is critical that the capacitors are surge tested for use
in switching power supplies. An excellent choice is the
AVX TPS series of surface mount tantalum. These are
specially constructed and tested for low ESR so they give
the lowest ESR for a given volume. Other capacitor types
include Sanyo POSCAP, Kemet T510 and T495 series, and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
R1
R2
⎛
⎞
VOUT = 0.611V 1+
⎜
⎝
⎟
⎠
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 1
Using Ceramic Input and Output Capacitors
The LTC3549 typically will require an output capacitor
in the 4.7µF to 10µF range for optimum stability. Higher
Table 2 gives 1% resistor values for selected output
voltages.
V
OUT
Table 2. Resistor Values for Selected Output Voltages
V
R1
R2
OUT
R1
LTC3549
0.85V
1.2V
1.5V
1.8V
53.6k
133k
200k
267k
137k
137k
137k
137k
V
FB
R2
GND
3549 F01
Figure 1. Setting the LTC3549 Output Voltage
3549f
10
LTC3549
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APPLICATIO S I FOR ATIO
Efficiency Considerations
hightolowtohighagain, apacketofcharge, dQ, moves
fromV toground.TheresultingdQ/dtisthecurrentout
IN
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
of V that is typically larger than the DC bias current. In
IN
continuous mode, I
= f(Q + Q ) where Q and
GATECHG
T B T
Q are the gate charges of the internal top and bottom
B
switches. Both the DC bias and gate charge losses are
proportional to V and thus their effects will be more
IN
Efficiency = 100% – (L1 + L2 + L3 + ...)
pronounced at higher supply voltages.
2
2. I R losses are calculated from the resistances of the
where L1, L2, etc. are the individual losses as a percent-
age of input power.
internal switches, R , and external inductor R . In
SW
L
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC3549 circuits: V quiescent current and
IN
2
I R losses. The V quiescent current loss dominates
IN
top and bottom MOSFET R
(DC) as follows:
and the duty cycle
DS(ON)
the efficiency loss at very low load currents whereas the
2
I R loss dominates the efficiency loss at medium to high
R
= (R
)(DC) + (R
DS(ON)TOP
)
DS(ON)BOT
SW
(1 – DC)
load currents. In a typical efficiency plot, the efficiency
curve at very low load currents can be misleading since
the actual power lost is of no consequence, as illustrated
in Figure 2.
TheR
forboththetopandbottomMOSFETscanbe
DS(ON)
obtainedfromtheTypicalPerformanceCharacteristics.
2
Thus, to obtain I R losses, simply add R to R and
SW
L
1.TheV quiescentcurrentisduetotwocomponents:the
IN
multiply the result by the square of the average output
current.
DCbiascurrentasgivenintheElectricalCharacteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
fromswitchingthegatecapacitanceoftheinternalpower
MOSFET switches. Each time the gate is switched from
Other losses including C and C
ESR dissipative los-
IN
OUT
ses and inductor core losses generally account for less
than 2% total additional loss.
1.0000
V
IN
BURST
2.5V
V
PULSE SKIP
2.5V
V
= 1.8V
OUT
IN
3.6V
3.6V
4.2V
4.2V
0.1000
0.0100
0.0010
0.0001
0.1
1
10
100
1000
LOAD CURRENT (mA)
3549 F02
Figure 2. Power Loss vs Load Current
3549f
11
LTC3549
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APPLICATIO S I FOR ATIO
Thermal Considerations
Checking Transient Response
InmostapplicationstheLTC3549doesnotdissipatemuch
heatduetoitshighefficiency.But,inapplicationswherethe
LTC3549 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperatureofthepart.Ifthejunctiontemperaturereaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
immediately shifts by an amount
OUT
equal to (ΔI
• ESR), where ESR is the effective series
LOAD
resistance of C . ΔI
also begins to charge or dis-
OUT
LOAD
charge C , which generates a feedback error signal. The
OUT
regulator loop then acts to return V
value. During this recovery time V
to its steady state
can be monitored
OUT
OUT
To avoid the LTC3549 from exceeding the maximum
junction temperature, the user will need to do a thermal
analysis. The goal of the thermal analysis is to determine
whether the operating conditions exceed the maximum
junction temperature of the part. The temperature rise is
given by:
for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching
in loads with large (> 1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in paral-
T = (P )(θ )
R
D
JA
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
where P is the power dissipated by the regulator and θ
D
JA
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately (25
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T , is given by:
J
• C
). Thus, a 10µF capacitor charging to 3.3V would
LOAD
T = T + T
R
J
A
require a 250µs rise time, limiting the charging current
to about 130mA.
where T is the ambient temperature.
A
Asanexample,considertheLTC3549indropoutataninput
voltage of 1.6V, a load current of 250mA and an ambient
temperature of 75°C. In the Switch Resistance graph
shown in the Typical Performance Characteristics, the
R
of the P-channel switch at 75°C is approximately
DS(ON)
0.8Ω. Therefore, power dissipated by the part is:
2
P = I
D
• R
= 50mW
DS(ON)
LOAD
For the DCB6 package, the θ is 64°C/W. Thus, the junc-
JA
tion temperature of the regulator is:
T = 75°C + (0.05)(64) = 78.2°C
J
which is well below the maximum junction temperature
of 125°C.
Notethatathighersupplyvoltages,thejunctiontemperature
is lower due to reduced switch resistance (R
).
DS(ON)
3549f
12
LTC3549
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APPLICATIO S I FOR ATIO
signals V should be routed away from noisy compo-
nents and traces, such as the SW line (Pin 3), and its
trace should be minimized.
Board Layout Considerations
FB
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3549. These items are also illustrated graphically
in the layout diagram of Figure 3. Check the following in
your layout.
4. Keep sensitive components away from the SW pins.
The input capacitor C and the resistors R1 and R2
IN
should be routed away from the SW traces and the
inductors.
1. Does the capacitor C connect to the power V (Pin 1)
IN
IN
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point. They should not share the high current path of
andGND(Pins2,7)ascloseaspossible?Thiscapacitor
provides the AC current to the internal power MOSFETs
and their drivers.
2. Are the C
and L1 closely connected? The (–) plate of
returns current to GND and the (–) plate of C .
OUT
C or C
.
IN
OUT
C
OUT
IN
6. Floodallunusedareasonalllayerswithcopper.Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C and a ground sense line
OUT
terminated near GND (Exposed Pad). The feedback
to V or G .
IN
ND
Figure 3a. Buck Regulator Top Layer
Figure 3b. Buck Regulator Bottom Layer
3549f
13
LTC3549
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APPLICATIO S I FOR ATIO
Design Example
Substituting V
= 1.5V, V = 3.1V, ΔI = 100mA and
IN L
OUT
f = 2.25MHz in Equation 3 gives:
As a design example, assume the LTC3549 is used in a
2-alkalinecellbattery-poweredapplication.TheV willbe
IN
1
1.5
3.1
⎛
⎞
⎠
L =
1.5 1–
≅ 3.3µH
operating from a maximum of 3.1V down to about 1.8V.
The load current requirement is a maximum of 250mA
but most of the time it will be in standby mode, requiring
only 2mA. Efficiency at both low and high load currents
is important. Output voltage is 1.5V. With this information
we can calculate L using Equation 3:
⎜
⎝
⎟
2.25MHz • 100mA
For best efficiency choose a 350mA or greater inductor
with less than 0.3Ω series resistance. C will require an
IN
RMS current rating of at least 0.125A ≅ I
/2 at
LOAD(MAX)
temperature.
For the feedback resistors, choose R2 = 137k. Then, from
Equation3,R1is200k.Figure4showsthecompletecircuit
along with its efficiency curve.
⎛
⎜
⎝
⎞
⎟
⎠
VOUT
f • ∆I
VOUT
V
L =
1–
(3)
L1
3.3µH*
V
IN
V
OUT
RUN
SW
1.8V TO
3.1V
1.5V
C
CL
22pF
IN
C
4.7µF
OUT
LTC3549
4.7µF
CERAMIC
CERAMIC
V
IN
R1
200k
V
FB
MODE
GND
R2
137k
*TDK VLF3012AT-3R3MR87
3549 F04a
Figure 4a. High Efficiency Step-Down Regulator
100
90
80
70
60
50
40
30
20
10
0
V
= 1.8
IN
V
OUT
100mV/DIV
V
= 3.1
IN
AC COUPLED
V
= 2.5
IN
I
LOAD
200mA/DIV
I
L
200mA/DIV
3549 F04c
20µs/DIV
= 100mA to 250mA
V
V
= 2.5V
OUT
LOAD
IN
= 1.5V
I
0.1
1
10
100
1000
LOAD CURRENT (mA)
3549 F04b
Figure 4b. Burst Mode Efficiency, V
= 1.5V
Figure 4c. Load Step Response
OUT
3549f
14
LTC3549
U
PACKAGE DESCRIPTIO
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715)
0.70 0.05
1.65 0.05
3.55 0.05
(2 SIDES)
2.15 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
1.35 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
2.00 0.10
(2 SIDES)
0.40 0.10
R = 0.05
TYP
4
6
3.00 0.10 1.65 0.10
(2 SIDES)
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
(DCB6) DFN 0405
3
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
1.35 0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3549f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3549
U
TYPICAL APPLICATIO
L1, 4.7µH*
V
IN
V
OUT
RUN
SW
2.5V TO
4.2V
1.8V
CL, 22pF
C
IN
C
OUT
LTC3549
4.7µF
4.7µF
CERAMIC
V
IN
CERAMIC
R1, 267k
V
FB
MODE
GND
R2
137k
*TDK VLF3012AT-4R7MR74
3549 TA03a
Efficiency vs Load Current
Load Step Response
100
90
80
70
60
50
40
30
20
10
0
V
= 2.5V
IN
V
OUT
V
= 3.6V
IN
100mV/DIV
AC COUPLED
V
= 4.2V
IN
I
LOAD
200mA/DIV
I
L
200mA/DIV
3549 TA03c
20µs/DIV
V
V
= 3.6V
OUT
LOAD
IN
V
= 1.8V
1
OUT
= 1.8V
I
= 100mA to 250mA
0.1
10
100
1000
LOAD CURRENT (mA)
3549 TA03b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1878
600mA (I ), 550kHz, Synchronous
96% Efficiency, V : 2.7V to 6V, V
= 0.8V, I = 10µA, I < 1µA,
OUT(MIN) Q SD
OUT
IN
Step-Down DC/DC Converter
MS8 Package
LTC1879
1.20A (I ), 550kHz, Synchronous
95% Efficiency, V : 2.7V to 10V, V
= 0.8V, I = 15µA, I < 1µA,
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IN
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™
LT3020
100mA, Low Voltage VLDO
V : 0.9V to 10V, V
= 0.20V, Dropout Voltage = 0.15V, I = 120µA,
IN
OUT(MIN) Q
I
< 3µA, V
= ADJ, DFN/MS8 Packages
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OUT
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100mA, Low Voltage VLDO
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OUT(MIN) Q
IN
I
< 1µA, V
= ADJ, DFN Package
SD
OUT
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600mA (I ), 1.4MHz, Synchronous
96% Efficiency, V : 2.7V to 6V, V
= 0.8V, I = 10µA, I < 1µA,
OUT(MIN) Q SD
OUT
IN
Step-Down DC/DC Converter
MS8 Package
LTC3405/LTC3405A
LTC3406/LTC3406B
LTC3407/LTC3407-2
LTC3409
300mA (I ), 1.5MHz, Synchronous
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 20µA, I < 1µA,
Q SD
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
™
Step-Down DC/DC Converter
ThinSOT Package
600mA (I ), 1.5MHz, Synchronous
96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 20µA, I < 1µA,
Q SD
OUT
IN
Step-Down DC/DC Converter
ThinSOT Package
Dual, 800mA (I ), 2.25MHz, Synchronous 95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 40µA, I < 1µA,
Q SD
OUT
IN
Step-Down DC/DC Converter
10-Lead MSE Package
600mA, 2.6MHz Low V , Synchronous
95% Efficiency, V : 1.6V to 5.5V, V
= 0.6V, I = 65µA, I < 1µA,
Q SD
IN
IN
Step-Down DC/DC Converter
DFN Package
LTC3410/LTC3410B
LTC3411
300mA, 2.25MHz, Synchronous Step-Down 96% Efficiency, V : 2.5V to 5.5V, V
DC/DC Converter
= 0.8V, I = 26µA/200µA, I < 1µA,
Q SD
IN
SC70 Package
1.25A (I ), 4MHz, Synchronous
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60µA, I < 1µA,
Q SD
OUT
IN
Step-Down DC/DC Converter
10-Lead MS Package
VLDO and ThinSOT are trademarks of Linear Technology Corporation.
3549f
LT 0706 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
© LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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