LTC3565IMSE-TRPBF [Linear]
1.25A, 4MHz, Synchronous Step-Down DC/DC Converter; 1.25A ，为4MHz ，同步降压型DC / DC转换器
| 型号： | LTC3565IMSE-TRPBF |
| 厂家： | 
Linear |
| 描述： | 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter |
| 文件： | 总20页 (文件大小：594K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3565
1.25A, 4MHz, Synchronous
Step-Down DC/DC Converter
FEATURES
DESCRIPTION
The LTC®3565 is a constant frequency, synchronous
step-down DC/DC converter. Intended for medium power
applications, it operates from a 2.5V to 5.5V input voltage
range and has a user configurable operating frequency
up to 4MHz, allowing the use of tiny, low cost capacitors
and inductors 1mm or less in height. The output voltage is
adjustablefrom0.6Vto5.5V. Internalsynchronouspower
switches provide high efficiency. The LTC3565’s current
mode architecture and external compensation allow the
transient response to be optimized over a wide range of
loads and output capacitors.
■
High Efficiency: Up to 95%
IN
■
V Range: 2.5V to 5.5V
■
High Frequency Operation: Up to 4MHz
■
Selectable Low Ripple (Typical 25mV
)
p-p
Burst Mode® Operation: I = 40μA
Q
■
■
■
■
Stable with Ceramic Capacitors
Uses Tiny Capacitors and Inductor
Low R
Internal Switches: 0.15Ω
DS(ON)
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
Low Dropout Operation: 100% Duty Cycle
■
■
■
■
■
■
■
The LTC3565 can be configured for automatic power
saving Burst Mode operation (I = 40μA) to reduce gate
charge losses when the load current drops below the level
required for continuous operation. For reduced noise and
RF interference, the SYNC/MODE pin can be configured to
skip pulses or provide forced continuous operation.
Low Shutdown Current: I ≤ 1μA
Q
Q
Output Voltages from 0.6V to 5V
Synchronizable to External Clock
Supports Pre-Biased Outputs
Small 10-Lead (3mm × 3mm) DFN or MSOP Package
To further maximize battery life, the P-channel MOSFET
is turned on continuously in dropout (100% duty cycle).
In shutdown, the device draws <1μA.
, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by
U.S. Patents, including 5481178, 6580258, 6498466, 6611131.
APPLICATIONS
■
Notebook Computers
■
Digital Cameras
■
Cellular Phones
■
Handheld Instruments
■
Board Mounted Power Supplies
TYPICAL APPLICATION
Efficiency and Power Loss vs Output Current
Step-Down 2.5V/1.25A Regulator
100
90
80
70
60
50
40
30
20
10
0
1
V
IN
2.5V TO 5.5V
22μF
0.1
SV PV
IN
IN
SYNC/MODE
RUN
2.2μH
V
OUT
0.01
0.001
SW
PGOOD
2.5V
LTC3565
1.25A
ITH
RT
22μF
22pF
12.1k
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
V
FB
931k
294k
GND
680pF
0.0001
10000
191k
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
3565 TA01a
3565 TA01b
3565f
1
LTC3565
ABSOLUTE MAXIMUM RATINGS (Note 1)
PV , SV Voltages ..................................... –0.3V to 6V
Operating Junction Temperature Range
IN
IN
V , ITH, RT Voltages ....................–0.3V to (V + 0.3V)
(Notes 2, 5, 8)........................................ –40°C to 125°C
Storage Temperature Range................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
FB
IN
SYNC/MODE, PGOOD Voltage .......–0.3V to (V + 0.3V)
IN
SW Voltage (DC) ...........................–0.3V to (V + 0.3V)
IN
RUN Voltage ............................................... –0.3V to 6V
PIN CONFIGURATION
TOP VIEW
TOP VIEW
RT
RUN
1
2
3
4
5
10 ITH
RT
RUN
1
2
3
4
5
10 ITH
9
8
7
6
V
FB
9
8
7
6
V
FB
11
SYNC/MODE
SW
PGOOD
11
SYNC/MODE
SW
PGOOD
SV
IN
PV
IN
SV
PV
IN
IN
GND
GND
MSE PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
T
= 125°C, θ = 40°C/W, θ = 10°C/W
JMAX
JA JC
10-LEAD (3mm × 3mm) PLASTIC DFN
= 125°C, θ = 43°C/W, θ = 7.5°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
T
JMAX
JA JC
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3565EDD#PBF
LTC3565IDD#PBF
LTC3565EMSE#PBF
LTC3565IMSE#PBF
TAPE AND REEL
PART MARKING*
LTDNR
PACKAGE DESCRIPTION
10-Lead (3mm × 3mm) Plastic DFN
TEMPERATURE RANGE
–40°C to 125°C
LTC3565EDD#TRPBF
LTC3565IDD#TRPBF
LTC3565EMSE#TRPBF
LTC3565IMSE#TRPBF
LTDNR
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LTDVJ
LTDVJ
10-Lead Plastic MSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, RT = 125k unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Operating Voltage Range
2.5
5.5
V
IN
I
Feedback Pin Input Current
Feedback Voltage
(Note 3)
(Note 3)
50
0.612
0.2
nA
V
FB
●
●
V
0.588
0.6
0.04
0.02
300
FB
ΔV
ΔV
Reference Voltage Line Regulation
Output Voltage Load Regulation
Error Amplifier Transconductance
V
= 2.5V to 5V
IN
%/V
%
LINEREG
ITH = 0.55V to 0.9V
0.2
LOADREG
g
ITH Pin Load = 5μA (Note 3)
μS
m(EA)
3565f
2
LTC3565
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, RT = 125k unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Input DC Supply Current (Note 4)
Active Mode
S
V
V
V
= 3.6V, V = 0.55V
330
40
0.1
450
60
1
μA
μA
μA
SYNC/MODE
SYNC/MODE
RUN
FB
Sleep Mode
= 3.6V, V = 0.8V
FB
Shutdown
= 0V
f
Oscillator Frequency
RT = 125k
(Note 7)
1.3
1.5
1.7
4
MHz
MHz
OSC
f
I
Synchronization Frequency
Peak Switch Current Limit
Top Switch On-Resistance
(Note 7)
0.4
1.5
4
MHz
SYNC
LIM
V
= 0.5V
2.1
2.5
0.2
A
FB
R
MSE Package
DD Package (Note 6)
0.15
0.15
Ω
Ω
DS(ON)
Bottom Switch On-Resistance
MSE Package
DD Package (Note 6)
0.13
0.13
0.18
Ω
Ω
I
Switch Leakage Current
RUN Threshold
V
= 5V, V
= 0V, V = 0V
0.01
1
1.5
1
μA
SW(LKG)
IN
RUN
FB
●
●
V
0.3
0.8
V
RUN
RUN
I
RUN Leakage Current
Undervoltage Lockout Threshold
Power Good Threshold
0.01
1.9
μA
V
V
V
Ramping Down
2.2
UVLO
IN
PGOOD
V
V
Ramping Up from 0.45V to 0.6V
Ramping Down from 0.69V to 0.6V
–7
7
%
%
FB
FB
R
Power Good Pull-Down On-Resistance
15
20
Ω
PGOOD
PGOOD Blanking
V
V
Step from 0V to 0.6V
Step from 0.6V to 0V
40
105
μs
μs
FB
FB
V
Pulse Skip
Force Continuous
Burst
0.63
V
V
V
SYNC-MODE
1.1
– 0.75
0.6
V – 1.05
IN
V
IN
t
10% to 90% of Regulation
0.9
1.2
ms
SOFT-START
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: T is calculated from the ambient T and power dissipation P
according to the following formulas:
J
A
D
LTC3565EDD: T = T + (P • 43°C/W)
J
A
D
LTC3565EMS: T = T + (P • 120°C/W)
J
A
D
Note 2: The LTC3565E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3565I is guaranteed over the full –40°C to 125°C operating junction
temperature range. High junction temperatures degrade operating lifetimes.
Operating lifetime is derated at junction temperatures greater than 125°C.
Note 6: Switch on-resistance is guaranteed by correlation to wafer level
measurements and assured by design characterization and correlation with
statistical process controls.
Note 7: 4MHz operation is guaranteed by design but not production tested
and is subject to duty cycle limitations (see Applications Information).
Note 8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: The LTC3565 is tested in a feedback loop which servos V to the
FB
midpoint for the error amplifier (V = 0.7V).
ITH
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
3565f
3
LTC3565
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.6V, fO = 1MHz, unless
otherwise noted.
Efficiency vs Input Voltage
Efficiency vs Output Current
Efficiency vs Output Current
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
I
= 100mA
I
= 10mA
OUT
OUT
I
= 1.25A
OUT
I
= 1mA
OUT
I
= 0.1mA
5.0
OUT
V
V
V
= 2.7V
= 3.6V
= 4.2V
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
20
10
0
IN
IN
IN
V
= 1.8V
OUT
V
OUT
= 1.8V
1
V
OUT
= 1.5V
1
4.5
INPUT VOLTAGE(V)
5.5
2.5
3.0
3.5
4.0
0.1
10
100
1000
10000
0.1
10
100
1000
10000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3565 G02
3565 G03
3565 G01
Efficiency vs Output Current
Efficiency vs Frequency
Load Regulation
95
94
93
92
91
90
89
88
100
90
80
70
60
50
40
30
20
10
0
1.00
Burst Mode
OPERATION
4.7μH
0.75
0.50
PULSE
SKIP
2.2μH
Burst Mode OPERATION
0.25
FORCED CONTINUOUS
PULSE SKIP
0.00
1μH
FORCED CONTINUOUS
= 1.8V
–0.25
–0.50
V
= 1.8V
V
OUT
OUT
V
= 1.8V
1000
OUT
4
0
1
2
3
5
800
1000 1200 1400
0.1
1
10
100
10000
0
200 400 600
OUTPUT CURRENT (mA)
FREQUENCY (MHz)
OUTPUT CURRENT(mA)
3565 G04
3565 G05
3565 G06
Reference Voltage vs
Temperature
Frequency Variation vs
Temperature
Line Regulation
615
610
605
600
0.6
6
0.4
0.2
4
2
0.0
0
595
590
585
–0.2
–0.4
–0.6
–2
–4
–6
V
= 1.8V
= 400mA
OUT
I
LOAD
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
4.5
2.5
3.0
3.5
4.0
5.0
5.5
50
–50 –25
0
25
75 100 125
INPUT VOLTAGE(V)
TEMPERATURE(°C)
3565 G08
3565 G07
3565 G09
3565f
4
LTC3565
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.6V, fO = 1MHz, unless
otherwise noted.
Frequency Variation vs Input
Voltage
RDS(ON) vs Input Voltage
RDS(ON) vs Temperature
0.25
0.20
0.30
0.25
6
4
2
0.20
0.15
0.10
0.15
0.10
0
–2
–4
–6
–8
0.05
0.0
0.05
0.0
MAIN SWITCH
MAIN SWITCH
SYNCHRONOUS SWITCH
SYNCHRONOUS SWITCH
4.5
INPUT VOLTAGE (V)
2.5
3.0
3.5
4.0
5.0
5.5
50
TEMPERATURE (°C)
–50 –25
0
25
75 100 125
4.5
INPUT VOLTAGE (V)
2.5
3.0
3.5
4.0
5.0
5.5
3565 G11
3565 G12
3565 G10
Dynamic Supply Current vs Input
Voltage
Dynamic Supply Current vs
Temperature
Switch Leakage vs Input Voltage
100
10
2500
100
10
FORCED CONTINUOUS
FORCED CONTINUOUS
2000
1500
1000
MAIN SWITCH
1
1
PULSE SKIP
PULSE SKIP
Burst Mode
OPERATION
Burst Mode
OPERATION
0.1
0.1
SYNCHRONOUS SWITCH
0.01
0.001
0.01
0.001
500
0
V
I
= 1.8V
= 0A
V
LOAD
= 1.8V
OUT
LOAD
OUT
I
= 0A
2.5
3.0
3.5
4.0
4.5
5.0
5.5
4
0
1
2
3
5
6
–50 –25
0
25
50
75
100 125
INPUT VOLTAGE (V)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3565 G13
3565 G14
3565 G15
Burst Mode Operation
Pulse Skipping Mode
Switch Leakage vs Temperature
600
500
SW
2V/DIV
SW
2V/DIV
400
300
200
100
0
V
V
OUT
OUT
50mV/DIV
50mV/DIV
AC COUPLED
AC COUPLED
I
I
L
L
200mA/DIV
200mA/DIV
MAIN SWITCH
SYNCHRONOUS SWITCH
3565 G17
3565 G18
4μs/DIV
4μs/DIV
V
V
I
= 3.6V
V
V
I
= 3.6V
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 5mA
= 50mA
50
–50 –25
0
25
75 100 125
LOAD
LOAD
TEMPERATURE (°C)
3565 G16
3565f
5
LTC3565
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.6V, fO = 1MHz, unless
Start-Up from Shutdown
otherwise noted.
Forced Continuous Mode
Start-Up from Shutdown
RUN
2V/DIV
SW
2V/DIV
RUN
2V/DIV
V
V
OUT
OUT
V
OUT
50mV/DIV
1V/DIV
1V/DIV
AC COUPLED
I
I
L
L
I
500mA/DIV
1A/DIV
L
200mA/DIV
3565 G20
3565 G21
400μs/DIV
400μs/DIV
V
V
I
= 3.6V
V
V
I
= 3.6V
IN
OUT
IN
OUT
3565 G19
2μs/DIV
= 1.8V
= 0A
= 1.8V
V
V
LOAD
= 3.6V
= 1.25A
IN
LOAD
LOAD
= 1.8V
Burst Mode OPERATION
Burst Mode OPERATION
OUT
I
= 80mA
Start-Up from Shutdown with
a Prebiased Output (Forced
Continuous Mode)
Load Step
Load Step
V
V
V
OUT
OUT
OUT
100mV/DIV
100mV/DIV
1V/DIV
AC COUPLED
AC COUPLED
I
I
I
L
L
L
1A/DIV
1A/DIV
500mA/DIV
I
I
LOAD
1A/DIV
LOAD
1A/DIV
3565 G23
3565 G24
3565 G22
40μs/DIV
40μs/DIV
200μs/DIV
V
V
I
= 3.6V
V
V
I
= 3.6V
V
= 3.6V
IN
OUT
IN
OUT
IN
= 1.8V
= 0A to 1.25A
= 1.8V
= 50mA to 1.25A
PREBIASED V
= 3V, V
= 1.8V
OUT
OUT
I
= 0A
LOAD
LOAD
LOAD
Burst Mode OPERATION
Burst Mode OPERATION
VOUT Short to VIN (Forced
Continuous Mode)
Load Step
VOUT Short to Ground
V
OUT
V
OUT
1V/DIV
100mV/DIV
AC COUPLED
V
OUT
1V/DIV
I
L
1A/DIV
I
I
L
L
2A/DIV
500mA/DIV
I
LOAD
1A/DIV
3565 G26
3565 G27
3565 G25
40μs/DIV
40μs/DIV
40μs/DIV
V
V
I
= 3.6V
V
V
I
= 3.6V
V
V
I
= 3.6V
IN
OUT
IN
OUT
IN
OUT
= 1.8V
= 0A
= 1.8V
= 0A
= 1.8V
= 250mA to 1.25A
LOAD
LOAD
LOAD
Burst Mode OPERATION
3565f
6
LTC3565
PIN FUNCTIONS
RT (Pin 1): Timing Resistor Pin. The oscillator frequency
is programmed by connecting a resistor from this pin to
ground.
PV (Pin 6): Main Supply Pin. Must be closely decoupled
IN
to GND.
SV (Pin 7): The Signal Power Pin. All active circuitry is
IN
RUN (Pin 2): Converter Enable Pin. Forcing this pin above
1.5V enables this part, while forcing it below 0.3V causes
the device to shut down. In shutdown, the device draws
<1μA supply current. This pin must be driven; do not float.
powered from this pin. Must be closely decoupled to GND.
SV must be greater than or equal to PV .
IN
IN
PGOOD (Pin 8): The Power Good Pin. This common drain
logic output is pulled to GND when the output voltage is
not within 7% of regulation.
SYNC/MODE (Pin 3): Combination Mode Selection and
Oscillator Synchronization Pin. This pin controls the
V
(Pin 9): Receives the feedback voltage from the ex-
FB
operation of the device. When tied to SV or GND, Burst
IN
ternal resistive divider across the output. Nominal voltage
Mode operation or pulse skipping mode is selected,
for this pin is 0.6V.
respectively. If this pin is held at half of SV , the forced
IN
ITH (Pin 10): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0.4V to
1.4V.
continuous mode is selected. The oscillation frequency
can be synchronized to an external oscillator applied to
this pin. When synchronized to an external clock, pulse
skip mode is selected.
Exposed Pad (Pin 11): Ground. Must be soldered to
electrical ground on PCB.
SW (Pin 4): The Switch Node Connection to the Inductor.
This pin swings from PV to GND.
IN
GND (Pin 5): Main Power Ground Pin. Connect to the
(–) terminal of C , and (–) terminal of C .
OUT
IN
NOMINAL (V)
TYP
ABSOLUTE MAX (V)
PIN
1
NAME
RT
DESCRIPTION
MIN
–0.3
–0.3
0
MAX
MIN
–0.3
–0.3
–0.3
–0.3
MAX
Timing Resistor
Enable Pin
0.4
SV
SV
SV
PV
SV + 0.3
IN
IN
IN
IN
IN
2
RUN
SV
IN
3
SYNC/MODE Mode Select/Synchronization Pin
SV + 0.3
IN
4
SW
Switch Node
0
PV + 0.3
IN
5
GND
Main Power Ground
Main Power Supply
Signal Power Supply
Power Good Pin
0
6
PV
SV
–0.3
2.5
0
5.5
5.5
SV
–0.3
–0.3
–0.3
–0.3
–0.3
6
6
IN
IN
7
8
PGOOD
SV + 0.3
IN
IN
9
V
Output Feedback Pin
Error Amplifier Compensation
0
0.8
1.0
1.5
SV + 0.3
IN
FB
10
ITH
0
SV + 0.3
IN
3565f
7
LTC3565
BLOCK DIAGRAM
SV
GND
5
ITH
10
PV
IN
IN
7
6
0.6V
PMOS CURRENT
COMPARATOR
VOLTAGE
REFERENCE
ITH
LIMIT
BCLAMP
+
–
+
–
–
+
9
V
FB
ERROR
AMPLIFIER
V
B
BURST
COMPARATOR
+
–
0.645V
SLOPE
COMPENSATION
4
SW
OSCILLATOR
+
–
LOGIC
0.555V
+
PGOOD
8
–
NMOS
COMPARATOR
–
+
5
GND
REVERSE
COMPARATOR
2
1
3
3565 BD
RUN
RT
SYNC/MODE
3565f
8
LTC3565
OPERATION
The LTC3565 uses a constant frequency, current mode
switch from continuous operation to the selected mode
when the load current is low.
architecture. The operating frequency is determined by
the value of the R resistor or can be synchronized to an
T
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3565
automaticallyswitchesintoBurstModeoperationinwhich
the PMOS switch operates intermittently based on load
demand. By running cycles periodically, the switching
losses which are dominated by the gate charge losses
of the power MOSFETs are minimized. The main control
loop is interrupted when the output voltage reaches the
desired regulated value. The burst comparator trips when
ITH is below approximately 0.5V, shutting off the switch
and reducing the power. The output capacitor and the
inductor supply the power to the load until ITH rises above
approximately 0.5V, turning on the switch and the main
control loop which starts another cycle.
external oscillator. To suit a variety of applications, the
selectable MODE pin allows the user to trade-off noise
for efficiency.
The output voltage is set by an external divider returned
to the V pin. An error amplifier compares the divided
FB
output voltage with the reference voltage of 0.6V and ad-
justs the peak inductor current accordingly. Overvoltage
andundervoltagecomparatorswillpullthePGOODoutput
low if the output voltage is not within 7% of its regulated
value. A tripping delay of 40μs and untripping delay of
105μs ensures PGOOD will not glitch due to transient
spikes on V
.
OUT
Main Control Loop
For lower output voltage ripple at low currents, pulse
skipping mode can be used. In this mode, the LTC3565
continues to switch at a constant frequency down to
very low currents, where it will eventually begin skipping
pulses.
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle.
Currentflowsthroughthisswitchintotheinductorandthe
load, increasing until the peak inductor current reaches
the limit set by the voltage on the ITH pin. Then, the top
switch is turned off, the bottom switch is turned on, and
the energy stored in the inductor forces the current to
flow through the bottom switch and the inductor out into
the load until the next clock cycle.
Finally, in forced continuous mode, the inductor cur-
rent is constantly cycled which creates a fixed output
voltage ripple at all output current levels. This feature is
desirable in telecommunications since the noise is at a
constant frequency and is thus easy to filter out. Another
advantage of this mode is that the regulator is capable
of both sourcing current into a load and sinking current
from the output.
The peak inductor current is controlled by the voltage
on the ITH pin, which is the output of the error amplifier.
The output is developed by the error amplifier comparing
the feedback voltage, V , to the 0.6V reference voltage.
FB
When the load current increases, the output voltage and
Dropout Operation
V
decrease slightly. This decrease in V causes the er-
FB
FB
Whentheinputsupplyvoltagedecreasestowardtheoutput
voltage, the duty cycle increases to 100% which is the
dropout condition. In dropout, the PMOS switch is turned
on continuously with the output voltage being equal to the
input voltage minus the voltage drops across the internal
P-channel MOSFET and the inductor.
ror amplifier to increase the ITH voltage until the average
inductor current matches the new load current.
The main control loop is shut down by grounding the RUN
pin, resetting the internal soft-start. Re-enabling the main
control loop by pulling RUN high activates the internal
soft-start, which slowly ramps the output voltage over
approximately 0.9ms until it reaches regulation.
Low Supply Operation
TheLTC3565incorporatesanundervoltagelockoutcircuit
which shuts down the part when the input voltage drops
below about 1.9V to prevent unstable operation.
Low Current Operation
Three modes are available to control the operation of the
LTC3565 at low currents. All three modes automatically
3565f
9
LTC3565
APPLICATIONS INFORMATION
A general LTC3565 application circuit is shown in
Figure 4.Externalcomponentselectionisdrivenbytheload
requirement, and begins with the selection of the inductor
inductances, but results in higher output ripple voltage,
greater core loss and lower output capability.
A reasonable starting point for setting ripple current is
L1. Once L1 is chosen, C and C
can be selected.
IN
OUT
ΔI = 0.4•I
,whereI
is1.25A.Thelargest
L
OUT(MAX)
OUT(MAX)
ripplecurrentΔI occursatthemaximuminputvoltage.To
L
Operating Frequency
guarantee that the ripple current stays below a specified
maximum, theinductorvalueshouldbechosenaccording
to the following equation:
Selectionoftheoperatingfrequencyisatrade-offbetween
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
ꢂ
ꢅ
VOUT
fO • ꢀIL
VOUT
VIN(MAX)
L =
• 1ꢁ
ꢄ
ꢇ
ꢃ
ꢆ
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
Theoperatingfrequency,f ,oftheLTC3565isdetermined
O
by an external resistor that is connected between the RT
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timingcapacitorwithintheoscillatorandcanbecalculated
by using the following equation:
6
–1.2674
R = 1.21 × 10 (f )
(kΩ)
T
O
5000
T
= 25°C
A
where R is in kΩ and f is in kHz or can be selected
T
O
4500
4000
3500
3000
2500
2000
1500
1000
500
using Figure 1.
The maximum usable operating frequency is limited by
the minimum on-time and the duty cycle. This can be
calculated as:
VOUT
fO(MAX) ≈ 6.67 •
(MHz)
V
IN(MAX)
0
The minimum frequency is limited by leakage and noise
0
100
200
300
400
500
600
coupling due to the large resistance of R .
R
(kΩ)
T
T
3565 F01
Inductor Selection
Figure 1. Frequency vs RT
Inductor Core Selection
The operating frequency, f , has a direct effect on the
O
inductorvalue,whichinturninfluencestheinductorripple
Different core materials and shapes will change the
size/current and price/current relationship of an induc-
tor. Toroid or shielded pot cores in ferrite or permalloy
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar electrical characteristics. The choice of which
style inductor to use often depends more on the price vs
sizerequirementsandanyradiatedfield/EMIrequirements
current, ΔI :
L
ꢂ
OUT ꢅ
V
VOUT
fO •L
ꢀIL =
• 1ꢁ
ꢄ
ꢇ
VIN
ꢃ
ꢆ
The inductor ripple current decreases with larger induc-
tanceorfrequency, andincreaseswithhigherV or V
.
IN
OUT
Accepting larger values of ΔI allows the use of lower
L
than on what the LTC3565 requires to operate. Table 1
3565f
10
LTC3565
APPLICATIONS INFORMATION
shows some typical surface mount inductors that work
diode peak current and average power dissipation so as
not to exceed the diode ratings. The main problem with
Schottkydiodesisthattheirparasiticcapacitancereduces
the efficiency, usually negating the possible benefits for
LTC3565 circuits. Another problem that a Schottky diode
can introduce is higher leakage current at high tempera-
tures, which could reduce the low current efficiency.
well in LTC3565 applications.
Table 1. Representative Surface Mount Inductors
MANU-
FACTURER PART NUMBER
MAXDC
VALUE CURRENT DCR HEIGHT
Toko
A914BYW-1R2M=P3:
D52LC
1.2μH 2.15A
44mΩ 2mm
A960AW-1R2M=P3:
D518LC
1.2μH
1.8A
46mΩ 1.8mm
Remember to keep lead lengths short and observe proper
grounding(seeBoardLayoutConsiderations)toavoidring-
ing and increased dissipation when using a catch diode.
DB3015C-1068AS-1R0N 1.0μH
DB3018C-1069AS-1R0N 1.0μH
DB3020C-1070AS-1R0N 1.0μH
2.1A
2.1A
2.1A
43mΩ 1.5mm
45mΩ 1.8mm
47mΩ 2mm
49mΩ 2mm
22mΩ 3mm
80mΩ 1mm
70mΩ 3mm
120mΩ 1mm
72mΩ 3mm
40mΩ 1.2mm
36mΩ 1.5mm
24mΩ 2mm
Input Capacitor (C ) Selection
IN
A914BYW-2R2M-D52LC 2.2μH 2.05A
In continuous mode, the input current of the converter is a
A915AY-2ROM-D53LC 2.0μH
3.3A
2.1A
2.3A
2.4A
2.1A
2.2A
2.2A
2.1A
square wave with a duty cycle of approximately V /V .
OUT IN
Coilcraft LPO1704-122ML
D01608C-222
1.2μH
2.2μH
2.2μH
1.0μH
1.0μH
1.2μH
1.1μH
1.0μH
1.1μH
Topreventlargevoltagetransients,alowequivalentseries
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
LP01704-222M
Sumida
CR32-1R0
CR5D11-1R0
CDRH3D14-1R2
CDRH4D18C/LD-1R1
CDRH4D28C/LD-1R0
CDRH4D28C-1R1
CDRH4D28-1R2
CDRH6D12-1R0
CDRH4D282R2
CDC5D232R2
VOUT(V − VOUT
)
IN
IRMS ≈ IMAX
V
IN
3.0A 17.5mΩ 3mm
3.8A 22mΩ 3mm
where the maximum average output current I
equals
MAX
1.2μH 2.56A 23.6mΩ 3mm
1.0μH 2.80A 37.5mΩ 1.5mm
the peak current minus half the peak-to-peak ripple cur-
rent, I ≅ I – ΔI /2.
MAX
LIM
L
2.2μH 2.04A
2.2μH 2.16A
23mΩ 3mm
30mΩ 2.5mm
27mΩ 1.8mm
29mΩ 3.2mm
32mΩ 2.8mm
24mΩ 5mm
80mΩ 1mm
This formula has a maximum at V = 2V , where
IN
OUT
I
= I /2. This simple worst case is commonly used
RMS
OUT
Taiyo
Yuden
NPO3SB1ROM
N06DB2R2M
1.0μH
2.2μH
2.2μH
2.2μH
0.9μH
2.6A
3.2A
2.9A
3.2A
1.4A
to design because even significant deviations do not offer
muchrelief. Notethatcapacitormanufacturer’sripplecur-
rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required.Severalcapacitorsmayalsobeparalleledtomeet
thesizeorheightrequirementsofthedesign.Anadditional
0.1μF to 1μF ceramic capacitor is also recommended on
N05DB2R2M
Murata
FDK
LQN6C2R2M04
MIPW3226DORGM
Catch Diode Selection
Although unnecessary in most applications, a small
improvement in efficiency can be obtained in a few ap-
plications by including the optional diode D1 shown in
Figure 2, which conducts when the synchronous switch
is off. When using Burst Mode operation or pulse skip
mode, the synchronous switch is turned off at a low
current and the remaining current will be carried by the
optional diode. It is important to adequately specify the
V for high frequency decoupling, when not using an all
IN
ceramic capacitor solution.
Output Capacitor (C ) Selection
OUT
The selection of C
is driven by the required ESR to
OUT
minimizevoltagerippleandloadsteptransients.Typically,
once the ESR requirement is satisfied, the capacitance
3565f
11
LTC3565
APPLICATIONS INFORMATION
is adequate for filtering. The output ripple (ΔV ) is
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3565 in parallel with the
main capacitors for high frequency decoupling.
OUT
determined by:
ꢂ
ꢄ
L ꢃ
ꢅ
ꢇ
ꢆ
1
ꢀVOUT ꢁ ꢀI ESR +
8fOCOUT
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now be-
coming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them
ideal for switching regulator applications. Because the
LTC3565’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
where f = operating frequency, C
= output capacitance
OUT
and ΔI = ripple current in the inductor. The output ripple
L
is highest at maximum input voltage since ΔI increases
L
with input voltage. With ΔI = 0.4 • I
, the output
L
OUT(MAX)
ripplewillbelessthan100mVatmaximumV
,aminimum
IN
C
of 10μF and f = 1MHz with:
OUT
O
ESRC
< 150mΩ
OUT
Once the ESR requirements for C
have been met, the
OUT
However, care must be taken when ceramic capacitors are
used at the input. When a ceramic capacitor is used at the
input and the power is supplied by a wall adapter through
long wires, a load step at the output can induce ringing at
RMS current rating generally far exceeds the I
RIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
currenthandlingrequirementoftheapplication.Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitors are all available in surface mount packages.
The OS-CON semiconductor dielectric capacitor avail-
able from Sanyo has the lowest ESR(size) product of any
aluminum electrolytic at a somewhat higher price. Special
polymer capacitors, such as Sanyo POSCAP, offer very
low ESR, but have a lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
density, but it has a larger ESR and it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surfacemounttantalums,availableincaseheightsranging
from2mmto4mm.Aluminumelectrolyticcapacitorshave
a significantly larger ESR, and is often used in extremely
cost-sensitive applications provided that consideration is
given to ripple current ratings and long term reliability.
Ceramic capacitors have the lowest ESR and cost but also
have the lowest capacitance density, a high voltage and
temperature coefficient and exhibit audible piezoelectric
effects.Inaddition,thehighQofceramiccapacitorsalong
withtraceinductancecanleadtosignificantringing.Other
capacitor types include the Panasonic specialty polymer
(SP) capacitors.
theinput, V . Atbest, thisringingcancoupletotheoutput
IN
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at V large enough to damage the
IN
part. Refer to Linear Technology Application Note 88 for
a detailed discussion of this potential issue.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation com-
ponents and the output capacitor value. Typically, 3 to 4
cycles are required to respond to a load step, but only in
the first cycle does the output drop linearly. The output
droop, V
, is usually about 2 to 3 times the linear
DROOP
3565f
12
LTC3565
APPLICATIONS INFORMATION
drop of the first cycle. Thus, a good place to start is with
the output capacitor value of approximately:
will ramp from zero to full scale over a time period of ap-
proximately0.9ms.ThispreventstheLTC3565fromhaving
to quickly charge the output capacitor and thus supplying
an excessive amount of instantaneous current.
ΔIOUT
COUT ≈ 2.5
fO • VDROOP
The LTC3565 can start into a back-biased output in force
continuous operation. When the output is pre-biased at
either a higher or lower value than the regulated output
voltage, theLTC3565willsinkorsourcecurrentasneeded
to bring the output back into regulation. However, during
soft-start the regulator will always start in pulse skip
mode ignoring the mode selected with the SYNC/MODE
pin. This prevents the output from discharging to below
the regulation point when soft-starting.
More capacitance may be required depending on the duty
cycle and load step requirements.
Inmostapplications,theinputcapacitorismerelyrequired
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Setting the Output Voltage
Mode Selection and Frequency Synchronization
The LTC3565 develops a 0.6V reference voltage between
the feedback pin, V , and the signal ground as shown in
FB
TheSYNC/MODEpinisamultipurposepinwhichprovides
mode selection and frequency synchronization. Connect-
Figure 4. The output voltage is set by a resistive divider
according to the following formula:
ing this pin to V enables Burst Mode operation, which
IN
provides the best low current efficiency at the cost of a
higheroutputvoltageripple. Whenthispinisconnectedto
ground,pulseskippingoperationisselectedwhichprovides
the lowest output voltage and current ripple at the cost
of low current efficiency. Applying a voltage that is half
the value of the input voltage results in forced continuous
mode, whichcreatesafixedoutputrippleandiscapableof
sinking up to 0.4A. Since the switching noise is constant
in this mode, it is also the easiest to filter out.
R2
ꢅ
R1
ꢁ
ꢂ
ꢄ
ꢆ
VOUT ꢀ 0.6V 1+
ꢃ
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce
the phase margin of the error amp loop.
To improve the frequency response, a feed-forward ca-
pacitor C may also be used. Great care should be taken
F
The LTC3565 can also be synchronized to an external
clock signal by the SYNC/MODE pin. The internal oscilla-
tor frequency should be set to 20% of the external clock
frequency to ensure adequate slope compensation, since
slopecompensationisderivedfromtheinternaloscillator.
During synchronization, the mode is set to pulse skipping
and the top switch turn on is synchronized to the falling
edge of the external clock.
to route the V line away from noise sources, such as
FB
the inductor or the SW line.
Shutdown and Soft-Start
PullingtheRUNpinhighallowsaninternalsoft-startcircuit
to slowly ramp the output voltage up until regulation.
Soft-start prevents surge currents from V by gradually
ramping the output voltage up during start-up. The output
IN
3565f
13
LTC3565
APPLICATIONS INFORMATION
mediately shif ts by an amount equal to ΔI
•ESR,where
Checking Transient Response
LOAD
ESR is the effective series resistance of C . ΔI
also
The OPTI-LOOP® compensation allows the transient re-
sponsetobeoptimizedforawiderangeofloadsandoutput
capacitors. The availability of the ITH pin not only allows
optimizationofthecontrolloopbehaviorbutalsoprovides
a DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling time at this test
point truly reflects the closed loop response. Assuming a
predominantlysecondordersystem,phasemarginand/or
damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
OUT
LOAD
begins to charge or discharge C
generating a feedback
OUT
error signal used by the regulator to return V
to its
OUT
OUT
steady-state value. During this recovery time, V
can
be monitored for overshoot or ringing that would indicate
a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capacitor
TheITHexternalcomponentsshowninthecircuitonpage1
ofthisdatasheetwillprovideanadequatestartingpointfor
most applications. The series R-C filter sets the dominant
pole-zero loop compensation. The values can be modified
slightly (from 0.5 to 2 times their suggested values) to
optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
theloopfeedbackfactorgainandphase.Anoutputcurrent
pulse of 20% to 100% of full load current having a rise
time of 1μs to 10μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop.
C can be added to improve the high frequency response,
F
as shown in Figure 2. Capacitor C provides phase lead by
F
creating a high frequency zero with R2 which improves
the phase margin.
Theoutputvoltagesettlingbehaviorisrelatedtothestability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
im-
OUT
V
IN
+
R5
R6
C6
C
IN
SV
PV
PGOOD
SW
PGOOD
IN
IN
L1
C8
V
OUT
D1
OPTIONAL
+
LTC3565
C
OUT
C5
RUN
C
F
V
FB
SYNC/MODE
ITH
R2
R1
R
RT
C
C
ITH
GND
R
C
C
T
3565 F04
Figure 2. LTC3565 General Schematic
3565f
14
LTC3565
APPLICATIONS INFORMATION
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
inputvoltageV dropstowardV ,theloadstepcapability
the losses in LTC3565 circuits: 1) LTC3565 V current,
IN
OUT
IN
2
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta or single inductor, positive buck/boost.
2) switching losses, 3) I R losses, 4) other losses.
1) The V current is the DC supply current given in the
IN
electrical characteristics which excludes MOSFET driver
andcontrolcurrents. V currentresultsinasmall(<0.1%)
IN
Insomeapplications,amoreseveretransientcanbecaused
by switching in loads with large (>1μF) input capacitors.
Thedischargedinputcapacitorsareeffectivelyputinparal-
loss that increases with V , even at no load.
IN
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
fromswitchingthegatecapacitanceofthepowerMOSFETs.
Each time a MOSFET gate is switched from low to high
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
can deliver enough current to prevent this problem, if the
switchconnectingtheloadhaslowresistanceandisdriven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates cur-
rent limiting, short-circuit protection, and soft-starting.
to low again, a packet of charge dQ moves from V to
IN
ground. The resulting dQ/dt is a current out of V that is
IN
typically much larger than the DC bias current. In continu-
ous mode, I
= f (QT + QB), where QT and QB are
GATECHG
O
the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V
IN
Efficiency Considerations
and thus their effects will be more pronounced at higher
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
supply voltages.
2
3) I R losses are calculated from the DC resistances of
the internal switches, R , and external inductor, R . In
SW
L
continuous mode, the average output current flowing
through inductor L is “chopped” between the internal top
and bottom switches. Thus, the series resistance look-
ing into the SW pin is a function of both top and bottom
%Efficiency = 100% – (L1 + L2 + L3 + ...)
MOSFET R
and the duty cycle (DC) as follows:
DS(ON)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
R
SW
= (R TOP)(DC) + (R BOT)(1 – DC)
DS(ON) DS(ON)
The R
for both the top and bottom MOSFETs can
1
DS(ON)
V
O
= 3.6V
IN
beobtainedfromtheTypicalPerformanceCharacteristics
f
= 1MHz
2
curves. Thus, to obtain I R losses:
0.1
2
I R losses = I 2(R + R )
OUT
SW
L
4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system.Theinternalbatteryandfuseresistancelossescan
0.01
0.001
V
V
= 1.2V
= 1.5V
OUT
OUT
= 1.2V-1.8V
V
OUT
0.0001
be minimized by making sure that C has adequate charge
0.1
1
10
100
1000
10000
IN
LOAD CURRENT (mA)
storageandverylowESRattheswitchingfrequency.Other
3565 F05
Hot Swap is a trademark of Linear Technology Corporation.
Figure 3. Power Loss vs Load Currrent
3565f
15
LTC3565
APPLICATIONS INFORMATION
lossesincludingdiodeconductionlossesduringdead-time
and inductor core losses, which generally account for less
than 2% total additional loss.
Remembering that the above junction temperature is
obtained from an R at 25°C, we might recalculate
DS(ON)
the junction temperature based on a higher R
since
DS(ON)
it increases with temperature. However, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
Thermal Considerations
In a majority of applications, the LTC3565 does not dis-
sipate much heat due to its high efficiency. However,
in applications where the LTC3565 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
Design Example
As a design example, consider using the LTC3565 in a
portable application with a Li-Ion battery. The battery
providesaV =2.5Vto4.2V.Theloadrequiresamaximum
IN
of 1.25A in active mode and 10mA in standby mode. The
output voltage is V
= 2.5V. Since the load still needs
OUT
power in standby, Burst Mode operation is selected for
good low load efficiency.
To avoid the LTC3565 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise
is given by:
First, calculate the timing resistor for 1MHz operation:
6
3 –1.2674
R = 1.21 • 10 (10 )
= 190.8k
Use a standard value of 191k. Next, calculate the inductor
value for about 40% ripple current at maximum V :
T
IN
ꢁ
ꢄ
T
= P • θ
D JA
2.5V
1MHz • 500mA
2.5V
4.2V
RISE
L =
• 1ꢀ
= 2μH
ꢃ
ꢆ
ꢂ
ꢅ
where P is the power dissipated by the regulator and θ
D
JA
is the thermal resistance from the junction of the die to
Choosing the closest inductor from a vendor of 2.2μH,
results in a maximum ripple current of:
the ambient temperature.
The junction temperature, T , is given by:
J
ꢂ
ꢅ
2.5V
1MHz • 2.2μH
2.5V
4.2V
ꢀIL =
• 1ꢁ
= 460mA
T = T
J
+ T
AMBIENT
ꢄ
ꢇ
RISE
ꢃ
ꢆ
As an example, consider the case when the LTC3565 is
in dropout at an input voltage of 3.3V with a load current
of 1A. From the Typical Performance Characteristics
graph of Switch Resistance, the R
P-channel switch is 0.160Ω. Therefore, power dissipated
by the part is:
For cost reasons, a ceramic capacitor will be used. C
OUT
selection is then based on load step droop instead of ESR
resistance of the
requirements. For a 5% output droop:
DS(ON)
1.25A
1MHz •(5% • 2.5V)
COUT ≈ 2.5
= 25μF
2
P = I
• R
= 160mW
D
OUT
DS(ON)
The closest standard value is 22μF. Since the output
TheMSEpackagejunction-to-ambientthermalresistance,
JA
junction temperature of the regulator operating in a 70°C
ambient temperature is approximately:
impedance of a Li-Ion battery is very low, C is typically
θ , will be in the range of about 40°C/W. Therefore, the
IN
22μF. In noisy environments, decoupling SV from PV
IN
IN
with an R6/C8 filter of 1Ω/0.1μF may help, but is typically
not needed.
T = 0.16 • 40 + 70 = 76.4°C
J
3565f
16
LTC3565
APPLICATIONS INFORMATION
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2μAwiththe0.6VfeedbackvoltagemakesR1~300k.Aclose
standard 1% resistor value is 294k then R2 is 931k.
provides the AC current to the internal power MOSFETs
and their drivers.
2. Are the C
OUT
and L1 closely connected? The (–) plate of
OUT
C
returns current to PGND and the (–) plate of C .
IN
3. The resistor divider, R1 and R2, must be connected
The compensation should be optimized for these compo-
nentsbyexaminingtheloadstepresponsebutagoodplace
to start for the LTC3565 is with a 12.1kΩ and 680pF filter.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
between the (+) plate of C
and a ground line. The
OUT
feedback signal V should be routed away from noisy
FB
components and traces, such as the SW line (Pin 4), and
its trace should be minimized.
4. Keep sensitive components away from the SW pin. The
ThePGOODpinisacommondrainoutputandrequiresapull-
up resistor. A 100k resistor is used for adequate speed.
input capacitor C , the compensation capacitor C and
IN
C
C
ITH
and all the resistors R1, R2, R , and R should be
T C
Thecircuitonpage1ofthisdatasheetshowsthecomplete
schematic for this design example.
routed away from the SW trace and the inductor L1. The
SW pin pad should be kept as small as possible.
5. A ground plane is preferred, but if not available, keep
thesignalandpowergroundssegregatedwithsmallsignal
components returning to the GND pin at one point.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3565. These items are also illustrated graphically
in the layout diagram of Figure 4. Check the following in
your layout:
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
one of the input supply rails: PV , SV or GND.
IN
IN
1. Does the capacitor CIN connect to the power VIN (Pin 6)
andpowerGND(Pin5)ascloseaspossible?Thiscapacitor
C
C
C
ITH
R1
R
10
R2
C
R
T
1
2
ITH
RT
C4
9
V
LTC3565
RUN
FB
8
PGOOD
3
4
5
SYNC/MODE
SW
L1
R5
7
6
V
OUT
SV
IN
V
IN
PV
IN
GND
C
OUT
3565 F06
C
IN
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 4. LTC3565 Layout Diagram (See Board Layout Checklist)
3565f
17
LTC3565
TYPICAL APPLICATION
General Purpose Buck Regulator Using Ceramic Capacitors
V
IN
2.5V TO
5.5V
C1
22μF
R5
100k
PGOOD
PV
IN
L1
SV
PGOOD
SW
IN
2.2μH
V
OUT
RS1
1M
1.8V/1.5V/1.2V
AT 1.25A
LTC3565
BM
PS
R2 294k
SYNC/MODE
ITH
V
FC
FB
SHDN/RT
RS2
1M
1.8V
1.5V
1.2V
C2
22μF
GND
C4 22pF
R3
12.1k
R4
191k
R1A
147k
R1B
196k
R1C
294k
C3
680pF
3565 TA02a
NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)
Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
Burst Mode
OPERATION
V
OUT
100mV/DIV
AC COUPLED
PULSE SKIP
I
L
1A/DIV
I
FORCED CONTINUOUS
LOAD
1A/DIV
3565 TA02c
V
V
O
= 3.6V
= 1.2V
= 1MHz
IN
OUT
40μs/DIV
V
V
I
= 3.6V
IN
OUT
f
= 1.2V
= 100mA TO 1.25A
0.1
1
10
100
1000
10000
LOAD
Burst Mode OPERATION
OUTPUT CURRENT (mA)
3565 TA02b
V
OUT
100mV/DIV
AC COUPLED
I
L
1A/DIV
I
LOAD
1A/DIV
3565 TA02d
40μs/DIV
V
V
= 3.6V
IN
= 1.8V
OUT
I
= 100mA TO 1.25A
LOAD
PULSE SKIPPING MODE
3565f
18
LTC3565
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
6
0.38 ± 0.10
10
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PACKAGE
OUTLINE
(DD) DFN 1103
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50
BSC
2.38 ±0.10
(2 SIDES)
2.38 ±0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD
PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev B)
BOTTOM VIEW OF
EXPOSED PAD OPTION
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
2.794 ± 0.102
(.110 ± .004)
0.889 ± 0.127
(.035 ± .005)
0.497 ± 0.076
(.0196 ± .003)
2.06 ± 0.102
(.081 ± .004)
1
10 9
8
7 6
REF
1.83 ± 0.102
(.072 ± .004)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
5.23
(.206)
MIN
4.90 ± 0.152
(.193 ± .006)
2.083 ± 0.102 3.20 – 3.45
(.082 ± .004) (.126 – .136)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
1
2
3
4
5
10
GAUGE PLANE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.50
(.0197)
BSC
MSOP (MSE) 0307 REV B
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3565f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
t ion t h a t t he in ter c onne c t ion o f i t s cir cui t s a s de s cr ib e d her ein w ill no t in fr inge on ex is t ing p a ten t r igh t s.
19
LTC3565
TYPICAL APPLICATION
1mm Height, 2MHz, Li-Ion to 1.8V Converter
V
IN
2.5V
R5
TO 4.2V
C1
100k
10μF
PV
SV
PGOOD
SW
PGOOD
C4 22pF
IN
V
OUT
1.8V
IN
L1
0.9μH
AT 1.25A
LTC3565
RUN
SYNC/MODE
ITH
C2
10μF
× 2
V
FB
R1
232k
R2
R3
13.3k
C3
GND
RT
464k
R4
80.6k
470pF
C1, C2: TAIYO YUDEN JMK107BJ106MA
L1: FDK MIPW3226DORGM
3565 TA04a
Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
V
V
OUT
OUT
100mV/DIV
AC COUPLED
100mV/DIV
AC COUPLED
I
L
I
L
1A/DIV
1A/DIV
I
I
LOAD
1A/DIV
LOAD
1A/DIV
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
3565 TA04c
3565 F04d
40μs/DIV
40μs/DIV
V
f
= 1.8V
OUT
= 2MHz
O
V
V
I
= 3.6V
V
V
I
IN
OUT
IN
OUT
= 1.8V
= 50mA TO 1.25A
0.1
1
10
100
1000
10000
LOAD
OUTPUT CURRENT (mA)
3565 TA04b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3406/LTC3406B 600mA (I ), 1.5MHz Synchronous Step-Down DC/DC Converters 96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V,
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
I = 20μA, I < 1μA, ThinSOT™
Q
SD
LTC3407A/LTC3407AB Dual 600mA/800mA (I ), 1.5MHz/2.25MHz Synchronous
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V,
= 0.8V,
= 0.8V,
OUT
IN
Step-Down DC/DC Converters
I = 40μA, I < 1μA, MS10E, DFN
Q SD
LTC3410/LTC3410B
LTC3411A
300mA (I ), 2.25MHz Synchronous Step-Down DC/DC Converters 95% Efficiency, V : 2.5V to 5.5V, V
OUT IN
I = 26μA, I < 1μA, SC70
Q
SD
1.25A (I ), 4MHz Synchronous Step-Down DC/DC Converter
96% Efficiency, V : 2.5V to 5.5V, V
IN
OUT
I = 60μA, I < 1μA, MS10, 3mm × 3mm DFN
Q
SD
LTC3412A
3A (I ), 4MHz Synchronous Step-Down DC/DC Converter
96% Efficiency, V : 2.25V to 5.5V, V
= 0.8V,
OUT(MIN)
OUT
IN
I = 62μA, I < 1μA, TSSOP16E, 4mm × 4mm QFN
Q
SD
LTC3531/LTC3531-3 200mA (I ), 1.5MHz Synchronous Buck-Boost DC/DC Converters 95% Efficiency, V : 1.8V to 5.5V, V
= 2V to 5V,
= 2.4V to
= 0.6V,
OUT
IN
OUT(MIN)
OUT(MIN)
LTC3531-3.3
LTC3532
I = 16μA, I < 1μA, ThinSOT, DFN
Q SD
500mA (I ), 2MHz Synchronous Buck-Boost DC/DC Converter
95% Efficiency, V : 2.4V to 5.5V, V
IN
OUT
5.25V, I = 35μA, I < 1μA, MS10, DFN
Q
SD
LTC3542
500mA (I ), 2.25MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, V : 2.5V to 5.5V, V
OUT IN OUT(MIN)
I = 26μA, I < 1μA, 2mm × 2mm DFN
Q
SD
LTC3544
Quad 300mA + 2× 200mA + 100mA, 2.25MHz Synchronous
Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V,
OUT(MIN)
IN
I = 70μA, I < 1μA, 3mm × 3mm QFN
Q
SD
LTC3547/LTC3547B
Dual 300mA, 2.25MHz Synchronous Step-Down DC/DC Converters 96% Efficiency, V : 2.5V to 5.5V, V
= 0.6V,
OUT(MIN)
IN
I = 40μA, I < 1μA, 2mm × 3mm DFN
Q
SD
LTC3548/LTC3548-1 Dual 400mA/800mA, (I ), 2.25MHz Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V,
OUT
IN
OUT(MIN)
OUT(MIN)
LTC3548-2
LTC3560
DC/DC Converters
I = 40μA, I < 1μA, MS10E, DFN
Q SD
800mA (I ), 2.25MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V,
OUT
IN
I = 16μA, I < 1μA, ThinSOT
Q
SD
ThinSOT is a trademark of Linear Technology Corporation.
3565f
LT 0109 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTC3567EUF#PBF
LTC3567 - High Efficiency USB Power Manager Plus 1A Buck-Boost Converter with I<sup>2</sup>C Control; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明