LTC3568EDD#PBF [Linear]
LTC3568 - 1.8A, 4MHz, Synchronous Step-Down DC/DC Converter; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C;
| 型号： | LTC3568EDD#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3568 - 1.8A, 4MHz, Synchronous Step-Down DC/DC Converter; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总18页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3568
1.8A, 4MHz, Synchronous
Step-Down DC/DC Converter
FeaTures
DescripTion
The LTC®3568 is a constant frequency, synchronous
step- down DC/DC converter. Intended for medium power
applications, it operates from a 2.5V to 5.5V input voltage
range and has a user configurable operating frequency
up to 4MHz, allowing the use of tiny, low cost capacitors
and inductors 2mm or less in height. The output voltage
is adjustable from 0.8V to 5V. Internal sychronous 0.11Ω
power switches with 2.4A peak current ratings provide
high efficiency. The LTC3568’s current mode architecture
and external compensation allow the transient response
to be optimized over a wide range of loads and output
capacitors.
n
ꢀ UsesꢀTinyꢀCapacitorsꢀandꢀInductor
n
ꢀ HighꢀFrequencyꢀOperation:ꢀUpꢀtoꢀ4MHz
n
ꢀ LowꢀR
ꢀInternalꢀSwitches:ꢀ0.110Ω
DS(ON)
n
n
n
High Efficiency: Up to 96%
Stable with Ceramic Capacitors
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
Low Dropout Operation: 100% Duty Cycle
n
n
n
n
n
n
n
n
Low Shutdown Current: I ≤ 1µA
Q
Low Quiescent Current: 60µA
Output Voltages from 0.8V to 5V
Selectable Burst Mode® Operation
Sychronizable to External Clock
Small 3mm × 3mm, 10-Lead DFN Package
The LTC3568 can be configured for automatic power sav-
ing Burst Mode operation to reduce gate charge losses
when the load current drops below the level required for
continuous operation. For reduced noise and RF interfer-
ence,theSYNC/MODEpincanbeconfiguredtoskippulses
or provide forced continuous operation.
applicaTions
n
Notebook Computers
n
Digital Cameras
To further maximize battery life, the P-channel MOSFET
is turned on continuously in dropout (100% duty cycle)
with a low quiescent current of 60µA. In shutdown, the
device draws <1µA.
n
Cellular Phones
Handheld Instruments
Board Mounted Power Supplies
n
n
L, LT, LTC, LTM, Linear Technology, the Linear logo, OPTI-LOOP and Burst Mode are
registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
5481178, 6580258, 6304066, 6127815, 6611131.
Typical applicaTion
EfficiencyꢀvsꢀLoadꢀCurrent
V
IN
2.5V TO 5.5V
100
95
90
85
80
75
70
1000
100
22µF
EFFICIENCY
V
IN
SYNC/MODE
PGOOD
PV
SV
IN
L1
IN
2µH
V
OUT
SW
2.5V/1.8A
LTC3568
I
22µF + 10µF
POWER LOSS
TH
887k
SHDN/R
V
FB
T
10
1
13k
1000pF
V
V
O
= 3.3V
= 2.5V
= 1MHz
SGND
PGND
IN
OUT
324k
412k
f
Burst Mode
OPERATION
NOTE: IN DROPOUT, THE OUTPUT TRACKS
THE INPUT VOLTAGE
3568 F01
1
10
100
1000
10000
LOAD CURRENT (mA)
3568 TA01
Figureꢀ1.ꢀStep-Downꢀ1.8AꢀRegulator
3568fa
ꢀ
LTC3568
absoluTe MaxiMuM raTings
pin conFiguraTion
(Noteꢀ1)
TOP VIEW
PV , SV Voltages .....................................–0.3V to 6V
IN
IN
SHDN/R
1
2
3
4
5
10
9
I
TH
V , I , SHDN/R Voltages.......... –0.3V to (V + 0.3V)
T
FB TH
T
IN
SYNC/MODE
SGND
V
FB
SYNC/MODE Voltage .................... –0.3V to (V + 0.3V)
IN
11
8
PGOOD
SW Voltage ................................... –0.3V to (V + 0.3V)
IN
SW
7
SV
IN
PV
IN
PGOOD Voltage............................................–0.3V to 6V
PGND
6
Operating Junction Temperature Range
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
(Note 2) .............................................–40°C to 125°C
Junction Temperature (Notes 5, 8)........................ 125°C
Storage Temperature Range ..................–65°C to 125°C
T
= 125°C, θ = 43°C/W, θ = 3°C/W
JA JC
JMAX
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEADꢀFREEꢀFINISH
LTC3568EDD#PBF
LTC3568IDD#PBF
LEADꢀBASEDꢀFINISH
LTC3568EDD
TAPEꢀANDꢀREEL
PARTꢀMARKING*
LCSG
PACKAGEꢀDESCRIPTION
TEMPERATUREꢀRANGE
LTC3568EDD#TRPBF
LTC3568IDD#TRPBF
TAPEꢀANDꢀREEL
–40°C to 125°C
–40°C to 125°C
TEMPERATUREꢀRANGE
–40°C to 125°C
–40°C to 125°C
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
PACKAGEꢀDESCRIPTION
LCSG
PARTꢀMARKING*
LCSG
LTC3568EDD#TR
LTC3568IDD#TR
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
LTC3568IDD
LCSG
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ꢀ
temperatureꢀrange,ꢀotherwiseꢀspecificationsꢀareꢀatꢀTAꢀ=ꢀ25°C.ꢀVINꢀ=ꢀ3.3V,ꢀRTꢀ=ꢀ324kꢀunlessꢀotherwiseꢀspecified.ꢀ(Noteꢀ2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
V
V
IN
Operating Voltage Range
Feedback Pin Input Current
Feedback Voltage
2.25
I
FB
(Note 3)
0.1
µA
l
l
V
FB
LTC3568E (Note 3)
LTC3568I (Note 3)
0.784
0.780
0.8
0.8
0.816
0.816
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 2.25V to 5V
0.04
0.2
%/V
ΔV
ΔV
IN
LINEREG
l
l
I
I
I
= 0.36, (Note 3)
= 0.84, (Note 3)
0.02
–0.02
0.2
–0.2
%
%
TH
TH
LOADREG
g
Error Amplifier Transconductance
Pin Load = 5µA (Note 3)
800
µS
m(EA)
TH
I
Input DC Supply Current (Note 4)
Active Mode
S
V
V
V
= 0.75V, SYNC/MODE = 3.3V
240
62
0.1
350
100
1
µA
µA
µA
FB
Sleep Mode
= 3.3V, V = 1V
FB
SYNC/MODE
Shutdown
= 3.3V
SHDN/RT
V
Shutdown Threshold High
Active Oscillator Resistor
V
– 0.6
V – 0.4
IN
1M
V
Ω
SHDN/RT
IN
324k
3568fa
ꢁ
LTC3568
ꢀ
temperatureꢀrange,ꢀotherwiseꢀspecificationsꢀareꢀatꢀTAꢀ=ꢀ25°C.ꢀVINꢀ=ꢀ3.3V,ꢀRTꢀ=ꢀ324kꢀunlessꢀotherwiseꢀspecified.ꢀ(Noteꢀ2)
f
Oscillator Frequency
R = 324k
0.85
1
1.15
4
MHz
MHz
OSC
T
(Note 7)
f
I
Synchronization Frequency
Peak Switch Current Limit
(Note 7)
0.4
2.4
4
4
MHz
A
SYNC
I
TH
= 1.3
3
LIM
R
Top Switch On-Resistance (Note 6)
Bottom Switch On-Resistance (Note 6)
Switch Leakage Current
V
V
V
V
= 3.3V
= 3.3V
= 6V, V
0.11
0.11
0.01
2
0.15
0.15
1
Ω
DS(ON)
IN
IN
IN
IN
Ω
I
= 0V, V = 0V
µA
V
SW(LKG)
ITH/RUN
FB
V
UVLO
Undervoltage Lockout Threshold
Power Good Threshold
Ramping Down
Ramping Up, SHDN/R = 1V
Ramping Down, SHDN/R = 1V
2.25
PGOOD
V
FB
V
FB
6.8
–7.6
%
%
T
T
RPGOOD
Power Good Pull-Down On-Resistance
118
200
Ω
Noteꢀ1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Noteꢀ4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Noteꢀ5: T is calculated from the ambient T and power dissipation P
J
A
D
according to the following formula:
Noteꢀ2: The LTC3568 is tested under pulsed load conditions such that T =
J
T = T + (P • 43°C/W)
Noteꢀ6: Switch on-resistance is guaranteed by correlation to wafer level
measurements.
Noteꢀ7: 4MHz operation is guaranteed by design but not production tested
and is subject to duty cycle limitations (see Applications Information).
Noteꢀ8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
J
A
D
T . The LTC3568E is guaranteed to meet performance specifications from
A
0°C to 85°C. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3568I is guaranteed over the
full –40°C to 125°C operating junction temperature range. The maximum
ambient temperature is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistors and
other environmental factors.
Noteꢀ3: The LTC3568 is tested in a feedback loop which servos V to the
FB
midpoint for the error amplifier (V = 0.6V).
ITH
3568fa
ꢂ
LTC3568
Typical perForMance characTerisTics
ꢀ
ꢀ
ꢀ
BurstꢀModeꢀOperation
PulseꢀSkippingꢀMode
ForcedꢀContinuousꢀMode
V
V
OUT
10mV/
DIV
OUT
V
OUT
10mV/
DIV
10mV/
DIV
S
S
W
W
S
W
2V/DIV
2V/DIV
2V/DIV
I
I
L
L
I
L
500mA/
DIV
200mA/
DIV
500mA/
DIV
3568 G01
3568 G02
3568 G03
V
V
LOAD
= 3.3V
10µs/DIV
V
V
LOAD
= 3.3V
2µs/DIV
V
V
LOAD
= 3.3V
IN
2µs/DIV
IN
IN
= 2.5V
= 2.5V
= 2.5V
OUT
OUT
OUT
I
= 100mA
I
= 100mA
I
= 100mA
ꢀ
ꢀ
ꢀ
EfficiencyꢀvsꢀLoadꢀCurrent
EfficiencyꢀvsꢀVIN
LoadꢀStep
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
Burst Mode
OPERATION
I
= 500mA
OUT
V
OUT
100mV/
DIV
I
= 1.8A
OUT
I
L
1A/
DIV
PULSE SKIP
FORCED CONTINUOUS
V
V
= 3.3V
IN
OUT
3568 G06
V
= 2.5V
V
V
LOAD
= 3.3V
50µs/DIV
= 2.5V
OUT
IN
CIRCUIT OF FIGURE 7
= 2.5V
CIRCUIT OF FIGURE 7
OUT
I
= 180mA TO 1.8A
1
10
100
1000
10000
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
LOAD CURRENT (mA)
V
(V)
IN
3568 G04
3568 G05
ꢀ
ꢀ
ꢀ
LoadꢀRegulation
LineꢀRegulation
FrequencyꢀvsꢀVIN
0.6
0.5
0.20
0.15
0.10
0.05
0
10
8
V
V
= 3.3V
OUT
V
= 1.8V
V
I
T
= 1.8V
OUT
IN
OUT
= 1.8V
= 1.25A
OUT
A
Burst Mode
OPERATION
= 25°C
0.4
6
0.3
4
I
= 1.8A
PULSE SKIP
OUT
0.2
2
I
= 500mA
OUT
0.1
0
0
–2
–4
–6
–8
–10
FORCED
–0.05
–0.10
–0.15
–0.20
CONTINUOUS
–0.1
–0.2
–0.3
–0.4
1
10
100
1000
10000
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
(V)
2
3
4
5
6
LOAD CURRENT (mA)
V
V
(V)
IN
IN
3568 G07
3568 G09
3568 G08
3568fa
ꢃ
LTC3568
Typical perForMance characTerisTics
FrequencyꢀVariationꢀꢀ
vsꢀTemperature
ꢀ
EfficiencyꢀvsꢀFrequency
10
8
100
95
V
= 3.3V
IN
V
= 2.5V
OUT
OUT
I
= 500mA
6
T
= 25°C
A
4
2
0
–2
–4
–6
–8
–10
90
85
–50 –25
0
25
50
75 100 125
0
1
2
3
4
TEMPERATURE (°C)
FREQUENCY (MHz)
3568 G10
3568 G11
ꢀ
R
ꢀ
DS(ON)ꢀvsꢀVIN
RDS(ON)ꢀvsꢀTemperature
120
115
110
105
100
95
160
150
140
130
120
110
100
90
T
= 25°C
A
V
= 2.5V
IN
V
= 3.3V
IN
SYNCHRONOUS SWITCH
MAIN SWITCH
V
= 5V
IN
80
70
MAIN SWITCH
SYNCHRONOUS SWITCH
90
2.5
60
3
3.5
4
V
4.5
(V)
5
5.5
6
–50 –25
0
25 50 75 100 125
TEMPERATURE (°C)
IN
3568 G12
3568 G13
3568fa
ꢄ
LTC3568
pin FuncTions
SHDN/R ꢀ (Pinꢀ 1): Combination Shutdown and Timing
PGNDꢀ(Pinꢀ5): Main Power Ground Pin. Connect to the
(–) terminal of C , and (–) terminal of C .
T
Resistor Pin. The oscillator frequency is programmed by
OUT
IN
connecting a resistor from this pin to ground. Forcing
PV ꢀ(Pinꢀ6): Main Supply Pin. Must be closely decoupled
IN
this pin to SV causes the device to be shut down. In
IN
to PGND.
shutdown all functions are disabled.
SV ꢀ(Pinꢀ7): The Signal Power Pin. All active circuitry
IN
SYNC/MODEꢀ(Pinꢀ2): Combination Mode Selection and
is powered from this pin. Must be closely decoupled to
Oscillator Synchronization Pin. This pin controls the op-
SGND. SV must be greater than or equal to PV .
IN
IN
eration of the device. When tied to SV or SGND, Burst
IN
PGOODꢀ(Pinꢀ8): The Power Good Pin. This common drain
logic output is pulled to SGND when the output voltage is
not within 7.5% of regulation.
Mode operation or pulse skipping mode is selected,
respectively. If this pin is held at half of SV , the forced
IN
continuous mode is selected. The oscillation frequency
can be syncronized to an external oscillator applied to
this pin. When synchronized to an external clock pulse
skip mode is selected.
V ꢀ(Pinꢀ9): Receives the feedback voltage from the ex-
FB
ternal resistive divider across the output. Nominal voltage
for this pin is 0.8V.
SGNDꢀ(Pinꢀ3): The Signal Ground Pin. All small signal
componentsandcompensationcomponentsshouldbecon-
nected to this ground (see Board Layout Considerations).
I ꢀ(Pinꢀ10): Error Amplifier Compensation Point. The
TH
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.5V.
SWꢀ(Pinꢀ4): The Switch Node Connection to the Inductor.
GNDꢀ (Exposedꢀ Padꢀ Pinꢀ 11): Thermal Ground. Con-
nect to SGND and solder to the PCB for rated thermal
performance.
This pin swings from PV to PGND.
IN
block DiagraM
SV
IN
SGND
3
I
PV
IN
TH
7
10
6
0.8V
PMOS CURRENT
COMPARATOR
VOLTAGE
REFERENCE
I
TH
LIMIT
+
–
+
–
BCLAMP
–
+
9
V
FB
ERROR
AMPLIFIER
V
B
BURST
COMPARATOR
+
–
0.74V
HYSTERESIS = 80mV
SLOPE
4
SW
COMPENSATION
OSCILLATOR
+
–
+
LOGIC
0.86V
–
NMOS
COMPARATOR
PGOOD
8
–
+
5
PGND
REVERSE
COMPARATOR
1
2
SYNC/MODE
SHDN/R
3568 BD
T
3568fa
ꢅ
LTC3568
operaTion
The LTC3568 uses a constant frequency, current mode
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3568
automaticallyswitchesintoBurstModeoperationinwhich
the PMOS switch operates intermittently based on load
demand. By running cycles periodically, the switching
losses which are dominated by the gate charge losses
of the power MOSFETs are minimized. The main control
loop is interrupted when the output voltage reaches the
desiredregulatedvalue.Thehystereticvoltagecomparator
architecture. The operating frequency is determined by
the value of the R resistor or can be synchronized to an
T
external oscillator. To suit a variety of applications, the
selectable Mode pin, allows the user to trade-off noise
for efficiency.
The output voltage is set by an external divider returned
to the V pin. An error amplfier compares the divided
FB
outputvoltagewithareferencevoltageof0.8Vandadjusts
the peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the PGOOD output
low if the output voltage is not within 7.5%.
BtripswhenI isbelow0.24V, shuttingofftheswitchand
TH
reducing the power. The output capacitor and the inductor
supply the power to the load until I /RUN exceeds 0.31V,
TH
turning on the switch and the main control loop which
starts another cycle.
MainꢀControlꢀLoop
For lower output voltage ripple at low currents, pulse
skipping mode can be used. In this mode, the LTC3568
continues to switch at a constant frequency down to
very low currents, where it will eventually begin skipping
pulses.
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the V voltage is below the the reference voltage.
FB
The current into the inductor and the load increases until
the current limit is reached. The switch turns off and
energy stored in the inductor flows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.
Finally, in forced continuous mode, the inductor current
is constantly cycled which creates a fixed output voltage
ripple at all output current levels. This feature is desirable
in telecommunications since the noise is at a constant
frequency and is thus easy to filter out. Another advan-
tage of this mode is that the regulator is capable of both
sourcing current into a load and sinking some current
from the output.
The peak inductor current is controlled by the voltage on
the I pin, which is the output of the error amplifier.This
TH
amplifier compares the V pin to the 0.8V reference.
FB
Whentheloadcurrentincreases,theV voltagedecreases
FB
slightly below the reference. This decrease causes the er-
ror amplifier to increase the I voltage until the average
TH
DropoutꢀOperation
inductor current matches the new load current.
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which
is the dropout condition. In dropout, the PMOS switch is
turnedoncontinuouslywiththeoutputvoltagebeingequal
to the input voltage minus the voltage drops across the
internal P-channel MOSFET and the inductor.
ThemaincontrolloopisshutdownbypullingtheSHDN/R
T
pin to SV . A digital soft-start is enabled after shutdown,
IN
which will slowly ramp the peak inductor current up over
1024 clock cycles or until the output reaches regulation,
whicheverisfirst.Soft-startcanbelengthenedbyramping
the voltage on the I pin (see Applications Information
TH
section).
LowꢀSupplyꢀOperation
LowꢀCurrentꢀOperation
TheLTC3568incorporatesanundervoltagelockoutcircuit
which shuts down the part when the input voltage drops
below about 2V.
Three modes are available to control the operation of the
LTC3568 at low currents. All three modes automatically
switch from continuous operation to to the selected mode
when the load current is low.
3568fa
ꢆ
LTC3568
applicaTions inForMaTion
A general LTC3568 application circuit is shown in
Figure 5.Externalcomponentselectionisdrivenbytheload
requirement, and begins with the selection of the inductor
A reasonable starting point for setting ripple current is
ΔI = 0.4 • I , where I is the maximum output cur-
L
OUT
OUT
rent. The largest ripplecurrent ∆I occurs atthe maximum
L
L1. Once L1 is chosen, C and C
can be selected.
input voltage. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
IN
OUT
OperatingꢀFrequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
VOUT
fO • ΔIL
VOUT
L =
• 1−
V
IN(MAX)
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
The operating frequency, f , of the LTC3568 is determined
O
by an external resistor that is connected between the R
T
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timingcapacitorwithintheoscillatorandcanbecalculated
by using the following equation:
4.5
T
= 25°C
A
−1.08
RT = 9.78 •1011
f
Ω
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
O
or can be selected using Figure 2.
The maximum usable operating frequency is limited by
the minimum on-time and the duty cycle. This can be
calculated as:
f
≈ 6.67 • (V
/ V ) (MHz)
IN(MAX)
O(MAX)
OUT
The minimum frequency is limited by leakage and noise
0
0
500
1000
1500
coupling due to the large resistance of R .
T
R
T
(kΩ)
3568 F02
InductorꢀSelection
Figureꢀ2.ꢀFrequencyꢀvsꢀRT
Although the inductor does not influence the operat-
ing frequency, the inductor value has a direct effect on
InductorꢀCoreꢀSelection
Differentcorematerialsandshapeswillchangethesize/cur-
rent and price/current relationship of an inductor. Toroid or
shieldedpotcoresinferriteorpermalloymaterialsaresmall
anddon’tradiatemuchenergy,butgenerallycostmorethan
powdered iron core inductors with similar electrical char-
acteristics. The choice of which style inductor to use often
depends more on the price vs size requirements and any
radiated field/EMI requirements than on what the LTC3568
requires to operate. Table 1 shows some typical surface
ripple current. The inductor ripple current ΔI decreases
L
with higher inductance and increases with higher V or
IN
V
:
OUT
VOUT
fO •L
VOUT
VIN
ΔIL =
• 1−
Accepting larger values of ΔI allows the use of low induc-
L
tances, but results in higher output voltage ripple, greater
mount inductors that work well in LTC3568 applications.
core losses, and lower output current capability.
3568fa
ꢇ
LTC3568
applicaTions inForMaTion
Tableꢀ1.ꢀRepresentativeꢀSurfaceꢀMountꢀInductors
V for high frequency decoupling, when not using an all
IN
ceramic capacitor solution.
MANU-ꢀ
FACTURER PARTꢀNUMBER
MAXꢀDCꢀ
VALUE CURRENT DCR HEIGHT
OutputꢀCapacitorꢀ(C )ꢀSelection
Toko
A914BYW-2R2M (D52LC) 2.2µH 2.05A
2mm
3mm
49mΩ
22mΩ
24mΩ
70mΩ
35mΩ
23mΩ
30mΩ
46mΩ
29mΩ
32mΩ
45mΩ
OUT
Toko
A915Y-2R0M (D53LC-A)
2µH
3.3A
2.33A
2.3A
The selection of C
is driven by the required ESR to
OUT
Toko
A918CY-2R0M (D62LCB) 2µH
2mm
minimizevoltagerippleandloadsteptransients. Typically,
Coilcraft
Sumida
Sumida
Sumida
TDK
D01608C-222
2.2µH
1.7µH
3mm
once the ESR requirement is satisfied, the capacitance
CDRH2D18/HP1R7
CDRH4D282R2
CDC5D232R2
1.8A
2mm
is adequate for filtering. The output ripple (ΔV ) is
OUT
determined by:
2.2µH 2.04A
2.2µH 2.16A
1.8µH 1.97A
3mm
2.5mm
2mm
1
VLCF4020T-1R8N1R9
ΔVOUT ≈ ΔIL ESR +
8fOCOUT
Taiyo Yuden N06DB2R2M
Taiyo Yuden N05DB2R2M
2.2µH
2.2µH
2µH
3.2A
2.9A
3.2mm
2.8mm
1.45mm
where f = operating frequency, C
= output capacitance
OUT
Cooper
SD14-2R0
2.37A
and ΔI = ripple current in the inductor. The output ripple
L
is highest at maximum input voltage since ΔI increases
L
with input voltage. With ΔI = 0.4 • I
the output ripple
L
OUT
CatchꢀDiodeꢀSelection
will be less than 100mV at maximum V and f = 1MHz
IN
O
A catch diode is not necessary.
with:
ESRC
< 130mΩ
InputꢀCapacitorꢀ(C )ꢀSelection
OUT
IN
Once the ESR requirements for C
have been met, the
In continuous mode, the input current of the converter is a
OUT
RMS current rating generally far exceeds the I
square wave with a duty cycle of approximately V /V .
RIPPLE(P-P)
OUT IN
requirement, except for an all ceramic solution.
Topreventlargevoltagetransients, alowequivalentseries
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
In surface mount applications, multiple capacitors may
havetobeparalleledtomeetthecapacitance, ESRorRMS
currenthandlingrequirementoftheapplication.Aluminum
electrolytic, special polymer, ceramic and dry tantulum
capacitors are all available in surface mount packages.
The OS-CON semiconductor dielectric capacitor avail-
able from Sanyo has the lowest ESR(size) product of any
aluminumelectrolyticatasomewhathigherprice. Special
polymer capacitors, such as Sanyo POSCAP, offer very
low ESR, but have a lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
density, but it has a larger ESR and it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surfacemounttantalums,avalableincaseheightsranging
from2mmto4mm.Aluminumelectrolyticcapacitorshave
a significantly larger ESR, and is often used in extremely
cost-sensitive applications provided that consideration
is given to ripple current ratings and long term reliability.
VOUT (V − VOUT
)
IN
IRMS ≈ IMAX
V
IN
where the maximum average output current I
equals
MAX
the peak current minus half the peak-to-peak ripple cur-
rent, I = I – ΔI /2.
MAX
LIM
L
This formula has a maximum at V = 2V , where
IN
OUT
I
= I /2. This simple worst case is commonly used
RMS
OUT
to design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple cur-
rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required.Severalcapacitorsmayalsobeparalleledtomeet
thesizeorheightrequirementsofthedesign.Anadditional
0.1µF to 1µF ceramic capacitor is also recommended on
3568fa
ꢈ
LTC3568
applicaTions inForMaTion
Ceramic capacitors have the lowest ESR and cost but also
have the lowest capacitance density, a high voltage and
temperature coefficient and exhibit audible piezoelectric
effects. Inaddition, thehighQofceramiccapacitorsalong
withtraceinductancecanleadtosignificantringing.Other
capacitor types include the Panasonic specialty polymer
(SP) capacitors.
cycles are required to respond to a load step, but only in
the first cycle does the output drop linearly. The output
droop, V
, is usually about 2 to 3 times the linear
DROOP
drop of the first cycle. Thus, a good place to start is with
the output capacitor size of approximately:
ΔIOUT
COUT ≈ 2.5
fO •VDROOP
In most cases, 0.1µF to 1µF of ceramic capacitors should
also be placed close to the LTC3568 in parallel with the
main capacitors for high frequency decoupling.
More capacitance may be required depending on the duty
cycle and load step requirements.
Inmostapplications,theinputcapacitorismerelyrequired
to supply high frequency bypassing, since the impedance
to the supply is very low. A 22µF ceramic capacitor is
usually enough for these conditions.
CeramicꢀInputꢀandꢀOutputꢀCapacitors
Higher value, lower cost ceramic capacitors are now be-
comingavailableinsmallercasesizes. Thesearetempting
for switching regulator use because of their very low ESR.
Unfortunately, the ESR is so low that it can cause loop
stabilityproblems.SolidtantalumcapacitorESRgenerates
aloop“zero”at5kHzto50kHzthatisinstrumentalingiving
acceptableloopphasemargin. Ceramiccapacitorsremain
capacitive to beyond 300kHz and ususally resonate with
their ESL before ESR becomes effective. Also, ceramic
caps are prone to temperature effects which requires the
designer to check loop stability over the operating tem-
perature range. To minimize their large temperature and
voltage coefficients, only X5R or X7R ceramic capacitors
should be used. A good selection of ceramic capacitors
is available from Taiyo Yuden, TDK and Murata.
SettingꢀtheꢀOutputꢀVoltage
The LTC3568 develops a 0.8V reference voltage between
the feedback pin, V , and the signal ground as shown in
FB
Figure 5. The output voltage is set by a resistive divider
according to the following formula:
R2
R1
VOUT ≈ 0.8V 1+
Keeping the current small (<5µA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, suchasfromawalladapter, aloadstepattheoutput
Toimprovethefrequencyresponse,afeed-forwardcapaci-
tor C may also be used. Great care should be taken to
F
route the V line away from noise sources, such as the
FB
inductor or the SW line.
can induce ringing at the V pin. At best, this ringing can
IN
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
ShutdownꢀandꢀSoft-Start
The SHDN/R pin is a dual purpose pin that sets the oscil-
T
lator frequency and provides a means to shut down the
LTC3568. This pin can be interfaced with control logic in
several ways, as shown in Figure 3(a) and Figure 3(b).
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation com-
ponents and the output capacitor size. Typically, 3 to 4
The I pin is primarily for loop compensation, but it can
TH
also be used to increase the soft-start time. Soft start
reduces surge currents from V by gradually increasing
IN
the peak inductor current. Power supply sequencing can
also be accomplished using this pin. The LTC3568 has an
3568fa
ꢀ0
LTC3568
applicaTions inForMaTion
SHDN/R
SHDN/R
SV
IN
T
T
to ground, pulse skipping operation is selected which
provides the lowest output voltage and current ripple
at the cost of low current efficiency. Applying a voltage
R
T
R
T
1M
RUN
between SV – 1V and 1V, results in forced continuous
RUN
IN
mode, which creates a fixed output ripple and is capable
of sinking some current (about 1/2ΔI ). Since the switch-
L
(3a)
(3b)
ing noise is constant in this mode, it is also the easiest to
filter out. In many cases, the output voltage can be simply
connected to the SYNC/MODE pin, giving the forced con-
tinuous mode, except at startup.
RUN OR V
I
IN
TH
R1
R
C
D1
C1
C
C
TheLTC3568canalsobesynchronizedtoanexternalclock
signal by the SYNC/MODE pin. The internal oscillator fre-
quency should be set to 20% lower than the external clock
frequency to ensure adequate slope compensation, since
slope compensation is derived from the internal oscillator.
During synchronization, the mode is set to pulse skipping
and the top switch turn on is synchronized to the rising
edge of the external clock.
3568 F03
(3c)
Figureꢀ3.ꢀSHDN/RTꢀPinꢀInterfacingꢀandꢀExternalꢀSoft-Start
internal digital soft-start which steps up a clamp on I
over 1024 clock cycles, as can be seen in Figure 4.
TH
The soft-start time can be increased by ramping the volt-
age on I during start-up as shown in Figure 3(c). As
TH
CheckingꢀTransientꢀResponse
the voltage on I ramps through its operating range the
TH
The OPTI-LOOP® compensation allows the transient
response to be optimized for a wide range of loads and
internal peak current limit is also ramped at a proportional
linear rate.
output capacitors. The availability of the I pin not only
TH
allows optimization of the control loop behavior but also
providesaDC-coupledandACfilteredclosedloopresponse
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantlysecondordersystem,phasemarginand/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
V
IN
5V/DIV
V
OUT
1V/DIV
I
L
1A/DIV
The I external components shown in the Figure 1 circuit
TH
3568 F04
will provide an adequate starting point for most applica-
tions. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedbackfactorgainandphase. Anoutputcurrentpulseof
20% to 100% of full load current having a rise time of 1µs
V
V
LOAD
= 3.3V
400µs/DIV
IN
= 2.5V
= 1.8A
OUT
I
Figureꢀ4.ꢀDigitalꢀSoft-Start
ModeꢀSelectionꢀandꢀFrequencyꢀSynchronization
TheSYNC/MODEpinisamultipurposepinwhichprovides
mode selection and frequency synchronization. Connect-
ing this pin to V enables Burst Mode operation, which
IN
provides the best low current efficiency at the cost of a
to10µswillproduceoutputvoltageandI pinwaveforms
higher output voltage ripple. When this pin is connected
TH
3568fa
ꢀꢀ
LTC3568
applicaTions inForMaTion
that will give a sense of the overall loop stability without
breaking the feedback loop.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
inputvoltageV dropstowardV ,theloadstepcapability
IN
OUT
Switching regulators take several cycles to respond to a
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta or single inductor, positive buck/boost.
step in load current. When a load step occurs, V
im-
OUT
•ESR,where
mediatelyshiftsbyanamountequaltoΔI
LOAD
ESR is the effective series resistance of C . ΔI
also
OUT LOAD
generating a feedback
begins to charge or discharge C
OUT
error signal used by the regulator to return V
to its
can
Insomeapplications,amoreseveretransientcanbecaused
by switching in loads with large (>1uF) input capacitors.
Thedischargedinputcapacitorsareeffectivelyputinparal-
OUT
steady-state value. During this recovery time, V
OUT
be monitored for overshoot or ringing that would indicate
a stability problem.
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
can deliver enough current to prevent this problem, if the
switchconnectingtheloadhaslowresistanceandisdriven
quickly.Thesolutionistolimittheturn-onspeedoftheload
switchdriver.Ahotswapcontrollerisdesignedspecifically
for this purpose and usually incorporates current limiting,
short-circuit protection, and soft-starting.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capacitor
EfficiencyꢀConsiderations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
C can be added to improve the high frequency response,
F
as shown in Figure 5. Capacitor C provides phase lead by
F
creating a high frequency zero with R2 which improves
the phase margin.
Theoutputvoltagesettlingbehaviorisrelatedtothestability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
V
IN
2.5V
+
TO 5.5V
R5
R6
C6
C
IN
SV
PV
PGOOD
SW
PGOOD
IN
IN
C8
V
OUT
PGND
PGND
L1
C
+
LTC3568
SYNC/MODE
F
SGND
C
C5
OUT
I
V
FB
TH
PGND
PGND
R2
R
SGND PGND SHDN/R
C
T
R1
C
SGND
ITH
R
T
C
C
SGND
SGND
GND
SGND SGND
3568 F05
Figureꢀ5.ꢀLTC3568ꢀGeneralꢀSchematic
3568fa
ꢀꢁ
LTC3568
applicaTions inForMaTion
the losses in LTC3568 circuits: 1) LTC3568 V current,
ThermalꢀConsiderations
IN
2
2) switching losses, 3) I R losses, 4) other losses.
In a majority of applications, the LTC3568 does not dis-
sipate much heat due to its high efficiency. However, in
applicationswheretheLTC3568isrunningathighambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
1. The V current is the DC supply current given in the
IN
electricalcharacteristicswhichexcludesMOSFETdriver
and control currents. V current results in a small loss
IN
that increases with V , even at no load.
IN
2. The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
To avoid the LTC3568 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
from V to ground. The resulting dQ/dt is a current
IN
out of V that is typically much larger than the DC bias
IN
current. In continuous mode, I
= f (QT + QB),
GATECHG
O
where QT and QB are the gate charges of the internal
top and bottom MOSFET switches. The gate charge
losses are proportional to V and thus their effects
IN
T
RISE
= P • θ
D JA
will be more pronounced at higher supply voltages.
where P is the power dissipated by the regulator and θ
D
JA
2
3. I R Losses are calculated from the DC resistances of
is the thermal resistance from the junction of the die to
the internal switches, R , and external inductor, RL. In
SW
the ambient temperature.
continuous mode, the average output current flowing
through inductor L is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
The junction temperature, T , is given by:
J
T = T
+ T
AMBIENT
J
RISE
As an example, consider the case when the LTC3568 is in
dropout at an input voltage of 3.3V with a load current of
1.8A with a 70°C ambient temperature. From the Typical
Performance Characteristics graph of Switch Resistance,
bottom MOSFET R
follows:
and the duty cycle (DC) as
DS(ON)
R
= (R TOP)(DC) + (R BOT)(1 – DC)
DS(ON) DS(ON)
SW
the R
resistance of the P-channel switch is 0.125Ω.
TheR
forboththetopandbottomMOSFETscanbe
DS(ON)
DS(ON)
Therefore, power dissipated by the part is:
obtained from the Typical Performance Characteristics
2
2
curves. Thus, to obtain I R losses:
P = I • R
= 405mW
D
DS(ON)
2
I R losses = I 2(R + RL)
OUT
SW
The DFN package junction-to-ambient thermal resistance,
is 43°C/W. Therefore, the junction temperature of the
θ
JA
4. Other“hidden”lossessuchascoppertraceandinternal
batteryresistancescanaccountforadditionalefficiency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
regulator operating in a 70°C ambient temperature is
approximately:
T = 0.405 • 43 + 70 = 87.4°C
J
Remembering that the above junction temperature is
can be minimized by making sure that C has adequate
IN
obtained from an R
at 70°C, we might recalculate
DS(ON)
charge storage and very low ESR at the switching fre-
quency.Otherlossesincludingdiodeconductionlosses
during dead-time and inductor core losses generally
account for less than 2% total additional loss.
the junction temperature based on a higher R
since
DS(ON)
it increases with temperature. However, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
3568fa
ꢀꢂ
LTC3568
applicaTions inForMaTion
DesignꢀExample
The closest standard value is 22µF plus 10µF. Since the
supply’s output impedance is very low, C is typically a
IN
Asadesignexample,considerusingtheLTC3568inatypical
22µF. In noisy environments, decoupling SV from PV
IN
IN
application with V = 5V. The load requires a maximum
IN
with an R6/C8 filter of 1Ω/0.1µF may help, but is typically
not needed.
of 1.8A in active mode and 10mA in standby mode. The
output voltage is V
= 2.5V. Since the load still needs
OUT
power in standby, Burst Mode operation is selected for
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2µA with the 0.8V feedback voltage makes R1~400k. A
close standard 1% resistor is 412k and R2 is then 887k.
good low load efficiency.
First, calculate the timing resistor:
RT = 9.78 •1011 1MHz −1.08 = 323.8k
The compensation should be optimized for these compo-
nentsbyexaminingtheloadstepresponsebutagoodplace
to start for the LTC3568 is with a 13kΩ and 1000pF filter.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
Use a standard value of 324k. Next, calculate the inductor
value for about 40% ripple current at maximum V :
IN
2.5V
1MHz •720mA
2.5V
5V
L =
• 1−
=1.7µH
The PGOOD pin is a common drain output and requires
a pull-up resistor. A 100k resistor is used for adequate
speed.
Choosing the closest inductor from a vendor of 2µH,
results in a maximum ripple current of:
Figure 1 shows the complete schematic for this design
example.
2.5V
1MHz •2µ
2.5V
5V
ΔIL =
• 1−
= 625mA
BoardꢀLayoutꢀConsiderations
For cost reasons, a ceramic capacitor will be used. C
OUT
selection is then based on load step droop instead of ESR
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3568. These items are also illustrated graphically
in the layout diagram of Figure 6. Check the following in
your layout:
requirements. For a 5% output droop:
1.8A
1MHz •(5%•2.5V)
COUT ≈2.5
= 36µF
C
IN
V
IN
C
OUT
PV
SV
PGND
SW
IN
IN
L1
V
OUT
R5
LTC3568
SGND
V
IN
PGOOD
PGOOD
V
SYNC/MODE
SHDN/R
FB
PS
BM
C4
R2
I
TH
T
R1
R3
R
T
C3
3568 F06
BOLD LINES INDICATE HIGH CURRENT PATHS
Figureꢀ6.ꢀLTC3568ꢀLayoutꢀDiagramꢀ(SeeꢀBoardꢀLayoutꢀChecklist)
3568fa
ꢀꢃ
LTC3568
applicaTions inForMaTion
1. Does the capacitor CIN connect to the power VIN
(Pin 6) and power GND (Pin 5) as close as possible?
This capacitor provides the AC current to the internal
power MOSFETs and their drivers.
4. Keep sensitive components away from the SW pin. The
input capacitor C , the compensation capacitor C and
IN
C
C
and all the resistors R1, R2, R , and R should be
ITH
T C
routed away from the SW trace and the inductor L1.
2. Are the C
and L1 closely connected? The (–) plate
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the SGND pin at one
point which is then connected to the PGND pin.
OUT
of C
returns current to PGND and the (–) plate
OUT
of C .
IN
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C and a ground line ter-
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. These copper areas should be
OUT
minated near SGND (Pin 3). The feedback signal V
FB
should be routed away from noisy components and
traces, such as the SW line (Pin 4), and its trace should
be minimized.
connected to one of the input supplies: PV , PGND,
IN
SV or SGND.
IN
Typical applicaTions
V
IN
2.5V TO
5.5V
C1
22µF
R5
100k
PGOOD
PGND
PV
IN
L1
SV
PGOOD
SW
IN
2µH
V
OUT
RS1
1M
1.8V/2.5V/3.3V
AT 1.8A
LTC3568
BM
PS
R2 887K
SYNC/MODE
V
FC
FB
I
SHDN/R
T
RS2
1M
TH
3.3V
2.5V
1.8V
C2
22µF
x2
SGND
PGND
C4 22pF
R3
13k
R4
324k
R1A
280k
R1B
412k
R1C
698k
C3
1000pF
3568 F07a
SGND
SGND
GND
SGND
PGND
NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A915AY-2ROM (D53LC SERIES)
Figureꢀ7.ꢀGeneralꢀPurposeꢀBuckꢀRegulatorꢀUsingꢀCeramicꢀCapacitors
EfficiencyꢀvsꢀLoadꢀCurrent
100
Burst Mode
OPERATION
95
90
85
80
PULSE SKIP
FORCED CONTINUOUS
V
V
= 3.3V
75
70
IN
OUT
= 2.5V
CIRCUIT OF FIGURE 7
100 1000 10000
LOAD CURRENT (mA)
1
10
3568 F07b
3568fa
ꢀꢄ
LTC3568
Typical applicaTions
LowꢀOutputꢀVoltage,ꢀ2mmꢀHeightꢀBuckꢀRegulator
EfficiencyꢀvsꢀLoadꢀCurrent
V
IN
95
90
85
80
75
70
2.5V
R5
C1
TO 5.5V
V
= 1.8V
OUT
100k
22µF
PV
IN
PGOOD
SW
PGOOD
V
OUT
PGND
SV
1.2V/1.5V/1.8V
AT 1.8A
IN
R
S1
L1
LTC3568
SYNC/MODE
C4 47pF
1M
C2
BM
1.7µH
47µF
x2
FC
V
= 1.2V
OUT
PS
R
S2
V
FB
1M
R3
13k
C3
1000pF
I
R2
402k
TH
SHDN/R
T
V
= 1.5V
OUT
10
1.8V
1.5V 1.2V
SGND PGND
SGND
R4
324k
R1A
316k
R1B
453k
R1C
787k
V
= 3.3V
IN
Burst Mode OPERATION
= 1MHz
GND
f
3568 TA04
O
1
100
1000
10000
C1: TAIYO YUDEN JMK325BJ226MM
C2: TAIYO YUDEN JMK325BJ476MM
L1: SUMIDA CDRH2D18/HP1R7
SGND
LOAD CURRENT (mA)
3568 TA05
package DescripTion
DDꢀPackage
10-LeadꢀPlasticꢀDFNꢀ(3mmꢀ×ꢀ3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
R = 0.125
0.40 p 0.10
TYP
6
10
0.70 p0.05
3.55 p0.05
1.65 p0.05
(2 SIDES)
3.00 p0.10 1.65 p 0.10
(4 SIDES)
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
2.15 p0.05
PIN 1
TOP MARK
(SEE NOTE 6)
PACKAGE
OUTLINE
CHAMFER
(DD) DFN REV C 0310
5
1
0.25 p 0.05
0.50 BSC
0.75 p0.05
0.200 REF
0.25 p 0.05
0.50
BSC
2.38 p0.10
(2 SIDES)
2.38 p0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3568fa
ꢀꢅ
LTC3568
revision hisTory
REV
DATE
DESCRIPTION
PAGEꢀNUMBER
A
9/10
I-Grade added. Reflected throughout the data sheet
1 to 18
3568fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ꢀꢆ
LTC3568
Typical applicaTion
1mmꢀHeight,ꢀ2MHz,ꢀLi-Ionꢀtoꢀ1.8VꢀConverter
EfficiencyꢀvsꢀLoadꢀCurrent
95
90
85
80
75
70
65
60
V
IN
V
= 2.7V
IN
2.5V
R5
TO 4.2V
C1
10µF
x2
100k
PV
SV
PGOOD
SW
PGOOD
C4 22pF
IN
V
OUT
1.8V
IN
L1
1µH
AT 1.8A
LTC3568
SYNC/MODE
C2
10µF
x3
V
= 4.2V
IN
V
= 3.6V
IN
I
TH
V
FB
R2
R1
R3
10k
C3
1000pF
C7
47pF
SGND PGND SHDN/R
T
887k
698k
R4
154k
V
O
= 1.8V
OUT
= 2MHz
f
3568 TA02
C1, C2: MURATA GRM319R60J106KE01B
L1: COOPER SD10-1R0
1
10
100
1000
10000
LOAD CURRENT (mA)
3568 TA03
relaTeD parTs
PARTꢀNUMBER
DESCRIPTION
600mA (I ), 1.5MHz, Synchronous Step-Down DC/DC Converter
COMMENTS
96% Efficiency, V : 2.5V to 5.5V, V = 0.6V,
OUT(MIN)
LTC3406/LTC3406B
OUT
IN
I = 20µA, I <1µA, ThinSOT™ Package
Q
SD
LTC3407/LTC3407-2 Dual 600mA/800mA (I ), 1.5MHz/2.25MHz, Synchronous Step-Down
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V,
OUT(MIN)
OUT
IN
DC/DC Converter
I = 40µA, I <1µA, MS10E and DFN Packages
Q SD
LTC3410/LTC3410B
LTC3411
300mA (I ), 2.25MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V,
OUT
IN
OUT(MIN)
I = 26µA, I <1µA, SC70 Package
Q
SD
1.25A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
96% Efficiency, V : 2.6V to 5.5V, V
IN
= 0.8V,
OUT
OUT(MIN)
I = 60µA, I <1µA, MS10 and DFN Packages
Q
SD
LTC3412
2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
96% Efficiency, V : 2.6V to 5.5V, V
= 0.8V,
OUT(MIN)
OUT
IN
I = 62µA, I <1µA, TSSOP-16E and QFN Packages
Q
SD
LTC3531/LTC3531-3/ 200mA (I ), 1.5MHz, Synchronous Buck-Boost DC/DC Converter
95% Efficiency, V : 1.8V to 5.5V, V
: 2V to 5V,
OUT(MIN)
OUT
IN
LTC3531-3.3
I = 16µA, I <1µA, ThinSOT and DFN Packages
Q SD
LTC3532
500mA (I ), 2MHz, Synchronous Buck-Boost DC/DC Converter
95% Efficiency, V : 2.4V to 5.5V, V
: 2.4V to
OUT(MIN)
OUT
IN
5.25V, I = 35µA, I <1µA, MS10 and DFN Packages
Q
SD
LTC3542
500mA (I ), 2.25MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V,
= 0.8V,
= 0.6V,
= 0.6V,
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
I = 26µA, I <1µA, DFN Package
Q
SD
LTC3544
Quad 300mA + 2x 200mA + 100mA 2.25MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
IN
I = 70µA, I <1µA, QFN Package
Q
SD
LTC3547/LTC3547B
Dual 300mA 2.25MHz, Synchronous Step-Down DC/DC Converter
96% Efficiency, V : 2.5V to 5.5V, V
IN
I = 40µA, I <1µA, DFN Package
Q
SD
LTC3548/LTC3548-1/ Dual 400mA and 800mA (I ), 2.25MHz, Synchronous Step-Down
LTC3548-2
95% Efficiency, V : 2.5V to 5.5V, V
IN
I = 40µA, I <1µA, MS10E and DFN Packages
Q SD
OUT
DC/DC Converter
LTC3560
800mA (I ), 2.25MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V,
OUT(MIN)
OUT
IN
I = 16µA, I <1µA, ThinSOT Package
Q
SD
3568fa
LT 0910 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
ꢀꢇ
●
●
LINEAR TECHNOLOGY CORPORATION 2007
(408)432-1900 FAX: (408) 434-0507 www.linear.com
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