LTC3577 [Linear]
Highly Integrated 6-Channel Portable PMIC; 高度集成的6通道便携式PMIC型号: | LTC3577 |
厂家: | Linear |
描述: | Highly Integrated 6-Channel Portable PMIC |
文件: | 总52页 (文件大小:623K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3577/LTC3577-1
Highly Integrated
6-Channel Portable PMIC
DESCRIPTION
FEATURES
n
Full Featured Li-Ion/Polymer Charger/PowerPath™
The LTC®3577 is a highly integrated power management
IC for single cell Li-Ion/Polymer battery applications. It
includesaPowerPathmanagerwithautomaticloadpriori-
tization,abatterycharger,anidealdiode,inputovervoltage
protectionandnumerousotherinternalprotectionfeatures.
TheLTC3577isdesignedtoaccuratelychargefromcurrent
limited supplies such as USB by automatically reducing
charge current such that the sum of the load current and
thechargecurrentdoesnotexceedtheprogrammedinput
current limit (100mA or 500mA modes). The LTC3577
reduces the battery voltage at elevated temperatures to
improve safety and reliability. Efficient high current charg-
ing from supplies up to 38V is available using the on-chip
Bat-Track controller. The LTC3577 also includes a push-
button input to control the three synchronous step-down
switching regulators and system reset. The onboard LED
backlight boost circuitry can drive up to 10 series LEDs
Control with Instant-On Operation
Triple Adjustable High Efficiency Step-Down
n
Switching Regulators (800mA, 500mA, 500mA I
6μA Battery Drain Current in Hard Reset
)
OUT
n
n
n
n
Bat-Track™ Control for External HV Buck DC/DCs
2
I C Adjustable SW Slew Rates for EMI Reduction
High Temperature Battery Voltage Reduction
Improves Safety and Reliability
n
n
Overvoltage Protection for USB (V )/Wall Inputs
BUS
Provides Protection to 30V
Integrated 40V Series LED Backlight Driver with 60dB
2
Brightness Control and Gradation via I C
n
n
1.5A Maximum Charge Current with Thermal Limiting
Battery Float Voltage:4.2V (LTC3577)
4.1V (LTC3577-1)
n
n
n
Pushbutton On/Off Control with System Reset
Dual 150mA Current Limited LDOs
Small 4mm × 7mm 44-Pin QFN Package
2
and includes versatile digital dimming via I C input. The
2
I C input also controls two 150mA LDOs as well as other
operating modes and status read back. The LTC3577 is
available in a low profile 4mm × 7mm × 0.75mm 44-pin
QFN package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. PowerPath and Bat-Track are trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by U.S.
Patents including 6522118, 6700364, 7511390, 5481178, 6580258. Other Patents Pending.
APPLICATIONS
n
PNDs, DMB/DVB-H; Digital/Satellite Radio;
Media Players
n
Portable Industrial/Medical Products
n
Universal Remotes, Photo Viewers
Other USB-Based Handheld Products
n
TYPICAL APPLICATION
HV SUPPLY
LED Driver Efficiency 10 LEDs
HIGH VOLTAGE
BUCK DC/DC
8V TO 38V
(TRANSIENTS TO 60V)
90
80
70
60
OPTIONAL
100mA/500mA
1000mA
USB
V
OUT
MAX PWM
CONSTANT
CURRENT
0V
OVERVOLTAGE
PROTECTION
50
40
30
20
10
0
CC/CV
CHARGER
+
SINGLE CELL
Li-Ion
NTC
LTC3577/LTC3577-1
CHARGE
2
0.8V to 3.6V/150mA
0.8V to 3.6V/150mA
DUAL LDO
REGULATORS
2
I C PORT
LED BACKLIGHT WITH DIGITALLY
CONTROLLED DIMMING
UP TO 10 LED
BOOST
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01
TRIPLE HIGH EFFICIENCY
STEP-DOWN SWITCHING
REGULATORS WITH
0.8V to 3.6V/800mA
0.8V to 3.6V/500mA
0.8V to 3.6V/500mA
LED CURRENT (A)
PB
3577 TA01b
PUSHBUTTON CONTROL
3577 TA01a
3577f
1
LTC3577/LTC3577-1
TABLE OF CONTENTS
FEATURES/APPLICATIONS ..........................................................................................................................................1
ABSOLUTE MAXIMUM RATINGS.................................................................................................................................3
PACKAGE/ORDER INFORMATION................................................................................................................................3
ELECTRICAL CHARACTERISTICS .......................................................................................................................... 4-10
TYPICAL PERFORMANCE CHARACTERISTICS .................................................................................................... 10-15
PIN FUNCTION..................................................................................................................................................... 15-18
BLOCK DIAGRAM ......................................................................................................................................................18
PowerPath OPERATION ....................................................................................................................................... 19-29
LOW DROPOUT LINEAR REGULATOR OPERATION............................................................................................. 29-30
STEP-DOWN SWITCHING REGULATOR OPERATION .......................................................................................... 30-33
LED BACKLIGHT/BOOST OPERATION.................................................................................................................. 33-36
2
I C OPERATION ................................................................................................................................................... 37-42
PUSHBUTTON INTERFACE OPERATION............................................................................................................... 42-46
LAYOUT AND THERMAL CONSIDERATIONS........................................................................................................ 47-48
TYPICAL APPLICATION........................................................................................................................................ 49-50
PACKAGE DESCRIPTION............................................................................................................................................51
RELATED PARTS........................................................................................................................................................52
3577f
2
LTC3577/LTC3577-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2, 3)
TOP VIEW
V
V
............................................................ –0.3V to 45V
BUS OUT IN12 IN3 INLDO1 INLDO2
SW
, V , V
, V , V
, V
, WALL
t < 1ms and Duty Cycle < 1% .................. –0.3V to 7V
Steady State............................................. –0.3V to 6V
I
1
2
37 IDGATE
36 PROG
35 NTC
34 NTCBIAS
33 SW1
LIM0
CHRG, BAT, LED_FS, LED_OV, PWR_ON, WAKE,
I
LIM1
LED_FS 3
WALL 4
SW3 5
PBSTAT, PG_DCDC, FB1, FB2, FB3, LDO1, LDO1_FB,
LDO2, LDO2_FB, DV , SCL, SDA ............... –0.3V to 6V
CC
V
6
32 V
IN3
IN12
NTC, PROG, CLPROG, ON, I
, I
LIM0 LIM1
45
FB3 7
OVSENS 8
LED_OV 9
DV 10
SDA 11
SCL 12
OVGATE 13
PWR_ON 14
ON 15
31 SW2
30 V
(Note 4)............................................–0.3V to V + 0.3V
CC
INLD02
29 LDO2
28 LDO1
27 LDO1_FB
26 FB1
25 FB2
24 LDO2_FB
I
I
I
I
I
I
I
, I
, I ........................................................2A
(Continuous)................................................850mA
VBUS VOUT BAT
SW3
CC
, I
(Continuous).......................................600mA
(Continuous).....................................200mA
SW2 SW1
, I
LDO1 LDO2
23 V
INLDO1
, I
, I
, I
, I
....................75mA
CHRG ACPR WAKE PBSTAT PG_DCDC
...................................................................10mA
OVSENS
, I
, I
, I
...............................2mA
CLPROG PROG LED_FS LED_OV
Junction Temperature ........................................... 110°C
Operating Temperature Range..................–40°C to 85°C
Storage Temperature Range...................–65°C to 125°C
UFF PACKAGE
44-LEAD (7mm s 4mm) PLASTIC QFN
T
JMAX
= 110°C, θ = 45°C/W
JA
EXPOSED PAD (PIN 45) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3577EUFF#PBF
LTC3577EUFF-1#PBF
TAPE AND REEL
PART MARKING
3577
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3577EUFF#TRPBF
LTC3577EUFF-1#TRPBF
–40°C to 85°C
–40°C to 85°C
44-Lead (4mm × 7mm) Plastic QFN
44-Lead (4mm × 7mm) Plastic QFN
35771
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3577f
3
LTC3577/LTC3577-1
ELECTRICAL CHARACTERISTICS
Power Manager. The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = WALL = 0V,
VINLDO1 = VINLDO2 = VIN12 = VIN3 = VOUT, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Power Supply
V
Input Supply Voltage
4.35
5.5
V
BUS
l
l
l
I
Total Input Current (Note 5)
I
I
I
= 0V, I
= 5V, I
= 5V, I
= 0V (1x Mode)
= 5V (5x Mode)
= 0V (10x Mode)
80
450
900
90
475
950
100
500
1000
mA
mA
mA
BUS(LIM)
LIM0
LIM0
LIM0
LIM1
LIM1
LIM1
I
Input Quiescent Current, POFF State
1x, 5x, 10x Modes
= 0V, I = 5V (Suspend Mode)
0.42
0.042
mA
mA
BUSQ
I
0.1
LIM0
LIM1
h
Ratio of Measured V
Current to
1000
mA/mA
CLPROG
BUS
CLPROG Program Current
V
CLPROG Servo Voltage in Current
Limit
1x Mode
5x Mode
10x Mode
0.2
1.0
2.0
V
V
V
CLPROG
V
V
V
V
Undervoltage Lockout
Rising Threshold
Falling Threshold
3.8
3.7
3.9
V
V
UVLO
BUS
3.5
to V
Differential Undervoltage Rising Threshold
Falling Threshold
50
–50
100
mV
mV
DUVLO
BUS
OUT
Lockout
R
Input Current Limit Power FET On-
Resistance (Between V and V
200
mΩ
ON_ILIM
)
OUT
BUS
Battery Charger
V
V
Regulated Output Voltage
BAT
LTC3577
4.179
4.165
4.079
4.065
4.200
4.200
4.100
4.100
4.221
4.235
4.121
4.135
V
V
V
V
FLOAT
LTC3577, 0 ≤ T ≤ 85°C
A
LTC3577-1
LTC3577-1, 0 ≤ T ≤ 85°C
A
l
l
l
ICHG
Constant-Current Mode Charge Current
R
PROG
R
PROG
R
PROG
= 1k, Input Current Limit = 2A
= 2k, Input Current Limit = 1A
= 5k, Input Current Limit = 0.4A
950
465
180
1000
500
200
1050
535
220
mA
mA
mA
IBATQ_HR
IBATQ_OFF
Battery Drain Current, Hard Reset
Battery Drain Current, POFF State
V
= 0V, I
= 0μA
OUT
7
15
μA
BUS
V
V
= 4.3V, Charger Time Out
= 0V
6
40
27
100
μA
μA
BAT
BUS
IBATQ_ON
Battery Drain Current, PON State
LDOs, and LED Backlight Disabled
V
= 0V, I
= 0μA, No Load on
OUT
90
160
μA
BUS
Supplies, Burst Mode Operation (Note 10)
V
V
PROG Pin Servo Voltage
V
V
> V
< V
1.000
0.100
V
V
PROG,CHG
PROG,TRKL
BAT
BAT
TRKL
TRKL
PROG Pin Servo Voltage in Trickle
Charge
h
Ratio of I
to PROG Pin Current
1000
50
mA/mA
mA
PROG
BAT
I
Trickle Charge Current
V
< V
40
60
TRKL
BAT
TRKL
V
Trickle Charge Rising Threshold
Trickle Charge Falling Threshold
V
V
Rising
Falling
2.85
2.75
3.0
V
V
TRKL
BAT
BAT
2.5
–75
3.2
Recharge Battery Threshold Voltage
Safety Timer Termination Period
Bad Battery Termination Time
Threshold Voltage Relative to V
–100
4
–125
4.8
mV
Hour
ΔV
FLOAT
RECHRG
t
t
Timer Starts when V
= V
– 50mV
TERM
BADBAT
BAT
FLOAT
V
BAT
< V
0.4
0.5
0.1
200
0.6
Hour
TRKL
h
C/10
End-of-Charge Indication Current Ratio (Note 6)
Battery Charger Power FET On-
0.085
0.11
mA/mA
mΩ
R
ON_CHG
Resistance (Between V
and BAT)
OUT
T
Junction Temperature in Constant
Temperature Mode
110
°C
LIM
3577f
4
LTC3577/LTC3577-1
ELECTRICAL CHARACTERISTICS
Power Manager. The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = WALL = 0V,
VINLDO1 = VINLDO2 = VIN12 = VIN3 = VOUT, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NTC, Battery Discharge Protection
V
V
V
Cold Temperature Fault Threshold
Voltage
Rising NTC Voltage
Hysteresis
75
34
76
77
36
%V
%V
COLD
HOT
NTCBIAS
NTCBIAS
1.3
Hot Temperature Fault Threshold
Voltage
Falling NTC Voltage
Hysteresis
35
1.3
%V
%V
NTCBIAS
NTCBIAS
NTC Discharge Threshold Voltage
Falling NTC Voltage
Hysteresis
24.5
–50
25.5
50
26.5
50
%V
2HOT
NTCBIAS
mV
I
I
NTC Leakage Current
BAT Discharge Current
BAT Discharge Threshold
V
V
= V = 5V
BUS
nA
mA
V
NTC
NTC
BAT
= 4.1V, NTC < V
180
3.9
BAT2HOT
TOO_HOT
V
I
< 0.1mA, NTC < V
TOO_HOT
BAT2HOT
BAT
Ideal Diode
V
Forward Voltage Detection
Diode On-Resistance, Dropout
Diode Current Limit
I
I
= 10mA
5
15
200
3.6
25
mV
mΩ
A
FWD
OUT
R
= 200mA
DROPOUT
MAX
OUT
I
(Note 7)
Overvoltage Protection
V
V
Overvoltage Protection Threshold
OVGATE Output Voltage
Rising Threshold, R
= 6.2k
OVSENS
6.10
6.35
6.70
12
V
OVCUTOFF
OVGATE
Input Below V
Input Above V
1.88 • V
V
V
OVCUTOFF
OVCUTOFF
OVSENS
0
I
t
OVSENS Quiescent Current
V
C
= 5V
40
2.5
μA
OVSENSQ
OVSENS
OVGATE
OVGATE Time to Reach Regulation
= 1nF
ms
RISE
Wall Adapter
V
ACPR Pin Output High Voltage
ACPR Pin Output Low Voltage
I
I
= 0.1mA
= 1mA
V
OUT
– 0.3
V
V
V
ACPR
ACPR
ACPR
OUT
0
0.3
V
Absolute Wall Input Threshold Voltage
V
WALL
Rising
Falling
4.3
3.2
4.45
V
V
W
WALL
V
3.1
0
Differential Wall Input Threshold
Voltage
V
WALL
– V Falling
25
75
mV
mV
ΔV
WALL
BAT
W
V
– V Rising
100
0.4
BAT
I
Wall Operating Quiescent Current
I
+ I
, I = 0mA,
= 5V
440
μA
QWALL
WALL
VOUT BAT
WALL = V
OUT
Logic (I
, I
and CHRG)
LIM0 LIM1
V
IL
V
IH
Input Low Voltage
I
I
I
I
, I
V
V
LIM0 LIM1
Input High Voltage
, I
1.2
LIM0 LIM1
I
PD
Static Pull-Down Current
CHRG Pin Output Low Voltage
CHRG Pin Input Current
, I ; V = 1V
LIM0 LIM1 PIN
2
0.15
0
μA
V
V
= 10mA
CHRG
0.4
1
CHRG
CHRG
I
V
= 4.5V, V
= 5V
CHRG
μA
BAT
3577f
5
LTC3577/LTC3577-1
2
I C Interface. The l denotes the specifications which apply over the full
ELECTRICAL CHARACTERISTICS
operating temperature range, otherwise specifications are at TA = 25°C. DVCC = 3.3V, VOUT = 3.8V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DV
Input Supply Voltage
1.6
5.5
V
CC
I
DV Supply Current
CC
SCL = 400kHz
SCL = SDA = 0kHz
1
0.4
μA
μA
DVCC
V
V
V
DV UVLO
1.0
50
50
V
DVCC,UVLO
CC
Input HIGH Voltage
70
%DV
%DV
IH
IL
CC
CC
Input LOW Voltage
30
–1
–1
I
IH
I
IL
Input HIGH Leakage Current
Input LOW Leakage Current
SDA Output LOW Voltage
SDA = SCL = DV = 5.5V
1
1
μA
μA
V
CC
SDA = SCL = 0V, DV = 5.5V
CC
V
OL
I
= 3mA
0.4
SDA
Timing Characteristics (Note 8) (All Values are Referenced to V and V )
IH
IL
f
t
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
400
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
SCL
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Bus Free Time Between Stop and Start Condition
Hold Time After (Repeated) Start Condition
Setup Time for a Repeated Start Condition
Stop Condition Set-Up Time
1.3
0.6
1.3
0.6
0.6
0.6
0
LOW
HIGH
BUF
HD,STA
SU,STA
SU,STO
HD,DATO
HD,DATI
SU,DAT
SP
Output Data Hold Time
900
50
Input Data Hold Time
0
Data Set-Up Time
100
Input Spike Suppression Pulse Width
Step-Down Switching Regulators. The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. VOUT = VIN12 = VIN3 = 3.8V, all regulators enabled unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Step-Down Switching Regulators (Buck1, Buck2 and Buck3)
l
V
V
, V
Input Supply Voltage
(Note 9)
and V Connected to V Through
OUT
2.7
2.5
5.5
V
V
V
IN12 IN3
UVLO
V
V
Falling
Rising
V
2.7
2.8
OUT
OUT
OUT
IN12
IN3
Low Impedance. Switching Regulators are
Disabled Below V UVLO
2.9
OUT
f
Oscillator Frequency
1.91
2.25
2.59
MHz
OSC
800mA Step-Down Switching Regulator 3 (Buck3 – Pushbutton Enabled, Third in Sequence)
I
Pulse-Skipping Mode Input Current
Burst Mode Input Current
Shutdown Input Current
Peak PMOS Current Limit
Feedback Voltage
(Note 10)
(Note 10)
100
17
μA
μA
VIN3Q
0.01
1400
μA
I
(Note 7)
1000
1700
mA
LIM3
l
l
V
Pulse-Skipping Mode
Burst Mode Operation
0.78
0.78
0.8
0.8
0.82
0.824
V
V
FB3
I
FB3 Input Current
Max Duty Cycle
(Note 10)
FB3 = 0V
–0.05
100
0.05
μA
%
Ω
FB3
D3
R
R
R
R
of PMOS
of NMOS
0.3
0.4
P3
N3
DS(ON)
DS(ON)
Ω
3577f
6
LTC3577/LTC3577-1
ELECTRICAL CHARACTERISTICS
Step-Down Switching Regulators. The l denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VOUT = VIN12 = VIN3 = 3.8V,
all regulators enabled unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
R
SW3 Pull-Down in Shutdown
POFF State
10
kΩ
SW3_PD
500mA Step-Down Switching Regulator 2 (Buck2 – Pushbutton Enabled, Second in Sequence)
I
Pulse-Skipping Mode Input Current
Burst Mode Input Current
Shutdown Input Current
Peak PMOS Current Limit
Feedback Voltage
(Note 10)
(Note 10)
100
17
μA
μA
VIN12Q
0.01
900
μA
I
(Note 7)
650
1200
mA
LIM2
l
l
V
Pulse-Skipping Mode
Burst Mode Operation
0.78
0.78
0.8
0.8
0.82
0.824
V
V
FB2
I
FB2 Input Current
Max Duty Cycle
(Note 10)
FB2 = 0V
–0.05
100
0.05
μA
%
FB2
D2
R
R
R
R
R
of PMOS
of NMOS
I
I
= 100mA
0.6
0.6
10
Ω
P2
DS(ON)
DS(ON)
SW2
SW2
= –100mA
Ω
N2
SW2 Pull-Down in Shutdown
POFF State
kΩ
SW2_PD
500mA Step-Down Switching Regulator 1 (Buck1 – Pushbutton Enabled, First in Sequence)
I
Pulse-Skipping Mode Input Current
Burst Mode Input Current
Shutdown Input Current
Peak PMOS Current Limit
Feedback Voltage
(Note 10)
(Note 10)
100
17
μA
μA
VIN12Q
0.01
900
μA
I
(Note 7)
650
1200
mA
LIM1
l
l
V
Pulse-Skipping Mode
Burst Mode Operation
0.78
0.78
0.8
0.8
0.82
0.824
V
V
FB1
I
FB1 Input Current
Max Duty Cycle
(Note 10)
FB1 = 0V
–0.05
100
0.05
μA
%
FB1
D1
R
R
R
R
R
of PMOS
of NMOS
I
I
= 100mA
0.6
0.6
10
Ω
P1
DS(ON)
DS(ON)
SW1
SW1
= –100mA
Ω
N1
SW1 Pull-Down in Shutdown
POFF State
kΩ
SW1_PD
LDO Regulators. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications
are at TA = 25°C. VINLDO1 = VINLDO2 = VOUT = VBAT = 3.8V, LDO1 and LDO2 enabled unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2
LDO Regulator 1 (LDO1 – Enabled Via I C)
l
V
V
Input Voltage Range
V
≤ V + 0.3V
OUT
1.65
2.5
5.5
2.9
V
INLDO1
INLDO1
V
OUT
V
OUT
Falling
Rising
LDO1 is Disabled Below V UVLO
OUT
2.7
2.8
V
V
OUT_UVLO
I
I
LD01 V
LD01 V
Quiescent Current
INLDO1
LDO1 Enabled, PON State, I
LDO1 Enabled, PON State, I
= 0mA
= 0mA
18
0.1
30
2
μA
μA
QLDO1_VO
QLDO1_VI
OUT
LDO1
LDO1
Quiescent Current
I
Shutdown Current
LDO1 Disabled, PON or POFF State
0.01
0.8
0.4
5
1
μA
V
VINLDO1
l
V
LDO1_FB Regulated Feedback Voltage
LDO1_FB Line Regulation (Note 11)
LDO1_FB Load Regulation (Note 11)
LDO1_FB Input Current
I
I
I
= 1mA
0.78
0.82
LDO1_FB
LDO1
LDO1
LDO1
= 1mA, V = 1.65V to 5.5V
mV/V
μV/mA
nA
IN
= 1mA to 150mA
I
I
LDO1_FB = 0.8V
–50
150
50
LDO1_FB
LDO1_OC
l
Available Output Current
mA
3577f
7
LTC3577/LTC3577-1
ELECTRICAL CHARACTERISTICS
LDO Regulators. The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VINLDO1 = VINLDO2 = VOUT = VBAT = 3.8V, LDO1 and LDO2
enabled unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Short-Circuit Output Current
Dropout Voltage (Note 12)
270
mA
LDO1_SC
V
I
I
I
= 150mA, V
= 150mA, V
= 3.6V
= 2.5V
160
200
170
260
320
280
mV
mV
mV
DROP1
LDO1
LDO1
LDO1
INLDO1
INLDO1
= 75mA, V
= 1.8V
INLDO1
R
Output Pull-Down Resistance in Shutdown
LDO1 Disabled
10
kꢀ
LDO1_PD
2
LDO Regulator 2 (LDO2 – Enabled Via I C)
l
V
V
Input Voltage Range
V
≤ V + 0.3V
OUT
1.65
2.5
5.5
2.9
V
INLDO2
INLDO2
V
OUT
V
OUT
Falling
Rising
LDO2 is Disabled Below V UVLO
OUT
2.7
2.8
V
V
OUT_UVLO
I
I
LDO2 V
LDO2 V
Quiescent Current
INLDO2
LDO2 Enabled, PON State, I
LDO2 Enabled, PON State, I
= 0mA
= 0mA
18
0.1
30
2
μA
μA
QLDO2_VO
QLDO2_VI
OUT
LDO2
LDO2
Quiescent Current
I
Shutdown Current
LDO2 Disabled, PON or POFF State
0.01
0.8
0.4
5
1
μA
V
VINLDO2
l
V
LDO2_FB Regulated Output Voltage
LDO2_FB Line Regulation (Note 11)
LDO2_FB Load Regulation (Note 11)
LDO2_FB Input Current
I
I
I
= 1mA
0.78
0.82
LDO2_FB
LDO2
LDO2
LDO2
= 1mA, V = 1.65V to 5.5V
mV/V
μV/mA
nA
IN
= 1mA to 150mA
I
I
I
LDO2_FB = 0.8V
–50
150
50
LDO2_FB
LDO2_OC
LDO2_SC
l
Available Output Current
mA
Short-Circuit Output Current
Dropout Voltage (Note 12)
270
mA
V
I
I
I
= 150mA, V
= 150mA, V
= 3.6V
= 2.5V
160
200
170
260
320
280
mV
mV
mV
DROP2
LDO2
LDO2
LDO1
INLDO2
INLDO2
= 75mA, V
= 1.8V
INLDO1
R
Output Pull-Down Resistance in Shutdown
LDO2 Disabled
14
kꢀ
LDO2_PD
LED Boost Switching Regulator. The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. VIN3 = VOUT = 3.8V, ROV = 10M, RLED_FS = 20k, boost regulator disabled unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
(Note 9)
MIN
TYP
MAX
UNITS
l
V
, V
IN3 OUT
Operating Supply Range
2.7
5.5
V
I
Operating Quiescent Current
Shutdown Quiescent Current
(Notes 10, 14)
560
0.01
μA
μA
VOUT_LED
V
LED_OV Overvoltage Threshold
LED_OV Rising
LED_OV Falling
1.0
1.25
V
V
LED_OV
0.6
800
18
0.85
I
I
I
Peak NMOS Switch Current
1000
20
1200
22
mA
mA
dB
LIM
I
I
Pin Full-Scale Operating Current
Pin Full-Scale Dimming Range
LED_FS
LED_DIM
LED
64 Steps
60
LED
R
R
of NMOS Switch
240
0.01
1.125
800
4
mΩ
μA
NSWON
NSWOFF
OSC
DS(ON)
I
f
NMOS Switch-Off Leakage Current
Oscillator Frequency
V
= 5.5V
1
SW
0.95
780
3.8
1.3
820
4.2
MHz
mV
μA
l
l
V
LED_FS Pin Voltage
LED_FS
LED_OV
I
LED_OV Pin Current
R
= 20k
LED_FS
D
BOOST
Maximum Duty Cycle
I
= 0
97
%
LED
l
V
Boost Mode I
Feedback Voltage
775
800
825
mV
BOOSTFB
LED
3577f
8
LTC3577/LTC3577-1
Pushbutton Controller. The l denotes the specifications which apply
ELECTRICAL CHARACTERISTICS
over the full operating temperature range, otherwise specifications are at TA = 25°C. VOUT = 3.8V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Pushbutton Pin (ON)
l
V
V
Pushbutton Operating Supply Range
(Note 9)
2.7
2.5
5.5
V
OUT
UVLO
V
V
Falling
Rising
Pushbutton is Disabled Below V
UVLO
2.7
2.8
V
V
OUT
OUT
OUT
OUT
2.9
1.2
V
ON Threshold Rising
ON Threshold Falling
0.8
0.7
V
V
ON_TH
0.4
I
ON
ON Input Current
V
ON
V
ON
= V
OUT
= 0V
–1
–4
1
–14
ꢁA
ꢁA
–9
Power-On Input Pin (PWR_ON)
V
PWR_ON Threshold Rising
PWR_ON Threshold Falling
0.8
0.7
1.2
1
V
V
PWR_ON
0.4
–1
I
PWR_ON Input Current
V
V
= 3V
ꢁA
PWR_ON
PWR_ON
Status Output Pins (PBSTAT, WAKE, PG_DCDC)
I
PBSTAT Output High Leakage Current
PBSTAT Output Low Voltage
= 3V
–1
–1
–1
1
0.4
1
ꢁA
V
PBSTAT
PBSTAT
PBSTAT
V
I
= 3mA
0.1
0.1
PBSTAT
WAKE
I
Wake Output High Leakage Current
Wake Low Output Voltage
V
WAKE
= 3V
ꢁA
V
V
WAKE
I
= 3mA
0.4
1
WAKE
I
PG_DCDC Output High Leakage Current
PG_DCDC Output Low Voltage
PG_DCDC Threshold Voltage
V
= 3V
ꢁA
V
PG_DCDC
PG_DCDC
PG_DCDC
V
I
= 3mA
0.1
–8
0.4
PG_DCDC
V
(Note 13)
%
THPG_DCDC
Pushbutton Timing Parameters
t
t
t
t
t
t
t
t
t
t
t
t
t
ON Low Time to PBSTAT Low
ON High to PBSTAT High
WAKE High
50
900
400
5
ms
ꢁs
ON_PBSTAT1
ON_PBSTAT2
ON_WAKE
PBSTAT Low > t
PBSTAT_PW
ON Low Time to WAKE High
ON Low to Hard Reset
WAKE Low > t
ms
PWR_ONBK2
Hard Reset = All Supplies Disabled
4.2
40
5.8
60
Seconds
ms
ON_HR
PBSTAT Minimum Pulse Width
WAKE High from USB or Wall Present
WAKE High to Buck1 Enable
PWR_ON High to WAKE High
PWR_ON Low to WAKE Low
PWR_ON Power-Up Blanking
PWR_ON Power-Down Blanking
Bucks in Regulation to PG_DCDC High
Bucks Disabled to PG_DCDC Low
50
100
5
PBSTAT_PW
WAKE_EXTP
WAKE_DCDC
PWR_ONH
PWR_ONL
WAKE Low > t
WAKE Low > t
WAKE Low > t
WAKE High > t
ms
PWR_ONBK2
PWR_ONBK2
PWR_ONBK2
PWR_ONBK1
μs
50
50
5
ms
ms
WAKE Rising Until PWR_ON Low Recognized
WAKE Falling Until PWR_ON High Recognized
All Bucks Within PG_DCDC Threshold Voltage
All Bucks Disabled
Seconds
Seconds
ms
PWR_ONBK1
PWR_ONBK2
PG_DCDCH
PG_DCDCL
1
230
44
ꢁs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3577E/LTC3577E-1 are guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 3: This IC includes over temperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperatures will exceed 110°C when over temperature protection is
active. Continuous operation above the specified maximum operating
junction temperature may result in device degradation or failure.
3577f
9
LTC3577/LTC3577-1
ELECTRICAL CHARACTERISTICS
Note 4: V is the greater of V , V
or BAT.
Note 10: FB high, not switching.
CC
BUS OUT
Note 5: Total input current is the sum of quiescent current, I
, and
BUSQ
Note 11: Measured with the LDO running unity gain with output tied to
feedback pin.
measured current given by V
/R
• (h
+ 1).
CLPROG CLPROG
CLPROG
Note 6: h
with indicated PROG resistor.
Note 7: The current limit features of this part are intended to protect the
IC from short term or intermittent fault conditions. Continuous operation
above the specified maximum pin current rating may result in device
degradation or failure.
is expressed as a fraction of measured full charge current
Note 12: Dropout voltage is the minimum input to output voltage
differential needed for an LDO to maintain regulation at a specified output
current. When an LDO is in dropout, its output voltage will be equal to
C/10
V
IN
– V
.
DROP
Note 13: PG_DCDC threshold is expressed as a percentage difference from
the Buck1-3 regulation voltages. The threshold is measured from Buck1-3
output rising.
Note 8: The serial port is tested at rated operating frequency. Timing
parameters are tested and/or guaranteed by design.
Note 14: I
is the sum of V and V current due to LED driver.
OUT IN3
VOUT_LED
Note 9: V
not in UVLO.
Note 15: The I
specifications represent the total battery load assuming
OUT
BATQ
V
, V
, V
and V are tied directly to V
.
INLDO1 INLDO2 IN12
IN3
OUT
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified
Input Supply Current
vs Temperature
Input Supply Current
Battery Drain Current
vs Temperature
vs Temperature (Suspend Mode)
400
350
300
250
200
150
100
50
0.10
0.08
0.06
0.04
0.02
0
0.8
NO LOAD ON SUPPLIES, LDOS AND LED
V
= 5V
V
= 5V
BUS
BUS
BOOST DISABLED. V
BUS
= 3.8V,
1x MODE
BAT
0.7
0.6
V
= 0V
PON STATE
PULSE-SKIPPING MODE
0.5
0.4
0.3
0.2
0.1
PON STATE
Burst Mode OPERATION
POFF STATE
HARD RESET STATE
0
0
–50
0
25
50
75 100 125
–25
–25
0
50
75 100 125
–50 –25
0
25
50
75
125
–50
25
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3577 G03
3577 G01
3577 G02
Input Current Limit
vs Temperature
Charge Current vs Temperature
(Thermal Regulation)
Input RON vs Temperature
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
300
280
260
240
220
180
160
140
120
100
0
600
500
400
300
V
R
= 5V
CLPROG
I
= 400mA
BUS
OUT
= 2.1k
10x MODE
V
= 4.5V
BUS
V
= 5V
BUS
5x MODE
V
= 5.5V
BUS
200
100
0
V
= 5V
BUS
1x MODE
10x MODE
R
= 2k
PROG
–50
0
25
50
75 100 125
–25
–50
0
25
50
75 100 125
–50
25
50
75
100 125
–25
–25
0
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3577 G04
3577 G05
3577 G06
3577f
10
LTC3577/LTC3577-1
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified
Battery Current and Voltage
vs Time
Battery Regulation (Float) Voltage
vs Temperature
LTC3577 IBAT vs VBAT
600
500
400
300
200
100
0
600
500
400
300
200
100
0
6
5
4
3
2
1
0
4.24
4.22
4.20
4.18
4.16
4.14
4.12
4.10
4.08
4.06
4.04
R
R
V
= 2.1k
CLPROG
PROG
I
= 2mA
BAT
= 2k
CHRG
LTC3577
= 5V
BUS
10x MODE
V
BAT
RISING V
BAT
FALLING V
BAT
SAFETY
TIMER
TERMINATION
LTC3577-1
1450mAhr
CELL
C/10
V
= 5V
BUS
PROG
R
R
= 2k
= 2k
I
BAT
CLPROG
2.0
2.4
2.8
3.2
(V)
3.6
4.0
4.4
0
2
3
4
5
6
–25
0
50
75 100 125
1
–50
25
TIME (HOUR)
V
TEMPERATURE (°C)
BAT
3577 G09
3577 G07
3577 G08
Forward Voltage vs Ideal Diode
Current (No External FET)
Forward Voltage vs Ideal Diode
Current (with Si2333DS External FET)
LTC3577-1 IBAT vs VBAT
600
500
400
300
200
100
0
40
35
30
25
0.25
0.20
0.15
0.10
R
R
V
= 2.1k
V
A
= 0V
BUS
V
V
T
= 3.8V
= 0V
CLPROG
PROG
BUS
BAT
BUS
= 2k
T
= 25°C
V
= 3.2V
BAT
= 5V
10x MODE
= 25°C
A
V
= 3.6V
BAT
V
= 4.2V
BAT
20
15
FALLING V
BAT
RISING V
10
5
BAT
0.05
0
0
2.0
2.8
3.2
(V)
3.6
4.0
4.4
0
0.2
0.4
I
0.8
1.0
2.4
0.6
(A)
0
0.4
0.6
(A)
0.8
1.0
1.2
0.2
V
I
BAT
BAT
BAT
3577 G10
3577 G12
3577 G11
Input Connect Waveform
Input Disconnect Waveform
Switching from 1x to 5x Mode
V
V
BUS
5V/DIV
BUS
5V/DIV
ILIM0/ILIM1
5V/DIV
V
V
OUT
OUT
5V/DIV
5V/DIV
I
I
I
BUS
BUS
BUS
0.5A/DIV
0.5A/DIV
0.5A/DIV
I
I
I
BAT
0.5A/DIV
BAT
BAT
0.5A/DIV
0.5A/DIV
3577 G13
3577 G14
3577 G15
V
= 3.75V
1ms/DIV
V
= 3.75V
1ms/DIV
V
= 3.75V
= 50mA
1ms/DIV
BAT
OUT
BAT
OUT
BAT
OUT
I
= 100mA
I
= 100mA
I
R
R
= 2k
R
R
= 2k
R
R
= 2k
CLPROG
CLPROG
CLPROG
= 2k
= 2k
= 2k
PROG
PROG
PROG
3577f
11
LTC3577/LTC3577-1
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified
Switching from Suspend Mode to
5x Mode
WALL Connect Waveform
WALL Disconnect Waveform
ILIM0
5V/DIV
WALL
5V/DIV
WALL
5V/DIV
V
V
OUT
V
OUT
OUT
5V/DIV
5V/DIV
5V/DIV
I
I
WALL
I
WALL
BUS
0.5A/DIV
0.5A/DIV
0.5A/DIV
I
I
I
BAT
BAT
BAT
0.5A/DIV
0.5A/DIV
0.5A/DIV
3577 G16
3577 G18
3577 G17
V
I
= 3.75V
= 100mA
= 2k
100μs/DIV
V
I
= 3.75V
= 100mA
= 2k
1ms/DIV
V
I
= 3.75V
= 100mA
= 2k
1ms/DIV
BAT
OUT
BAT
OUT
R
PROG
BAT
OUT
R
R
CLPROG
PROG
R
= 2k
PROG
ILIM1 = 5V
Oscillator Frequency
vs Temperature
Step-Down Switching Regulator 1
3.3V Output Efficiency vs IOUT1
Step-Down Switching Regulator 2
1.8V Output Efficiency vs IOUT2
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
100
90
100
90
Burst Mode
OPERATION
Burst Mode
OPERATION
V
V
= 3.8V
IN
80
80
V
= 5V
IN
70
70
PULSE-SKIPPING MODE
60
50
60
50
PULSE-SKIPPING MODE
40
30
20
10
0
40
30
20
10
0
V
= 2.9V
IN
= 2.7V
IN
V
= 3.3V
V
OUT2
= 1.8V
OUT1
V
IN12
V
IN12
= 3.8V
= 5V
V
= 3.8V
= 5V
IN12
IN12
V
–50
0
25
50
75 100 125
–25
0.01
0.1
1
I
10
(mA)
100
1000
0.01
0.1
1
I
10
(mA)
100
1000
TEMPERATURE (°C)
OUT
OUT
3577 G20
3577 G21
3577 G19
Step-Down Switching Regulator
Step-Down Switching Regulator 3
1.2V Output Efficiency vs IOUT3
Step-Down Switching Regulator 3
2.5V Output Efficiency vs IOUT3
Short-Circuit Current vs Temperature
1500
1400
1300
1200
1100
1000
900
100
90
100
90
Burst Mode
OPERATION
Burst Mode
OPERATION
80
80
800mA BUCK
500mA BUCK
70
70
PULSE-SKIPPING MODE
60
50
60
50
PULSE-SKIPPING MODE
40
30
20
10
0
40
30
20
10
0
800
700
V
= 2.5V
V
= 1.2V
OUT3
OUT3
V
INx
V
INx
= 3.8V
= 5V
V
V
= 3.8V
= 5V
V
V
= 3.8V
= 5V
IN3
IN3
600
IN3
IN3
500
–25
0
50
75 100 125
–50
25
0.01
0.1
1
I
10
(mA)
100
1000
0.01
0.1
1
I
10
(mA)
100
1000
TEMPERATURE (°C)
OUT
OUT
3577 G23
3577 G22
3577 G24
3577f
12
LTC3577/LTC3577-1
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified
Step-Down Switching Regulator
Output Transient (Burst Mode
Operation)
Step-Down Switching Regulator
Output Transient (Pulse-Skipping
Mode)
Step-Down Switching Regulator
Switch Impedance vs Temperature
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
V
V
= 3.2V
OUT1
INX
V
OUT1
50mV/DIV
(AC)
50mV/DIV
(AC)
500mA
PMOS
V
OUT2
V
OUT2
500mA
NMOS
50mV/DIV
(AC)
50mV/DIV
(AC)
V
OUT3
V
OUT3
100mV/DIV
(AC)
100mV/DIV
(AC)
800mA PMOS
800mA NMOS
500mA
500mA
I
I
OUT3
OUT3
5mA
5mA
3577 G25
3577 G26
V
I
= 3.3V
= 10mA
= 1.8V
= 20mA
= 1.2V
50μs/DIV
V
I
= 3.3V
= 30mA
= 1.8V
= 20mA
= 1.2V
50μs/DIV
OUT1
OUT1
OUT1
OUT1
V
V
OUT2
OUT2
OUT2
OUT2
0
I
I
–50 –25
0
25
125
50
75 100
V
V
V
V
OUT3
OUT
OUT3
OUT
TEMPERATURE (°C)
= V
= 3.8V
= V
= 3.8V
BAT
BAT
3577 G27
800mA Step-Down Switching
Regulator Feedback Voltage
vs Output Current
500mA Step-Down Switching
Regulator Feedback Voltage
vs Output Current
LDO Load Step
0.85
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
0.85
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
LDO1
50mV/DIV
(AC)
Burst Mode
OPERATION
Burst Mode
OPERATION
LDO2
20mV/DIV
(AC)
PULSE-SKIPPING MODE
PULSE-SKIPPING MODE
100mA
I
OUT1
5mA
3577 G30
LDO1 = 1.2V
LDO2 = 2.5V
20μs/DIV
3.8V
5V
3.8V
5V
I
= 40mA
LDO2
V
= V
= 3.8V
0.1
1
10
100
1000
0.1
1
10
100
1000
OUT
BAT
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3577 G29
3577 G28
OVP Connection Waveform
OVP Protection Waveform
OVP Reconnection Waveform
V
BUS
5V/DIV
V
V
BUS
BUS
5V/DIV
5V/DIV
OVGATE
5V/DIV
OVGATE
5V/DIV
OVGATE
5V/DIV
OVP
INPUT
OVP
INPUT
VOLTAGE
5V TO 10V
STEP 5V/DIV
OVP
INPUT
VOLTAGE
0V TO 5V
STEP 5V/DIV
VOLTAGE
10V TO 5V
STEP 5V/DIV
3577 G31
3577 G32
3577 G33
500μs/DIV
500μs/DIV
500μs/DIV
3577f
13
LTC3577/LTC3577-1
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified
OVSENS Quiescent Current
vs Temperature
Rising Overvoltage Threshold
vs Temperature
OVGATE vs OVSENS
6.280
6.275
6.270
6.265
6.260
6.255
12
10
37
35
33
31
29
27
OVSENS CONNECTED
TO INPUT THROUGH
6.2k RESISTOR
V
= 5V
OVSENS
8
6
4
2
0
–40
–15
10
35
60
85
0
2
4
6
8
–40
–15
10
35
60
85
INPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3577 G35
3577 G36
3577 G34
Input and Battery Current
vs Load Current
LED Driver Efficiency 10 LEDs
LED Driver Efficiency 8 LEDs
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
55
50
600
500
400
300
200
100
0
R
R
= 2k
PROG
CLPROG
I
= 2k
IN
I
LOAD
I
BAT
(CHARGING)
3V
3V
3.6V
4.2V
4.8V
5.5V
3.6V
4.2V
4.8V
5.5V
I
BAT
(DISCHARGING)
WALL = 0V
100
–100
0
2
4
6
8
I
10 12 14 16 18 20
(mA)
400
600
0
2
4
6
8
10 12 14 16 18 20
(mA)
LED
0
200
300
(mA)
500
I
I
LED
LOAD
3577 G38
3577 G37
35773 G39
LED Boost Current Limit
vs Temperature
LED Driver Efficiency 6 LEDs
LED Driver Efficiency 4 LEDs
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
55
50
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
3V
3V
3.6V
4.2V
4.8V
5.5V
3.6V
4.2V
4.8V
5.5V
0
2
4
6
8
I
10 12 14 16 18 20
(mA)
0
2
4
6
8
I
10 12 14 16 18 20
(mA)
LED
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
3577 G42
LED
3577 G40
3577 G41
3577f
14
LTC3577/LTC3577-1
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise specified
LED Boost Maximum Duty Cycle
vs Temperature
DAC Code vs LED Current
LED Boost Start-Up Transient
70
60
96.6
96.5
96.4
96.3
96.2
96.1
96.0
95.9
95.8
60dB = 20mA
0dB = 20μA
R
= 20k
LED_FS
I
LED
10mA/DIV
50
40
30
20
10
V
BOOST
20V/DIV
I
L
200mA/DIV
3V
3.6V
4.2V
5.5V
0
95.7
3577 G44
40
30
DAC CODE
60
70
2ms/DIV
0
10
20
50
–50 –25
0
25
125
50
75 100
TEMPERATURE (°C)
3577 G43
3577 G45
LED PWM
vs Constant Current Efficiency
Battery Discharge
vs Temperature
Too Hot BAT Discharge
200
180
160
140
120
100
80
90
80
70
60
50
40
30
20
10
0
200
V
V
< V
TOO_HOT
= 0V
NTC
BUS
175
150
V
V
= 5V
= 0V
BUS
BUS
125
100
75
MAX PWM
CONSTANT
CURRENT
60
50
V
V
= 4.1V
BAT
NTC
40
< V
TOO_HOT
5x MODE
25
20
I
= 0mA
VOUT
0
0
1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01
50 60
70
80
90 100 110 120
3.8
3.9
4.0
(V)
4.2
4.1
LED CURRENT (A)
V
TEMPERATURE (°C)
BAT
3577 G46
3577 G47
3577 G48
PIN FUNCTIONS
I
, I
(Pins 1, 2): Input Current Control Pins. I
SW3 (Pin 5): Power Transmission (Switch) Pin for Step-
Down Switching Regulator 3 (Buck 3).
LIM0 LIM1
LIM0
and I
control the input current limit. See Table 1 in
LIM1
“USB PowerPath Controller” section. Both pins are pulled
low by a weak current sink.
V
(Pin6):PowerInputforStep-DownSwitchingRegula-
IN3
tor 3. This pin should be connected to V
.
OUT
LED_FS (Pin 3): A resistor between this pin and ground
FB3 (Pin 7): Feedback Input for Step-Down Switching
Regulator 3 (Buck 3). This pin servos to a fixed voltage
of 0.8V when the control loop is complete.
sets the full-scale output current of the I
pin.
LED
WALL (Pin 4): Wall Adapter Present Input. Pulling this
pin above 4.3V will disconnect the power path from V
BUS
OVSENSE (Pin 8): Overvoltage Protection Sense Input.
to V . The ACPR pin will also be pulled low to indicate
OUT
OVSENSE should be connected through a 6.2k resistor
that a wall adapter has been detected.
to the input power connector and the drain of an external
3577f
15
LTC3577/LTC3577-1
PIN FUNCTIONS
N-channel MOS pass transistor. When the voltage on
this pin exceeds a preset level, the OVGATE pin will be
pulled to GND to disable the pass transistor and protect
downstream circuitry.
WAKE(Pin17):Open-DrainOutput.TheWAKEpinindicates
theoperatingstateofthebuckDC/DCs.IfWAKEisHi-Z,the
BUCK DC/DCs are enabled and either up or powering up.
A low on WAKE indicates that the buck DC/DCs are either
powered down or are powering down. See “Pushbutton
Interface Operation” section for more information.
LED_OV(Pin9):Aresistorbetweenthispinandtheboosted
LED backlight voltage sets the overvoltage limit on the
boostoutput.Iftheboostvoltageexceedstheprogrammed
limit the LED boost converter will be disabled.
SW(Pins18,19,20):PowerTransmission(Switch)Pinfor
LEDBoostConverter.See“LEDBacklight/BoostOperation”
2
section for circuit hook-up and component selection. I C
2
DV (Pin 10): Supply Voltage for I C Lines. This pin sets
CC
2
is used to control LED driver enable. I C default is LED
the logic reference level of the LTC3577. A UVLO circuit on
driver off.
the DV pin forces all registers to all 0s whenever DV
CC
CC
is <1V. Bypass to GND with a 0.1μF capacitor.
PG_DCDC (Pin 21): Open-Drain Output. PG_DCDC goes
highimpedance230msafterallbuckDC/DCsareinregula-
tion (within 8% of final value).
2
SDA (Pin 11): I C Data Input. Serial data is shifted one bit
per clock to control the LTC3577. The logic level for SDA
is referenced to DV .
I
(Pin 22): Series LED Backlight Current Sink Output.
CC
LED
This pin is connected to the cathode end of the series LED
backlightstring.ThecurrentdrawnthroughtheseriesLEDs
can be programmed via a 6-bit 60dB DAC and dimmed via
2
SCL (Pin 12): I C Clock Input. The logic level for SCL is
referenced to DV .
CC
2
OVGATE (Pin 13): Overvoltage Protection Gate Output.
Connect OVGATE to the gate pin of an external N-channel
MOS pass transistor. The source of the transistor should
an internal 4-bit PWM function. I C is used to control LED
2
driver enable, brightness, gradation (soft on/soft off). I C
default is LED driver off, current = 0mA.
be connected to V
and the drain should be connected
BUS
V
(Pin 23): Input Supply of Low Dropout Linear
INLDO1
to the product’s DC input connector. In the absence of an
overvoltage condition, this pin is connected to an internal
charge pump capable of creating sufficient overdrive to
fully enhance this transistor. If an overvoltage condition
is detected, OVGATE is brought rapidly to GND to prevent
damage. OVGATE works in conjunction with OVSENSE to
provide this protection.
Regulator1(LDO1).Thispinshouldbebypassedtoground
with a 1μF or greater ceramic capacitor.
LDO2_FB (Pin 24): Feedback Voltage Input for Low Drop-
out Linear Regulator 2 (LDO2). LDO2 output voltage is
set using an external resistor divider between LDO2 and
LDO2_FB.
PWR_ON (Pin 14): Logic Input Used to Keep Buck
DC/DCs Enabled After Power-Up. May also be used to
enable the buck DC/DCs directly (sequence = buck1 →
buck2 → buck3). See “Pushbutton Interface Operation”
section for more information.
FB2 (Pin 25): Feedback Input for Step-Down Switching
Regulator 2 (Buck 2). This pin servos to a fixed voltage
of 0.8V when the control loop is complete.
FB1 (Pin 26): Feedback Input for Step-Down Switching
Regulator 1 (Buck 1). This pin servos to a fixed voltage
of 0.8V when the control loop is complete.
ON (Pin 15): Pushbutton Input. A weak internal pull-up
forces ON high when left floating. A normally open push-
button is connected from ON to ground to force a low
state on this pin.
LDO1_FB (Pin 27): Feedback Voltage Input for Low Drop-
out Linear Regulator 1 (LDO1). LDO1 output voltage is
set using an external resistor divider between LDO1 and
LDO1_FB.
PBSTAT (Pin 16): Open-drain output is a de-bounced
and buffered version of ON to be used for processor
interrupts.
LDO1(Pin28):OutputofLowDropoutLinearRegulator 1.
This pin must be bypassed to ground with a 1μF or greater
ceramic capacitor.
3577f
16
LTC3577/LTC3577-1
PIN FUNCTIONS
LDO2(Pin29):OutputofLowDropoutLinearRegulator 2.
This pin must be bypassed to ground with a 1μF or greater
ceramic capacitor.
either deliver system power to V
through the ideal
OUT
diode or be charged from the battery charger.
V
(Pin39):OutputVoltageofthePowerPathController
OUT
V
(Pin 30): Input Supply of Low Dropout Linear
and Input Voltage of the Battery Charger. The majority of
INLDO2
Regulator2(LDO2).Thispinshouldbebypassedtoground
the portable product should be powered from V . The
OUT
with a 1μF or greater ceramic capacitor.
LTC3577 will partition the available power between the
external load on V
and the internal battery charger.
OUT
SW2 (Pin 31): Power Transmission (Switch) Pin for Step-
Down Switching Regulator 2 (Buck 2).
Priority is given to the external load and any extra power
is used to charge the battery. An ideal diode from BAT to
V
(Pin 32): Power Input for Step-Down Switching
IN12
V
ensuresthatV ispoweredeveniftheloadexceeds
OUT
OUT
Regulators 1 and 2. This pin will generally be connected
the allotted input current from V
or if the V
power
BUS
BUS
to V
.
OUT
source is removed. V
impedance multilayer ceramic capacitor.
should be bypassed with a low
OUT
SW1 (Pin 33): Power Transmission (Switch) Pin for Step-
Down Switching Regulator 1 (Buck 1).
V
(Pin 40): USB Input Voltage. V
will usually be
BUS
BUS
connected to the USB port of a computer or a DC output
NTCBIAS (Pin 34): Output Bias Voltage for NTC. A
resistor from this pin to the NTC pin will bias the NTC
thermistor.
wall adapter. V
should be bypassed with a low imped-
BUS
ance multilayer ceramic capacitor.
ACPR(Pin41):WallAdapterPresentOutput(ActiveLow).
A low on this pin indicates that the wall adapter input com-
parator has had its input pulled above its input threshold
(typically 4.3V). This pin can be used to drive the gate of
NTC (Pin 35): The NTC pin connects to a battery’s therm-
istor to determine if the battery is too hot or too cold
to charge. If the battery’s temperature is out of range,
charging is paused until it drops back into range. A low
drift bias resistor is required from NTCBIAS to NTC and
a thermistor is required from NTC to ground.
an external P-channel MOSFET to provide power to V
from a power source other than a USB port.
OUT
V (Pin 42): High Voltage Buck Regulator Control Pin.
C
PROG (Pin 36): Charge Current Program and Charge
Current Monitor Pin. Connecting a resistor from PROG
to ground programs the charge current:
This pin can be used to drive the V pin of an approved
C
external high voltage buck switching regulator. The V pin
C
isdesignedtoworkwiththeLT®3480, LT3653andLT3505.
Consult factory for additional approved high voltage buck
regulators. See “External HV Buck Control through the VC
Pin” section for operating information.
1000V
RPROG
ICHG
=
A
( )
If sufficient input power is available in constant current
mode, this pin servos to 1V. The voltage on this pin always
represents the actual charge current.
CLPROG (Pin 43): Input Current Program and Input
Current Monitor Pin. A resistor from CLPROG to ground
determines the upper limit of the current drawn from the
IDGATE (Pin 37): Ideal Diode Gate Connection. This
pin controls the gate of an optional external P-channel
MOSFET transistor used to supplement the internal ideal
diode. The source of the P-channel MOSFET should be
V
pin (i.e., the input current limit). A precise fraction
BUS
of the input current, h
, is sent to the CLPROG
CLPROG
pin. The input PowerPath delivers current until the
CLPROGpinreaches2V(10xmode),1V(5xmode)or0.2V
connected to V
and the drain should be connected to
OUT
(1x mode). Therefore, the current drawn from V
will
BUS
BAT. It is important to maintain high impedance on this
pin and minimize all leakage paths.
be limited to an amount given by h
In USB applications the resistor R
to no less than 2.1k.
and R
.
CLPROG
CLPROG
CLPROG
should be set
BAT (Pin 38): Single Cell Li-Ion Battery Pin. Depending
on available power and load, a Li-Ion battery on BAT will
3577f
17
LTC3577/LTC3577-1
PIN FUNCTIONS
CHRG (Pin 44): Open-Drain Charge Status Output. The
CHRG pin indicates the status of the battery charger. If
CHRG is high then the charger is near the float voltage
(charge current less than 1/10th programmed charge cur-
rent)orchargingiscompleteandchargerisdisabled.Alow
on CHRG indicates that the charger is enabled. For more
information see the “Charge Status Indication” section.
Exposed Pad (Pin 45): Ground. The exposed package pad
is ground and must be soldered to the PC board for proper
functionality and for maximum heat transfer.
BLOCK DIAGRAM
8
13
OVGATE
4
41
ACPR
42
OVSENS
WALL
V
C
OVERVOLTAGE
PROTECTON
WALL
DETECT
V
C
CONTROL
V
V
OUT
BUS
40
43
39
37
+
–
IDGATE
INPUT
CURRENT
LIMIT
CC/CV
CHARGER
IDEAL
DIODE
CLPROG
–
+
NTCBIAS
NTC
15mV
34
35
BATTERY
TEMP
BAT
OVERTEMP BATTERY
SAFETY DISCHARGE
38
36
MONITOR
PROG
HRST UVLO
I
I
LIM0
1
2
I
V
IN12
LIM
LIM1
EN 500mA, 2.25MHz
BUCK REGULATOR
32
33
LOGIC
SW1
FB1
CHRG
44
0.8V
CHRGE
STATUS
PG
26
31
PWR_ON
WAKE
ON
14
17
15
16
EN 500mA, 2.25MHz
BUCK REGULATOR
PUSH-
BUTTON
INPUT
SW2
FB2
0.8V
PBSTAT
PG
25
6
DV
CC
10
11
12
2
V
IN3
SDA
SCL
I C
EN 800mA, 2.25MHz
BUCK REGULATOR
LOGIC
SW3
5
0.8V
PG_DCDC
21
230ms
FALLING
DELAY
FB3
PG
7
V
INLD01
EN
23
LED_OV
0.8V
21
40V LED BACKLIGHT
BOOST CONVERTER
SW
18,19,20
LDO1
28
27
150mA
LDO1
LDO1_FB
DAC
V
INLD02
EN
30
I
0.8V
0.8V
LED
22
3
LDO2
LED_FS
29
24
150mA
LDO2
LDO2_FB
GND
45
3577 BD
3577f
18
LTC3577/LTC3577-1
OPERATION
PowerPath OPERATION
that input current does not violate the USB average input
current specification. The ideal diode from BAT to V
guarantees that ample power is always available to V
OUT
OUT
Introduction
even if there is insufficient or absent power at V . The
BUS
The LTC3577 is a highly integrated power management
IC that features:
LTC3577 also has the ability to receive power from a wall
adapter or other non-current-limited power source. Such
– PowerPath controller
– Battery charger
– Ideal diode
– Input overvoltage protection
– Pushbutton controller
– Three step-down switching regulators
– High voltage buck regulator V controller
– Two low dropout linear regulators
– 40V LED backlight controller
a power supply can be connected to the V
pin of the
OUT
LTC3577 through an external device such as a power
Schottky or FET as shown in Figure 1. The LTC3577 has
the unique ability to use the output, which is powered by
an external supply, to charge the battery while provid-
ing power to the load. A comparator on the WALL pin is
configured to detect the presence of the wall adapter and
shut off the connection to the USB. This prevents reverse
C
conductionfromV
toV
whenawalladapterispres-
C
OUT
BUS
ent. The LTC3577 provides a V output pin which can be
used to drive the V pin of an external high voltage buck
C
DesignedspecificallyforUSBapplications,thePowerPath
controller incorporates a precision input current limit
which communicates with the battery charger to ensure
switchingregulatorsuchastheLT3480,LT3653orLT3505
to provide power to the V
pin. The V control circuitry
OUT
C
adjusts the regulation point of the switching regulator to
FROM AC ADAPTER (OR HIGH VOLTAGE BUCK OUTPUT)
42
V
C
OPTIONAL CONTROL
FOR HIGH VOLTAGE BUCK REGS
LT3480, LT3481 OR LT3505
4.3V
(RISING)
3.2V
–
+
(FALLING)
WALL
ACPR
4
41
+
–
75mV (RISING)
25mV (FALLING)
+
–
FROM
USB
ENABLE
V
BUS
V
V
OUT
OUT
40
39
37
SYSTEM
LOAD
USB CURRENT LIMIT
IDEAL
DIODE
OPTIONAL
EXTERNAL
IDEAL DIODE
PMOS
+
–
IDGATE
CONSTANT CURRENT
CONSTANT VOLTAGE
BATTERY CHARGER
–
+
15mV
BAT
BAT
38
+
Li-Ion
3577 F01
Figure 1. Simplified PowerPath Block Diagram
3577f
19
LTC3577/LTC3577-1
OPERATION
a small voltage above the BAT pin voltage. This control
method provides a high input voltage, high efficiency
battery charger and PowerPath function.
current. When a programming resistor is connected from
CLPROG to GND, the voltage on CLPROG represents the
input current:
The LTC3577 also includes a pushbutton input to control
the three synchronous step-down switching regulators
and system reset. The three 2.25MHz constant frequency
current mode step-down switching regulators provide
500mA, 500mA and 800mA each and support 100% duty
cycle operation as well as Burst Mode operation for high
efficiency at light load. No external compensation compo-
nents are required for the switching regulators.
VCLPROG
IVBUS =IBUSQ
+
•hCLPROG
RCLPROG
and h are given in the Electrical Char-
CLPROG
where I
BUSQ
acteristics table.
The input current limit is programmed by the I
and
LIM0
I
pins. The LTC3577 can be configured to limit input
LIM1
current to one of several possible settings as well as be
deactivated (USB suspend). The input current limit will be
set by the appropriate servo voltage and the resistor on
CLPROG according to the following expression:
The onboard LED backlight boost circuitry can drive up
to 10 series LEDs and includes versatile digital dimming
2
2
via the I C input. The I C input also controls two 150mA
low dropout (LDO) linear regulators.
0.2V
RCLPROG
1V
RCLPROG
2V
RCLPROG
All regulators can be programmed for a minimum output
voltage of 0.8V and can be used to power a microcon-
troller core, microcontroller I/O, memory or other logic
circuitry.
IVBUS =IBUSQ
IVBUS =IBUSQ
IVBUS =IBUSQ
+
+
+
•hCLPROG 1x Mode
(
)
•hCLPROG 5x Mode
(
)
USB PowerPath Controller
•hCLPROG 10x Mode
(
)
The input current limit and charge control circuits of the
LTC3577 are designed to limit input current as well as
control battery charge current as a function of I
OUT
step-downswitchingregulators, twoLDOs, LEDbacklight
and the battery charger.
.
Under worst-case conditions, the USB specification for
VOUT
V
drives the combination of the external load, the three
average input current will not be violated with an R
CLPROG
resistor of 2.1k or greater. Table 1 shows the available
settings for the I
and I
pins:
LIM0
LIM1
If the combined load does not exceed the programmed
Table 1. Controlled Input Current Limit
inputcurrentlimit,V
willbeconnectedtoV
through
OUT
BUS
I
I
I
BUS(LIM)
LIM1
LIM0
an internal 200mꢀ P-channel MOSFET. If the combined
load at V exceeds the programmed input current limit,
the battery charger will reduce its charge current by the
amountnecessarytoenabletheexternalloadtobesatisfied
while maintaining the programmed input current. Even if
the battery charge current is set to exceed the allowable
USB current, the average input current USB specification
0
0
100mA (1x)
1A (10x)
OUT
0
1
1
1
0
1
Suspend
500mA (5x)
Notice that when I
is high and I
is low, the input
LIM0
LIM1
current limit is set to a higher current limit for increased
charging and current availability at V . This mode is
OUT
will not be violated. Furthermore, load current at V
OUT
typically used when there is a higher power, non-USB
will always be prioritized and only excess available cur-
source available at the V
pin.
BUS
rent will be used to charge the battery. The current out
of the CLPROG pin is a fraction (1/h ) of the V
CLPROG BUS
3577f
20
LTC3577/LTC3577-1
OPERATION
Ideal Diode from BAT to V
Using the WALL Pin to Detect the Presence of an
External Power Source
OUT
The LTC3577 has an internal ideal diode as well as a con-
trollerforanoptionalexternalidealdiode.Boththeinternal
and the external ideal diodes respond quickly whenever
The WALL input pin can be used to identify the presence
of an external power source (particularly one that is not
V
drops below BAT. If the load increases beyond the
subject to a fixed current limit like the USB V
input).
OUT
BUS
input current limit, additional current will be pulled from
Typically, such a power supply would be a 5V wall adapter
output or the low voltage output of a high voltage buck
regulator (specifically, LT3480, LT3653 or LT3505). When
the wall adapter output (or buck regulator output) is con-
nected directly to the WALL pin, and the voltage exceeds
the battery via the ideal diodes. Furthermore, if power to
V
(USB) or V
(external wall power or high voltage
BUS
OUT
regulator) is removed, then all of the application power
will be provided by the battery via the ideal diodes. The
ideal diodes are fast enough to keep V
from dropping
the WALL pin threshold, the USB power path (from V
OUT
BUS
significantly with just the recommended output capacitor
(seeFigure2).Theidealdiodeconsistsofaprecisionampli-
fier that enables an on-chip P-channel MOSFET whenever
to V ) will be disconnected. Furthermore, the ACPR pin
OUT
will be pulled low. In order for the presence of an external
power supply to be acknowledged, both of the following
conditions must be satisfied:
the voltage at V
is approximately 15mV (V ) below
OUT
FWD
the voltage at BAT. The resistance of the internal ideal
diode is approximately 200mꢀ. If this is sufficient for
the application, then no external components are neces-
sary. However, if lower resistance is needed, an external
1. The WALL pin voltage must exceed approximately
4.3V.
2. The WALL pin voltage must be greater than 75mV
above the BAT pin voltage.
P-channel MOSFET can be added from BAT to V . The
OUT
IDGATE pin of the LTC3577 drives the gate of the external
The input power path (between V
and V ) is re-
OUT
BUS
P-channel MOSFET for automatic ideal diode control. The
enabled and the ACPR pin is pulled high when either of
source of the MOSFET should be connected to V
and
OUT
the following conditions is met:
the drain should be connected to BAT. Capable of driving a
1nFload,theIDGATEpincancontrolanexternalP-channel
MOSFET having extremely low on-resistance.
1. The WALL pin voltage falls to within 25mV of the BAT
pin voltage.
2. The WALL pin voltage falls below 3.2V.
Each of these thresholds is suitably filtered in time to
prevent transient glitches on the WALL pin from falsely
triggering an event.
4.0V
V
3.8V
3.6V
OUT
500mA
External HV Buck Control Through the V Pin
C
I
0
BAT
The WALL, ACPR and V pins can be used in conjunction
C
–500mA
1A
with an external high voltage buck regulator such as the
I
LT3480, LT3505 or LT3653 to provide power directly to the
VOUT
LOAD
0A
V
pin as shown in Figures 3 to 5 (Consult factory for
3577 F02
OUT
V
V
= 3.8V
= 5V
10μs/DIV
BAT
BUS
5x MODE
complete list of approved high voltage buck regulators).
When the WALL pin voltage exceeds 4.3V, V pin control
C
= 10μF
C
OUT
circuitry is enabled and drives the V pin of the LT3480,
C
Figure 2. Ideal Diode Transient Response
LT3505 or LT3653. The V pin control circuitry is designed
C
so that no compensation components are required on the
V node. The voltage at the V
pin is regulated to the
C
OUT
larger of (BAT + 300mV) or 3.6V as shown in Figure 6.
3577f
21
LTC3577/LTC3577-1
OPERATION
HV
IN
4
2
3
8V TO 38V
(TRANSIENTS
TO 60V)
V
BOOST
LT3480
IN
0.47μF
68nF
150k
4.7μF
6.8μH
5
RUN/SS SW
R
T
10
DFLS240L
499k
100k
40.2k
22μF
1
8
7
6
NC
NC
BD
FB
GND
V
C
11
9
LT3480
Si2333DS
UP TO
2A
HIGH VOLTAGE
BUCK CIRCUITRY
V
OUT
42
4
41
C
OUT
V
WALL ACPR
C
39
37
38
V
OUT
IDGATE
BAT
Si2333DS
(OPT)
LTC3577
BAT
+
Li-Ion
3577 F03
Figure 3. LT3480 Buck Control Using VC (800kHz Switching)
1N4148
3
4
1
2
HV
IN
V
BOOST
SW
IN
8V TO 36V
0.1μF
68nF
20k
150k
1μF
LT3505
6.8μH
SHDN
49.9k
10.0k
BZT52C16T
MBRM140
10μF
806k
6
R
7
T
FB
C
GND
5, 9
V
8
LT3505
Si2333DS
UP TO
1.2A
HIGH VOLTAGE
BUCK CIRCUITRY
V
OUT
42
4
41
C
OUT
V
WALL ACPR
C
39
37
38
V
OUT
IDGATE
BAT
Si2333DS
(OPT)
LTC3577
BAT
+
Li-Ion
3577 F04
Figure 4. LT3505 Buck Control Using VC (2.2MHz Switching with Frequency Foldback)
3577f
22
LTC3577/LTC3577-1
OPERATION
HV
IN
1
7
8
7.5V TO 30V
(TRANSIENTS
TO 60V)
V
BOOST
SW
IN
0.1μF
10V
4.7μH
4.7μF
60V
DFLS240L
LT3653
324k
4
9
6
5
I
I
SENSE
LIM
GND
V
V
OUT
HVOK
C
3
2
UP TO
1.2A
HIGH VOLTAGE
BUCK CIRCUITRY
V
OUT
42
4
41
C
OUT
V
WALL ACPR
C
39
37
38
V
OUT
IDGATE
BAT
Si2333DS
(OPT)
LTC3577
BAT
+
Li-Ion
3577 F05
Figure 5. LT3653 Buck Control Using VC
5.0
4.5
4.0
3.5
I
I
I
= 0.0A
= 0.75A
= 1.5A
O
O
O
3.0
2.5
BAT
2.5
3
3.5
4
4.5
3577 F06
BAT (V)
Figure 6. VOUT Voltage vs Battery Voltage (LT3480)
5.0
4.5
4.0
3.5
3.0
I
I
= 0.0A
= 0.6A
O
O
BAT
2.5
2.5
3
3.5
4
4.5
3577 F07
BAT (V)
Figure 7. VOUT Voltage vs Battery Voltage (LT3505)
3577f
23
LTC3577/LTC3577-1
OPERATION
The feedback network of the high voltage buck regulator
should be set to generate an output voltage higher than
4.4V (be sure to include the output voltage tolerance
V
Undervoltage Lockout (UVLO) and Undervoltage
BUS
Current Limit (UVCL)
An internal undervoltage lockout circuit monitors V
and keeps the input current limit circuitry off until V
BUS
BUS
of the buck regulator). The V control of the LTC3577
C
overdrives the local V control of the external high volt-
C
rises above the rising UVLO threshold (3.8V) and at least
50mV above V . Hysteresis on the UVLO turns off the
age buck. Therefore, once the V control is enabled, the
C
OUT
output voltage is set independent of the buck regulator
inputcurrentlimitifV
dropsbelow3.7Vor50mVbelow
BUS
feedback network.
V
. When this happens, system power at V
will be
OUT
OUT
This technique provides a significant efficiency advantage
over the use of a 5V buck to drive the battery charger. With
drawn from the battery via the ideal diode. To minimize the
possibility of oscillation in and out of UVLO when using
resistive input supplies, the input current limit is reduced
a simple 5V buck output driving V , battery charger
OUT
efficiency is approximately:
as V
falls below 4.45V (typ).
BUS
VBAT
5V
Battery Charger
ηCHARGER = ηBUCK
•
The LTC3577 includes a constant-current/constant-volt-
age battery charger with automatic recharge, automatic
termination by safety timer, low voltage trickle charging,
bad cell detection and thermistor sensor input for out of
temperature charge pausing. When a battery charge cycle
begins, the battery charger first determines if the battery
where η
is the efficiency of the high voltage buck
BUCK
regulator and 5V is the output voltage of the buck regu-
lator. With a typical buck efficiency of 87% and a typical
battery voltage of 3.8V, the total battery charger efficiency
is approximately 66%. Assuming a 1A charge current,
this works out to nearly 2W of power dissipation just to
charge the battery!
is deeply discharged. If the battery voltage is below V
,
TRKL
typically2.85V,anautomatictricklechargefeaturesetsthe
battery charge current to 10% of the programmed value.
If the low voltage persists for more than one-half hour, the
batterychargerautomaticallyterminates.Oncethebattery
voltageisabove2.85V,thebatterychargerbeginscharging
infullpowerconstantcurrentmode. Thecurrentdelivered
With the V control technique, battery charger efficiency
is approximately:
C
VBAT
ηCHARGER = ηBUCK
•
0.3V + VBAT
to the battery will try to reach 1000V/R
. Depending
PROG
on available input power and external load conditions, the
battery charger may or may not be able to charge at the
full programmed rate. The external load will always be
prioritized over the battery charge current. The USB cur-
rent limit programming will always be observed and only
additional current will be available to charge the battery.
When system loads are light, battery charge current will
be maximized.
With the same assumptions as above, the total battery
charger efficiency is approximately 81%. This example
worksouttojust900mWofpowerdissipation.Forapplica-
tions, component selection and board layout information
beyond those listed here please refer to the respective
high voltage buck regulator data sheet.
Suspend Mode
When I
is pulled low and I
is pulled high the
LIM0
LIM1
Charge Termination
LTC3577 enters suspend mode to comply with the USB
specification. In this mode, the power path between V
The battery charger has a built-in safety timer. When the
battery voltage approaches the float voltage, the charge
currentbeginstodecreaseastheLTC3577entersconstant
voltage mode. Once the battery charger detects that it
has entered constant voltage mode, the four hour safety
BUS
and V
BUS
is put in a high impedance state to reduce the
OUT
V
input current to 50ꢁA. If no other power source
is available to drive WALL and V , the system load
connected to V
connected to BAT.
OUT
is supplied through the ideal diodes
OUT
3577f
24
LTC3577/LTC3577-1
OPERATION
timer is started. After the safety timer expires, charging
of the battery will terminate and no more current will be
delivered.
Thermal Regulation
To prevent thermal damage to the IC or surrounding
components, an internal thermal feedback loop will
automatically decrease the programmed charge current
if the die temperature rises to approximately 110°C.
Thermal regulation protects the LTC3577 from excessive
temperature due to high power operation or high ambient
thermal conditions and allows the user to push the limits
of the power handling capability with a given circuit board
design without risk of damaging the LTC3577 or external
components. The benefit of the LTC3577 thermal regula-
tion loop is that charge current can be set according to
actual conditions rather than worst-case conditions with
the assurance that the battery charger will automatically
reduce the current in worst-case conditions.
Automatic Recharge
After the battery charger terminates, it will remain off
drawing only microamperes of current from the battery.
If the portable product remains in this state long enough,
thebatterywilleventuallyselfdischarge.Toensurethatthe
battery is always topped off, a charge cycle will automati-
cally begin when the battery voltage falls below V
RECHRG
(typically 4.0V for LTC3577-1 and 4.1V for LTC3577). In
the event that the safety timer is running when the battery
voltage falls below V
, the timer will reset back to
RECHRG
zero. To prevent brief excursions below V
from re-
RECHRG
setting the safety timer, the battery voltage must be below
formorethan1.3ms. Thechargecycleandsafety
V
Charge Status Indication
RECHRG
timerwillalsorestartiftheV
UVLOcycleslowandthen
BUS
TheCHRGpinindicatesthestatusofthebatterycharger.An
open-drainoutput,theCHRGpincandriveanindicatorLED
throughacurrentlimitingresistorforhumaninterfacingor
simply a pull-up resistor for microprocessor interfacing.
When charging begins, CHRG is pulled low and remains
lowforthedurationofanormalchargecycle.Whencharg-
ing is complete, i.e., the charger enters constant voltage
mode and the charge current has dropped to one-tenth
of the programmed value, the CHRG pin is released (high
impedance). The CHRG pin does not respond to the C/10
threshold if the LTC3577 is in input current limit. This
preventsfalseend-of-chargeindicationsduetoinsufficient
power available to the battery charger. Even though charg-
ing is stopped during an NTC fault, the CHRG pin will stay
low indicating that charging is not complete.
high (e.g., V , is removed and then replaced).
BUS
Charge Current
The charge current is programmed using a single resistor
from PROG to ground. 1/1000th of the battery charge cur-
rent is delivered to PROG which will attempt to servo to
1.000V. Thus, the battery charge current will try to reach
1000 times the current in the PROG pin. The program
resistor and the charge current are calculated using the
following equations:
1000V
ICHG
1000V
RPROG
RPROG
=
, ICHG =
Ineithertheconstant-currentorconstant-voltagecharging
modes, the PROG pin voltage will be proportional to the
actual charge current delivered to the battery. Therefore,
the actual charge current can be determined at any time
by monitoring the PROG pin voltage and using the fol-
lowing equation:
Battery Charger Stability Considerations
The LTC3577’s battery charger contains both a constant-
voltageandaconstant-currentcontrolloop.Theconstant-
voltage loop is stable without any compensation when a
battery is connected with low impedance leads. Excessive
lead length, however, may add enough series inductance
to require a bypass capacitor of at least 1μF from BAT to
GND. Furthermore, a 4.7μF capacitor in series with a 0.2Ω
to 1Ω resistor from BAT to GND is required to keep ripple
voltage low when the battery is disconnected.
VPROG
RPROG
IBAT
=
•1000
In many cases, the actual battery charge current, I , will
BAT
belowerthanI
duetolimitedinputcurrentavailableand
CHG
prioritization with the system load drawn from V
.
OUT
3577f
25
LTC3577/LTC3577-1
OPERATION
High value, low ESR multilayer ceramic chip capacitors
reduce the constant-voltage loop phase margin, possibly
resulting in instability. Ceramic capacitors up to 22μF may
beusedinparallelwithabattery,butlargerceramicsshould
be decoupled with 0.2Ω to 1Ω of series resistance.
NTCBIAS
34
LTC3577
NTC BLOCK
0.76 • NTCBIAS
R
NOM
–
+
100k
TOO_COLD
NTC
35
In constant-current mode, the PROG pin is in the feed-
back loop rather than the battery voltage. Because of the
additional pole created by any PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the battery
charger is stable with program resistor values as high
as 25k. However, additional capacitance on this node
reduces the maximum allowed program resistor. The pole
frequency at the PROG pin should be kept above 100kHz.
Therefore, if the PROG pin has a parasitic capacitance,
R
NTC
100k
–
+
TOO_HOT
0.35 • NTCBIAS
0.26 • NTCBIAS
+
–
BATTERY
OVERTEMP
3577 F08
C
, the following equation should be used to calculate
PROG
the maximum resistance value for R
:
PROG
Figure 8. Typical NTC Thermistor Circuit
1
To improve safety and reliability the battery voltage is re-
ducedwhenthebatterytemperaturebecomesexcessively
high. When the resistance of the NTC thermistor drops to
about 0.35 times the value of R25 or approximately 35k
(for a Vishay “Curve 1” thermistor, this corresponds to
approximately 50°C) the NTC enables circuitry to moni-
tor the battery voltage. If the battery voltage is above the
battery discharge threshold (about 3.9V) then the battery
discharge circuitry is enabled and draws about 140mA
RPROG
≤
2π •100kHz •CPROG
NTC Thermistor and Battery Voltage Reduction
The battery temperature is measured by placing a nega-
tive temperature coefficient (NTC) thermistor close to
the battery pack. To use this feature connect the NTC
thermistor, R , between the NTC pin and ground and a
NTC
NOM
bias resistor, R
, from NTCBIAS to NTC. R
should
NOM
from the battery when V
= 0V and about 180mA when
BUS
be a 1% resistor with a value equal to the value of the
chosen NTC thermistor at 25°C (R25). The LTC3577 will
pause charging when the resistance of the NTC thermistor
drops to 0.54 times the value of R25 or approximately 54k
(for a Vishay “Curve 1” thermistor, this corresponds to
approximately 40°C). If the battery charger is in constant
voltage (float) mode, the safety timer also pauses until the
thermistor indicates a return to a valid temperature. As the
temperature drops, the resistance of the NTC thermistor
rises. The LTC3577 is also designed to pause charging
when the value of the NTC thermistor increases to 3.17
times the value of R25. For a Vishay “Curve 1” thermistor
this resistance, 317k, corresponds to approximately 0°C.
The hot and cold comparators each have approximately
3°Cofhysteresistopreventoscillationaboutthetrippoint.
The typical NTC circuit is shown in Figure 8.
V
=5V.Asthebatteryvoltageapproachesthedischarge
BUS
threshold the discharge current is linearly reduced until
it reaches 0mA at which point the discharge circuitry is
disabled. Reducing the discharge current in this fashion
keeps the circuit from causing oscillations on V
to battery ESR.
due
BAT
When the charger is disabled an internal watchdog timer
samples the NTC thermistor for about 150μs every 150ms
and will enable the battery monitoring circuitry if the bat-
tery temperature exceeds the NTC TOO_HOT threshold.
If adding a capacitor to the NTC pin for filtering the time
constant must be much less than 150μs so that the NTC
pin can settle to its final value during the sampling period.
A time constant of less than 10μs is recommended. Once
the battery monitoring circuitry is enabled it will remain
enabledandmonitoringthebatteryvoltageuntilthebattery
3577f
26
LTC3577/LTC3577-1
OPERATION
temperature falls back below the discharge temperature
threshold. The battery discharge circuitry is only enabled
if the battery voltage is greater than the battery discharge
threshold.
NTCBIAS
34
LTC3577
NTC BLOCK
0.76 • NTCBIAS
R
NOM
–
105k
TOO_COLD
NTC
35
+
Alternate NTC Thermistors and Biasing
R1
The LTC3577 provides temperature qualified charging if
a grounded thermistor and a bias resistor are connected
to NTC. By using a bias resistor whose value is equal to
the room temperature resistance of the thermistor (R25)
the upper and lower temperatures are pre-programmed
to approximately 40°C and 0°C, respectively (assuming
a Vishay “Curve 1” thermistor).
12.7k
–
R
100k
NTC
TOO_HOT
0.35 • NTCBIAS
+
+
0.26 • NTCBIAS
BATTERY
OVERTEMP
–
The upper and lower temperature thresholds can be ad-
justed by either a modification of the bias resistor value
or by adding a second adjustment resistor to the circuit.
If only the bias resistor is adjusted, then either the upper
or the lower threshold can be modified but not both. The
other trip point will be determined by the characteristics
of the thermistor. Using the bias resistor in addition to an
adjustmentresistor,boththeupperandthelowertempera-
ture trip points can be independently programmed with
the constraint that the difference between the upper and
lower temperature thresholds cannot decrease. Examples
of each technique follows.
3577 F09
Figure 9. NTC Thermistor Circuit with Additional Bias Resistor
The trip points for the LTC3577’s temperature qualifica-
tion are internally programmed at 0.35 • V
for the hot
NTC
threshold and 0.76 • V
for the cold threshold.
NTC
Therefore, the hot trip point is set when:
RNTC|HOT
•NTCBIAS= 0.35•NTCBIAS
RNOM +RNTC|HOT
NTC thermistors have temperature characteristics which
areindicatedonresistance-temperatureconversiontables.
TheVishay-DalethermistorNTHS0603N011-N1003F,used
in the following examples, has a nominal value of 100k
and follows the Vishay “Curve 1” resistance-temperature
characteristic.
and the cold trip point is set when:
RNTC|COLD
•NTCBIAS= 0.76 •NTCBIAS
RNOM +RNTC|COLD
SolvingtheseequationsforR
in the following:
andR
results
NTC|COLD
NTC|HOT
In the following explanation, this notation is used.
R25 = Value of the thermistor at 25°C
R
= 0.538 • R
NTC|HOT
NOM
R
R
= Value of thermistor at the cold trip point
NTC|COLD
and
= Value of the thermistor at the hot trip point
NTC|HOT
R
= 3.17 • R
NTC|COLD
NOM
r
r
= Ratio of R
to R25
COLD
NTC|COLD
By setting R
equal to R25, the above equations result
NOM
= 0.538 and r
in r
= 3.17. Referencing these ratios
= Ratio of R
to R25
HOT
COLD
HOT
NTC|HOT
to the Vishay Resistance-Temperature Curve 1 chart gives
a hot trip point of about 40°C and a cold trip point of about
0°C. The difference between the hot and cold trip points
R
= Primary thermistor bias resistor (see Figure 9)
NOM
R1 = Optional temperature range adjustment resistor
(see Figure 9)
is approximately 40°C.
3577f
27
LTC3577/LTC3577-1
OPERATION
By using a bias resistor, R
, different in value from R25,
NOM
Overvoltage Protection (OVP)
the hot and cold trip points can be moved in either direc-
tion. The temperature span will change somewhat due to
the non-linear behavior of the thermistor. The following
equations can be used to easily calculate a new value for
the bias resistor:
The LTC3577 can protect itself from the inadvertent ap-
plication of excessive voltage to V
or WALL with just
BUS
two external components: an N-channel FET and a 6.2k
resistor. The maximum safe overvoltage magnitude will
be determined by the choice of the external NMOS and
its associated drain breakdown voltage.
rHOT
0.538
rCOLD
RNOM
=
=
•R25
•R25
The overvoltage protection module consists of two pins.
Thefirst,OVSENS,isusedtomeasuretheexternallyapplied
voltagethroughanexternalresistor.Thesecond,OVGATE,
is an output used to drive the gate pin of an external FET.
The voltage at OVSENS will be lower than the OVP input
RNOM
3.17
where r
and r
are the resistance ratios at the de-
HOT
COLD
sired hot and cold trip points. Note that these equations
are linked. Therefore, only one of the two trip points can
be chosen, the other is determined by the default ratios
designed in the IC.
voltage by (I
• 6.2k) due to the OVP circuit’s qui-
OVSENS
escent current. The OVP input will be 200mV to 400mV
higher than OVSENS under normal operating conditions.
When OVSENS is below 6V, an internal charge pump will
drive OVGATE to approximately 1.88 • OVSENS. This will
enhance the N-channel FET and provide a low impedance
Consider an example where a 60°C hot trip point is
desired. From the Vishay Curve 1 R-T characteristics,
connection to V
or WALL which will, in turn, power the
r
is 0.2488 at 60°C. Using the above equation, R
BUS
HOT
NOM
, the cold
LTC3577. If OVSENS should rise above 6V (6.35V OVP
input) due to a fault or use of an incorrect wall adapter,
OVGATE will be pulled to GND, disabling the external FET
to protect downstream circuitry. When the voltage drops
below 6V again, the external FET will be re-enabled.
should be set to 46.4k. With this value of R
NOM
trip point is about 16°C. Notice that the span is now 44°C
rather than the previous 40°C. This is due to the decrease
in “temperature gain” of the thermistor as absolute tem-
perature increases.
In an overvoltage condition, the OVSENS pin will be
clamped at 6V. The external 6.2k resistor must be
sized appropriately to dissipate the resultant power.
For example, a 1/10W 6.2k resistor can have at most
√PMAX • 6.2kꢀ = 24V applied across its terminals. With
the 6V at OVSENS, the maximum overvoltage magnitude
that this resistor can withstand is 30V. A 1/4W 6.2k resis-
tor raises this value to 45V.
The upper and lower temperature trip points can be inde-
pendentlyprogrammedbyusinganadditionalbiasresistor
as shown in Figure 9. The following formulas can be used
to compute the values of R
and R1:
NOM
rCOLD –rHOT
RNOM
=
•R25
2.714
R1= 0.536 •RNOM –rHOT •R25
For example, to set the trip points to 0°C and 45°C with
a Vishay Curve 1 thermistor choose
The charge pump output on OVGATE has limited output
drive capability. Care must be taken to avoid leakage on
this pin, as it may adversely affect operation.
3.266 – 0.4368
RNOM
=
•100k =104.2k
2.714
Dual Input Overvoltage Protection
the nearest 1% value is 105k.
It is possible to protect both V
and WALL from
BUS
overvoltage damage with several additional components,
as shown in Figure 10. Schottky diodes D1 and D2 pass
the larger of V1 and V2 to R1 and OVSENS. If either V1 or
R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k
the nearest 1% value is 12.7k. The final solution is shown
in Figure 9 and results in an upper trip point of 45°C and
a lower trip point of 0°C.
V2exceeds6VplusV
,OVGATEwillbepulledto
F(SCHOTTKY)
GND and both the WALL and USB inputs will be protected.
3577f
28
LTC3577/LTC3577-1
OPERATION
MN1
MN2
MP1
MN1
USB/WALL
ADAPTER
WALL
V1
V
BUS
C1
D1
OVGATE
LTC3577
LTC3577
R1
500k
R2
6.2k
OVGATE
OVSENS
V2
V
BUS
D2
D1
C1
3577 F11
D1: 5.6V ZENER
MP1: Si2323DS, BVDSS = 20V
R1
OVSENS
V
V
POSITIVE PROTECTION UP TO BVDSS OF MN1
NEGATIVE PROTECTION UP TO BVDSS OF MP1
BUS
BUS
3577 F10
Figure 10. Dual Input Overvoltage Protection
Figure 11. Dual Polarity Voltage Protection
Each input is protected up to the drain-source breakdown,
BVDSS, of MN1 and MN2. R1 must also be rated for the
power dissipated during maximum overvoltage. See the
“Overvoltage Protection” section for an explanation of
this calculation. Table 2 shows some NMOS FETs that are
suitable for overvoltage protection.
V
INLDOx
MP
0
1
LDOxEN
LDOx
LDOx
OUTPUT
R1
C
OUT
LDOx_FB
0.8V
Table 2. Recommended Overvoltage FETs
NMOS FET
Si1472DH
BVDSS
30V
R
PACKAGE
SC70-6
SOT-23
SOT-23
SOT-23
SOT-23
ON
R2
GND
82mΩ
60mΩ
65mΩ
80mΩ
35mΩ
Si2302ADS
Si2306BDS
Si2316BDS
IRLML2502
20V
3577 F12
30V
Figure 12. LDO Application Circuit
30V
20V
The LDOs are further disabled if V
falls below the V
OUT
OUT
UVLO threshold and cannot be enabled until the UVLO
Reverse Input Voltage Protection
condition is removed.
The LTC3577 can also be easily protected against the
application of reverse voltage as shown in Figure 10. D1
and R1 are necessary to limit the maximum VGS seen by
MP1 during positive overvoltage events. D1’s breakdown
voltage must be safely below MP1’s BVGS. The circuit
shown in Figure 11 offers forward voltage protection up
to MN1’s BVDSS and reverse voltage protection up to
MP1’s BVDSS.
WhendisabledallLDOcircuitryispoweredoffleavingonly
a few nanoamps of leakage current on the LDO supply.
TheLDOoutputsareindividuallypulledtogroundthrough
internal resistors when disabled.
The power good status bits of LDO1 and LDO2 are avail-
able in I C through the read-back registers PGLDO[1] and
PGLDO[2] for LDO1 and LDO2 respectively. The power
good comparators for both LDOs are sampled when the
I C port receives the correct I C read address.
2
2
2
LOW DROPOUT LINEAR REGULATOR OPERATION
LDO Operation and Voltage Programming
Figure 12 shows the LDO application circuit. The full-
scale output voltage for each LDO is programmed using
a resistor divider from the LDO output (LDO1 or LDO2)
connected to the feedback pins (LDO1_FB or LDO2_FB)
such that:
The LTC3577 contains two 150mA adjustable output LDO
regulators. To enable the LDOs write a 1 to the LDO1EN
2
and/or LDO2EN I C registers. The LDOs can be disabled
three ways: 1) Write a 0 to the LDO1EN and LDO2EN
R1
R2
⎛
⎞
registers; 2) Bring DV below the DV undervoltage
CC
CC
VLDOx = 0.8V •
+1
⎜
⎝
⎟
⎠
threshold; 3) Enter the power-down pushbutton state.
3577f
29
LTC3577/LTC3577-1
OPERATION
Forstability,eachLDOoutputmustbebypassedtoground
thespecifiedoperatingrangeasoperationisnotguaranteed
beyond this range.
with a minimum 1ꢁF ceramic capacitor (C ).
OUT
LDO Operating as a Current Limited Switch
Output Voltage Programming
The LDO can be used as a current limited switch by simply
connecting the LDOx_FB input to ground. In this case
Figure 13 shows the step-down switching regulator ap-
plication circuit. The full-scale output voltage for each
step-down switching regulator is programmed using a
resistor divider from the step-down switching regulator
output connected to the feedback pins (FB1, FB2 and
FB3) such that:
the LDOx output will be pulled up to V
through the
INLDOx
LDO’s internal current limit (about 300mA). Enabling the
2
LDO via the I C interface effectively connects LDOx and
V
, while disabling the LDO disconnected LDOx
INLDOx
INLDOx
from V
.
R1
R2
⎛
⎞
⎠
VOUTx = 0.8V •
+1
⎜
⎝
⎟
STEP-DOWN SWITCHING REGULATOR OPERATION
Introduction
Typical values for R1 are in the range of 40k to 1M. The
capacitor C cancels the pole created by feedback resis-
FB
The LTC3577 includes three 2.25MHz constant frequency
current mode step-down switching regulators providing
500mA, 500mA and 800mA each. All step-down switch-
ing regulators can be programmed for a minimum output
voltageof0.8Vandcanbeusedtopoweramicrocontroller
core, microcontroller I/O, memory or other logic circuitry.
All step-down switching regulators support 100% duty
cycle operation (low dropout mode) when the input volt-
age drops very close to the output voltage and are also
capable of Burst Mode operation for highest efficiencies
at light loads. Burst Mode operation is individually select-
able for each step-down switching regulator through the
tors and the input capacitance of the FB pin and also helps
to improve transient response for output voltages much
greater than 0.8V. A variety of capacitor sizes can be used
for C but a value of 10pF is recommended for most ap-
FB
plications. Experimentation with capacitor sizes between
2pF and 22pF may yield improved transient response.
V
IN
EN
MP
MN
L
SWx
FBx
MODE
SLEW
PWM
CONTROL
V
OUTx
C
OUT
C
R1
FB
2
I C register bits BK1BRST, BK2BRST and BK3BRST. The
step-down switching regulators also include soft-start to
limit inrush current when powering on, short-circuit cur-
rent protection, and switch node slew limiting circuitry
to reduce EMI radiation. No external compensation com-
ponents are required for the switching regulators. The
regulators are sequenced up and down together through
the pushbutton interface (see “Pushbutton Interface”
section for more information). It is recommended that
0.8V
R2
GND
3577 F13
Figure 13. Step-Down Switching Regulator Application Circuit
PG_DCDC Operation
The PG_DCDC pin is an open-drain output used to indi-
cate that all step-down switching regulators are enabled
and have reached their final regulation voltage. A 230ms
delay is included from the time all switching regulators
reach 92% of their regulation value to allow a system
controller ample time to reset itself. PG_DCDC may be
used as a power-on reset to a microprocessor powered
the step-down switching regulator input supplies (V
IN12
and V ) be connected to the system supply pin (V ).
IN3
OUT
This is recommended because the undervoltage lockout
circuit on the V pin (V UVLO) disables the step-
OUT
OUT
down switching regulators when the V
voltage drops
OUT
below the V
UVLO threshold. If driving the step-down
OUT
switching regulator input supplies from a voltage other
than V the regulators should not be operated outside
by the step-down switching regulators. PG_DCDC is an
OUT
3577f
30
LTC3577/LTC3577-1
OPERATION
open-drain output and requires a pull-up resistor to an
appropriate power source. Optimally the pull-up resistor
is connected to one of the step-down switching regulator
output voltages so that power is not dissipated while the
regulators are disabled.
control loop to minimize both noise and switching losses.
While operating in Burst Mode operation, the output
capacitor is charged to a voltage slightly higher than the
regulation point. The step-down switching regulator then
goes into sleep mode, during which the output capacitor
provides the load current. In sleep mode, most of the
switching regulator’s circuitry is powered down, helping
conserve battery power. When the output voltage drops
below a pre-determined value, the step-down switching
regulator circuitry is powered on and another burst cycle
begins. The sleep time decreases as the load current
increases. Beyond a certain load current point (about
1/4 rated output load current) the step-down switching
regulators will switch to a low noise constant frequency
PWM mode of operation, much the same as pulse-skip-
ping operation at high loads.
Operating Modes
The step-down switching regulators include two possible
operatingmodestomeetthenoise/powerneedsofavariety
of applications. In pulse-skipping mode, an internal latch
is set at the start of every cycle, which turns on the main
P-channel MOSFET switch. During each cycle, a current
comparator compares the peak inductor current to the
output of an error amplifier. The output of the current
comparatorresetstheinternallatch,whichcausesthemain
P-channel MOSFET switch to turn off and the N-channel
MOSFET synchronous rectifier to turn on. The N-channel
MOSFET synchronous rectifier turns off at the end of the
2.25MHz cycle or if the current through the N-channel
MOSFET synchronous rectifier drops to zero. Using this
method of operation, the error amplifier adjusts the peak
inductor current to deliver the required output power. All
necessary compensation is internal to the step-down
switching regulator requiring only a single ceramic output
capacitorforstability.Atlightloadsinpulse-skippingmode,
the inductor current may reach zero on each pulse which
will turn off the N-channel MOSFET synchronous rectifier.
In this case, the switch node (SW1, SW2 or SW3) goes
high impedance and the switch node voltage will “ring.”
Thisisdiscontinuousoperation,andisnormalbehaviorfor
a switching regulator. At very light loads in pulse-skipping
mode, the step-down switching regulators will automati-
cally skip pulses as needed to maintain output regulation.
For applications that can tolerate some output ripple at low
output currents, Burst Mode operation provides better ef-
ficiency than pulse-skipping at light loads. The step-down
switching regulators allow mode transition on-the-fly,
providing seamless transition between modes even under
load. This allows the user to switch back and forth between
modes to reduce output ripple or increase low current ef-
ficiency as needed. Burst Mode operation is individually
selectable for each step-down switching regulator through
2
the I C register bits BK1BRST, BK2BRST and BK3BRST.
Shutdown
The step-down switching regulators are shut down when
the pushbutton circuitry is in the power-down, power
off or hard reset states. In shutdown all circuitry in the
step-down switching regulator is disconnected from
the switching regulator input supply leaving only a few
nanoamps of leakage current. The step-down switching
regulatoroutputsareindividuallypulledtogroundthrough
internal 10k resistors on the switch pin (SW1, SW2 or
SW3) when in shutdown.
At high duty cycle (V
approaching V ) it is possible
OUTX
INX
for the inductor current to reverse at light loads causing
the stepped down switching regulator to operate continu-
ously. When operating continuously, regulation and low
noise output voltage are maintained, but input operating
current will increase to a few milliamps.
Dropout Operation
In Burst Mode operation, the step-down switching regula-
tors automatically switch between fixed frequency PWM
operation and hysteretic control as a function of the load
current. At light loads the step-down switching regulators
control the inductor current directly and use a hysteretic
It is possible for a step-down switching regulator’s input
voltagetoapproachitsprogrammedoutputvoltage(e.g.,a
battery voltage of 3.4V with a programmed output voltage
of 3.3V). When this happens, the PMOS switch duty cycle
3577f
31
LTC3577/LTC3577-1
OPERATION
increasesuntilitisturnedoncontinuouslyat100%.Inthis
dropoutcondition,therespectiveoutputvoltageequalsthe
regulator’s input voltage minus the voltage drops across
the internal P-channel MOSFET and the inductor.
Figures 14 and 15 show the efficiency and power loss
graph for Buck3 programmed for 1.2V and 2.5V outputs.
Note that the power loss curves remain fairly constant for
both graphs yet changing the slew rate has a larger effect
on the 1.2V output efficiency. This is mainly because for
a given output current the 2.5V output is delivering more
than 2x the power than the 1.2V output. Efficiency will
always decrease and show more variation to slew rate as
the programmed output voltage is decreased.
Soft-Start Operation
Soft-startisaccomplishedbygraduallyincreasingthepeak
inductor current for each step-down switching regulator
overa500ꢁsperiod.Thisallowseachoutputtoriseslowly,
helping minimize inrush current required to charge up the
switching regulator output capacitor. A soft-start cycle
occurs whenever a given switching regulator is enabled.
A soft-start cycle is not triggered by changing operating
modes. This allows seamless output transition when
actively changing between operating modes.
Low Supply Operation
An undervoltage lockout circuit on V
(V
UVLO)
OUT
OUT
shutsdownthestep-downswitchingregulatorswhenV
OUT
drops below about 2.7V. It is recommended that the step-
down switching regulator input supplies (V
, V ) be
IN12 IN3
connected to the power path output (V ) directly. This
OUT
Slew Rate Control
UVLO prevents the step-down switching regulators from
operating at low supply voltages where loss of regula-
tion or other undesirable operation may occur. If driving
the step-down switching regulator input supplies from
The step-down switching regulators contain new patent
pending circuitry to limit the slew rate of the switch node
(SW1, SW2 and SW3). This new circuitry is designed to
transition the switch node over a period of a few nanosec-
onds, significantly reducing radiated EMI and conducted
supply noise while maintaining high efficiency. Since
slowingtheslewrateoftheswitchnodescausesefficiency
loss,theslewrateofthestep-downswitchingregulatorsis
a voltage other than the V
pin, the regulators should
OUT
not be operated outside the specified operating range as
operation is not guaranteed beyond this range.
Inductor Selection
2
adjustableviatheI CregistersSLEWCTL1andSLEWCTL2.
Many different sizes and shapes of inductors are available
fromnumerousmanufacturers.Choosingtherightinductor
fromsuchalargeselectionofdevicescanbeoverwhelming,
butfollowingafewbasicguidelineswillmaketheselection
ThisallowstheusertooptimizeefficiencyorEMIasneces-
sary with four different slew rate settings. The power-up
default is the fastest slew rate (highest efficiency) setting.
100
90
80
70
60
50
40
30
20
10
1.00E+00
1.00e-01
1.00E-02
1.00E-03
1.00E-04
1.00E-05
100
90
80
70
60
50
40
30
20
10
1.00E+00
1.00e-01
1.00E-02
1.00E-03
1.00E-04
1.00E-05
Burst Mode
OPERATION
IN
Burst Mode
OPERATION
IN
V
= 3.8V
V
= 3.8V
SW[1:0] =
SW[1:0] =
00
01
10
11
00
01
10
11
0
0
1.00E-05
1.00E-0.3
1.00E-01
1.00E-05
1.00E-0.3
1.00E-01
I
(mA)
I
(mA)
OUT3
OUT3
3577 F14
3577 F15
Figure 14. VOUT3 (1.2V) Efficiency and Power Loss vs IOUT3
Figure 15. VOUT3 (2.5V) Efficiency and Power Loss vs IOUT3
3577f
32
LTC3577/LTC3577-1
OPERATION
Table 3. Recommended Inductors for Step-Down Switching Regulators
INDUCTOR TYPE
L (ꢀH)
MAX I (A)
MAX DCR (Ω)
SIZE in mm (L × W × H) MANUFACTURER
DC
DB318C
4.7
3.3
4.7
3.3
4.7
3.3
1.07
1.20
0.79
0.90
1.15
1.37
0.1
0.07
Toko
www.toko.com
3.8 × 3.8 × 1.8
3.8 × 3.8 × 1.8
3.6 × 3.6 × 1.2
3.6 × 3.6 × 1.2
3.0 × 2.8 × 1.2
3.0 × 2.8 × 1.2
0.24
D312C
0.20
0.13*
0.105*
DE2812C
CDRH3D16
CDRH2D11
4.7
3.3
4.7
3.3
4.7
0.9
1.1
0.11
0.085
0.17
Sumida
4 × 4 × 1.8
4 × 4 × 1.8
www.sumida.com
0.5
3.2 × 3.2 × 1.2
3.2 × 3.2 × 1.2
4.9 × 4.9 × 1
0.6
0.75
0.123
0.19
CLS4D09
SD3118
4.7
3.3
4.7
3.3
4.7
3.3
4.7
3.3
1.3
1.59
0.8
0.97
1.29
1.42
1.08
1.31
0.162
0.113
Cooper
www.cooperet.com
3.1 × 3.1 × 1.8
3.1 × 3.1 × 1.8
3.1 × 3.1 × 1.2
3.1 × 3.1 × 1.2
5.2 × 5.2 × 1.2
5.2 × 5.2 × 1.2
5.2 × 5.2 × 1.0
5.2 × 5.2 × 1.0
SD3112
SD12
0.246
0.165
0.117*
0.104*
0.153*
0.108*
SD10
LPS3015
4.7
3.3
1.1
1.3
0.2
0.13
Coil Craft
www.coilcraft.com
3.0 × 3.0 × 1.5
3.0 × 3.0 × 1.5
*Typical DCR
process much simpler. The step-down switching regula-
tors are designed to work with inductors in the range of
2.2ꢁH to 10ꢁH. For most applications a 4.7ꢁH inductor is
suggested for step-down switching regulators providing
up to 500mA of output current while a 3.3ꢁH inductor is
suggested for step-down switching regulators providing
upto800mA.Largervalueinductorsreduceripplecurrent,
which improves output ripple voltage. Lower value induc-
tors result in higher ripple current and improved transient
responsetime,butwillreducetheavailableoutputcurrent.
To maximize efficiency, choose an inductor with a low DC
resistance. For a 1.2V output, efficiency is reduced about
2% for 100mꢀ series resistance at 400mA load current,
and about 2% for 300mꢀ series resistance at 100mA load
current. Choose an inductor with a DC current rating at
least 1.5 times larger than the maximum load current to
ensure that the inductor does not saturate during normal
operation. If output short-circuit is a possible condition,
the inductor should be rated to handle the maximum peak
current specified for the step-down converters. Different
core materials and shapes will change the size/current
and price/current relationship of an inductor. Toroid or
shielded pot cores in ferrite or Permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
electrical characteristics. Inductors that are very thin or
have a very small volume typically have much higher core
and DCR losses, and will not give the best efficiency. The
choice of which style inductor to use often depends more
on the price versus size, performance, and any radiated
EMI requirements than on what the step-down switching
regulatorsrequirestooperate. Theinductorvaluealsohas
an effect on Burst Mode operation. Lower inductor values
will cause Burst Mode switching frequency to increase.
Table 3 shows several inductors that work well with the
step-down switching regulators. These inductors offer a
good compromise in current rating, DCR and physical
size. Consult each manufacturer for detailed information
on their entire selection of inductors.
Input/Output Capacitor Selection
LowESR(equivalentseriesresistance)ceramiccapacitors
should be used at both step-down switching regulator
outputs as well as at each step-down switching regulator
input supply. Only X5R or X7R ceramic capacitors should
be used because they retain their capacitance over wider
voltage and temperature ranges than other ceramic types.
A 10ꢁF output capacitor is sufficient for the step-down
switching regulator outputs. For good transient response
3577f
33
LTC3577/LTC3577-1
OPERATION
and stability the output capacitor for step-down switching
regulators should retain at least 4ꢁF of capacitance over
operating temperature and bias voltage. Each switching
regulator input supply should be bypassed with a 2.2ꢁF
capacitor. Consult with capacitor manufacturers for de-
tailed information on their selection and specifications
of ceramic capacitors. Many manufacturers now offer
very thin (<1mm tall) ceramic capacitors ideal for use in
height-restricted designs. Table 4 shows a list of several
ceramic capacitor manufacturers.
protection threshold is set by adjusting R1 in Figure 16
such that:
R1
BOOST(MAX)= 800mV •
+LED_OV
10•R2
where LED_OV is about 1.0V.
In the case of Figure 16 BOOST(MAX) is set to 40V for a
10-LED string.
Capacitor C3 provides soft-start, limiting the inrush cur-
rentwhentheboostconverterisfirstenabled. C3provides
Table 4. Ceramic Capacitor Manufacturers
AVX
feedback to the I pin. This feedback limits the rise time
LED
www.avxcorp.com
www.murata.com
www.t-yuden.com
www.vishay.com
www.tdk.com
of output voltage and the inrush current while the output
Murata
capacitor, C2, is charging.
Taiyo Yuden
Vishay Siliconix
TDK
The boost converter will be operated in either continuous
conduction mode, discontinuous conduction mode or
pulse-skipping mode depending on the inductor current
required for regulation.
LED BACKLIGHT/BOOST OPERATION
Introduction
C1
22μF
39
V
OUT
L1
10μH
LTC3577
The LED driver uses a constant frequency, current mode
boost converter to supply power to up to 10 series LEDs.
As shown in Figure 16 the series string of LEDs is con-
nected from the output of the boost converter (BOOST) to
LPS4018-103ML
18
19
20
D12
ZLLS400
SW
SW
SW
BOOST
R1
10M
9
LED_OV
C2
the I
pin. Under normal operation the boost converter
R2
20k
D1 D2 D3 D4 D5
D10 D9 D8 D7 D6
LED
1μF
C3
22nF
50V
3
50V
BOOST output will be driven to a voltage where the I
I
LED_FS
LED
pin regulates at 300mV. The I pin is a constant-current
22
LED
I
LED
2
sink that is programmed via I C “LED DAC register”. The
3577 F16
2
LEDcanbefurthercontrolledusingI Ctoprogrambright-
Figure 16. LED Boost Application Circuit
2
ness levels and soft turn-on/turn-off effects. See the “I C
LED Constant Current Sink
Interface” section for more information on programming
the I
current. The boost converter also includes an
LED
TheLEDdriverusesaprecisioncurrentsinktoregulatethe
LED current up to 20mA. The current sink is programmed
overvoltage protection feature to limit the BOOST output
voltage as well as variable slew rate control of the SW pin
to reduce EMI.
2
via I C “LED DAC Register” and utilizes a 6-bit 60dB expo-
nential DAC. This DAC provides accurate current control
from 20ꢁA to 20mA with approximately 1dB per step for
LED Boost Operation
I
= 20mA. The LED current can be approximated
LED(FS)
The LED boost converter is designed for very high duty
cycle operation and can boost from 3V to 40V for load
currents up to 20mA. The boost converter also features
an overvoltage protection feature to protect the output in
case of an open circuit in the LED string. The overvoltage
by the following equations:
DAC – 63
⎛
⎞
ILED =ILED(FS) •10⎜⎝ 3 •
⎟
⎠
63
(1)
0.8V
R2
ILED(FS)
=
•500
3577f
34
LTC3577/LTC3577-1
OPERATION
2
where DAC is the decimal value programmed into the I C
“LED DAC register”. For example with I = 20mA and
The full-scale LED current is set using a resistor (R2 in
Figure 16)connectedbetweentheLED_FSpinandground.
Typically R2 should be set to 20k to give 20mA of LED
current at full-scale. The resistance may be increased to
decrease the current or the resistance may be decreased
to increase the LED current. The DAC has been optimized
for best performance at 20mA full-scale. The full-scale
current may be adjusted but the accuracy of the output
current will be degraded the further it is programmed
from 20mA. The LED_FS pin is current limited and will
only source about 80μA. This protects the pin and limits
LED(FS)
DAC[5:0]=000000(0decimal)I equatesto20ꢁA,while
LED
LED
DAC[5:0]=111111(63decimal)I equatesto20mA.Asa
finalexampleDAC[5:0]=101010is42decimalandequates
to I = 2mA for I
= 20mA. The DAC approximates
LED
LED(FS)
the Equation 1 using the nominal values in Table 5. The
differences between the approximation equation and the
table are due to design of the DAC using eight linear seg-
ments that approximate the exponential function.
Table 5. LED DAC Codes to Output Current
the I
current in a case where LED_FS is shorted to
LED
DAC Codes
Output Current
20.0μA
23.5μA
27.0μA
30.5μA
34.0μA
37.6μA
41.1μA
44.6μA
48.1μA
56.5μA
65.0μA
73.4μA
81.9μA
90.3μA
98.7μA
107μA
116μA
136μA
156μA
177μA
197μA
217μA
237μA
258μA
278μA
327μA
376μA
424μA
473μA
522μA
571μA
DAC Codes
Output Current
668μA
ground, it is not recommended to program the LED cur-
rent above 25mA.
0
1
2
3
4
5
6
7
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
786μA
903μA
LED Gradation
1.02mA
1.14mA
1.26mA
1.37mA
1.49mA
1.61mA
1.89mA
2.17mA
2.45mA
2.74mA
3.02mA
3.30mA
3.58mA
3.86mA
4.54mA
5.22mA
5.90mA
6.58mA
7.26mA
7.93mA
8.61mA
9.29mA
10.8mA
12.4mA
13.9mA
15.4mA
17.0mA
18.5mA
20.0mA
The LED driver features an automatic gradation circuit.
The gradation circuit ramps the LED current up when
the LED driver is enabled and ramps the current down
when the LED driver is disabled. The DAC is enabled and
8
9
2
disabled with the EN bit of the I C “LED control register.”
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
The gradation function is automatic when enabling and
disablingtheLEDdriver;onlythegradationspeedneedsto
be programmed to use this function. The gradation speed
2
is set by the GR1 and GR2 bits of the I C “LED control
register” which allows transitions times of approximately
15ms, one-half second, one second and two seconds.
2
See the “I C Interface” section for more information. The
gradation function allows the LEDs to turn on and off
gradually as opposed to an abrupt step.
LED PWM vs Constant Current Operation
The LED driver provides both linear LED current mode as
wellasPWMLEDcurrentmode.Thesemodesareselected
2
through the MD1 and MD2 bits of the I C “LED control
register.” When both bits are 0 the LED boost converter is
in constant current (CC) mode and the I
current sink
LED
is constant whose value is set by the DAC[5:0] bits of the
2
I C “LED DAC register.”
620μA
SettingMD1to0andMD2to1selectstheLEDPWMmode.
In this mode the LED driver is pulsed using an internally
generated PWM signal. The PWM mode may be used to re-
duce the LED intensity for a given programmed current.
3577f
35
LTC3577/LTC3577-1
OPERATION
WhendimmingviaPWMtheLEDdriverandboostconverter
are both turned on and off together. This allows some
degree of additional control over the LED current, and in
somecasesmayofferamoreefficientmethodofdimming
since the boost could be operated at an optimal efficiency
point and then pulsed for the desired LED intensity.
WhenPWMmodeisenabled,asmall(2μA)standbycurrent
source is always enabled on the I pin. The purpose of
LED
thisistohavesomecurrentflowingintheLEDsatalltimes.
This helps to reduce the magnitude of the voltage swing
on the I
pin as the current is pulsed on and off.
LED
Fixed Boost Output
The PWM mode, if enabled, is set up using 3 values;
2
SettingMD1to1andMD2to0selectsthefixedhighvoltage
boost mode. This mode can be used to generate output
PWMNUM[3:0] and PWMDEN[3:0] in the I C “LED PWM
Register” and PWMCLK, set by PWMC2 and PWMC1 in
2
voltages at or greater than V . When configured as a
the I C “LED Control Register.”
OUT
boost converter the I
pin becomes the feedback pin,
LED
PWMNUM
Duty Cycle =
and will regulate the output voltage such that the voltage
on the I pin is 800mV.
PWMDEN
LED
PWMCLK
PWMDEN
Figure 17 shows a fixed 12V output generated using the
boost converter in the fixed high voltage boost mode. Any
output voltage up to 40V may be programmed by select-
ing appropriate values for the R1 and R2 voltage divider
from the equation:
Frequency =
Table 6. PWM Clock Frequency
PWMC2
PWMC1
PWMCLK
8.77kHz
4.39kHz
2.92kHz
2.19kHz
0
0
1
1
0
1
0
1
R1
R2
⎛
⎞
⎠
VBOOST = 0.8V •
+1
⎜
⎝
⎟
Values for R2 should be kept below 24.3k to keep the pole
at I beyond cross over.
UsingthePWMcontrol,a4-bitinternallygeneratedPWMis
possible as additional dimming. Using these control bits a
number of PWM duty cycles and frequencies are available
in the 100Hz to 500Hz range. This range was selected to
be below the audio range and above the frequency where
the PWM is visible.
LED
Theboostisdesignedprimarilyasahighvoltage,highduty
cycle converter. When operating with a lower boost ratio,
a larger output capacitor, 10μF, should be used. Operating
with a very low duty cycle will cause cycle skipping which
will increase ripple.
For example, given PWMC2 = 1, PWMC1 = 0, PWM-
NUM[3:0] = 0111 and PWMDEN[3:0] = 1100 then the duty
cycle will be 58.3% and PWM frequency will be 243Hz.
C1
22μF
39
V
OUT
3
L4
I
LED_FS
If PWMNUM is set to 0 then the duty cycle will be 0%
and the current sink will effectively be off. If PWMNUM
is programmed to a value larger than PWMDEN the duty
cycle will be 100% and the current sink will effectively be
constant. PWMDEN and PWMNUM may both be changed
to result in 73 different duty cycle possibilities and 41 dif-
ferent PWM frequencies between 8.77kHz and 100Hz.
10μH
LTC3577
LPS4018-103ML
D12
ZLLS400
18
19
20
SW
SW
SW
BOOST
C2
R1
10μF
10V
301k
800mV V
REF
22
9
I
LED
R2
21.5k
LED_OV
3577 F17
Figure 17. Fixed 12V/75mA Boost Output Application
3577f
36
LTC3577/LTC3577-1
OPERATION
To keep the average steady-state inductor current below
300mA the maximum output current is reduced as pro-
grammed output voltage increases. The output current
available is given by:
Diode Selection
When boosting to increasingly higher voltages, parasitic
capacitance at the switch pin becomes an increasing
large component of the switching loses. For this reason
it is important to minimize the capacitance on the switch
node. The diode selected should be sized to handle the
peak inductor current and the average output current.
At high boost voltages a diode with the lowest possible
junction capacitance will often result in a more efficient
solution than one with a lower forward drop.
VOUT(MIN)
IBOOST(MAX) = 300mA •
VBOOST
Note that the maximum boost output current must be
set by the minimum V
converter is allowed to operate down to the V
operating voltage. If the boost
OUT
UVLO
OUT
then 2.5V must be assumed as the minimum operating
voltage.
2
I C OPERATION
V
OUT
2
I C Interface
Inductor Selection
The LTC3577 may communicate with a bus master using
The LED boost converter is designed to work with a 10ꢁH
inductor. The inductor must be able to handle a peak
current of 1A and should have a low ESR value for good
efficiency. Table 7 shows several inductors that work
well with the LED boost converter. These inductors offer
a good compromise in current rating, DCR and physical
size. Consult each manufacturer for detailed information
on their entire selection of inductors.
2
the standard I C 2-wire interface. The Timing Diagram
shows the relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be high when the bus is
not in use. External pull-up resistors or current sources,
such as the LTC1694 SMBus accelerator, are required
on these lines. The LTC3577 is both a slave receiver and
2
slave transmitter. The I C control signals, SDA and SCL
are scaled internally to the DV supply. DV should be
CC
CC
connected to the same power supply as the bus pull-up
resistors.
2
The I C port has an undervoltage lockout on the DV pin.
CC
2
When DV is below approximately 1V, the I C serial port
CC
is cleared, the LTC3577 is set to its default configuration
of all zeros.
Table 7. Recommended Inductors for Boost Switching Reguators
INDUCTOR TYPE
L (ꢀH)
MAX I (A)
MAX DCR (Ω)
SIZE in mm (L × W × H) MANUFACTURER
DC
DB62LCB
10
1.22
10.5
1.28
1.1
0.118
Toko
6.2 × 6.2 × 2
4.8 × 4.8 × 1.8
5.2 × 5.2 × 1.8
4.0 × 4.0 × 1.8
www.toko.com
CDRH4D16NP-100M
SD18-100-R
10
10
10
0.155
0.158*
0.200
Sumida
www.sumida.com
Cooper
www.cooperet.com
LPS4018-103
*Typical
Coil Craft
www.coilcraft.com
3577f
37
LTC3577/LTC3577-1
OPERATION
I2C Timing Diagram
DATA BYTE A
DATA BYTE B
ADDRESS
WR
0
0
0
0
1
0
0
1
1
A7
1
A6
2
A5
3
A4
A3
A2
6
A1
7
A0
8
B7
1
B6
2
B5
3
B4
B3
B2
6
B1
7
B0
8
START
STOP
SDA
SCL
0
0
0
1
0
0
0
8
ACK
9
ACK
9
ACK
9
1
2
3
4
5
6
7
4
5
4
5
SDA
t
t
t
BUF
SU, DAT
SU, STA
t
t
t
t
LOW
HD, STA
SU, STO
HD, DAT
3577 TD
SCL
t
t
t
SP
HD, STA
HIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
t
t
f
r
2
2
I C Bus Speed
I C Acknowledge
2
The I C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3577 is written
to (write address), it acknowledges its write address as
well as the subsequent two data bytes. When it is read
from (read address), the LTC3577 acknowledges its read
address only. The bus master should acknowledge receipt
of information from the LTC3577.
2
operation when addressed from an I C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
2
I C START and STOP Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to the
LTC3577,themastermaytransmitaSTOPconditionwhich
commandstheLTC3577toactuponitsnewcommandset.
A STOP condition is sent by the master by transitioning
SDA from LOW to HIGH while SCL is HIGH. The bus is
An acknowledge (active LOW) generated by the LTC3577
letsthemasterknowthatthelatestbyteofinformationwas
received.Theacknowledgerelatedclockpulseisgenerated
by the master. The master releases the SDA line (HIGH)
during the acknowledge clock cycle. The LTC3577 pulls
down the SDA line during the write acknowledge clock
pulse so that it is a stable LOW during the HIGH period
of this clock pulse.
When the LTC3577 is read from, it releases the SDA line so
thatthemastermayacknowledgereceiptofthedata.Since
the LTC3577 only transmits one byte of data, a master not
2
then free for communication with another I C device.
2
I C Byte Format
2
acknowledging the data sent by the LTC3577 has no I C
2
Each byte sent to or received from the LTC3577 must
be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3577
most significant bit (MSB) first.
specific consequence on the operation of the I C port.
3577f
38
LTC3577/LTC3577-1
OPERATION
2
I C Slave Address
LTC3577 will remember the last input of valid data that it
received. Once all chips on the bus have been addressed
and sent valid data, a global STOP can be sent and the
LTC3577 will update its command latches with the data
that it had received.
The LTC3577 responds to a 7-bit address which has been
factory programmed to b’0001001[R/W]’. The LSB of
the address byte, known as the read/write bit, should be
0 when writing data to the LTC3577 and 1 when reading
data from it. Considering the address an eight bit word,
then the write address is 0x12 and the read address is
0x13. The LTC3577 will acknowledge both its read and
write address.
2
I C Bus Read Operation
The bus master reads the status of the LTC3577 with a
START condition followed by the LTC3577 read address. If
thereadaddressmatchesthatoftheLTC3577,theLTC3577
returns an acknowledge. Following the acknowledgement
of its read address the LTC3577 returns one bit of status
information for each of the next 8 clock cycles. A STOP
command is not required for the bus read operation.
2
I C Sub-Addressed Writing
The LTC3577 has four command registers for control
2
input. They are accessed by the I C port via a sub-
addressed writing system.
2
Each write cycle of the LTC3577 consists of exactly three
bytes.ThefirstbyteisalwaystheLTC3577’swriteaddress.
The second byte represents the LTC3577’s sub-address.
The sub address is a pointer which directs the subsequent
data byte within the LTC3577. The third byte consists of
the data to be written to the location pointed to by the sub-
address. The LTC3577 contains control registers at only
four sub-address locations: 0x00, 0x01, 0x02 and 0x03.
Writing to sub-addresses outside the four sub-addresses
listed is not recommended as it can cause data in one of
the four listed sub-addresses to be overwritten.
I C Input Data
There are 4 bytes of data that can be written to on the
LTC3577. The bytes are accessed through the sub-
addresses 0x00 to 0x03. At first power application (V
,
BUS
WALL or BAT) all bits default to 0. Additionally all bits are
cleared to 0 when DV drops below its undervoltage lock
CC
out or if the pushbutton enters the power-down (PDN1
or PDN2) state.
Table 8. LDO and Buck Control Register
LDO and BUCK
CONTROL REGISTER
ADDRESS: 00010010
SUB-ADDRESS: 00000000
2
BIT NAME
FUNCTION
I C Bus Write Operation
B0 LDO1EN
B1 LDO2EN
B2 BK1BRST
B3 BK2BRST
B4 BK3BRST
B5 SLEWCTL1
B6 SLEWCTL2
B7 N/A
Enable LDO 1
The master initiates communication with the LTC3577
with a START condition and the LTC3577’s write address.
If the address matches that of the LTC3577, the LTC3577
returns an acknowledge. The master should then deliver
the sub-address. Again the LTC3577 acknowledges and
the cycle is repeated for the data byte. The data byte is
transferred to an internal holding latch upon the return of
its acknowledge by the LTC3577. This procedure must be
repeatedforeachsub-addressthatrequiresnewdata.After
oneormorecyclesof[ADDRESS][SUB-ADDRESS][DATA],
themastermayterminatethecommunicationwithaSTOP
condition.Alternatively,aREPEAT-STARTconditioncanbe
Enable LDO 2
Buck1 Burst Mode Enable
Buck2 Burst Mode Enable
Buck2 Burst Mode Enable
Buck SW Slew Rate: 00 = 1ns,
01 = 2ns, 10 = 4ns, 11 = 8ns
Not Used—No Effect on Operation
Table 8 shows the first byte of data that can be written to
at sub-address 0x00. This byte of data is referred to as
the “LDO and buck control register.”
Bits B0 and B1 enable and disable the LDOs. Writing 1
to B0 or B1 will enable LDO1 or LDO2 respectively, while
writing a 0 will disable the respective LDO.
2
initiated by the master and another chip on the I C bus can
be addressed. This cycle can continue indefinitely and the
3577f
39
LTC3577/LTC3577-1
OPERATION
Bits B2, B3, and B4 set the operating modes of the step-
down switching regulators (bucks). Writing 1 to any of
thesethreeregisterswillputthatrespectivebuckconverter
in the high efficiency Burst Mode operation, while a 0 will
enable the low noise pulse-skipping mode operation.
BitsB5andB6setthePWMclockspeedasshowninTable 9
of the “LED Backlight / Boost Operation” section.
Bit B7 sets the slew rate of the LED boost SW pin. Setting
B7 to 0 results in the fastest slew rate and provides the
most efficient mode of operation. Setting B7 to 1 should
only be used in cases where EMI due to SW slewing is an
issue as the slower slew rate causes a loss in efficiency.
The B5 and B6 bits adjust the slew rate of all SW pins
together so they all slew at the same rate. It is recom-
mended that the fastest slew rate (B6:B5 = 00) be used
unless EMI is an issue in the application as slower slew
rates cause reduced efficiency.
See “LED Backlight/Boost Operation” section for more
detailed operating information.
Table 10 shows the third byte of data that can be written
to at sub-address 0x02. This byte of data is referred to as
the “LED DAC register.” The LED current source utilizes a
6-bit 60dB exponential DAC. This DAC provides accurate
current control from 20ꢁA to 20mA with approximately
Table 9. I2C LED Control Register
LED CONTROL
REGISTER
ADDRESS: 00010010
SUB-ADDRESS: 00000001
BIT NAME
B0 EN
FUNCTION
Enable: 1 = Enable 0 = Off
1dB per step with I
programmed to 20mA. The LED
LED(FS)
B1 GR2
Gradation GR[2:1]: 00 = 15ms, 01 = 460ms,
10 = 930ms, 11 = 1.85s
current can be approximated by the following equation:
B2 GR1
DAC – 63
63
⎛
⎞
B3 MD1
Mode MD[2:1]: 00 = CC Boost,
10 = PWM Boost; 01 = HV Boost
ILED =ILED(FS) •10⎜⎝ 3 •
⎟
⎠
B4 MD2
B5 PWMC1
B6 PWMC2
B7 SLEWLED
PWM CLK PWMC[2:1]: 00 = 8.77kHz,
01 = 4.39kHz, 10 = 2.92kHz, 11 = 2.19kHz
2
where DAC is the decimal value programmed into the I C
“LED DAC register.” For example with I
DAC[5:0] = 101010 (42 decimal) I
LED SW Slew Rate: 0/1 = Fast/Slow
= 20mA and
equates to 2mA.
LED(FS)
LED
Table 9 shows the second byte of data that can be written
to at sub-address 0x01. This byte of data is referred to as
the “LED control register.”
Table 10. I2C LED DAC Register
ADDRESS: 00010010
SUB-ADDRESS: 00000010
LED DAC REGISTER
BIT NAME
B0 DAC[0]
B1 DAC[1]
B2 DAC[2]
B3 DAC[3]
B4 DAC[4]
B5 DAC[5]
B6 N/A
BitB0enablesanddisablestheLEDboostcircuitry.Writing
a 1 to B0 enables the LED boost circuitry, while writing a
0 disables the LED boost circuitry.
FUNCTION
6-Bit Log DAC Code
Bits B1 and B2 are the LED gradation which sets the ramp
up and down time of the LED current when enabled or
disabled. The gradation function allows the LEDs to turn
on/off gradually as opposed to an abrupt step.
Not Used—No Effect On Operation
Not Used—No Effect On Operation
Bits B3 and B4 set the operating mode of the LED boost
circuitry. The operating modes are: B4:B3 = 00 LED
constant current (CC) boost operation; B4:B3 = 10 LED
PWM boost operation; B4:B3 = 01 fixed high voltage (HV)
output boost operation; B4:B3 = 11 not supported, do not
use. See the “LED Backlight/Boost Operation” section for
more information on the operating modes.
B7 N/A
3577f
40
LTC3577/LTC3577-1
OPERATION
Table 11 shows the final byte of data that can be written
to at sub-address 0x03. This byte of data is referred to as
the “LED PWM register”. See the “LED PWM vs Constant
Current Operation” section for detailed information on
how to set the values of this register.
BitA7showsthepowergoodstatusofbuck3.A1indicates
that buck3 is enabled and is regulating correctly. A 0 indi-
cates that either buck3 is not enabled, or that the buck3 is
enabled, but is out of regulation by more than 8%.
BitA6showsthepowergoodstatusofbuck2.A1indicates
that buck2 is enabled and is regulating correctly. A 0 indi-
cates that either buck2 is not enabled, or that the buck2 is
enabled, but is out of regulation by more than 8%.
Table 11. LED PWM Register
ADDRESS: 00010010
LED PWM REGISTER
BIT NAME
SUB-ADDRESS: 00000011
FUNCTION
BitA5showsthepowergoodstatusofbuck1.A1indicates
that buck1 is enabled and is regulating correctly. A 0 indi-
cates that either buck1 is not enabled, or that the buck1 is
enabled, but is out of regulation by more than 8%.
B0 PWMDEN[0]
B1 PWMDEN[1]
B2 PWMDEN[2]
B3 PWMDEN[3]
B4 PWMNUM[0]
B5 PWMNUM[1]
B6 PWMNUM[2]
B7 PWMNUM[3]
PWM DENOMINATOR
BitA4showsthepowergoodstatusofLDO2. A1indicates
that LDO2 is enabled and is regulating correctly. A 0 indi-
cates that either LDO2 is not enabled, or that the LDO2 is
enabled, but is out of regulation by more than 8%.
PWM NUMERATOR
BitA3showsthepowergoodstatusofLDO1. A1indicates
that LDO1 is enabled and is regulating correctly. A 0 indi-
cates that either LDO1 is not enabled, or that the LDO1 is
enabled, but is out of regulation by more than 8%.
2
I C Output Data
One status byte may be read from the LTC3577. Table 12
represents the status byte information. A 1 read back in
the any of the bit positions indicates that the condition is
true. For example, 1 read back from bit A3 indicate that
LDO1 is enabled and regulating correctly. A status read
from the LTC3577 captures the status information when
the LTC3577 acknowledges its read address.
Bits A2 and A1 indicate the fault status of the charger
circuit and are decoded in Table 12. The “too cold/hot”
state indicates that the thermistor temperature is out of
the valid charging range (either below 0°C or above 40°C
for a curve 1 thermistor) and that charging has paused
until a return to valid temperature. The battery overtemp
state indicates that the battery’s thermistor has reached
a critical temperature (above 50°C for a curve 1 thermis-
tor) and that long-term battery capacity may be seriously
compromised if the condition persists. The battery fault
state indicates that an attempt was made to charge a
low battery (typically < 2.85V) but that the low voltage
condition persisted for more than 1/2 hour. In this case
charging has terminated.
Table 12. I2C READ Register
ADDRESS: 00010011
STATUS REGISTER
BIT NAME
SUB-ADDRESS: None
FUNCTION
A0 CHARGE
A1 STAT[0]
A2 STAT[1]
Charge Status (1 = Charging)
STAT[1:0]; 00 = No Fault
01 = TOO COLD/HOT
10 = BATTERY OVERTEMP
11 = BATTERY FAULT
A3 PGLDO[1]
A4 PGLDO[2]
A5 PGBCK[1]
A6 PGBCK[2]
A7 PGBCK[3]
LDO1 Power Good
LDO2 Power Good
Buck1 Power Good
Buck2 Power Good
Buck3 Power Good
Bit A0 indicates the status of the battery charger. A 1 in-
dicates that the charger is enabled and is in the constant
current charge state. In this case the battery is being
charged unless the NTC thermistor is outside its valid
charge range in which case charging is temporarily sus-
pended but not complete. Charging will continue once the
3577f
41
LTC3577/LTC3577-1
OPERATION
battery has returned to a valid charging temperature. A 0
in bit A0 indicates that charging has entered the end-of-
ADDRESS: 00010010
LED PWM REGISTER
BIT NAME
SUB-ADDRESS: 00000011
FUNCTION
PWM Denominator
charge state (h ) and is near V
or that charging
C/10
FLOAT
B0 PWMDEN[0]
B1 PWMDEN[1]
B2 PWMDEN[2]
B3 PWMDEN[3]
B4 PWMNUM[0]
B5 PWMNUM[1]
B6 PWMNUM[2]
B7 PWMNUM[3]
has been terminated. Charging can be terminated by
reaching the end of the charge timer or by a battery fault
as described previously.
2
2
PWM Numerator
I C WRITE REGISTER MAP (see “I C Input Data” section
for more details, all registers default to 0 when reset)
LDO and BUCK CONTOL ADDRESS: 00010010
REGISTER
SUB-ADDRESS: 00000000
BIT NAME
FUNCTION
PUSHBUTTON INTERFACE OPERATION
B0 LDO1EN
B1 LDO2EN
B2 BK1BRST
B3 BK2BRST
B4 BK3BRST
B5 SLEWCTL1
B6 SLEWCTL2
B7 N/A
Enable LDO 1
Enable LDO 2
Buck1 Burst Mode Enable
Buck2 Burst Mode Enable
Buck2 Burst Mode Enable
Buck SW Slew Rate: 00 = 1ns,
01 = 2ns, 10 = 4ns, 11 = 8ns
State Diagram/Operation
Figure 18 shows the LTC3577 pushbutton state diagram.
Upon first application of power (V , WALL or BAT) an
BUS
internalpower-onreset(POR)signalplacesthepushbutton
circuitry into the power-down (PDN1) state. One second
after entering the PDN1 state the pushbutton circuitry will
transition into the hard reset (HR) state. The following
events cause the state machine to transition out of HR
into the power-up (PUP1) state:
Not Used—No Effect On Operation
LED CONTROL
REGISTER
BIT NAME
ADDRESS: 00010010
SUB-ADDRESS: 00000001
FUNCTION
Enable: 1= Enable 0 = Off
B0 EN
B1 GR2
B2 GR1
B3 MD1
B4 MD2
B5 PWMC1
B6 PWMC2
B7 SLEWLED
Gradation GR[2:1]: 00 = 15ms, 01 = 460ms,
10 = 930ms, 11 = 1.85 Seconds
1) ON input low for 400ms (PB400MS)
2) Application of external power (EXTPWR)
3) PWR_ON input going high (PWR_ON)
Mode MD[2:1]: 00 = CC Boost,
10 = PWM Boost, 01 = HV Boost
PWM CLK PWMC[2:1]: 00 = 8.77kHz,
01 = 4.39kHz, 10 = 2.92kHz, 11 = 2.19kHz
HR
LED SW Slew rate: 0/1 = Fast/Slow
PB400MS +
EXTPWR +
PWR_ON
ADDRESS: 00010010
SUB-ADDRESS: 00000010
FUNCTION
6-Bit Log DAC Code
LED DAC REGISTER
BIT NAME
PUP2
POFF
PUP1
PB400MS +
EXTPWR +
PWR_ON
5SEC
5SEC
B0 DAC[0]
B1 DAC[1]
B2 DAC[2]
B3 DAC[3]
B4 DAC[4]
B5 DAC[5]
B6 N/A
PON
PWR_ON
HRST
1SEC
1SEC
+UVLO
HRST
PDN2
PDN1
Not Used—No Effect On 0peration
Not Used—No Effect On 0peration
HRST
POR
B7 N/A
Figure 18. Pushbutton State Diagram
3577f
42
LTC3577/LTC3577-1
OPERATION
Upon entering the PUP1 state, the pushbutton circuitry
will sequence up the three step-down switching regula-
tors in numerical order. LDO1, LDO2 and LED backlight
Power-Up via Pushbutton Timing
Thetimingdiagram,Figure19, showstheLTC3577power-
ing up through application of the external pushbutton. For
this example the pushbutton circuitry starts in the POFF or
HR state with a battery connected and all buck disabled.
Pushbutton application (ON low) for 400ms transitions
the pushbutton circuitry into the PUP state which brings
WAKE Hi-Z for 5 seconds. WAKE going Hi-Z sequences
buck1-3 up in numerical order. WAKE will stay Hi-Z if
PWR_ON is driven high before the 5 seconds PUP period
is over. If PWR_ON is low or goes low after the 5 second
period, WAKE will go low and buck1-3 will be shut down
together. PG_DCDC is asserted once all enabled bucks are
within 8% of their regulation voltage for 230ms.
2
are enabled via I C and do not take part in the power-up
sequence of the pushbutton. Five seconds after entering
thePUP1state,thepushbuttoncircuitrywilltransitioninto
the power-on (PON) state. Note that the PWR_ON input
must be brought high before entering the PON state if the
part is to remain in the PON state.
PWR_ON going low, or V
dropping to its undervoltage
OUT
lockout(V UVLO)thresholdwillcausethestatemachine
OUT
to leave the PON state and enter the power-down (PDN2)
2
state. The PDN1 and PDN2 states reset the I C registers
effectively shutting down the LDOs and LED backlight as
well as disable all switching regulators together. The one
seconddelaybeforeleavingeitherpower-downstateallows
allLTC3577generatedsuppliestopowerdowncompletely
before they can be re-enabled.
PBSTAT does not go low impedance with ON going low
during the power-up pushbutton application. PBSTAT will
go low impedance with ON on subsequent pushbutton
applications once in the PUP1, PUP2 or PON states.
The same three events used to exit HR are also used to
exit the POFF state and enter PUP2 state. The PUP2 state
operates in the same manner as the PUP1 state previously
described.
The LDOs and LED backlight can be enabled and disabled
2
at any time via I C once in the PUP1, PUP2 or PON states.
The PWR_ON input can be driven via a ꢁP/ꢁC or by one of
the buck outputs through a high impedance (100kΩ typ)
to keep the bucks enabled as described above.
The hard reset (HRST) event is generated by pressing and
holding the pushbutton (ON input low) for 5 seconds. For
a valid HRST event to occur the initial pushbutton applica-
tion must start in the PUP1, PUP2 or PON state, but can
end in any state. If a valid HRST event is present in PON,
PDN2 or POFF, then the state machine will transition to the
PDN1 state and subsequently transition to the HR state
one second later.
BAT
V
BUS
ON (PB)
PBSTAT
WAKE
400ms
BUCKS SEQUENCE UP
1 2 3
BUCK1-3
In the HR state all supplies are disabled and the Power-
Path circuitry is placed in an ultralow quiescent state to
minimize battery drain. If no external charging supply is
230ms
PG_DCDC
5SEC
PWR_ON
STATE
present (WALL or V ) then the ideal diode is shut down
BUS
POFF/HR
PUP2/PUP1
PON
disconnecting V
from BAT to further minimize battery
OUT
3755 F19
drain. The ultralow power consumption in the HR state
makes it ideal for shipping or long term storage, minimiz-
ing battery drain.
Figure 19. Power-Up via Pushbutton Timing
3577f
43
LTC3577/LTC3577-1
OPERATION
Power-Up via External Power Timing
Power-Up via PWR_ON Timing
Thetimingdiagram,Figure20,showstheLTC3577power-
The timing diagram, Figure 21, shows the LTC3577
powering up by driving PWR_ON high. For this example
the pushbutton circuitry starts in the POFF or HR state
with a battery connected and all bucks disabled. 50ms
after PWR_ON goes high the WAKE output goes Hi-Z for
5 seconds. WAKE going Hi-Z sequences buck1-3 up in
numerical order. WAKE will stay Hi-Z as long as PWR_ON
is high at the end of the 5 second PUP period. If PWR_ON
is low or goes low after the 5 second period, WAKE will
go low and buck1-3 will be shut down together. PG_DCDC
is asserted once all enabled bucks are within 8% of their
regulation voltage for 230ms.
ing up through application of the external power (V
or
BUS
WALL). For this example the pushbutton circuitry starts
in the POFF or HR state with a battery connected and all
buck disabled. 100ms after WALL or V
application the
BUS
WAKE output goes Hi-Z for 5 seconds. The 100ms delay
time allows the applied supply to settle. WAKE going
Hi-Z sequences buck1-3 up in numerical order. WAKE
will stay Hi-Z if the PWR_ON input is driven high before
the 5 seconds PUP period is over. If PWR_ON is low or
goes low after the 5 second period, WAKE will go low and
buck1-3 will be shut down together. PG_DCDC is asserted
once all enabled bucks are within 8% of their regulation
voltage for 230ms.
The LDOs and LED backlight can be enabled and disabled
2
via I C any time after entering the PUP1, PUP2 or PON
The LDOs and LED backlight can be enabled and disabled
state.
2
via I C any time after entering the PUP1, PUP2 or PON
Powering up via PWR_ON is useful for applications
containing an always on ꢁC. This allows the ꢁC to power
the application up and down for house keeping and other
activities outside the user’s control.
state. The PWR_ON input can be driven via a ꢁP/ꢁC or one
of the buck outputs through a high impedance (100kΩ
typ) to keep the bucks enabled as described above.
Without a battery present initial power application causes
a power on reset which puts the pushbutton circuitry in
the PDN2 state and subsequently the HR state 1 second
later. In this case the pushbutton must be applied to enter
the PUP1 state after initial power application.
BAT
ON (PB)
PBSTAT
5SEC
PWR_ON
5Oms
WAKE
BAT
BUCKS SEQUENCE UP
BUCK1-3
1 2 3
V
BUS
230ms
PG_DCDC
STATE
ON (PB)
POFF/HR
PUP2/PUP1
PON
PBSTAT
WAKE
3577 F21
100ms
BUCKS SEQUENCE UP
1 2 3
Figure 21. Power-Up via PWR_ON Timing
BUCK1-3
230ms
PG_DCDC
5SEC
PWR_ON
STATE
POFF/HR
PUP2/PUP1
PON
3755 F20
Figure 20. Power-Up via External Power Timing
3577f
44
LTC3577/LTC3577-1
OPERATION
Power-Down via Pushbutton Timing
UVLO Minimum Off-Time Timing (Low Battery)
The timing diagram, Figure 22, shows the LTC3577
powering down by ꢁC/ꢁP control. For this example the
pushbutton circuitry starts in the PON state with a bat-
tery connected and all bucks enabled. In this case the
pushbutton is applied (ON low) for at least 50ms, which
generates a low impedance on the PBSTAT output. After
receiving the PBSTAT the ꢁC/ꢁP will drive the PWR_ON
input low. 50ms after PWR_ON goes low the WAKE
output will go low and the pushbutton circuitry will enter
the PDN2 state. The bucks are disabled together at once
upon entering the PDN2 state. Once entering the PDN2
state a 1 second wait time is initiated before entering the
POFF state. During this 1 second time ON and PWR_ON
inputs as well as external power application are ignored
to allow all LTC3577 generated supplies to go low. Though
the above assumes a battery present, the same operation
Thetimingdiagram,Figure23, assumesthebatteryiseither
missing or at a voltage below the V
UVLO threshold
OUT
and the application is running via external power (V
or WALL). A glitch on the external supply causes V
BUS
OUT
to drop below the V
UVLO threshold temporarily. The
OUT
V
UVLO condition will cause the pushbutton circuitry
OUT
to transition from the PON state to the PDN2 state. Upon
entering the PDN2 state WAKE and PG_DCDC will go low
while the bucks, LDOs and LED backlight power down
together. If the external supply recovers after entering the
PND2 state such that V
is no longer in UVLO then the
OUT
LTC3577 will transition back into the PUP2 state once the
PDN2 one second delay is complete. Though not shown
in Figure 23, the pushbutton logic briefly visits the POFF
state when transitioning between PDN2 and PUP2. Enter-
ing the PUP2 state will cause the bucks to sequence up as
described previously in the power-up sections. The LDOs
would take place with a valid external supply (V
WALL) with or without a battery present.
or
BUS
2
and LED backlight must be re-enabled via I C once device
is powered back up.
Upon entering the PDN2 state the LDOs and LED backlight
2
I C registers are cleared effectively disabling both. If this
BAT
is not desirable the LDOs and LED backlight should be
V
2
BUS/WALL
disabled via I C prior to entering the PDN2 state.
ON (PB)
Holding ON low through the 1 second power-down period
will not cause a power-up event at end of the 1 second
period. The ON input must be brought high following the
power-down event and then go low again to establish a
valid power-up event.
PBSTAT
5SEC
PWR_ON
1SEC
WAKE
BUCKS SEQUENCE UP
BUCKS
PG_DCDC
STATE
1 2 3
230ms
BAT
PON
PDN2
PUP2
PON
V
BUS/WALL
3577 F23
1SEC
ON (PB)
Figure 23. UVLO Minimum Off-Time
50ms
PBSTAT
μC/μP CONTROL
PWR_ON
WAKE
50ms
ALL BUCKS LOW
BUCK1-3
PG_DCDC
STATE
PON
PDN2
POFF
3577 F22
Figure 22. Power-Down va Pushbutton Timing
3577f
45
LTC3577/LTC3577-1
OPERATION
Hard Reset Timing
Power-Up Sequencing
Hard reset provides an ultralow power-down state for
shipping or long-term storage as well as a way to power
down the application in case of a software lock-up. In the
case of software lock-up ON is brought low by the user
applying the pushbutton. If the user holds the pushbutton
for 5 seconds a hard reset event (HRST) will occur placing
the pushbutton circuitry in the PDN1 state. At this point
the bucks, LDOs and LED backlight will all be shut down
and WAKE and PG_DCDC will both go low. Following a 1
second power-down period the pushbutton circuitry will
enter the hard reset state (HR).
Figure 25 shows the actual power-up sequencing of the
LTC3577. Buck1, buck2 and buck3 are all initially disabled
(0V). Once the pushbutton has been applied (ON low) for
400ms, WAKE goes high and buck1 is enabled. Buck1
slews up and enters regulation once enabled. The actual
slew rate is controlled by the soft-start function of buck1
in conjunction with output capacitance and load (see
“Step-Down Switching Regulator Operation” section for
moreinformation).Whenbuck1iswithinabout8%offinal
regulation, buck2 is enabled and slews up into regulation.
Finally when buck2 is within about 8% of final regulation,
buck3 is enabled and slews up into regulation. 230ms
after buck3 is within 8% of final regulation the PG_DCDC
output will go high impedance (not shown in Figure 25).
The regulators in Figure 25 are slewing up with nominal
output capacitors and no load. Adding a load or increasing
output capacitance on any of the outputs will reduce the
slew rate and lengthen the time it takes the regulator to get
intoregulation. Reducingtheslewratealsopushesoutthe
time until the next regulator is enabled proportionally.
Holding ON low through the 1 second power-down period
willnotcauseapower-upeventatendofthe1secondperiod.
The ON must be brought high following the power-down
event and then go low for again for 400ms to establish a
valid power up event as shown in Figure 24.
BAT
5SEC
1
ON (PB)
WAKE
PBSTAT
400ms
WAKE
0
BUCK1
2V/DIV
1 2 3
BUCKS
0V
1SEC
BUCK2
1V/DIV
PWR_ON
0V
PG_DCDC
STATE
BUCK3
1V/DIV
PON
PDN1
HR
PUP
0V
3577 F24
3577 F23
50μs/DIV
Figure 24. Hard Reset Timing
Figure 25. Power-Up Sequencing
3577f
46
LTC3577/LTC3577-1
OPERATION
LAYOUT AND THERMAL CONSIDERATIONS
The power dissipated on chip by a LDO regulator can be
estimated as follows:
Printed Circuit Board Power Dissipation
P
= (V
– LOUTx) • I
INLDOx OUT
DLDOx
In order to be able to deliver maximum charge current
under all conditions, it is critical that the exposed ground
pad on the backside of the LTC3577 package is soldered
to a ground plane on the board. Correctly soldered to
where LOUTx is the programmed output voltage, V
INLDOx
is the LDO output load
is the LDO supply voltage and I
OUT
current. Note that if the LDO supply is connected to one
of the buck output, then its supply current must be added
to the buck regulator load current for calculating the buck
power loss.
2
2500mm ground plane on a double-sided 1oz. copper
board the LTC3577 has a thermal resistance (θ ) of ap-
JA
proximately45°C/W.Failuretomakegoodthermalcontact
between the Exposed Pad on the backside of the package
and a adequately sized ground plane will result in thermal
resistances far greater than 45°C/W.
The power dissipated by the LED boost regulator can be
estimated as follows:
2
⎛
⎜
⎝
⎞
⎟
BOOST
VOUT –1
The conditions that cause the LTC3577 to reduce charge
current due to the thermal protection feedback can be
approximated by considering the power dissipated in the
part.Forhighchargecurrentswithawalladapterappliedto
PDLED =ILED •0.3V +RNSWON • ILED
•
⎠
where BOOST is the output voltage driving the top of
the LED string, R is the on-resistance of the SW
NSWON
V , the LTC3577 power dissipation is approximately:
OUT
N-FET (typically 330mΩ), I
is the LED programmed
LED
P = (V
– BAT) • I + P
BAT DREGS
D
OUT
current sink.
where, P is the total power dissipated, V
is the sys-
D
OUT
Thus the power dissipated by all regulators is:
= P + P + P + P + P
tem supply voltage, BAT is the battery voltage, and I
BAT
P
+ P
DLED
DREGS
DSW1
DSW2
DSW3
DLDO1
DLDO2
is the battery charge current. P
is the sum of power
DREGS
dissipated on-chip by the step-down switching, LDO and
LED boost regulators.
It is not necessary to perform any worst-case power dis-
sipationscenariosbecausetheLTC3577willautomatically
reduce the charge current to maintain the die temperature
at approximately 110°C. However, the approximate ambi-
ent temperature at which the thermal feedback begins to
protect the IC is:
The power dissipated by a step-down switching regulator
can be estimated as follows:
100 –Eff
PD(SWx) = BOUTx •I
•
(
)
OUT
100
T = 110°C – P • θ
JA
A
D
where BOUTx is the programmed output voltage, I
Example: Consider the LTC3577 operating from a wall
adapter with 5V (V ) providing 1A (I ) to charge a
OUT
is the load current and Eff is the % efficiency which can
be measured or looked up on an efficiency table for the
programmed output voltage.
OUT
BAT
Li-Ion battery at 3.3V (BAT). Also assume P
= 0.3W,
DREGS
so the total power dissipation is:
P = (5V – 3.3V) • 1A + 0.3W = 2W
D
The ambient temperature above which the LTC3577 will
begin to reduce the 1A charge current, is approximately
T = 110°C – 2W • 45°C/W = 20°C
A
3577f
47
LTC3577/LTC3577-1
OPERATION
The LTC3557 can be used above 20°C, but the charge
current will be reduced below 1A. The charge current at
a given ambient temperature can be approximated by:
2. The step-down switching regulator input supply pins
(V and V ) and their respective decoupling ca-
IN12
IN3
pacitors should be kept as short as possible. The GND
side of these capacitors should connect directly to the
ground plane of the part. These capacitors provide the
AC current to the internal power MOSFETs and their
drivers. It’s important to minimizing inductance from
these capacitors to the pins of the LTC3577. Connect
110°C – TA
PD =
Thus:
= V
–BAT •IBAT +PD(REGS)
(
)
OUT
θJA
V
and V to V
through a short low impedance
(110°C− TA )
IN12
trace.
IN3
OUT
−PDREGS
θJA
VOUT –BAT
IBAT
=
3. TheswitchingpowertracesconnectingSW1,SW2,and
SW3 to their respective inductors should be minimized
to reduce radiated EMI and parasitic coupling. Due to
thelargevoltageswingoftheswitchingnodes,sensitive
nodes such as the feedback nodes (FBx, LDOx_FB and
LED_OV) should be kept far away or shielded from the
switching nodes or poor performance could result.
Consider the above example with an ambient temperature
of 55°C. The charge current will be reduced to approxi-
mately:
110°C – 55°C
− 0.3W
45°C/W
IBAT
=
=
4. Connectionsbetweenthestep-downswitchingregulator
inductorsandtheirrespectiveoutputcapacitorsshould
be kept should be kept as short as possible. The GND
side of the output capacitors should connect directly
to the thermal ground plane of the part.
5V – 3.3V
1.22W – 0.3W
IBAT
= 542mA
1.7V
If an external buck switching regulator controlled by the
5. Keep the buck feedback pin traces (FB1, FB2, and FB3)
asshortaspossible.Minimizeanyparasiticcapacitance
between the feedback traces and any switching node
(i.e. SW1, SW2, SW3, and logic signals). If necessary
shield the feedback nodes with a GND trace.
LTC3577 V pin is used instead of a 5V wall adapter we see
C
asignificantreductioninpowerdissipatedbytheLTC3577.
This is because the external buck switching regulator will
drive the PowerPath output (V ) to about 3.6V with the
OUT
battery at 3.3V. If you go through the example above and
6. Connections between the LTC3577 PowerPath pins
substitute 3.6V for V
we see that thermal regulation
OUT
(V
and V ) and their respective decoupling ca-
does not kick in until about 83°C. Thus, the external high
voltage buck regulator not only allows higher charging
currents, but lower power dissipation means a cooler
running application.
BUS
OUT
pacitors should be kept as short as possible. The GND
side of these capacitors should connect directly to the
ground plane of the part.
7. The boost converter switching power trace connect-
ing SW to the inductor should be minimized to reduce
radiated EMI and parasitic coupling. Due to the large
voltage swing of the SW node, sensitive nodes such
as the feedback nodes (FBx, LDOx_FB and LED_OV)
should be kept far away or shielded from this switching
node or poor performance could result.
Printed Circuit Board Layout
When laying out the printed circuit board, the following
list should be followed to ensure proper operation of the
LTC3577:
1. TheExposedPadofthepackage(Pin45)shouldconnect
directlytoalargegroundplanetominimizethermaland
electrical impedance.
3577f
48
LTC3577/LTC3577-1
TYPICAL APPLICATION
USB Plus 5V Adapter Input Charger, Multi-Channel Power Supply and PowerPath Controller
5V WALL
ADAPTER
Si2333DS
R1
Si2306BDS
D3
Si2333DS
42
4
41
V
WALL ACPR
C
V
OUT
13
8
30
39
32
6
SYSTEM
LOAD
OVGATE
V
INLDO2
6.2k
10μF
2.2μF
2.2μF
OVSENSE
V
OPTIONAL OVERVOLTAGE/
REVERSE VOLTAGE PROTECTION
OUT
V
IN12
1k
40
USB
V
V
IN3
BUS
44
37
10μF
CHRG
Si2333DS
(OPT)
IDGATE
2.1k
2k
43
36
38
CLPROG
PROG
BAT
BAT
+
100k
34
35
Li-Ion
NTCBIAS
NTC
20μF
ZLLS400
100k
NTC
10μH
LTC3577
10
11
12
18,19,20
DV
SDA
SCL
DV
CC
SDA
SCL
SW
CC
1μF
50V
6M
9
LED_OV
6-LED BACKLIGHT
22nF
22
I
499k 499k
LED
μC/μP
20k
3
17
16
14
LED_FS
WAKE
PBSTAT
WAKE
PBSTAT
PWR_ON
21
PG_DCDC
PWR_ON
100k
4.7μH
V
1
2
OUT1
33
I
I
I
I
LIM0
LIM0
LIM1
SW1
FB1
3.3V
500mA
RST
LIM1
10pF
1.02M
10μF
324k
PUSHBUTTON
26
23
15
28
V
ON
INLDO1
4.7μH
3.3μH
V
V
LDO1
OUT2
31
1.2V
LDO1
SW2
1.8V
75mA
500mA
1μF
1μF
232k
10pF
10pF
806k
232k
10μF
10μF
464k
470k
649k
464k
27
29
25
5
LDO1_FB
LDO2
FB2
V
V
OUT3
LDO2
SW3
1.2V
2.5V
800mA
150mA
1.00M
7
24
LDO2_FB
FB3
GND
45
3577 TA02
3577f
49
LTC3577/LTC3577-1
TYPICAL APPLICATION
USB Plus HV Input Charger, Multi-Channel Power Supply and PowerPath Controller
HV
IN
OPTIONAL HIGH VOLTAGE
BUCK INPUT
2
3
4
5
8V TO 38V
(TRANSIENTS
TO 60V)
BOOST
LT3480
V
IN
0.47μF
6.8μH
150k
68nF
4.7μF
RUN/SS
SW
40.2k
499k
22μF
100k
10
6
DFLS240L
RT
1
8
NC
NC
SYNC
BD
FB
C
7
PG
GND
V
V
11
9
Si2333DS
42
C
4
41
WALL ACPR
V
OUT
30
39
32
6
SYSTEM
LOAD
V
INLDO2
10μF
2.2μF
2.2μF
Si2306BDS
6.2k
40
USB
V
BUS
V
OUT
10μF
V
IN12
1k
13
8
V
OVGATE
IN3
44
37
OVSENSE
CHRG
OPTIONAL
OVERVOLTAGE
PROTECTION
Si2333DS
(OPT)
IDGATE
2.1k
43
36
38
CLPROG
PROG
BAT
BAT
+
100k
34
35
Li-Ion
NTCBIAS
NTC
2k
20μF
100k
NTC
10μH
LTC3577
ZLLS400
10
11
12
18,19,20
DV
CC
SDA
SCL
DV
CC
SDA
SCL
SW
1μF
50V
10M
9
LED_OV
10-LED BACKLIGHT
22nF
22
I
499k 499k
LED
μC/μP
20k
3
17
16
14
LED_FS
WAKE
PBSTAT
WAKE
21
PBSTAT
PWR_ON
PG_DCDC
PWR_ON
100k
4.7μH
V
1
2
OUT1
33
I
I
I
I
LIM0
LIM1
LIM0
LIM1
SW1
FB1
3.3V
400mA
RST
10pF
1.02M
10μF
324k
PUSHBUTTON
26
23
15
28
V
ON
INLDO1
4.7μH
V
V
LDO1
OUT2
31
1.2V
LDO1
SW2
1.8V
75mA
400mA
1μF
1μF
232k
10pF
10pF
806k
232k
10μF
10μF
464k
470k
649k
464k
27
29
25
5
LDO1_FB
LDO2
FB2
3.3μH
V
V
OUT3
LDO2
SW3
1.2V
2.5V
600mA
150mA
1.00M
7
24
LDO2_FB
FB3
GND
45
3577 TA03
3577f
50
LTC3577/LTC3577-1
PACKAGE DESCRIPTION
UFF Package
Variation: UFFMA
44-Lead Plastic QFN (4mm × 7mm)
(Reference LTC DWG # 05-08-1762 Rev Ø)
1.48 0.05
0.70 0.05
0.98 0.05
1.70 0.05
2.56 0.05
4.50 0.05
3.10 0.05
2.40 REF
2.02 0.05
2.76 0.05
2.64 0.05
PACKAGE
OUTLINE
0.20 0.05
5.60 REF
0.40 BSC
6.10 0.05
7.50 0.05
RECOMMENDED SOLDER PAD LAYOUT
PIN 1 NOTCH
R = 0.30 TYP
OR 0.35 s 45o
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
CHAMFER
0.75 p0.05
2.40 REF
4.00 p0.10
43
44
0.00 – 0.05
0.40 p0.10
1
2
PIN 1
TOP MARK
(SEE NOTE 6)
2.64
0.10
2.56
0.10
7.00 p0.10
5.60 REF
R = 0.10
TYP
1.70
0.10
2.76
0.10
0.74 0.10
R = 0.10 TYP
0.74 0.10
(UFF44MA) QFN REF Ø 1107
R = 0.10 TYP
0.200 REF
0.20 p0.05
0.40 BSC
0.98 0.10
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3577f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
51
LTC3577/LTC3577-1
RELATED PARTS
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Package
2
I C Controlled High Efficiency USB
Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max
Charge Current, 180mꢀ Ideal Diode with <50mꢀ Option, 3.3V/25mA Always-On LDO, Three
Synchronous Buck Regulators, One 1A Buck-Boost Regulator, 4mm × 5mm QFN28 Package
Power Manager Plus Triple Step-Down
DC/DC
High Efficiency USB Power Manager
Plus Dual Buck Plus Buck-Boost DC/DC Charge Current, 180mꢀ Ideal Diode with <50mꢀ Option, 3.3V/25mA Always-On LDO, Two
Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max
400mA Synchronous Buck Regulators, One 1A Buck-Boost Regulator, 4mm × 5mm QFN28
Package
LTC3557/
LTC3557-1
USB Power Manager with Li-
Ion/Polymer Charger and Triple
Synchronous Buck Converter
Complete Multifunction ASSP: Linear Power Manager and Three Buck Regulaters
Charge Current Programmable up to 1.5A from Wall Adapter Input, Thermal Regulation
Synchronous Buck Efficiency: >95%, ADJ Outputs: 0.8V to 3.6V at 400mA/400mA/600mA
Bat-Track Adaptive Output Control, 200m Ideal Diode, 4mm × 4mm QFN28 Package,
“-1” version has 4.1V Float Voltage.
LTC3566
LTC3567
Switching USB Power Manager with
Multifunction PMIC: Switchmode Power Manager and 1A Buck-Boost Regulator + LDO,
Li-Ion/Polymer Charger, 1A Buck-Boost Charge Current Programmable Up to 1.5A from Wall Adapter Input, Thermal Regulation
Converter Plus LDO
Synchronous Buck-Boost Converters Efficiency: >95%, ADJ Output: Down to 0.8V at 1A,
2
Bat-Track Adaptive Output Control, 180mꢀ Ideal Diode, LTC3567 Has I C Interface,
4mm × 4mm QFN24 Package
LTC3576/-1
LTC3586
Switching USB Power Manager with
USB OTG + Triple Step-Down DC/DCs
Complete Multi-Function PMIC: Bi-Directional Switching Power Manager + 3 Bucks + LDO,
ADJ Output Down to 0.8V at 400mA/400mA/1A, Over-Voltage Protection, USB On-The-Go,
2
Charge Current Programmable Up to 1.5A from Wall Adapter Input, Thermal Regulation, I C,
Hi-Voltage Bat-Track Buck Interface, 180mΩ Ideal Diode, 4mm × 6mm QFN-38 Package
Switching USB Power Manager with
Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max
Li-Ion/Polymer Charger Plus Dual Buck Charge Current, 180mΩ Ideal Diode with <50mΩ Option, 3.3V/25mA Always-On LDO, Two
Plus Buck-Boost Plus Boost DC/DC
400mA Synchronous Buck Regulators, One 1A Buck-Boost Regulator, One 600mA Boost
Regulator, 4mm × 6mm 38-Pin QFN Package
LTC4085/
LTC4085-1
USB Power Manager with Ideal Diode
Controller and Li-Ion Charger
Charges Single Cell Li-Ion Batteries Directly from a USB Port, Thermal Regulation, 200m Ideal
Diode with <50m Option, 4mm × 3mm DFN14 Package, “-1” version has 4.1V Float Voltage.
LTC4088
High Efficiency USB Power Manager
and Battery Charger
Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max
Charge Current, 180mꢀ Ideal Diode with <50m Option, 3.3V/25mA Always-On LDO,
4mm × 3mm DFN14 Package
LTC4088-1
High Efficiency USB Power Manager
and Battery Charger with Regulated
Output Voltage
Maximizes Available Power from USB Port, Bat-Track, “Instant-On” Operation, 1.5A Max
Charge Current, 180mꢀ Ideal Diode with <50mꢀ Option, Automatic Charge Current
Reduction Maintains 3.6V Minimum V , Battery charger disabled when all logic inputs are
OUT
grounded, 3mm × 4mm DFN14 Package
LTC4088-2
LTC4098
High Efficiency USB Power Manager
and Battery Charger with Regulated
Output Voltage
Maximizes Available Power from USB Port, Bat-Track, “Instant-On” Operation, 1.5A Max
Charge Current, 180mꢀ Ideal Diode with <50mꢀ Option, Automatic Charge Current
Reduction Maintains 3.6V Minimum V , 3mm × 4mm DFN14 Package
OUT
USB-Compatible Switchmode Power
Manager with OVP
High V : 38V Operating, 60V Transient; 66V OVP. Maximizes Available Power from USB
IN
Port, Bat-Track, “Instant-On” Operation, 1.5A Max Charge Current from Wall, 600mA Charge
Current from USB, 180mꢀ Ideal Diode with <50mꢀ Option; 3mm × 4mm
Ultra-Thin QFN20 Package
Hot Swap is a trademark of Linear Technology Corporation.
3577f
LT 0709 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
52
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© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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