LTC3589HUJ-2#PBF_技术文档

LTC3589/LTC3589-1/

LTC3589-2

8-Output Regulator with

2

Sequencing and I C

FeaTures

DescripTion

2

n

Triple I C Adjustable High Efﬁciency Step-Down DC/

The LTC^®3589 is a complete power management solu-

tion for ARM and ARM-based processors and advanced

portable microprocessor systems. The device contains

three step-down DC/DC converters for core, memory and

SoC rails, a buck-boost regulator for I/O at 1.8V to 5V and

three 250mA LDO regulators for low noise analog sup-

DC Converters: 1.6A, 1A/1.2A, 1A/1.2A

n

High Efﬁciency 1.2A Buck-Boost DC/DC Converter

n

Triple 250mA LDO Regulators

n

Pushbutton ON/OFF Control with System Reset

n

Flexible Pin-Strap Sequencing Operation

2

n

plies. An I C serial port is used to control enables, output

I C and Independent Enable Control Pins

n

voltage levels, dynamic voltage scaling, operating modes

and status reporting. Differences between the LTC3589,

LTC3589-1, and LTC3589-2 are summarized in Table 1.

Power Good and Reset Outputs

Dynamic Voltage Scaling and Slew Rate Control

Selectable 2.25MHz or 1.12MHz Switching Frequency

Always-Alive 25mA LDO Regulator

8µA Standby Current

Regulator start-up is sequenced by connecting outputs to

enable pins in the desired order or programmed via the

2

40-Pin 6mm × 6mm × 0.75mm QFN

I Cport. Systempower-on, power-off, andresetfunctions

2

are controlled by pushbutton interface, pin inputs, or I C

applicaTions

interface.

n

Handheld Instruments and Scanners

The LTC3589 supports i.MX53/51, PXA and OMAP pro-

cessors with eight independent rails at appropriate power

levels. Other features include interface signals such as

the VSTB pin that simultaneously toggle up to four rails

between programmed run and standby output voltages.

The device is available in a low profile 40-pin 6mm × 6mm

exposed pad QFN package.

n

Portable Industrial Devices

n

Automotive Infotainment

n

Medical Devices

n

High End Consumer Devices

n

Multirail Systems

n

Supports Freescale i.MX53/51, Marvell PXA and

Other Application Processors

L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks

of Linear Technology Corporation. All other trademarks are the property of their respective owners.

Typical applicaTion

V

2.7V TO 5.5V

Start-Up Sequence

IN

1µH

V

IN

0.5V TO V

0.8V TO V

IN

SW1

SW2

SW3

LDO1_STBY

LDO2

AT 1.6A

AT 25mA

BB_OUT

22µF

1µF

WAKE

(1V/DIV)

1.5µH

0.5V TO V

AT 1A

0.36V TO V

IN

AT 250mA

SW2

1µF

LTC3589

LDO3

SW3

0.5V/DIV

1.8V

AT 250mA

0.5V TO V

AT 1A

LDO3

LDO4

22µF

LDO2

SW1

2.8V

AT 250mA

2.7µH

3

SW4AB

SW4CD

1µF

2

I C

7

3589 TA01b

500µs/DIV

ENABLES

PWR_ON

1.8V TO 5V

BB_OUT

WAKE

4

ON

STATUS

GND

3589 TA01a

3589fh

1

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

Table oF conTenTs

Features............................................................................................................................ 1

Applications ....................................................................................................................... 1

Typical Application ............................................................................................................... 1

Description......................................................................................................................... 1

Absolute Maximum Ratings..................................................................................................... 3

Pin Configuration ................................................................................................................. 3

Order Information................................................................................................................. 3

Electrical Characteristics........................................................................................................ 4

Typical Performance Characteristics .......................................................................................... 9

Pin Functions.....................................................................................................................13

Block Diagram....................................................................................................................15

Operation..........................................................................................................................16

Introduction.......................................................................................................................................................... 16

LTC3589, LTC3589-1, and LTC3589-2 Functional Comparison ............................................................................. 17

Always-On LDO..................................................................................................................................................... 17

Step-Down Switching Regulators......................................................................................................................... 20

Buck-Boost Switching Regulator .......................................................................................................................... 24

Slewing DAC Reference Operation........................................................................................................................ 28

Pushbutton Operation........................................................................................................................................... 29

Enable and Power-On Sequencing ........................................................................................................................ 31

Fault Detection, Shutdown, and Reporting............................................................................................................ 32

2

I C Operation........................................................................................................................................................ 36

Thermal Considerations and Board Layout........................................................................................................... 42

Typical Application ..............................................................................................................46

Package Description ............................................................................................................48

Revision History .................................................................................................................49

Typical Application ..............................................................................................................50

Related Parts.....................................................................................................................50

3589fh

2

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

absoluTe MaxiMuM raTings ^{(Notes 1, 3)}

V , DV , SW1, SW2, SW3, SW4AB, SW4CD.... –0.3V to 6V

LDO4, PGOOD, VSTB, EN1, EN2, EN3, EN4, EN_LDO2,

EN_LDO34, EN_LDO3, ON, PBSTAT, WAKE, RSTO,

PWR_ON, IRQ, ........................................... –0.3V to 6V

IN

DD

SW1, SW2, SW3, SW4AB, SW4CD

(Transients < 1µs, Duty Cycle < 5%) ............... –2V to 7V

PV , PV , PV , PV ............... –0.3V to V + 0.3V

SDA, SCL ......................................–0.3V to DV + 0.3V

IN1

IN2

, V

IN3

IN4

IN

DD

V

......................... –0.3V to V + 0.3V

Operating Junction Temperature Range

IN_LDO2 IN_LDO34

LDO1_STBY, LDO1_FB, BUCK1_FB, BUCK2_FB,

BUCK3_FB, BB_FB, BB_OUT, LDO2, LDO2_FB, LDO3,

(Note 2).................................................. –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

pin conFiguraTion

LTC3589

LTC3589-1/LTC3589-2

TOP VIEW

40 39 38 37 36 35 34 33 32 31

V

1

2

3

4

5

6

7

8

9

30

29

28

SCL

V

1

2

3

4

5

6

7

8

9

30

29

28

SCL

IN_LDO2

LDO2

IN_LDO2

LDO2

PGOOD

VSTB

PGOOD

VSTB

LDO3

LDO4

LDO3

LDO4

27 PV

IN3

26 SW3

25

IN3

26 SW3

25

V

41

GND

V

41

GND

IN_LDO34

PV

SW2

PV

SW2

IN1

SW1

RSTO

24 PV

SW1

RSTO

24 PV

IN2

23

22

21

WAKE

23

22

21

WAKE

EN_LDO2

PBSTAT

EN_LDO2

PBSTAT

EN1 10

ON

EN1 10

ON

11 12 13 14 15 16 17 18 19 20

UJ PACKAGE

40-LEAD (6mm × 6mm) PLASTIC QFN

UJ PACKAGE

40-LEAD (6mm × 6mm) PLASTIC QFN

T

= 150°C, θ = 33°C/W

JA

JMAX

T

= 150°C, θ = 33°C/W

JA

JMAX

EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

http://www.linear.com/product/LTC3589#orderinfo

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

40-Lead (6mm × 6mm) Plastic QFN

TEMPERATURE RANGE

–40°C to 125°C

LTC3589EUJ#PBF

LTC3589EUJ#TRPBF

LTC3589UJ

LTC3589IUJ#PBF

LTC3589IUJ#TRPBF

LTC3589HUJ#TRPBF

LTC3589EUJ-1#TRPBF

LTC3589IUJ-1#TRPBF

LTC3589HUJ-1#TRPBF

LTC3589EUJ-2#TRPBF

LTC3589IUJ-2#TRPBF

LTC3589HUJ-2#TRPBF

LTC3589UJ

40-Lead (6mm × 6mm) Plastic QFN

–40°C to 125°C

–40°C to 150°C

–40°C to 125°C

–40°C to 150°C

–40°C to 125°C

–40°C to 150°C

LTC3589HUJ#PBF

LTC3589EUJ-1#PBF

LTC3589IUJ-1#PBF

LTC3589HUJ-1#PBF

LTC3589EUJ-2#PBF

LTC3589IUJ-2#PBF

LTC3589HUJ-2#PBF

LTC3589UJ

LTC3589UJ-1

LTC3589UJ-2

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

3589fh

3

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

elecTrical characTerisTics

The ldenotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= PV_IN1= PV_IN2= PV_IN3= PV_IN4= V_{IN_LDO2}= V_{IN_LDO34}

= DV_DD= 3.8V. All regulators disabled unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

l

V

Operating Input Supply Voltage, V

2.7

5.5

18

V

µA

IN

I

f

V

Standby Current

All Enables = 0V, PWR_ON = 0V, I = 0mA

LDO1

8

STANDBY

OSC

IN

Oscillator Frequency

1.8

2.25

2.6

MHz

Step-Down Switching Regulators 1, 2, and 3

l

I

Pulse-Skipping Mode V Quiescent Current

V

= 0.85V (Note 5)

120

23

200

µA

VIN

IN

FB

per Buck

Burst Mode^®V Quiescent Current per Buck

40

50

µA

nA

IN

I

FB

Feedback Pin Input Current

Maximum Duty Cycle

V

= 0.8V

= 0V

–50

100

FB

D

R

%

X

FB

SW Pull-Down Resistance

Soft-Start Rate

Regulators Disabled

(Note 6)

2.5

0.8

kΩ

V/ms

V

SW

t

SS

l

V

Maximum Feedback Voltage

BxDTV1 = BxDTV2 = 11111,

V

0.735

0.75

0.765

FB(MAX)

= 2.7V to 5.5V

IN

V

Feedback LSB Step Size

12.5

mV

V

FB(LSB)

Minimum Feedback Voltage

BxDTV1 = BxDTV2 = 00000,

V

0.351 0.3625 0.374

FB(MIN)

= 2.7V to 5.5V

IN

1.6A Step-Down Switching Regulator 1

Peak PMOS Current Limit SW1

I

2.0

2.7

180

110

A

mΩ

LIM1

RP1

RN1

R

DS(ON)

R

DS(ON)

of PMOS1

of NMOS1

I

= –100mA

= 100mA

SW1

1.0A/1.2A Step-Down Switching Regulators 2 and 3

l

I

Peak PMOS Current Limit SW2 and SW3 (LTC3589)

Peak PMOS Current Limit SW2 and SW3 (LTC3589-1/

LTC3589-2)

1.5

1.8

1.9

A

LIM2, 3

2.3

250

130

A

mΩ

RP2, 3

RN2, 3

R

of PMOS2 and PMOS3

of NMOS2 and NMOS3

I

= –100mA

= 100mA

DS(ON)

SW1

R

SW1

1.2A Buck-Boost Switching Regulator 4 (Buck-Boost)

PWM Mode V Quiescent Current

l

I

V

= 0.85V (Note 5)

BB_FB

115

19

170

35

µA

VIN

IN

Burst Mode V Quiescent Current

IN

l

V

Feedback Voltage

V

= 2.7V to 5.5V

IN

0.776

1.8

0.8

0.824

5.0

V

BB_FB

OUTBB

LIM4

Output Voltage Range

l

I

Peak PMOS Current Limit SW4AB

Forward Burst Current Limit (Switch A)

Reverse Current Limit (Switch D)

Reverse Burst Current Limit (Switch D)

2.3

2.9

600

1

A

Burst Mode Operation

mA

A

PEAK4

LIMR4

ZERO4

0

mA

mΩ

kΩ

V/ms

nA

RP4

RN4

R

DS(ON)

R

DS(ON)

of Switch A and Switch D

of Switch B and Switch C

I

= I

= 100mA

160

110

2.5

2

SW4AB

SW4CD

= –100mA

R

BB_OUT Pull-Down Resistance

Soft-Start Rate

Regulator Disabled

(Note 6)

OUT4

t

SS

I

FB

Feedback Pin Input Current

V

FB

= 0.85V

–50

50

3589fh

4

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= PV_IN1= PV_IN2= PV_IN3= PV_IN4= V_{IN_LDO2}= V_{IN_LDO34}

= DV_DD= 3.8V. All regulators disabled unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

LDO Regulators

t

Soft-Start Time LDO2, LDO3, LDO4

100

2.5

µs

LDO_SS

R

Output Pull-Down Resistance LDO2, LDO3, LDO4 LDO Disabled

kΩ

LDO_PD

Always-On Regulator (LDO1_STBY)

l

V

LDO1 Feedback Voltage

LDO1 Line Regulation

0.76

25

0.8

0.84

V

LDO1_FB

I

= 1mA, LDO1_STBY = 1.2V,

0.15

%/V

LDO1

LDO1_STBY

IN

V

= 2.7V to 5.5V

LDO1 Load Regulation

I

= 0.1mA to 25mA,

0.1

%

LDO1

LDO1_STBY = 1.2V

l

I

Available Output Current

Short-Circuit Output Current Limit

Dropout Voltage (Note 4)

LDO1_FB Input Current

mA

mV

nA

LDO1

65

100

50

LDO1_SC

V

I

= 25mA, LDO1_STBY = 3.3V

200

DROP1

LDO1

I

V

= 0.85V

–50

1.7

LDO1_FB

LDO Regulator 2 (LDO2)

l

V

Input Voltage Range

V

IN

V

IN_LDO2

l

I

V

Quiescent Current

Shutdown Current

Regulator Enabled

Regulator Disabled

12

0

20

1

µA

VIN_LDO2

IN_LDO2

l

I

V

Quiescent Current

IN

EN_LDO2 = High

50

0.75

85

µA

V

VIN

V

LDO2 Maximum Feedback Voltage

LDO2 Feedback LSB Step Size

LDO2 Minimum Feedback Voltage

L2DTV1 = L2DTV2 = 11111

0.735

0.351

0.765

FB2(MAX)

FB2(LSB)

FB2(MIN)

12.5

mV

V

l

L2DTV1 = L2DTV2 = 00000

0.3625

0.374

V

= V = 2.7V to 5.5V,

IN

IN_LDO2

I

= 1mA

LDO2

LDO2 Line Regulation

=1mA, V

= 2.7V to 5.5V

0.01

%/V

%

IN_LDO2

LDO2 Load Regulation

= 1mA to 250mA

l

I

LDO2 Available Output Current

LDO2 Short-Circuit Current Limit

Dropout Voltage (Note 4)

250

300

mA

LDO2

450

600

LDO2_SC

V

I

= 200mA, V

= 2.5V

= 1.2V

140

350

180

500

mV

DROP2

LDO2

I

LDO2_FB Input Current

V

= 0.8V

–50

50

nA

LDO2_FB

LDO Regulator 3 (LDO3)

l

V

Input Range (LTC3589)

2.35

3.0

V

IN_LDO34

VIN_LDO34

VIN

IN_LDO34

IN

Input Range (LTC3589-1/LTC3589-2)

l

I

V

Quiescent Current

Shutdown Current

Regulator Enabled

Regulator Disabled

15

0

29

1

µA

IN_LDO34

l

V

Quiescent Current

EN_LDO3 = High

50

85

µA

IN

l

V

LDO3

LDO3 Output Voltage (LTC3589)

V

= V = 2.7V to 5V,

1.746

2.716

1.8

2.8

1.854

2.884

V

IN_LDO34

IN

LDO3 Output Voltage (LTC3589-1/LTC3589-2)

I

= 1mA

LDO3

LD03 Line Regulation

=1mA, V

= 2.7V to 5.5V

0.01

0.05

%/V

%

IN_LDO34

LDO3 Load Regulation

= 1mA to 250mA

l

I

LDO3 Available Output Current

LDO3 Short-Circuit Current Limit

250

300

mA

LDO3

450

600

LDO3_SC

V

LDO3 Dropout Voltage (LTC3589) (Note 4)

LDO3 Dropout Voltage (LTC3589-1/LTC3589-2)

(Note 4)

I

= 200mA, V

= 1.8V

= 2.8V

190

140

250

180

mV

DROP3

LDO3

3589fh

5

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= PV_IN1= PV_IN2= PV_IN3= PV_IN4= V_{IN_LDO2}= V_{IN_LDO34}

= DV_DD= 3.8V. All regulators disabled unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

LDO Regulator 4 (LDO4)

l

V

Input Range (LTC3589)

Input Range (LTC3589-1/LTC3589-2)

2.35

1.7

V

IN

V

IN

V

IN_LDO34

I

V

Quiescent Current

Shutdown Current

Regulator Enabled

Regulator Disabled

l

14

0

24

1

µA

VIN_LDO34

IN_LDO34

l

V

Quiescent Current

EN_LDO4 = High

50

85

µA

VIN

IN

l

V

LDO 4 Output Voltage

LD04 Line Regulation

I

= 1mA, L2DTV2[6:5] = 00

2.716

2.425

1.746

3.201

2.8

2.5

1.8

3.3

2.884

2.575

1.854

3.399

V

LDO4

(LTC3589)

L2DTV2[6:5] = 01

L2DTV2[6:5] = 10

L2DTV2[6:5] = 11

l

V

I

= 1mA, L2DTV2[6:5] = 00

1.164

1.746

2.425

3.104

1.2

1.8

2.5

3.2

1.236

1.854

2.575

3.296

V

LDO4

(LTC3589-1)

(LTC3589-2)

L2DTV2[6:5] = 01

L2DTV2[6:5] = 10

L2DTV2[6:5] = 11

I

=1mA, V

= 2.7V to 5.5V,

IN_LDO34

0.01

%/V

LDO4

V

= 1.8V

OUT

LDO4 Load Regulation

I

= 1mA to 250mA

0.05

%

mA

LDO4

l

I

LDO4 Available Output Current

LDO4 Short-Circuit Current Limit

LDO4 Dropout Voltage (Note 4)

250

300

LDO4

450

600

LDO4_SC

V

I

= 200mA, V

= 3.3V

120

190

120

160

250

160

mV

DROP4

LDO4

I

= 1.8V

LDO4

I

= 3.2V (LTC3589-1/

LDO4

LTC3589-2)

Enable Inputs

l

V

Threshold Rising

All Enables Low

0.8

1.2

V

ENx_THR

l

V

Threshold Rising

Threshold Falling

Any Enable High

0.5

0.45

0.530

V

ENx_THR2

ENx_THF2

0.420

R

Input Pull-Down Resistance

4.5

MΩ

ENX

VSTB, PWR_ON Inputs

l

V

VSTB Pin Threshold Rising

VSTB Pin Threshold Falling

0.8

0.7

1.2

V

VSTB_THR

VSTB_THF

0.4

R

Pull-Down Resistance

4.5

MΩ

VSTB

l

V

PWR_ON Pin Threshold Rising

PWR_ON Pin Threshold Falling

0.8

0.7

V

PWR_ONTHR

PWR_ONTHF

R

Pull-Down Resistance

4.5

MΩ

PWR_ON

2

I C Port

l

DV

DV Input Supply Voltage

1.6

5.5

V

µA

V

DD

I

DV Quiescent Current

DD

SCL/SDA = 0kHz

0.5

0.8

DVDD

V

DV UVLO Level

DD

DVDD_UVLO

ADDRESS

Device Address – Write

Device Address – Read

01101000

01101001

V

IH

V

IL

SDA, SCL SDA and SCL Input Threshold Rising

SDA, SCL SDA and SCL Input Threshold Falling

70

%DV

DD

30

I

SDA and SCL Input Current

SDA Output Low Voltage

SDA = SCL = 0V to 5.5V

= 3mA

–250

250

0.4

400

nA

V

IHSCx ILSCx

l

V

SDA

I

SDA

OL

f

SCL Clock Operating Frequency

kHz

SCL

3589fh

6

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

elecTrical characTerisTics ^Theldenotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= PV_IN1= PV_IN2= PV_IN3= PV_IN4= V_{IN_LDO2}= V_{IN_LDO34}

= DV_DD= 3.8V. All regulators disabled unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

0.6

0

TYP

MAX

UNITS

µs

t

Repeated Start Condition Set-Up Time

Stop Condition Set-Up Time

Data Hold Time Output

Data Hold Time Input

Data Set-Up Time

SU_STA

µs

SU_STO

900

ns

HD_DAT(O)

0

ns

HD_DAT(I)

100

1.3

0.6

ns

SU_DAT

SCL Clock Low Period

SCL Clock High Period

Data Fall Time

µs

LOW

µs

HIGH

C = Capacitance of One BUS Line (pF)

B

20 + 0.1C

B

300

50

ns

f

Data Rise Time

C = Capacitance of One BUS Line (pF)

B

20 + 0.1C

B

ns

r

Input Spike Suppression Pulse Width

ns

SP

Pushbutton Interface

l

V

ON Threshold Rising

ON Threshold Falling

0.8

0.7

1.2

V

ON_THR

ON_THF

0.4

I

ON Input Current

ON = V

ON = 0V

–100

100

nA

µA

ON

IN

40

50

0.2

400

5

t

ON Low Time to PBSTAT Low

ON High Time to PBSTAT High

ON Low Time to WAKE High

ON Low Time to Hard Reset

ms

µs

ms

s

ON_PBSTAT1

ON_PBSTAT2

ON_WAKE

ON_HR

PBSTAT Minimum Pulse Width

PBSTAT Blanking from WAKE Low

Minimum WAKE Low Time

50

1

ms

s

PBSTAT_PW

PBSTAT_BK

WAKE_OFF

WAKE_ON

PWR_ON

1

s

WAKE High Time with PWR_ON = 0V

5

s

PWR_ON to WAKE High (LTC3589)

PWR_ON to WAKE High (LTC3589-1/LTC3589-2)

50

2

ms

t

PWR_ON to WAKE Low (LTC3589)

PWR_ON to WAKE Low (LTC3589-1/LTC3589-2)

50

2

ms

PWR_OFF

Status Output Pins (PBSTAT, WAKE, PGOOD, RSTO, IRQ)

V

PBSTAT Output Low Voltage

I

= 3mA

= 3.8V

0.1

0.4

0.1

0.4

0.1

0.4

0.1

V

µA

V

PBSTAT

I

PBSTAT Output High Leakage Current

WAKE Output Low Voltage

V

–0.1

PBSTAT

V

I

= 3mA

= 3.8V

WAKE

I

WAKE Output High Leakage Current

PGOOD Output Low Voltage

V

µA

V

WAKE

V

I

= 3mA

= 3.8V

PGOOD

I

PGOOD Output High Leakage Current

V

µA

PGOOD

V

PGOOD Threshold Rising

PGOOD Threshold Falling

–6

–8

%

PGOOD

NRSTO

UVLO

LDO1 Power Good Threshold Rising

LDO1 Power Good Threshold Falling

–6

–8

%

Undervoltage Lockout Rising

Undervoltage Lockout Falling

2.65

2.55

2.7

V

3589fh

7

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

The ldenotes the specifications which apply over the specified operating

elecTrical characTerisTics

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= PV_IN1= PV_IN2= PV_IN3= PV_IN4= V_{IN_LDO2}= V_{IN_LDO34}

= DV_DD= 3.8V. All regulators disabled unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Undervoltage Warning Rising

Undervoltage Warning Falling

3

2.9

UVWARN

V

RSTO Output Low Voltage

I

= 3mA

= 3.8V

0.1

0.4

0.1

0.4

0.1

V

µA

V

RSTO

I

RSTO Output High Leakage Current

IRQ Output Low Voltage

V

–0.1

RSTO

V

I

= 3mA

= 3.8V

0.1

IRQ

I

IRQ Output High Leakage Current

V

µA

IRQ

Note 1: Stresses beyond those listed Under Absolute Maximum ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum rating condition for extended periods may affect device

reliability and lifetime.

Note that the maximum ambient temperature consistent with these

specifications is determined by specific operating conditions in

conjunction with board layout, the rated package thermal impedance and

other environmental factors.

Note 2: The LTC3589 are tested under pulsed load conditions such

Note 3: The LTC3589 include overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the specified maximum operating temperature

may impair device reliability.

that T ≈ T . The LTC3589E are guaranteed to meet specifications from

J

A

0°C to 85°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3589I are guaranteed over the –40°C to 125°C operating junction

temperature range and the LTC3589H are guaranteed over the full

–40°C to 150°C operating junction temperature range. High junction

temperatures degrade operating lifetimes; operating lifetime is derated for

Note 4: Dropout voltage is defined as (V – V ) for LDO1 or

IN

LDO

(V

– V ) for other LDOs when V

is 3% lower than V

IN_LDO

LDO

measured with V = V

= 4.3V.

IN

IN_LDO

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency.

Note 6: Soft-start measured in test mode with regulator error amplifier in

unity gain mode.

junction temperatures greater than 125°C. The junction temperature (T

J

in °C) is calculated from the ambient temperature (T in °C) and power

A

dissipation (PD, in Watts) according to the formula:

T = T + (PD • θ ), where the package junction to ambient thermal

J

A

JA

impedance θ = 33°C/W.

JA

3589fh

8

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

V_IN= 3.8V, T_A= 25°C, unless otherwise noted.

Typical perForMance characTerisTics

Step-Down Switching Regulator

I_VINvs V_IN

Standby I_VINvs V_IN

LDO2 to LDO4 I_VINvs V_IN

250

200

150

100

50

900

14

12

PULSE-SKIPPING MODE

800

ENABLE THREE LDOs

ENABLE THREE BUCKS

ENABLE TWO BUCKS

700

600

500

400

300

200

10

8

ENABLE TWO LDOs

ENABLE ONE LDO

6

ENABLE ONE BUCK

4

2

100

0

3.0

3.5

4.5

5.0

5.5

3.0

3.5

4.5

5.0

5.5

3.0

3.5

4.5

5.0

5.5

2.5

4.0

(V)

2.5

4.0

(V)

2.5

4.0

(V)

V

IN

3589 G01

3589 G02

3589 G03

Step-Down Switching Regulator

I_VINvs V_IN

Input Supply Current

vs Temperature

Buck-Boost I_VINvs V_IN

120

100

80

60

40

20

0

1200

1000

800

600

400

200

0

450

400

350

300

250

200

150

100

50

Burst Mode OPERATION

ENABLE THREE BUCKS

ALL REGULATORS ENABLED

PULSE-SKIPPING MODE

PWM MODE

ENABLE TWO BUCKS

ENABLE ONE BUCK

ALL REGULATORS ENABLED

Burst Mode OPERATION

STANDBY (ONLY LDO1 ON)

0

3.0

3.5

4.5

5.0

5.5

2.5

4.0

(V)

–25

0

75 100 125 150

25 50

TEMPERATURE (°C)

3.0

3.5

5.0

5.5

–50

2.5

4.0

(V)

4.5

V

IN

3589 G04

3589 G05

3589 G06

Oscillator Frequency

vs Temperature

Switching Frequency Change vs V_IN

Buck-Boost Efficiency vs I_OUT

1.0

0.8

100

90

80

70

60

50

40

30

20

2.30

2.25

2.20

2.15

2.10

2.05

2.00

1.95

V

= 3.8V

IN

BURST

0.6

0.4

0.2

PWM MODE

0

–0.2

–0.4

–0.6

–0.8

V

= 5.0V

= 2.5V

= 3.3V

OUT

V

OUT

10

0

V

OUT

3.0

3.5

4.5

5.0

5.5

2.5

4.0

(V)

–10

30

TEMPERATURE (°C)

110

150

0.01

0.1

1

10

100

1000

–50

70

LOAD CURRENT (mA)

V

IN

3589 G9

3589 G08

3589 G07

3589fh

9

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

Typical perForMance characTerisTics V_IN= 3.8V, T_A= 25°C, unless otherwise noted.

Step-Down Switching Regulator 1

Efficiency vs I_OUT

Step-Down Switching Regulator 2

Efficiency vs I_OUT

Buck-Boost Efficiency vs I_OUT

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

V

= 1.2V

V

= 1.8V

OUT

V

= 3.3V

OUT

BURST

PWM MODE

FORCED

CONTINUOUS

FORCED

CONTINUOUS

V

= 5.0V

= 4.2V

= 3.0V

IN

PULSE-SKIPPING

10

0

10

0

10

0

0.01

0.1

1

10

100

1000

0.01

0.1

1

10

100

1000

0.01

0.1

1

10

100

1000

LOAD CURRENT (mA)

3589 G11

3589 G12

3589 G10

Buck-Boost R_DS(ON)

vs Temperature

Step-Down Switching Regulator 3

Efficiency vs I_OUT

Step-Down Switching Regulator

R_DS(ON)vs Temperature

100

90

80

70

60

50

40

30

20

0.40

0.35

0.30

0.25

0.20

0.25

V

= 3.3V

OUT

0.20

0.15

0.10

BURST

PMOS

BUCK2, 3 PMOS

BUCK1 PMOS

PULSE-

SKIPPING

FORCED

NMOS

CONTINUOUS

BUCK2, 3 NMOS

0.15

0.10

BUCK1 NMOS

0.05

0

0.05

0

10

0

0.01

0.1

1

10

100

1000

–50

–10

30

70

110

150

–10

30

TEMPERATURE (°C)

110

150

–50

70

LOAD CURRENT (mA)

TEMPERATURE (°C)

3589 G13

3589 G14

3589 G15

Step-Down Switching

Regulator Current Limit

vs Temperature

Buck-Boost Current Limit

vs Temperature

Step-Down Switching Regulator

Soft-Start

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

BUCK1

OUT

PEAK LIMIT

BUCK2, BUCK3

(LTC3589-1/LTC3589-2)

500mV/DIV

200mA/DIV

CLAMP LIMIT

BUCK2, BUCK3

I

L

3589 G18

200µs/DIV

–25

0

25 50

TEMPERATURE (°C)

125 150

–50

–25

0

25 50

125 150

75 100

–50

75 100

TEMPERATURE (°C)

3589 G16

3589 G17

3589fh

10

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

Typical perForMance characTerisTics V_IN= 3.8V, T_A= 25°C, unless otherwise noted.

Buck-Boost Switching Regulator

Soft-Start

Step-Down Switching Regulator 1

Load Step

Dynamic Voltage Slew

PULSE-SKIPPING MODE

1V/DIV

V

OUT

V

OUT

V

50mV/DIV

1A/DIV

OUT

1V/DIV

PGOOD

5V/DIV

I

LOAD

500mA/DIV

V

STB

I

L

3589 G19

3589 G20

3589 G21

100µs/DIV

200µs/DIV

= 1.75mV/µs

40µs/DIV

V

LOAD CAPACITANCE = 44µF

RRCR

Step-Down Switching Regulator 1

Load Step

Buck-Boost Switching Regulator 1

Load Step

Maximum Buck-Boost Load

Current vs V_IN

2.5

2.0

1.5

1.0

0.5

0

Burst Mode OPERATION

V

OUT

200mV/DIV

50mV/DIV

1A/DIV

I

LOAD

I

LOAD

1A/DIV

V

= 1.8V

= 3.3V

= 5V

3589 G23

3589 G22

OUT

40µs/DIV

LOAD CAPACITANCE = 22µF

LOAD CAPACITANCE = 44µF

3.0

3.5

4.5

5.0

5.5

2.5

4.0

(V)

V

IN

3589 G24

LDO1 Short-Circuit Current

vs Temperature

LDO1 Dropout Voltage

vs Temperature

LDO1 Output Change vs V_IN

0.5

80

70

60

50

500

V

= 25mA

LDO1

V

= 1.8V

LDO1

0.0

–0.5

–1.0

–1.5

–2.0

400

300

200

100

0

V

= 3.3V

LDO1

40

30

20

V

= 1.2V

= 1.8V

= 2.8V

= 3.3V

LDO1

3

4

5

2

–25

0

25 50

125 150

75 100

–25

0

25 50

125 150

75 100

–50

V

(V)

TEMPERATURE (°C)

IN

3589 G26

3589 G27

3589 G25

3589fh

11

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

Typical perForMance characTerisTics V_IN= 3.8V, T_A= 25°C, unless otherwise noted.

LDO2, LDO3, LDO4 Dropout

Voltage vs Temperature

LDO2, LDO3, LDO4 Dropout

Voltage vs Load Current

LDO2, LDO3, LDO4 Short-Circuit

Current vs Temperature

500

400

300

200

100

0

500

450

400

350

500

400

300

200

100

0

V

= 1.2V

LDO

V

= 1.2V

LDO

V

LDO

= 1.8V

V

= 1.8V

LDO

300

250

200

V

LDO

= 3.3V

V

= 3.3V

LDO

50

100

LOAD CURRENT (mA)

250

–25

0

25 50

125 150

75 100

–25

0

25 50

TEMPERATURE (°C)

= 200mA

125 150

0

150

200

–50

75 100

TEMPERATURE (°C)

I

3589 G29

3589 G30

3589 G28

LOAD

LDO2, LDO3, LDO4 Enable

Response

LDO2, LDO3, LDO4 Load Step

Response

LDO1 Load Step Response

V

=2.8V

LDO4

1.8V

V

1.2V

V

LDO3

=1.8V

V

LDO1

50mV/DIV

LDO

50mV/DIV

1V/DIV

V

=1.2V

LDO2

220mA

20mA

I

LDO

LDO1

V

,V

EN_LDO2 EN_LDO34

100µs/DIV

100mA/DIV

10mA/DIV

10mA

1mA

3589 G32

3589 G33

3589 G31

10µs/DIV

40µs/DIV

LOAD CAPACITANCE = 1µF

3589fh

12

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

pin FuncTions

V

(Pin 1): Power Input for LDO2. This pin should

SW4AB (Pin 12): Switch Pin for Buck-Boost Switching

Regulator 4. Connected to the buck-boost internal power

switches A and B. Connect an inductor between this pin

and SW4CD (Pin 19).

IN_LDO2

be bypassed to ground with a 1µF or greater ceramic

capacitor.

LDO2 (Pin 2): Output Voltage of LDO2. Nominal output

voltageissetwitharesistorfeedbackdividerthatservosto

EN3 (Pin 13): Enable Step-Down Switching Regulator 3.

Active high input to enable step-down switching

regulator 3. A weak pull-down forces EN3 low when left

floating.

2

an I C register controlled DAC reference. This pin must be

bypassedtogroundwitha1µForgreaterceramiccapacitor.

LDO3 (Pin 3): Output Voltage of LDO3. Nominal output

voltage is fixed at 1.8V or 2.8V (LTC3589-1/LTC3589-2).

This pin must be bypassed to ground with a 1µF or greater

ceramic capacitor.

EN4 (Pin 14): Enable Buck-Boost Switching Regulator 4.

Active high input to enable buck-boost switching

regulator 4. A weak pull-down forces EN4 low when left

floating.

LDO4 (Pin 4): Output Voltage of LDO4. Output voltage is

2

selected via the I C port. This pin must be bypassed to

PV (Pin 15): Power Input for Switching Regulator 4.

IN4

ground with a 1µF or greater ceramic capacitor.

Tie this pin to V supply. This pin should be bypassed to

IN

ground with a 4.7µF or greater ceramic capacitor.

V

(Pin 5): Power Input for LDO3 and LDO4. This

IN_LDO34

pin should be bypassed to ground with a 1µF or greater

BB_OUT (Pin16):OutputVoltageofBuck-BoostSwitching

Regulator 4. This pin must be bypassed to ground with a

22µF or greater ceramic capacitor.

ceramic capacitor.

PV

(Pin 6): Power Input for Step-Down Switching

IN1

Regulator 1. Tie this pin to V supply. This pin should

IRQ (Pin 17): Interrupt Request Output. Open-drain

driver is pulled low for power good, undervoltage, and

overtemperature warning and fault conditions. Clear IRQ

IN

be bypassed to ground with a 4.7µF or greater ceramic

capacitor.

2

by writing to the I C CLIRQ command register.

SW1 (Pin 7): Switch Pin for Step-Down Switching

Regulator 1. Connect one side of step-down switching

regulator 1 inductor to this pin.

EN_LDO34 (Pin 18): LTC3589 Enable LDO3 and LDO4

LogicInput.ActivehightoenableLDO3andLDO4.Disable

2

LDO4 via I C software commands using I C command

registers OVEN or L2DTV2. A weak pull-down forces

EN_LDO34 low when left floating.

RSTO (Pin 8): Reset Output. Open-drain output pulls low

when the always-on regulator LDO1 is below regulation

and during a hard reset initiated by a pushbutton input.

EN_LDO3 (Pin 18): LTC3589-1/LTC3589-2 Enable LDO3

LogicInput.ActivehightoenableLDO3.Aweakpull-down

forces EN_LDO3 low when left floating.

EN_LDO2 (Pin 9): Enable LDO2 Logic Input. Active high

input to enable LDO2. A weak pull-down forces EN_LDO2

low when left floating.

SW4CD (Pin 19): Switch Pin for Buck-Boost Switching

Regulator 4. Connected to the buck-boost internal power

switches C and D. Connect an inductor between this node

and SW4AB (Pin 12).

EN1 (Pin 10): Enable Step-Down Switching Regulator 1.

Active high input to enable step-down switching

regulator 1. A weak pull-down forces EN1 low when left

floating.

PWR_ON (Pin 20): External Power-On. Handshaking pin

toacknowledgesuccessfulpower-onsequence.PWR_ON

must be driven high within five seconds of WAKE going

high to keep power on. It can be used to activate the WAKE

output by driving high. Drive low to shut down WAKE.

EN2 (Pin 11): Enable Step-Down Switching Regulator 2.

Active high input to enable step-down switching

regulator 2. A weak pull-down forces EN2 low when left

floating.

3589fh

13

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

pin FuncTions

2

ON (Pin 21): Pushbutton Input. A weak internal pull-

up forces ON high when left floating. A normally open

pushbutton is connected from ON to ground to force a

low state on this pin.

DV (Pin 32): Supply Voltage for I C Serial Port. This

DD

2

pin sets the logic reference level of SCL and SDA I C pins.

2

DV resetsI Cregisterstopoweronstatewhendrivento

DD

<1V.SCLandSDAlogiclevelsarescaledtoDV .Connect

DD

a 0.1µF decoupling capacitor from this pin to ground.

PBSTAT (Pin 22): Pushbutton Status. Open-drain output

to be used for processor interrupts. PBSTAT mirrors the

status of ON pushbutton pin. PBSTAT is delayed 50ms

from ON pin for debounce.

BUCK2_FB (Pin 33): Feedback Input for Step-Down

Switching Regulator 2. Set full-scale output voltage using

resistor divider connected from the output of step-down

switching regulator 2 to this pin to ground.

WAKE(Pin23):SystemWakeUp.Open-draindriveroutput

releases high when signaled by pushbutton activation or

PWR_ON input. It may be used to initiate a pin-strapped

power-upsequencebyconnectingtoaregulatorenablepin.

BUCK3_FB (Pin 34): Feedback Input for Step-Down

Switching Regulator 3. Set full-scale output voltage using

resistor divider connected from the output of step-down

switching regulator 3 to this pin to ground.

PVIN2 (Pin 24): Power Input for Step-Down Switching

Regulator 2. Tie this pin to V supply. This pin should

LDO1_FB (Pin 35): Feedback Input for LDO1. Set

output voltage using a resistor divider connected from

LDO1_STDBY to this pin to ground.

IN

be bypassed to ground with a 4.7µF or greater ceramic

capacitor.

SW2 (Pin 25): Switch Pin for Step-Down Switching

Regulator 2. Connect one side of step-down switching

regulator 2 inductor to this pin.

LDO1_STDBY (Pin 36): Always-On LDO1 Output. This pin

providesanalways-onsupplyvoltageusefulforlightloads

such as a watchdog microprocessor or a real-time clock.

Connect a 1µF capacitor from LDO1_STBY to ground.

SW3 (Pin 26): Switch Pin for Step-Down Switching

Regulator 3. Connect one side of step-down switching

regulator 3 inductor to this pin.

V

(Pin 37): Supply Voltage Input. This pin should

IN

be bypassed to ground with a 1µF or greater ceramic

capacitor.

PVIN3 (Pin 27): Power Input for Step-Down Switching

Regulator 3. Tie this pin to the V supply. This pin should

LDO2_FB(Pin38):FeedbackInputforLDO2.Setfull-scale

output voltage using a resistor divider connected from

LDO2_OUT to this pin to ground.

IN

be bypassed to ground with a 4.7µF or greater ceramic

capacitor.

VSTB (Pin 28): Voltage Standby. When VSTB is low, DAC

reference registers are selected by bit values in command

register VCCR. When VSTB is high, the DAC registers are

forced xxDVT2 registers. Tie VSTB to ground if unused.

BUCK1_FB (Pin 39): Feedback Input for Step-Down

Switching Regulator 1. Set full-scale output voltage using

resistor divider connected from the output of step-down

switching regulator 1 to this pin to ground.

PGOOD (Pin 29): Power Good Output. Open-drain output

pulls down when any regulator falls below power good

threshold and during regulator dynamic voltage slew

BB_FB(Pin40):FeedbackInputforBuck-BoostSwitching

Regulator 4. Set the output voltage using resistor divider

connected from BB_OUT to this pin to ground.

2

unless disabled in I C register. Pulls down when all

GND(ExposedPadPin41):Ground.TheExposedPadmust

be connected to a continuous ground plane on the second

layer of the printed circuit board by several interconnect

viasdirectlyundertheLTC3589formaximumheattransfer.

regulators are disabled.

2

SCL (Pin 30): Clock Input Pin for the I C Serial Port. The

2

I C logic levels are scaled with respect to DV .

DD

2

SDA (Pin 31): Data Input Pin for the I C Serial Port. The

2

I C logic levels are scaled with respect to DV .

DD

3589fh

14

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

block DiagraM

V

IN

PV

IN4

1.8V TO 5.0V

AT 1.2A

BB_OUT

V

BUCK-BOOST

REF

OK

0.8V TO V

AT 25mA

IN

SW4AB

SW4CD

V

REF

LDO1_STDBY

LDO1_FB

ALWAYS ON LDO1

EN

OK

BB_FB

IRQ

PV

IN1

ON (PB)

PBSTAT

WAKE

BUCK 1

CONTROL + SEQUENCE

0.5V TO V

AT 1.6A

IN

EN

OK

SW1

PWR_ON

VSTB

V

REF

DAC

BUCK1_FB

EN1

EN-PINS

PV

EN2

IN2

2

EN-I C

EN3

BUCK 2

EN4

0.5V TO V

IN

EN_LDO2

EN

OK

SW2

AT 1A/1.2A

EN_LDO34

EN_LDO3

(LTC3589-1/

LTC3589-2)

V

REF

DAC

n

BUCK2_FB

DV

DD

PV

IN3

SDA

SCL

2

I C

BUCK 3

PGOOD

0.5V TO V

IN

AT 1A/1.2A

EN

OK

SW3

V

REF

DAC

RSTO

7

BUCK3_FB

POWER

GOOD

V

IN_LDO2

LDO2

LDO3

V

REF

0.36V TO V

IN

AT 250mA

LDO2

EN

OK

LDO2_FB

V

IN_LDO34

LDO4

V

REF

1.8V, 2.5V, 2.8V, 3.3V (LTC3589)

1.2V, 1.8V, 2.5V, 3.2V (LTC3589-1/

LTC3589-2) AT 250mA

EN

OK

EN

OK

1.8V (LTC3589)

LDO4

LDO3

2.8V (LTC3589-1/

LTC3589-2) AT 250mA

3589 BD

GND (EXPOSED PAD)

3589fh

15

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

INTRODUCTION

The power-on default frequency is 2.25MHz. Each of the

step-downregulatorshavedynamicallyslewingDACinput

referencesandexternalfeedbackpinstosetoutputvoltage

range. The step-down regulators three operating modes,

pulse-skipping, burst, or forced continuous, are set using

The LTC3589 is a complete power management solution

for portable microprocessors and peripheral devices. It

generates a total of eight voltage rails for supplying power

totheprocessorcore,SDRAM,systemmemory,PCcards,

always-onreal-timeclockandHDDfunctions.Supplyingthe

voltagerailsareanalways-onlowquiescentcurrent25mA

LDO, one1.6Aandtwo1A(1.2AforLTC3589-1/LTC3589-

2) step-down regulators, a 1.2A buck-boost regulator,

and three 250mA low dropout regulators. Supporting

the multiple regulators is a highly configurable power-

on sequencing capability, dynamic voltage slewing DAC

output voltage control, a pushbutton interface controller,

2

theI Cinterface. Inpulse-skippingmodetheregulatorwill

support 100% duty cycle. For best efficiency at low output

loads select Burst Mode operation. Forced continuous

mode minimizes output voltage ripple at light loads.

The 4-switch buck-boost DC/DC voltage mode converter

generates a user-programmable output voltage rail from

1.8V to 5V. Utilizing a proprietary switching algorithm,

the buck-boost converter maintains high efficiency and

low noise operation with input voltages that are above,

below or equal to the required output rail. The buck-boost

error amplifier uses a fixed 0.8V reference and the output

voltage is set by an external resistor divider. Burst Mode

2

regulator control via an I C interface, and extensive status

and interrupt outputs.

The LTC3589 operates over an input supply range of 2.7V

to 5.5V. The input supplies for the 250mA LDO regulators

may operate as low as 1.7V to limit power loss at low

output voltages.

2

operation is enabled through the I C control registers. No

external compensation components are required for the

buck-boost converter.

The always-on LDO1 provides a resistor programmable

output voltage as low as 0.8V and is capable of supplying

25mA. With only the always-on LDO active the LTC3589

draws just 8µA (typical). Always-on LDO1 will continue to

Thereferenceinputsforthethreestep-downregulatorsand

LDO2 are 5-bit D to A converters with up-down ramping

at selectable slew rates. The slew endpoint voltages and

2

select bits are stored in I C registers for each DAC. A

operate with V levels as low as 2.0V (typical) to maintain

IN

2

select bit in the I C command registers chooses which

memory and RTC function as long as possible.

register to use for each target voltage. Variable reference

slew rates from 0.88mV/µs to 7mV/µs are selectable in

Each of the 250mA LDO regulators has unique output

voltage configurations. LDO3 has a fixed 1.8V (2.8V for

LTC3589-1/LTC3589-2) output. LDO4 has four output

2

the I C register. Each of the four DACs has independent

voltage, voltage select, and slew rate control registers.

2

levels selectable via the I C interface. Its possible outputs

TheLTC3589isequippedwithapushbuttoncontrolcircuit

that will activate the WAKE output, indicate pushbutton

status via the PBSTAT pin, and initiate a hard reset

shutdownoftheregulators. GroundingtheONpinwiththe

pushbutton for 400ms will force the WAKE pin to release

HIGH. The WAKE pin output can be tied to the enable pin

of the first regulator in a power-on sequence. Once in the

power-on state, subsequent pushes of the button longer

than 50ms are mirrored by the PBSTAT output. Holding

ON LOW for five seconds disables all the regulators, pulls

down the WAKE pin, and pulls down RSTO for one second

to indicate to the processor that a hard reset occurred. All

regulator enables and pushbutton inputs are inhibited for

are 1.8V, 2.5V, 2.8V, and 3.3V (1.2V, 1.8V, 2.5V, 3.2V for

LTC3589-1/LTC3589-2).LDO2hasadynamicallyslewing

DAC set point reference and an external feedback pin to

set the output voltage range with a resistive divider. Each

LDO draws 50µA (typical) quiescent current.

The LTC3589 includes three internally compensated

constant frequency current mode step-down switching

regulators two capable of supplying 1A of output current

and one capable of supplying 1.6A. The LTC3589-1/

LTC3589-2 step-down regulators can supply 1.2A, 1.2A,

and 1.6A. Step-down regulator switching frequencies of

2.25MHzor1.125MHzareindependentlyselectedforeach

2

step-down regulator using the I C command registers.

one second following the hard reset.

3589fh

16

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

The LTC3589 has flexible options for enabling and

sequencing the regulator enables. The regulators are

enabled using input pins or the I C serial port. To define

LTC3589, LTC3589-1, AND LTC3589-2 FUNCTIONAL

COMPARISON

2

Table 1. summarizes the functional differences between

the LTC3589, LTC3589-1, and LTC3589-2.

a power-on sequence tie the enable of the first regulator

to be powered up to the WAKE pin. Connect the first

regulatorsoutputtotheenablepinofthesecondregulator,

and so on. One or more regulators may be started in any

sequence. Each enable pin has a 200µs (typical) delay

between the pin and the internal enable of the regulator.

When the system controllers are satisfied that power rails

are up, the controller must drive PWR_ON HIGH to keep

WAKE active. To ensure correct start-up sequencing, the

regulators outputs are monitored by voltage comparators

whichrequireeachoutputtodischargebelow300mVbefore

re-enabling.Asoftwarecontrolcommandregisterfunction

is available which sets the regulators to effectively ignore

Table 1. LTC3589, LTC3589-1, and LTC3589-2 Functional

Differences

LTC3589

LTC3589-1

LTC3589-2

Power-On Inhibit

Enable Delay

1 second

<2ms

Buck2 Current

Output

1A

1.2A

Buck3 Current

Output

1A

1.2A

PGOOD Fault

Timeout

Enabled by

Default. I C

Disable.

Disabled by

Default. I C

Enable.

Disabled by

Default. I C

Enable.

2

PWR_ON to WAKE 50ms

Delay

2ms

their enable pins but respond to I C register enables. This

functionenablessoftware-onlycontrolofanycombination

of pin-strapped regulators and is useful for implementing

system power saving modes. Keep-alive mode exempts

selected regulators from turning off during normal

shutdown.Inkeep-alivemode,theLTC3589powersdown

normally and is ready for the next start-up sequence, but

selected regulators are kept on to power memory or other

functions during system standby modes.

LDO3 V

LDO4 V

1.8V

2.8V

OUT

1.8V, 2.5V,

2.8V*, 3.3V

1.2V*, 1.8V,

2.5V, 3.2V

1.2V*, 1.8V,

2.5V, 3.2V

* Indicates Default

V

OUT

2

Default LDO4

Enable

LDO34_EN Pin I C

I C

Wait to Enable Until Yes by Default. Yes by Default. No by Default.

Output < 300mV

2

I C Select.

Insert 2k Discharge Yes if Start-Up

Yes if Start-Up

Always

The LTC3589 will shut down all regulators and pull down

Resistor When

Disabled

is Wait to Enable is Wait to Enable

Until Output <

300mV

the WAKE pin under high temperature, V undervoltage,

IN

Until Output <

300mV

and extended low regulator output voltage conditions.

Status of a hard shutdown is reported by the IRQ status

pin and the IRQSTAT status register.

Details of the operation of the LTC3589 are found in the

following sections.

2

The I C serial port on the LTC3589 contains 13 command

registers for controlling each of the regulators, one read-

only register for monitoring each regulators power good

status, one read-only register for reading the cause of

an IRQ event, and one clear IRQ command register. The

ALWAYS-ON LDO

TheLTC3589includesalowquiescentcurrentlowdropout

regulator that remains powered whenever a valid supply

2

is present on V . The always-on LDO will remain active

IN

LTC3589I Csupportsrandomaddressingofanyregister.

until V drops below 2.0V (typical). This is below the 2.5V

IN

3589fh

17

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

operaTion

undervoltagethresholdineffectfortherestoftheLTC3589

circuits. The always-on LDO is used to provide power to

a standby microcontroller, real-time clock, or other keep-

alive circuits. The LDO is guaranteed to support a 25mA

load. A1µFlowimpedanceceramicbypasscapacitorfrom

LDO1_STBYtoGNDisrequiredforcompensation.Apower

good monitor pulls RSTO LOW for a minimum of 14ms

(typical) whenever LDO1_STBY is 8% belowits regulation

target. An LDO1_STBY undervoltage condition is reported

in the PGOOD status register. The output voltage of LDO1

is set with a resistor divider connected from LDO1_STBY

to the feedback pin LDO1_FB, as shown in Figure 1.

current limit protection circuits. Default operation for the

LTC3589 is when an LDO regulator is disabled, a 2.5k

pull-down resistor is connected to its output.

TohelpreduceLDOpowerlossinthesystem,theregulators

have dedicated supply inputs that may be lower than the

main V supply. Connect a low ESR 1µF capacitor to each

IN

of the output pins LDO2, LDO3, and LDO4.

LDO Regulator 2

One of the LTC3589 dynamic slewing DACs serves as the

reference input of LDO2. The output range of LDO2 is set

using an external resistor divider connected from LDO2

to the feedback pin LDO2_FB, as shown in Figure 2. Set

the output voltage of LDO2 using the following formula:

⎛

⎞

R1

R2

V_{LDO1_STBY}=0.8 • 1+

(V)

⎟

⎜

⎝

⎠

⎛

⎞

R1

R2

V_OUT= 1+

•(0.3625+L2DTVx • 0.0125)(V)

⎟

⎜

Typical values for R1 are in the range of 40k to 1M.

⎝

⎠

LDO1_STBY is protected from short-circuits and

overloading.

L2DTVxisthefivebitwordcontainedintheLDO2dynamic

target voltage 1 (L2DTV1) or the LDO2 dynamic target

voltage 2 (L2DTV2) command registers. The default value

of L2DTVx[4-0] is 11001 to output a reference voltage of

0.675V. LDO2 is enabled by writing bit 4 in the output

voltage enable (OVEN) command register to 1 or driving

theEN_LDO2pinhigh.Wheneverthecommandisgivento

slew LDO2 DAC reference to a lower voltage an integrated

2.5k pull-down resistor is connected to LDO2 output.

V

IN

+

–

0.8V

LDO1_STBY

1µF

R1

R2

LDO1_FB

3589 F01

PV

IN

Figure 1. Always-On LDO Application Circuit

EA

LDO2

250mA LDO REGULATORS

0.3625V

TO 0.75V

1µF

R1

R2

Three LDO regulators on the LTC3589 will each deliver

up to 250mA output. The LDO regulators are enabled by

FB

2

5

pin input or I C command register. Pin EN_LDO2 enables

DAC

LDO2 and the LTC3589 EN_LDO34 pin enables LDO3 and

2

LDO4together. AnI Ccommandregisterbitisavailableto

3589 F02

decoupleLDO4frompinEN_LDO34sothatLDO4isunder

commandregistercontrolonly.TheLTC3589-1/LTC3589-2

EN_LDO3 pin enables LDO3 only. LDO4 is controlled

Figure 2. LDO2 Application Circuit

2

using the I C command registers. All the regulators have

3589fh

18

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

Table 2. Shows the I C command register settings used

to control LDO2.

2

LDO Regulator 4

LDO4 has four output voltage options that are controlled

by the contents of command register bits L2DTV2[6]

and L2DTV2[5]. When pin EN_LDO34 is low, LDO3 and

LDO4 are controlled by writing to command register

bits OVEN[5] and OVEN[6] respectively. By default, the

LTC3589 pin EN_LDO34 enables and disables LDO3

and LDO4 simultaneously when command register bits

OVEN[5] and OVEN[6] are low. When command register

bit L2DTV2[7] is high, control of LDO4 is disconnected

from pin EN_LDO34 and controlled by command register

bit OVEN[6] regardless of the status of EN_LDO34. The

LTC3589-1/LTC3589-2 pin EN_LDO3 enables only LDO3.

Control of LDO4 on the LTC3589-1/LTC3589-2 is under

Table 2. LDO 2 Command Register Settings

COMMAND

REGISTER[BIT]

VALUE SETTING

OVEN[4]

0*

1

Disable

Enable

SCR2[4]

LTC3589/

LTC3589-1

0*

1

Wait for Output Below 300mV Before Enable

Enable Immediately

SCR2[4]

LTC3589-2

0*

1

Enable Immediately

Wait for Output Below 300mV Before Enable

VCCR[7]

0*

1

Select Register L2DTV1 (V1) Reference

Select Register L2DTV2 (V2) Reference

VCCR[6]

1

Initiate Dynamic Voltage Slew

VRRCR[7-6]

00

01

Reference Slew Rate = 0.88mV/µs

Reference Slew Rate = 1.75mV/µs

Reference Slew Rate = 3.5mV/µs

Reference Slew Rate = 7mV/µs

2

I C control only. Table 4 shows the I C command register

settings that control LDO4.

10

11*

Table 4. LTC3589 LDO4 Command Register Settings

L2DTV1[4-0]

L2DTV1[5]

11001* DAC Dynamic Target Voltage V1

COMMAND

REGISTER[BIT]

VALUE SETTING

0*

1

Force PGOOD Low When Slewing

Normal PGOOD Operation When Slewing

OVEN[6]

0*

1

Disable

Enable

L2DTV1[7]

0*

1

Shutdown LDO2 Normally

Keep LDO2 Alive

SCR2[6]

0*

1

Wait for Output Below 300mV Before Enable

Enable Immediately

L2DTV2[4-0]

11001* DAC Dynamic Target Voltage V2

L2DTV2[6-5]

00*

01

V

LDO4

V

LDO4

V

LDO4

V

LDO4

= 2.8V

= 2.5V

= 1.8V

= 3.3V

* Denotes Default Power-On Value

10

11

LDO Regulator 3

L2DTV2[7]

0*

1

LDO4 Enable Controlled by EN_LDO34

LDO4 Enable Controlled by OVEN[6]

LDO3 is a fixed 1.8V or 2.8V (LTC3589-1/LTC3589-2)

outputregulator.LDO3isenabledbydrivingpinEN_LDO34

orEN_LD03highorbywritingcommandregisterOVEN[5]

to 1.

LTC3589-1/LTC3589-2 LDO4 Command Register Settings

OVEN[6]

0*

1

Disable

Enable

SCR2[6]

LTC3589-1

0*

1

Wait for Output Below 300mV Before Enable

Enable Immediately

2

Table 3 shows the I C command register settings used

to control LDO3.

SCR2[6]

LTC3589-2

0*

1

Enable Immediately

Wait for Output Below 300mV Before Enable

L2DTV2[6-5]

00*

01

V

= 1.2V

= 1.8V

= 2.5V

= 3.2V

Table 3. LDO 3 Command Register Settings

LDO4

COMMAND

REGISTER[BIT]

VALUE SETTING

10

11

OVEN[5]

0* Disable

L2DTV2[7]

0*

1

Unused

1

Enable

SCR2[5]

LTC3589

LTC3589-1

0* Wait for Output Below 300mV Before Enable

1 Enable Immediately

* Denotes Default Power-On Value

SCR2[5]

LTC3589-2

0* Enable Immediately

1 Wait for Output Below 300mV Before Enable

* Denotes Default Power-On Value

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

STEP-DOWN SWITCHING REGULATORS

Operating Modes

Thestep-downswitchingregulatorsincludethreepossible

operating modes to meet the noise and power needs of a

variety of applications.

Output Voltage Programming

Each of the step-down converters uses a dynamically

slewing DAC output for its reference. The full-scale output

voltage is set by using a resistor divider connected from

the step-down switching regulator output to the feedback

pins (B1_FB, B2_FB, and B3_FB), as shown in Figure 3.

Set the output voltage of step-down switching regulators

using the following formula:

In pulse-skipping mode, at the start of every cycle, a latch

is set that turns on the main P-channel MOSFET switch.

During the cycle, a current comparatorcompares the peak

inductor current to the output of an error amplifier. The

outputofthecurrentcomparatorresetsthelatch.Atthistime

the P-channel MOSFET switch turns off and the N-channel

MOSFET synchronous rectifier turns on. The N-channel

MOSFETsynchronousrectifierwillturnoffwhentheendof

the clock cycle is reached or if the inductor current drops

through zero. Using this method of operation, the error

amplifier adjusts the peak inductor current to deliver the

required output power. All necessary loop compensation

is internal to the step-down switching regulator requiring

only a single ceramic output capacitor for stability. At light

loads in pulse-skipping mode, the inductor current may

reach zero on each pulse that will turn off the N-channel

MOSFET synchronous rectifier. In this case the switch

node (SW1, SW2, or SW3) goes HIGH impedance and the

switch node will ring. This is discontinuous operation and

is normal behavior for a switching regulator. At very light

loads in pulse-skipping mode, the step-down switching

regulators will automatically skip pulses as needed to

⎛

⎞

R1

R2

V_OUT= 1+

•(0.3625+BxDTVx • 0.0125)(V)

⎟

⎜

⎝

⎠

BxDTVx is the decimal value of the five bit binary number

2

intheI CBxDTV1orBxDTV2commandregisters.BxDTV1

andBxDTV2defaultto11001tooutputareferencevoltage

of 0.675V. Typical values for R1 are in the range of 40k

to 1M. The capacitor C cancels the pole created by the

FB

feedback resistors and the input capacitance on the FB pin

and also helps to improve load step transient response.

A value of 10pF is recommended for most applications.

Experimentation with capacitor sizes between 10pF and

33pF may yield improved transient response.

PV

IN

maintain output regulation. At high duty cycle (V

IN

>

OUTX

EN

PWM

CONTROL

V /2) it is possible for the inductor current to reverse at

L1

SW

FB

MODE

light loads causing the step-down switching regulator

to operate continuously. When operating continuously,

regulation and low noise output voltage are maintained,

butinputoperatingcurrentwillincreasetoafewmilliamps.

C

OUT

R1

R2

C

FB

In the forced continuous mode of operation, the inductor

current is allowed to be less than zero over the full range

of duty cycles. Operating in forced continuous mode is

a lower noise option at light loads than pulse-skipping

0.3625V

TO 0.75V

5

DAC

3589 F03

operation but with the drawback of higher V current

IN

Figure 3. Step-Down Switching Regulator

Application Circuit

due to the continuous operation of the MOSFET switch

3589fh

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

2

and rectifier. Since the inductor current is allowed to be

negative in forced continuous operation the step-down

switching regulator has the ability to sink output current.

TheLTC3589automaticallyforcesthestep-downswitching

regulator into forced continuous mode when dynamically

slewing the DAC voltage reference down.

Table 5, Table 6, and Table 7 show the I C command

register settings used to control the step-down switching

regulators.

Table 5. Step-Down Switching Regulator 1 Command Register

Settings

COMMAND

VALUE SETTING

REGISTER[BIT]

When the LTC3589 step-down switching regulators are in

Burst Mode operation, they automatically switch between

fixed frequency pulse-skipping operation and hysteretic

Burst Mode control as a function of the load current. At

light loads the step-down switching regulators control

the inductor current directly and use a hysteretic control

loop to minimize both noise and switching losses. While

in Burst Mode operation, the output capacitor is charged

to a voltage slightly higher than the regulation point. The

step-down switching regulator then goes into a low power

sleep mode during which the output capacitor provides

the load current. In sleep mode, most of the switching

regulator’s circuitry is powered off to conserve battery

power.Whentheoutputvoltagedropsbelowtheregulation

point the regulator’s circuitry is powered on and another

burst cycle begins. As the load current increases, the time

betweenburstcyclesdecreases.Abovealoadcurrentabout

one-quarter rated output load, the step-down switching

regulators will switch to low noise constant-frequency

PWM operation.

SCR1[1-0]

00* Pulse-Skipping Mode

01

10

Burst Mode Operation

Forced Continuous Mode

OVEN[0]

0*

1

Disable

Enable

SCR2[0]

LTC3589/

LTC3589-1

0*

1

Wait for Output Below 300mV Before Enable

Enable Immediately

SCR2[0]

LTC3589-2

0*

1

Enable Immediately

Wait for Output Below 300mV Before Enable

VCCR[1]

0*

1

Select Register B1DTV1 (V1) Reference

Select Register B1DTV2 (V2) Reference

VCCR[0]

1

Initiate Dynamic Voltage Slew

VRRCR[1-0]

00

01

10

Reference Slew Rate = 0.88mV/µs

Reference Slew Rate = 1.75mV/µs

Reference Slew Rate = 3.5mV/µs

11* Reference Slew Rate = 7mV/µs

B1DTV1[5]

0*

1

Force PGOOD Low When Slewing

Normal PGOOD Operation When Slewing

B1DTV1[4-0]

B1DTV2[4-0]

B1DTV2[5]

11001* DAC Dynamic Target Voltage V1

11001* DAC Dynamic Target Voltage V2

0*

1

2.25MHz Switching Frequency

1.125MHz Switching Frequency

Set the mode of operation for the step-down switching

2

B1DTV2[6]

B1DTV2[7]

0*

1

Switch on Clock Phase 1

Switch on Clock Phase 2

regulators by using the I C command register SCR1. Each

of the three regulators has independent mode control.

0*

1

Shutdown Regulator 1 Normally

Keep Regulator 1 Alive

A step-down switching regulator may enter a dropout

condition when its input voltage drops to near its

programmed output voltage. For example, a discharging

battery voltage of 3.4V dropping to the regulators

programmed output voltage of 3.3V. When this happens

thedutycycleoftheP-channelMOSFETswitchisincreased

until it turns on continuously with 100% duty cycle. In

dropout,theregulatorsoutputvoltageequalstheregulators

input voltage minus the voltage drops across the internal

P-channel MOSFET and the inductor DC resistance.

* Denotes Default Power-On Value

Soft-Start

Soft-start is accomplished by gradually increasing the

input reference voltage on each step-down switching

regulator from 0V to the dynamic reference DAC output

level at a rate of 0.8V/ms. This allows each output to

rise slowly, helping minimize inrush current required to

chargeuptheregulatoroutputcapacitor.Asoft-startcycle

3589fh

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

occurs whenever a regulator is enabled either initially or

while powering up following a fault condition. A soft-start

cycle is not triggered by a change of operating modes or

a dynamic voltage slew. During soft-start the converter is

forced to pulse-skipping mode regardless of the settings

in the SCR1 command register.

Since slowing the slew rate of the switch nodes causes

efficiency loss, the slew rate of the step-down switching

2

regulators is adjustable using the I C command register

B1DTV1 bits 6 and 7. Optimize efficiency or EMI as

necessarywithfourdifferentslewratesettings.Thepower-

ondefaultisthefastestslewrate,highestefficiencysetting.

Table 6. Step-Down Switching Regulator 2 Command Register

Settings

Table 7. Step-Down Switching Regulator 3 Command Register

Settings

COMMAND

REGISTER[BIT]

VALUE SETTING

COMMAND

REGISTER[BIT]

VALUE SETTING

SCR1[3-2]

00* Pulse-Skipping Mode

SCR1[5-4]

00* Pulse-Skipping Mode

01

10

Burst Mode Operation

01

10

Burst Mode Operation

Forced Continuous Mode

OVEN[1]

0*

1

Disable

Enable

OVEN[2]

0*

1

Disable

Enable

SCR2[1]

LTC3589/

LTC3589-1

0*

1

Wait for Output Below 300mV Before Enable

Enable immediately

SCR2[2]

LTC3589/

LTC3589-1

0*

1

Wait for Output Below 300mV Before Enable

Enable Immediately

SCR2[1]

LTC3589-2

0*

1

Enable immediately

Wait for Output Below 300mV Before Enable

SCR2[2]

LTC3589-2

0*

1

Enable Immediately

Wait for Output Below 300mV Before Enable

VCCR[3]

0*

1

Select Register B2DTV1 (V1) Reference

Select Register B2DTV2 (V2) Reference

VCCR[5]

0*

1

Select Register B3DTV1 (V1) Reference

Select Register B3DTV2 (V2) Reference

VCCR[2]

1

Initiate Dynamic Voltage Slew

VCCR[4]

1

Initiate Dynamic Voltage Slew

VRRCR[3-2]

00

01

10

Reference Slew Rate = 0.88mV/µs

Reference Slew Rate = 1.75mV/µs

Reference Slew Rate = 3.5mV/µs

VRRCR[5-4]

00

01

10

Reference Slew Rate = 0.88mV/µs

Reference Slew Rate = 1.75mV/µs

Reference Slew Rate = 3.5mV/µs

11* Reference Slew Rate = 7mV/µs

B2DTV1[5]

0*

1

Force PGOOD Low When Slewing

Normal PGOOD Operation When Slewing

B3DTV1[5]

0*

1

Force PGOOD Low When Slewing

Normal PGOOD Operation When Slewing

B2DTV1[4-0]

B2DTV2[4-0]

B2DTV2[5]

11001* DAC Dynamic Target Voltage V1

11001* DAC Dynamic Target Voltage V2

B3DTV1[4-0]

B3DTV2[4-0]

B3DTV2[5]

11001* DAC Dynamic Target Voltage V1

11001* DAC Dynamic Target Voltage V2

0*

1

2.25MHz Switching Frequency

1.125MHz Switching Frequency

0*

1

2.25MHz Switching Frequency

1.125MHz Switching Frequency

B2DTV2[6]

B2DTV2[7]

0*

1

Switch on Clock Phase 1

Switch on Clock Phase 2

B3DTV2[6]

B3DTV2[7]

0*

1

Switch on Clock Phase 1

Switch on Clock Phase 2

0*

1

Shutdown Regulator 2 Normally

Keep Regulator 2 Alive

0*

1

Shutdown Regulator 3 Normally

Keep Regulator 3 Alive

* Denotes Default Power-On Value

Switching EMI Control

Operating Frequency

The step-down switching regulators contain new patent

pending circuitry to limit the edge rate of the switch

nodes SW1, SW2, and SW3. This new circuitry controls

the transition of the switch node over a period of a few

nanoseconds, significantly reducing radiated EMI and

conducted supply noise while maintaining high efficiency.

The switching frequency of each of the LTC3589 step-

downswitchingregulatorsmaybeindependentlysetusing

2

I C command register bits B1DTV2[5], B2DTV2[5] and

B3DTV2[5]. The power-on default frequency is 2.25MHz.

Writing bit BxDTV2[5] HIGH will reduce the switching

frequency to 1.125MHz. Selection of the operating

3589fh

22

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

operaTion

frequencyisdeterminedbydesiredefficiency, component

size and converter duty cycle.

by lowering the peak current to be closer to the average

output current. Larger inductors, however, generally

have higher series resistance that counters the efficiency

advantage of reduced peak current.

Operation at lower frequency improves efficiency by

reducing internal gate charge and switching losses but

requires larger inductance and capacitance values for

comparable output ripple voltage. The lowest duty cycle

of the step-down switching regulator is determined by

the converters minimum on-time. Minimum on-time is

the shortest time duration that the converter is capable of

turning its top PMOS on and off again. The time consists

of the gate charge time plus internal delays associated

with peak current sensing. The minimum on-time of the

LTC3589 is approximately 90ns. If the duty cycle falls

below what can be accommodated by the minimum on-

time, the converter will begin to skip cycles. The output

voltage will continue to be regulated but the ripple voltage

and current will increase. With the switching frequency

set to 2.25MHz, the minimum supported duty cycle is

20%. Switching at 1.125MHz the converter can support

a 10% duty cycle.

Inductorripplecurrentisafunctionofswitchingfrequency,

inductance, V , and V , as shown in this equation:

IN

OUT

⎛

⎞

1

f •L

V_OUT

V_IN

ΔI_L=

• V_OUT1–

⎜

⎟

⎝

⎠

In an example application the LTC3589 step-down

switching regulator 3 has a maximum load of 1A, V

IN

equals 3.8V, and V

is set for 1.2V. A good starting

OUT

design point for inductor ripple is 30% of output current

or 300mA. Using the equation for ripple current, a 1.2µH

inductor should be selected.

An inductor with low DC resistance will improve converter

efficiency.SelectaninductorwithaDCcurrentratingatleast

1.5 times larger than the maximum load current to ensure

the inductor does not saturate during normal operations.

If short-circuit is a possible condition, the inductor should

be rated to handle the maximum peak current specified

for the step-down converter. Table 8 shows inductors

that work well with the step-down switching regulators.

Phase Selection

To reduce the cycle by cycle peak current drawn by the

switching regulators, the clock phase of each of the

LTC3589step-downswitchingregulatorscanbesetusing

Input/Output Capacitor Selection

2

I C command register bits B1DTV2[6], B2DTV2[6] and

B3DTV2[6]. The internal full-rate clock has a nominal

duty cycle of 20% while the half-rate clocks have a 50%

duty cycle. Setting the command register bits high will

delay the start of each converter switching cycle by 20%

or 50% depending on the selected operating frequency.

LowESR(equivalentseriesresistance)ceramiccapacitors

should be used at both the output and input supply of the

switchingregulators. OnlyX5RorX7Rceramiccapacitors

should be used because they retain their capacitance over

wider voltage and temperature ranges than other ceramic

types. A 22µF capacitor is sufficient for the step-down

switching regulator outputs. For good transient response

and stability the output capacitor should retain at least

10µF of capacitance over operating temperature and bias

voltage. Place at least 4.7µF decoupling capacitance as

Inductor Selection

The choice of step-down switching regulator inductor

influencestheefficiencyoftheconverterandthemagnitude

of the output voltage ripple. Larger inductance values

reduce inductor current ripple and therefore lower output

voltage ripple. A larger value inductor improves efficiency

close as possible to each PV pin. Refer to Table 12 for

IN

recommended ceramic capacitor manufacturers.

3589fh

23

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

operaTion

BUCK-BOOST SWITCHING REGULATOR

The value of R1 plays a role in setting the dynamics of

the buck-boost voltage mode control loop. In general, a

larger value for R1 will increase stability but reduce the

speed of the transient response. A good starting point is

to choose R1 equal to 1MΩ and calculate the value of R2

needed to set the target output voltage. If a large output

capacitorisused,thebandwidthoftheconverterisreduced

and R1 may be reduced to improve transient response. If

a large inductor or small output capacitor is used then a

larger R1 should be used to bring the loop toward more

stable operation.

Output Voltage Programming

SettheoutputvoltageoftheLTC3589buck-boostswitching

regulator using an external resistor divider connected

from BB_OUT to the feedback pin BB_FB and to GND, as

shown in Figure 4.

⎛

⎞

R1

R2

V_{BB_OUT}=0.8 • 1+

(V)

⎟

⎜

⎝

⎠

Table 8. Inductors for Step-Down Switching Regulator 1

VALUE

MAX DC

CURRENT (A)

MANUFACTURERS

PART NUMBER

(µH)

DCR (Ω)

SIZE (mm) W × L × H

Coilcraft

XPL4020-102ML

XPL4020-152ML

XPL4020-222ML

LPS6225-222ML

LPS6225-332ML

LPS6225-472ML

1.0

1.5

2.2

3.3

4.7

0.029

0.036

0.060

0.045

0.055

0.065

4.00

3.60

2.60

3.90

3.50

3.00

4.2 × 4.2 × 2.0

6.0 × 6.0 × 2.0

Cooper

SD14-1R2-R

SD14-1R5-R

SD14-2R0-R

SD25-2R2-R

1.2

1.5

2.0

2.2

0.034

0.039

0.045

0.031

3.35

2.91

2.56

2.80

5.2 × 5.2 × 1.45

5.2 × 5.2 × 2.5

Sumida

TDK

CDRH5D16NP-3R3N

3.3

0.045

2.60

5.6 × 5.6 × 1.8

VLF5014ST-1R0N2R7

VLF5014st-2R2N2R3

VLCF5020T-2R2N2R6-1

1.0

2.2

0.050

0.073

0.071

2.7

2.3

2.6

4.8 × 4.6 × 1.4

5.0 × 5.0 × 2.0

TOKO

Tokin

1124BS-1R2N

1124BS-1R8N

1.2

1.8

0.047

0.056

2.9

2.7

4.5 × 4.7 × 1.8

H-DI-0520-2R2

H-DI-0630-2R4

H-DI-0630-3R8

2.2

2.4

3.8

0.048

0.028

0.040

2.6

2.5

2

5.3 × 5.3 × 2.0

6.3 × 6.3 × 3.0

Wurth

744042001

744052002

744053003

7440530047

7440430022

1.0

2.5

3.0

4.7

2.2

0.028

0.030

0.024

0.030

0.023

2.60

2.4

2.8

2.4

2.5

4.8 × 4.8 × 1.8

5.8 × 5.8 × 1.8

5.8 × 5.8 × 2.8

4.8 × 4.8 × 2.8

3589fh

24

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

operaTion

P

SW4AB

SW4CD BB_OUT

D

VIN4

A

B

C

EN

MODE

PWM

CONTROL

R1

R2

22µF

BB_FB

–

+

0.8V

3589 F04

Figure 4. Buck-Boost Switching Regulator Application Circuit

Table 9. Inductors for Step-Down Switching Regulators 2 and 3

VALUE

(µH)

MAX DC

CURRENT (A)

MANUFACTURERS

PART NUMBER

DCR (Ω)

SIZE (mm) W × L × H

Coilcraft

Cooper

XPL4020-102ML

XPL4020-152ML

XPL4020-472ML

1.0

1.5

4.7

0.029

0.036

0.130

4.00

3.60

1.90

4.2 × 4.2 × 2.0

SD14-1R2-R

SD14-3R2-R

SD25-3R3-R

1.2

3.2

3.3

0.034

0.066

0.038

3.35

2.00

2.21

5.2 × 5.2 × 1.45

4.8 × 4.8 × 2.5

Sumida

TDK

CDRH5D16NP-4R7N

CDRH38D16RHPNP-3R3M

4.7

3.3

0.064

0.059

2.05

1.46

5.6 × 5.6 × 1.8

4.2 × 4.2 × 1.8

VLF5014ST-2R2N2R3

VLCF5020T-2R7N2R2-1

VLCF5020T-3R3N2R0-1

2.2

2.7

3.3

0.073

0.083

0.096

2.3

2.2

2

4.8 × 4.6 × 1.4

5.0 × 5.0 × 2.0

TOKO

Tokin

1124BS-2R4N

1124BS-3R3N

2.4

3.3

0.065

0.074

2.30

2.10

4.5 × 4.7 × 1.8

H-DI-0520-3R3

H-DI-0520-4R7

H-DI-0630-3R8

H-DI-0630-4R7

3.3

4.7

3.8

4.7

0.062

0.090

0.040

0.043

2.00

1.80

2.00

1.90

5.3 × 5.3 × 2.0

6.3 × 6.3 × 3.0

Wurth

744043004

744052002

7440530047

744042003

7440430022

4.7

2.5

4.7

3.3

2.2

0.052

0.030

0.055

0.023

1.55

2.4

1.95

2.5

5.0 × 5.0 × 3.0

5.8 × 5.8 × 1.8

5.8 × 5.8 × 2.8

4.8 × 4.8 × 1.8

4.8 × 4.8 × 2.8

3589fh

25

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

operaTion

Operating Modes

If the buck-boost load exceeds the maximum Burst Mode

currentcapabilitythentheoutputrailwillloseregulationand

the power good comparator will indicate a fault condition.

2

Table 10 shows the I C command registers used to

control the operating modes of the LTC3589 buck-boost

converter. When command register SCR1 bit 6 is LOW,

the LTC3589 buck-boost switching regulator operates

in a fixed frequency pulse width modulation mode using

voltage mode feedback control. A proprietary switching

algorithm allows the converter to transition between

buck, buck-boost, and boost modes without discontinuity

in inductor current or loop characteristics. The switch

topology is shown in the application circuit in Figure 4.

When the LTC3589 buck-boost is not enabled, a 2.5k pull-

down resistor is connected between BB_OUT and ground.

Soft-Start

The buck-boost converter has an internal voltage mode

soft-start circuit that ramps the buck-boosts error amp

reference from 0V to 800mV at a rate of 2V/ms. During

soft-start, the converter is regulating to the ramping

reference and will respond to output load transients.

During soft-start the buck-boost converter is forced into

continuous mode operation regardless of the state of the

SCR1 command register.

When the input voltage is significantly greater than the

output voltage, the buck-boost converter operates in

buck mode. Switch D turns on continuously and switch C

remains off. Switches A and B are pulse width modulated

to produce the required duty cycle to support the output

regulationvoltage.Astheinputvoltagedecreases,switchA

remains on for a larger portion of the switching cycle.

When the duty cycle reaches approximately 85%, the

switch pair AC begins turning on for a small fraction of the

switching period. As the input voltage decreases further,

the AC switch pair remains on for longer durations and

the duration of the BD phase decreases proportionately.

As the input voltage drops below the output voltage, the

AC phase will eventually increase to the point that there is

no longer any BD phase. At this point, switch A remains

on continuously while switches CD operate as a boost

converter to regulate the desired output voltage.

Current Limit Operation

The LTC3589 buck-boost regulator has current limit

circuits to limit forward current through the A switch and

reversecurrentthroughtheDswitch.Theprimaryforward

current limit circuit injects a small fraction of the induc-

tor current into the feedback node whenever the inductor

current exceeds 2.7A (typical). Forcing the current into

the feedback node in the high gain feedback circuit has

the effect of lowering the output voltage until the aver-

age current in switch A is equal to the current limit. The

average limit uses the error amplifier in its active linear

state so once the fault condition is removed the recovery

is smooth with little overshoot.

The buck-boost is set to Burst Mode operation by writing

a 1 to command register SCR1 bit 6. Using Burst Mode

operation at light loads improves efficiency and reduces

standby current at zero loads. In Burst Mode operation,

theinductorischargedwithburstsoffixedpeakamplitude

current pulses. The current pulses are repeated as often

as necessary to maintain the target output voltage. The

maximumoutputcurrentthatcanbesuppliedinBurstMode

operation is dependent upon the input and output voltage.

A hard short on the output of the buck-boost will cause the

inductor current to exceed the 2.7A average current limit.

A second current limit turns off switch A in the event peak

inductor current reaches 3A (typical). The instantaneous

forwardcurrentlimitprovidesextraprotectionintheevent

of a sudden hard short.

The reverse current comparator on the D switch moni-

tors the current entering the BB_OUT pin. When this

current exceeds 1A (typical) switch D will turn off for the

remainder of the switching cycle. This feature protects

the buck-boost converter from excessive reverse current

if the buck-boost output is held above the regulation point

by an external source.

Typically I

in Burst Mode operation is equal to:

OUT(MAX)

0.28 • V_IN

I_OUT(MAX)

=

(A)

V_{BB_OUT}+ V_IN

3589fh

26

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

operaTion

Table 10. Buck-Boost Command Register Settings

Inductor Selection

COMMAND

VALUE SETTING

Inductorselectioncriteriaforthebuck-boostaresimilarto

those given for the step-down switching regulators. The

buck-boost converter is designed to work with inductors

in the range of 1µH to 3.3µH. For most applications use a

1.5µHinductor.ChooseaninductorwithaDCcurrentrating

at leasttwotimeslargerthan themaximumloadcurrentto

ensure that the inductor does not saturate during normal

operation. If output short-circuit is a possible condition,

the inductor should be rated to handle the maximum peak

current specified for the buck-boost converter. Table 11

shows several inductors that work well with the LTC3589

buck-boost regulator.

REGISTER[BIT]

SCR1[6]

OVEN[3]

0*

1

Continuous Mode

Burst Mode Operation

0*

1

Disable

Enable

SCR2[3]

LTC3589/

LTC3589-1

0*

1

Wait for Output Below 300mV Before Enable

Enable Immediately

SCR2[3]

LTC3589-2

0*

1

Enable Immediately

Wait for Output Below 300mV Before Enable

* Denotes Default Power-On Value

Table 11. Inductors for Buck-Boost Switching Regulator

PART

NUMBER

VALUE

(µH)

MAX DC

CURRENT (A)

MANUFACTURERS

DCR (Ω)

SIZE (mm) W × L × H

Coilcraft

XFL4020-152ME

XFL4020-222ME

XFL4020-332ME

LPS6225-332ML

LPS6225-472ML

1.5

2.2

3.3

4.7

0.014

0.021

0.035

0.055

0.065

4.10

3.10

2.70

3.50

3.00

4.0 × 4.0 × 2.1

6.0 × 6.0 × 2.0

Cooper

SD14-1R5-R

SD14-2R0-R

SD14-2R5-R

SD14-3R2-R

SD25-3R3-R

1.5

2.0

2.5

3.2

3.3

0.039

0.045

0.060

0.066

0.038

2.91

2.56

2.29

2.00

2.21

5.2 × 5.2 × 1.45

4.8 × 4.8 × 2.5

Sumida

TDK

CDRH5D16NP-3R3N

CDRH5D16NP-4R7N

3.3

4.7

0.045

0.064

2.60

2.05

5.6 × 5.6 × 1.8

VLF5014ST-2R2N2R3

VLCF5020T-2R7N2R2-1

VLCF5020T-3R3N2R0-1

2.2

2.7

3.3

0.073

0.083

0.096

2.3

2.2

2

4.8 × 4.6 × 1.4

5.0 × 5.0 × 2.0

TOKO

Tokin

Wurth

1124BS-1R8N

1124BS-3R3N

1.8

3.3

0.056

0.074

2.70

2.10

4.5 × 4.7 × 1.8

H-DI-0520-3R3

H-DI-0630-3R8

3.3

3.8

0.062

0.040

2.00

5.3 × 5.3 × 2.0

6.3 × 6.3 × 3.0

744052002

7440420027

744053003

7440530047

2.5

2.7

3.0

4.7

0.030

0.047

0.024

0.030

2.4

2.2

2.8

2.4

5.8 × 5.8 × 1.8

4.8 × 4.8 × 1.8

5.8 × 5.8 × 2.8

3589fh

27

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

operaTion

Capacitor Selection

Table 13. Slewing DAC Command Register Control Summary

COMMAND

REGISTER[BIT]

FUNCTION

Low ESR ceramic capacitors should be used at both the

output and input supply of the buck-boost switching

regulator. Only X5R or X7R ceramic capacitors should

be used because they retain their capacitance over wider

voltage and temperature ranges than other ceramic types.

A 22µF capacitor is sufficient for the buck-boost switch-

ing regulator output. For good transient response and

stability the output capacitor should retain at least 10µF of

capacitance over operating temperature and bias voltage.

Place at least 4.7µF decoupling capacitance as close as

VCCR[0], VCCR[2],

VCCR[4], VCCR[6]

Voltage Change Control Register

G0 / Slew

Write a 1 to Initiate a Slew to the Voltage

Selected in VCCR[1], VCCR[3], VCCR[5],

VCCR[7] Respectively.

Bits are Reset to 0 at the End of the Slew

Operation.

VCCR[1], VCCR[3],

VCCR[5], VCCR[7]

Voltage Change Control Register

Dynamic Target Select

Write a 0 to Select Voltage V1 Stored in

Registers B1DTV1[4-0], B2DTV1[4-0],

B3DTV1[4-0], L2DTV1[4-0].

possible to PV pin. Refer to Table 12 for recommended

IN4

ceramic capacitor manufacturers.

Write a 1 to Select Voltage V2 in Registers

B1DTV2[4-0], B2DTV2[4-0], B3DTV2[4-0],

L2DTV2[4-0].

Table 12. Ceramic Capacitor Manufacturers

AVX

www.avxcorp.com

www.murata.com

www.t-yuden.com

www.vishay.com

www.tdk.com

Murata

B1DTV1[4-0], B2DTV1[4-0], Dynamic Target Voltage 1

B3DTV1[4-0], L2DTV1[4-0]

Taiyo Yuden

Vishay Siliconix

TDK

Five Bits Corresponding to V1 Output from

Each DAC.

B1DTV1[5], B2DTV1[5],

B3DTV1[5], L2DTV1[5]

PGOOD Mask

Write a 1 to Continue Normal PGOOD

Operation When Slewing.

SLEWING DAC REFERENCE OPERATION

Controlling the DAC References

Write a 0 to Force PGOOD to Pull Low

During Slew.

B1DTV2[4-0], B2DTV2[4-0], Dynamic Target Voltage 2

B3DTV2[4-0], L2DTV2[4-0]

The three LTC3589 step-down switching regulators and

linear regulator LDO2 have programmable DAC reference

inputs.EachDACisprogrammablefrom0.3625Vto0.75V

in 12.5mV steps:

Five Bits Corresponding to V2 Output from

Each DAC.

VRRCR[1-0], VRRCR[3-2], Voltage Ramp Rate Control

VRRCR[5-4], VRRCR[7-6]

Two Bits That Set the DAC Output Slew

Rate for Step-Down Switching Regulator

and LDO2.

⎛

⎞

R1

R2

V_OUT= 1+

•(0.3625+BxDTVx • 0.0125)(V)

⎟

⎜

⎝

⎠

Setting and Slewing the DAC Outputs

The 5-bit word in dynamic target voltage command reg-

isters B1DTV1, B2DTV1, B3DTV1, and L2DTV1 programs

referencevoltageV1.The5-bitwordincommandregisters

B1DTV2, B2DTV2, B3DTV2, and L2DTV2 programs refer-

ence voltage V2. A resistor divider network on the output

andfeedbackpinsoftheregulatorssettheiroutputvoltage.

The DAC references may be commanded to independently

slew between two voltages at one of four selectable slew

rates. Table 13 summarizes the command registers used

to control slewing DAC operation.

3589fh

28

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

operaTion

Writing a 0 or 1 to the odd bits of voltage change control

register VCCR selects DAC output voltages V1 or V2,

respectively. A slew of the DAC is initiated by writing a 1

to an even bit of register VCCR. The DAC output will slew

to either voltage, V1 or V2, as selected by the odd bits of

register VCCR. Slew begins when the I C STOP condition

is detected. At the end of the slewing operation the GO

bits in command register VCCR are cleared.

input to 0.625V. VCCR[0] set to 1 initiates the dynamic

slew to go to the new voltage. To slew back to 1.2V write

01 to command register bits VCCR[1:0].

Table 14. Dynamic Slewing Example for Step-Down Switching

Regulator 1

2

COMMAND

REGISTER

V

=1.2V

V

=1V

OUT

VRRCR[1:0]

VCCR[1]

Dynamic Slew Rate

Select DTV

01

0

01

1

The slew rate for each regulator is set in the ramp rate

controlregisterVRRCR.EachDAChasindependentoutput

voltageregisters,voltageregisterselect,andslewrateand

start controls. The regulators do not have to be enabled

to change the DAC outputs.

B1DTV1[4:0]

B1DTV2[4:0]

11111

10101

11111

10101

Resistor Divider Shown

in Figure 3

R1 = 301kΩ

R2 = 499kΩ

TheVSTBpinisusedtosettheDACcontrolledoutputrails

to a low power standby condition. When VSTB is driven

HIGH, all four of the DAC references will immediately slew

to V2. To use VSTB to set the rails to standby voltage,

select V1 for normal rail voltages and V2 for standby rail

voltages. Drive VSTB high to immediately slew all the

DAC outputs to V2. When VSTB is driven LOW, the DAC

outputs will slew to V1.

PUSHBUTTON OPERATION

State Event Diagram

Figure 5 shows the LTC3589 pushbutton state diagram.

Upon the first power application to the LTC3589 V pin an

IN

internalpower-onresetcircuitputsthepushbuttonintothe

power-down (PDN) state and initiates a one second timer.

TheLTC3589statuspinRSTOispulledlowuntilonesecond

times out and the always-alive LDO1 is indicating power

good status. After the one second interval the pushbutton

circuitwilltransitiontothepower-off(POFF)standbystate.

TheLTC3589-1/LTC3589-2powersondirectlytothePOFF

statebypassingtheoneseconddelay.StatuspinRSTOwill

be released high when LDO1 indicates power good status.

The LTC3589 will not leave the POFF state and enter the

power-up state (PUP) until ON is held LOW for at least

Thedefaultpower-upvalueofallthedynamictargetvoltage

registers is 11001 corresponding to a DAC output volt-

age of 0.675V. The DTV registers may be reprogrammed

prior to initiating a power-up sequence or at any time for

dynamic slewing.

When a step-down switching regulator output is slewing

downitsmodeisautomaticallyswitchedtoforcedcontinu-

ous to enable the regulator to sink current. When LDO2 is

slewing down, a 2.5k pull-down is connected to its output.

PUP

Table 14 shows command register and feedback divider

settingstoenableslewingstep-downswitchingregulator1

between 1.2V and 1V in 70µs. The voltage ramp rate

controlregisterbitsVRRCR[1:0]aresetto01whichselects

a ramp rate of 1.75mV/µs at the DAC output. The slew rate

attheregulatoroutputisafunctionofthefeedbackresistor

divider gain. In this example, the slew is equal to 1.75 • (1

+ 301/499) = 2.8mV/µs. Therefore, a slew of 200mV will

take 70µs. To initiate a change from 1.2V to 1V write 11 to

voltage change control register bits VCCR[1:0]. VCCR[1]

selectstargetregisterB1DTV2tosettheregulatorreference

ON OR

5 SEC

PWR_ON

POR

POFF

PON

FAULT OR

PWR_ON OR

HARD RESET

POFF

PON

FAULT OR

PWR_ON OR

HARD RESET

1 SEC

POR

1 SEC

PDN

LTC3589-1/LTC3589-2

3589 F05

LTC3589

Figure 5. Pushbutton Controller State Diagram

3589fh

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

400ms (PB400ms) or until PWR_ON is activated by the

PWR_ON pin. When the controller enters the PUP state

the open-drain WAKE pin releases HIGH. The WAKE pin

is typically used to enable the first regulator in a start-up

sequence. The pushbutton state will stay in PUP for five

seconds before transitioning to the power-on (PON) state.

Before leaving PUP, the PWR_ON pin must be brought

HIGH by the application to indicate that the system rails

are correct. If PWR_ON is not active at the end of five

seconds the pushbutton controller will continue directly

through PON to the power-down (PDN) state and pull the

WAKE pin down. Three events will cause the pushbutton

to leave the PON state: 1) lowering the PWR_ON pin, 2)

forcing a hard reset by holding the ON pin LOW for five

seconds, and 3) a fault condition is detected. Fault condi-

thePBSTATpinispulledLOW.Thesystemcontrollershould

monitor the PBSTAT pin to determine the pushbutton has

been pushed. If the controller decides that a power-down

is desired, then it should drive the PWR_ON pin LOW.

Power-Up and Down Using PWR_ON Pin

An alternate power-up method is to drive the PWR_ON pin

to a HIGH state. After a delay of 50ms from the PWR_ON

signal, the WAKE pin will pull HIGH to drive regulator en-

able pins. When PWR_ON is HIGH for five seconds, the

sequence controller will enter the PON state. To power

down, drive the PWR_ON pin LOW. 50ms later WAKE will

pull low, all enabled regulators are disabled and the OVEN

command register is reset to 0x00.

tions are low V , device over temperature, or extended

Hard Reset Using the Pushbutton

IN

undervoltage of one of the regulator outputs. All regulator

enables, the ON input, and PWR_ON signals are inhibited

for one second while in the PDN state. After one second

in PDN the pushbutton controller returns to POFF.

When the ON pin is pulled LOW for five seconds, a hard

reset is initiated. At the end of five seconds, WAKE is

2

pulled LOW, the I C command registers are reset to POR

states, enable pin states are ignored, and the one second

power-downtimerisstarted.Duringthepower-downtime,

the enables continue to be ignored to allow the regulator

outputs to discharge. The RSTO pin is pulled LOW for

the power-down time to indicate a pushbutton hard reset

occurred. If the PWR_ON pin is LOW at the end of the

one second power-down time, the LTC3589 will remain

in standby mode. If PWR_ON is HIGH at the end of one

second and there are no fault conditions, the LTC3589 will

power-up in the same way shown in Figure 8.

PBSTAT Operation

PBSTAT goes LOW 50ms after the initial pushbutton ap-

plication (ON LOW) and will stay LOW for a minimum of

50ms.PBSTATwillgoHIGHcoincidentwithONgoingHIGH

unless ON goes HIGH before the 50ms minimum on-time.

Power-Up Using the Pushbutton

When in the POFF standby state, the LTC3589 is in com-

plete shutdown except the always active LDO1 and any

regulatorsenabledwiththekeep-alivecontrolbits.Pullthe

ON pin to ground with a pushbutton for 400ms to begin a

power-up sequence with the WAKE pin tied to an enable

pin. Drive PWR_ON high within five seconds to signal the

LTC3589 to remain in the power-on state.

Hard Reset Due to a Fault Condition

A hard reset due to V undervoltage, extended undervolt-

IN

age of an output rail, or an overtemperature condition

initiates a hard shutdown of the LTC3589. When the fault

2

occurs, wake is pulled LOW, the I C command registers

are reset to POR states, enable pin inputs are ignored,

and the one second power-down timer is started. Dur-

ing the power-down time, the enables continue to be

ignored to allow the regulator outputs to discharge. If the

PWR_ON pin is LOW at the end of the power-down time,

the LTC3589 will remain in standby mode with just the

always-active LDO operating. If PWR_ON is HIGH at the

Power-Down Using the Pushbutton

The pushbutton power-down operation is performed by

thesystemmicroprocessorbymonitoringthePBSTATpin.

OnceinthePONstate,thesystemcontrollerisresponsible

for deciding what action to take with a pushbutton event.

WhentheONpinisheldLOWfora50msdebounceperiod,

3589fh

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ON(PB)

PBSTAT

WAKE

end of one second and the fault condition has cleared, the

LTC3589willpower-upinthesamewayshowninFigure8.

Neither IRQ nor the status registers are cleared by the

fault induced shutdown.

400ms

<5 SEC

µC/µP CONTROL

PWR_ON

3589 F06

ENABLE AND POWER-ON SEꢀUENCING

Enable Input Pin Operation

Figure 6. Power-Up Using the Pushbutton

<5 SEC

ON(PB)

PBSTAT

WAKE

The regulator enable input pins facilitate pin-strapping an

output rail to the enable pin of the next regulator in the

desired sequence. The regulator enable inputs normally

havea0.8V(typical)inputthreshold.Ifanyenableisdriven

HIGH, the remaining enable input thresholds switch to a

more accurate 500mV (typical) threshold.

50ms

50ms - LTC3589

2ms - LTC3589-1/

LTC3589-2

µC/µP CONTROL

PWR_ON

3589 F07

Figure 7. Power Down Using Pushbutton

Figure 11 shows an application circuit for a typical pin-

strapped start-up sequence. Holding ON LOW for 400ms

brings up the WAKE pin that is tied to EN1 and EN3 to

enablestep-downswitchingregulators1and3.Theoutput

of regulator 1 is tied to EN2 and EN4 which enable step-

down switching regulator 2 and the buck-boost switching

regulator4.Theoutputofstep-downswitchingregulator2

is tied to EN_LDO2 and EN_LDO34 to enable LDO2, LDO3

and LDO4. Within five seconds of WAKE going HIGH, the

microprocessor or microcontroller must drive PWR_ON

HIGH to tell LTC3589 that rails are good and to stay in

the power-on state.

ON(PB)

PBSTAT

WAKE

50ms - LTC3589

2ms - LTC3589-1/LTC3589-2

5 SEC

50ms

µC/µP CONTROL

PWR_ON

3589 F08

Figure 8. Power-Up and Down Using PWR_ON Pin

ON(PB)

50ms

PBSTAT

WAKE

5 SEC

µC/µP CONTROL

PWR_ON

RSTO

1 SEC

V

IN

LTC3589

3589 F09

EN1

WAKE

SW1

Figure 9. Hard Reset Using the Pushbutton

EN2

1V TO 1.2V

1.8V

EN3

SW2

EN4

SW3

0.8V TO 1V

3.3V

FAULT

ON(PB)

PBSTAT

WAKE

EN_LDO2

EN_LDO34

ON

BB_OUT

LDO2

LDO3

LDO4

1.2V

1.8V

PWR_ON

2.8V

<1 SEC

3589 F11

µC/µP CONTROL

PWR_ON

IRQ

Figure 11. Pin-Strap Start-Up Sequence Application Circuit

CLIRQ

3589 F10

Figure 10. Hard Reset Due to a Fault Condition

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Figure 12 shows the start-up timing for the application

shown in Figure 11. There is a 200µs (typical) delay

between the enable pin and the internal enable signal to

each regulator.

a regulator’s keep-alive bit in its dynamic target voltage

register will keep a regulator alive when the LTC3589 is

in standby (POFF) mode. A regulator with its keep-alive

bit set will stay enabled until the bit is reset writing the bit

LOW, resettingtheLTC3589withapushbuttonhardreset,

or a fault condition (UVLO, PGOOD, timeout or thermal

shutdown) occurs. PGOOD and fault status are reported

in the IRQSTAT and PGSTAT registers and on the IRQ and

PGOOD pins for keep-alive regulators when PWR_ON and

WAKE are LOW.

WAKE

V1

1.2V

1V

200µs

0.5V

V3

1.8V

200µs

0.5V

3.3V

V2

V4

1.2V

Software Control Mode

200µs

LDO2

LDO3

LDO4

1.8V

2.8V

Once a power-up sequence is completed each regulator

may be enabled and disabled individually by the system

as needed for power mode requirements. Setting the out-

put voltage enable command register bit OVEN[7] HIGH

disconnects each regulator from its enable pin so control

is solely through the OVEN command register. To enter

software control mode, set command bit OVEN[7] HIGH

and the desired enable bits in OVEN[6:0] HIGH. Any of the

regulators enabled in OVEN[6:0] will stay on regardless

of the state of their enable pins when OVEN[7] is HIGH.

Setting the regulator enable bits and the software control

3589 F12

Figure 12. Pin-Strap Sequencing Timing

To help ensure startup sequencing, the LTC3589 is

designed toblocktheinternalenable ofaregulatoruntilits

outputhasdischargedtolessthan300mV.TheI Csystem

control register 2 (SCR2) controls whether the LTC3589

waits or enables immediately. The POR default setting for

the LTC3589 and LTC3589-1 is to wait for the output to be

less than 300mV before enabling. The output discharge

resistors on the LTC3589 and LTC3589-1 regulators are

tied to the settings in SCR2.

2

bit in OVEN[7] may occur on the same I C start-stop

sequence. A normal shutdown using PWR_ON resets

all eight bits of the OVEN register to 0x00 to ensure all

regulators are shut off.

For use in systems that might back drive the regulator

outputs higher than 300mV, the LTC3589-2 POR default

setting is to always enable regardless of output voltage

and to always engage the discharge resistors whenever

the regulator is not enabled.

FAULT DETECTION, SHUTDOWN, AND REPORTING

TheLTC3589monitorsV ,outputrailvoltagesandinternal

IN

die temperature. A warning condition is indicated when

V

is less than 2.9V and when internal die temperature

IN

approaches the thermal shutdown temperature. A fault

Keep-Alive Operation

condition occurs when V is less than 2.6V, any regulator

IN

For systems which require an active supply rail when in

system standby, any of the three LTC3589 step-down

switching regulators or LDO2 may be kept alive regard-

less of the status of PWR_ON and WAKE. Writing a 1 to

output is 8% low for 14ms, or the internal die temperature

is HIGH. Warning and fault states are reported via the IRQ,

PGOOD, and RTSO pins. Specific fault states are read via

2

the I C serial port status registers IRQSTAT and PGSTAT.

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RSTO Pin Function

voltage for longer than 25µs (typical), the PGOOD pin is

pulled LOW and the appropriate bit in the PGSTAT status

register (Table 15) is set.

The RSTO (reset output) pin is an open-drain output for

use as a power-on reset signal. It is pulled LOW at initial

power until LDO1 is within 8% of its target and the initial

onesecondstart-uptimerisfinished.RSTOremainsHIGH

during normal operation and will be pulled low if LDO1

loses regulation for more than 25µs or a pushbutton hard

reset is initiated. RSTO is released high 14ms after LDO1

returns to regulation.

Table 15. PGSTAT Read-Only Register Bit Definitions

PGSTAT[BIT] VALUE SETTING

LDO1_STBY Output Low

LDO1_STBY Output Good

0

1

2

3

4

5

6

7

0

1

Step-Down Switching Regulator 1 Output Low

Step-Down Switching Regulator 1 Output Good

0

1

Step-Down Switching Regulator 2 Output Low

Step-Down Switching Regulator 2 Output Good

0

1

Figure 13 shows a initial power-up for the RSTO pin. If

V

is not above its undervoltage thresholds at the end

IN

Step-Down Switching Regulator 3 Output Low

Step-Down Switching Regulator 3 Output Good

0

1

of the 1 second start-up time, the IRQ pin will be pulled

LOW and an undervoltage bit will be set in the IRQSTAT

status register.

Buck-Boost Regulator 4 Output Low

Buck-Boost Regulator 4 Output Good

0

1

LDO2 Output Low

LDO2 Output Good

0

1

2.7V

–8%

V

IN

LDO3 Output Low

LDO3 Output Good

0

1

LDO4 Output Low

LDO4 Output Good

0

1

LDO1

25µs

Figure 14 shows the PGOOD pin and PGSTAT status reg-

ister timing. When no regulator is enabled, the PGOOD

pin is pulled LOW and PGSTAT bits are LOW. PGOOD and

the PGSTAT bits are HIGH 250µs after the last enabled

regulator is within 7% of its target.

RSTO

1 SEC

INITIAL POWER-UP

14ms

LDO1 UNDERVOLTAGE

LTC3589

V

IN

WAKE HIGH AFTER 1sec

–8%

IF PWR_ON HIGH

1sec

WAKE

LDO1

25µs

ENx

RSTO

25µs

DISABLED IF

WAKE LOW

14ms

200µs

INITIAL POWER-UP

LDO1 UNDERVOLTAGE

V

OUTx

250µs

LTC3589-1/LTC3589-2

3589 F13

250µs

14ms

PGOOD

Figure 13. Initial Power-Up and LDO1 Undervoltage RSTO Timing

IRQ

PGOOD Pin and PGSTAT Status Register Function

EXTENDED

UNDERVOLTAGE

(FAULT)

UNDERVOLTAGE

DISABLE

ENABLE

Each LTC3589 regulator has an internal power good out-

put that is active whenever the regulators feedback pin is

closer than 7% (typical) from its input reference voltage.

If any of the internal power good signals indicate a low

3589 F14

Figure 14. PGOOD Pin and PGSTAT Status Register Timing

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If any enabled regulator output falls more than 7% low

for longer than 25µs PGOOD is pulled LOW and a cor-

responding status bit in the PGSTAT register is set to 0.

The PGOOD pin and PGSTAT status bit remain LOW for

as long as the low voltage condition persists plus 250µs.

Thermal Shutdown Fault and Warning

Similar to the V undervoltage detection circuits the over-

IN

temperature detection circuits check for warning and fault

levels. Anovertemperaturefaultwillinitiateafaultinduced

shutdown. An overtemperature warning sets register bit

IRQSTAT[6] and pulls the IRQ pin LOW.

An extended low output rail causing the PGOOD pin to

be LOW for longer than 14ms defines a PGOOD timeout

fault condition that triggers a hard reset if not masked in

IRQ Pin and IRꢀSTAT Status Register Function

2

I C register bit SCR2[7]. When SCR2[7] is HIGH, PGOOD

The IRQ pin and IRQSTAT status register report PGOOD

remains in normal operation.

timeout fault, V undervoltage warning and fault, and

IN

high temperature warning and fault. Table 16 shows the

During a dynamic voltage slew, PGOOD is pulled LOW

unless bit 5 in the dynamic target voltage register for

each regulator is set HIGH. The status register PGSTAT

is unaffected by a dynamic voltage slew.

meaning of the IRQSTAT read-only status register bits.

Table 16. IRꢀSTAT Read-Only Register Bit Definitions

IRꢀSTAT[BIT]

VALUE SETTING

PGOOD Timeout Fault (PGOOD Low >

14ms)

3

1

Undervoltage Detection

V

Undervoltage Warning (V < 2.9V)

TheLTC3589undervoltage(UV)detectioncircuitwilloutput

4

5

6

7

1

IN

a fault condition, locking out regulator operation, until V

Undervoltage Fault (V < 2.6V)

IN

reaches 2.7V. Once V is above 2.7V the LTC3589 will

Thermal Limit Warning (T > 130°C)

IN

J

operate normally until V drops to 2.55V (typical). When

IN

Thermal Limit Fault (T > 150°C)

J

V drops below 2.55V, the fault condition initiates a hard

IN

Figure 16 shows the timing of the IRQ and IRQSTAT status

registerfollowingawarning(V <2.9Vorhightemperature

shutdown reset. Figure 15 shows undervoltage warning

IN

and fault detection levels.

warning) event. When a warning occurs, IRQ is latched

LOWandbitIRQSTAT[4]orIRQSTAT[5]isset.IRQremains

low and the IRQSTAT status bits remain active until the

FAULT

WARNING

V

2

IN

I C CLIRQ command is given and the warning condition

UNDERVOLTAGE

has passed.

2.55V 2.65V 2.9V

3V

V

IN

3589 F15

TSD OR UV

WARNING

Figure 15. UV Detection Hard Reset and Warning Levels

IRQ

IRQSTAT

AnundervoltagewarningsetsregisterbitIRQSTAT[4]and

pulls the IRQ pin LOW.

CLIRQ

3589 F16

To minimize standby quiescent current the UVLO and

thermal sensor circuits are disabled when all the regula-

tors are off.

Figure 16. IRQ and IRꢀSTAT Status Register Warning Timing

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Figure 17 shows the timing of the IRQ pin and IRQSTAT

status register following a fault induced hard shutdown

event. When a fault occurs, IRQ is latched LOW and bit

IRQSTAT[3], IRQSTAT[5], or IRQSTAT[7] is set. IRQ re-

mains LOW until the CLIRQ command is issued. When the

CLIRQ command has been issued, the IRQSTAT status bit

remains set for the one second enable inhibit time or as

long as the fault condition persists, whichever is longer.

Fault Induced Shutdown

Any of the three fault conditions will initiate a hard reset

shutdown triggering the following events: 1) A bit corre-

sponding to the fault is set in status register IRQSTAT, 2)

IRQ and WAKE pins are pulled LOW, 3) enable pin inputs

are ignored and the regulators are disabled, 4) all enable

bits and software control mode bit in the output voltage

enable OVEN command register are cleared, and 5) the

pushbutton controller is sent to the PDN state for one

second and then to POFF. Re-enabling of regulators is

inhibited until both the fault condition and the one second

time out have passed to allow regulator outputs sufficient

time to discharge. When one second timeout and the fault

condition are both passed, if PWR_ON is HIGH, WAKE will

come up and the LTC3589 will respond to any enable pins

that are also HIGH.

TSD, UV,

OR PGOOD FAULT

IRQ

1 SEC

IRQSTAT

CLIRQ

3589 F17

Figure 17. IRQ and IRꢀSTAT Status Register Fault Timing

SDA

t

HD, STA

BUF

t

SU, STO

SU, DAT

t

LOW

HD, STA

HD, DAT

3589 F18

SCL

t

HIGH

t

HD, STA

SP

START

CONDITION

REPEATED START

CONDITION

STOP

START

t

r

t

f

Figure 18. LTC3589 I²C Timing

ADDRESS

SUB ADDRESS

S7 S6 S5 S4 S3 S2 S1 S0

DATA

SUB ADDRESS

DATA

D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

WR

D7 D6 D5 D4 D3 D2 D1 D0

S7 S6 S5 S4 S3 S2 S1 S0

START

SDA

STOP

0

1

2

1

3

0

4

0

6

0

7

0

8

1

5

ACK

9

ACK

9

ACK

9

ACK

9

ACK

9

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

SCL

3589 F19

Figure 19. LTC3589 I²C Serial Port Multiple Write Pattern

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I C OPERATION

2

commands the LTC3589 to act upon its new command

set. A STOP condition is sent by the master by transition-

ing SDA from LOW to HIGH while SCL is HIGH. The bus

2

I C Interface

2

it then free for communication with another I C device.

The LTC3589 communicates with a bus master using the

2

standard I C 2-wire interface. The two bus lines, SDA and

2

I C Byte Format

SCL, must be HIGH when the bus is not in use. External

pull-up resistors or current sources, such as the LTC1694

SMBus accelerator, are required on these lines. The

LTC3589isbothaslavereceiverandslavetransmitter. The

Each byte sent to or received from the LTC3589 must

be 8 bits long followed by an extra clock cycle for the

acknowledge bit. The data should be sent to the LTC3589

most significant bit (MSB) first.

2

I C control signals, SDA and SCL are scaled internally to

the DV supply. DV should be connected to the same

DD

2

I C Acknowledge

power supply as the bus pull-up resistors.

2

The acknowledge signal is used for handshaking between

the master and the slave. When the LTC3589 is written to,

it acknowledges its write address and subsequent register

address and data bytes. When reading from the LTC3589,

it acknowledges its read address and 8-bit status byte.

The I C port has an undervoltage lockout on the DV

DD

2

pin. When DV is below approximately 1V, the I C serial

DD

port is reset to power-on states and registers are set to

default values.

2

I C Bus Speed

An acknowledge pulse (active LOW) generated by the

LTC3589 lets the master know that the latest byte of

information was transferred. The master generates the

clock cycle and releases the SDA line (HIGH) during the

acknowledgeclockcycle.TheLTC3589pullsdowntheSDA

line during the write acknowledge clock pulse so that it is

a stable LOW during the HIGH period of this clock pulse.

2

The I C port operates at speeds up to 400kHz. It has

built-in timing delays to ensure correct operation when

2

addressed from an I C compliant master device. It also

containsinputfiltersdesignedtosuppressglitchesshould

the bus become corrupted.

2

I C START and STOP Conditions

2

I C Slave Address

A bus master signals the beginning of communications

by transmitting a START condition. A START condition is

generated by transitioning SDA from HIGH to LOW while

SCL is HIGH. The master may transmit either the slave

write or the slave read address. Once data is written to the

LTC3589, the master may transmit a STOP condition that

The LTC3589 responds to factory programmed read and

write addresses. The write address is 0x68. The read ad-

dress is 0x69. The least significant bit of the address byte,

known as the read/write bit, is 0 when writing data to the

LTC3589 and 1 when reading from it.

ADDRESS

SUB ADDRESS

ADDRESS

DATA

0

1

0

1

0

WR

S7 S6 S5 S4 S3 S2 S1 S0

0

1

0

1

0

RD

R7 R6 R5 R4 R3 R2 R1 R0

START

ACK

STOP

0

SDA

SCL

1

2

1

3

0

4

1

5

0

6

0

7

0

8

ACK

9

0

1

2

1

3

0

4

1

5

0

6

0

7

1

8

ACK

9

ACK

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

3589 F20

Figure 20. LTC3589 I²C Serial Port Read Pattern

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I C Sub-Addressed Writing

2

information for each of the next 8 clock cycles. A STOP

condition is not required for the read operation. The read

sub address is stored until a new sub address is written.

The LTC3589 has 14 writable command registers for

2

control inputs. They are accessed by the I C port via a

sub-addressed writing system.

Verify the data written to the internal data hold latches

prior to committing data to the command registers by

reading back the data before sending a STOP condition.

Each write cycle of the LTC3589 consists of a series of

three or more bytes beginning with the LTC3589 write ad-

dress.Thesecondbyteisthesubaddressofthecommand

registerbeingwrittento.Thesubaddressisapointertothe

register where the data in the third byte will be stored. The

third byte is the data to be written to the just-received sub

address. Continue alternating sub address and data bytes

to write multiple registers in a single START sequence.

ContinuouslypollaregisterbyrepeatedlysendingaSTART

conditionfollowedbytheLTC3589readaddress, andthen

clocking the data out after the read address acknowledge.

2

I C Command and Status Registers

2

Table 17 and Table 18 show the LTC3589 I C command

and status registers. System control register (SCR1) sets

the operating modes of the switching regulators. Each

step-down switching regulator has pulse-skipping, Burst

Mode operation, or forced continuous operation. The

buck-boost switching regulator can be put in continuous

or Burst Mode operation.

2

I C Bus Write Operation

The master initiates communication with the LTC3589

with a START condition and the LTC3589 write address.

If the address matches that of the LTC3589, the LTC3589

returns an acknowledge pulse. The master should then

deliver the sub address. Again the LTC3589 acknowl-

edges and the cycle is repeated for the data byte. The

data byte is transferred to an internal holding latch

upon the return of its acknowledge by the LTC3589.

Continue writing sub address and data pairs into the

holding latches. Addressing the LTC3589 is not required

for each sub address and data pair. If desired a REPEAT-

START condition may be initiated by the master where

The output voltage enable (OVEN) command register

controls the individual enables of each regulator. When

OVEN[7] is set to a logic LOW value, bits OVEN[6-0] are

ORed with their respective enable pins. When OVEN[7]

is HIGH, the input pins EN1, EN2, EN3, EN4, EN_LDO2,

and EN_LDO34, are ignored and the LTC3589 regulators

respond only to the OVEN register. When the regulators

are configured in a hard wired power-up sequence, setting

OVEN[7] allows software control of individual regulators.

When the PWR_ON pin is pulled LOW all bits in the OVEN

register are reset to POR state of 0x00.

2

another device on the I C bus is addressed. The LTC3589

remembers the valid data it has received. Once all the

2

devices on the I C have been addressed and sent valid

data and a global STOP has been sent, the LTC3589 will

update its command latches with the data it has received.

Systemcontrolregister2(SCR2)controlstheoperationof

the regulator start-up and regulator power good (PGOOD)

hard shutdown operation. Command register bit SCR2[7]

controlstheLTC3589behaviorduringanextendedPGOOD

fault condition longer than 14ms. Bit SCR2[7] does not

alter PGOOD status reporting by the IRQ pin or IRQSTAT

status register. The bits in SCR2[6-0] control whether a

regulator will wait to turn on when its output is greater

than 300mV. Default POR LOW cause the LTC3589 and

LTC3589-1 regulators to wait for the output to discharge

to less than 300mV. Default POR low of the LTC3589-2

allows the regulators to start at any output voltage.

2

I C Sub-Addressed Reading

2

The LTC3589 I C interface supports random address

reading of the I C command and status registers. Before

reading a register, the registers sub address must be

written. Send a START condition followed by the LTC3589

write address followed by the sub address of the register

to be read. The sub address is now stored as a pointer to

the register. Send a REPEAT-START condition followed

by the LTC3589 read address. Following the acknowledg-

ment of its read address the LTC3589 returns one bit of

3589fh

37

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

Table 17. LTC3589 Command Register Table

REG

NAME B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

DEFAULT

0x07

SCR1

Buck-Boost

Mode:

Step-Down Switching

Regulator 3 Mode :

Step-Down Switching

Regulator 2 Mode :

Step-Down Switching

Regulator 1 Mode :

0000 0000

0 = Continuous 0 0 = Pulse-Skipping

1 = Burst Mode 0 1 = Burst

1 0 = Forced Continuous

0 0 = Pulse-Skipping

0 1 = Burst

0 0 = Pulse-Skipping

0 1 = Burst

1 0 = Forced Continuous

0x10

OVEN Software

EN_LDO4

EN_LDO3

EN_LDO2

EN4

EN3

EN2

EN1

0000 0000

Control Mode:

0 = Enable

with Pin or

OVEN Register

1 = Enable/

Disable with

OVEN Register

Only

0x12

LTC3589

SCR2 Mask PGOOD LDO4

LDO3

Start-Up:

LDO2

Start-Up:

Buck-Boost Step-Down

Step-Down

Switching

Step-Down

Switching

Regulator 1

Start-Up:

0000 0000

Hard

Start-Up:

Switching

Shutdown:

Regulator 3 Regulator 2

Start-Up:

0 = Allow

PGOOD

0 = Wait for

0 = Wait

0 = Wait for

Output <

0 = Wait

0 = Wait for

Output <

Output < 300mV for Output

for Output

< 300mV

for Output

Timeout Hard Before Enable < 300mV

300mV Before < 300mV

< 300mV Before 300mV Before

Shutdown.

1 = Inhibit

PGOOD Hard and Disable

Shutdown.

Before Enable Enable

Before Enable Before Enable Enable

Enable

1 = Don’t Wait 1 = Don’t Wait 1 = Don’t Wait 1 = Don’t Wait 1 = Don’t Wait 1 = Don’t Wait 1 = Don’t Wait

and Disable

Discharge

Resistor.

and Disable

Discharge

Resistor.

and Disable and Disable and Disable

Discharge

Resistor.

and Disable

Discharge

Resistor.

Discharge

Resistor.

Discharge

Resistor.

Discharge

Resistor.

0x12

LTC3589-1

SCR2 Mask PGOOD LDO4

LDO3

Start-Up:

LDO2

Start-Up:

Buck-Boost Step-Down

Step-Down

Switching

Step-Down

Switching

Regulator 1

Start-Up:

0000 0000

Hard

Start-Up:

Switching

Shutdown:

Regulator 3 Regulator 2

Start-Up:

0 = Inhibit

PGOOD

0 = Wait for

0 = Wait

0 = Wait for

Output <

0 = Wait

0 = Wait for

Output <

Output < 300mV for Output

for Output

< 300mV

for Output

Timeout Hard Before Enable < 300mV

300mV Before < 300mV

< 300mV Before 300mV Before

Shutdown.

1 = Allow

PGOOD Hard and Disable

Shutdown.

Before Enable Enable

Before Enable Before Enable Enable

Enable

1 = Don’t Wait 1 = Don’t Wait 1 = Don’t Wait 1 = Don’t Wait 1 = Don’t Wait 1 = Don’t Wait 1 = Don’t Wait

and Disable

Discharge

Resistor.

and Disable

Discharge

Resistor.

and Disable and Disable and Disable

Discharge

Resistor.

and Disable

Discharge

Resistor.

Discharge

Resistor.

Discharge

Resistor.

Discharge

Resistor.

3589fh

38

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

Table 17. LTC3589 Command Register Table

REG

NAME B[7]

B[6]

B[5]

B[4]

B[3]

Buck-Boost Step-Down Step-Down

Start-Up: Switching Switching

Regulator 3 Regulator 2

Start-Up: Start-Up:

B[2]

B[1]

B[0]

DEFAULT

0x12

LTC3589-2

SCR2 Mask PGOOD LDO4

LDO3

Start-Up:

LDO2

Start-Up:

Step-Down 0000 0000

Switching

Regulator 1

Start-Up:

Hard

Shutdown:

Start-Up:

0 = Inhibit

PGOOD

0 = Don’t Wait 0 = Don’t Wait 0 = Don’t Wait 0 = Don’t Wait 0 = Don’t Wait 0 = Don’t Wait 0 = Don’t Wait

for Output < for Output < for Output < for Output for Output < for Output < for Output <

Timeout Hard 300mV Before 300mV Before 300mV Before < 300mV

300mV Before 300mV Before 300mV Before

Shutdown.

Enable

Before Enable Enable

Enable

1 = Allow

1 = Wait for

Output <

1 = Wait

1 = Wait for 1 = Wait for

1 = Wait for

Output <

PGOOD Hard Output < 300mV Output <

for Output

Output < Output <

Shutdown.

Before Enable 300mV Before 300mV Before < 300mV

300mV Before 300mV Before 300mV Before

Enable

Before Enable Enable

Enable

0x20

VCCR LDO2

Start LDO2

Slew:

Step-Down

Switching

Regulator 3

Reference

Select:

Start

Step-Down Start

Step-Down

Switching

Start

0000 0000

Reference

Select:

Step-Down

Switching

Regulator 3

Slew:

Switching

Step-Down

Switching

Regulator 1

Slew:

Regulator 2 Switching

Regulator 1

Reference

Select:

Regulator 2 Reference

Slew:

Select:

0 =

0 = Went

1 = GO

0 =

0 = Went

1= GO

0 =

0 = Went

1= GO

0 =

0 = Went

1= GO

L2DTV1[4-0]

B3DTV1[4-0]

B2DTV1[4-0]

B1DTV1[4-0]

1 =

L2DTV2[4-0]

B3DTV2[4-0]

B2DTV2[4-0]

B1DTV2[4-0]

0x21

0x23

CLIRQ

B1DTV1 Step-Down Switching

Regulator Switch DV/DT

Control:

PGOOD Mask: Step-Down Switching Regulator 1 Feedback Reference Input (V1)

0 = PGOOD

0001 1001

Low When

Slewing

00000 = 362.5mV

11001 = 675mV

11111 = 750mV

00 = 1ns

01 = 2ns

10 = 4ns

11 = 8ns

1 = PGOOD 12.5mV Step Size

Not Forced

Low When

Slewing.

0x24

0x25

B1DTV2 Keep-Alive

Mode:

Phase

Select:

Step-Down

Switching

Regulator 1 11001 = 675mV

Step-Down Switching Regulator 1 Feedback Reference Input (V2)

00000 = 362.5mV

0001 1001

1111 1111

0 = Normal

Shutdown

0 = Clock

Phase 1

Clock Rate

11111 = 750mV

12.5mV Step Size

0 = 2.25MHz

1 = 1.12MHz

1= Keep-Alive 1 = Clock

Phase 2

VRRCR LDO2 Dynamic Reference

Slew Rate:

Step-Down Switching

Regulator 3 Dynamic

Reference Slew Rate:

Step-Down Switching

Regulator 2 Dynamic

Reference Slew Rate:

Step-Down Switching

Regulator 1 Dynamic

Reference Slew Rate:

00 = 0.88mV/µs

01 = 1.75mV/µs

10 = 3.5mV/µs

11 = 7mV/µs

00 = 0.88mV/µs

01 = 1.75mV/µs

10 = 3.5mV/µs

11 = 7mV/µs

00 = 0.88mV/µs

01 = 1.75mV/µs

10 = 3.5mV/µs

11 = 7mV/µs

00 = 0.88mV/µs

01 = 1.75mV/µs

10 = 3.5mV/µs

11 = 7mV/µs

3589fh

39

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

Table 17. LTC3589 Command Register Table

REG

NAME B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

DEFAULT

0x26

B2DTV1 Unused

PGOOD Mask: Step-Down Switching Regulator 2 Feedback Reference Input (V1)

0001 1001

0 = PGOOD 00000 = 362.5mV

Low When

Slewing

11001 = 675mV

11111 = 750mV

12.5mV Step Size

1 = PGOOD

Not Forced

Low When

Slewing.

0x27

0x29

B2DTV2 Keep-Alive

Mode:

Phase

Select:

Step-Down

Switching

Regulator 2 00000 = 362.5mV

Step-Down Switching Regulator 2 Feedback Reference Input (V2)

0001 1001

0 = Normal

Shutdown

0 = Clock

Phase 1

Clock Rate

11001 = 675mV

11111 = 750mV

12.5mV Step Size

0 = 2.25MHz

1 = 1.125MHz

1= Keep-Alive 1 = Clock

Phase 2

B3DTV1 Unused

PGOOD Mask: Step-Down Switching Regulator 3 Feedback Reference Input (V1)

0 = PGOOD 00000 = 362.5mV

Low When

Slewing

11001 = 675mV

11111 = 750mV

12.5mV Step Size

1 = PGOOD

Not Forced

Low When

Slewing.

0x2A

0x32

B3DTV2 Keep-Alive

Mode:

Phase

Select:

Step-Down

Switching

Regulator 3 00000 = 362.5mV

Step-Down Switching Regulator 3 Feedback Reference Input (V2)

0001 1001

0 = Normal

Shutdown

0 = Clock

Phase 1

Clock Rate

11001 = 675mV

11111 = 750mV

12.5mV Step Size

0 = 2.25MHz

1 = 1.125MHz

1= Keep-Alive 1 = Clock

Phase 2

L2DTV1 Keep-Alive

Unused

PGOOD Mask: LDO 2 Feedback Reference Input (V1)

Mode:

0 = PGOOD 00000 = 362.5mV

0 = Normal

Shutdown

Low When

Slewing

11001 = 675mV

11111 = 750mV

12.5mV Step Size

1= Keep-Alive

1 = PGOOD

Not Changed

When

Slewing.

3589fh

40

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

Table 17. LTC3589 Command Register Table

REG

NAME B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

DEFAULT

0x33

L2DTV2 LDO4 Control LDO4 Output Voltage:

MODE:

LDO 2 Feedback Reference Input (V2)

0001 1001

LTC3589

00 = 2.8V

01 = 2.5V

10 = 1.8V

11 = 3.3V

00000 = 362.5mV

11001 = 675mV

11111 = 750mV

12.5mV Step Size

0 = LDO4

Enable with

EN_LDO34

1 = LDO4

Enable with

OVEN[6]

0x33

L2DTV2 Unused

LDO4 Output Voltage:

LDO 2 Feedback Reference Input (V2)

0001 1001

LTC3589-1

LTC3589-2

00 = 1.2V

01 = 1.8V

10 = 2.5V

11 = 3.2V

00000 = 362.5mV

11001 = 675mV

11111 = 750mV

12.5mV Step Size

Table 18. LTC3589 Read-Only Status Register Table

REG NAME B[7] B[6] B[5]

Near Thermal Undervoltage Near Undervoltage PGOOD

B[4]

B[3]

B[2]

B[1]

B[0]

0x02 IRQSTAT Thermal

Limit Hard

Unused

Limit

Hard Shutdown Limit

Occurred

Timeout Hard

Shutdown

Occurred

Shutdown

Occurred

0x13 PGSTAT LDO4 Status: LDO3 Status: LDO2 Status: Buck_Boost Status: Step-Down

Step-Down

Switching

Regulator 2

Status:

Step-Down

Switching

Regulator 1

Status:

LDO1 Status:

Switching

Regulator 3

Status:

0 = V

1 = V

Low 0 = V

Good 1 = V

Low 0 = V

Good 1 = V

Low 0 = V

Good 1 = V

Low

0 = V

1 = V

Low 0 = V

Low

OUT

Good

Good 1 = V

Good

OUT

3589fh

41

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

LDO2andstep-downswitchingregulators1to3eachhave

a pair of control bits in the voltage change control register

VCCR. The reference select bit selects which of two 5-bit

words are used as inputs to the regulators feedback refer-

ence DAC inputs. The slew GO bit initiates a DAC slew to

the voltage selected by the reference select bit. When the

slew is complete, the slew GO bits are reset LOW.

value. The slew rate of the output voltage is scaled by the

gain of the resistor divider network that sets the regulator

output voltage. For example, a regulator set to an output

voltage of 1.2V when the dynamic target voltage reference

is 0.75V has a gain of 1.6. Slewing the regulator output

from 1.2V to 1V requires slewing the DAC output down

125mV from 750mV to 625mV. With a VRRCR slew rate

setting of 01 the slew time of the regulator output is 71µs.

Accessing the CLIRQ command register will clear the IRQ

pin and will let the IRQ pin to release HIGH. The pin is

clearedwhentheLTC3589acknowledgesthesubaddress.

Data written to the CLIRQ command register is ignored.

THERMAL CONSIDERATIONS AND BOARD LAYOUT

Printed Circuit Board Power Dissipation

There are eight command registers that are used to store

the 5-bit dynamic target voltage input to the feedback

reference slewing DACs – B1DTV1, B1DTV2, B2DTV1,

B2DTV2, B3DTV1, B3DTV2, L2DTV1 and L2DTV2. The

registers ending with V2 use bits 4 through 0 to store

the V2 feedback reference voltage for the regulators. The

regulators input reference voltage is set to V2 by setting

the reference select bits HIGH in VCCR and writing to the

go bits in VCCR. The V2 voltage is also selected whenever

the VSTB pin is driven HIGH. The registers ending with

V1 use bits 4 through 0 to store the V1 feedback voltage

reference for the regulators. The regulators input refer-

ence voltage is set to V1 voltage by setting the reference

select bits LOW in command register VCCR. Whenever

a new dynamic target voltage is set, either by changing

the 5-bit value or by changing the reference select bits in

VCCR, the go bits in VCCR must be written to initiate the

dynamic voltage slew. When bit 5 in B1DTV1, B2DTV1,

B3DTV1, and L2DTV1 is LOW the PGOOD pin pulls LOW

during a dynamic voltage slew. Bits 7 and 6 in B1DTV1

set the switch DV/DT rate for all the step-down switch-

ing regulators. Bit 5 in registers B1DTV2, B2DTV2 and

B3DTV2 selects the switching frequency of step-down

switching regulators 1, 2 and 3. Writing the bit LOW sets

the switching frequency to 2.25MHz. Writing the bit HIGH

sets the switching frequency to 1.125MHz.

In order to ensure optimal performance and the ability

to deliver maximum output power to any regulator, it is

critical that the exposed ground pad on the backside of

the LTC3589 package be soldered to a ground plane on

the board. The exposed pad is the only GND connection

2

fortheLTC3589.Correctlysolderedtoa2500mm ground

plane on a double sided 1oz copper board the LTC3589

has a thermal resistance (θ ) of approximately 34°C/W.

JA

Failuretomakegoodthermalcontactbetweentheexposed

pad on the backside of the package and an adequately

sized ground plane will result in thermal resistances far

greater than 34°C/W.

To ensure the junction temperature of the LTC3589 die

does not exceed the maximum rated limit and to prevent

overtemperature faults, the power output of the LTC3589

must be managed by the application. The total power dis-

sipation in the LTC3589 is approximated by summing the

power dissipation in each of the switching regulators and

the LDO regulators.

The power dissipation in a switching regulator is esti-

mated by:

100 –Eff

P_D(SWX)=(V_OUTX•I_OUTX)•

(W)

100

Where V

is the programmed output voltage, I

OUTX

The dynamic slew rates of the four feedback reference

DACs are independently set using bits in voltage ramp

rate command register (VRRCR). The rate shown is the

slew of the DAC output as it slews up or down to its target

is the load current and Eff is the % efficiency that can

be measured or looked up in an efficiency table for the

programmed output voltage.

3589fh

42

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LTC3589/LTC3589-1/

LTC3589-2

operaTion

The power dissipated by an LDO regulator is estimated by:

Printed Circuit Board Layout

P

_D(LDO)=(V_IN(LDO)– V_LDO) •I_LDO(W)

When laying out the printed circuit board, the following

checklist should be followed to ensure proper operation

of the LTC3589:

Where V is the programmed output voltage, V

is the LDO supply voltage, and I

current. If one of the switching regulator outputs is used

as an LDO supply voltage, remember to include the LDO

supply current in the switching regulator load current for

calculating power loss.

LDO

IN(LDO)

is the output load

LDO

1. Connect the exposed pad of the package (Pin 41)

directly to a large ground plane to minimize thermal

and electrical impedance.

2. The switching regulator input supply traces and their

decoupling capacitors should be as short as possible.

Connect the GND side of the capacitors directly to the

ground plane of the board. The decoupling capacitors

provide the AC current to the internal power MOSFETs

andtheirdrivers. Itisimportanttominimizeinductance

from the capacitors to the LTC3589 pins.

Anexampleusingtheequationsabovewiththeparameters

in Table 19 shows an application that is at the maximum

junction temperature of 125°C at an ambient temperature

of 85°C. LDO2, LDO3, and LDO4 are powered by step-

down switching regulator 2 and the buck-boost switching

regulator. The total load on those two switching regula-

tors is the sum of the application load and the LDO load.

This example is with the LDO regulators at one half rated

current and the switching regulators at three quarters

rated current.

3. Minimize the switching power traces connecting SW1,

SW2, SW3, and buck-boost switch pins SW4AB and

SW4CD to the inductors to reduce radiated EMI and

parasitic coupling. Keep sensitive nodes such as the

feedback pins away from or shielded from the large

voltage swings on the switching nodes.

Table 19. T_JCalculation Example

OUTPUT

V

IN

V

APP LOAD TOTAL

LOAD

EFF

POWER

DISS

OUT

4. Minimize the length of the connection between the

step-downswitchingregulatorinductorsandtheoutput

capacitors. Connect the GND side of the output capaci-

tors directly to the thermal ground plane of the board.

LDO1_VSTB 3.8V 1.2V

10mA

100mA

1.2A

10mA

100mA

1.2A

30mW

60mW

LDO2

LDO3

LDO4

1.8V 1.2V

3.3V 1.8V

3.3V 2.5V

3.8V 1.2V

3.8V 1.8V

3.8V 1.25V

3.8V 3.3V

150mW

80mW

5. Minimize the length of the connection between the

buck-boost regulator output (BB_OUT) and the output

capacitor.ConnecttheGNDsideoftheoutputcapacitor

directly to the thermal ground plane of the board.

V

80%

90%

85%

90%

290mW

140mW

300mW

OUT1

OUT2

OUT3

OUT4

0.65A

0.75A

0.70A

0.75A

0.90A

TOTAL POWER 1180mW

INTERNAL JUNCTION TEMPERATURE AT 85°C AMBIENT 125°C

3589fh

43

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

applicaTions inForMaTion

The LTC3589 is optimized to support several families of

advanced portable applications processors including the

Marvell PXA3xx and PXA168 Xscale processors, the Fre-

escale i.MX family including the new i.MX53 and i.MX51,

the TI OMAP processors utilizing their Smart reflex, and

many additional ARM processors.

The LTC3589 RSTO signal is used to drive the Monahans

hard reset signal nRESET and is based on the state of

the always-active regulator output LDO1_STBY and by a

pushbutton hard reset request. The release of the RSTO

output is delayed a minimum of 10ms as required or as

long as 1s when the LTC3589 is reset using its pushbut-

ton controller.

PXA3XX Monahans Processor Support

PXA16X Armada Processor Support

The PXA3XX processors are hard-coded to communicate

with a PMIC at specific command register addresses in

order to power up the processor supply rails from the

LTC3589 includes spare register bits that can be accessed

by the processor for setting and recalling hibernate and

resume operation.

2

low power state. The LTC3589 I C device address and

command register addresses map to PXA3xx command

register sub-address requirements. The LTC3589 write

address is 0x68. The key command register addresses

for PXA3xx support are the Output Voltage Enable (OVEN)

register at address 0x10. VCC_APPS/A_EN is mapped

to OVEN bit 0 (enable step-down switching regulator 1).

VCC_SRAM/S_EN is mapped to OVEN bit 2 (enable step-

down switching regulator 3). The voltage change control

register (VCCR) at command register address 0x20 con-

trols the dynamic voltage select and go bits required to

command a voltage change and slew when coming out of

low voltage standby or sleep modes into run mode. The

dynamic target voltage (xxDTV[1,2]) registers map to the

mandatory command register addresses. The full register

map for the LTC3589 shown in Table 17 and Table 18

The keep-alive function allow a step-down switching

regulator to maintain system memory during a hibernate

shutdown state of the Armada processor.

i.MX53 and i.MX51 Processor Support

The LTC3589 has hardware features specifically designed

for the latest i.MX family of processors from Freescale

Semiconductor. The i.MX53 and i.MX51 control the

VSTB input pin of the LTC3589 to command transitions

between the run mode core voltage and the lower level

standby voltage. The run and standby voltage levels are

2

initially programmed in I C command registers xxBTV1

and xxBTV2. When the VSTB pin is asserted high all four

dynamically controlled output supply rails will slew to the

xxBTV2 set point. When xxBTV1 and xxBTV2 are set at

the same value, as they are by default, then no slewing

occurs. This allows the single VSTB pin to control any

combination of the four DAC controlled regulators to slew

between two programmed output voltages. When VSTB is

de-asserted back to a zero value the regulators slew back

up to the xxBTV1 set point.

2

supports Monahans, hard-coded I C commands for start-

of-dayoperation,voltage-changesequence,supplyenable,

and return-to-D0 state sequence.

The LTC3589 does not specifically reference the Mona-

hans SYS_EN and PWR_EN enable pins but supports

these signals with individual enable input pins EN[1-4]

and EN_LDO[2,34] that should be hard-wired to SYS_EN

or PWR_EN as required for proper system-level power

sequencing.

3589fh

44

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LTC3589/LTC3589-1/

LTC3589-2

applicaTions inForMaTion

Earlieri.MXfamilyprocessorssuchasthei.MX31included

two VSTB pins used for controlling the regulator outputs

foralowvoltagestandbymode,nominalvoltagerunmode,

and a higher voltage overdrive mode. The LTC3589 can

be used with these processors using the VSTB input pin

to select between run and standby voltages and using

minimal software overhead to set the overdrive voltage

OMAP3 and DaVinci Processor Support

TheOMAP3familyofARMprocessorshassimilarrequire-

mentstotheprocessorsdescribedabove.TheLTC3589I C

2

control can fully accommodate the smart reflex dynamic

voltage control with proper embedded software drivers

tailored to the LTC3589 register mapping. The LTC3589

demo board demonstrates configuring and dynamically

2

in I C command registers.

2

slewingandsequencingtheoutputsusingI Ccontrol.The

The default DAC reference value in all xxBTVx registers

is 0x19. This accommodates i.MX processors and others

requiring an overdrive voltage. The value can be increased

up to 0x1F for overdrive or supply margining above the

same provisions can be incorporated into embedded soft-

ware drivers for the OMAP3 or any other target processor.

Back-Driving LTC3589 Outputs

2

nominal run voltage. Once programmed into the I C com-

Multirail processors or board level designs may have

surprise leakage paths between power rails. During a

start-up sequence an LTC3589 regulator output may be

pulled higher than 300mV. This violates the default set-

tings for a LTC3589 and LTC3589-1 start-up sequence.

The LTC3589-2 power up default is to allow its regulators

to enable at any output voltage and is recommended for

designs with rail back-drive conditions.

mand registers xxBTVx two voltage outputs are selected

by the VSTB pin. All voltage levels and changes are fully

2

controllable using the I C serial port.

Reference Designs and Drivers

Reference designs, schematics, and software drivers are

available to assist the development of Freescale i.MX53

systems that use the LTC3589. Please contact your local

Linear Technology sales representative for details.

3589fh

45

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

Typical applicaTion

V

IN

10µF

FREESCALE

i.MX536

10µF

1µH

37

IN

ARM CORE

1.10V RUN

0.85V STBY

1.6A

6

V

PV

IN1

NVCC_SRTC_PDW

7

SW1

VDDGP_1-15

100k

158k

10pF

47µF

V

RTC

1.3V

36

35

39

LDO1_STDBY

LDO1_FB

BUCK1_FB

25mA

1µF

100k

158k

10µF

24

PERIPHERAL CORE

1.31V RUN

0.95V STBY

1.2A

PV

IN2

1.5µH

SW2_VCC

25

33

SW2

VCC_1-33

LTC3589-2

IMX_LDO_1V8

22µF

180k

191k

10pF

22µF

VDD_ANA_PLL(LDO_OUT)

NVCC_CKIH

NVCC_RESET

ENABLE_DDR_1V5

BUCK2_FB

1.3V

22µF

10µF

VDD_DIG_PLL(LDO_OUT)

27

PV

IN3

IMX_LDO_1V8 10

WAKE 11

EN1

VDD_REG(IMX_LDO_1V8_IN)

NVCC_XTAL

NVCC_LVDS

2.2µH

2.5V 1.2A

26

34

EN2

SW3

SW2_VCC 13

DDR_1V5 14

9

NVCC_LVDS_BG

USB_OTG_VDDA25

USB_H1_VDDA25

VPH1

EN3

270k

100k

10pF

22µF

EN4

BUCK3_FB

EN_LDO2

EN_LDO3

PWR_ON

VHP2

18

10µF

15

16

VI-O

3.35V

1.2A

20

PV

IN4

NVCC_NANDF

NVCC_EIM_MAIN_1

NVCC_EIM_MAIN_2

NVCC_EIM_SEC

NVCC_SD1

PWR_ON

BB_OUT

511k

158k

21

ON

40

12

NVCC_SD2

BB_FB

NVCC_PATA

SW4AB

NVCC_FEC

NVCC_GPIO

2.5µH

NVCC_CSI

19

SW4CD

NVCC_KEYPAD

USB_H1_VDDA33

USB_OTG_VDDA33

1µF

ANALOG

1.3V

250mA

1

2

V

IN_LDO2

VDDA_1-4

VDDAL1

VP1-2

LDO2

180k

2.2µF

38

LDO2_FB

DDR_1V5

DDR_REF

NVCC_EMI_DRAM_1-5

DDR_REF

191k

10µF

ANALOG

2.8V

250mA

5

3

V

NVCC_LCD_1-2

NVCC_JTAG

TVDAC_AHVDDRGB_1-2

TVDAC_DHVDD

IN_LDO34

LDO3

2.2µF

3.2V 250mA

4

VDD_FUSE

LDO4

32

31

30

28

8

4.7k

47k

DV

DD

I2C2_SDA (KEY_ROW3)

I2C2_SCL (EMI_EB2)

PMIC_STBY_REQ

PMIC_ON_REQ

GPIO/PMIC_RDY

GPIO/IRQ

SDA

SCL

VSTB

47k

RST0

PGOOD

IRQ

PBSTAT

WAKE

PWR_ON

29

17

22

23

GPIO

V

FASTR_ANA

FASTR_DIG

GND 1-95

3589 TA02

IN

GND

41

47k

3589fh

46

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

Typical applicaTion

V

IN

10µF

FREESCALE

i.MX51

10µF

1µH

37

IN

6

V

PV

IN1

NVCC_SRTC_POW

V

CORE

0.647V TO 1.34V

1.6A

7

SW1

V

CC(CORE)

V

RTC

FASTR_ANA

FASTR_DIG

604k

768k

10pF

47µF

36

35

1.2V

LDO1_STDBY

LDO1_FB

39

24

25

33

25mA

BUCK1_FB

511k

1µF

10µF

PV

IN2

V

/DDR

1.8V

1A

SRAM

NVCC_EMI_DRAM

NVCC_CNTL_EMI

NVCC_PER2,3,4,5,6,8,9

NVCC_EMI(NAND+EMI)

1.5µH

1.02M

SW2

LTC3589

715k

422k

10pF

22µF

BUCK2_FB

18.2k

V

9.09k

SRAM

10µF

10k

V

27

26

34

SOC

PV

IN3

V

10

SOC

10k

EN1

EN2

0.676V to 1.4V

1A

11

13

14

9

18

20

1.5µH

SW3

VDDGP

WAKE

EN3

EN4

EN_LDO2

EN_LDO34

PWR_ON

9.09k

681k

787k

10pF

22µF

V

CORE

BUCK3_FB

10k

PWR_ON

10µF

15

16

V

IO

3.3V

1.2A

PV

IN4

VDDA33

VDD_FUSE

NVCC__EMI

NVCC_PER13,14

BB_OUT

21

1M

4.7pF

ON

40

BB_FB

316k

12

19

SW4AB

SW4CD

2.7µH

V

1µF

VDDA

VDD_DIG_PLL_A&B

VDD_TVDIG

MEMORY

1

2

0.647V TO 1.34V

250mA

V

IN_LDO2

LDO2

V

ANALOG

1.8V

604k

VDD_AVA_PLL_A&B

NVCC_IPU

38

250mA

1µF

LDO2_FB

768k

1µF

5

3

VDD_TVSUPPLY

AHVDDRGB

V

IN_LDO34

LDO3

NVCC_DAC

1µF

NVCC_TV_BACK

NVCC_USBPHY

NVCC_OSC

V

AUX

2.8V

4

250mA

LDO4

1µF

47k

4.7k 4.7k

47k

32

31

30

28

23

22

29

17

8

DV

DD

PWR_ON

GPIO

SDA

SCL

VSTB

I2C2_SDA

I2C2_SCL

PMIC_VSTBY_REQ

GPIO

WAKE

PBSTAT

PGOOD

IRQ

GPIO

PMIC_RDY

GPIO1/IRQ

POR_B

RST0

GND

41

3589 TA03

3589fh

47

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

package DescripTion

Please refer to http://www.linear.com/product/LTC3589#packaging for the most recent package drawings.

UJ Package

40-Lead Plastic ꢀFN (6mm × 6mm)

(Reference LTC DWG # 05-08-1728 Rev Ø)

0.70 ±0.05

6.50 ±0.05

5.10 ±0.05

4.42 ±0.05

4.50 ±0.05

(4 SIDES)

4.42 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 ± 0.05

R = 0.115

TYP

6.00 ± 0.10

(4 SIDES)

R = 0.10

TYP

39 40

0.40 ± 0.10

PIN 1 TOP MARK

(SEE NOTE 6)

1

2

PIN 1 NOTCH

R = 0.45 OR

0.35 × 45°

CHAMFER

4.42 ±0.10

4.50 REF

(4-SIDES)

4.42 ±0.10

(UJ40) QFN REV Ø 0406

0.200 REF

0.25 ± 0.05

0.50 BSC

0.00 – 0.05

NOTE:

BOTTOM VIEW—EXPOSED PAD

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

3589fh

48

For more information www.linear.com/LTC3589

LTC3589/LTC3589-1/

LTC3589-2

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

9/10

Removed 0V from LDO4 on Block Diagram

15

3

B

12/10 Updated Part Marking in Order Information section

02/11 LTC3589-1 part added. Changes reflected throughout the data sheet

01/12 Updated part numbers on iMx application processors

Updated Absolute Maximum Ratings and Pin Configuration sections

Added Reference Designs and Drivers section

C

1-46

1, 42

3

D

43

Added Typical Application

44

Updated Typical Application

45

E

F

03/12 Added LTC3589-2 throughout

1-50

17

Updated Table 1: LTC3589/-1/-2 Functional Differences

Clarified Enable and Power-On Sequencing section

31-32

37

2

Clarified I C Command and Status Register sections

Enhanced Command Register Table

Added section on Back-Driving Outputs

02/13 Clarified Absolute Maximum Ratings

Clarified WAKE pin function operation

Clarified buck-boost inductor part numbers

Clarified EN pin operation

38-39

45

3

14

27

31

2

Clarified I C timing diagram

36

Clarified Command Register Table

07/15 Changed pin name on Typical Application

Changed pin names on Pin Configuration

Modified conditions and symbols

39, 41

1

G

3

4-7

18

Changed pin name in the LDO Regulator 2 section

Changed Command Register [Bit] name in Table 2

Modified equation in the Operating Modes section

Modified equation variables

19

26

43

Updated Table number references

44

Modified Typical Application circuits

46, 47, 50

3

H

09/16 Corrected T

from +125°C to +150°C

JMAX

3589fh

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

49

For more information www.linear.com/LTC3589

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3589/LTC3589-1/

LTC3589-2

Typical applicaTion

Integrated Power IC for Mobile µProcessor System with USB/Automotive Battery Charger

C7

0.47µF

3.3V, 25mA

10µF

P

10µF

2

L2

10µH

V

IN

4

37

6

24

VIN2

27

15

VIN4

SW1

V

BOOST

SW

IN

HVBUCK

3

8

R2

C6

68nF

V

P

C1

4.7µF

IN

VIN1

VIN3

1µH

150k

5

V

B1

7

36

35

R11

499k

C4

22µF

LT3480

LDO1_STDBY

1.2V

1.6A

RUN/SS

10

1µF

1M

10pF 604k

768k

R

T

FB

GND BD SYNC

39

R6

40.2k

47µF

R12

100k

LDO1_FB

BUCK1_FB

PG

V

C

7

9

11

1

6

316K

68k

1.5µH

8

V

B2

C2

10µF

0805

M4

25

33

RSTO

EN1

1.8V

1A

SW2

L1

3.3µH

10

11

13

14

9

LTC3589

10pF 715k

422k

V

EN2

C5

B1

20 18

19

14

22µF

BUCK2_FB

13

10µF

V

EN3

USB

V

WALL ACPR SW

C

L2

BUS

0805

EN4

B3

B2

V

EN_LDO2

EN_LDO34

WAKE

PWR_ON

PGOOD

IRQ

OVGATE

2

1

12

V

B3

26

34

OVGATE

OVSENS

D0–D2

V

18

23

20

29

17

OUT

1.2V

1A

SW3

BB

10

11

68k

IDGATE

BAT

M5

10pF 681k

787k

15-17

TO µC

22µF

BUCK3_FB

8

4

LTC4098

68k

CHRG

68k

NTCBIAS

R7

V

BB

100k

16

5

32

31

30

3.3V

1A

BB_OUT

NTC

V

DV

DD

BB

CLPROG PROG GND BATSENS

4.7k

SDA

SCL

R8

100k

4.7pF 1M

316k

3

7

9, 21

6

T

C3

0.1µF

0603

40

12

22µF

R9

R10

1k

+

BB_FB

Li-Ion

2.94k

28

22

21

SW4AB

TO µP

VSTB

PBSTAT

ON

68k

2.7µH

M1

M2

19

1

ZXMP10A18G

SW4CD

HVIN

V

B2

VIN_LDO2

AUTOMOTIVE,

FIREWIRE,

ETC.

V

L2

1.2V

D1

2

LDO2

MMBZ524-

0BLT1G

10V

R5

250mA

10k

1µF

V

604k

768k

38

5

LDO2_FB

R1

1k

R3

33k

VIN_LDO34

V

BB

M3

L3

3

4

ZXMN10A08E6

R4

10k

1.8V

250mA

LDO3

1µF

V

L4

LDO4

2.8V

250mA

GND

41

3589 TA04

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

Seamless Transition Between Multiple Input Power Sources, V Range: 1.8V to 5.5V,

LTC3101

1.8V to USB, Multioutput DC/DC

Converter with Low Loss USB Power

Controller

IN

Buck-Boost Converter V

Range: 1.5V to 5.25V, 3.3V at 800mA for V ≥ 3V, Dual

OUT IN

OUT

350mA Buck Regulators, V : 0.6V to V , 38μA Quiescent Current in Burst Mode

OUT

IN

Operation, 24-Lead 4mm × 4mm × 0.75mm QFN Package

Switching USB Power Manager PMIC Complete Multifunction PMIC: Switching Power Manager, 1A Buck-Boost + 2 Buck

with Li-Ion/Polymer Charger Regulators + LDO, 4mm × 5mm QFN-28 Package

LTC3577/LTC3577-1/ Highly Integrated Portable/Navigation Complete Multifunction PMIC: Linear Power Manager and Three Buck Regulators,

LTC3577-3/LTC3577-4 PMIC 10-LED Boost Reg, 4mm × 7mm QFN-44 Package, -1 and -4 Versions Have 4.1V

, -3 Version for SiRF Atlas IV Processors

LTC3556

V

FLOAT

LTC3586/LTC3586-1

Switching USB Power Manager PMIC Complete Multifunction PMIC: Switching Power Manager, 1A Buck-Boost + 2 Bucks +

with Li-Ion/Polymer Charger Boost + LDO, 4mm × 6mm QFN-38 Package, -1 Version Has 4.1V V

.

FLOAT

3589fh

LT 0916 REV H • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

50

For more information www.linear.com/LTC3589

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3589

●

 LINEAR TECHNOLOGY CORPORATION 2010


型号：	LTC3589HUJ-2#PBF
厂家：	Linear
描述：	LTC3589 - 8-Output Regulator with Sequencing and I2C; Package: QFN; Pins: 40; Temperature Range: -40°C to 125°C 开关输出元件
文件：	总50页 (文件大小：677K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3589HUJ-2#PBF [Linear]

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