LTC3589IUJ-TRPBF_技术文档

Electrical Specifications Subject to Change

LTC3589

8-Output Regulator with

2

Sequencing and I C

FEATURES

DESCRIPTION

2

The LTC^®3589 is a complete power management solu-

tion for ARM and ARM-based processors and advanced

portable microprocessor systems. The device contains

three synchronous step-down DC/DC converters for

core, memory and SoC rails, a synchronous buck-boost

regulator for I/O at 3.3V to 5V, and three 250mA LDO

n

Triple I C Adjustable High Efﬁciency Step-Down

Switching Regulators: 1.6A, 1A, 1A

n

High Efﬁciency 1.2A Buck-Boost Switching Regulator

n

Triple 250mA LDO Regulators

n

Always Alive 25mA LDO Regulator

n

Flexible Pin-Strap Sequencing Operation

2

n

I C and Independent Enable Control Pins

regulatorsforlownoiseanalogsupplies. AnI Cserialport

n

Power Good and Reset Outputs

is used to control regulator enables, output voltage levels,

dynamic voltage scaling and slew rate, operating modes

and status reporting. Regulator start-up is sequenced by

connecting regulator outputs to enable pins in the desired

n

Dynamic Voltage Scaling and Slew Rate Control

n

Selectable 2.25MHz or 1.12MHz Switching Frequency

n

Pushbutton ON/OFF Control with System Reset

n

2

10μA Standby Current

order or via the I C port. System power-on, power-off

n

40-Pin 6mm × 6mm × 0.75mm QFN

and reset functions are controlled by pushbutton inter-

2

face, pin inputs, or I C interface. The LTC3589 supports

APPLICATIONS

i.MX, PXA and OMAP processors with eight independent

rails at appropriate power levels, dynamic control and

sequencing. Other features include interface signals such

as the VSTB pin that toggles between programmed run

and standby output voltages on up to four rails simultane-

ously. The device is available in a low proﬁle 40-pin 6mm

× 6mm exposed pad QFN package.

n

Handheld Instruments and Scanners

n

Portable Industrial Devices

n

Automotive Infotainment

n

Portable Medical Devices

n

High End Consumer Devices

n

Multirail Systems

n

Supports Freescale i.MX, Marvell PXA and Other

L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered

trademarks, Hot Swap and Bat-track are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

Application Processors

TYPICAL APPLICATION

V

2.7V TO 5.5V

IN

Start-Up Sequence

V

IN

CORE

VRTC 1.2V

AT 25mA

SW1

SW2

SW3

0.6V TO 1.2V

AT 1.6A

LDO1_STDBY

I/O

V

MEMORY

0.9V TO 1.2V

AT 250mA

SRAM

LTC3589

WAKE

(1V/DIV)

0.9V TO 1.8V

AT 1A

LDO2

V

SRAM

V

SOC

ANALOG 1.8V

AT 250mA

ANALOG

LDO3

LDO4

0.625V TO 1.25V

AT 1A

DDR

MEMORY

V

SOC

1.8V, 2.5V,

2.8V, 3.3V

AT 250mA

MEMORY

3

7

SW4AB

SW4CD

BB_OUT

2

V

CORE

I C

I/O

ENABLES

VSTB

3589 TA01b

500μs/DIV

3.3V AT 1.2A

FROM μPROCESSOR

OR 5V AT 1A

PWR_ON

WAKE

HDD

OR I/O

ON (PB)

PBSTAT

PGOOD

RSTO

GND

3589 TA01a

3589p

1

LTC3589

TABLE OF CONTENTS

Features............................................................................................................................ 1

Applications ....................................................................................................................... 1

Typical Application ............................................................................................................... 1

Description......................................................................................................................... 1

Absolute Maximum Ratings..................................................................................................... 3

Pin Conﬁguration ................................................................................................................. 3

Order Information................................................................................................................. 3

Electrical Characteristics........................................................................................................ 4

Typical Performance Characteristics .......................................................................................... 8

Pin Functions.....................................................................................................................12

Block Diagram....................................................................................................................14

Operation..........................................................................................................................15

Introduction.......................................................................................................................................................... 15

Always-On LDO..................................................................................................................................................... 16

250mA LDO Regulators........................................................................................................................................ 16

Step-Down Switching Regulators......................................................................................................................... 18

Buck-Boost Switching Regulator .......................................................................................................................... 22

Slewing DAC Reference Operation........................................................................................................................ 26

Pushbutton Operation........................................................................................................................................... 27

Enable and Power-On Sequencing ........................................................................................................................ 29

Fault Detection, Shutdown, and Reporting............................................................................................................ 30

2

I C Operation........................................................................................................................................................ 32

Thermal Considerations and Board Layout........................................................................................................... 38

Applications Information .......................................................................................................40

Typical Application ..............................................................................................................42

Package Description ............................................................................................................43

Typical Application ..............................................................................................................44

Related Parts.....................................................................................................................44

3589p

2

LTC3589

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 3)

SW1, SW2, SW3, SW4AB, SW4CD (Transients < 1ms,

Duty Cycle < 1%) ......................................... –0.3V to 7V

VSTB, EN1, EN2, EN3, EN4, EN_LDO2, EN_LDO34, ON,

PBSTAT, WAKE, RSTO, PWR_ON, IRQ, ....... –0.3V to 6V

PV , PV , PV , PV ............... –0.3V to V + 0.3V

SDA, SCL .....................................–0.3V to DV to 0.3V

IN1

IN2

, V

DD

IN3

IN4

IN

IN +

DD

V

..........................–0.3V to V

0.3V

Operating Junction Temperature Range

IN_LDO2 IN_LDO34

V , DV ..................................................... –0.3V to 6V

(Note 2)..................................................–40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

IN

LDO1_STBY,LDO1_FB,BUCK1_FB,BUCK2_FB,BUCK3_FB,

BB_FB, BB_OUT, LDO2, LDO2_FB,LDO3, LDO4, PGOOD,

PIN CONFIGURATION

TOP VIEW

40 39 38 37 36 35 34 33 32 31

V

1

2

3

4

5

6

7

8

9

30

29

28

SCL

IN_LDO2

LDO2

PGOOD

VSTB

LDO3

LDO4

27 PV

IN3

V

26 SW3

25

41

GND

IN_LD34

PV

SW2

IN1

SW1

24 PV

IN2

RSTO

23

WAKE

EN_LDO2

22 PBSTAT

21

EN1 10

ON

11 12 13 14 15 16 17 18 19 20

UJ PACKAGE

40-LEAD (6mm × 6mm) PLASTIC QFN

T

= 125°C, θ = 34°C/W

JA

JMAX

EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC3589EUJ#PBF

LTC3589IUJ#PBF

LTC3589HUJ#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTC3589EUJ#TRPBF

LTC3589IUJ#TRPBF

LTC3589HUJ#TRPBF

3589

40-Lead (6mm × 6mm) Plastic QFN

–40°C to 125°C

–40°C to 150°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

3589p

3

LTC3589

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating junction

temperature range, otherwise speciﬁcations are at T_A= 25°C (Note 2). V_IN= PV_IN1= PV_IN2= PV_IN3= PV_IN4= V_{IN_LDO2}= V_{IN_LDO34}

= DV_DD= 3.8V. All regulators disabled unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

5.5

17

UNITS

V

l

V

Operating Input Supply Voltage, V

2.7

IN

I

f

V

Quiescent Current

IN

All Enables = 0V

10

μA

VINLDO1

OSC

Oscillator Frequency

1.9

2.25

2.6

MHz

Step Down Switching Regulators 1, 2, and 3

l

I

Pulse-Skipping Mode V Quiescent Current

V

= 0.85V (Note 5)

135

27

TBD

μA

VIN

IN

FB

Per Buck

Burst Mode^®V Quiescent Current Per Buck

40

μA

IN

I

Feedback Pin Input Current

Maximum Duty Cycle

V

= 0.8V

= 0V

–0.1

100

0.1

FB

D

R

%

X

SW Pull-Down Resistance

Soft-Start Rate

Regulators Disabled

(Note 6)

2000

2

Ω

SW

t

V/ms

V

SS

l

V

Maximum Feedback Voltage

BxDTV1 = BxDTV2 = 11111,

V

0.735

0.351

2.2

0.75

0.765

0.374

FB(MAX)

= 2.7V to 5.5V

IN

V

Feedback LSB Step Size

12.5

mV

V

FB(LSB)

FB(MIN)

Minimum Feedback Voltage

BxDTV1 = BxDTV2 = 00000,

V

0.3625

= 2.7V to 5.5V

IN

1.6A Step Down Switching Regulator 1 (Buck 1)

Peak PMOS Current Limit SW1

I

2.7

180

110

A

mΩ

LIM1

RP1

RN1

R

of PMOS1

of NMOS1

I

= 100mA

DS(ON)

SW1

1.0A Step Down Switching Regulators 2 and 3

Peak PMOS Current Limit SW2

l

I

1.5

1.9

250

130

A

mΩ

LIM2, 3

RP2, 3

RN2, 3

R

of PMOS3

of NMOS3

DS(ON)

1.2A Buck-Boost Switching Regulator 4 (Buck-Boost)

l

I

PWM Mode V Quiescent Current

V

= 0.85V

BB_FB

130

19

μA

VIN

IN

Burst Mode V Quiescent Current

IN

l

V

Feedback Voltage

= 2.7V to 5.5V, V = 5.5V

OUT

0.776

1.8

0.8

0.824

5.0

V

BB_FB

OUTBB

LIM4

IN

Output Voltage Range

l

I

Peak PMOS Current Limit SW4AB

Forward Burst Current Limit (Switch A)

Reverse Current Limit (Switch D)

Reverse Burst Current Limit (Switch D)

2.5

2.7

500

800

0

A

Burst Mode Operation

mA

mΩ

Ω

PEAK4

LIMR4

ZERO4

RP4

RN4

R

of Switch A and Switch D

of Switch B and Switch C

I

= I

= 100mA

160

110

2000

2

DS(ON)

SW4AB

SW4CD

= –100mA

R

BB_OUT Pull-Down Resistance

Soft-Start Rate

Regulator Disabled

(Note 6)

OUT4

t

I

V/ms

μA

SS

FB

Feedback Pin Input Current

V

= 0.85V

–0.1

0.1

FB

3589p

4

LTC3589

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating junction

temperature range, otherwise speciﬁcations are at T_A= 25°C (Note 2). V_IN= PV_IN1= PV_IN2= PV_IN3= PV_IN4= V_{IN_LDO2}= V_{IN_LDO34}

= DV_DD= 3.8V. All regulators disabled unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

LDO Regulators

t

Soft-Start Time LDO2, LDO3, LDO4

100

μs

Ω

LDO_SS

R

Output Pull-Down Resistance LDO2, LDO3,

LDO4

LDO Disabled

2000

LDO_PD

Always-On Regulator (LDO1_STDBY)

l

V

LDO1 Feedback Voltage

LDO1 Line Regulation

0.76

25

0.8

0.2

0.84

V

LDO1_FB

LDO1

I

= 1mA, LDO1_STBY = 3.3V,

%/V

LDO1_STBY

IN

V

= 2.7V to 5.5V

LDO1 Load Regulation

I

= 0.1mA to 25mA,

0.2

%

LDO1

LDO1_STBY = 3.3V

l

I

Available Output Current

Short Circuit Output Current Limit

Dropout Voltage (Note 4)

LDO1_FB Input Current

mA

mV

μA

LDO1

65

100

280

0.1

LDO1_SC

V

I

= 25mA, LDO1_STBY = 3.3V

LDO1

180

DROP1

I

V

= 0.85V

LDO1_FB

–0.1

1.7

LDO1_FB

LDO Regulator 2 (LDO2)

l

V

Input Voltage Range

V

IN

V

IN_LDO2

l

I

V

Quiescent Current

Shutdown Current

EN_LDO2 = High, LDO2_FB = 0.85V

EN_LDO2 = Low

14

0

19

1

μA

VIN_LDO2

IN_LDO2

l

I

V

Quiescent Current

IN

EN_LDO2 = High

50

0.75

80

μA

V

VIN

V

LDO2 Maximum Feedback Voltage

LDO2 Feedback LSB Step Size

LDO2 Minimum Feedback Voltage

L2DTV1 = L2DTV2 = 11111

0.735

0.351

0.765

FB2(MAX)

FB2(LSB)

FB2(MIN)

12.5

mV

V

l

L2DTV1 = L2DTV2 = 00000

0.3625

0.373

V

= V = 2.7V to 5.5V,

IN

IN_LDO2

I

= 1mA

LDO2

LDO2 Line Regulation

=1mA, V

= 2.7V to 5.5V

0.1

%/V

%

INLDO2

LDO2 Load Regulation

= 1mA to 250mA

l

I

LDO2 Available Output Current

LDO2 Short-Circuit Current Limit

Dropout Voltage (Note 4)

250

300

mA

OUT2

SC2

420

600

V

I

= 200mA, V

= 2.5V

= 1.2V

130

330

180

500

mV

DROP2

LDO2

I

LDO2_FB Input Current

V

= 0.8V

LDO2_FB

–0.1

2.35

0.1

μA

LDO2_FB

LDO Regulator 3 (LDO3)

l

V

Input Range

V

IN

V

IN_LDO34

l

I

V

Quiescent Current

Shutdown Current

EN_LDO3 = High, LDO3_FB = 0.85V

Regulator Disabled

14

0

24

1

μA

VIN_LDO34

IN_LDO34

l

I

V

Quiescent Current

IN

50

80

μA

V

VIN

V

LDO3 Output Voltage

V

= V = 2.7V to 5V,

1.746

1.8

1.854

LDO3

IN_LDO34

IN

I

= 1mA

LDO3

LD03 Line Regulation

=1mA, V

= 2.7V to 5.5V

0.1

%/V

%

INLDO34

LDO3 Load Regulation

= 1mA to 250mA

l

I

LDO3 Available Output Current

LDO3 Short-Circuit Current Limit

LDO3 Dropout Voltage (Note 4)

250

300

mA

mV

LDO3

420

180

600

250

LDO3_SC

V

I

= 200mA, V

= 1.8V

LDO3

DROP3

LDO3

3589p

5

LTC3589

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating junction

temperature range, otherwise speciﬁcations are at T_A= 25°C (Note 2). V_IN= PV_IN1= PV_IN2= PV_IN3= PV_IN4= V_{IN_LDO2}= V_{IN_LDO34}

= DV_DD= 3.8V. All regulators disabled unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

LDO Regulator 4 (LDO4)

l

V

Input Range

2.35

V

IN

V

IN_LDO34

I

V

Quiescent Current

Shutdown Current

LDO4 Enabled, LDO4_FB = 0.85V

LDO4 Disabled

l

14

0

22

1

μA

VIN_LDO34

IN_LDO34

l

I

Enabled V Quiescent Current

50

80

μA

VIN

IN

l

V

LDO 4 Output Voltage

I

= 1mA, L2DTV2[6:5] = 00

LDO4

2.716

2.245

1.746

3.201

2.8

2.5

1.8

3.3

2.884

2.575

1.854

3.399

V

LDO4

L2DTV2[6:5] = 01

L2DTV2[6:5] = 10

L2DTV2[6:5] = 11

LD04 Line Regulation

I

=1mA, V

= 1.8V

= 2.7V to 5.5V,

INLDO4

0.1

%/V

LDO4

OUT

V

LDO4 Load Regulation

I

= 1mA to 250mA

0.1

%

mA

LDO4

l

I

LDO4 Available Output Current

LDO4 Short Circuit Current Limit

LDO4 Dropout Voltage (Note 4)

250

300

LDO4

420

600

LDO4_SC

V

I

= 200mA, V

= 3.3V

= 1.8V

100

180

130

250

mV

DROP4

LDO4

Enable Inputs

l

V

Threshold Rising, All Enables Low

0.8

1.2

V

ENx_THR

l

V

Threshold Rising, Any Enable High

Threshold Falling, Any Enable High

0.5

0.45

0.525

V

ENx_THR2

ENx_THF2

0.425

R

Input Pull-Down Resistance

4.5

MΩ

ENX

VSTB, PWR_ON Inputs

l

V

VSTB Pin Threshold Rising

VSTB Pin Threshold Falling

0.8

0.7

1.2

V

VSTB_THR

VSTB_THF

0.4

R

Pull-Down Resistence

4.5

MΩ

VSTB

l

V

PWR_ON Pin Threshold Rising

PWR_ON Pin Threshold Falling

0.8

0.7

V

PWR_ONTHR

PWR_ONTHF

R

Pull-Down Resistence

4.5

MΩ

PWR_ON

2

I C Port

DV

DV Input Supply Voltage

1.6

5.5

V

μA

V

DD

I

DV Quiescent Current

SCL/SDA = 0kHz

0.3

1

DVDD

DD

V

DV UVLO Level

DVDD_UVLO

DD

ADDRESS

LTC3589 Device Address – Write

LTC3589 Device Address – Read

01101000

01101001

V

SDA, SCL SDA and SCL Input Threshold Rising

SDA, SCL SDA and SCL Input Threshold Falling

70

–1

%DV

IH

IL

DD

30

1

I

SDA and SCL Input Current

SDA Output Low Voltage

SDA = SCL = 0V to 5.5V

= 3mA

μA

V

IHSCx ILSCx

V

SDA

I

0.4

400

OL

SCL

BUF

SDA

f

t

SCL Clock Operating Frequency

kHz

μs

Bus Free Time Between Stop and Start

Condition

1.3

t

Hold Time After (Repeated) Start Condition

Repeated Start Condition Setup Time

Stop Condition Setup Time

0.6

0

μs

ns

HD_STA

SU_STA

SU_STO

HD_DAT(O)

Data Hold Time Output

900

3589p

6

LTC3589

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating junction

temperature range, otherwise speciﬁcations are at T_A= 25°C (Note 2). V_IN= PV_IN1= PV_IN2= PV_IN3= PV_IN4= V_{IN_LDO2}= V_{IN_LDO34}

= DV_DD= 3.8V. All regulators disabled unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

0

TYP

MAX

UNITS

ns

t

Data Hold Time Input

Data Setup Time

HD_DAT(I)

100

ns

SU_DAT

SCL Clock Low Period

SCL Clock High Period

Clock/Data Fall Time

Clock/Data Rise Time

Input Spike Supression Pulse Width

1.3

μs

LOW

0.6

μs

HIGH

C = Capacitance of One BUS Line (pF)

B

20 + 0.1C

300

50

ns

f

B

C = Capacitance of One BUS Line (pF)

B

20 + 0.1C

ns

r

ns

SP

Pushbutton Interface

l

V

ON Threshold Rising

ON Threshold Falling

0.8

0.7

1.2

1

V

ON_TH

0.4

–1

I

ON Input Current

ON = V

μA

ON

IN

ON = 0V

40

50

0.2

400

5

t

ON Low Time to PBSTAT Low

ON High Time to PBSTAT High

ON Low Time to WAKE High

ON Low time to Hard Reset

ms

μs

ms

s

ON_PBSTAT1

ON_PBSTAT2

ON_WAKE

ON_HR

PBSTAT Minimum Pulse Width

PBSTAT Blanking from WAKE Low

Minimum WAKE Low Time

50

1

ms

s

PBSTAT_PW

PBSTAT_BK

WAKE_OFF

WAKE_ON

PWR_ON

1

s

WAKE High Time with PWR_ON = 0V

PWR_ON High to WAKE High

PWR_ON Low WAKE Low

5

s

50

ms

PWR_OFF

Status Output Pins (PBSTAT, WAKE, PGOOD, RSTO, IRQ)

V

PBSTAT Output Low Voltage

I

= 3mA

= 3.8V

0.1

0.4

0.1

0.4

0.1

0.4

0.1

V

μA

V

PBSTAT

I

PBSTAT Output High Leakage Current

WAKE Output Low Voltage

V

–0.1

PBSTAT

V

I

= 3mA

= 3.8V

WAKE

I

WAKE Output High Leakage Current

PGOOD Output Low Voltage

V

μA

V

WAKE

V

I

= 3mA

= 3.8V

PGOOD

I

PGOOD Output High Leakage Current

V

μA

PGOOD

V

PGOOD Threshold Rising

PGOOD Threshold Falling

–6

–8

%

PGOOD

NRSTO

UVLO

LDO1 Power Good Threshold Rising

LDO1 Power Good Threshold Falling

–6

–8

%

Undervoltage Lockout Rising

Undervoltage Lockout Falling

2.65

2.55

2.7

V

Undervoltage Warning Rising

Undervoltage Warning Falling

3

2.9

UVWARN

RSTO Output Low Voltage

I

= 3mA

RSTO

0.4

0.1

0.4

0.1

V

μA

V

RSTO

I

RSTO Output High Leakage Current

IRQ Output Low Voltage

V

= 3.8V

–0.1

RSTO

V

I

= 3mA

IRQ

I

IRQ Output High Leakage Current

V

= 3.8V

μA

IRQ

3589p

7

LTC3589

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed Under Absolute Maximum ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum rating condition for extended periods may affect device

reliability and lifetime.

Note that the maximum ambient temperature consistent with these

speciﬁcations is determined by speciﬁc operating conditions in

conjunction with board layout, the rated package thermal impedance and

other environmental factors.

Note 2: The LTC3589 is tested under pulsed load conditions such that T ≈ T .

The LTC3589E is guaranteed to meet speciﬁcations from 0°C to 85°C

Note 3: The LTC3589 includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the speciﬁed maximum operating temperature

may impair device reliability.

J

A

junction temperature. Speciﬁcations over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3589I is guaranteed

over the –40°C to 125°C operating junction temperature range and the

LTC3589H is guaranteed over the full –40°C to 150°C operating junction

temperature range. High junction temperatures degrade operating

lifetimes; operating lifetime is derated for junction temperatures greater

Note 4: Dropout voltage is deﬁned as (V – V ) for LDO1 or

IN

LDO

(V

IN_LDO

– V ) for other LDOs when V

is 3% lower than V

LDO

measured with V = V

= 4.3V.

IN

IN_LDO

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency.

Note 6: Soft-Start measured in test mode with regulator error ampliﬁer in

unity gain mode.

than 125°C. The junction temperature (T in °C) is calculated from the

J

ambient temperature (T in °C) and power dissipation (PD, in Watts)

A

according to the formula:

T = T + (PD • θ ), where the package junction to ambient thermal

J

A

JA

impedance θ = 34°C/W.

JA

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Step-Down Switching Regulator

I_DDvs V_IN

Standby I_VINvs V_IN

LDO2 to LDO4 I_DDI_VINvs V_IN

250

200

150

100

50

900

14

12

PULSE-SKIPPING MODE

ENABLE THREE BUCKS

ENABLE TWO BUCKS

ALL REGULATORS DISABLED

800

700

600

500

400

300

200

ENABLE THREE LDOs

ENABLE TWO LDOs

10

8

6

ENABLE ONE LDO

ENABLE ONE BUCK

4

2

100

0

3.0

3.5

4.5

5.0

5.5

3.0

3.5

4.5

5.0

5.5

3.0

3.5

4.5

5.0

5.5

2.5

4.0

2.5

4.0

2.5

4.0

VOLTAGE (V)

22554 G01

3589 G02

3589 G03

Step-Down Switching Regulator

I_DDvs V_IN

Input Supply Current vs

Temperature

Buck-Boost I_DDvs V_IN

120

100

80

60

40

20

0

1200

1000

800

600

400

200

0

450

400

350

300

250

200

150

100

50

Burst Mode OPERATION

ENABLE THREE BUCKS

ALL REGULATORS ENABLED

PULSE-SKIPPING MODE

FORCED

CONTINUOUS

ENABLE TWO BUCKS

ENABLE ONE BUCK

ALL REGULATORS ENABLED

Burst Mode OPERATION

STANDBY (ONLY LDO1 ON)

0

3.0

3.5

4.5

5.0

5.5

2.5

4.0

–25

0

75 100 125 150

25 50

TEMPERATURE (°C)

3.0

3.5

5.0

5.5

–50

2.5

4.0

4.5

VOLTAGE (V)

3589 G04

3589 G05

3589 G06

3589p

8

LTC3589

TYPICAL PERFORMANCE CHARACTERISTICS T_A= 25°C, unless otherwise noted.

Oscillator Frequency vs

Temperature

Switching Frequency Change vs V_IN

Buck-Boost Efﬁciency vs I_OUT

2.30

2.25

2.20

2.15

2.10

2.05

2.00

1.95

1.0

0.8

100

90

80

70

60

50

40

30

20

V

= 3.8V

IN

BURST

0.6

0.4

0.2

FORCED

CONTINUOUS

0

–0.2

–0.4

–0.6

–0.8

V

OUT

V

OUT

V

OUT

= 5.0V

= 2.5V

= 3.3V

10

0

–10

30

TEMPERATURE (°C)

110

150

–50

70

3.0

3.5

4.5

VOLTAGE (V)

5.0

5.5

2.5

4.0

0.01

0.1

1

10

100

1000

LOAD CURRENT (mA)

3589 G9

3589 G07

3589 G08

Step-Down Switching Regulator 1

Efﬁciency vs I_OUT

Step-Down Switching Regulator 2

Efﬁciency vs I_OUT

Buck-Boost Efﬁciency vs I_OUT

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

V

= 1.2V

V

= 1.8V

OUT

V

= 3.3V

OUT

BURST

FORCED

CONTINUOUS

FORCED

CONTINUOUS

FORCED

CONTINUOUS

V

= 5.0V

= 4.2V

= 3.0V

IN

PULSE-SKIPPING

10

0

10

0

10

0

0.01

0.1

1

10

100

1000

0.01

0.1

1

10

100

1000

0.01

0.1

1

10

100

1000

LOAD CURRENT (mA)

3589 G11

3589 G12

3589 G10

Step-Down Switching Regulator 3

Efﬁciency vs I_OUT

Step-Down Switching Regulator

R_DS(ON)vs Temperature

Buck-Boost R_DS(ON)vs Temperature

100

90

80

70

60

50

40

30

20

0.40

0.35

0.30

0.25

0.20

0.25

V

= 1.2V

OUT

0.20

0.15

0.10

BURST

PMOS

BUCK2 PMOS

BUCK1 PMOS

PULSE-

SKIPPING

FORCED

NMOS

CONTINUOUS

BUCK2 NMOS

0.15

0.10

BUCK1 NMOS

0.05

0

0.05

0

10

0

0.01

0.1

1

10

100

1000

–10

30

TEMPERATURE (°C)

110

150

–10

30

TEMPERATURE (°C)

110

150

–50

70

–50

70

LOAD CURRENT (mA)

3589 G13

3589 G14

3589 G15

3589p

9

LTC3589

TYPICAL PERFORMANCE CHARACTERISTICS T_A= 25°C, unless otherwise noted.

Step-Down Switching

Regulator Current Limit vs

Temperature

Step-Down Switching Regulator

Soft-Start

Buck-Boost Current Limit vs

Temperature

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

BUCK1

V

OUT

PEAK LIMIT

CLAMP LIMIT

500mV/DIV

200mA/DIV

BUCK2, BUCK3

I

L

3589 G18

200μs/DIV

–25

0

25 50

TEMPERATURE (°C)

125 150

–25

0

25 50

125 150

75 100

–50

75 100

–50

TEMPERATURE (°C)

3589 G16

3589 G17

Buck-Boost Switching Regulator

Soft-Start

Step-Down Switching Regulator 1

Load Step

Dynamic Voltage Slew

V

OUT

V

50mV/DIV

1A/DIV

OUT

1V/DIV

PGOOD

I

LOAD

500mA/DIV

V

STB

I

L

3589 G20

3589 G21

3589 G19

200μs/DIV

= 1.75mV/μs

40μs/DIV

100μs/DIV

V

PULSE-SKIPPING MODE

RRCR

Step-Down Switching Regulator 1

Load Step

Buck-Boost Switching Regulator 1

Load Step

Maximum Buck-Boost Load

Current vs V_IN

2.5

2.0

1.5

1.0

0.5

0

V

= 3.0V

IN

V

OUT

200mV/DIV

50mV/DIV

1A/DIV

I

LOAD

I

LOAD

1A/DIV

V

= 1.5V

= 3.3V

= 5V

OUT

3589 G23

3589 G22

40μs/DIV

Burst Mode OPERATION

3.0

3.5

4.5

5.0

5.5

2.5

4.0

VOLTAGE (V)

3589 G24

3589p

10

LTC3589

TYPICAL PERFORMANCE CHARACTERISTICS T_A= 25°C, unless otherwise noted.

LDO1 Dropout Voltage vs

Temperature

LDO1 Short-Circuit Current vs

Temperature

LDO1 Output Change vs V_IN

80

70

60

50

500

0.5

V

= 25mA

LDO1

V

= 1.8V

LDO1

400

300

200

100

0

0.0

–0.5

–1.0

–1.5

–2.0

V

= 3.3V

LDO1

40

30

20

V

= 1.2V

= 1.8V

= 2.8V

= 3.3V

LDO1

–25

0

25 50

125 150

75 100

–50

–25

0

25 50

TEMPERATURE (°C)

125 150

3

4

5

–50

75 100

2

TEMPERATURE (°C)

V

(V)

IN

3589 G27

3589 G25

3589 G26

LDO2, LDO3, LDO4 Dropout

Voltage vs Temperature

LDO2, LDO3, LDO4 Dropout

Voltage vs Load Current

LDO2, LDO3, LDO4 Short-Circuit

Current vs Temperature

500

400

300

200

100

0

500

400

300

200

100

0

500

450

400

350

V

= 1.2V

LDO

V

= 1.2V

LDO

V

LDO

= 1.8V

V

LDO

= 1.8V

300

250

200

V

= 3.3V

LDO

V

= 3.3V

LDO

–25

0

25 50

125 150

75 100

–50

50

100

LOAD CURRENT (mA)

250

0

150

200

–25

0

25 50

125 150

75 100

–50

TEMPERATURE (°C)

3589 G28

3589 G29

3589 G30

LDO2, LDO3, LDO4 Enable

Response

LDO2, LDO3, LDO4 Load Step

Response

LDO1 Load Step Response

V

LDO4

=2.8V

V

LDO3

=1.8V

1.8V

1.2V

V

LDO1

50mV/DIV

LDO

50mV/DIV

1V/DIV

V

=1.2V

LDO2

220mA

20mA

I

LDO

10mA/DIV

LDO

V

,V

EN_LDO2 EN_LDO34

100μs/DIV

100mA/DIV

10mA

1mA

3589 G31

3589 G32

3589 G33

100μs/DIV

40μs/DIV

LOAD CAPACITANCE = 1μF

3589p

11

LTC3589

PIN FUNCTIONS

IN_LDO2

be bypassed to ground with a 1μF or greater ceramic

capacitor.

V

(Pin 1): Power Input for LDO2. This pin should

SW4AB (Pin 12): Switch Pin for Buck-Boost Switching

Regulator 4. Connected to the buck-boost internal power

switches A and B. Connect an inductor between this pin

and SW4CD (Pin 19).

LDO2 (Pin 2): Output Voltage of LDO2. Nominal output

voltage is set with a resistor feedback divider that servos

EN3 (Pin 13): Enable Step-Down Switching Regulator 3.

Active high input to enable step down switching

regulator 3. A weak pull-down forces EN3 low when left

ﬂoating.

2

to an I C register controlled DAC reference. This pin must

be bypassed to ground with a 1μF or greater ceramic

capacitor.

LDO3 (Pin 3): Output Voltage of LDO3. Nominal output

voltage is ﬁxed at 1.8V. This pin must be bypassed to

ground with a 1μF or greater ceramic capacitor.

EN4 (Pin 14): Enable Buck-Boost Switching Regulator 4.

Active high input to enable buck-boost switching

regulator 4. A weak pull-down forces EN4 low when left

ﬂoating.

LDO4 (Pin 4): Output Voltage of LDO4. Output voltages

2

of 1.8V, 2.5V, 2.8V, and 3.3V are selected via the I C port.

PV (Pin 15): Power Input for Switching Regulator 4.

IN4

This pin must be bypassed to ground with a 1μF or greater

ceramic capacitor.

This pin should be bypassed to ground with a 4.7μF or

greater ceramic capacitor.

V

(Pin 5): Power Input for LDO3 and LDO4. This

BB_OUT(Pin16):OutputVoltageofBuck-BoostSwitching

Regulator 4. This pin must be bypassed to ground with a

22μF or greater ceramic capacitor.

IN_LDO34

pin should be bypassed to ground with a 1μF or greater

ceramic capacitor.

PV

(Pin 6): Power Input for Step-Down Switching

IRQ (Pin 17): Interrupt Request Output. Open drain driver

is pulled low for power good, undervoltage, and over

temperature warning and fault conditions. Clear IRQ by

IN1

Regulator 1. This pin should be bypassed to ground with

a 4.7μF or greater ceramic capacitor.

2

writing to the I C CLIRQ command register.

SW1 (Pin 7): Switch Pin for Step-Down Switching

Regulator 1. Connect one side of step-down switching

regulator 1 inductor to this pin.

EN_LDO34 (Pin 18): Enable LDO3 and LDO4 Logic Input.

Active high to enable LDO3 and LDO4. Disable LDO4 via

2

I C software commands using I C command registers

OVEN or L2DTV2. A weak pull-down forces EN_LDO34

low when left ﬂoating.

RSTO (Pin 8): Reset Output. Open drain output pulls low

when the always on regulator LDO1 is below regulation

and during a hard reset initiated by a pushbutton input.

SW4CD (Pin 19): Switch Pin for Buck-Boost Switching

Regulator 4. Connected to the buck-boost internal power

switches C and D. Connect an inductor between this node

and SW4AB (Pin 12).

EN_LDO2 (Pin 9): Enable LDO2 Logic Input. Active high

input to enable LDO2. A weak pull-down forces EN_LDO2

low when left ﬂoating.

EN1 (Pin 10): Enable Step-Down Switching Regulator 1.

Active high input to enable step-down switching

regulator 1. A weak pull-down forces EN1 low when left

ﬂoating.

PWR_ON (Pin 20): External Power-On. Handshaking pin

toacknowledgesuccessfulpower-onsequence. PWR_ON

must be driven high within ﬁve seconds of WAKE going

high to keep power on. It can be used to activate the WAKE

output by driving high. Drive low to shut down WAKE.

EN2 (Pin 11): Enable Step-Down Switching Regulator 2.

Active high input to enable step-down switching

regulator 2. A weak pull-down forces EN2 low when left

ﬂoating.

ON (Pin 21): Pushbutton Input. A weak internal pull-up

forces ON high when left ﬂoating. A normally open push-

button is connected from ON to ground to force a low

state on this pin.

3589p

12

LTC3589

PIN FUNCTIONS

2

PBSTAT (Pin 22): Pushbutton Status. Open drain output

to be used for processor interrupts. PBSTAT mirrors the

status of ON pushbutton pin. PBSTAT is delayed 50ms

from ON pin for debounce.

DV (Pin 32): Supply Voltage for I C Serial Port. This

DD

2

pin sets the logic reference level of SCL and SDA I C pins.

2

DV resetsI Cregisterstopoweronstatewhendrivento

DD

<1V. SCLandSDAlogiclevelsarescaledtoDV . Connect

DD

a 0.1μF decoupling capacitor from this pin to ground.

WAKE(Pin23):SystemWakeUp.Opendraindriveroutput

releases high when signaled by pushbutton activation or

PWR_ON input. It may be used to initiate a pin-strapped

power-up sequence by connecting to a regulator enable

pin to initiate a pin strapped power-on sequence.

BUCK2_FB (Pin 33): Feedback Input for Step-Down

Switching Regulator 2. Set full scale output voltage using

resistor divider connected from the output of step-down

switching regulator 2 to this pin to ground.

PVIN2 (Pin 24): Power Input for Step-Down Switching

Regulator 2. This pin should be bypassed to ground with

a 4.7μF or greater ceramic capacitor.

BUCK3_FB (Pin 34): Feedback Input for Step-Down

Switching Regulator 3. Set full scale output voltage using

resistor divider connected from the output of step-down

switching regulator 3 to this pin to ground.

SW2(Pin25):SwitchPinforStep-DownSwitchingRegula-

tor 2. Connect one side of step-down switching regulator

2 inductor to this pin.

LDO1_FB (Pin 35): Feedback Input for LDO1. Set out-

put voltage using a resistor divider connected from

LDO1_STDBY to this pin to ground.

SW3(Pin26):SwitchPinforStep-DownSwitchingRegula-

tor 3. Connect one side of step-down switching regulator

3 inductor to this pin.

LDO1_STDBY (Pin 36): Always On LDO1 Output. This pin

providesanalwaysonsupplyvoltageusefulforlightloads

such as a watchdog microprocessor or a real time clock.

Connect a 1μF capacitor from LDO1_STBY to ground.

PVIN3 (Pin 27): Power Input for Switching Regulator 3.

Tie this pin to the V supply. This pin should be bypassed

IN

to ground with a 4.7μF or greater ceramic capacitor.

V

(Pin 37): Supply Voltage Input. This pin should

IN

be bypassed to ground with a 1μF or greater ceramic

capacitor.

VSTB (Pin 28): Voltage Standby. When VSTB is low, DAC

reference voltages are selected by bit values in command

register VCCR. When VSTB is high, the DAC voltages are

forced to the bit values found in the V2 registers. Tie VSTB

to ground if unused.

LDO2_FB (Pin 38): Feedback Input for LDO2. Set full

scale output voltage using a resistor divider connected

from LDO2_OUT to this pin to ground.

PGOOD (Pin 29): Power Good Output. Open drain output

pulls down when any regulator falls below power good

threshold and during regulator dynamic voltage slew. Un-

BUCK1_FB (Pin 39): Feedback Input for Step-Down

Switching Regulator 1. Set full scale output voltage using

resistor divider connected from the output of step-down

switching regulator 1 to this pin to ground.

2

lessdisabledinI Cregister.Pullsdownwhenallregulators

are disabled.

BB_FB(Pin40):FeedbackInputforBuck-BoostSwitching

Regulator 4. Set the output voltage using resistor divider

connected from BB_OUT to this pin to ground.

2

SCL (Pin 30): Clock Input Pin for the I C Serial Port. The

2

I C logic levels are scaled with respect to DV .

DD

2

SDA (Pin 31): Data Input Pin for the I C Serial Port. The

GND (Exposed Pad Pin 41): Ground. The Exposed Pad

must be connected to a continuous ground plane on the

second layer of the printed circuit board by several inter-

connect vias directly under the LTC3589 for maximum

heat transfer.

2

I C logic levels are scaled with respect to DV .

DD

3589p

13

LTC3589

BLOCK DIAGRAM

V

IN

PV

IN4

I/O AT 1.2A

BB_OUT

V

REF

BUCK-BOOST

VRTC AT 25mA

LDO1_STDBY

SW4AB

SW4CD

V

REF

OK

LDO1_FB

ALWAYS ON LDO1

EN

OK

BB_FB

IRQ

PV

IN1

ON (PB)

PBSTAT

WAKE

BUCK 1

CONTROL + SEQUENCE

V

CORE

AT 1.6A

EN

OK

SW1

PWR_ON

VSTB

V

REF

DAC

BUCK1_FB

EN1

EN-PINS

PV

EN2

IN2

2

EN-I C

EN3

BUCK 2

EN4

V

SRAM

AT 1A

EN_LDO2

EN_LDO34

EN

OK

SW2

V

REF

DAC

n

BUCK2_FB

DV

DD

PV

IN3

SDA

SCL

2

I C

BUCK 3

PGOOD

V

SOC

AT 1A

EN

OK

SW3

V

REF

DAC

RSTO

7

BUCK3_FB

POWER

GOOD

V

IN_LDO2

LDO2

LDO3

V

REF

V

MEM

AT 250mA

LDO2

EN

OK

LDO2_FB

V

IN_LDO34

LDO4

V

REF

EN

OK

EN

OK

0V, 1.8V,

2.5V, 2.8V, 3.3V

AT 250mA

LDO4

LDO3

V

1.8V

ANALOG

AT 250mA

3589 BD

GND (EXPOSED PAD)

3589p

14

LTC3589

OPERATION

INTRODUCTION

2

or forced continuous, are set using the I C interface. In

pulse-skipping mode the regulator will support 100%

duty cycle. For best efﬁciency at low output loads select

BurstModeoperation.Forcedcontinuousmodeminimizes

output voltage ripple at light loads.

The LTC3589 is a complete power management solution

for portable microprocessors and peripheral devices. It

generates a total of eight voltage rails for supplying power

totheprocessorcore,SDRAM,systemmemory,PCcards,

always-on real time clock and HDD functions. Supplying

the voltage rails are an always-on low quiescent current

25mA LDO, one 1.6A and two 1A step-down regulators, a

1.2A buck-boost regulator, and three 250mA low dropout

regulators. Supporting the multiple regulators is a highly

conﬁgurable power-on sequencing capability, dynamic

voltage slewing DAC output voltage control, a pushbutton

The 4-switch buck-boost DC/DC voltage mode converter

generates a user-programmable output voltage rail from

2.5V to 5V. Utilizing a proprietary switching algorithm,

the buck-boost converter maintains high efﬁciency and

low noise operation with input voltages that are above,

below or equal to the required output rail. The buck-boost

error ampliﬁer uses a ﬁxed 0.8V reference and the output

voltage is set by an external resistor divider. Burst Mode

2

interface controller, regulator control via an I C interface,

2

and extensive status and interrupt outputs.

operation is enabled through the I C control registers. No

external compensation components are required for the

buck-boost converter.

The LTC3589 operates over an input supply range of 2.7V

to 5.5V. The input supplies for the 250mA LDO regulators

may operate as low as 1.7V to limit power loss at low

output voltages.

The reference inputs for the three step-down regulators

and LDO2 are 5-bit D to A converters with up-down ramp-

ing at selectable slew rates. The slew endpoint voltages

The always-on LDO1 provides a resistor programmable

output voltage as low as 0.8V and is capable of supplying

25mA. With only the always-on LDO active the LTC3589

drawsjust10μA(typical). AlwaysonLDO1willcontinueto

2

and select bits are stored in I C registers for each DAC.

2

A select bit in the I C command registers chooses which

register to use for each target voltage. Variable reference

slew rates from 0.88mV/μs to 7mV/μs are selectable in

operate with V levels as low as 2.0V (typical) to maintain

IN

2

the I C register. Each of the four DACs has independent

memory and RTC function as long as possible.

voltage, voltage select, and slew rate control registers.

Eachofthe250mALDOregulatorshasuniqueoutputvolt-

age conﬁgurations. LDO3 has a ﬁxed 1.8V output. LDO4

TheLTC3589isequippedwithapushbuttoncontrolcircuit

that will activate the WAKE output, indicate pushbutton

status via the PBSTAT pin, and initiate a hard reset shut-

down of the regulators. Grounding the ON pin with the

pushbutton for 400ms will force the WAKE pin to release

HIGH. The WAKE pin output can be tied to the enable pin

of the ﬁrst regulator in a power-on sequence. Once in the

power-on state, subsequent pushes of the button longer

than 50ms are mirrored by the PBSTAT output. Holding

ON LOW for ﬁve seconds disables all the regulators, pulls

down the WAKE pin, and pulls down RSTO for one second

to indicate to the processor that a hard reset occurred. All

regulator enables and pushbutton inputs are inhibited for

one second following the hard reset.

2

has four output levels selectable via the I C interface.

Its possible outputs are 1.8V, 2.5V, 2.8V, and 3.3V. LDO2

has a dynamically slewing DAC set point reference and

an external feedback pin to set the output voltage range

with a resistive divider. Each LDO draws 60μA (typical)

quiescent current.

The LTC3589 includes three internally compensated

constant frequency current mode step-down switching

regulators providing 1A, 1A, and 1.6A. Step-down regula-

tor switching frequencies of 2.25MHz or 1.125MHz are

independently selected for each step-down regulator

2

using the I C command registers. The power-on default

frequency is 2.25MHz. Each of the step-down regulators

havedynamicallyslewingDACinputreferencesandexternal

feedback pins to set output voltage range. The step-down

regulators three operating modes, pulse-skipping, burst,

TheLTC3589hasﬂexibleoptionsforenablingandsequenc-

ing the regulator enables. The regulators are enabled us-

2

ing input pins or the I C serial port. To deﬁne a power-on

3589p

15

LTC3589

OPERATION

sequencetietheenableoftheﬁrstregulatortobepowered

up to the WAKE pin. Connect the ﬁrst regulators output

to the enable pin of the second regulator, and so on. One

or more regulators may be started in any sequence. Each

enable pin has a 200μs (typical) delay between the pin and

the internal enable of the regulator. When the system con-

trollers are satisﬁed that power rails are up, the controller

mustdrivePWR_ONHIGHtokeepWAKEactive.Shutdown

sequencing is monitored by output voltage comparators

whichrequireeachoutputtodischargebelow300mVbefore

re-enabling.Asoftwarecontrolcommandregisterfunction

is available which sets the regulators to effectively ignore

other keep-alive circuits. The LDO is guaranteed to sup-

port a 25mA load. A 1μF low impedance ceramic bypass

capacitor from LDO1_STBY to GND is required for com-

pensation. A power good monitor pulls RSTO LOW for a

minimum of 14ms (typical) whenever LDO1_STBY is 8%

below its regulation target. An LDO1_STBY undervoltage

condition is reported in the PGOOD status register. The

output voltage of LDO1 is set with a resistor divider con-

nected from LDO1_STBY to the feedback pin LDO1_FB

as shown in Figure 1.

ꢀ

ꢃ

R1

V_{LDO_STBY}=0.8 • 1+

(V)

ꢅ

ꢂ

2

their enable pins but respond to I C register enables. This

R2

ꢁ

ꢄ

functionenablessoftware-onlycontrolofanycombination

of pin-strapped regulators and is useful for implementing

system power saving modes. Keep-alive mode exempts

selected regulators from turning off during normal shut-

down. In keep-alive mode, the LTC3589 powers down

normally and is ready for the next start-up sequence, but

selected regulators are kept on to power memory or other

function during system standby modes.

Typical values for R1 are in the range of 40k to 1M.

V

IN

+

–

0.8V

LDO1_STBY

1μF

R1

R2

LDO1_FB

The LTC3589 will shut down all regulators and pull down

3589 F01

the WAKE pin under high temperature, V under voltage,

IN

and extended low regulator output voltage conditions.

Status of a hard shutdown is reported by the IRQ status

pin and the IRQSTAT status register.

Figure 1. Always-On LDO Application Circuit

2

The I C serial port on the LTC3589 contains 13 command

LDO1_STBY is protected from short circuits and over

loading.

registers for controlling each of the regulators, one read

only register for monitoring each regulators power good

status, one read only register for reading the cause of

an IRQ event, and one clear IRQ command register. The

LTC3589 I C supports random addressing of any register

and registers may be written in any order using multiple

START sequences.

250MA LDO REGULATORS

2

Three LDO regulators on the LTC3589 will each deliver up

to 250mA output. The LDO regulators are enabled by pin

2

inputorI Ccommandregister.PinEN_LDO2enablesLDO2

and pin EN_LDO34 enables LDO3 and LDO4 together. An

2

I C command register bit is available to decouple LDO4

ALWAYS-ON LDO

from pin EN_LDO34 so that LDO4 is under command

register control only. All the regulators have current limit

protectioncircuits. Whendisabled, a2kinternalpull-down

resistor is connected to the regulators output. Depend-

TheLTC3589includesalowquiescentcurrentlowdropout

regulator that remains powered whenever a valid supply

is present on V . The always-on LDO will remain active

IN

until V drops below 2.0V (typical). This is below the

IN

2

ing on settings in I C system control register 2 (SCR2),

2.5V undervoltage threshold in effect for the rest of the

LTC3589 circuits. The always-on LDO is used to provide

power to a standby microcontroller, real time clock, or

a regulator’s output must discharge to less than 300mV

before it will respond to its enable. The output discharge

3589p

16

LTC3589

OPERATION

feature is to guarantee proper startup sequencing. This

feature and the 2k pull-down resistors may be overridden

by bit settings in command register SCR2.

2

Table 1. Shows the I C command register settings used

to control LDO2.

Table 1. LDO 2 Command Register Settings

To help reduce LDO power loss in the system, the regula-

tors have dedicated supply inputs that may be lower than

COMMAND

VALUE SETTING

REGISTER[BIT]

OVEN[4]

SCR2[4]

VCCR[5]

0*

1

Disable

Enable

the main V supply. Connect a low ESR 1μF capacitor to

IN

each of the output pins LDO2, LDO3, and LDO4.

0*

1

Wait for Output Below 300mV Before Enable

Enable Immediately

LDO Regulator 2

0*

1

Select Register L2DTV1 (V1) Reference

Select Register L2DTV2 (V2) Reference

One of the LTC3589 dynamic slewing DACs serves as the

reference input of LDO2. The output range of LDO2 is set

using an external resistor divider connected from LDO2 to

the feedback pin LDO2_FB as shown in Figure 2. Set the

output voltage of LDO2 using the following formula:

VCCR[6]

1

Initiate Dynamic Voltage Slew

VRRCR[7-6]

00* Reference Slew Rate = 0.88mV/μs

01

10

11

Reference Slew Rate = 1.75mV/μs

Reference Slew Rate = 3.5mV/μs

Reference Slew Rate = 7mV/μs

L2DTV1[4-0]

L2DTV1[5]

11001* DAC Dynamic Target Voltage V1

ꢀ

ꢃ

R1

R2

0*

1

Force PGOOD Low When Slewing

Normal PGOOD Operation When Slewing

V_OUT= 1+

•(0.3625+L2DTVx • 0.0125)

ꢅ

ꢂ

ꢁ

ꢄ

L2DTV1[7]

0*

1

Shutdown LDO2 Normally

Keep LDO2 Alive

L2DTVxistheﬁvebitwordcontainedintheLDO2dynamic

target voltage 1 (L2DTV1) or the LDO2 dynamic target

voltage 2 (L2DTV2) command registers. The default value

of L2DTVx[4-0] is 11001 to output a reference voltage

of 0.675V. LDO2 is enabled by writing bit 4 in the output

voltage enable (OVEN) command register to 1 or driving

theLDO2_ENpinhigh.Wheneverthecommandisgivento

slew LDO2 DAC reference to a lower voltage an integrated

2k pull down resistor is connected to LDO2 output.

L2DTV2[4-0]

11001* DAC Dynamic Target Voltage V2

* Denotes Default Power-On Value

LDO Regulator 3

LDO3 is a ﬁxed 1.8V output regulator. LDO3 is enabled

by driving pin EN_LDO34 high or by writing command

register OVEN[5] to 1.

2

Table 2 shows the I C command register settings used

to control LDO3.

PV

IN

EA

Table 2. LDO 3 Command Register Settings

LDO2

FB

COMMAND

REGISTER[BIT]

VALUE SETTING

0.3625V

TO 0.75V

1μF

R1

R2

OVEN[5]

SCR2[5]

0*

1

Disable

Enable

0*

1

Wait for Output Below 300mV Before Enable

Enable Immediately

5

DAC

* Denotes Default Power-On Value

3589 F02

Figure 2. LDO2 Application Circuit

3589p

17

LTC3589

OPERATION

LDO Regulator 4

PV

IN

EN

LDO4 has four output voltage options that are controlled

by the contents of command register L2DTV2 bits 6

and 5. By default, pin EN_LDO34 enables and disables

LDO3 and LDO4 simultaneously when command register

bits OVEN[6] and OVEN[7] are LOW. When EN_LDO34 is

LOW, LDO3 and LDO4 are controlled by writing to com-

mand register bits OVEN[6] and OVEN[7] respectively.

WhencommandregisterbitL2DTV2[7]isHIGH,controlof

LDO4 is disconnected from pin EN_LDO34 and controlled

by command register bit OVEN[7] regardless of the status

PWM

L1

CONTROL

SW

FB

MODE

C

OUT

R1

R2

C

FB

0.3625V

TO 0.75V

5

DAC

3589 F03

2

of EN_LDO34. Table 3 shows the I C command register

Figure 3. Step-Down Switching Regulator

Application Circuit

settings used to control LDO4.

Table 3. LDO 4 Command Register Settings

COMMAND

VALUE SETTING

of 0.675V. Typical values for R1 are in the range of 40k

REGISTER[BIT]

to 1M. The capacitor C cancels the pole created by the

FB

OVEN[6]

0*

1

Disable

Enable

feedback resistors and the input capacitance on the FB pin

and also helps to improve load step transient response.

A value of 10pF is recommended for most applications.

Experimentation with capacitor sizes between 10pF and

33pF may yield improved transient response.

SCR2[6]

0*

1

Wait for Output Below 300mV Before Enable

Enable Immediately

L2DTV2[6-5]

00*

01

V

LDO4

V

LDO4

V

LDO4

V

LDO4

= 2.8V

= 2.5V

= 1.8V

= 3.3V

10

11

Operating Modes

L2DTV2[7]

0

1

LDO4 Enable Controlled by EN_LDO34

LDO4 Enable Controlled by OVEN[6]

Thestep-downswitchingregulatorsincludethreepossible

operating modes to meet the noise and power needs of a

variety of applications.

* Denotes Default Power-On Value

STEP-DOWN SWITCHING REGULATORS

Output Voltage Programming

In pulse-skipping mode, at the start of every cycle, a latch

is set that turns on the main P-channel MOSFET switch.

During the cycle, a current comparator compares the

peak inductor current to the output of an error ampliﬁer.

The output of the current comparator resets the latch.

At this time the P-channel MOSFET switch turns off and

the N-channel MOSFET synchronous rectiﬁer turns on.

The N-channel MOSFET synchronous rectiﬁer will turn

off when the end of the clock cycle is reached or if the

inductor current drops through zero. Using this method

of operation, the error ampliﬁer adjusts the peak inductor

current to deliver the required output power. All necessary

loop compensation is internal to the step-down switching

regulator requiring only a single ceramic output capacitor

for stability. At light loads in pulse-skipping mode, the

inductor current may reach zero on each pulse that will

Each of the step-down converters uses a dynamically

slewing DAC output for its reference. The full-scale output

voltage is set by using a resistor divider connected from

the step-down switching regulator output to the feedback

pins (B1_FB, B2_FB, and B3_FB) as shown in Figure 3.

Set the output voltage of step-down switching regulators

using the following formula:

ꢀ

ꢃ

R1

R2

V_OUT= 1+

•(0.3625+BxDTVx • 0.0125)(V)

ꢅ

ꢂ

ꢁ

ꢄ

BxDTVx is the decimal value of the ﬁve bit binary number

2

intheI CBxDTV1orBxDTV2commandregisters.BxDTV1

andBxDTV2defaultto11001tooutputareferencevoltage

3589p

18

LTC3589

OPERATION

turn off the N-channel MOSFET synchronous rectiﬁer. In

thiscasethe switch node (SW1, SW2, or SW3)goes HIGH

impedance and the switch node will ring. This is discon-

tinuous operation and is normal behavior for a switching

regulator. At very light loads in pulse-skipping mode, the

step down switching regulators will automatically skip

pulses as needed to maintain output regulation. At high

Set the mode of operation for the step-down switching

2

regulators by using the I C command register SCR1. Each

of the three regulators has independent mode control.

Astep-downswitchingregulatormayenteradropoutcondi-

tion when its input voltage drops to near its programmed

outputvoltage. Forexample, adischargingbatteryvoltage

of 3.4V dropping to the regulators programmed output

voltage of 3.3V. When this happens the duty cycle of the

P-channel MOSFET switch is increased until it turns on

continuously with 100% duty cycle. In dropout, the regu-

lators output voltage equals the regulators input voltage

minus the voltage drops across the internal P-channel

MOSFET and the inductor DC resistance.

duty cycle (V

> V /2) it is possible for the inductor

OUTX

IN

current to reverse at light loads causing the stepped down

switchingregulatortooperatecontinuously.Whenoperat-

ing continuously, regulation and low noise output voltage

are maintained, but input operating current will increase

to a few milliamps.

In the forced continuous mode of operation, the inductor

current is allowed to be less than zero over the full range

of duty cycles. Operating in forced continuous mode is

a lower noise option at light loads than pulse-skipping

Register Controls

2

Table 4, Table 5, and Table 6 show the I C command

register settings used to control the step-down switching

regulators.

operation but with the drawback of higher V current

IN

due to the continuous operation of the MOSFET switch

and rectiﬁer. Since the inductor current is allowed to be

negative in forced continuous operation the step-down

switching regulator has the ability to sink output current.

TheLTC3589automaticallyforcesthestep-downswitching

regulator into forced continuous mode when dynamically

slewing the DAC voltage reference down.

Table 4. Step-Down Switching Regulator 1 Command Register

Settings

COMMAND

REGISTER[BIT]

VALUE SETTING

SCR1[1-0]

00*

01

10

Pulse-Skipping Mode

Burst Mode Operation

Forced Continuous Mode

OVEN[0]

SCR2[0]

VCCR[1]

0*

1

Disable

Enable

When the LTC3589 step-down switching regulators are in

Burst Mode operation, they automatically switch between

ﬁxed frequency pulse-skipping operation and hysteretic

Burst Mode control as a function of the load current. At

light loads the step-down switching regulators control

the inductor current directly and use a hysteretic control

loop to minimize both noise and switching losses. While

operating in Burst Mode operation, the output capacitor

is charged to a voltage slightly higher than the regulation

point. The step-down switching regulator then goes into

a low power sleep mode during which the output capaci-

tor provides the load current. In sleep mode most of the

switching regulator’s circuitry is powered off to conserve

battery power. When the output voltage drops below the

regulationpointtheregulator’scircuitryispoweredonand

another burst cycle begins. As the load current increases,

the time between burst cycles decreases. Above a load

current about ¼ rated output load, the step-down switch-

ing regulators will switch to low noise constant frequency

PWM operation.

0*

1

Wait for Output Below 300mV Before Enable

Enable Immediately

0*

1

Select Register B1DTV1 (V1) Reference

Select Register B1DTV2 (V2) Reference

VCCR[0]

1

Initiate Dynamic Voltage Slew

VRRCR[1-0]

00*

01

10

11

Reference Slew Rate = 0.88mV/μs

Reference Slew Rate = 1.75mV/μs

Reference Slew Rate = 3.5mV/μs

Reference Slew Rate = 7mV/μs

B1DTV1[5]

0*

1

Force PGOOD Low When Slewing

Normal PGOOD Operation When Slewing

B1DTV1[4-0]

B1DTV2[4-0]

B1DTV2[5]

11001* DAC Dynamic Target Voltage V1

11001* DAC Dynamic Target Voltage V2

0

1

2.25MHz Switching Frequency

1.125MHz Switching Frequency

B1DTV2[6]

B1DTV2[7]

0*

1

Switch on Clock Phase 1

Switch on Clock Phase 2

0*

1

Shutdown Regulator 1 Normally

Keep Regulator 1 Alive

* Denotes Default Power-On Value

3589p

19

LTC3589

OPERATION

Soft-Start

Switching EMI Control

Soft-start is accomplished by gradually increasing the

input reference voltage on each step-down switching

regulator from 0V to the dynamic reference DAC output

level at a rate of 2mV/μs. This allows each output to rise

slowly,helpingminimizeinrushcurrentrequiredtocharge

up the regulator output capacitor. A soft-start cycle oc-

curs whenever a regulator is enabled either initially or

while powering up following a fault condition. A soft-start

cycle is not triggered by a change of operating modes or

a dynamic voltage slew. During soft-start the converter is

forced to pulse-skipping mode regardless of the settings

in the SCR1 command register.

The step-down switching regulators contain new patent

pending circuitry to limit the edge rate of the switch nodes

SW1,SW2,andSW3.Thisnewcircuitrycontrolsthetransi-

tionoftheswitchnodeoveraperiodofafewnanoseconds,

signiﬁcantly reducing radiated EMI and conducted supply

noise while maintaining high efﬁciency. Since slowing

the slew rate of the switch nodes causes efﬁciency loss,

the slew rate of the step-down switching regulators is

2

adjustable using the I C command register B1DTV1 bits

6 and 7. Optimize efﬁciency or EMI as necessary with four

different slew rate settings. The power-on default is the

fastest slew rate, highest efﬁciency setting.

Table 5. Step-Down Switching Regulator 2 Command Register

Settings

Table 6. Step-Down Switching Regulator 3 Command Register

Settings

COMMAND

REGISTER[BIT]

VALUE SETTING

COMMAND

REGISTER[BIT]

VALUE SETTING

SCR1[3-2]

00*

01

10

Pulse-Skipping Mode

SCR1[5-4]

00*

01

10

Pulse-Skipping Mode

Burst Mode Operation

Forced Continuous Mode

OVEN[1]

SCR2[1]

VCCR[3]

0*

1

Disable

Enable

OVEN[2]

SCR2[2]

VCCR[5]

0*

1

Disable

Enable

0*

1

Wait for Output Below 300mV Before Enable

Enable immediately

0*

1

Wait for Output Below 300mV Before Enable

Enable Immediately

0*

1

Select Register B2DTV1 (V1) Reference

Select Register B2DTV2 (V2) Reference

0*

1

Select Register B3DTV1 (V1) Reference

Select Register B3DTV2 (V2) Reference

VCCR[2]

1

Initiate Dynamic Voltage Slew

VCCR[4]

1

Initiate Dynamic Voltage Slew

VRRCR[3-2]

00*

01

Reference Slew Rate = 0.88mV/μs

Reference Slew Rate = 1.75mV/μs

Reference Slew Rate = 3.5mV/μs

Reference Slew Rate = 7mV/μs

VRRCR[5-4]

00*

01

Reference Slew Rate = 0.88mV/μs

Reference Slew Rate = 1.75mV/μs

Reference Slew Rate = 3.5mV/μs

Reference Slew Rate = 7mV/μs

10

11

B2DTV1[5]

0*

1

Force PGOOD Low When Slewing

Normal PGOOD Operation When Slewing

B3DTV1[5]

0*

1

Force PGOOD Low When Slewing

Normal PGOOD Operation When Slewing

B2DTV1[4-0]

B2DTV2[4-0]

B2DTV2[5]

11001* DAC Dynamic Target Voltage V1

11001* DAC Dynamic Target Voltage V2

B3DTV1[4-0]

B3DTV2[4-0]

B3DTV3[5]

11001* DAC Dynamic Target Voltage V1

11001* DAC Dynamic Target Voltage V2

0

1

2.25MHz Switching Frequency

1.125MHz Switching Frequency

0

1

2.25MHz Switching Frequency

1.125MHz Switching Frequency

B2DTV2[6]

B2DTV2[7]

0*

1

Switch on Clock Phase 1

Switch on Clock Phase 2

B3DTV2[6]

B3DTV2[7]

0*

1

Switch on Clock Phase 1

Switch on Clock Phase 2

0*

1

Shutdown Regulator 2 Normally

Keep Regulator 2 Alive

0*

1

Shutdown Regulator 3 Normally

Keep Regulator 3 Alive

* Denotes Default Power-On Value

3589p

20

LTC3589

OPERATION

Operating Frequency

Inductor Selection

The switching frequency of each of the LTC3589 step-

downswitchingregulatorsmaybeindependentlysetusing

Thechoiceofstep-downswitchingregulatorinductorinﬂu-

ences the efﬁciency of the converter and the magnitude of

theoutputvoltageripple. Largerinductancevaluesreduce

inductor current ripple and therefore lower output voltage

ripple. A larger value inductor improves efﬁciency by low-

ering the peak current to be closer to the average output

current. Larger inductors, however, generally have higher

series resistance that counters the efﬁciency advantage

of reduced peak current.

2

I C command register bits B1DTV2[5], B2DTV2[5] and

B3DTV2[5]. The power-on default frequency is 2.25MHz.

Writing bit BxDTV2[5] HIGH will reduce the switching fre-

quencyto1.125MHz. Selectionoftheoperatingfrequency

is determined by desired efﬁciency, component size and

converter duty cycle.

Operation at lower frequency improves efﬁciency by

reducing internal gate charge and switching losses but

requires larger inductance and capacitance values for

comparable output ripple voltage. The lowest duty cycle

of the step-down switching regulator is determined by

the converters minimum on-time. Minimum on-time is

the shortest time duration that the converter is capable of

turning its top PMOS on and off again. The time consists

of the gate charge time plus internal delays associated

with peak current sensing. The minimum on-time of the

LTC3589 is approximately 90ns. If the duty cycle falls

below what can be accommodated by the minimum on-

time, the converter will begin to skip cycles. The output

voltage will continue to be regulated but the ripple voltage

and current will increase. With the switching frequency

set to 2.25MHz, the minimum supported duty cycle is

20%. Switching at 1.125MHz the converter can support

a 10% duty cycle.

Inductorripplecurrentisafunctionofswitchingfrequency,

inductance, V , and V

as shown in this equation:

IN

OUT

ꢁ

ꢄ

V

1

f •L

ꢀI_L=

• V

1–

_OUTꢃ

^OUTꢆ

V_IN

ꢅ

ꢂ

InanexampleapplicationtheLTC3589step-downswitching

regulator 3 has a maximum load of 1A, V equals 3.8V,

IN

and V

is set for 1.2V. A good starting design point for

OUT

inductor ripple is 30% of output current or 300mA. Using

the equation for ripple current, a 1.2μH inductor should

be selected.

An inductor with low DC resistance will improve converter

efﬁciency.SelectaninductorwithaDCcurrentratingatleast

1.5 times larger than the maximum load current to ensure

the inductor does not saturate during normal operations.

If short circuit is a possible condition, the inductor should

be rated to handle the maximum peak current speciﬁed

for the step-down converter. Table 7 shows inductors that

work well with the step-down switching regulators.

Phase Selection

To reduce the cycle by cycle peak current drawn by the

switching regulators, the clock phase of each of the

LTC3589 step-down switching regulators can be set using

Input/Output Capacitor Selection

2

I C command register bits B1DTV2[6], B2DTV2[6] and

LowESR(equivalentseriesresistance)ceramiccapacitors

should be used at both the output and input supply of the

switchingregulators. OnlyX5RorX7Rceramiccapacitors

should be used because they retain their capacitance over

wider voltage and temperature ranges than other ceramic

types. A 22μF capacitor is sufﬁcient for the step-down

B3DTV2[6]. The internal full rate clock has a nominal duty

cycle of 20% while the half rate clocks have a 50% duty

cycle. Setting the command register bits high will delay

the start of each converter switching cycle by 20% or 50%

depending on the selected operating frequency.

3589p

21

LTC3589

OPERATION

switching regulator outputs. For good transient response

and stability the output capacitor should retain at least

10μF of capacitance over operating temperature and bias

voltage. Place at least 4.7μF decoupling capacitance as

PV

A

BB_OUT

IN4

D

SW4AB

SW4CD

B

C

close as possible to each PV pin. Refer to Table 11 for

IN

recommended ceramic capacitor manufacturers.

BUCK-BOOST SWITCHING REGULATOR

Output Voltage Programming

EN

MODE

PWM

CONTROL

Set the output voltage of the LTC3589 buck-boost switch-

ing regulator using an external resistor divider connected

from BB_OUT to the feedback pin BB_FB and to GND as

shown in Figure 4.

R1

R2

22μF

BB_FB

–

+

0.8V

3589 F04

ꢀ

ꢃ

R1

R2

V_{BB_OUT}= 0.8 • 1+

(V)

ꢅ

ꢂ

Figure 4. Buck-Boost Switching Regulator Application Circuit

ꢁ

ꢄ

Table 7. Inductors for Step-Down Switching Regulator 1

VALUE

MAX DC

CURRENT (A)

MANUFACTURERS

PART NUMBER

(μH)

DCR (Ω)

SIZE (mm) W × L × H

Coilcraft

XPL4020-102ML

XPL4020-152ML

XPL4020-222ML

LPS6225-222ML

LPS6225-332ML

LPS6225-472ML

1.0

1.5

2.2

3.3

4.7

0.029

0.036

0.060

0.045

0.055

0.065

4.00

3.60

2.60

3.90

3.50

3.00

4.2 × 4.2 × 2.0

6.0 × 6.0 × 2.0

Cooper

SD14-1R2-R

SD14-1R5-R

SD14-2R0-R

SD25-2R2-R

1.2

1.5

2.0

2.2

0.034

0.039

0.045

0.031

3.35

2.91

2.56

2.80

5.2 × 5.2 × 1.45

5.2 × 5.2 × 2.5

Sumida

TDK

CDRH5D16NP-3R3N

3.3

0.045

2.60

5.6 × 5.6 × 1.8

VLF5014ST-1R0N2R7

VLF5014st-2R2N2R3

VLCF5020T-2R2N2R6-1

1.0

2.2

0.050

0.073

0.071

2.7

2.3

2.6

4.8 × 4.6 × 1.4

5.0 × 5.0 × 2.0

TOKO

Tokin

1124BS-1R2N

1124BS-1R8N

1.2

1.8

0.047

0.056

2.9

2.7

4.5 × 4.7 × 1.8

H-DI-0520-2R2

H-DI-0630-2R4

H-DI-0630-3R8

2.2

2.4

3.8

0.048

0.028

0.040

2.6

2.5

2

5.3 × 5.3 × 2.0

6.3 × 6.3 × 3.0

Wurth

744042001

744052002

744053003

7440530047

7440430022

1.0

2.5

3.0

4.7

2.2

0.028

0.030

0.024

0.030

0.023

2.60

2.4

2.8

2.4

2.5

4.8 × 4.8 × 1.8

5.8 × 5.8 × 1.8

5.8 × 5.8 × 2.8

4.8 × 4.8 × 2.8

3589p

22

LTC3589

OPERATION

Table 8. Inductors for Step-Down Switching Regulators 2 and 3

VALUE

(μH)

MAX DC

CURRENT (A)

MANUFACTURERS

PART NUMBER

DCR (Ω)

SIZE (mm) W × L × H

Coilcraft

XPL4020-102ML

XPL4020-152ML

XPL4020-472ML

1.0

1.5

4.7

0.029

0.036

0.130

4.00

3.60

1.90

4.2 × 4.2 × 2.0

Cooper

SD14-1R2-R

SD14-3R2-R

SD25-3R3-R

1.2

3.2

3.3

0.034

0.066

0.038

3.35

2.00

2.21

5.2 × 5.2 × 1.45

4.8 × 4.8 × 2.5

Sumida

TDK

CDRH5D16NP-4R7N

4.7

3.3

0.064

0.059

2.05

1.46

5.6 × 5.6 × 1.8

4.2 × 4.2 × 1.8

CDRH38D16RHPNP-3R3M

VLF5014ST-2R2N2R3

VLCF5020T-2R7N2R2-1

VLCF5020T-3R3N2R0-1

2.2

2.7

3.3

0.073

0.083

0.096

2.3

2.2

2

4.8 × 4.6 × 1.4

5.0 × 5.0 × 2.0

TOKO

Tokin

1124BS-2R4N

1124BS-3R3N

2.4

3.3

0.065

0.074

2.30

2.10

4.5 × 4.7 × 1.8

H-DI-0520-3R3

H-DI-0520-4R7

H-DI-0630-3R8

H-DI-0630-4R7

3.3

4.7

3.8

4.7

0.062

0.090

0.040

0.043

2.00

1.80

2.00

1.90

5.3 × 5.3 × 2.0

6.3 × 6.3 × 3.0

Wurth

744043004

744052002

7440530047

744042003

7440430022

4.7

2.5

4.7

3.3

2.2

0.052

0.030

0.055

0.023

1.55

2.4

5.0 × 5.0 × 3.0

5.8 × 5.8 × 1.8

5.8 × 5.8 × 2.8

4.8 × 4.8 × 1.8

4.8 × 4.8 × 2.8

2.4

1.95

2.5

The value of R1 plays a role in setting the dynamics of

the buck-boost voltage mode control loop. In general, a

larger value for R1 will increase stability but reduce the

speed of the transient response. A good starting point is

to choose R1 equal to 1MΩ and calculate the value of R2

needed to set the target output voltage. If a large output

capacitorisused,thebandwidthoftheconverterisreduced

and R1 may be reduced to improve transient response. If

a large inductor or small output capacitor is used then a

larger R1 should be used to bring the loop toward more

stable operation.

the converter to transition between buck, buck-boost, and

boost modes without discontinuity in inductor current or

loop characteristics. The switch topology is shown in the

application circuit in Figure 4.

Table 9. Buck-Boost Command Register Settings

COMMAND

REGISTER[BIT]

VALUE SETTING

SCR1[6]

OVEN[3]

SCR2[3]

0*

1

Continuous Mode

Burst Mode Operation

0*

1

Disable

Enable

0*

1

Wait for Output Below 300mV Before Enable

Enable Immediately

Modes of Operations

* Denotes Default Power-On Value

2

Table 9 shows the I C command registers used to control

When the input voltage is signiﬁcantly greater than the

output voltage, the buck-boost converter operates in

buck mode. Switch D turns on continuously and switch C

remains off. Switches A and B are pulse width modulated

to produce the required duty cycle to support the output

theoperatingmodesoftheLTC3589buck-boostconverter.

When command register SCR1 bit 6 is LOW, the LTC3589

buck-boost switching regulator operates in a ﬁxed fre-

quency pulse width modulation mode using voltage mode

feedbackcontrol.Aproprietaryswitchingalgorithmallows

3589p

23

LTC3589

OPERATION

regulationvoltage.Astheinputvoltagedecreases,switchA

remains on for a larger portion of the switching cycle.

When the duty cycle reaches approximately 85%, the

switch pair AC begins turning on for a small fraction of the

switching period. As the input voltage decreases further,

the AC switch pair remains on for longer durations and

the duration of the BD phase decreases proportionately.

As the input voltage drops below the output voltage, the

AC phase will eventually increase to the point that there is

no longer any BD phase. At this point, switch A remains

on continuously while switches CD operate as a boost

converter to regulate the desired output voltage.

current into the feedback node whenever the inductor

current exceeds 2.5A (typical). Forcing the current into

the feedback node in the high gain feedback circuit has

the effect of lowering the output voltage until the aver-

age current in switch A is equal to the current limit. The

average limit uses the error ampliﬁer in its active linear

state so once the fault condition is removed the recovery

is smooth with little overshoot.

A hard short on the output of the buck-boost will cause the

inductor current to exceed the 2.5A average current limit.

A second current limit turns off switch A in the event peak

inductor current reaches 3A (typical). The instantaneous

forwardcurrentlimitprovidesextraprotectionintheevent

of a sudden hard short.

The buck-boost is set to Burst Mode operation by writing

a 1 to command register SCR1 bit 6. Using Burst Mode

operation at light loads improves efﬁciency and reduces

standby current at zero loads. In Burst Mode operation,

the inductor is charged with bursts of ﬁxed peak amplitude

current pulses. The current pulses are repeated as often

as necessary to maintain the target output voltage. The

maximumoutputcurrentthatcanbesuppliedinBurstMode

operation is dependent upon the input and output voltage.

The reverse current comparator on the D switch monitors

the current entering the BB_OUT pin. When this current

exceeds 500mA (typical) switch D will turn off for the

remainder of the switching cycle. This feature protects

the buck-boost converter from excessive reverse current

if the buck-boost output is held above the regulation point

by an external source.

Typically I

in Burst Mode operation is equal to:

OUT(MAX)

Soft-Start

0.15 • V

^IN(A)

_OUT+ V_IN

I_OUT(MAX)

=

The buck-boost converter has an internal voltage mode

soft-start circuit that ramps the buck-boosts error amp

reference from 0V to 800mV at a rate of 2mV/μs. During

soft-start, the converter is regulating to the ramping ref-

erence and will respond to output load transients during

soft-start. During soft-start the buck-boost converter is

forced into continuous mode operation regardless of the

state of the SCR1 command register.

V

If the buck-boost load exceeds the maximum Burst Mode

current capability then the output rail will lose regula-

tion and the power good comparator will indicate a fault

condition.

When the LTC3589 buck-boost is not enabled, a 2k

pull down resistor is connected between BB_OUT and

ground.

Inductor Selection

Inductorselectioncriteriaforthebuck-boostaresimilarto

those given for the step-down switching regulators. The

buck-boost converter is designed to work with inductors

in the range of 1μH to 3.3μH. For most applications use a

1.5μHinductor.ChooseaninductorwithaDCcurrentrating

Current Limit Operation

TheLTC3589buck-boostregulatorhascurrentlimitcircuits

to limit forward current through the A switch and reverse

current through the D switch. The primary forward cur-

rent limit circuit injects a small fraction of the inductor

3589p

24

LTC3589

OPERATION

Table 10. Inductors for Buck-Boost Switching Regulator

PART

NUMBER

VALUE

(μH)

MAX DC

CURRENT (A)

MANUFACTURERS

DCR (Ω)

SIZE (mm) W × L × H

Coilcraft

XPL4020-152ML

XPL4020-222ML

XPL4020-332ML

LPS6225-332ML

LPS6225-472ML

1.5

2.2

3.3

4.7

0.036

0.060

0.085

0.055

0.065

3.60

2.60

2.40

3.50

3.00

4.2 × 4.2 × 2.0

6.0 × 6.0 × 2.0

Cooper

SD14-1R5-R

SD14-2R0-R

SD14-2R5-R

SD14-3R2-R

SD25-3R3-R

1.5

2.0

2.5

3.2

3.3

0.039

0.045

0.060

0.066

0.038

2.91

2.56

2.29

2.00

2.21

5.2 × 5.2 × 1.45

4.8 × 4.8 × 2.5

Sumida

TDK

CDRH5D16NP-3R3N

CDRH5D16NP-4R7N

3.3

4.7

0.045

0.064

2.60

2.05

5.6 × 5.6 × 1.8

VLF5014ST-2R2N2R3

VLCF5020T-2R7N2R2-1

VLCF5020T-3R3N2R0-1

2.2

2.7

3.3

0.073

0.083

0.096

2.3

2.2

2

4.8 × 4.6 × 1.4

5.0 × 5.0 × 2.0

TOKO

Tokin

Wurth

1124BS-1R8N

1124BS-3R3N

1.8

3.3

0.056

0.074

2.70

2.10

4.5 × 4.7 × 1.8

H-DI-0520-3R3

H-DI-0630-3R8

3.3

3.8

0.062

0.040

2.00

5.3 × 5.3 × 2.0

6.3 × 6.3 × 3.0

744052002

7440420027

744053003

7440530047

2.5

2.7

3.0

4.7

0.030

0.047

0.024

0.030

2.4

2.2

2.8

2.4

5.8 × 5.8 × 1.8

4.8 × 4.8 × 1.8

5.8 × 5.8 × 2.8

A 22μF capacitor is sufﬁcient for the buck-boost switch-

ing regulator output. For good transient response and

stability the output capacitor should retain at least 10μF of

capacitance over operating temperature and bias voltage.

Place at least 4.7μF decoupling capacitance as close as

at least two times larger than the maximum load current to

ensure that the inductor does not saturate during normal

operation. If output short circuit is a possible condition,

the inductor should be rated to handle the maximum peak

current speciﬁed for the buck-boost converter. Table 9

shows several inductors that work well with the LTC3589

buck-boost regulator.

possible to PV pin. Refer to Table 11 for recommended

IN4

ceramic capacitor manufacturers.

Table 11. Ceramic Capacitor Manufacturers

Capacitor Selection

AVX

www.avxcorp.com

www.murata.com

www.t-yuden.com

www.vishay.com

www.tdk.com

Low ESR ceramic capacitors should be used at both the

output and input supply of the buck-boost switching

regulator. Only X5R or X7R ceramic capacitors should

be used because they retain their capacitance over wider

voltage and temperature ranges than other ceramic types.

Murata

Taiyo Yuden

Vishay Siliconix

TDK

3589p

25

LTC3589

OPERATION

SLEWING DAC REFERENCE OPERATION

Setting and Slewing the DAC Outputs

The 5-bit word in dynamic target voltage command reg-

isters B1DTV1, B2DTV1, B3DTV1, and L2DTV1 programs

reference voltage V1. The 5-bit word in command regis-

ters B1DTV2, B2DTV2, B3DTV2, and L2DTV2 programs

reference voltage V2. A resistor divider network on the

output and feedback pins of the regulators set their output

voltage.

Controlling the DAC References

The three LTC3589 step-down switching regulators and

linear regulator LDO2 have programmable DAC reference

inputs.EachDACisprogrammablefrom0.3625Vto0.75V

in 12.5mV steps:

ꢀ

ꢃ

R1

R2

V_OUT= 1+

•(0.3625+BxDTVx • 0.0125)(V)

ꢅ

A 0 or 1 to the odd bits of voltage change control register

VCCRselectsDACoutputvoltagesV1orV2respectively.A

slew of the DAC is initiated by writing a 1 to an even bit of

register VCCR. The DAC output will slew to either voltage,

V1 or V2, as selected by the even bits of register VCCR.

ꢂ

ꢁ

ꢄ

The DAC references may be commanded to independently

slew between two voltages at one of four selectable slew

rates. Table 12 summarizes the command registers used

to control slewing DAC operation.

2

Slew begins when the I C STOP condition is detected. At

the end of the slewing operation the GO bits in command

register VCCR are cleared.

Table 12. Slewing DAC Command Register Control Summary

COMMAND

FUNCTION

The slew rate for each regulator is set in the ramp rate

controlregisterVRRCR.EachDAChasindependentoutput

voltageregisters,voltageregisterselect,andslewrateand

start controls. The regulators do not have to be enabled

to change the DAC outputs.

REGISTER[BIT]

VCCR[0], VCCR[2],

VCCR[4], VCCR[6]

Voltage Change Control Register

G0 / Slew

Write a 1 to Initiate a Slew to the Voltage

Selected in VCCR[1], VCCR[3], VCCR[5],

VCCR[7] Respectively.

TheVSTBpinisusedtosettheDACcontrolledoutputrails

to a low power standby condition. When VSTB is driven

HIGH, all four of the DAC references will immediately slew

to V2. To use VSTB to set the rails to standby voltage,

select V1 for normal rail voltages and V2 for standby rail

voltages. Drive VSTB high to immediately slew all the

DAC outputs to V2. When VSTB is driven LOW, the DAC

outputs will slew to V1.

Bits are Reset to 0 at the End of the Slew

Operation.

VCCR[1], VCCR[3],

VCCR[5], VCCR[7]

Voltage Change Control Register

Dynamic Target Select

Write a 0 to Select Voltage V1 Stored in

Registers B1DTV1[4-0], B2DTV1[4-0],

B3DTV1[4-0], L2DTV1[4-0].

Write a 1 to Select Voltage V2 in

Registers B1DTV2[4-0], B2DTV2[4-0],

B3DTV2[4-0], L2DTV2[4-0].

B1DTV1[4-0], B2DTV1[4-0], Dynamic Target Voltage 1

B3DTV1[4-0], L2DTV1[4-0]

Thedefaultpowerupvalueofallthedynamictargetvoltage

registers is 11001 corresponding to a DAC output volt-

age of 0.675V. The DTV registers may be reprogrammed

prior to initiating a power-up sequence or at any time for

dynamic slewing.

Five Bits Corresponding to V1 Output

from Each DAC.

PGOOD Mask

B1DTV1[5], B2DTV1[5],

B3DTV1[5], L2DTV1[5]

Write a 1 to Continue Normal PGOOD

Operation When Slewing.

Write a 0 to Force PGOOD to Pull Low

During Slew.

When a step-down switching regulator output is slew-

ing down its mode is automatically switched to forced

continuous to enable the regulator to sink current. When

LDO2 is slewing down, a 2k pull down is connected to

its output.

B1DTV2[4-0], B2DTV2[4-0], Dynamic Target Voltage 2

B3DTV2[4-0], L2DTV2[4-0]

Five Bits Corresponding to V2 Output

from Each DAC.

VRRCR[1-0], VRRCR[3-2], Voltage Ramp Rate Control

VRRCR[5-4], VRRCR[7-6]

Two Bits That Set the DAC Output Slew

Rate for Step-Down Switching Regulator

and LDO2.

3589p

26

LTC3589

OPERATION

Table 13 shows command register and feedback divider

settingstoenableslewingstep-downswitchingregulator1

between 1.2V and 1V in 70μs. The voltage ramp rate

control register bits VRRCR[1:0] are set to 10 which

selects a ramp rate of 1.75mV/μs at the DAC output.

The slew rate at the regulator output is a function of the

feedback resistor divider gain. In this example, the slew

is equal to 1.75 • (1 + 301/499) = 2.8mV/μs. Therefore, a

slew of 200mV will take 70μs. To initiate a change from

1.2V to 1V write 11 to voltage change control register bits

VCCR[1:0]. VCCR[1] selects target register B1DTV2 to

set the regulator reference input to 0.625V. VCCR[0] set

to 1 initiates the dynamic slew to go to the new voltage.

To slew back to 1.2V write 01 to command register bits

VCCR[1:0].

isactivatedbythePWR_ONpin.Whenthecontrollerenters

the PUP state the open drain WAKE pin releases HIGH.

The WAKE pin is typically used to enable the ﬁrst regulator

in a start-up sequence. The pushbutton state will stay in

PUP for ﬁve seconds before transitioning to the power-on

(PON) state. Before leaving PUP, the PWR_ON pin must be

broughtHIGHbytheapplicationtoindicatethatthesystem

rails are correct. If PWR_ON is not active at the end of ﬁve

seconds the pushbutton controller will continue directly

through PON to the power-down (PDN) state and pull the

WAKE pin down. Three events will cause the pushbutton

to leave the PON state: 1) lowering the PWR_ON pin, 2)

forcing a hard reset by holding the ON pin LOW for ﬁve

seconds, and 3) a fault condition is detected. Fault condi-

tions are low V , device over temperature, or extended

IN

undervoltage of one of the regulator outputs. All regulator

enables, the ON input, and PWR_ON signals are inhibited

for one second while in the PDN state. After one second

in PDN the pushbutton controller returns to POFF.

Table 13. Dynamic Slewing Example for Step-Down Switching

Regulator 1

COMMAND

REGISTER

V

=1.2V

V

=1V

OUT

VRRCR[1:0]

VCCR[1]

Dynamic Slew Rate

Select DTV

01

0

01

1

B1DTV1[4:0]

B1DTV2[4:0]

11111

10101

11111

10101

Resistor Divider Shown

in Figure 3

PUP

PB400ms OR

PWR_ON

R1 = 301kΩ

5 SEC

R2 = 499kΩ

POFF

PON

PUSHBUTTON OPERATION

State Event Diagram

FAULT OR

PWR_ON

1 SEC

POR

PDN

3589 F05

Figure 5 shows the LTC3589 pushbutton state diagram.

Upon ﬁrst power application to V an internal power-on

Figure 5. Pushbutton Controller State Diagram

IN

reset circuit puts the pushbutton into power-down (PDN)

state and initiates a one second timer. Status pin RSTO is

pulled LOW until one second is timed out and the always-

alive LDO1 has indicated power good status. After the one

secondintervalthepushbuttoncircuitwilltransitiontothe

power-off (POFF) state. The pushbutton will not leave the

POFF state and enter the power-up state (PUP) until ON is

held LOW for at least 400ms (PB400ms) or until PWR_ON

PBSTAT Operation

PBSTAT goes LOW 50ms after the initial pushbutton ap-

plication (ON LOW) and will stay LOW for a minimum of

50ms. PBSTAT will go HIGH coincident with ON going

HIGH unless ON goes HIGH before the 50ms minimum

on-time.

3589p

27

LTC3589

OPERATION

Power-Up Using the Pushbutton

ON(PB)

PBSTAT

WAKE

When in the POFF state, the LTC3589 is in complete

shutdown except the always active LDO1 and regulators

enabled with the keep-alive control bits. Pull the ON pin to

ground with a pushbutton for 400ms to begin a power-up

sequence with the WAKE pin tied to an enable pin. Drive

PWR_ON high within ﬁve seconds to signal the LTC3589

to remain in the power-on state.

50ms

5 SEC

50ms

μC/μP CONTROL

PWR_ON

3589 F08

Figure 8. Power-Up and Down Using PWR_ON Pin

ON(PB)

Hard Reset Using the Pushbutton

PBSTAT

When the ON pin is pulled LOW for ﬁve seconds, a hard

400ms

WAKE

reset is initiated. At the end of ﬁve seconds, WAKE is

<5 SEC

2

pulled LOW, the I C command registers are reset to POR

μC/μP CONTROL

PWR_ON

3589 F06

states, enable pin states are ignored, and the one second

power-downtimerisstarted.Duringthepower-downtime,

the enables continue to be ignored to allow the regulator

outputs to discharge. The RSTO pin is pulled LOW for

the power-down time to indicate a pushbutton hard reset

occurred. If the PWR_ON pin is LOW at the end of the one

secondpower-downtime,theLTC3589willremaininsleep

mode. If PWR_ON is HIGH at the end of one second and

there are no fault conditions, the LTC3589 will power-up

in the same way shown in Figure 8.

Figure 6. Power-Up Using the Pushbutton

Power-Down Using the Pushbutton

The pushbutton power-down operation is performed by

thesystemmicroprocessorbymonitoringthePBSTATpin.

OnceinthePONstate,thesystemcontrollerisresponsible

for deciding what action to take with a pushbutton event.

WhentheONpinisheldLOWfora50msdebounceperiod,

thePBSTATpinispulledLOW.Thesystemcontrollershould

monitor the PBSTAT pin to determine the pushbutton has

been pushed. If the controller decides that a power down

is desired, then it should drive the PWR_ON pin LOW.

ON(PB)

50ms

PBSTAT

WAKE

5 SEC

<5 SEC

ON(PB)

μC/μP CONTROL

PWR_ON

50ms

PBSTAT

1 SEC

RSTO

WAKE

PWR_ON

3589 F09

50ms

Figure 9. Hard Reset Using the Pushbutton

μC/μP CONTROL

3589 F07

Figure 7. Power Down Using Pushbutton

Hard Reset Due to a Fault Condition

Power-Up and Down Using PWR_ON Pin

AhardresetduetoV undervoltage,extendedundervoltage

IN

An alternate power-up method is to drive the PWR_ON pin

to a HIGH state. After a delay of 50ms from the PWR_ON

signal, the WAKE pin will pull HIGH to drive regulator en-

able pins. When PWR_ON is HIGH for ﬁve seconds, the

sequence controller will enter the PON state. To power

down, drive the PWR_ON pin LOW. WAKE will pull down

50ms later.

of an output rail, or an over temperature condition initiates

a hard shutdown of the LTC3589. When the fault occurs,

2

wake is pulled LOW, the I C command registers are reset

to POR states, enable pin inputs are ignored, and the one

second power down timer is started. During the power-

down time, the enables continue to be ignored to allow the

3589p

28

LTC3589

OPERATION

regulator outputs to discharge. If the PWR_ON pin is LOW

attheendofthepower-downtime,theLTC3589willremain

in sleep mode with just the always-active LDO operating.

If PWR_ON is HIGH at the end of one second and the fault

condition has cleared, the LTC3589 will power-up in the

same way shown in Figure 8. Neither IRQ nor the status

registers are cleared by the fault induced shutdown.

brings up the WAKE pin that is tied to EN1 and EN3 to

enablestep-downswitchingregulators1and3.Theoutput

of regulator 1 is tied to EN2 and EN4 that enables step-

down switching regulator 2 and the buck-boost switching

regulator4.Theoutputofstep-downswitchingregulator2

is tied to EN_LDO2 and EN_LDO3 to enable LDO2, LDO3

and LDO4. Within ﬁve seconds of WAKE going HIGH, the

microprocessor or microcontroller must drive PWR_ON

HIGH to tell LTC3589 that rails are good and to stay in the

power-on state.

FAULT

ON(PB)

PBSTAT

Figure 12 shows the start-up timing for the application

shown in Figure 11. There is a 200μs (typical) delay

between the enable pin and the internal enable signal to

each regulator.

<1 SEC

WAKE

μC/μP CONTROL

PWR_ON

IRQ

WAKE

V1

CLIRQ

1.2V

1V

200μs

0.5V

3589 F10

Figure 10. Hard Reset Due to a Fault Condition

ENABLE AND POWER-ON SEQUENCING

Enable Input Pin Operation

V3

1.8V

200μs

0.5V

3.3V

V2

V4

1.2V

1.8V

200μs

LDO2

LDO3

LDO4

The regulator enable input pins facilitate pin-strapping an

output rail to the enable pin of the next regulator in the

desired sequence. The regulator enable inputs normally

havea0.8V(typical)inputthreshold.Ifanyenableisdriven

HIGH, the remaining enable input thresholds switch to a

more accurate 500mV (typical) threshold.

2.8V

3589 F12

Figure 12. Pin Strap Sequencing Timing

Keep-Alive Operation

Figure 11 shows an application circuit for a typical pin-

strapped start-up sequence. Holding ON LOW for 400ms

For systems which require an active supply rail when in

system standby, any of the three LTC3589 step-down

switching regulators or LDO2 may be kept alive regard-

less of the status of PWR_ON and WAKE. Writing a 1 to

a regulator’s keep-alive bit in its dynamic target voltage

register will keep a regulator alive when the LTC3589 is

in standby mode. A regulator with its keep-alive bit set

will stay enabled until the bit is reset writing the bit LOW,

resetting the LTC3589 with a push button hard reset, or

a fault condition (UVLO, PGOOD time out, or thermal

shutdown) occurs. PGOOD and fault status are reported

in the IRQSTAT and PGSTAT registers and on the IRQ and

PGOOD pins for keep-alive regulators when PWR_ON and

WAKE are LOW.

LTC3589

EN1

WAKE

SW1

EN2

1V TO 1.2V

1.8V

EN3

SW2

EN4

SW3

0.8V TO 1V

3.3V

EN_LDO2

EN_LDO34

ON

BB_OUT

LDO2

LDO3

LDO4

1.2V

1.8V

PWR_ON

2.8V

3589 F11

Figure 11. Pin Strap Start-Up Sequence Application Circuit

3589p

29

LTC3589

OPERATION

Software Control Mode

2.7V

V

IN

>25μs

14ms

Once a power-up sequence is completed each regulator

may be enabled and disabled individually by the system

as needed for power mode requirements. Setting the out-

put voltage enable command register bit OVEN[7] HIGH

disconnects each regulator from its enable pin so control

is solely through the OVEN command register. To enter

software control mode, set command bit OVEN[7] HIGH

and the desired enable bits in OVEN[6:0] HIGH. Any of the

regulators enabled in OVEN[6:0] will stay on regardless

of the state of their enable pins when OVEN[7] is HIGH.

Setting the regulator enable bits and the software control

LDO1

1 SEC

INITIAL POWER-UP

RSTO

LDO1 UNDERVOLTAGE

3589 F13

Figure 13. Initial Power-Up and LDO1 Undervoltage RSTO Timing

PGOOD Pin and PGSTAT Status Register Function

Each LTC3589 regulator has an internal power good out-

put that is active whenever the regulators feedback pin is

closer than –8% (typical) from its input reference voltage.

If any of the internal power good signals indicate a low

voltage for longer than 25μs (typical), the PGOOD pin is

pulled LOW and the appropriate bit in the PGSTAT status

register (Table 14) is set.

2

bit in OVEN[7] may occur on the same I C start-stop

sequence. A normal shutdown using PWR_ON, OVEN

register to 0x00 to ensure all regulators are shut off.

FAULT DETECTION, SHUTDOWN, AND REPORTING

Table 14. PGSTAT Read Only Register Bit Deﬁnitions

PGSTAT[BIT] VALUE SETTING

TheLTC3589monitorsV ,outputrailvoltagesandinternal

IN

die temperature. A warning condition is indicated when

LDO1_STBY Output Low

LDO1_STBY Output Good

0

1

2

3

4

5

6

7

0

1

V

is less than 2.9V and when internal die temperature

IN

approaches the thermal shutdown temperature. A fault

Step-Down Switching Regulator 1 Output Low

Step-Down Switching Regulator 1 Output Good

0

1

condition occurs when V is less than 2.6V, any regulator

IN

output is 8% low for 14ms, or the internal die temperature

is HIGH. Warning and fault states are reported via the IRQ,

PGOOD,andRTSOpins.Speciﬁcfaultstatesarereadviathe

Step-Down Switching Regulator 2 Output Low

Step-Down Switching Regulator 2 Output Good

0

1

Step-Down Switching Regulator 3 Output Low

Step-Down Switching Regulator 3 Output Good

0

1

2

I C serial port status registers IRQSTAT and PGSTAT.

Buck-Boost Regulator 4 Output Low

Buck-Boost Regulator 4 Output Good

0

1

RSTO Pin Function

LDO2 Output Low

LDO2 Output Good

0

1

The RSTO (reset output) pin is an open drain output for

use as a power-on reset signal. It is pulled LOW at initial

power until LDO1 is within 8% of its target and the initial

onesecondstart-uptimerisﬁnished.RSTOremainsHIGH

during normal operation and will be pulled low if LDO1

loses regulation for more than 25μs or a pushbutton hard

reset is initiated.

LDO3 Output Low

LDO3 Output Good

0

1

LDO4 Output Low

LDO4 Output Good

0

1

Figure 13 shows a initial power up for the RSTO pin. If

V

IN

is not above its under voltage thresholds at the end

of the 1 second start up time, the IRQ pin will be pulled

LOW and an under voltage bit will be set in the IRQSTAT

status register.

3589p

30

LTC3589

OPERATION

Figure 14 shows the PGOOD pin and PGSTAT status reg-

ister timing. When no regulator is enabled, the PGOOD

pin is pulled LOW and PGSTAT bits are LOW. PGOOD and

the PGSTAT bits are HIGH 250μs after the last enabled

regulator is within 7% of its target.

fault condition initiates a hard shutdown reset. Figure 15

shows undervoltage warning and fault detection levels.

FAULT

WARNING

V

IN

UNDERVOLTAGE

WAKE HIGH AFTER 1sec

IF PWR_ON HIGH

1sec

2.55V 2.65V 2.9V

3V

V

IN

WAKE

3589 F15

ENx

Figure 15. UV Detection Hard Reset and Warning Levels

25μs

DISABLED IF

WAKE LOW

200μs

AnundervoltagewarningsetsregisterbitIRQSTAT[4]and

V

OUTx

250μs

pulls the IRQ pin LOW.

250μs

14ms

PGOOD

To minimize standby quiescent current the UVLO and

thermal sensor circuits are disabled when all the regula-

tors are off.

IRQ

EXTENDED

UNDERVOLTAGE

(FAULT)

UNDERVOLTAGE

DISABLE

ENABLE

3589 F14

Thermal Shutdown Fault and Warning

Figure 14. PGOOD Pin and PGSTAT Status Register Timing

Similar to the V undervoltage detection circuits the over

IN

temperature detection circuits check for warning and fault

levels.Anovertemperaturefaultwillinitiateafaultinduced

shutdown. An over temperature warning sets register bit

IRQSTAT[6] and pulls the IRQ pin LOW.

If any enabled regulator output falls more than 8% low for

longer than 25μs PGOOD is pulled LOW and a status bit is

set in the PGSTAT register. The PGOOD pin and PGSTAT

status bit remain LOW for as long as the low voltage

condition persists plus 250μs.

IRQ Pin and IRQSTAT Status Register Function

An extended low output rail causing the PGOOD pin to

be LOW for longer than 14ms deﬁnes a PGOOD timeout

fault condition that triggers a hard reset if not masked in

The IRQ pin and IRQSTAT status register report PGOOD

timeout fault, V undervoltage warning and fault, and

IN

high temperature warning and fault. Table 15 shows the

meaning of the IRQSTAT read only status register bits.

2

I C register bit SCR2[7].

During a dynamic voltage slew, PGOOD is pulled LOW

unless bit 5 in the dynamic target voltage register for each

regulator is set HIGH. When SCR2[7] is HIGH, PGOOD

remains in normal operation. The status register PGSTAT

is unaffected by a dynamic voltage slew.

Table 15. IRQSTAT Read Only Register Bit Deﬁnitions

IRQSTAT[BIT] VALUE SETTING

PGOOD Timeout Fault (PGOOD low >

14ms)

3

1

V

Under Voltage Warning (V < 2.9V)

4

5

6

7

1

IN

Under Voltage Fault (V < 2.6V)

IN

Undervoltage Detection

Thermal Limit Warning (T > 130°C)

J

The LTC3589 under voltage (UV) detection circuit will

output a fault condition, locking out regulator operation,

Thermal Limit Fault (T > 150°C)

J

until V reaches 2.7V (typical). Once V is above the

IN

fault threshold the LTC3589 will operate normally until V

IN

drops to 2.6V (typical). When V drops below 2.6V, the

IN

3589p

31

LTC3589

OPERATION

Figure 16 shows the timing of the IRQ and IRQSTAT

Fault Induced Shutdown

status register following a warning (V <2.9V or high

IN

Any of the three fault conditions will initiate a hard reset

shutdown triggering the following events: 1) A bit corre-

sponding to the fault is set in status register IRQSTAT, 2)

IRQ and WAKE pins are pulled LOW, 3) enable pin inputs

are ignored and the regulators are disabled, 4) all enable

bits and software control mode bit in the output voltage

enable OVEN command register are cleared, and 5) the

pushbutton controller is sent to the PDN state for one

second and then to POFF. Re-enabling of regulators is

inhibited until both the fault condition and the one second

time out have passed to allow regulator outputs sufﬁcient

time to discharge. When one second timeout and the fault

condition are both passed, if PWR_ON is HIGH, WAKE will

come up and the LTC3589 will respond to any enable pins

that are also HIGH.

temperature warning) event. When a warning occurs, IRQ

is latched LOW and bit IRQSTAT[4] or IRQSTAT[5] is set.

2

IRQ remains LOW until I C command register CLIRQ is

written. The status bits in the IRQSTAT register will remain

active until CLIRQ is accessed and the warning condition

has passed.

TSD OR UV

WARNING

IRQ

IRQSTAT

CLIRQ

3589 F16

Figure 16. IRQ and IRQSTAT Status Register Warning Timing

2

I C OPERATION

Figure 17 shows the timing of the IRQ pin and IRQSTAT

status register following a fault induced hard shutdown

event. When a fault occurs, IRQ is latched LOW and bit

IRQSTAT[3], IRQSTAT[5], or IRQSTAT[7] is set. IRQ re-

2

I C Interface

The LTC3589 communicates with a bus master using the

standard I C 2-wire interface. The two bus lines, SDA and

2

mainsLOWuntilI CcommandregisterCLIRQisaccessed.

When the CLIRQ command has been issued, the IRQSTAT

status bit remains set for the one second enable inhibit

time or as long as the fault condition persists, whichever

is longer.

SCL, must be HIGH when the bus is not in use. External

pull-up resistors or current sources, such as the LTC1694

SMBus accelerator, are required on these lines. The

LTC3589 is both a slave receiver and slave transmitter. The

2

I C control signals, SDA and SCL are scaled internally to

TSD, UV,

OR PGOOD FAULT

the DV supply. DV should be connected to the same

DD

power supply as the bus pull-up resistors.

IRQ

1 SEC

2

The I C port has an under voltage lockout on the DV

DD

IRQSTAT

CLIRQ

2

pin. When DV is below approximately 1V, the I C serial

DD

port is reset to power-on states and registers are set to

3589 F17

default values.

Figure 17. IRQ and IRQSTAT Status Register Fault Timing

3589p

32

LTC3589

OPERATION

I C Bus Speed

2

I C Byte Format

2

The I C port operates at speeds up to 400kHz. It has

Each byte sent to or received from the LTC3589 must

be 8 bits long followed by an extra clock cycle for the

acknowledge bit. The data should be sent to the LTC3589

most signiﬁcant bit (MSB) ﬁrst.

built-in timing delays to ensure correct operation when

addressed from an I C compliant master device. It also

containsinputﬁltersdesignedtosuppressglitchesshould

the bus become corrupted.

2

I C Acknowledge

2

I C START and STOP Conditions

The acknowledge signal is used for handshaking between

the master and the slave. When the LTC3589 is written

to (write address), it acknowledges its write address and

subsequent register address and data bytes. When read-

ing from the LTC3589, it acknowledges its read address

and 8-bit status byte.

A bus master signals the beginning of communications

by transmitting a START condition. A START condition is

generated by transitioning SDA from HIGH to LOW while

SCL is HIGH. The master may transmit either the slave

write or the slave read address. Once data is written to the

LTC3589, the master may transmit a STOP condition that

commandstheLTC3589toactuponitsnewcommandset.

A STOP condition is sent by the master by transitioning

SDA from LOW to HIGH while SCL is HIGH. The bus it then

An acknowledge pulse (active LOW) generated by the

LTC3589letsthemasterknowthatthelatestbyteofinforma-

tion was transferred. Themastergenerates the clock cycle

and releases the SDA line (HIGH) during the acknowledge

2

free for communication with another I C device.

SDA

t

HD, STA

BUF

t

SU, STO

SU, DAT

t

LOW

HD, STA

HD, DAT

3589 F18

SCL

t

HIGH

t

HD, STA

SP

START

CONDITION

REPEATED START

CONDITION

STOP

START

t

r

t

f

Figure 18. LTC3589 I²C Timing

ADDRESS

SUB-ADDRESS

S7 S6 S5 S4 S3 S2 S1 S0

DATA

SUB-ADDRESS

DATA

D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

WR

D7 D6 D5 D4 D3 D2 D1 D0

S7 S6 S5 S4 S3 S2 S1 S0

START

SDA

STOP

0

1

2

1

3

0

4

0

6

0

7

0

8

1

5

ACK

9

ACK

9

ACK

9

ACK

9

ACK

9

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

SCL

3589 F19

Figure 19. LTC3589 I²C Serial Port Multiple Write Pattern

3589p

33

LTC3589

OPERATION

clock cycle. The LTC3589 pulls down the SDA line during

the write acknowledge clock pulse so that it is a stable

LOW during the HIGH period of this clock pulse.

transferred to an internal holding latch upon the return of

itsacknowledgebytheLTC3589.Continuewritingsub-ad-

dress and data pairs into the holding latches. Addressing

the LTC3589 is not required for each sub-address and

data pair. If desired a REPEAT-START condition may be

2

I C Slave Address

2

initiated by the master where another device on the I C

The LTC3589 responds to factory programmed read and

write addresses. The write address is 0x68. The read ad-

dress is 0x69. The LSb of the address byte, known as the

read/write bit, is 0 when writing data to the LTC3589 and

1 when reading from it.

bus is addressed. The LTC3589 remembers the valid data

2

it has received. Once all the devices on the I C have been

addressed and sent valid data and a global STOP has been

sent, the LTC3589 will update its command latches with

the data it has received.

2

I C Sub-Addressed Writing

2

I C Sub-Addressed Reading

TheLTC3589has14commandregistersforcontrolinputs.

2

The LTC3589 I C interface supports random address

They are accessed by the I C port via a sub-addressed

reading of the I C command and status registers. Before

writing system.

reading a register, the registers sub-address must be writ-

ten.SendaSTARTconditionfollowedbytheLTC3589write

address followed by the sub-address of the register to be

read. The sub-address is now stored as a pointer to the

register. Send a REPEAT-START condition followed by the

LTC3589 read address. Following the acknowledgment of

itsreadaddresstheLTC3589returnsonebitofinformation

for each of the next 8 clock cycles. A STOP condition is

not required for the read operation. The read sub-address

is stored until a new sub-address is written.

Each write cycle of the LTC3589 consists of a series of

three or more bytes beginning with the LTC3589 write

address. The second byte is the sub-address of the

command register being written to. The sub-address is

a pointer to the register where the data in the third byte

will be stored. The third byte is the data to be written to

the just-received sub-address. Continue alternating sub-

address and data bytes to write multiple registers in a

single START sequence.

2

Verifythedatawrittentotheinternaldataholdlatchesprior

to committing date to the command registers by reading

back the data before sending a STOP condition.

I C Bus Write Operation

The master initiates communication with the LTC3589

with a START condition and the LTC3589’s write address.

If the address matches that of the LTC3589, the LTC3589

returns an acknowledge pulse. The master should then

deliverthesub-address.AgaintheLTC3589acknowledges

and the cycle is repeated for the data byte. The data byte is

Continuously poll a register by repeatedly sending a

START condition followed by the LTC3589 read address,

and then clocking the data out after the read address

acknowledge.

ADDRESS

SUB-ADDRESS

ADDRESS

DATA

0

1

0

1

0

WR

S7 S6 S5 S4 S3 S2 S1 S0

0

1

0

1

0

RD

R7 R6 R5 R4 R3 R2 R1 R0

START

ACK

STOP

0

1

2

1

3

SDA

SCL

0

4

1

5

0

6

0

7

0

8

ACK

9

0

1

2

1

3

0

4

1

5

0

6

0

7

1

8

ACK

9

ACK

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

3589 F20

Figure 20. LTC3589 I²C Serial Port Read Pattern

3589p

34

LTC3589

OPERATION

I C Command and Status Registers

2

clearedwhentheLTC3589acknowledgesthesub-address.

Data written to the CLIRQ command register is ignored.

2

Table 16 and Table 17 show the LTC3589 I C command

and status registers. System control register (SCR1) sets

the operating modes of the switching regulators. Each

step-down switching regulator has pulse-skipping, Burst

Mode operation, or forced continuous operation. The

buck-boost switching regulator can be put in continuous

or Burst Mode operation.

There are eight command registers that are used to store

the 5-bit dynamic target voltage input to the feedback

reference slewing DACs – B1DTV1, B1DTV2, B2DTV1,

B2DTV2, B3DTV1, B3DTV2, L2DTV1 and L2DTV2. The

registers ending with V2 use bits 4 through 0 to store

the V2 feedback reference voltage for the regulators. The

regulators input reference voltage is set to V2 by setting

the reference select bits HIGH in VCCR and writing to the

go bits in VCCR. The V2 voltage is also selected whenever

the VSTB pin is driven HIGH. The registers ending with

V1 use bits 4 through 0 to store the V1 feedback voltage

reference for the regulators. The regulators input refer-

ence voltage is set to V1 voltage by setting the reference

select bits LOW in command register VCCR. Whenever

a new dynamic target voltage is set, either by changing

the 5-bit value or by changing the reference select bits in

VCCR, the go bits in VCCR must be written to initiate the

dynamic voltage slew. When bit 5 in B1DTV1, B2DTV1,

B3DTV1, and L2DTV1 is LOW the PGOOD pin pulls LOW

during a dynamic voltage slew. Bits 7 and 6 in B1DTV1

set the switch DV/DT rate for all the step-down switch-

ing regulators. Bit 5 in registers B1DTV2, B2DTV2 and

B3DTV2 selects the switching frequency of step-down

switching regulators 1, 2 and 3. Writing the bit LOW sets

the switching frequency to 2.25MHz. Writing the bit HIGH

sets the switching frequency to 1.125MHz.

The output voltage enable (OVEN) command register

controls the individual enables of each regulator. When

OVEN[7] is set to a logic LOW value, bits OVEN[6-0} are

ORed with their respective enable pins. When OVEN[7]

is HIGH, the input pins EN1, EN2, EN3, EN4, EN_LDO2,

and EN_LDO34, are ignored and the LTC3589 regulators

respond only to the OVEN register. When the regulators

are conﬁgured in a hard wired power-up sequence, setting

OVEN[7] allows software control of individual regulators.

When the PWR_ON pin is pulled LOW all bits in the OVEN

register are reset to POR state of 0x00.

Systemcontrolregister2(SCR2)controlstheoperationof

theregulatorstart-upandregulatorpower-good(PGOOD)

hardshutdownoperation. SetcommandregisterSCR2[7]

to inhibit a hard shutdown of the regulators in the event

of an extended low output rail voltage. The low output

voltage event is still reported via the IRQ pin and IRQSTAT

status register. Set the bits in SCR2[6-0] LOW to force a

regulator to ignore its enable until its output has fallen to

less than 300mV (typical). If set HIGH, the regulator will

enable without waiting for its output to discharge and will

not engage the 2k discharge resistor.

The dynamic slew rates of the four feedback reference

DACsareindependentlysetusingbitsinvoltageramprate

commandregister(VRRCR). Therateshownistheslewof

the DAC output as it slews up or down to its target value.

The slew rate of the output voltage is scaled by the gain of

the resistor divider network that sets the regulator output

voltage. For example, a regulator set to an output voltage

of1.2Vwhenthedynamictargetvoltagereferenceis0.75V

has a gain of 1.6. Slewing the regulator output from 1.2V

to 1V requires slewing the DAC output down 125mV from

750mV to 625mV. With a VRRCR slew rate setting of 01

the slew time of the regulator output is 71μs.

LDO2andstep-downswitchingregulators1to3eachhave

a pair of control bits in the voltage change control register

VCCR. The reference select bit selects which of two 5-bit

words are used as inputs to the regulators feedback refer-

ence DAC inputs. The slew go bit initiates a DAC slew to

the voltage selected by the reference select bit. When the

slew is complete, the slew go bits are reset LOW.

Accessing the CLIRQ command register will clear the IRQ

pin and will let the IRQ pin to release HIGH. The pin is

3589p

35

LTC3589

OPERATION

Table 16. LTC3589 Command Register Table

REG NAME B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

DEFAULT

0x07 SCR1

Buck-Boost

Mode:

Step-Down Switching

Regulator 3 Mode :

Step-Down Switching

Regulator 2 Mode :

Step-Down Switching

Regulator 1 Mode :

0000 0000

0 =

0 0 = Pulse-Skipping

0 1 = Burst

0 0 = Pulse-Skipping

0 1 = Burst

0 0 = Pulse-Skipping

0 1 = Burst

Continuous

1 = Burst

Mode

1 0 = Forced Continuous

0x10 OVEN

Software

Control Mode:

EN_LDO4

EN_LDO3

EN_LDO2

EN4

EN3

EN2

EN1

0000 0000

0 = Enable

with Pin

or OVEN

Register

1 = Enable/

Disable

with OVEN

Register Only

0x12 SCR2

Mask

LDO4 Startup: LDO3

Startup:

LDO2

Startup:

Buck-Boost

Startup:

Step-Down

Switching

Regulator 3

Startup:

Step-Down

Switching

Regulator 2

Startup:

Step-Down 0000 0000

Switching

PGOOD

Hard

Regulator 1

Shutdown:

Startup:

0 = Wait for

Output <

0 = Wait

0 = Allow

PGOOD

Timeout

Hard

0 = Wait

for Output

< 300mV

for Output

< 300mV

for Output

< 300mV

for output

< 300mV

300mV Before for Output

for Output

< 300mV

Enable

< 300mV

Before Enable Before

Enable

Before Enable Before Enable Before Enable Before Enable

Shutdown.

1 = Don’t Wait 1 = Don’t Wait 1 = Don’t Wait 1 = Don’t

and Disable

1 = Don’t Wait 1 = Don’t Wait

and Disable

Discharge

Resistor.

and Disable

Discharge

Resistor.

Wait and

Disable

Discharge

Resistor.

1 = Inhibit

PGOOD

Hard

and Disable

Discharge

Resistor.

and Disable 1 = Don’t Wait Discharge

Discharge

Resistor.

and Disable Resistor.

Discharge

Shutdown.

Resistor.

0x20 VCCR

LDO2

Reference

Select:

Start LDO2

Slew:

Step-Down

Switching

Regulator 3

Reference

Select:

Start

Step-Down Switching

Switching Regulator 2

Step-Down

Start

Step-Down

Switching

Regulator 1

Reference

Select:

Start

0000 0000

Step-Down

Switching

Regulator 2

Slew:

Step-Down

Switching

Regulator 1

Slew:

Regulator 3 Reference

Slew:

Select:

0 =

0 = Went

1 = GO

0 =

0 = Went

1= GO

0 =

0 = Went

1= GO

0 =

0 = Went

1= GO

L2DTV1[4-0]

B3DTV1[4-0]

B2DTV1[4-0]

B1DTV1[4-0]

1 =

L2DTV2[4-0]

B3DTV2[4-0]2

B2DTV2[4-0]

B1DTV2[4-0]2

0x21 CLIRQ

0x23 B1DTV1 Step-Down Switching

Regulator Switch DV/DT

Control:

PGOOD

Mask:

Step-Down Switching Regulator 1 Feedback Reference Input (V1)

0001 1001

0 = PGOOD

Low When

Slewing

00 = 1ns

01 = 2ns

10 = 4ns

11 = 8ns

1 = PGOOD

Not Forced

Low When

Slewing.

3589p

36

LTC3589

OPERATION

Table 16. LTC3589 Command Register Table

0x24 B1DTV2 Keep-Alive

Mode:

Phase

Step-Down

Switching

Regulator 1

Clock Rate

Step-Down Switching Regulator 1 Feedback Reference Input (V2)

1111 1111

Select:

0 = Normal

Shutdown

0 = Clock

Phase 1

0 = 2.25MHz

1 = 1.12MHz

1 = Keep-Alive 1 = Clock

Phase 2

0x25 VRRCR LDO2 Dynamic Reference

Slew Rate:

Step-Down Switching

Regulator 3 Dynamic

Reference Slew Rate:

Step-Down Switching

Regulator 2 Dynamic

Reference Slew Rate:

Step-Down Switching

1111 1111

0001 1001

Regulator 1 Dynamic

Reference Slew Rate:

00 = 0.88mV/μs

01 = 1.75mV/μs

10 = 3.5mV/μs

11 = 7mV/μs

00 = 0.88mV/μs

01 = 1.75mV/μs

10 = 3.5mV/μs

11 = 7mV/μs

00 = 0.88mV/μs

01 = 1.75mV/μs

10 = 3.5mV/μs

11 = 7mV/μs

00 = 0.88mV/μs

01 = 1.75mV/μs

10 = 3.5mV/μs

11 = 7mV/μs

0x26 B2DTV1 Unused

PGOOD

Mask:

Step-Down Switching Regulator 2 Feedback Reference Input (V1)

0 = PGOOD

Low When

Slewing

1 = PGOOD

Not Forced

Low When

Slewing.

0x27 B2DTV2 Keep-Alive

Mode:

Phase

Step-Down

Switching

Regulator 2

Clock Rate

Step-Down Switching Regulator 2 Feedback Reference Input (V2)

Step-Down Switching Regulator 3 Feedback Reference Input (V1)

0001 1001

Select:

0 = Normal

Shutdown

0 = Clock

Phase 1

0 = 2.25MHz

1 = 1.125MHz

1 = Keep-Alive 1 = Clock

Phase 2

0x29 B3DTV1 Unused

PGOOD

Mask:

0 = PGOOD

Low When

Slewing

1 = PGOOD

Not Forced

Low When

Slewing.

0x2A B3DTV2 Keep-Alive

Mode:

Phase

Step-Down

Switching

Regulator 3

Clock Rate

Step-Down Switching Regulator 3 Feedback Reference Input (V2)

0001 1001

Select:

0 = Normal

Shutdown

0 = Clock

Phase 1

0 = 2.25MHz

1 = 1.125MHz

1 = Keep-Alive 1 = Clock

Phase 2

3589p

37

LTC3589

OPERATION

Table 16. LTC3589 Command Register Table

0x32 L2DTV1 Keep-Alive

Mode:

Unused

PGOOD

Mask:

LDO 2 Feedback Reference Input (V1)

0001 1001

0 = Normal

Shutdown

0 = PGOOD

Low When

Slewing

1 = Keep-Alive

1 = PGOOD

Not Changed

When

Slewing.

0x33 L2DTV2 LDO4 Control LDO4 Output Voltage:

MODE:

LDO 2 Feedback Reference Input (V2)

0001 1001

00 = 2.8V

0 = LDO4

01 = 2.5V

Enable with

10 = 1.8V

EN_LDO34

11 = 3.3V

1 = LDO4

Enable with

OVEN[6]

Table 17. LTC3589 Read Only Status Register Table

REG NAME

B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

0x02 IRQSTAT Thermal

Limit Hard

Near Thermal Undervoltage Near

PGOOD

Unused

Limit

Hard Shut

Down

Undervoltage

Limit

Timeout Hard

Shutdown

Occurred

Shut Down

Occurred

0x13 PGSTAT LDO4 Status: LDO3 Status: LDO2 Status: Buck_Boost

Status:

Step-Down

Switching

Regulator 3

Status:

Step-Down

Switching

Regulator 2

Status:

Step-Down

Switching

Regulator 1

Status:

LDO1 Status:

0 = V

1 = V

Low 0 = V

1 = V

Low 0 = V

1 = V

Low 0 = V

Good 1 = V

Low

0 = V

1 = V

Low 0 = V

Low

OUT

Good

1 = V

Good 1 = V

Good

OUT

Good

OUT

Good

OUT

Good

OUT

THERMAL CONSIDERATIONS AND BOARD LAYOUT

Printed Circuit Board Power Dissipation

To ensure the junction temperature of the LTC3589 die

does not exceed the maximum rated limit and to prevent

over temperature faults, the power output of the LTC3589

must be managed by the application. The total power dis-

sipation in the LTC3589 is approximated by summing the

power dissipation in each of the switching regulators and

the LDO regulators.

In order to ensure optimal performance and the ability

to deliver maximum output power to any regulator, it is

critical that the exposed ground pad on the backside of

the LTC3589 package be soldered to a ground plane on

the board. The exposed pad is the only GND connection

Thepowerdissipationinaswitchingregulatorisestimated

by:

2

fortheLTC3589. Correctlysolderedtoa2500mm ground

plane on a double sided 1oz copper board the LTC3589

100 – Eff

has a thermal resistance (θ ) of approximately 34°C/W.

JA

P_D(SWX)=(V_OUTX•I_OUTX)•

100

Failuretomakegoodthermalcontactbetweentheexposed

pad on the backside of the package and an adequately

sized ground plane will result in thermal resistances far

greater than 34°C/W.

Where V

is the programmed output voltage, I

OUTX

is the load current and Eff is the % efﬁciency that can

3589p

38

LTC3589

OPERATION

be measured or looked up in an efﬁciency table for the

programmed output voltage.

Printed Circuit Board Layout

When laying out the printed circuit board, the following

checklist should be followed to ensure proper operation

of the LTC3589:

The power dissipated by an LDO regulator is estimated

by:

1. Connect the exposed pad of the package (Pin 41)

directly to a large ground plane to minimize thermal

and electrical impedance.

P

_D(LDOX)=(V_IN(LDOX)– V _LDOX)•I_LDOX

WhereV istheprogrammedoutputvoltage,V

is the LDO supply voltage, and I

current. If one of the switching regulator outputs is used

as an LDO supply voltage, remember to include the LDO

supply current in the switching regulator load current for

calculating power loss.

LDOX

IN(LDOX)

is the output load

LDOX

2. The switching regulator input supply traces and their

decoupling capacitors should be as short as possible.

Connect the GND side of the capacitors directly to the

ground plane of the board. The decoupling capacitors

provide the AC current to the internal power MOSFETs

andtheirdrivers. Itisimportanttominimizeinductance

from the capacitors to the LTC3589 pins.

With θ of 34°C/W and maximum ambient operating

JA

temperature of 85°C, the power dissipation must be kept

under 1.18W so that maximum junction temperature is

less than 125°C.

3. Minimize the switching power traces connecting SW1,

SW2, SW3, and buck-boost switch pins SW4AB and

SW4CD to the inductors to reduce radiated EMI and

parasitic coupling. Keep sensitive nodes such as the

feedback pins away from or shielded from the large

voltage swings on the switching nodes.

Anexampleusingtheequationsabovewiththeparameters

in Table 18 shows an application that is at the maximum

junction temperature of 125°C at an ambient temperature

of 85°C. LDO2, LDO3, and LDO4 are powered by step-

down switching regulator 2 and the buck-boost switching

regulator. The total load on those two switching regulators

is the sum of the application load and the LDO load. This

example is with the LDO regulators at one half rated cur-

rent and the switching regulators at three quarters rated

current.

4. Minimize the length of the connection between the

step-down switching regulator inductors and the out-

put capacitors. Connect the GND side of the output

capacitors directly to the thermal ground plane of the

board.

5. Minimize the length of the connection between the

buck-boost regulator output (BB_OUT) and the output

capacitor. Connect the GND side of the output capacitor

directly to the thermal ground plane of the board.

Table 18. T_JCalculation Example

OUTPUT

V

APP LOAD TOTAL

LOAD

EFF

POWER

DISS

IN

OUT

LDO1_VSTB 3.8V 1.2V

10mA

100mA

1.2A

10mA

100mA

1.2A

30mW

60mW

LDO2

LDO3

LDO4

1.8V 1.2V

3.3V 1.8V

3.3V 2.5V

3.8V 1.2V

3.8V 1.8V

3.8V 1.25V

3.8V 3.3V

150mW

80mW

V

80%

90%

85%

90%

290mW

140mW

300mW

OUT1

OUT2

OUT3

OUT4

0.65A

0.75A

0.70A

0.75A

0.90A

TOTAL POWER 1180mW

INTERNAL JUNCTION TEMPERATURE AT 85°C AMBIENT 125°C

3589p

39

LTC3589

APPLICATIONS INFORMATION

The LTC3589 is optimized to support several families

of advanced portable applications processors including

the Marvell PXA3xx and PXA168 xscale processors, the

Freescale i.MX family including the new i.MX51, the TI

OMAP processors utilizing their Smart reﬂex, and many

additional ARM processors.

The LTC3589 RSTO signal is used to drive the Monahans

hard reset signal nRESET and is based on the state of

the always-active regulator output LDO1_STBY and by a

pushbutton hard reset request. The release of the RSTO

output is delayed a minimum of 10ms as required or as

long as 1s when the LTC3589 is reset using its pushbut-

ton controller.

PXA3XX Monahans Processor Support

PXA16X Armada Processor Support

The PXA3XX processors are hardcoded to communicate

with a PMIC at speciﬁc command register addresses in

order to power up the processor supply rails from the

LTC3589 includes spare register bits that can be accessed

by the processor for setting and recalling hibernate and

resume operation.

2

low power state. The LTC3589 I C device address and

command register addresses map to PXA3xx command

register sub-address requirements. The LTC3589 write

address is 0x68. The key command register addresses

for PXA3xx support are the Output Voltage Enable (OVEN)

register at address 0x10. VCC_APPS/A_EN is mapped

to OVEN bit 0 (enable step-down switching regulator 1).

VCC_SRAM/S_EN is mapped to OVEN bit 2 (enable step-

down switching regulator 3). The voltage change control

register (VCCR) at command register address 0x20 con-

trols the dynamic voltage select and go bits required to

command a voltage change and slew when coming out

of low voltage standby or sleep modes into run mode.

The dynamic target voltage (xxDTV[1,2]) registers map

to the mandatory command register addresses. The full

register map for the LTC3589 shown in Table 15 and Table

The keep-alive function allow a step-down switching

regulator to maintain system memory during a hibernate

shutdown state of the Armada processor.

i.MX Processor Support

The LTC3589 has hardware features speciﬁcally designed

for the latest i.MX family of processors from Freescale

Semiconductor. The i.MX37 controls the VSTB input pin

of the LTC3589 to command transitions between the run

modecorevoltageandthelowerlevelstandbyvoltage.The

run and standby voltage levels are initially programmed

2

in I C command registers xxBTV1 and xxBTV2. When the

VSTB pin is asserted high all four dynamically controlled

output supply rails will slew to the xxBTV2 set point. When

xxBTV1 and xxBTV2 are set at the same value, as they are

by default, then no slewing occurs. This allows the single

VSTB pin to control any combination of the four DAC con-

trolledregulatorstoslewbetweentwoprogrammedoutput

voltages. When VSTB is de-asserted back to a zero value

the regulators slew back up to the xxBTV1 set point.

2

16 supports Monahans, hard-coded I C commands for

start-of-day operation, voltage-change sequence, supply

enable, and return-to-D0 state sequence.

The LTC3589 does not speciﬁcally reference the Mo-

nahans SYS_EN and PWR_EN enable pins but supports

these signals with individual enable input pins EN[1-4]

and EN_LDO[2,3] that should be hard-wired to SYS_EN

or PWR_EN as required for proper system level power

sequencing.

Earlieri.MXfamilyprocessorssuchasthei.MX31included

two VSTB pins used for controlling the regulator outputs

foralowvoltagestandbymode,nominalvoltagerunmode,

and a higher voltage overdrive mode. The LTC3589 can

be used with these processors using the VSTB input pin

3589p

40

LTC3589

APPLICATIONS INFORMATION

OMAP3 and DaVinci Processor Support

to select between run and standby voltages and using

minimal software overhead to set the overdrive voltage

TheOMAP3familyofARMprocessorshassimilarrequire-

mentstotheprocessorsdescribedabove.TheLTC3589I C

2

in I C command registers.

2

control can fully accommodate the smart reﬂex dynamic

voltage control with proper embedded software drivers

tailored to the LTC3589 register mapping. The LTC3589

demo board demonstrates conﬁguring and dynamically

The default DAC reference levels in all xxBTVx registers

is 0x19. This accommodates i.MX processors and oth-

ers requiring an overdrive voltage. The voltage can be

increased up to 0x1F for overdrive or supply margining

abovethenominalrunvoltage. Onceprogrammedintothe

2

slewing and sequencing the outputs using I C control.

2

The same provisions can be incorporated into embed-

ded software drivers for the OMAP3 or any other target

processor.

I C command registers xxBTVx two voltage outputs are

selected by the VSTB pin. All voltage levels and changes

2

are fully controlled using the I C serial port.

3589p

41

LTC3589

TYPICAL APPLICATION

V

IN

10μF

FREESCALE

i.MX51

10μF

1μH

37

IN

6

V

PV

IN1

NVCC_SRTC_PDW

V

CORE

0.647V TO 1.34V

1.6A

7

SW1

V

CC(CORE)

V

RTC

FASTR_ANA

FASTR_DIG

604K

768K

10pF

22μF

36

35

1.2V

LDO1_STDBY

LDO1_FB

39

24

25

33

25mA

BUCK1_FB

511k

1μF

10μF

PV

IN2

V

/DDR

SRAM

1.8V

1A

NVCC_EMI_DRAM

NVCC_CNTL_EMI

NVCC_PER2,3,4,6,8,9

NVCC_EMI(NAND+EMI)

1.5μH

1.02M

SW2

LTC3589

715K

422K

10pF

22μF

BUCK2_FB

18.2k

V

9.09k

SRAM

10μF

10k

V

27

26

34

SOC

PV

IN3

V

10

SOC

10k

EN1

EN2

0.676V to 1.4V

1A

11

13

14

9

18

20

1.5μH

SW3

VDDGP

WAKE

EN3

EN4

EN_LDO2

EN_LDO34

PWR_ON

9.09k

681K

787K

10pF

22μF

V

CORE

BUCK3_FB

10k

PWR_ON

10μF

15

16

V

IO

PV

IN4

3.3V

1.2A

VDDA33

VDD_FUSE

NVCC__EMI

NVCC_PER13,14

BB_OUT

21

1M

4.7pF

ON

40

BB_FB

316k

12

19

SW4AB

SW4CD

2.7μH

V

1μF

VDDA

VDD_DIG_PLL_A&B

VDD_TVDIG

MEMORY

1

2

0.647V TO 1.34V

250mA

V

IN_LDO2

LDO2

V

ANALOG

1.8V

604k

VDD_AVA_PLL_A&B

NVCC_IPU

38

250mA

1μF

LDO2_FB

768k

1μF

5

3

VDD_TVSUPPLY

AHVDDRGB

V

IN_LDO34

LDO3

NVCC_DAC

1μF

NVCC_TV_BACK

NVCC_USBPHY

NVCC_OSC

V

AUX

2.8V

4

250mA

LDO4

1μF

32

31

30

28

23

22

29

17

8

DV

DD

PWR_ON

GPIO

SDA

SCL

VSTB

I2C2_SDA

I2C2_SCL

PMIC_VSTBY_REQ

GPIO

WAKE

PBSTAT

PGOOD

IRQ

GPIO

PMIC_RDY

GPIO1/IRQ

POR_B

RST0

GND

41

3589 TA02

3589p

42

LTC3589

PACKAGE DESCRIPTION

UJ Package

40-Lead Plastic QFN (6mm × 6mm)

(Reference LTC DWG # 05-08-1728 Rev Ø)

0.70 ±0.05

6.50 ±0.05

5.10 ±0.05

4.42 ±0.05

4.50 ±0.05

(4 SIDES)

4.42 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 ± 0.05

R = 0.115

TYP

6.00 ± 0.10

(4 SIDES)

R = 0.10

TYP

39 40

0.40 ± 0.10

PIN 1 TOP MARK

(SEE NOTE 6)

1

2

PIN 1 NOTCH

R = 0.45 OR

0.35 × 45°

CHAMFER

4.42 ±0.10

4.50 REF

(4-SIDES)

4.42 ±0.10

(UJ40) QFN REV Ø 0406

0.200 REF

0.25 ± 0.05

0.00 – 0.05

0.50 BSC

NOTE:

BOTTOM VIEW—EXPOSED PAD

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

3589p

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

43

LTC3589

TYPICAL APPLICATION

RELATED PARTS

PART

NUMBER

DESCRIPTION

COMMENTS

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2

Converters Efﬁciency: >95%, ADJ Outputs: 0.8V to 3.6V at 800mA/500mA/500mA, Pushbutton Control, I C

Interface, 2 × 150mA LDOs, Overvoltage Protection Bat-Track Adaptive Output Control, 200mΩ Ideal Diode,

4mm × 7mm QFN-44 Package -1 and -4 versions have 4.1V V

, -3 Version for SiRF Atlas IV Processors

FLOAT

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Converter + Boost + LDO

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.

FLOAT

3589p

LT 0610 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

44

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3589IUJ-TRPBF
厂家：	Linear
描述：	8-Output Regulator with Sequencing and I2C 8路输出稳压器，带有排序和I2C 稳压器
文件：	总44页 (文件大小：560K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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