LTC3612EUDC#PBF_技术文档

LTC3612

3A, 4MHz Monolithic

Synchronous Step-Down

DC/DC Converter

DescripTion

FeaTures

The LTC^®3612 is a low quiescent current monolithic syn-

chronous buck regulator using a current mode, constant

n

3A Output Current

n

2.25V to 5.5V Input Voltage Range

Low Output Ripple Burst Mode^®Operation: I = 70µA frequency architecture. The no-load DC supply current

n

Q

n

±±1 Output Voltage Accuracy

in sleep mode is only 70µA while maintaining the output

voltage(BurstModeoperation)atnoload,droppingtozero

currentinshutdown.The2.25Vto5.5Vinputsupplyvoltage

range makes the LTC3612 ideally suited for single Li-Ion

as well as fixed low voltage input applications. 100% duty

cyclecapabilityprovideslowdropoutoperation,extending

the operating time in battery-powered systems.

Output Voltage Down to 0.6V

High Efficiency: Up to 951

Low Dropout Operation: 100% Duty Cycle

Shutdown Current: ≤1µA

Adjustable Switching Frequency: Up to 4MHz

Optional Active Voltage Positioning (AVP) with

Internal Compensation

The operating frequency is externally programmable up to

4MHz, allowing the use of small surface mount inductors.

For switching noise-sensitive applications, the LTC3612

can be synchronized to an external clock at up to 4MHz.

n

Selectable Pulse-Skipping/Forced Continuous/

Burst Mode Operation with Adjustable Burst Clamp

Programmable Soft-Start

n

Inputs for Start-Up Tracking or External Reference

ForcedcontinuousmodeoperationintheLTC3612reduces

noiseandRFinterference.Adjustablecompensationallows

the transient response to be optimized over a wide range

of loads and output capacitors.

DDR Memory Mode, I

= 1.5A

OUT

Available in Thermally Enhanced 20-Pin

(3mm × 4mm) QFN and TSSOP Packages

applicaTions

The internal synchronous switch increases efficiency and

eliminates the need for an external catch diode, saving

external components and board space. The LTC3612 is

offeredinaleadless20-pin3mm×4mmQFNorathermally

enhanced 20-pin TSSOP package.

L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks

of Linear Technology Corporation. All other trademarks are the property of their respective

owners. Protected by U.S. Patents, including 6580258, 5481178, 5994885, 6304066, 6498466,

6611131.

n

Point-of-Load Supplies

n

Distributed Power Supplies

n

Portable Computer Systems

n

DDR Memory Termination

n

Handheld Devices

Typical applicaTion

Efficiency and Power Loss vs Load Current

100

90

80

70

60

50

40

30

20

10

0

10

V

IN

2.5V TO 5.5V

22µF

1

s2

SV

PV

IN

RUN

TRACK/SS

RT/SYNC

PV

IN_DRV

DDR

0.1

0.01

0.001

560nH

665k

V

2.5V

3A

OUT

LTC3612

SW

SGND

PGND

PGOOD

ITH

47µF

MODE

V

FB

V

= 5V

= 3.3V

= 2.8V

IN

3612 TA01a

210k

1

10

100

1000

10000

OUTPUT CURRENT (mA)

3612 TA01b

3612fa

ꢀ

LTC3612

absoluTe MaxiMuM raTings ^{(Notes ±, ±±)}

PV , SV , PV Voltages ..................... –0.3V to 6V

Operating Junction Temperature Range

IN

IN_DRV

SW Voltage ..................................–0.3V to (PV + 0.3V)

(Notes 2, 11).......................................... –40°C to 125°C

Storage Temperature.............................. –65°C to 150°C

Reflow Peak Body Temperature (QFN).................. 260°C

Lead Temperature (Soldering, 10 sec)

IN

ITH, RT/SYNC Voltages............... –0.3V to (SV + 0.3V)

IN

DDR, TRACK/SS Voltages........... –0.3V to (SV + 0.3V)

IN

MODE, RUN, V Voltages .......... –0.3V to (SV + 0.3V)

FB

IN

PGOOD Voltage............................................ –0.3V to 6V

TSSOP .............................................................. 300°C

pin conFiguraTion

TOP VIEW

SV

1

2

3

4

5

6

7

8

9

20

19

18

17

16

15

14

13

12

11

PV

IN_DRV

IN

RUN

PGOOD

MODE

SW

NC

SW

PV

20 19 18 17

DDR

RT/SYNC

SGND

NC

1

2

3

4

5

6

16 PGOOD

15 RUN

V

FB

IN

21

14 SV

13 PV

IN

ITH

TRACK/SS

DDR

PV

IN

21

IN_DRV

SW

NC

SW

NC

SW

12 SW

11 SW

SW

RT/SYNC

7

8

9 10

SGND 10

FE PACKAGE

UDC PACKAGE

20-LEAD (3mm s 4mm) PLASTIC QFN

20-LEAD PLASTIC TSSOP

T

= 125°C, θ = 38°C/W

JA

EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED TO PCB

JMAX

T

JMAX

= 125°C, θ = 43°C/W

JA

EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

LTC3612EUDC#PBF

LTC3612IUDC#PBF

LTC3612EFE#PBF

LTC3612IFE#PBF

TAPE AND REEL

PART MARKING*

LDQT

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3612EUDC#TRPBF

LTC3612IUDC#TRPBF

LTC3612EFE#TRPBF

LTC3612IFE#TRPBF

–40°C to 125°C

20-Lead (3mm × 4mm) Plastic QFN

20-Lead Plastic TSSOP

LDQT

LTC3612FE

20-Lead Plastic TSSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3612fa

ꢁ

LTC3612

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating junction

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 3.3V, RT/SYNC = SV_IN, unless otherwise specified (Note 2).

SYMBOL

PARAMETER

CONDITIONS

MIN

2.25

1.7

TYP

MAX

UNITS

l

V

Operating Voltage Range

Undervoltage Lockout Threshold

5.5

V

IN

l

SV Ramping Down

V

UVLO

IN

SV Ramping Up

2.25

IN

V

FB

Feedback Voltage Internal Reference (Notes 3, 4) V

= SV , V

= 0V

TRACK/SS

IN DDR

0°C < T < 85°C

0.594

0.591

0.6

0.606

0.609

V

J

l

–40°C < T < 125°C

J

Feedback Voltage External Reference (Notes 3, 4) V

= 0.3V, V

= 0.5V, V

= SV

0.289

0.489

0.3

0.5

0.311

0.511

30

V

TRACK/SS

DDR

IN

(Note 7)

(Notes 3, 4) V

= 0.6V

= SV

DDR

IN

l

I

FB

Feedback Input Current

Line Regulation

V

FB

nA

SV = PV = 2.25V to 5.5V

0.2

%/V

∆V

IN

LINEREG

(Notes 3, 4) TRACK/SS = SV

IN

Load Regulation

ITH from 0.5V to 0.9V (Notes 3, 4)

0.25

2.6

%

∆V

LOADREG

V

= SV (Note 5)

IN

ITH

I

S

Active Mode

Sleep Mode

= 0.5V, V

= 0.7V, V

= SV (Note 6)

1100

70

µA

FB

MODE

IN

= 0V, ITH = SV

100

IN

(Note 5)

V

= 0.7V, V

= 0V (Note 4)

120

0.1

70

160

1

µA

FB

MODE

Shutdown

SV = PV = 5.5V, V

= 0V

RUN

IN

R

Top Switch On-Resistance

Bottom Switch On-Resistance

Top Switch Current Limit

PV = 3.3V (Note 10)

mΩ

DS(ON)

IN

PV = 3.3V (Note 10)

45

IN

I

Sourcing (Note 8), V = 0.5V

LIM

FB

Duty Cycle <35%

5.2

4

6

6.8

–5

A

Duty Cycle = 100%

Bottom Switch Current Limit

Sinking (Note 8), V = 0.7V,

–3

–4

A

FB

Forced Continuous Mode

g

Error Amplifier Transconductance

Error Amplifier Max Output Current

Internal Soft-Start Time

–5µA < I < 5µA (Note 4)

200

30

1

µS

µA

m(EA)

ITH

I

t

(Note 4)

EAO

V

from 0.06V to 0.54V,

0.65

1.5

ms

SS

FB

TRACK/SS = SV

IN

V

Enable Internal Soft-Start

(Note 7 )

0.62

70

V

TRACK/SS

t

Soft-Start Discharge Time at

Start-Up

µs

TRACK/SS_DIS

R

TRACK/SS Pull-Down Resistor at

Start-Up

200

Ω

ON(TRACK/SS_DIS)

OSC

l

f

Oscillator Frequency

RT/SYNC = 370k

= SV

0.8

1.8

0.3

1.2

.

1

1.2

2.7

4

MHz

V

Internal Oscillator Frequency

Synchronization Frequency

SYNC Level High

V

2.25

RT/SYNC

IN

f

SYNC

V

RT/SYNC

SYNC Level Low

0.3

1

V

I

Switch Leakage Current

DDR Option Enable Voltage

Internal Burst Mode Operation

Pulse-Skipping Mode

SV = PV = 5.5V, V = 0V

RUN

0.1

µA

V

SW(LKG)

IN

V

SV – 0.3

IN

DDR

0.3

V

MODE

(Note 9)

SV – 0.3

IN

V

Forced Continuous Mode

External Burst Mode Operation

1.1

SV • 0.58

V

IN

0.45

0.8

V

3612fa

ꢂ

LTC3612

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating junction

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 3.3V, RT/SYNC = SV_IN, unless otherwise specified (Note 2).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PGOOD

Power Good Voltage Windows

TRACK/SS = SV , Entering Window

IN

V

Ramping Up

–3.5

3.5

–6

6

%

FB

Ramping Down

TRACK/SS = SV , Leaving Window

IN

V

Ramping Up

9

–9

11

–11

%

FB

Ramping Down

t

Power Good Blanking Time

Power Good Pull-Down On-Resistance

RUN Voltage

Entering and Leaving Window

70

8

105

17

140

33

µs

Ω

PGOOD

R

PGOOD

RUN

l

V

Input High

Input Low

1

V

0.4

Note ±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: This parameter is tested in a feedback loop which servos V to

FB

the midpoint for the error amplifier (V = 0.75V).

ITH

Note 4: External compensation on ITH pin.

Note 5: Tying the ITH pin to SV enables the internal compensation and

IN

Note 2: The LTC3612 is tested under pulsed load conditions such that

AVP mode.

T

≈

T . The LTC3612E is guaranteed to meet performance specifications

J

A

Note 6: Dynamic supply current is higher due to the internal gate charge

being delivered at the switching frequency.

from 0°C to 85°C junction temperature. Specifications over the

–40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LTC3612I is guaranteed over the full –40°C to 125°C operating

junction temperature range. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

impedance and other environmental factors. The junction temperature

(T , in °C) is calculated from the ambient temperature (T , in °C) and

Note 7: See description of the TRACK/SS pin in the Pin Functions section.

Note 8: In sourcing mode the average output current is flowing out of SW

pin. In sinking mode the average output current is flowing into the SW Pin.

Note 9: See description of the MODE pin in the Pin Functions section.

Note ±0: Guaranteed by correlation and design to wafer level

measurements for QFN packages.

Note ±±: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

J

A

power dissipation (P , in watts) according to the formula:

D

T = T + (P • θ ), where θ (in °C/W) is the package thermal

J

A

D

JA

impedance.

Typical perForMance characTerisTics ^V_IN= 3.3V, RT/SYNC = SV_IN, unless otherwise noted.

Efficiency vs Load Current

(V_MODE= 0V)

Efficiency vs Load Current

(V_MODE= 0V)

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

OUT

= 1.8V

V

OUT

= 1.2V

V

= 5V

= 3.3V

= 2.5V

V

= 5V

= 3.3V

= 2.5V

IN

1

10

100

1000

10000

1

10

100

1000

10000

OUTPUT CURRENT (mA)

3612 G01

3612 G02

3612fa

ꢃ

LTC3612

Typical perForMance characTerisTics ^V_IN= 3.3V, RT/SYNC = SV_IN, unless otherwise noted.

Efficiency vs Input Voltage

(V_MODE= 0V)

Efficiency vs Frequency

(V_MODE= 0V), I_OUT= ±A

Efficiency vs Load Current

100

90

80

70

60

50

40

30

20

10

0

95

94

93

92

91

90

89

88

87

86

85

84

83

82

100

90

V

OUT

= 1.8V

V

= 1.8V

V

OUT

= 1.8V

OUT

Burst Mode

EXTERNAL

CLAMP = 0.7V

Burst Mode

INTERNAL

CLAMP

PULSE-

SKIPPING

MODE

80

70

60

50

40

I

= 3mA

OUT

= 300mA

= 1A

1µH

0.68µH

0.33µH

FORCED

CONTINUOUS

MODE

= 3A

30

0.5

1.5 2.0 2.5 3.0 3.5 4.0 4.5

FREQUENCY (MHz)

1.0

1

10

100

1000

10000

2.25

2.75 3.25

3.75 4.25 4.75 5.25

INPUT VOLTAGE (V)

OUTPUT CURRENT (mA)

3612 G03

3612 G05

3612 G04

Load Regulation

Line Regulation

Burst Mode Operation

0.3

0.2

1.5

1.3

1.1

0.9

0.7

0.5

0.3

0.1

–0.1

FORCED CONTINUOUS MODE

INTERNAL Burst Mode OPERATION

PULSE-SKIPPING MODE

V

OUT

20mV/DIV

0.1

I

L

0

500mA/DIV

3612 G08

–0.1

–0.2

–0.3

V

= 1.8V

20µs/DIV

OUT

I

= 75mA

V

= 0V

MODE

V

= 1.8V

OUT

–0.3

2.20

3.30 3.85 4.40

INPUT VOLTAGE (V)

4.95 5.50

2.75

0

500 1000 1500

OUTPUT CURRENT (mA)

3000

2000 2500

3612 G07

3612 G06

Pulse-Skipping Mode Operation

Forced Continuous Mode Operation

V

OUT

20mV/DIV

V

OUT

20mV/DIV

I

L

200mA/DIV

I

L

500mA/DIV

3612 G10

3612 G09

V

I

= 1.8V

= 100mA

= 1.5V

1µs/DIV

V

I

= 1.8V

= 75mA

= 3.3V

20µs/DIV

OUT

MODE

OUT

MODE

V

3612fa

ꢄ

LTC3612

Typical perForMance characTerisTics ^V_IN= 3.3V, RT/SYNC = SV_IN, unless otherwise noted.

Load Step Transient in

Burst Mode Operation

Load Step Transient in

Pulse-Skipping Mode

V

OUT

200mV/DIV

I

L

1A/DIV

3612 G12

3612 G11

V

I

= 1.8V

50µs/DIV

V

I

= 1.8V

50µs/DIV

OUT

LOAD

OUT

LOAD

= 100mA TO 3A

= 0V

= 100mA TO 3A

= 3.3V

V

MODE

COMPENSATION FIGURE 1

Load Step Transient in Forced

Continuous Mode without AVP Mode

Load Step Transient in Forced

Continuous Mode with AVP Mode

V

OUT

100mV/DIV

V

OUT

200mV/DIV

I

L

1A/DIV

I

L

1A/DIV

3612 G14

V

I

= 1.8V

50µs/DIV

OUT

LOAD

3612 G13

= 100mA TO 3A

= 1.5V

V

I

= 1.8V

50µs/DIV

OUT

LOAD

V

= 100mA TO 3A

= 1.5V

MODE

V

= V

IN

V

ITH

MODE

OUTPUT CAPACITOR VALUE FIGURE 1

COMPENSATION FIGURE 1

Load Step Transient in Forced

Continuous Mode Sourcing and

Sinking Current

V

OUT

20mV/DIV

V

OUT

200mV/DIV

SW

2V/DIV

I

L

0A

2A/DIV

I

L

500mA/DIV

3612 G16

3612 G15

V

I

= 1.2V

= –1A

MODE

1µs/DIV

V

I

= 1.8V

50µs/DIV

OUT

LOAD

= –1.5A TO 3A

= 1.5V

V

= 1.5V

V

MODE

COMPENSATION FIGURE 1

3612fa

ꢅ

LTC3612

Typical perForMance characTerisTics ^V_IN= 3.3V, RT/SYNC = SV_IN, unless otherwise noted.

Tracking Up/Down in

Forced Continuous Mode,

DDR Pin Tied to 0V

Internal Start-Up in Forced

Continuous Mode

RUN

1V/DIV

V

OUT

1V/DIV

V

OUT

500mV/DIV

V

TRACK/SS

500mV/DIV

I

L

1A/DIV

PGOOD

2V/DIV

PGOOD

2V/DIV

3612 G17

V

I

= 1.8V

= 3A

MODE

500µs/DIV

OUT

3612 G18

2ms/DIV

V

= 1.5V

V

= 0V TO 1.8V

= 3A

OUT

I

V

= 0V TO 0.7V

TRACK/SS

= 1.5V

MODE

DDR

= 0V

Tracking Up/Down in Forced

Continuous Mode, DDR Pin Tied

to SV_IN

Reference Voltage

vs Temperature

0.606

0.604

V

OUT

500mV/DIV

V

TRACK/SS

0.602

200mV/DIV

PGOOD

2V/DIV

0.600

0.598

3612 G19

2ms/DIV

V

= 0V TO 1.2V

= 3A

OUT

I

0.596

0.594

V

= 0V TO 0.4V

TRACK/SS

= 1.5V

MODE

DDR

= 3.3V

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

3612 G20

Switch On-Resistance

vs Temperature

Switch On-Resistance

vs Input Voltage

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

MAIN SWITCH

SYNCHRONOUS SWITCH

0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

–50 –30 –10 10 30 50

TEMPERATURE (°C)

130

70 90 110

INPUT VOLTAGE (V)

3612 G21

3612 G22

3612fa

ꢆ

LTC3612

Typical perForMance characTerisTics ^V_IN= 3.3V, RT/SYNC = SV_IN, unless otherwise noted.

Frequency vs Resistor on

Frequency vs Temperature

RT/SYNC Pin

0.8

4500

0.6

4000

0.4

3500

0.2

3000

0

2500

–0.2

2000

1500

1000

500

–0.4

–0.6

–0.8

–1.0

–1.2

0

–50 –30 –10 10 30 50 70 90 100 130

TEMPERATURE (°C)

0

200 400 600

1400

800 1000 1200

RESISTOR ON RT/SYNC PIN (kΩ)

3612 G24

3612 G23

Switch Leakage vs Temperature,

Main Switch

Frequency vs Input Voltage

4000

3500

3000

2500

2000

1500

1000

500

1.0

0.5

V

= 2.25V

= 3.3V

= 5.5V

IN

0

–0.5

–1.0

–1.5

–2.0

0

–2.5

30 50

TEMPERATURE (°C)

–50 –30 –10 10

70 90 110 130

2.25

2.75 3.25

3.75 4.25 4.75 5.25

INPUT VOLTAGE (V)

3612 G26

3612 G25

Dynamic Supply Current vs Input

Voltage without AVP Mode

Switch Leakage vs Temperature,

Synchronous Switch

100

10

1

4000

3500

3000

2500

2000

1500

1000

500

V

= 2.25V

= 3.3V

= 5.5V

IN

FORCED CONTINUOUS MODE

PULSE-SKIPPING MODE

Burst Mode OPERATION

0.1

0

0.01

30 50

TEMPERATURE (°C)

–50 –30 –10 10

70 90 110 130

2.25 2.75 3.25 3.75 4.25 4.75 5.25

INPUT VOLTAGE (V)

3612 G28

3612 G27

3612fa

ꢇ

LTC3612

Typical perForMance characTerisTics ^V_IN= 3.3V, RT/SYNC = SV_IN, unless otherwise noted.

Start-Up from Shutdown with

Dynamic Supply Current vs

Temperature without AVP Mode

V_OUTShort to GND,

Forced Continuous Mode

Prebiased Output

(Forced Continuous Mode)

100

10

1

PGOOD

5V/DIV

V

OUT

1V/DIV

V

OUT

500mV/DIV

FORCED CONTINUOUS MODE

I

L

2A/DIV

I

L

PULSE-SKIPPING MODE

Burst Mode OPERATION

2A/DIV

3612 G30

3612 G31

V

I

= 2.5V

= 0A

MODE

50µs/DIV

20µs/DIV

= 2.2V

OUT

PREBIASED V

OUT

0.1

V

= 1.5V

V

= 1.2V

= 0A

OUT

I

V

= 1.5V

MODE

0.01

–50 –30 –10 10 30 50 70 90 110 130

TEMPERATURE (°C)

3612 G29

Output Voltage During Sinking

vs Input Voltage

Output Voltage During Sinking

vs Input Voltage

1.90

1.88

0.95

V

= 1.8V

V

= 0.9V

OUT

1µH INDUCTOR

0.94

1.86

0.93

1.84

1.82

1.80

1.78

0.92

0.91

0.90

0.89

–1.5A, 2MHz, 120°C

–1.5A, 2MHz, 25°C

–1.5A, 1MHz, 120°C

–1.5A, 1MHz, 25°C

1.76

0.88

2.25

2.75 3.25

3.75 4.25 4.75 5.25

INPUT VOLTAGE (V)

2.75 3.25

3.75 4.25 4.75 5.25

INPUT VOLTAGE (V)

3612 G32

3612 G33

3612fa

ꢈ

LTC3612

pin FuncTions ^(QFN/FE)

DDR (Pin ±/Pin 8): DDR Mode Pin. Tying the DDR pin to

window for more than 105µs the PGOOD pin is released.

If the FB voltage leaves the power good window for more

than 105µs the PGOOD pin is pulled down.

SV selects DDR mode and TRACK/SS can be used as

IN

an external reference input. If DDR is tied to SGND, the

internal 0.6V reference will be used.

InDDRmode(DDR=V ), thepowergoodwindowmoves

IN

RT/SYNC (Pin 2/Pin 9): Oscillator Frequency. This pin

provides three ways of setting the constant switching

frequency:

in relation to the actual TRACK/SS pin voltage. During up/

down tracking the PGOOD pin is always pulled down.

In shutdown the PGOOD output will actively pull down

and may be used to discharge the output capacitors via

an external resistor.

1. Connecting a resistor from RT/SYNC to ground will set

the switching frequency based on the resistor value.

2. Driving the RT/SYNC pin with an external clock signal

will synchronize the LTC3612 to the applied frequency.

Theslopecompensationisautomaticallyadaptedtothe

external clock frequency.

MODE (Pin ±7/Pin 4): Mode Selection. Tying the MODE

pintoSV orSGNDenablespulse-skippingmodeorBurst

IN

Mode operation (with an internal Burst Mode clamp),

respectively. If this pin is held at slightly higher than half

of SV , forced continuous mode is selected. Connecting

IN

3. Tying the RT/SYNC pin to SV enables the internal

IN

this pin to an external voltage selects Burst Mode opera-

tion with the burst clamp set to the pin voltage. See the

Operation section for more details.

2.25MHz oscillator frequency.

SGND (Pin 3/Pin ±0): Signal Ground. All small-signal and

compensationcomponentsshouldconnecttothisground,

which in turn should connect to PGND at a single point.

V

(Pin ±8/Pin 5): Voltage Feedback Input Pin. Senses

FB

the feedback voltage from the external resistive divider

NC (Pins 4, 7, ±0/Pins ±±, ±3, ±8): Can be connected to

ground or left open.

across the output.

ITH (Pin ±9/Pin 6): Error Amplifier Compensation. The

currentcomparator’sthresholdincreaseswiththiscontrol

voltage.TyingthispintoSV_INenablesinternalcompensa-

tion and AVP mode.

SW (Pins 5, 6, ±±, ±2/Pins ±2, ±4, ±7, ±9): Switch Node.

Connection to the inductor. This pin connects to the drains

of the internal synchronous power MOSFET switches.

PV (Pins 8, 9/Pins ±5, ±6): Power Input Supply. PV

IN

TRACK/SS (Pin 20/Pin 7): Track/External Soft-Start/Ex-

ternal Reference. Start-up behavior is programmable with

the TRACK/SS pin:

connects to the source of the internal P-channel power

MOSFET. This pin is independent of SV and may be con-

IN

nected to the same voltage or to a lower voltage supply.

1. Tying this pin to SV selects the internal soft-start

IN

PV

(Pin ±3/Pin 20): Internal Gate Driver Input Sup-

IN_DRV

circuit.

ply. This pin must be connected to PV .

IN

2. External soft-start timing can be programmed with a

SV (Pin ±4/Pin ±): Signal Input Supply. This pin pow-

IN

capacitor to ground and a resistor to SV .

IN

ers the internal control circuitry and is monitored by the

3. TRACK/SS can be used to force the LTC3612 to track

the start-up behavior of another supply.

undervoltage lockout comparator.

RUN (Pin ±5/Pin 2): Enable Pin. Forcing this pin to ground

shuts down the LTC3612. In shutdown, all functions are

disabled and the chip draws <1µA of supply current.

Thepincanalsobeusedasexternalreferenceinput.Seethe

Applications Information section for more information.

PGND (Pin 2±/Pin 2±): Power Ground. The exposed pad

connects to the source of the internal N-channel power

MOSFET. This pin should be connected close to the (–)

PGOOD (Pin ±6/Pin 3): Power Good. This open-drain

output is pulled down to SGND on start-up and while the

FB voltage is outside the power good voltage window. If

the FB voltage increases and stays inside the power good

terminal of C and C

and soldered to PCB ground for

IN

OUT

rated thermal performance.

3612fa

ꢀ0

LTC3612

FuncTional block DiagraM

SV

SGND

RT/SYNC

ITH

PV

IN_DRV

IN

ITH SENSE

COMPARATOR

+

–

BANDGAP

AND

BIAS

RUN

INTERNAL

COMPENSATION

CURRENT

SENSE

OSCILLATOR

SV – 0.3V

IN

R

PMOS CURRENT

COMPARATOR

–

+

ITH

LIMIT

+

–

FOLDBACK

AMPLIFIER

–

+

0.3V

SLOPE

COMPENSATION

ERROR

AMPLIFIER

0.6V

BURST

COMPARATOR

+

–

+

V

FB

SLEEP

DRIVER

+

MODE

TRACK/SS

SOFT-START

SW

0.555V

+

–

LOGIC

REVERSE

+

–

COMPARATOR

+

–

I

REV

0.645V

PGND

PGOOD

EXPOSED PAD

DDR

MODE

3612 BD

3612fa

ꢀꢀ

LTC3612

operaTion

Main Control Loop

Mode Selection

The LTC3612 is a monolithic, constant frequency, current

mode step-down DC/DC converter. During normal opera-

tion, the internal top power switch (P-channel MOSFET) is

turned on at the beginning of each clock cycle. Current in

the inductor increases until the current comparator trips

and turns off the top power switch. The peak inductor cur-

rent at which the current comparator trips is controlled by

the voltage on the ITH pin. The error amplifier adjusts the

voltage on the ITH pin by comparing the feedback signal

The MODE pin is used to select one of four different

operating modes:

Mode Selection Voltage

SV

IN

PS

FC

PULSE-SKIPPING MODE ENABLE

SV – 0.3V

IN

SV • 0.58

IN

FORCED CONTINUOUS MODE ENABLE

1.1V

0.8V

from a resistor divider on the V pin with an internal 0.6V

FB

Burst Mode ENABLE—EXTERNAL CLAMP,

CONTROLLED BY VOLTAGE APPLIED AT

MODE PIN

reference. When the load current increases, it causes a

reduction in the feedback voltage relative to the reference.

The error amplifier raises the ITH voltage until the average

inductor current matches the new load current. Typical

voltage range for the ITH pin is from 0.1V to 1.05V with

0.45V corresponding to zero current.

BM

EXT

0.45V

0.3V

BM

Burst Mode ENABLE—INTERNAL CLAMP

SGND

3612 OP01

Burst Mode Operation—Internal Clamp

Connecting the MODE pin to SGND enables Burst Mode

operation with an internal clamp. In Burst Mode operation

the internal power switches operate intermittently at light

loads. This increases efficiency by minimizing switching

losses. During the intervals when the switches are idle,

the LTC3612 enters sleep state where many of the internal

circuits are disabled to save power. During Burst Mode

operation,theminimumpeakinductorcurrentisinternally

clamped and the voltage on the ITH pin is monitored by

the burst comparator to determine when sleep mode is

enabled and disabled. When the average inductor current

is greater than the load current, the voltage on the ITH pin

drops. As the ITH voltage falls below the internal clamp,

the burst comparator trips and enables sleep mode. Dur-

ing sleep mode, the power MOSFETs are held off and the

load current is solely supplied by the output capacitor.

When the output voltage drops, the top power switch is

turned back on and the internal circuits are re-enabled.

This process repeats at a rate that is dependent on the

load current.

When the top power switch shuts off, the synchronous

power switch (N-channel MOSFET) turns on until either

the bottom current limit is reached or the next clock cycle

begins. The bottom current limit is typically set at –4A for

forced continuous mode and 0A for Burst Mode operation

and pulse-skipping mode.

The operating frequency defaults to 2.25MHz when

RT/SYNCisconnectedtoSV , orcanbesetbyanexternal

IN

resistor connected between the RT/SYNC pin and ground,

orbyaclocksignalappliedtotheRT/SYNCpin.Theswitch-

ing frequency can be set from 300kHz to 4MHz.

Overvoltage and undervoltage comparators pull the

PGOOD output low if the output voltage varies typically

more than 7.5% from the set point.

3612fa

ꢀꢁ

LTC3612

operaTion

Burst Mode Operation—External Clamp

Dropout Operation

ConnectingtheMODEpintoavoltageintherangeof0.45V

to0.8VenablesBurstModeoperationwithexternalclamp.

Duringthismodeofoperationtheminimumvoltageonthe

ITH pin is externally set by the voltage on the MODE pin.

It is recommended to use Burst Mode operation with an

internal clamp for temperatures above 85°C ambient.

Astheinputsupplyvoltageapproachestheoutputvoltage,

the duty cycle increases toward the maximum on-time.

Further reduction of the supply voltage forces the main

switch to remain on for more than one cycle, eventually

reaching 100% duty cycle. The output voltage will then be

determined by the input voltage minus the voltage drop

across the internal P-channel MOSFET and the inductor.

Pulse-Skipping Mode Operation

Low Supply Operation

Pulse-skipping mode is similar to Burst Mode operation,

but the LTC3612 does not disable power to the internal

circuitry during sleep mode. This improves output voltage

ripple but uses more quiescent current, compromising

light load efficiency.

The LTC3612 is designed to operate down to an input

supplyvoltageof2.25V. Animportantconsiderationatlow

input supply voltages is that the R

of the P-channel

DS(ON)

andN-channelpowerswitchesincreases. Theusershould

calculate the power dissipation when the LTC3612 is used

at 100% duty cycle with low input voltages to ensure that

thermal limits are not exceeded. See the Typical Perfor-

mance Characteristics graphs.

Tying theMODE pin to SV enablespulse-skippingmode.

IN

As the load current decreases, the peak inductor current

will be determined by the voltage on the ITH pin until the

ITHvoltagedropsbelowthevoltagelevelcorrespondingto

0A. At this point, the peak inductor current is determined

by the minimum on-time of the current comparator. If the

load demand is less than the average of the minimum on-

time inductor current, switching cycles will be skipped to

keep the output voltage in regulation.

Short-Circuit Protection

Thepeakinductorcurrentatwhichthecurrentcomparator

shuts off the top power switch is controlled by the voltage

on the ITH pin.

Iftheoutputcurrentincreases,theerroramplifierraisesthe

ITH pin voltage until the average inductor current matches

the new load current. In normal operation the LTC3612

clamps the maximum ITH pin voltage at approximately

1.05V which corresponds typically to 6A peak inductor

current.

Forced Continuous Mode

In forced continuous mode the inductor current is con-

stantly cycled which creates a minimum output voltage

ripple at all output current levels.

Connecting the MODE pin to a voltage in the range of

1.1V to SV • 0.58 will enable forced continuous mode

Whentheoutputisshortedtoground,theinductorcurrent

decays very slowly during a single switching cycle. The

LTC3612 uses two techniques to prevent current runaway

from occurring.

IN

operation.

At light loads, forced continuous mode operation is less

efficient than Burst Mode or pulse-skipping operation, but

maybedesirableinsomeapplicationswhereitisnecessary

to keep switching harmonics out of the signal band.

Forced continuous mode must be used if the output is

required to sink current.

3612fa

ꢀꢂ

LTC3612

operaTion

Iftheoutputvoltagedropsbelow50%ofitsnominalvalue,

the clamp voltage at ITH pin is lowered causing the maxi-

mum peak inductor current to decrease gradually with the

output voltage. When the output voltage reaches 0V the

clamp voltage at the ITH pin drops to 40% of the clamp

voltage during normal operation. The short-circuit peak

inductor current is determined by the minimum on-time

of the LTC3612, the input voltage and the inductor value.

This foldback behavior helps in limiting the peak inductor

currentwhentheoutputisshortedtoground.Itisdisabled

duringinternalorexternalsoft-startandtrackingup/down

operation (see the Applications Information section).

A secondary limit is also imposed on the valley inductor

current. If the inductor current measured through the

bottom MOSFET increases beyond 6A typical, the top

power MOSFET will be held off and switching cycles will

be skipped until the inductor current is reduced.

applicaTions inForMaTion

The basic LTC3612 application circuit is shown in Figure 1.

the ramp current that is used to charge and discharge an

internal timing capacitor within the oscillator and can be

calculated by using the following equation:

Operating Frequency

Selectionoftheoperatingfrequencyisatrade-offbetween

efficiency and component size. High frequency operation

allows the use of smaller inductor and capacitor values.

3.82•10¹¹Hz

R_T=

Ω –16kΩ

f_OSCHz

( )

Although frequencies as high as 4MHz are possible, the

minimum on-time of the LTC3612 imposes a minimum

limit on the operating duty cycle. The minimum on-time

is typically 60ns; therefore, the minimum duty cycle is

Operation at lower frequencies improves efficiency by

reducing internal gate charge losses but requires larger

inductance values and/or capacitance to maintain low

output ripple voltage.

equal to 100 • 60ns • f (Hz)%.

OSC

The operating frequency of the LTC3612 is determined

by an external resistor that is connected between the

RT/SYNC pin and ground. The value of the resistor sets

Tying the RT/SYNC pin to SV sets the default internal

IN

operating frequency to 2.25MHz 20%.

V

IN

2.25V TO 5.5V

C

IN2

22µF

IN1

R

SS

22µF

SV

PV

IN

2M

RUN

TRACK/SS

RT/SYNC

PV

IN_DRV

DDR

L1

470nH

C

SS

V

1.8V

3A

OUT

R

T

22nF

LTC3612

SW

SGND

PGND

R

130k

C

OUT2

22µF

OUT1

PGOOD

ITH

15k

47µF

C

R1

392k

MODE

V

FB

C1

C

10pF

470pF

3612 F01

(OPT)

R2

196k

Figure ±. ±.8V, 3A Step-Down Regulator

3612fa

ꢀꢃ

LTC3612

applicaTions inForMaTion

Frequency Synchronization

Inductor Selection

The LTC3612’s internal oscillator can be synchronized to

an external frequency by applying a square wave clock

signaltotheRT/SYNCpin.Duringsynchronization,thetop

switch turn-on is locked to the falling edge of the external

frequency source. The synchronization frequency range

is 300kHz to 4MHz. During synchronization all operation

modes can be selected.

For a given input and output voltage, the inductor value

and operating frequency determine the ripple current. The

ripple current ∆I increases with higher V and decreases

L

IN

with higher inductance:













V_OUT

V_IN

∆I_L=

• 1–









f

•L





SW

It is recommended that the regulator is powered down

(RUN pin to ground) before removing the clock signal

on the RT/SYNC pin in order to reduce inductor current

ripple.

Having a lower ripple current reduces the core losses

in the inductor, the ESR losses in the output capacitors

and the output voltage ripple. A reasonable starting point

for selecting the ripple current is ∆I = 0.3 • I

.

L

OUT(MAX)

AC coupling should be used if the external clock genera-

tor cannot provide a continuous clock signal throughout

start-up, operation and shutdown of the LTC3612. The

The largest ripple current occurs at the highest V . To

IN

guarantee that the ripple current stays below a specified

maximum, theinductorvalueshouldbechosenaccording

to the following equation:

size of capacitor C

depends on parasitic capacitance

SYNC

on the RT/SYNC pin and is typically in the range of 10pF

to 22pF















V_OUT

V_IN

L =

• 1–





f

• ∆I



_L(MAX)

SW

V

IN

LTC3612

SV

f

IN

OSC

The inductor value will also have an effect on Burst Mode

operation. The transition to low current operation begins

whenthepeakinductorcurrentfallsbelowalevelsetbythe

burst clamp. Lower inductor values result in higher ripple

current which causes this to occur at lower load currents.

Thiscausesadipinefficiencyintheupperrangeoflowcur-

rent operation. In Burst Mode operation, lower inductance

values will cause the burst frequency to increase.

2.25MHz

RT/SYNC

V

IN

LTC3612

SV

IN

f

t1/R

T

0.4V

OSC

RT/SYNC

SGND

R

T

V

IN

LTC3612

SV

IN

f

OSC

P

Inductor Core Selection

1/T

RT/SYNC

SGND

Once the value forL is known, the type ofinductor must be

selected. Actual core loss is independent of core size for

fixed inductor value, but it is very dependent on the induc-

tanceselected.Astheinductanceincreases,corelossesde-

crease.Unfortunately,increasedinductancerequiresmore

turns ofwire and therefore, copperlosses willincrease.

1.2V

0.3V

T

P

V

IN

LTC3612

SV

C

SYNC

IN

f

OSC

P

1/T

RT/SYNC

SGND

Ferritedesignshaveverylowcorelossesandarepreferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” meaning that inductance

collapses abruptly when the peak design current is ex-

ceeded. This results in an abrupt increase in inductor

R

T

3612 F02

Figure 2. Setting the Switching Frequency

3612fa

ꢀꢄ

LTC3612

applicaTions inForMaTion

ripple current and consequently output voltage ripple. Do

not allow a ferrite core to saturate!

Table ±. Representative Surface Mount Inductors

INDUCTANCE DCR

MAX

DIMENSIONS

(mm)

HEIGHT

(mm)

(µH) (mΩ) CURRENT (A)

Differentcorematerialsandshapeswillchangethesize/cur-

rent and price/current relationship of an inductor. Toroid

or shielded pot cores in ferrite or permalloy materials are

small and do not radiate much energy, but generally cost

more than powdered iron core inductors with similar

characteristics. The choice of which style inductor to use

mainly depends on the price versus size requirements

and any radiated field/EMI requirements. Table 1 shows

some typical surface mount inductors that work well in

LTC3612 applications.

Vishay IHLP-2525AH-0± Series

0.33

0.47

0.68

0.82

1.0

7

12

11

9

1.8

6.7 × 7

9

13

15

18

8

7

Vishay IHLP-±6±6BZ-0± Series

0.22

0.47

1.00

8

24

11.5

8.5

2

4.3 × 4.7

18

37

Sumida CDMC6D28 Series

Input Capacitor (C ) Selection

0.3

0.47

0.68

1

3.2

4.2

5.4

8.8

15.4

13.6

11.3

8.8

3

6.7 × 7.25

IN

In continuous mode, the source current of the top P-chan-

nel MOSFET is a square wave of duty cycle V /V . To

OUT IN

preventlargevoltagetransients, alowESRcapacitorsized

NEC/Tokin MPLC0730L Series

for the maximum RMS current must be used at V .

IN

0.47

0.75

1.0

4.5

7.5

9.0

16.6

12.2

10.6

3.0

6.9 × 7.7

The maximum RMS capacitor current is given by:





V_OUT

V_IN

Cooper HCP0703 Series

I_RMS=I_OUT(MAX)

•

–1





V





0.22

0.47

0.68

0.82

1.0

2.8

4.2

5.5

8.0

10.0

9.6

23

17

15

13

11

61

3.0

3.2

7 × 7.3

6.9 × 7.3

OUT

This formula has a maximum at V = 2V , where I =

RMS

IN

OUT

I

/2.Thissimpleworst-caseconditioniscommonlyused

OUT

fordesignbecauseevensignificantdeviationsdonotoffer

muchrelief.Notethatripplecurrentratingsfromcapacitor

manufacturers are often based on only 2000 hours of life

which makes it advisable to further derate the capacitor,

or choose a capacitor rated at a higher temperature than

required.Severalcapacitorsmayalsobeparalleledtomeet

size or height requirements in the design.

1.5

Würth Elektronik WE-HC7443±2 Series

0.25

0.47

0.72

1.0

2.5

3.4

18

16

12

11

9

3.8

7 × 7.7

7.5

9.5

1.5

10.5

Output Capacitor (C ) Selection

OUT

Coilcraft DO±8±3H Series

The selection of C

is typically driven by the required

0.33

4

10

5

8.9 × 6.1

OUT

ESR to minimize voltage ripple and load step transients

(low ESR ceramic capacitors are discussed in the next

section). Typically, once the ESR requirement is satisfied,

the capacitance is adequate for filtering. The output ripple

0.56

10

7.7

Coilcraft v Series

0.27

0.35

0.4

0.1

14

11

8

3

7.5 × 6.7

∆V

is determined by:

OUT









1

∆V_OUT≤ ∆I_L• ESR+



8 • f_SW•C

_OUT

3612fa

ꢀꢅ

LTC3612

applicaTions inForMaTion

where f

= operating frequency, C

L

= output capaci-

must instantaneously supply the current to support the

load until the feedback loop raises the switch current

enough to support the load. The time required for the

feedback loop to respond is dependent on the compensa-

tion components and the output capacitor size. Typically,

3 to 4 cycles are required to respond to a load step, but

only in the first cycle does the output drop linearly. The

OSC

OUT

tance and ∆I = ripple current in the inductor. The output

ripple is highest at maximum input voltage since ∆I

increases with input voltage.

L

In surface mount applications, multiple capacitors may

have to be paralleled to meet the capacitance, ESR or RMS

currenthandlingrequirementoftheapplication.Aluminum

electrolytic, special polymer, ceramic and dry tantalum

capacitors are all available in surface mount packages.

output droop, V

, is usually about 2 to 4 times the

DROOP

linear drop of the first cycle; however, this behavior can

vary depending on the compensation component values.

Thus, a good place to start is with the output capacitor

size of approximately:

Tantalumcapacitorshavethehighestcapacitancedensity,

but can have higher ESR and must be surge tested for

use in switching power supplies. Aluminum electrolytic

capacitors have significantly higher ESR, but can often

be used in extremely cost-sensitive applications provided

that consideration is given to ripple current ratings and

long term reliability.

3.5• ∆I_OUT

f_SW• V_DROOP

C_OUT

≈

This is only an approximation; more capacitance may

be needed depending on the duty cycle and load step

requirements.

Ceramic Input and Output Capacitors

Inmostapplications,theinputcapacitorismerelyrequired

to supply high frequency bypassing, since the impedance

to the supply is very low.

Ceramic capacitors have the lowest ESR and can be cost

effective, but also have the lowest capacitance density,

high voltage and temperature coefficients, and exhibit

audible piezoelectric effects. In addition, the high-Q of

ceramic capacitors along with trace inductance can lead

to significant ringing.

Output Voltage Programming

The output voltage is set by an external resistive divider

according to the following equation:

They are attractive for switching regulator use because

of their very low ESR, but great care must be taken when

using only ceramic input and output capacitors.

R1

R2





V_OUT= 0.6 • 1+

V









Ceramic capacitors are prone to temperature effects

which require the designer to check loop stability over

the operating temperature range. To minimize their large

temperature and voltage coefficients, only X5R or X7R

ceramic capacitors should be used.

The resistive divider allows pin V to sense a fraction of

FB

the output voltage, as shown in Figure 1.

Burst Clamp Programming

If the voltage on the MODE pin is less than 0.8V, Burst

Mode operation is enabled.

Whenaceramiccapacitorisusedattheinputandthepower

is being supplied through long wires, such as from a wall

adapter, a load step at the output can induce ringing at the

IfthevoltageontheMODEpinislessthan0.3V,theinternal

defaultburstclamplevelisselected.Theminimumvoltage

on the ITH pin is typically 525mV (internal clamp).

V pin. At best, this ringing can couple to the output and

IN

be mistaken as loop instability. At worst, the ringing at the

input can be large enough to damage the part.

If the voltage is between 0.45V and 0.8V, the voltage on

the MODE pin (V

) is equal to the minimum voltage

BURST

Since the ESR of a ceramic capacitor is so low, the input

and output capacitor must instead fulfill a charge storage

requirement. During a load step, the output capacitor

on the ITH pin (external clamp) and determines the burst

clamp level I (typically from 0A to 3.5A).

BURST

3612fa

ꢀꢆ

LTC3612

applicaTions inForMaTion

When the ITH voltage falls below the internal (or external)

clamp voltage, the sleep state is enabled.

ITH pin allows the transient response to be optimized over

a wide range of output capacitance.

Astheoutputloadcurrentdrops,thepeakinductorcurrent

decreases to keep the output voltage in regulation. When

the output load current demands a peak inductor current

The ITH external components (R and C ) shown in Fig-

C C

ure 1 provide adequate compensation as a starting point

for most applications. The values can be modified slightly

to optimize transient response once the final PCB layout

is done and the particular output capacitor type and value

have been determined. The output capacitors need to be

selected because the various types and values determine

the loop gain and phase. The gain of the loop will be in-

that is less than I

, the burst clamp will force the peak

BURST

inductor current to remain equal to I

further reductions in the load current.

regardless of

BURST

Sincetheaverageinductorcurrentisgreaterthantheoutput

loadcurrent,thevoltageontheITHpinwilldecrease.When

the ITH voltage drops, sleep mode is enabled in which

both power switches are shut off along with most of the

circuitry to minimize power consumption. All circuitry is

turned back on and the power switches resume opera-

tion when the output voltage drops out of regulation. The

creased by increasing R and the bandwidth of the loop

C

will be increased by decreasing C . If R is increased by

C

the same factor that C is decreased, the zero frequency

C

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system. The external capaci-

value for I

is determined by the desired amount of

BURST

output voltage ripple. As the value of I

increases, the

BURST

tor, C , (Figure 1) is not needed for loop stability, but it

C1

sleep period between pulses and the output voltage ripple

increase. Note that for very high V voltage settings,

helps filter out any high frequency noise that may couple

onto that node. The general purpose buck regulator ap-

plication in the Typical Applications section uses a faster

compensation to improve load step response.

BURST

the power good comparator may trip, since the output

ripple may get bigger than the power good window.

Pulse-skippingmode,whichisacompromisebetweenlow

output voltage ripple and efficiency, can be implemented

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

by connecting MODE to SV . This sets I

to 0A. In

IN

BURST

this condition, the peak inductor current is limited by the

minimum on-time of the current comparator. The lowest

output voltage ripple is achieved while still operating

discontinuously. During very light output loads, pulse

skipping allows only a few switching cycles to skip while

maintaining the output voltage in regulation.

with C , causing a rapid drop in V . No regulator can

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. More output

capacitance may be required depending on the duty cycle

and load step requirements.

Internal and External Compensation

AVP Mode

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC load current.

Fast load transient response, limited board space and low

cost are typical requirements of microprocessor power

supplies. A microprocessor has typical full load step with

veryfastslewrate.Thevoltageatthemicroprocessormust

be held to about 0.1V of nominal in spite of these load

current steps. Since the control loop cannot respond this

fast, the output capacitors must supply the load current

until the control loop can respond.

When a load step occurs, V

shifts by an amount equal

OUT

to∆I

,whereESRistheeffectiveseriesresistance

LOAD(ESR)

of C . ∆I

also begins to charge or discharge C

,

OUT

LOAD

OUT

generatingthefeedbackerrorsignalthatforcestheregula-

tor to adapt to the current change and return V to its

OUT

steady-state value. During this recovery time V

can

be monitored for excessive overshoot or ringing, which

Normally, several capacitors in parallel are required to

meet microprocessor transient requirements. Capacitor

would indicate a stability problem. The availability of the

3612fa

ꢀꢇ

LTC3612

applicaTions inForMaTion

ESR and ESL primarily determine the amount of droop or

overshoot in the output voltage.

output voltage can have more overshoot and stay within

the specified voltage range (see Figures 3 and 4).

Thebenefitisalowerpeak-to-peakoutputvoltagedeviation

for a given load step without having to increase the output

filtercapacitance.Alternatively,theoutputvoltagefilterca-

pacitancecanbereducedwhilemaintainingthesamepeak

to peak transient response. Due to the reduced loop gain

in AVP mode, no external compensation is required.

ConsidertheLTC3612withoutAVPwithabankoftantalum

output capacitors. If a load step with very fast slew rate

occurs, the voltage excursion will be seen in both direc-

tions, for full load to minimum load transient and for the

minimum load to full load transient.

If the ITH pin is tied to SV , the active voltage positioning

IN

(AVP) mode and internal compensation are selected.

DDR Mode

AVP mode intentionally compromises load regulation by

reducing the gain of the feedback circuit, resulting in an

outputvoltagethatvarieswithloadcurrent. Whentheload

currentsuddenlyincreases, theoutputvoltagestartsfrom

a level slightly higher than nominal so the output voltage

can droop more and stay within the specified voltage

range. When the load current suddenly decreases the

output voltage starts at a level lower than nominal so the

TheLTC3612canbothsourceandsinkcurrentiftheMODE

pin is configured to forced continuous mode.

Current sinking is typically limited to 1.5A, for 1MHz

frequency and a 1µH inductor, but can be lower at higher

frequenciesandlowoutputvoltages.Ifhigherripplecurrent

can be tolerated, smaller inductor values can increase the

sink current limit. See the Typical Performance Charac-

teristics curves for more information.

In addition, tying the DDR pin to SV , lower external

IN

V

OUT

reference voltage and tracking output voltage between

channels are possible. See the Output Voltage Tracking

and External Reference Input sections.

200mV/DIV

I

L

1A/DIV

Soft-Start

3612 F03

V

= 3.3V

50µs/DIV

IN

The RUN pin provides a means to shut down the LTC3612.

Tying the RUN pin to SGND places the LTC3612 in a low

quiescent current shutdown state (I < 1µA).

= 1.8V

OUT

I

= 100mA TO 3A

= 1.5V

LOAD

V

MODE

COMPENSATION FIGURE 1

Q

Figure 3. Load Step Transient Forced Continuous Mode

(AVP Inactive)

The LTC3612 is enabled by pulling the RUN pin high.

However, the applied voltage must not exceed SV . In

IN

some applications, the RUN signal is generated within

another power domain and is driven high while the SV

IN

V

OUT

and PV is still 0V. In this case, it’s required to limit the

IN

100mV/DIV

current into the RUN pin by either adding a 1MΩ resistor

I

L

or a 100kΩ resistor, plus a Schottky diode, to SV . After

IN

1A/DIV

pulling the RUN pin high, the chip enters a soft start-up

state. This type of soft start-up behavior is set by the

TRACK/SS pin:

3612 F04

V

LOAD

= 3.3V

50µs/DIV

IN

= 1.8V

OUT

I

= 100mA TO 3A

1. Tying TRACK/SS to SV selects the internal soft-start

IN

V

= 1.5V

MODE

circuit. This circuit ramps the output voltage to the final

= 3.3V

ITH

OUTPUT CAPACITOR VALUE FIGURE 1

value within 1ms.

Figure 4. Load Step Transient Forced Continuous Mode

with AVP Mode

2. If a longer soft-start period is desired, it can be set ex-

ternally with a resistor and capacitor on the TRACK/SS

3612fa

ꢀꢈ

LTC3612

applicaTions inForMaTion

pin, as shown in Figure 1. The TRACK/SS pin reduces

V

OUT1

OUT2

thevalueoftheinternalreferenceatV untilTRACK/SS

FB

is pulled above 0.6V. The external soft-start duration

can be calculated by using the following formula:













SV

IN

t_SS=R_SS•C_SS•ln

SV – 0.6V

IN

3. The TRACK/SS pin can be used to track the output

voltage of another supply.

TIME

(5a) Coincident Tracking

Each time the RUN pin is tied high and the LTC3612 is

turned on, the TRACK/SS pin is internally pulled down

for ten microseconds in order to discharge the external

capacitor. This discharging time is typically adequate

for capacitors up to about 33nF. If a larger capacitor is

required, connect the external soft-start resistor to the

RUN pin.

V

OUT1

OUT2

Regardless of either internal or external soft-start state,

the MODE pin is ignored and soft-start will always be

in pulse-skipping mode. In addition, the PGOOD pin

is kept low and foldback of the switching frequency is

disabled.

3612 F05

TIME

(5b) Ratiometric Tracking

Figure 5. Two Different Modes of Output Voltage Tracking

Output Voltage Tracking Input

If the DDR pin is not tied to SV , once V

0.6V,therunstateisenteredandtheMODEselection,power

good and current foldback circuits are enabled.

exceeds

IN

TRACK/SS

To implement the coincident tracking behavior in Fig-

ure 5a, connect an extra resistive divider to the output

of the master channel and connect its midpoint to the

TRACK/SS pin for the slave channel. The ratio of this

divider should be selected to be the same as that of the

slavechannel’sfeedbackdivider(Figure 6a).Inthistrack-

ing mode, the master channel’s output must be set higher

than slave channel’s output. To implement the ratiometric

tracking behavior in Figure 5b, different resistor divider

values must be used as specified in Figure 6b.

In the run state, the TRACK/SS pin can be used for track-

ing down/up the output voltage of another supply. If the

V

drops below 0.6V, the LTC3612 enters the down

TRACK/SS

trackingstateandV isreferencedtotheTRACK/SSvolt-

OUT

age. If the TRACK/SS pin drops below 0.2V, the switching

frequency is reduced to ensure that the minimum duty

cycle limit does not prevent the output from following

the TRACK/SS pin. The run state will resume if V

TRACK/SS

Forcoincidentstart-up, thevoltagevalueattheTRACK/SS

pin for the slave channel needs to reach the final reference

value after the internal soft-start time (around 1ms). The

master start-up time needs to be adjusted with an external

capacitor and resistor to ensure this.

again exceeds 0.6V and V

is referenced to the internal

OUT

precision reference (see Figure 7).

Through the TRACK/SS pin, the output voltage can be set

up for either coincident or ratiometric tracking, as shown

in Figure 5.

3612fa

ꢁ0

LTC3612

applicaTions inForMaTion

V

OUT1

where L1, L2, etc. are the individual losses as a percent-

age of input power.

V

OUT2

R4

R3

R2

Although all dissipative elements in the circuit produce

V

IN

V

FB1

FB2

losses, two main sources usually account for most of

R2

LTC3612

TRACK/SS2

LTC3612

TRACK/SS1

2

the losses: V quiescent current and I R losses. The V

IN

R4 ≤ R3

quiescent current loss dominates the efficiency loss at

2

3612 F06a

very low load currents whereas the I R loss dominates

LTC3612 CHANNEL 2

SLAVE

LTC3612 CHANNEL 1

MASTER

the efficiency loss at medium to high load currents. In a

typical efficiency plot, the efficiency curve at very low load

currents can be misleading since the actual power lost is

usually of no consequence.

Figure 6a. Set-Up for Coincident Tracking

V

OUT1

V

OUT2

1. TheV quiescentcurrentisduetotwocomponents:the

R1

R5

R3 R1/R2 < R5/R6

IN

DCbiascurrentasgivenintheElectricalCharacteristics

and the internal main switch and synchronous switch

gate charge currents. The gate charge current results

fromswitchingthegatecapacitanceoftheinternalpower

MOSFET switches. Each time the gate is switched from

low to high to low again, a packet of charge dQ moves

V

FB1

FB2

R2

R6

R4

LTC3612

TRACK/SS2

LTC3612

TRACK/SS1

V

IN

LTC3612 CHANNEL 2

SLAVE

LTC3612 CHANNEL 1

MASTER

3612 F06b

Figure 6b. Set-Up for Ratiometric Tracking

from V to ground. The resulting dQ/dt is the current

IN

out of V due to gate charge, and it is typically larger

External Reference Input (DDR Mode)

If the DDR pin is tied to SV (DDR mode), the run state

is entered when V

down behavior is possible if the V

below 0.6V.

IN

than the DC bias current. Both the DC bias and gate

IN

chargelossesareproportionaltoV ;thus, theireffects

IN

exceeds 0.3V and tracking

TRACK/SS

will be more pronounced at higher supply voltages.

voltage is

TRACK/SS

2

2. I R losses are calculated from the resistances of the

internal switches, R , and external inductor, R . In

SW

L

This allows TRACK/SS to be used as an external reference

between 0.3V and 0.6V if desired. During the run state in

DDR mode, the power good window moves in relation

to the actual TRACK/SS pin voltage if the voltage value

is between 0.3V and 0.6V. Note: if TRACK/SS voltage is

0.6V, either the tracking circuit or the internal reference

can be used.

continuous mode the average output current flowing

through inductor L is “chopped” between the main

switch and the synchronous switch. Thus, the series

resistance looking into the SW pin is a function of both

top and bottom MOSFET R

(DC) as follows:

and the duty cycle

DS(ON)

R

= (R )(DC) + (R )(1 – DC)

DS(ON)TOP DS(ON)BOT

SW

During up/down tracking the output current foldback is

disabled and the PGOOD pin is always pulled down (see

Figure 8).

The R

for both the top and bottom MOSFETs can

DS(ON)

be obtained from the Typical Performance Character-

2

istics curves. To obtain I R losses, simply add R to

SW

Efficiency Considerations

R and multiply the result by the square of the average

L

output current.

Theefficiencyofaswitchingregulatorisequaltotheoutput

power divided by the input power times 100%. It is often

useful to analyze individual losses to determine what is

limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as:

Other losses including C and C

ESR dissipative

OUT

IN

losses and inductor core losses generally account for

less than 2% of the total loss.

Efficiency = 100% – (L1 + L2 + L3 + ...)

3612fa

ꢁꢀ

LTC3612

applicaTions inForMaTion

0.6V

V

FB

VOLTAGE

0V

0.6V

TRACK/SS

PIN VOLTAGE

0.2V

0V

V

IN

RUN PIN

VOLTAGE

0V

V

IN

SV PIN

IN

VOLTAGE

0V

TIME

SHUTDOWN SOFT-START

RUN STATE

REDUCED

SWITCHING

FREQUENCY

RUN STATE

STATE

> 1ms

3612 F07

t

SS

DOWN

TRACKING TRACKING

STATE STATE

UP

Figure 7. DDR Pin Not Tied to S_VIN

0.45V

0.3V

V

FB

VOLTAGE

0V

EXTERNAL

VOLTAGE

REFERENCE 0.45V

0.45V

0.3V

TRACK/SS

PIN VOLTAGE

0.2V

0V

V

IN

RUN PIN

VOLTAGE

0V

V

IN

SV PIN

IN

VOLTAGE

0V

TIME

SHUTDOWN SOFT-START

STATE STATE

> 1ms

RUN STATE

REDUCED

SWITCHING

FREQUENCY

RUN STATE

3612 F08

t

SS

DOWN

TRACKING

STATE

UP

TRACKING

STATE

Figure 8. DDR Pin Tied to SV_IN. Example DDR Application

3612fa

ꢁꢁ

LTC3612

applicaTions inForMaTion

Thermal Considerations

Note that for very low input voltage, the junction tempera-

ture will be higher due to increased switch resistance,

DS(ON)

Inmostapplications,theLTC3612doesnotdissipatemuch

heat due to its high efficiency.

R

. It is not recommended to use full load current

for high ambient temperature and low input voltage.

However, in applications where the LTC3612 is running at

highambienttemperaturewithlowsupplyvoltageandhigh

duty cycles, such as in dropout, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 160°C,

both power switches will be turned off and the SW node

will become high impedance.

To maximize the thermal performance of the LTC3612 the

Exposed Pad should be soldered to a ground plane. See

the PCB Layout Board Checklist.

Design Example

As a design example, consider using the LTC3612 in an

application with the following specifications:

To prevent the LTC3612 from exceeding the maximum

junction temperature, some thermal analysis is required.

The temperature rise is given by:

V = 2.25V to 5.5V, V

= 1.8V, I

= 3A, I

OUT(MAX) OUT(MIN)

IN

OUT

= 100mA, f = 2.6MHz.

Efficiency is important at both high and low load current,

so Burst Mode operation will be utilized.

T

= (P )(θ )

D JA

RISE

where P is the power dissipated by the regulator and θ

D

JA

First, calculate the timing resistor:

is the thermal resistance from the junction of the die to

the ambient temperature. The junction temperature, T ,

J

3.82•10¹¹Hz

is given by:

R_T=

Ω –16kΩ=130kΩ

2.6MHz

T = T + T

J RISE

A

Next, calculate the inductor value for about 30% ripple

where T is the ambient temperature.

A

current at maximum V :

IN

As an example, consider the case when the LTC3612 is in

dropout at an input voltage of 3.3V with a load current of

3A at an ambient temperature of 70°C. From the Typical

Performance Characteristics graph of Switch Resistance,

1.8V

2.6MHz •1A

1.8V

5.5V



 



L =

• 1–

= 0.466µH





 

 





Using a standard value of 0.47µH inductor results in a

maximum ripple current of:

the R

resistance of the P-channel switch is 0.075Ω.

DS(ON)

Therefore, power dissipated by the part is:

2



1.8V

2.6MHz•0.47µH



1.8V

5.5V

P = (I ) • R

= 675mW





D

OUT

DS(ON)

∆I_L=

• 1–

= 0.99A

















For the QFN package, the θ is 43°C/W.

JA

Therefore,thejunctiontemperatureoftheregulatoroperat-

ing at 70°C ambient temperature is approximately:

C

will be selected based on the ESR that is required to

OUT

satisfy the output voltage ripple requirement and the bulk

capacitance needed for loop stability. For this design, a

68µF (or 47µF plus 22µF) ceramic capacitor is used with

a X5R or X7R dielectric.

T = 0.675W • 43°C/W + 70°C = 99°C

J

Wecansafelyassumethattheactualjunctiontemperature

will not exceed the absolute maximum junction tempera-

ture of 125°C.

3612fa

ꢁꢂ

LTC3612

applicaTions inForMaTion

C should be sized for a maximum current rating of:

IN

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3612:

1.8V

3.6V

1.8V





I_RMS= 3A •

•

–1 =1.5A







RMS



1. Agroundplaneisrecommended.Ifagroundplanelayer

is not used, the signal and power grounds should be

segregated with all small-signal components returning

to the SGND pin at one point which is then connected

to the PGND pin close to the LTC3612.

DecouplingthePV withtwo22µFcapacitors, isadequate

IN

for most applications.

IfwesetR2=196k, thevalueofR1cannowbedetermined

by solving the following equation.

1.8V

0.6V





2. Connect the (+) terminal of the input capacitor(s), C ,

R1 = 196k •

−1



IN







ascloseaspossibletothePV pin, andthe(–)terminal

IN

as close as possible to the exposed pad, PGND. This

capacitorprovidestheACcurrentintotheinternalpower

MOSFETs.

A value of 392k will be selected for R1.

Finally, define the soft start-up time choosing the proper

value for the capacitor and the resistor connected to

3. Keep the switching node, SW, away from all sensitive

small-signal nodes.

TRACK/SS. If we set minimum t = 5ms and a resistor

SS

of 2M, the following equation can be solved with the

4. Flood all unused areas on all layers with copper. Flood-

ing with copper will reduce the temperature rise of

powercomponents. ConnectthecopperareastoPGND

(exposed pad) for best performance.

maximum SV = 5.5V :

IN

5ms

5.5V

5.5V – 0.6V

C_SS=

= 21.6nF





2M•In









5. Connect the V pin directly to the feedback resistors.

FB

The resistor divider must be connected between V

and SGND.

OUT

The standard value of 22nF guarantees the minimum

soft-start up time of 5ms.

Figure 1 shows the schematic for this design example.

3612fa

ꢁꢃ

LTC3612

Typical applicaTions

General Purpose Buck Regulator Using Ceramic Capacitors, 2.25MHz

V

IN

2.25V TO 5.5V

C2

22µF

C1

22µF

R

F

24Ω

C

F

1µF

SV

RUN

TRACK/SS

RT/SYNC

PV

IN

R

IN

SS

4.7M

PV

IN_DRV

DDR

C

SS

L1

10nF

470nH

LTC3612

V

R4

100k

OUT

SW

SGND

PGND

1.8V

R

C

O2

3A

O1

PGOOD

ITH

MODE

43k

47µF

22µF

C

C1

10pF

C

R5A

1M

R1

392k

V

FB

220pF

C3

22pF

R2

196k

R5B

1M

3612 TA02a

L1: VISHAY IHLP-2020BZ 0.47µH

Efficiency vs Output Current

Load Step Response in Forced Continuous Mode

100

90

80

70

60

50

40

30

20

10

0

V

OUT

100mV/DIV

I

OUT

1A/DIV

V

= 2.5V

= 3.3V

= 4V

IN

3612 TA02c

V

= 3.3V

20µs/DIV

IN

= 1.8V

OUT

= 5.5V

I

= 100mA TO 3A

= 1.5V

V

MODE

1

10

100

1000

10000

OUTPUT CURRENT (mA)

3612 TA02b

3612fa

ꢁꢄ

LTC3612

Typical applicaTions

Master and Slave for Coincident Tracking Outputs Using a ±MHz External Clock

V

IN

2.25V TO 5.5V

C2

22µF

C1

22µF

R

F1

4.7M

10nF

24Ω

C

F1

1µF

SV

PV

IN

RUN

TRACK/SS

RT/SYNC

PV

IN_DRV

DDR

CHANNEL 1

MASTER

1MHz

CLOCK

L1

1µH

LTC3612

V

1.8V

3A

OUT1

R5

100k

SW

SGND

PGND

R

C1

C

O12

22µF

O11

PGOOD

ITH

MODE

15k

47µF

C

C2

10pF

C1

R1

V

FB

4.7M

R3

470pF

715k

464k

C3

22pF

R2

357k

R4

464k

C5

22µF

C6

22µF

R

F2

24Ω

C

F2

1µF

SV

PV

IN

RUN

TRACK/SS

RT/SYNC

PV

IN_DRV

DDR

CHANNEL 2

SLAVE

L2

1µH

LTC3612

V

1.2V

3A

OUT2

R7

100k

SW

SGND

PGND

R

C2

C

O22

22µF

O21

PGOOD

ITH

15k

47µF

C

C3

C4

R5

301k

MODE

V

FB

470pF

10pF

C7

22pF

R6

301k

3612 TA03a

Coincident Start-Up

Coincident Tracking Up/Down

V

OUT1

OUT2

V

OUT1

500mV/DIV

V

OUT2

3612 TA03b

3612 TA03c

2ms/DIV

200ms/DIV

3612fa

ꢁꢅ

LTC3612

package DescripTion

UDC Package

20-Lead Plastic QFN (3mm × 4mm)

(Reference LTC DWG # 05-08-1742 Rev Ø)

0.70 0.05

3.50 0.05

2.ꢀ0 0.05

2.65 0.05

ꢀ.50 REF

ꢀ.65 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

2.50 REF

3.ꢀ0 0.05

4.50 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN ꢀ NOTCH

R = 0.20 OR 0.25

0.75 0.05

s 45° CHAMFER

ꢀ.50 REF

ꢀ9 20

R = 0.05 TYP

3.00 0.ꢀ0

0.40 0.ꢀ0

ꢀ

2

PIN ꢀ

TOP MARK

(NOTE 6)

2.65 0.ꢀ0

ꢀ.65 0.ꢀ0

4.00 0.ꢀ0

2.50 REF

(UDC20) QFN ꢀꢀ06 REV Ø

0.200 REF

0.00 – 0.05

0.25 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

R = 0.ꢀꢀ5

TYP

NOTE:

ꢀ. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3612fa

ꢁꢆ

LTC3612

package DescripTion

FE Package

20-Lead Plastic eTSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663 Rev G)

Exposed Pad Variation CB

6.40 – 6.60*

3.86

(.152)

(.252 – .260)

3.86

(.152)

20 1918 17 16 15 14 1312 11

6.60 p0.10

2.74

(.108)

4.50 p0.10

6.40

(.252)

BSC

2.74

(.108)

SEE NOTE 4

0.45 p0.05

1.05 p0.10

0.65 BSC

5

7

8

1

2

3

4

6

9 10

RECOMMENDED SOLDER PAD LAYOUT

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0o – 8o

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.195 – 0.30

FE20 (CB) eTSSOP REV G 0510

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

3612fa

ꢁꢇ

LTC3612

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

08/10 Updated Temperature Range in Order Information

Edited Electrical Characteristics table and updated Note 2

Updated text in graphs G19, G31

2

3, 4

7, 9

10

11

13

18

19

23

25

30

Updated Pin 16/Pin 3 and Pin 21/Pin 21 text

Updated Functional Block Diagram

Updated Burst Mode Operation—External Clamp section

Updated Internal and External Compensation section

Updated Soft-Start section

Updated Timing Resistor equation in Design Example section

Updated TA02a and TA02c in Typical Applications

Updated Related Parts

3612fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

ꢁꢈ

LTC3612

Typical applicaTion

DDR Termination with Ratiometric Tracking of V_DD, ±MHz

V

IN

3.3V

C1

22µF

C2

22µF

SV

PV

IN

RUN

TRACK/SS

RT/SYNC

PV

IN_DRV

DDR

V

DD

1.8V

R6

562k

R3

100k

R8

365k

L1

LTC3612

1µH

V

TT

R7

187k

PGOOD

SW

0.9V

1.5A

C4

C5

47µF

R

C

100µF

SGND

PGND

6k

ITH

MODE

C

C1

10pF

C

R1

200k

V

FB

2.2nF

R4

1M

C3

22pF

R2

200k

R5

1M

L1: COILCRAFT DO3316T

3612 TA04a

Ratiometric Start-Up

V

DD

V

TT

500mV/DIV

3612 TA04b

500µs/DIV

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

95% Efficiency, V : 2.25V to 5.5V, V

LTC3614

LTC3616

LTC3601

LTC3603

LTC3605

LTC3412A

LTC3413

5.5V, 4A (I ), 4MHz, Synchronous Step-Down DC/DC

= 0.6V, I = 75µA,

Q

OUT

IN

OUT(MIN)

Converter with Tracking and DDR

I

< 1µA, 3mm × 5mm QFN-24 Package

SD

5.5V, 6A (I ), 4MHz, Synchronous Step-Down DC/DC

95% Efficiency, V : 2.25V to 5.5V, V

= 0.6V, I = 75µA,

Q

OUT

IN

Converter with Tracking and DDR

I

< 1µA, 3mm × 5mm QFN-24 Package

SD

15V, 1.5A (I ), Synchronous Step-Down DC/DC Converter 95% Efficiency, V : 4.5V to 15V, V

= 0.6V, I = 300µA,

Q

OUT

IN

OUT(MIN)

I

< 1µA, MSOP-16E and 3mm × 3mm QFN-16 Packages

SD

15V, 2.5A, Synchronous Step-Down DC/DC Converter

92% Efficiency, V : 4.5V to 15V, V

= 0.6V, I = 75µA, I < 1µA,

IN

OUT(MIN) Q SD

4mm × 4mm QFN-16 Package

15V, 5A (I ), Synchronous Step-Down DC/DC Converter

95% Efficiency, V : 4V to 15V, V

= 0.6V, I = 2mA, I < 15µA,

OUT

IN

OUT(MIN) Q SD

4mm × 4mm QFN-24 Package

5.5V, 3A (I ), 4MHz, Synchronous Step-Down

95% Efficiency, V : 2.25V to 5.5V, V

SD

= 0.8V, I = 60µA,

Q

OUT

IN

OUT(MIN)

DC/DC Converter

I

< 1µA, TSSOP-16E and 4mm × 4mm QFN-16 Packages

5.5V, 3A (I

Sink/Source), 2MHz, Monolithic Synchronous 90% Efficiency, V : 2.25V to 5.5V, V

= V /2, I = 280µA,

REF Q

OUT

IN

Regulator for DDR/QDR Memory Termination

I

SD

< 1µA, TSSOP-16E Package

3612fa

LT 0810 REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

ꢂ0

●

 LINEAR TECHNOLOGY CORPORATION 2009

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3612EUDC#PBF
厂家：	Linear
描述：	LTC3612 - 3A, 4MHz Monolithic Synchronous Step-Down DC/DC Converter; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C 开关输出元件
文件：	总30页 (文件大小：2436K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3612EUDC#PBF [Linear]

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