LTC3615EUF-TRPBF_技术文档

LTC3615

Dual 4MHz, 3A Synchronous

Step-Down DC/DC Converter

DescripTion

FeaTures

TheLTC^®3615isadual3Asynchronousstep-downregula-

torusingacurrentmode,constant-frequencyarchitecture.

TheDCsupplycurrentisonly130µA(BurstModeoperation

at no-load) while maintaining the output voltages, drop-

ping to zero current in shutdown. The 2.25V to 5.5V input

supply range makes the LTC3615 ideally suited for single

Li-Ion applications. 100% duty cycle capability provides

low dropout operation, which extends operating time in

battery-operated systems.

n

High Efﬁciency: Up to 94%

n

Dual Outputs with 2 × 3A Output Current Capability

Low Output Ripple Burst Mode^®Operation:I = 130µA

n

Q

n

2.25V to 5.5V Input Voltage Range

n

1% Output Voltage Accuracy

n

Output Voltages Down to 0.6V

n

Programmable Slew Rate at Switch Pins

n

Low Dropout Operation: 100% Duty Cycle

n

Shutdown Current ≤1µA

n

Adjustable Switching Frequency Up to 4MHz

The operating frequency is externally programmable up to

4MHz, allowing the use of small surface mount inductors.

0°, 90°, or 180° of phase shift between the two channels

can be selected to minimize input current ripple and

output voltage ripple in a single 6A output conﬁguration.

ProgrammableslewratelimitingreducesEMI,andexternal

synchronization can be applied up to 4MHz.

n

Internal or External Compensation

n

Selectable Pulse-Skipping/Forced Continuous/

Burst Mode Operation with Adjustable Burst Clamp

n

Optional Active Voltage Positioning (AVP) with

Internal Compensation

n

Selectable 0°/90°/180° Phase Shift Between Channels

Fixed Internal and Programmable External Soft-Start

n

The internal synchronous switches increase efﬁciency

and eliminate the need for external catch diodes, saving

external components and board space.

Accurate Start-Up Tracking Capability

DDR Memory Mode I = 1.5A

OUT

Availablein 4mm×4mm QFN-24andTSSOP-24Packages

The LTC3615 is offered in leadless 24-pin 4mm × 4mm

applicaTions

QFN and thermally enhanced 24-pin TSSOP packages.

n

Point-of-Load Supplies

L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks

of Linear Technology Corporation. All other trademarks are the property of their respective

owners. Protected by U.S. Patents, including 5481178, 5994885, 6304066, 6498466, 6580258,

6611131.

n

Distributed Power Supplies

n

Portable Computer Systems

DDR Memory Termination

n

Handheld Devices

Efﬁciency and Power Loss vs Load Current

Typical applicaTion

100

90

80

70

60

50

40

30

20

10

0

10

V

IN

100µF

SV

IN

RUN1

PV

IN1

PV

IN2

SW1

0.47µH

V

1

OUT1

1.8V/3A

TRACK/SS1

PGOOD1

ITH1

47µF

422k

210k

0.1

LTC3615

FB1

SRLIM

R /SYNC

T

0.01

0.001

0.0001

MODE

V

OUT2

2.5V/3A

SW2

PHASE

47µF

RUN2

665k

210k

V

= 3.3V

= 4V

= 5V

IN

TRACK/SS2

PGOOD2

2.25MHz

= 2.5V

FB2

V

OUT

ITH2 SGND PGND

0.001

0.01

0.1

1

3615 TA01a

OUTPUT CURRENT (A)

3615 TA01b

3615f

ꢀ

LTC3615

absoluTe MaxiMuM raTings

(Note 1)

PV , PV Voltages.....................–0.3V to SV + 0.3V

Operating Junction Temperature

IN1

IN2

IN

SV Voltage................................................. –0.3V to 6V

Range (Note 2).......................................–40°C to 125°C

Storage Temperature..............................–65°C to 150°C

Lead Soldering Temperature (TSSOP) .................. 300°C

Reﬂow Peak Body Temperature (QFN).................. 260°C

IN

SW1 Voltage .............................–0.3V to (PV + 0.3V)

IN1

SW2 Voltage ..............................–0.3V to (PV + 0.3V)

IN2

PGOOD1, PGOOD2 Voltages........................ –0.3V to 6V

All Other Pins.............................. –0.3V to (SV + 0.3V)

IN

pin conFiguraTion

TOP VIEW

1

2

MODE

FB1

24

23

22

21

20

19

18

17

16

15

14

13

PHASE

FB2

3

ITH1

24 23 22 21 20 19

ITH2

4

TRACK/SS1

TRACK/SS2

SGND

ITH1

FB1

1

2

3

4

5

6

18 PGOOD1

5

SV

IN

SRLIM

17

16

25

PGND

MODE

PHASE

FB2

PGOOD2

6

PV

IN1

PV

IN2

25

PGND

15 R /SYNC

7

PV

IN1

PV

IN2

T

14

RUN1

8

SW1

SW2

ITH2

13 RUN2

9

SW1

10

11

12

PGOOD1

SRLIM

PGOOD2

7

8

9 10 11 12

RUN2

RUN1

R /SYNC

T

FE PACKAGE

24-LEAD PLASTIC TSSOP

UF PACKAGE

24-LEAD (4mm s 4mm) PLASTIC QFN

T

= 125°C, θ = 33°C/W

JA

JMAX

T

= 125°C, θ = 37°C/W

JMAX JA

EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

LTC3615EFE#PBF

LTC3615IFE#PBF

LTC3615EUF#PBF

LTC3615IUF#PBF

TAPE AND REEL

PART MARKING*

LTC3615FE

3615

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3615EFE#TRPBF

LTC3615IFE#TRPBF

LTC3615EUF#TRPBF

LTC3615IUF#TRPBF

24-Lead Plastic TSSOP

–40°C to 125°C

24-Lead Plastic TSSOP

24-Lead (4mm × 4mm) Plastic QFN

3615

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

3615f

ꢁ

LTC3615

elecTrical characTerisTics ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_A= 25°C (Note 2), SV_IN= PV_INx= 3.3V, R_T= 178k, R_SRLIM= 40.2k, unless

otherwise speciﬁed (Notes 1, 2, 11).

SYMBOL

PARAMETER

CONDITIONS

MIN

2.25

1.7

TYP

MAX

UNITS

l

V

Operating Voltage Range

Undervoltage Lockout Threshold

5.5

V

IN

SV Ramping Down

IN

UVLO

SV Ramping Up

IN

2.25

V

Feedback Voltage Internal Reference (Note 3) V

= SV , V

= 0V

FB

TRACK

IN SRLIM

0°C < T < 85°C

0.592

0.590

0.6

0.608

0.610

V

J

l

–40°C < T < 125°C

J

Feedback Voltage External Reference (Note 3) V

= 0.3V, V

= SV

0.289

0.489

0.3

0.5

0

0.311

0.511

30

V

TRACK

SRLIM

IN

(Note 7)

(Note 3) V

= 0.5V, V

IN

l

I

FB

Feedback Input Current

Line Regulation

V

= 0.6V

FBx

nA

∆V

LINEREG

SV = PV = 2.25V to 5.5V (Note 4)

0.2

%/V

IN

INx

∆V

LOADREG

Load Regulation

V

from 0.5V to 0.9V (Note 4)

0.2

2

%

ITHx

= SV , V = 0.6V (Note 5)

IN FBx

I

Active Mode

Sleep Mode

V

= 0.5V, V

= SV , V = 0V (Note 6)

IN RUN2

1100

1900

95

µA

S

FB1

MODE

RUN1

= 0.5V, V

= SV , V

= SV (Note 6)

FBx

IN RUNx

IN

V

= 0.7V, V

= SV , V

= 0V,

=0V,

130

220

200

360

1

FB1

MODE

IN RUN2

= 0V, V

= SV (Note 5)

ITH1

IN

V

= 0.7V, V

MODE

= SV , V

IN RUN2

145

130

240

µA

FBx

RUN1

= 0V (Note 4)

V

= 0.7V, V

= SV , V

RUNx IN MODE

FBx

= SV (Note 5)

ITHx

IN

V

= 0.7V, V = SV , V

RUNx IN MODE

= (Note 4)

FBx

I

TH

Shutdown

SV = PV = 5.5V, V = 0V

RUNx

0.1

75

55

µA

mΩ

IN

R

Top Switch On-Resistance

Bottom Switch On-Resistance

Top Switch Current Limit

PV = 3.3V (Note 10)

INx

DS(ON)

PV = 3.3V (Note 10)

INx

I

Sourcing (Note 8), V = 0.5V

LIM

FB

Duty Cycle <35%

4.5

3.6

6

7.5

–5

1

A

Duty Cycle = 100%

Bottom Switch Current Limit

Sinking (Note 8), V = 0.7V,

Forced Continuous Mode

–2.5

–3.5

A

FB

I

Switch Leakage Current

SV = PV = 5.5V, V = 0V

RUNx

0.01

240

30

µA

µmho

µA

SW(LKG)

IN

g

Error Ampliﬁer Transconductance

Error Ampliﬁer Output Current

Internal Soft-Start Time

–5µA < I < 5µA

m(EA)

TH

I

t

(Note 4)

EAO

V

from 0.06V to 0.54V, TRACK/SSx = SV

IN

0.65

1.1

1.7

ms

SOFT-START

FBx

R

TRACK/SS Pull-Down Resistance at

Start-Up

200

Ω

ON(TRACK/SS_DIS)

t

f

Soft-Start Discharge Time at Start-Up

Internal Oscillator Frequency

70

1.85

1.8

0.4

1.2

µs

MHz

V

TRACK/SS_DIS

l

R

= 178k

2.25

2.65

2.7

4

OSC

RT/SYNC

V

= SV

IN

RT/SYNC

f

Synchronization Frequency

SYNC Level High

t

, t

> 30ns

SYNC

LOW HIGH

V

RT/SYNC

SYNC Level Low

0.3

V

3615f

ꢂ

LTC3615

elecTrical characTerisTics ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_A= 25°C (Note 2), SV_IN= PV_INx= 3.3V, R_T= 178k, R_SRLIM= 40.2k, unless

otherwise speciﬁed (Notes 1, 2, 11).

SYMBOL

PARAMETER

CONDITIONS

V < 0.15 • SV

PHASE

MIN

TYP

0

MAX

UNITS

Deg

V

Output Phase Shift Between SW1

and SW2

j

IN

SW1–SW2

0.35 • SV < V

< 0.65 • SV

IN

90

IN

PHASE

V

> 0.85 • SV

180

PHASE

IN

V

Voltage at SRLIM to Enable DDR

Mode

(Note 9)

SV – 0.3

IN

SRLIM

MODE

Internal Burst Mode Operation

Pulse-Skipping Mode

0.3

V

(Note 9)

SV – 0.3

IN

Forced Continuous Mode

External Burst Mode Operation

Power Good Voltage Windows

1.1

0.5

SV • 0.58

IN

0.85

PGOOD

TRACK/SSx = SV , Entering Window

IN

V

Ramping Up

–3.5

3.5

–6

6

%

FBx

Ramping Down

TRACK/SSx = SV , Leaving Window

IN

V

Ramping Up

9

–9

11

–11

%

FBx

Ramping Down

t

Power Good Blanking Time

Entering/Leaving Window

70

8

105

12

140

30

µs

Ω

PGOOD

R

Power Good Pull-Down On-Resistance I = 10mA

PGOOD

l

V

Enable Pin

Input High

Input Low

1

V

RUN

0.4

Pull-Down Resistance

4

MΩ

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: This parameter is tested in a feedback loop which servos V

to

FB1,2

the midpoint for the error ampliﬁer (V

= 0.75V).

ITH1,2

Note 4: External compensation on ITH pin.

Note 5: Tying the ITH pin to SV enables internal compensation and AVP

IN

Note 2: The LTC3615 is tested under pulsed load conditions such that

mode for the selected channel.

Note 6: Dynamic supply current is higher due to the internal gate charge

T

≈ T . The LTC3615E is guaranteed to meet performance speciﬁcations

J

A

over the 0°C to 85°C operating junction temperature range. Speciﬁcations

over the –40°C to 125°C operating junction temperature range are

assured by design, characterization and correlation with statistical process

controls. The LTC3615I is guaranteed to meet speciﬁcations over the

full –40°C to 125°C operating junction temperature range. Note that

the maximum ambient temperature is determined by speciﬁc operating

conditions in conjunction with board layout, the rated package thermal

resistance and other environmental factors. Note that the maximum

ambient temperature consistent with these speciﬁcations is determined by

speciﬁc operating conditions in conjunction with board layout, the rated

package thermal impedance and other environmental factors. The junction

being delivered at the switching frequency.

Note 7: See description of the TRACK/SS pin in the Pin Functions section.

Note 8: When sourcing current, the average output current is deﬁned

as ﬂowing out of the SW pin. When sinking current, the average output

current is deﬁned as ﬂowing into the SW pin. Sinking mode requires the

use of forced continuous mode.

Note 9: See description of the MODE pin in the Pin Functions section.

Note 10: Guaranteed by design and correlation to wafer level

measurements for QFN packages.

Note 11: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the speciﬁed maximum operating junction

temperature may impair device reliability or permanently damage the

device.

temperature (T , in °C) is calculated from the ambient temperature

J

(T , in °C) and power dissipation (P , in watts) according to the formula:

A

D

T = T + (P • θ )

JA

J

A

D

where θ (in °C/W) is the package thermal impedence.

JA

3615f

ꢃ

LTC3615

Typical perForMance characTerisTics ^V_IN= 3.3V, R_T/SYNC = SV_IN, unless otherwise noted.

Efﬁciency vs Load Current

(V_MODE= 0V)

Efﬁciency vs Load Current

(V_MODE= 0V)

Efﬁciency vs Load Current

(V_MODE= 0V)

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

= 1.8V

V

= 1.2V

V

= 2.5V

OUT

V

= 2.5V

= 3.3V

= 5V

V

= 2.5V

= 3.3V

= 5V

V

= 3.3V

= 4V

= 5V

IN

10

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

OUTPUT CURRENT (A)

3615 G01

3615 G02

3615 G03

Efﬁciency vs Load Current

(V_MODE= 0.55 • SV_IN)

Efﬁciency vs Load Current

(V_MODE= 0.55 • SV_IN)

Efﬁciency vs Input Voltage

(V_MODE= 0V)

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

95

90

85

80

75

70

65

60

55

50

V

= 1.8V

V

OUT

= 1.2V

V

OUT

= 1.8V

OUT

I

= 3A

OUT

= 2A

V

= 2.25V

= 3.3V

= 5V

V

= 2.25V

= 3.3V

= 5V

= 1A

IN

= 0.3A

= 0.2A

10

0.001

0.01

0.1

1

0.001

0.01

0.1

1

2.25

2.75 3.25

3.75 4.25 4.75 5.25

INPUT VOLTAGE (V)

OUTPUT CURRENT (A)

3615 G04

3615 G05

3615 G06

Load Regulation

Line Regulation

0.20

0.15

0.5

0.4

V

= 1.5V

MODE

INTERNAL

COMPENSATION

0.3

0.10

0.05

(I = SV

TH

)

IN

0.2

0.1

0

EXTERNAL

–0.05

–0.10

–0.15

–0.20

COMPENSATION

–0.1

–0.2

–0.3

–0.4

2.25 2.75 3.25 3.75 4.25 4.75 5.25

INPUT VOLTAGE (V)

0

0.5

1

1.5

2

2.5

3

OUTPUT CURRENT (A)

3615 G08

3615 G07

3615f

ꢄ

LTC3615

Typical perForMance characTerisTics ^V_IN= 3.3V, R_T/SYNC = SV_IN, unless otherwise noted.

Forced Continuous Mode

Operation (FCM)

Pulse-Skipping Mode Operation

Burst Mode Operation

V

OUT

20mV/DIV

V

OUT

20mV/DIV

I

L

200mA/DIV

I

L

I

L

500mA/DIV

3615 G10

3615 G11

3615 G09

V

I

= 1.8V

= 75mA

= 3.3V

20µs/DIV

V

I

= 1.8V

= 75mA

= 0V

20µs/DIV

V

I

= 1.8V

= 100mA

= 1.5V

1µs/DIV

OUT

MODE

OUT

MODE

OUT

MODE

V

Load Step Transient in

Burst Mode Operation

Load Step Transient in

FCM External Compensation

Load Step Transient

in Pulse-Skipping Mode

V

OUT

V

OUT

200mV/DIV

I

L

I

L

1A/DIV

3615 G12

3615 G14

3615 G13

V

I

= 1.8V

50µs/DIV

V

I

= 1.8V

OUT

LOAD

V

MODE

50µs/DIV

= 100mA TO 3A

= 0V

V

I

= 1.8V

50µs/DIV

OUT

LOAD

OUT

LOAD

= 100mA TO 3A

= 1.5V

= 100mA TO 3A

= 3.3V

V

MODE

COMPENSATION FIGURE 1

Load Step Transient in Forced

Continuous Mode Sourcing and

Sinking Current

Internal Start-Up in Forced

Continuous Mode

Load Step Transient in FCM

with AVP Mode

V

OUT

RUN

100mV/DIV

1V/DIV

V

OUT

200mV/DIV

V

OUT

I

L

500mV/DIV

1A/DIV

I

L

1A/DIV

I

L

0A

2A/DIV

PGOOD

2V/DIV

3615 G15

3615 G17

V

I

= 1.8V

50µs/DIV

V

I

= 1.8V

= 3A

MODE

500µs/DIV

OUT

LOAD

OUT

3615 G16

= 100mA TO 3A

= 1.5V

V

I

= 1.8V

50µs/DIV

OUT

LOAD

V

= 1.5V

= –1.5A TO 3A

= 1.5V

MODE

V

= 3.3V

V

ITH

MODE

OUTPUT CAPACITOR VALUE FIGURE 1

COMPENSATION FIGURE 1

3615f

ꢅ

LTC3615

Typical perForMance characTerisTics ^V_IN= 3.3V, R_T/SYNC = SV_IN, unless otherwise noted.

Reference Voltage

vs Temperature

Switch On-Resistance

vs Input Voltage

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

0.606

0.604

MAIN SWITCH

0.602

0.600

0.598

SYNCHRONOUS SWITCH

0.596

0.594

–50 –30 –10 10 30 50 70 90 110 130

2.25

3.25

4.25

(V)

5.25

TEMPERATURE (°C)

V

IN

3615 G18

3615 G19

Switch On-Resistance

vs Temperature

Frequency vs R_T/SYNC

4.0

3.6

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0

100

90

80

70

60

50

40

30

20

10

0

MAIN SWITCH

SYNCHRONOUS SWITCH

100 200 300 400 500 600 700 800 900 1000

–40

–10

5

20 35 50 65 80 95 110 125

–25

R /SYNC (kΩ)

T

TEMPERATURE (°C)

3615 G20

3615 G22

Frequency vs Temperature

Frequency vs Input Voltage

2.60

2.50

2.40

2.30

2.20

2.10

2.00

1.90

1.80

1.70

1.60

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

1.9

1.8

R /SYNC = SV

T

IN

R /SYNC = SV

T

IN

R /SYNC = 200k

T

R = 178k

T

–40

–10

5

20 35 50 65 80 95 110 125

–25

2.25

3.00

3.75

4.50

5.25

V

(V)

TEMPERATURE (°C)

IN

3615 G24

3615 G23

3615f

ꢆ

LTC3615

Typical perForMance characTerisTics ^V_IN= 3.3V, R_T/SYNC = SV_IN, unless otherwise noted.

No Load Supply Current

vs Input Voltage

No Load Supply Current

vs Temperature

Switch Leakage vs Temperature

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

180

160

140

120

100

80

180

160

140

120

100

80

V

= 5.5V

MODE = 0V

IN

RUNx = ITHx = SV

IN

MAIN SWITCH

60

40

SYNCHRONOUS SWITCH

20

0

–40

–10

5

20 35 50 65 80 95 110 125

–25

–40

–10 5

20 35 50 65 80 95 110 125

–25

2.25

3.25 3.75 4.25 4.75 5.25

2.75

TEMPERATURE (°C)

V

(V)

TEMPERATURE (°C)

IN

3615 G25

3615 G26

3615 G27

Slew Rate of Falling Edge at

SW1/2 vs SRLIM Resistor

Slew Rate of Rising Edge at

SW1/2 vs SRLIM Resistor

Sinking Current

V

= 3.3V

V

= 3.3V

IN

V

IN

OUT

= 1.8V

OUT

= 1A

OUT

V

= 1.8V

= 1A

20mV/DIV

OUT

I

SRLIM =

SGND OR SV

IN

SW

2V/DIV

40.2k

100k

OPEN

1V/DIV

I

L

OPEN

500mA/DIV

3615 G30

V

= 1.2V

= –1A

MODE

1µs/DIV

OUT

I

V

= 1.5V

3615 G28

3615 G29

2ns/DIV

Tracking Up/Down in

Forced Continuous Mode,

SRLIM Pin Tied to 0V

Tracking Up/Down in

Forced Continuous Mode,

SRLIM Pin Tied to SV_IN

V

OUT1

V

OUT1

500mV/DIV

1V/DIV

V

TRACK/SS

V

TRACK/SS

200mV/DIV

500mV/DIV

PGOOD

2V/DIV

PGOOD

2V/DIV

3615 G32

3615 G31

2ms/DIV

V

I

= 0V TO 1.2V

= 3A

V

I

= 0V TO 1.8V

= 3A

OUT

V

= 0V TO 0.4V

V

= 0V TO 0.7V

TRACK/SS

V

= 1.5V

= 3.3V

V

= 1.5V

= 0V

MODE

SRLIM

MODE

SRLIM

3615f

ꢇ

LTC3615

pin FuncTions ^(FE/UF)

PHASE (Pin 1/Pin 4): Phase Shift Selection. If pin is tied to

slope compensation is automatically adapted to the

external clock frequency.

SGND, the phase between SW1 and SW2 will be 0°. Tying

PHASE to SV will select 180° of phase shift. With the

IN

3. Tying this pin to SV enables the internal 2.25MHz

IN

PHASE pin tied to half of the SV voltage, 90° of phase

IN

oscillator frequency.

shift will be selected.

PGOOD2 (Pin 13/Pin 16): Power Good Output for

Channel 2. See PGOOD1.

V

(Pin 2/Pin 5): Voltage Feedback Input Pin for Chan-

FB2

nel 2. See V

.

FB1

SRLIM (Pin 14 /Pin 17): Slew Rate Limit. Slew rate on the

switch pins is programmed with the SRLIM pin:

ITH2 (Pin 3/Pin 6): Error Ampliﬁer Compensation of

Channel 2. See ITH1.

1. Tying this pin to SGND selects maximum slew rate.

2. Minimum slew rate is selected when the pin is open.

TRACK/SS2(Pin4/Pin7):Internal,ExternalSoft-Start,Ex-

ternal Reference Input for Channel 2. See TRACK/SS1.

3. Connecting a resistor from SRLIM to SGND allows the

slew rate to be continuously adjusted.

SGND (Pin 5/Pin 8): Signal Ground. All small-signal and

compensationcomponentsshouldconnecttothisground

pin which, in turn, should be connected to PGND at one

point.

4. If SRLIM is tied to SV the slew rate is set to maxi-

IN

mum and DDR mode is enabled (see the Applications

Information section).

PV (Pins 6, 7/Pins 9, 10) Channel 2 Power Supply

IN2

Input. See PV

.

IN1

PGOOD1 (Pin 15/Pin 18): Power Good Output Pin for

Channel 1. The open-drain output will be pulled down to

ground when the FB1 voltage of the channel is not within

the power good voltage window. The PGOOD1 will also be

pulled down if the channel is not enabled with the RUN1

SW2 (Pins 8, 9/Pins 11, 12): Channel 2 Switching Node.

See SW1.

RUN2 (Pin 10/Pin 13): Enable Pin for Channel 2. See

RUN1.

pin or an undervoltage at SV is detected. In DDR mode

IN

RUN1 (Pin 11/Pin 14): Enable Pin for Channel 1. Forc-

ing RUN1 above the input threshold enables the output

SW1 of channel 1. Forcing both RUNx pins to ground

shuts down the LTC3615. In shutdown, all functions

are disabled and the LTC3615 draws <1µA of supply

current.

(SRLIM=SV ),thepowergoodwindowmovesinrelation

IN

to the actual TRACK/SS pin voltage.

SW1 (Pins 17, 16/Pins 19, 20): Channel 1 Switching

Node. Connection to the external inductor. This pin con-

nects to the drains of the internal synchronous power

MOSFET switches.

R /SYNC (Pin 12/Pin 15): Oscillator Frequency. This

T

PV (Pins 18, 19/Pins 21, 22): Channel 1 Power Supply

IN1

pin provides three modes of setting the switching fre-

Inputs. These pins connect to the source of the internal

quency.

power P-channel MOSFET of channel 1. P

and P

VIN1

VIN2

1. Connecting a resistor from R /SYNC to ground will

are independent of each other. They may connect to equal

or lower supplies than S

T

set the switching frequency based on the resistor

.

VIN

value.

SV (Pin 20/Pin 23) Signal Input Supply. This pin pow-

IN

2. Driving R /SYNC with an external clock signal will

ers the internal control circuitry and is monitored by the

T

synchronize the switcher to the applied frequency. The

undervoltage lockout comparator.

3615f

ꢈ

LTC3615

pin FuncTions ^(FE/UF)

TRACK/SS1 (Pin 21/Pin 24): Internal, External Soft-

Start, External Reference Input for Channel 1. The type

of start-up behavior for channel 1 is programmable with

the TRACK/SS1 pin:

MODE (Pin 24/Pin 3): Mode Selection.

1. Tying the MODE pin to SV or SGND enables pulse-

IN

skippingmodeorBurstModeoperation(withaninternal

Burst Mode clamp), respectively.

1.Internalsoft-startwithaﬁxedtimingcanbeprogrammed

2. If this pin is held at slightly higher than half of SV ,

IN

by tying TRACK/SS1 to SV .

IN

forced continuous mode will be selected.

2. External soft-start can be programmed with the timing

3. Connecting this pin to an external voltage will select

Burst Mode operation with the burst clamp set to the

pin voltage.

set by a capacitor to ground and a resistor to SV .

IN

3. Tracking the start-up behavior of another supply is

programmable (see the Applications Information

section).

PGND (Exposed Pad Pin 25/ Exposed Pad Pin 25): Power

Ground. The exposed pad connects to the sources of the

power N-channel MOSFETs. The PGND pin is common

for both channels. The exposed pad must be soldered

to the PCB.

4. The pin can be used as external reference input.

ITH1 (Pin 22/Pin 1): Error Ampliﬁer Compensation. Con-

nection for external compensation from ITH to SGND.

The current comparator’s threshold increases with this

control voltage. Tying this pin to SV enables AVP mode

with internal compensation.

For electrical connection and rated thermal performance,

refer to the Operation and Applications Information sec-

tions for more information.

IN

V

(Pin 23/Pin 2): Voltage Feedback Input Pin for

FB1

Channel 1. Receives the feedback voltage for channel 1

from the external resistive divider across the output.

3615f

ꢀ0

LTC3615

FuncTional block DiagraM

CHANNEL 1

ITH1

PGOOD1

PGOOD

WINDOW-

COMPARATOR

DELAY

INTERNAL/

EXTERNAL

COMPENSATION

ITH-VOLTAGE

LIMIT

ERROR

AMPLIFIER

FB1

V

BURST

+

–

COMPARATOR

MODE

REF

+

–

+

IDEAL

DIODE

PMOS

CURRENT SENSE

PMOS

–

SLOPE

CURRENT

PV

+ –

COMPENSATION

IN1

COMPARATOR

MODE

CONTROLLER LOGIC

SW1

TRACK/SS1

SOFT-START

OR

GATE DRIVER

RUN1

RUN2

CLK1

PLL

OSCILLATOR

AND PHASE

SELECTOR

+

R /SYNC

T

NMOS

CURRENT SENSE

PHASE

0A

–

SV

IN

CLK2

UNDERVOLTAGE

LOCKOUT

REVERSE

SGND

SHUTDOWN

CURRENT

COMPARATOR

SRLIM

PGND

DUPLICATE FOR CHANNEL 2

PV

IN2

PGOOD2

FB2

SW2

TRACK/SS2

ITH2

3615f

ꢀꢀ

LTC3615

operaTion

Main Control Loop

MODE SELECTION

The LTC3615 is a dual monolithic step-down DC/DC

converter featuring current-mode, constant-frequency

operation. Both channels are identical and share common

clock and reference circuits to improve channel-to-chan-

nel matching.

The MODE pin is used to select one of four different

operating modes for both channels together (see Figures

1 and 3):

SV

IN

PS

FC

PULSE-SKIPPING MODE ENABLE

SV – 0.3V

IN

During normal operation, the internal top power switch

(P-channel MOSFET) of each channel is turned on at the

beginning of its clock cycle. Current in the inductor in-

creasesuntilthecurrentcomparatortripsandturnsoffthe

toppowerMOSFET. Thepeakinductorcurrentatwhichthe

current comparator shuts off is controlled by the voltage

on the ITH pin. The error ampliﬁer adjusts the voltage on

the ITH pin by comparing the feedback signals derived

SV • 0.58

IN

FORCED CONTINUOUS MODE ENABLE

1.1V

0.8V

Burst Mode ENABLE—EXTERNAL CLAMP,

CONTROLLED BY VOLTAGE APPLIED AT

MODE PIN

BM

EXT

0.5V

0.3V

BM

Burst Mode ENABLE—INTERNAL CLAMP

SGND

from an external resistor divider on the V pin with an

FBx

3615 F01

internal 0.6V reference. When the load current increases,

it causes a reduction in the feedback voltage relative to

the reference. The error ampliﬁer raises the ITH voltage

until the average inductor current matches the new load

current. TypicalvoltagerangefortheITHpinisfrom0.45V

to 1.05V with 0.45V corresponding to zero current.

Figure 1. Mode Selection Voltage

Burst Mode Operation—Internal Clamp

Connecting the MODE pin to the SGND pin enables Burst

Mode operation with its peak current set internally. In

BurstModeoperationtheinternalpowerMOSFETsoperate

intermittently at light loads. This increases efﬁciency by

minimizingswitchinglosses.Duringtheintervalswhenthe

MOSFETs are not switching, the LTC3615 enters a sleep

state where many of the internal circuits are disabled to

save power. During Burst Mode operation, the ITH volt-

age is monitored by the burst comparator to determine

when the sleep state is entered or exited again. When the

average inductor current is greater than the load current,

the voltage on the ITH pin drops. As the ITH voltage falls

below the internal threshold, the LTC3615 enters the sleep

state. In the sleep state, the power MOSFETs are held

off and the load current is solely supplied by the output

capacitor. When the output voltage drops, the top power

MOSFET is switched back on and the internal circuits are

reenabled. This process repeats at a rate that is dependent

on the load current.

When the top power MOSFET shuts off, the synchronous

power switch (N-channel MOSFET) turns on until either

the current limit is reached or the next clock cycle begins.

The bottom current limit is typically set at –4A for forced

continuous mode and 0A for Burst Mode operation and

pulse-skipping mode.

The operating frequency defaults to 2.25MHz when

R /SYNC is connected to SV , or can be set by an ex-

T

IN

ternal resistor connected between the R /SYNC pin and

T

ground, or by a clock signal applied to the R /SYNC pin.

T

The switching frequency can be set from 400kHz to 4MHz

(see the Applications Information section).

OvervoltageandundervoltagecomparatorspullthePGOOD

output low if the output voltage varies more than 7.5%

from the set point.

3615f

ꢀꢁ

LTC3615

operaTion

Burst Mode Operation—External Clamp

Forced Continuous Mode Operation

Connecting the MODE pin to a voltage in the range of 0.5V

to0.8VenablesBurstModeoperationwithexternalclamp.

Duringthismodeofoperation,theminimumvoltageonthe

ITH pin is externally set by the voltage on the MODE pin.

It is recommended to use Burst Mode operation with the

internal clamp for ambient temperatures above 85°C.

In forced continuous mode the inductor current is con-

stantly cycled which creates a minimum output voltage

ripple at all output current levels.

Connecting the MODE pin, to a voltage in the range of

1.1V to SV • 0.58 will select the forced continuous mode

IN

operation.

Pulse-Skipping Mode Operation

The forced continuous mode must be used if the output

is required to sink current.

Pulse-skipping mode is similar to Burst Mode operation,

but the LTC3615 does not disable power to the internal

circuitry during sleep mode. This improves output voltage

ripple but uses more quiescent current compromising

light load efﬁciency.

Dropout Operation

Astheinputsupplyvoltageapproachestheoutputvoltage,

the duty cycle increases toward the maximum on-time.

Further reduction of the supply voltage forces the main

switch to remain on for more than one cycle, eventually

reaching 100% duty cycle. The output voltage will then be

determined by the input voltage minus the voltage drop

across the internal P-channel MOSFET and the inductor.

Connecting the MODE pin to SV enables pulse-skipping

IN

mode. As the load current decreases, the peak inductor

current will be determined by the voltage on the ITH pin

until the ITH voltage drops below 450mV, corresponding

to 0A. At this point switching cycles will be skipped to

keep the output voltage in regulation.

LTC3615

SV

SW1

V

IN

V

IN

OUT1

R

M1

MODE

SGND

FB1

0V

M2

0V

SGND

2a. Burst Mode Operation

Internally Controlled

2b. Burst Mode Operation

Externally Controlled

LTC3615

SV

IN

V

IN

R

M1

MODE

SGND

M2

0V

SGND

3615 F02

2c. Pulse-Skipping Mode

2d. Forced Continuous Mode

Figure 2. Modes of Operation

3615f

ꢀꢂ

LTC3615

operaTion

Low Supply Operation

LTC3615 clamps the maximum ITH pin voltage at ap-

proximately 1.05V which corresponds to about 5A peak

inductor current.

The LTC3615 is designed to operate down to an input

supply voltage of 2.25V. An important consideration

at low input supply voltages is that the R

P-channel and N-channel power switches increases by

50% compared to 5V. The user should calculate the

power dissipation when the LTC3615 is used at 100%

duty cycle with low input voltages to ensure that thermal

limits are not exceeded.

of the

Whentheoutputisshortedtoground,theinductorcurrent

decays very slowly during a single switching cycle. The

LTC3615 uses two techniques to prevent current runaway

from occurring:

DS(ON)

1. If the output voltage drops below 50% of its nominal

value, the clamp voltage at pin ITH is lowered, causing

the maximum peak inductor current to lower gradu-

ally with the output voltage. When the output voltage

reaches 0V, the clamp voltage at the ITH pin drops to

40% of the clamp voltage during normal operation. The

short-circuitpeakinductorcurrentisdeterminedbythe

minimum on-time of the LTC3615, the input voltage

and the inductor value. This foldback behavior helps

in limiting the peak inductor current when the output

is shorted to ground. It is disabled during internal or

externalsoft-startandtrackingup/downoperation(see

the Applications Information section).

Slope Compensation and Inductor Peak Current

Slope compensation provides stability in current mode

constant-frequency architectures by preventing subhar-

monic oscillations at duty cycles greater than 50%. The

LTC3615 implements slope compensation by adding a

compensation ramp to the inductor current signal.

Short-Circuit Protection

Thepeakinductorcurrentatwhichthecurrentcomparator

shuts off the top power switch is controlled by the voltage

on the ITH pin.

2. If the inductor current of the bottom MOSFET increases

beyond 6A typical, the top power MOSFET will be held

off and switching cycles will be skipped until the induc-

tor current reduces.

If the output current increases, the error ampliﬁer raises

the ITH pin voltage until the average inductor current

matches the new load current. In normal operation, the

3615f

ꢀꢃ

LTC3615

applicaTions inForMaTion

Operating Frequency

is typically 60ns, therefore, the minimum duty cycle is

equal to 60ns • 100% • f (Hz)

OSC

Selectionoftheoperatingfrequencyisatrade-offbetween

efﬁciency and component size. High frequency operation

allows the use of smaller inductor and capacitor values.

Tying the R /SYNC pin to SV sets the default internal

T

IN

operating frequency to 2.25MHz 20%.

Operation at lower frequencies improves efﬁciency by

reducing internal gate charge losses but requires larger

inductance values and/or capacitance to maintain low

output ripple voltage.

Frequency Synchronization

The LTC3615’s internal oscillator can be synchronized to

an external frequency by applying a square wave clock

signal to the R /SYNC pin. During synchronization, the

T

The operating frequency of the LTC3615 is determined by

top MOSFET turn-on of channel 1 is locked to the rising

edgeoftheexternalfrequencysource.Thesynchronization

frequency range is 400kHz to 4MHz. The internal slope

compensation is automatically adapted to the external

clock frequency.

anexternalresistorthatisconnectedbetweenpinR /SYNC

T

andground.Thevalueoftheresistorsetstherampcurrent

that is used to charge and discharge an internal timing

capacitor within the oscillator and can be calculated by

using the following equation:

In the signal path from the R /SYNC clock input to the

T

4 • 10¹¹ΩHz

SW output, the LTC3615 is processing the external clock

R_T=

f_OSC

frequency through an internal PLL.

Although frequencies as high as 4MHz are possible, the

minimum on-time of the LTC3615 imposes a minimum

limit on the operating duty cycle. The minimum on-time

After detecting an external clock on the ﬁrst rising edge

of R /SYNC the PLL starts up with the internal default of

T

2.25MHz. The internal PLL then requires a certain number

V

IN

3.3V

47µF

1µF

SV

(2s) PV

IN1 IN2

IN

0.47µH

V

OUT1

(2s) SW1

RUN1

1.8V/3A

47µF

R1

422k

R

SS

4.7M

FB1

TRACK/SS1

PGOOD1

C

SS

R2

10nF

29.4k

ITH1

LTC3615

MODE

10pF

R

C

R3

178k

15k

R , 200k

T

R /SYNC

T

C

0.47µH

V

OUT2

R

1000pF

SRLIM

40.2k

(2s) SW2

2.5V/3A

47µF

R5

665k

SRLIM

PHASE

FB2

R4

210k

RUN2

TRACK/SS2

PGOOD2

ITH2 SGND

PGND

3615 F03

Figure 3. Soft-Start and Compensation for Channel 1 Externally Programmed,

Soft-Start and Compensation for Channel 2 Internally Programmed

3615f

ꢀꢄ

LTC3615

applicaTions inForMaTion

V

IN

V

IN

LTC3615

15pF

SV

f

IN

f

IN

f

SW

1/T

P

SW

P

f

t1/R

OSC

0.4V

SW

2.25MHz

1/T

R /SYNC

T

R /SYNC

T

R /SYNC

T

R /SYNC

T

SGND

1.2V

0.3V

1.2V

0.3V

R

OSC

R

T

3615 F04

T

P

Figure 4. Setting the Switching Frequency

of periods to settle until the frequency at SW matches the

Foradutycycleoflessthan40%foronechannelandmore

than 60% for the other channel, choose a phase shift of 0

frequency and phase of R /SYNC.

T

or 180° (PHASE = SGND or SV ). If both channels have

a duty cycle of around 50%, select a phase difference of

IN

When the external clock signal is removed, the LTC3615

needs approximately 5µs to detect the absence of the

external clock. During this time, the PLL will continue to

provide clock cycles before it is switched back to the de-

fault frequency or selected frequency (set via the external

90° (PHASE = one-half SV ).

IN

Inductor Selection

R resistor).

For a given input and output voltage, the inductor value

and operating frequency determine the ripple current. The

T

A safe way of driving the R /SYNC input is with an AC

T

ripple current ∆I increases with higher V and decreases

L

IN

couplingtotheclockgeneratorviaa15pFcapacitor.TheAC

couplingavoidscomplicationsiftheexternalclockgenera-

tor cannot provide a continuous clock signal at the time of

start-up, operation and shut down of the LTC3615.

with higher inductance.











V_OUT

∆I_L=

• 1–





f

•L

V







_IN(MAX)

SW

In general, any abrupt clock frequency change of the

regulator will have an effect on the SW pin timing and

may cause equally sudden output voltage changes. This

must be taken into account in particular if the external

clock frequency is signiﬁcantly different from the internal

default of 2.25MHz.

Having a lower ripple current reduces the core losses

in the inductor, the ESR losses in the output capacitors

and the output voltage ripple. A reasonable starting point

for selecting the ripple current is ∆I = 0.3(I

).

L

OUT(MAX)

The largest ripple current occurs at the highest V . To

IN

guarantee that the ripple current stays below a speciﬁed

maximum, theinductorvalueshouldbechosenaccording

to the following equation:

Phase Selection

Channel 2 will operate in-phase, 180° out-of-phase

(anti-phase) or shifted by 90° from channel 1 depending

on the state of the PHASE pin—low, midrail and high,

respectively. Antiphase generally reduces input voltage

and current ripple. Crosstalk between switch nodes SW1,

SW2 and components or sensitive lines connected to FBx,











V_OUT

_SW• ∆I

V_OUT

L =

• 1–







f

V



_L(MAX)



IN(MAX)

The inductor value will also have an effect on Burst Mode

operation. The transition to low current operation begins

when the peak inductor current falls below a level set by

the burst clamp. Lower inductor values result in higher

ripple current which causes this to occur at lower DC

load currents. This causes a dip in efﬁciency in the upper

range of low current operation. In Burst Mode operation,

lower inductance values will cause the burst frequency

to increase.

ITHx, R /SYNC or SRLIM can cause unstable switching

T

waveforms and unexpectedly large input and output volt-

age ripple.

The situation improves if rising and falling edges of the

switchnodesaretimedcarefullynottocoincide.Depending

on the duty cycle of the two channels, choose the phase

differencebetweenthechannelstokeepedgesasfaraway

from each other as possible.

3615f

ꢀꢅ

LTC3615

applicaTions inForMaTion

Inductor Core Selection

This formula has a maximum at V = 2V , where I

OUT

=

RMS

IN

OUT

I

/2.Thissimpleworst-caseconditioniscommonlyused

Once the value for L is known, the type of inductor must

be selected. Actual core loss is independent of core size

for ﬁxed inductor value, but it is very dependent on the

inductance selected. As the inductance increases, core

losses decrease. Unfortunately, increased inductance

requires more turns of wire, and therefore, copper losses

will increase.

fordesignbecauseevensigniﬁcantdeviationsdonotoffer

muchrelief.Notethatripplecurrentratingsfromcapacitor

manufacturers are often based on only 2000 hours of life

which makes it advisable to further derate the capacitor,

or choose a capacitor rated at a higher temperature than

required.Severalcapacitorsmayalsobeparalleledtomeet

size or height requirements in the design.

Ferrite designs have very low core losses and are pre-

ferred at high switching frequencies, so design goals can

concentrate on copper loss and preventing saturation.

Ferrite core material saturates hard, which means that

inductancecollapsesabruptlywhenthepeakdesigncurrent

is exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow a ferrite core to saturate!

Table 1. Representative Surface Mount Inductors

INDUCTANCE DCR

MAX

DIMENSIONS

(mm)

HEIGHT

(mm)

(µH) (mΩ) CURRENT (A)

Vishay IHLP-2020BZ-01

0.33

0.47

0.68

1

7.6

8.9

25

21

15

16

2

5.18 × 5.49

11.2

18.9

Different core materials and shapes will change the size/

current and price/current relationship of an inductor.

Toroidorshieldedpotcoresinferriteorpermalloymaterials

are small and do not radiate much energy, but generally

cost more than powdered iron core inductors with similar

characteristics. The choice of which style inductor to use

mainly depends on the price versus size requirements

and any radiated ﬁeld/EMI requirements. Table 1 shows

some typical surface mount inductors that work well in

LTC3615 applications.

Toko DE3518C Series

0.22

Sumida CDMC6D28 Series

8

24

2

4.3 × 4.7

0.3

0.47

0.68

1

3.2

4.2

5.4

8.8

15.4

13.6

11.3

8.8

3

6.7 × 7.25

NEC/Tokin MPLC0730L Series

0.47

0.75

1.0

4.5

7.5

9.0

16.6

12.2

10.6

3.0

6.9 × 7.7

Input Capacitor C Selection

IN

Coilcraft DO1813H Series

0.33

0.56

4

10

5

8.9 × 6.1

In continuous mode, the source current of the top P-chan-

10

7.7

nel MOSFET is a square wave of duty cycle V /V . To

OUT IN

Coilcraft SLC7530 Series

preventlargevoltagetransients, alowESRcapacitorsized

0.27

0.35

0.4

0.1

14

11

8

3

7.5 × 6.7

for the maximum RMS current must be used for C .

IN

The maximum RMS capacitor current is given by:





V_OUT

V

OUT

IN

I_RMS= I_OUT(MAX)

•

– 1





V





IN

3615f

ꢀꢆ

LTC3615

applicaTions inForMaTion

Output Capacitor C

Selection

Capacitors are tempting for switching regulator use

because of their very low ESR. Great care must be taken

when using only ceramic input and output capacitors.

OUT

The selection of C

is typically driven by the required

OUT

ESR to minimize voltage ripple and load step transients

(low-ESR ceramic capacitors are discussed in the next

section). Typically, once the ESR requirement is satisﬁed,

the capacitance is adequate for ﬁltering. The output ripple

Ceramic caps are prone to temperature effects which re-

quirethedesignertocheckloopstabilityovertheoperating

temperaturerange.Tominimizetheirlargetemperatureand

voltage coefﬁcients, only X5R or X7R ceramic capacitors

should be used.

∆V

is determined by:

OUT









1

∆V_OUT≤ ∆I_L• ESR +



8 • f_SW• C

When a ceramic capacitor is used at the input, and the

power is being supplied through long wires, such as from

a wall adapter, a load step at the output can induce ringing

_OUT

wheref =operatingfrequency,C =outputcapacitance

SW

OUT

and ∆I = ripple current in the inductor. The output ripple

at the V pin. At best, this ringing can couple to the output

L

IN

is highest at maximum input voltage since ∆I increases

and be mistaken as loop instability. At worst, the ringing

at the input can be large enough to damage the part.

L

with input voltage.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the capacitance, ESR or RMS

currenthandlingrequirementoftheapplication.Aluminum

electrolytic, special polymer, ceramic and dry tantalum

capacitors are all available in surface mount packages.

Since the ESR of a ceramic capacitor is so low, the input

and output capacitor must instead fulﬁll a charge storage

requirement.Duringaloadstep,theoutputcapacitormust

instantaneously supply the current to support the load

until the feedback loop raises the switch current enough

to support the load. The time required for the feedback

loop to respond is dependent on the compensation com-

ponents and the output capacitor size. Typically, three to

four cycles are required to respond to a load step, but only

in the ﬁrst cycle does the output drop linearly. The output

Tantalumcapacitorshavethehighestcapacitancedensity,

but can have higher ESR and must be surge tested for

use in switching power supplies. Aluminum electrolytic

capacitors have signiﬁcantly higher ESR, but can often

be used in extremely cost-sensitive applications provided

that consideration is given to ripple current ratings and

long term reliability.

droop, V

, is usually about two to three times the

DROOP

linear drop of the ﬁrst cycle. Thus, a good place to start

is with the output capacitor size of approximately:

Ceramic Input and Output Capacitors

2.5 • ∆I_OUT

f_SW• V_DROOP

C_OUT

≈

Ceramic capacitors have the lowest ESR and can be cost

effective, but also have the lowest capacitance density,

high voltage and temperature coefﬁcients, and exhibit

audible piezoelectric effects. In addition, the high-Q of

ceramic capacitors along with trace inductance can lead

to signiﬁcant ringing.

More capacitance may be required depending on the duty

cycle and load step requirements. In most applications,

the input capacitor is merely required to supply high

frequency bypassing, since the impedance to the supply

is very low.

3615f

ꢀꢇ

LTC3615

applicaTions inForMaTion

Output Voltage Programming

Pulse-Skipping Mode

The output voltages are set by external resistive dividers.

Pulse-skippingmode,whichisacompromisebetweenlow

output voltage ripple and efﬁciency, can be implemented

For example, V

equation:

can be set according to the following

OUT2

by connecting the MODE pin to SV . This sets I

to

IN

BURST

0A. In this condition, the peak inductor current is limited

by the minimum on-time of the current comparator. The

lowestoutputvoltagerippleisachievedwhilestilloperating

discontinuously. During very light output loads, pulse-

skipping allows only a few switching cycles to skip while

maintaining the output voltage in regulation.





R5

R4

V_OUT2= 0.6V • 1+









The resistive divider allows pin V to sense a fraction of

the output voltage as shown in Figure 3.

FB

Burst Clamp Programming

Internal and External Compensation

If the voltage on the MODE pin is less than 0.8V, Burst

Mode operation is enabled. If the voltage on the MODE pin

is less than 0.3V, the internal default burst clamp level is

selected. The minimum voltage on the ITH pin is typically

525mV (internal clamp).

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC load current.

When a load step occurs, like the one shown in Figure 5,

V

shifts by an amount equal to ∆I

• ESR, where

OUT

LOAD

If the voltage is between 0.45V and 0.8V, the voltage on

ESR is the effective series resistance of C . ∆I

OUT

LOAD

the MODE pin (V

) is equal to the minimum voltage

BURST

also begins to charge or discharge C , generating the

feedback error signal that forces the regulator to adapt

to the current change and return V

value. During this recovery time, V

OUT

on the ITH pin (external clamp) and determines the burst

clamp level I (typically from 1A to 3.5A).

BURST

to its steady-state

can be monitored

OUT

When the ITH voltage falls below the internal (or external)

clamp voltage, the sleep state is entered. As the output

load current drops, the peak inductor current decreases

to keep the output voltage in regulation. When the output

load current demands a peak inductor current that is less

for excessive overshoot or ringing, which would indicate

a stability problem. The availability of the ITH pin allows

the transient response to be optimized over a wide range

of output capacitance.

than I

, the burst clamp will force the peak inductor

BURST

The ITH1 external components (15k and 100pF) shown

in Figure 3 will provide an adequate compensation as

well as a starting point for most applications. The values

can be modiﬁed slightly to optimize transient response

once the ﬁnal PCB layout is complete and the particular

output capacitor type and value have been determined.

The output capacitors need to be selected because the

various types and values determine the loop gain and

phase. The gain of the loop will be increased by increas-

current to remain equal to I

regardless of further

BURST

reductions in the load current.

Since the average inductor current is greater than the

output load current, the voltage on the ITH pin will

decrease. When the ITH voltage drops, sleep mode is

enabled in which both power switches are shut off along

withmostofthecircuitrytominimizepowerconsumption.

All circuitry is turned back on and the power switches

resume operation when the output voltage drops out of

ing R and the bandwidth of the loop will be increased

C

by decreasing C . If R is increased by the same factor

regulation. The value for I

is determined by the

C

BURST

that C is decreased, the zero frequency will be kept the

desired amount of output voltage ripple. As the value of

increases, the sleep period between pulses and

C

same, thereby keeping the phase shift the same in the

most critical frequency range of the feedback loop. The

output voltage settling behavior is related to the stabil-

ity of the closed-loop system. The external compensa-

tion, forced continuous operation circuit in the Typical

I

BURST

the output voltage ripple increase. It is recommend to

use Burst Mode operation with internal clamp for tem-

peratures above 85°C ambient.

3615f

ꢀꢈ

LTC3615

applicaTions inForMaTion

Applicationssectionusesfastercompensationtoimprove

load step response.

When the load current suddenly decreases, the output

voltage starts at a level lower than nominal so the output

voltage can have more overshoot and stay within the

speciﬁed voltage range. This behavior is demonstrated

in Figure 6.

A second, more severe transient is caused by switching

in loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C , causing a rapid drop in V . No regulator can

The beneﬁt is a lower peak-to-peak output voltage devia-

tion for a given load step without having to increase the

output ﬁlter capacitance. Alternatively, the output voltage

ﬁlter capacitance can be reduced while maintaining the

same peak-to-peak transient response. For this operation

mode, theloopgainisreducedandnoexternalcompensa-

tion is required.

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. More output

capacitance may be required depending on the duty cycle

and load step requirements.

If the ITH pin is tied to SV , the active voltage positioning

IN

(AVP) mode and the internal compensation is selected.

Programmable Switch Pin Slew Rate

In AVP mode, the load regulation performance is inten-

tionally reduced, setting the output voltage at a point that

is dependent on the load current. When the load current

suddenly increases, the output voltage starts from a level

slightly higher than nominal so the output voltage can

droop more and stay within the speciﬁed voltage range.

Asswitchingfrequenciesrise,itisdesirabletominimizethe

transitiontimerequiredwhenswitchingtominimizepower

losses and blanking time for the switch to settle. However,

fast slewing of the switch node results in relatively high

external radiated EMI and high on-chip supply transients,

which can cause problems for some applications.

V

OUT

100mV/DIV

V

OUT

200mV/DIV

3A

I

L

1A/DIV

I

L

1A/DIV

100mA

3615 F06

3615 F05

50µs/DIV

V

I

= 1.8V

V

I

= 1.8V

OUT

LOAD

OUT

LOAD

= 100mA TO 3A

= 1.5V

= 100mA TO 3A

= 1.5V

V

MODE

= V = 3.3V

ITH

MODE

V

COMPENSATION AND OUTPUT CAPACITOR

VALUES OF FIGURE 3

IN

OUTPUT CAPACITOR VALUE FIGURE 3

Figure 5. Load Step Transient in FCM with External Compensation

Figure 6. Load Step Transient in FCM in AVP Mode

3615f

ꢁ0

LTC3615

applicaTions inForMaTion

The LTC3615 allows the user to control the slew rate of

the switching node SW by using the SRLIM pin. Tying this

pin to ground selects the fastest slew rate. The slowest

slew rate is selected when the pin is open. Connecting a

resistor (between 10k to 100k) from SRLIM pin to ground

adjuststheslewratebetweenthemaximumandminimum

values. The reduced dV/dt of the switch node results in a

signiﬁcant reduction of the supply and ground ringing, as

well as lower radiated EMI. See Figure 7a and the Typical

Performance Characteristics section for examples.

pin to SGND and discharging the external capacitor C

(see Figure 3).

SS

The initial discharge is adequate to discharge capacitors

up to 33nF. If a larger capacitor is required, connect the

external soft-start resistor R to the RUN pin to fully

SS

discharge the capacitor.

1. Tying this pin to SV selects the internal soft-start

IN

circuit. This circuit ramps the output voltage to the ﬁnal

value within 1ms.

2. If a longer soft-start period is desired, it can be set ex-

ternallywitharesistorandcapacitorontheTRACK/SSx

pins as shown in Figure 3. The voltage applied at the

TRACK/SSx pins sets the value of the internal refer-

Reducing the slew rate causes a trade-off between ef-

ﬁciency and low EMI (see Figure 7b).

Particularattentionshouldbeusedwithveryhighswitching

frequencies. Using the slowest slew rate (SRLIM open)

can reduce the minimum duty cycle capability.

ence at V until TRACK/SSx is pulled above 0.6V. The

FB

external soft-start duration can be calculated by using

the following equation:

Soft-Start





SV

IN

t_SS= R_SS• C_SS• In

The RUNx pins provide a means to shut down each chan-

nel of the LTC3615. Pulling both pins below 0.3V places

the LTC3615 in a low quiescent current shutdown state





SV – 0.6V





IN

3. The TRACK/SSx pin can be used to track the output

voltage of another supply.

(I < 1µA).

Q

After enabling the LTC3615 by bringing either one or both

RUNxpinsabovethethreshold,theenabledchannelsenter

a soft-start-up state. The type of soft-start behavior is set

by the TRACK/SSx pins. The soft-start cycle begins with

an initial discharge pulse pulling down the TRACK/SSx

Regardless of either the internal or external soft-start

state, the MODE pin is ignored during start-up and the

regulator defaults to pulse-skipping mode. In addition,

the PGOODx pin is kept low, and the frequency foldback

function is disabled.

92

V

I

= 3.3V

V

I

= 1.8V

= 1A

IN

OUT

FCM

= 1.8V

= 1A

91

90

89

88

87

86

85

84

83

82

OUT

SRLIM =

GND OR SV

OPEN

IN

SGND OR SV

IN

40.2k

20k

40.2k

100k

1V/DIV

OPEN

3615 F07a

2ns/DIV

2.25

3.06

4.69

5.50

3.88

(V)

V

IN

3615 07b

(7a) Slew Rate of Rising Edge at SW1/2 vs SRLIM Resistor

(7b) Efﬁciency vs SRLIM Resistor Programming

Figure 7. Slew Rate and the SRLIM Resistor

3615f

ꢁꢀ

LTC3615

applicaTions inForMaTion

Output Voltage Tracking Input

Through the TRACK/SS pin, the output voltage can be set

up to either coincidental or ratiometric tracking, as shown

in Figures 8 and 9.

If SRLIM is low, once V

reaches or exceeds 0.6V

TRACK/SS

the run state is entered, and the MODE selection, power

good and current foldback circuits are enabled.

To implement the coincidental tracking waveform in

Figure 8, connect an extra resistive divider to the output

of the master channel and connect its midpoint to the

TRACK/SS pin for the slave channel. The ratio of this

divider should be selected the same as that of the slave

channel’s feedback divider (Figure 10).

In the run state, the TRACK/SS pin can be used to track

down/up the output voltage of another supply. If the

V

again drops below 0.6V, the LTC3615 enters

TRACK/SS

the down-tracking state and the V

is referenced to

OUT

the TRACK/SS voltage. If V

reaches 0.1V value

TRACK/SS

In this tracking mode, the master channel’s output must

be set higher than slave channel’s output. To implement

the ratiometric start-up in Figure 9, no extra divider is

needed; simply connect the TRACK/SS pin to the other

the switching frequency is reduced by 4x to ensure that

the minimum duty cycle limit does not prevent the out-

put from following the TRACK/SS pin. The run state will

resume if the V

again exceeds 0.6V and the V

TRACK/SS

OUT

channel’s V pin (Figure 12).

is referenced to the internal reference.

FB

V

OUT1

OUT2

OUT1

OUT2

3615 F08

3615 F09

TIME

Figure 8. Coincident Start-Up Tracking

Figure 9. Ratiometric Start-Up Tracking

V

OUT1

R1

V

OUT1

V

OUT1

R3

R4

R1

R2

R3

R1

LTC3615

FB1

LTC3615

FB1

LTC3615

FB1

R2

TRACK/SS2

FB2

TRACK/SS2

FB2

TRACK/SS2

FB2

V

OUT2

R5

R6

R4

R3

R4

R5

3615 F10

3615 F11

3615 F12

Figure 10. Set for Coincidentally

Tracking (R3 = R5, R4 = R6)

Figure 11. Alternative Set-Up for Coincident

Start-Up Tracking (R1 = R3, R2 = R3 = R5)

Figure 12. Set-Up for

Ratiometric Tracking

3615f

ꢁꢁ

LTC3615

applicaTions inForMaTion

External Reference Input (DDR Mode)

In DDR mode, the maximum slew rate is selected. If

V

is within 0.3V and 0.5V, the PGOOD function

TRACK/SS

is enabled. If V

If SRLIM is tied to SV , the TRACK/SS pin can be used

IN

is less than 0.3V, the output cur-

TRACK/SS

as an external reference input between 0.3V and 0.5V, if

rent foldback is disabled and the PGOOD pin is always

pulled down.

desired (see Figure 13).

0.6V

V

FB

VOLTAGE

0V

0.6V

TRACK/SS

PIN VOLTAGE

0.1V

0V

V

IN

RUN PIN

VOLTAGE

0V

V

IN

SV PIN

IN

VOLTAGE

0V

TIME

SHUTDOWN SOFT-START

RUN STATE

REDUCED

SWITCHING

FREQUENCY

RUN STATE

STATE

> 1ms

3615 F13

t

SS

DOWN-

UP-

TRACKING TRACKING

STATE STATE

Figure 13. Tracking if V_SRLIMIs Low

0.45V

0.3V

V

FB

VOLTAGE

0V

EXTERNAL

VOLTAGE

REFERENCE 0.45V

0.45V

0.3V

TRACK/SS

PIN VOLTAGE

0.1V

0V

V

IN

RUN PIN

VOLTAGE

0V

V

IN

SV PIN

IN

VOLTAGE

0V

TIME

SHUTDOWN SOFT-START

STATE STATE

> 1ms

RUN STATE

REDUCED

SWITCHING

FREQUENCY

RUN STATE

3615 F14

t

SS

DOWN-

UP-

TRACKING

STATE

TRACKING

STATE

Figure 14. Tracking if V_SRLIMIs Tied to SV_IN

3615f

ꢁꢂ

LTC3615

applicaTions inForMaTion

DDR Application

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of

The LTC3615 can be used in DDR memory power supply

2

the losses: V quiescent current and I R losses. The V

IN

applicationsbytyingtheSRLIMpintoSV . InDDRmode,

IN

quiescent current loss dominates the efﬁciency loss at

the maximum slew rate is selected. The output can both

sourceandsinkcurrent.Currentsinkingistypicallylimited

to 1.5A, for 1MHz frequency and 1µH inductance, but can

be lower at higher frequencies and low output voltages.

If higher ripple current can be tolerated, smaller inductor

values can increase the sink current limit. See the Typical

PerformanceCharacteristicscurvesformoreinformation.

In addition, in DDR mode, lower external reference volt-

ages and tracking output voltages between channels are

possible. See the Output Voltage Tracking Input section.

2

very low load currents whereas the I R loss dominates

the efﬁciency loss at medium to high load currents. In a

typical efﬁciency plot, the efﬁciency curve at very low load

currents can be misleading since the actual power lost is

of little consequence.

1. The V quiescent current is due to two components:

IN

the DC bias current as given in the Electrical Charac-

teristics and the internal main switch and synchronous

switch gate charge currents. The gate charge current

results from switching the gate capacitance of the

internal power MOSFET switches. Each time the gate

is switched from high to low to high again, a packet

Single, Low Ripple 6A Output Application

The LT3615 can generate a single, low ripple 6A output if

theoutputsofthetwoswitchingregulatorsaretiedtogether

and share a single output capacitor (see Figure 15 on back

ofdatasheet).Inordertoevenlysharethecurrentbetween

the two regulators, it is needed to connect pins FB1 to

FB2, ITH1 to ITH2 and to select forced continuous mode

at the MODE pin. To achieve lowest ripple, 90°, or better,

180°, antiphase is selected by connecting the PHASE pin

of charge dQ moves from V to ground. The resulting

IN

dQ/dt is the current out of V due to gate charge, and

IN

it is typically larger than the DC bias current. Both the

DC bias and gate charge losses are proportional to V ,

IN

thus, their effects will be more pronounced at higher

supply voltages.

2

2. I R losses are calculated from the resistances of the

to midrail or SV . There are several advantages to this

internal switches, R , and external inductor R . In

IN

SW

L

2-phase buck regulator. Ripple currents at the input and

output are reduced, reducing voltage ripple and allowing

the use of smaller, less expensive capacitors. Although

two inductors are required, each will be smaller than the

inductor required for a single-phase regulator. This may

be important when there are tight height restrictions on

the circuit.

continuous mode the average output current ﬂowing

through inductor L is “chopped” between the main

switch and the synchronous switch. Thus, the series

resistance looking into the SW pin is a function of both

top and bottom MOSFET R

(DC), as follows:

and the duty cycle

DS(ON)

R

SW

= (R )(DC) + (R )(1 – DC)

DS(ON)TOP DS(ON)BOT

Efﬁciency Considerations

The R

for both the top and bottom MOSFETs can

DS(ON)

be obtained from the Typical Performance Characteristics

Theefﬁciencyofaswitchingregulatorisequaltotheoutput

power divided by the input power times 100%. It is often

useful to analyze individual losses to determine what is

limiting the efﬁciency and which change would produce

the most improvement. Efﬁciency can be expressed as:

Efﬁciency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc.

are the individual losses as a percentage of input power.

2

curves. To obtain I R losses, simply add R to R and

SW

L

multiply the result by the square of the average output

current.

Otherlosses,includingC andC ESRdissipativelosses

IN

OUT

and inductor core losses, generally account for less than

2% of the total loss.

3615f

ꢁꢃ

LTC3615

applicaTions inForMaTion

Thermal Considerations

R

. It is not recommended to use full load current at

DS(ON)

high ambient temperature and low input voltage.

In most applications, the LTC3615 does not dissipate

much heat due to its high efﬁciency. However, in ap-

plications where the LTC3615 is running at high ambient

temperature with low supply voltage and high duty cycles,

such as in dropout, the heat dissipated may exceed the

maximum junction temperature of the part. If the junction

temperature reaches approximately 160°C, all four power

switches will be turned off and the SW node will become

high impedance.

To maximize the thermal performance of the LTC3615, the

Exposed Pad should be soldered to a ground plane. See

the PC Board Layout Checklist.

Design Example

As a design example, consider using the LTC3615 in an

application with the following speciﬁcations:

V = 3.3V to 5.5V

IN

To prevent the LTC3615 from exceeding the maximum

junction temperature, the user will need to do some ther-

mal analysis. To determine whether the power dissipated

exceeds the maximum junction temperature of the part.

The temperature rise is given by:

V

= 2.5V

= 1.2V

OUT1

OUT2

I

= 1A

= 3A

= 100mA

OUT1(MAX)

OUT2(MAX)

OUT(MIN)

T

RISE

= P • θ

JA

f = 2.25MHz

D

where P is the power dissipated by the regulator, and

JA

to the ambient temperature. The junction temperature,

T , is given by:

J

Because efﬁciency is important at both high and low load

current,BurstModeoperationwillbeselectedbyconnect-

ing the MODE pin to SGND.

D

θ

is the thermal resistance from the junction of the die

First, calculate the timing resistor:

T = T + T

RISE

J

A

4E11Ω • Hz

2.25MHz

R_RT/SYNC

=

= 178k

where T is the ambient temperature.

A

As an example, consider this case: the LTC3615 is in

dropout at an input voltage of 3.3V with a load current for

each channel of 2A at an ambient temperature of 70°C.

Assuming a 20°C rise in junction temperature, to 90°C,

Next, calculate the inductor values for about 1A ripple

current at maximum V :

IN



 



2.5V

2.25MHz • 1A

2.5V

5.5V

L1=

L2 =

• 1–

= 0.6µH





 

 





results in an R

of 0.086mΩ (see the graph in the

DS(ON)

Typical Performance Characteristics section). Therefore,

the power dissipated by the part is:



 



1.2V

5.5V

• 1–

= 0.42µH



 



2

2.25MHz • 1A



 



P = (I + I ) • R = 0.69W

DS(ON)

D

1

2

Using a standard value of 0.56µH and 0.47µH inductors

results in maximum ripple currents of:

For the QFN package, the θ is 37°C/W.

JA

Therefore,thejunctiontemperatureoftheregulatoroperat-

ing at 70°C ambient temperature is approximately:













2.5V

5.5V

∆I_L1

=

• 1–

= 1.08A













2.25MHz • 0.56µH

T = 0.69W • 37°C/W + 70°C = 95°C

J















1.2V

2.25MHz • 0.47µH

1.2V

5.5V

Note that for very low input voltage, the junction tem-

perature will be higher due to increased switch resistance

∆I_L2

=

• 1–

= 0.89A











3615f

ꢁꢄ

LTC3615

applicaTions inForMaTion

PC Board Layout Checklist

C

will be selected based on the ESR that is required

OUT

to satisfy the output voltage ripple requirement and the

bulk capacitance needed for loop stability. For this design,

47µF ceramic capacitors will be used with X5R or X7R

dielectric.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3615:

1. A ground plane is recommended. If a ground plane

layer is not used, the signal and power grounds should

be segregated with all small signal components return-

ing to the SGND pin at one point which is then con-

nected to the PGND node at the exposed pad close to

the LTC3615

C should be sized for a maximum current rating of:

IN

I_OUT1I_OUT2

I_RMS(MAX)

=

+

= 2A_RMS

2

Decoupling the PV with two 47µF capacitors is adequate

IN

for most applications.

2. Connect the (+) terminal of the input capacitors, C ,

IN

Finally, it is possible to deﬁne the soft-start up time choos-

ing the proper value for the capacitor and the resistor

as close as possible to the PV pins, and the (–) ter-

INx

minal as close as possible to the exposed pad PGND.

This capacitor provides the AC current into the internal

power MOSFETs.

connected to TRACK/SS pin. If one sets minimum T

=

SS

5ms and a resistor of 4.7M, the following equation can

be solved with the maximum SV = 5.5V:

IN

3. Keep the switching nodes, SWx, away from all sensitive

small signal nodes FBx, ITHx, RTSYNC, SRLIM.

5ms

C_SS

=

= 9.2nF





5.5V

4.Floodallunusedareasonalllayerswithcopper.Flooding

with copper will reduce the temperature rise of power

components. Connect the copper areas to PGND (ex-

posed pad) for best performance.

4.7M • In









5.5V – 0.6V

The standard value of 10nF and 4.7M guarantees the

minimum soft-start time of 5ms. In Figure 3, channel 1

shows the schematic for this design example.

5. Connect the V pins directly to the feedback resistors.

FBx

The resistor divider must be connected between V

and SGND.

OUTx

3615f

ꢁꢅ

LTC3615

Typical applicaTions

External Compensation, Forced Continuous Operation,

In-Phase Switching, Slew Rate Limit, Common PGOOD Output

V

IN

3.3V

47µF

1µF

SV

(2s) PV

IN2

(2s) SW1

IN

IN1

0.47µH

V

OUT1

1.8V/3A

RUN

RUN1

R1

47µF

TRACK/SS1

412k

PGOOD1

ITH1

FB1

MODE

R2

205k

R

178k

LTC3615

T

10pF

R

C1

43k

R /SYNC

T

C

R5

40.2k

C1

220pF

0.47µH

V

OUT2

2.5V/3A

(2s) SW2

SRLIM

MODE

PHASE

47µF

R3

665k

FB2

R6

226k

R7

174k

R4

210k

RUN2

TRACK/SS2

100k

PGOOD2

PGOOD

ITH2 SGND

PGND

3615 TA02

R

10pF

C2

43k

C

C2

220pF

V_OUT1Waveform

V_OUT2Waveform

V

OUT2

100mV/DIV

OUT1

100mV/DIV

I

OUT2

1A/DIV

OUT1

1A/DIV

3615 TA02b

3615 TA02c

20µs/DIV

3615f

ꢁꢆ

LTC3615

Typical applicaTions

DDR Memory Termination

V

IN

3.3V

C

IN1

47µF

C

IN3

1µF

IN2

47µF

L1

0.47µH

SV (2s) PV

(2s) PV

IN2

IN

IN1

V

DDQ

RUN1

(2s) SW1

1.8V/3A

TRACK/SS1

C

R3

150k

R1

121k

OUT1

47µF

PGOOD1

ITH1

FB1

C1

R10

15k

C2

R2

R4

10pF

R /SYNC

T

60.4k

49.9k

LTC3615

SRLIM

MODE

1000pF

L2

0.47µH

R9

226k

V

TT

R8

174k

0.9V

(2s) SW2

3A/–1.5A

OUT2

PHASE

RUN2

R5

49.9k

C

47µF

FB2

TRACK/SS2

PGOOD2

R6

49.9k

ITH2 SGND PGND

C3

10pF

3615 TA03a

R7

15k

C4

1000pF

Ratiometric Start-Up

V

DD

500mV/

DIV

V

TT

3615 TA03b

500µs/DIV

3615f

ꢁꢇ

LTC3615

Typical applicaTions

Master and Slave for Coincident Tracking Outputs Using a 2MHz External Clock

R

F1

24Ω

C

F1

1µF

V

IN

3.3V

C1

47µF

C2

47µF

L1

0.47µH

4.7M

V

OUT1

SV

(2s) PV (2s) PV

IN1 IN2

IN

1.8V/3A

C3

22pF

(2s) SW1

RUN1

TRACK/SS1

C

O12

22µF

R3

453k

R1

715k

O11

47µF

10nF

FB1

R5

100k

R2

357k

R4

453k

LTC3615

C

SYNC

PGOOD1

T

ITH1

PGOOD1

R

15pF

R /SYNC

2MHz

CLOCK

C

C2

R

T

C1

10pF

SRLIM

MODE

200k

15k

L2

C

C1

0.47µH

1000pF

V

R9

226k

OUT2

(2s) SW2

1.2V/3A

R8

174k

R5

294k

C

O21

O22

PHASE

RUN2

47µF

22µF

C7

22pF

FB2

R7

100k

TRACK/SS2

R6

294k

PGOOD2

ITH2 SGND

PGND

C

C4

R

C2

10pF

15k

C

C3

3615 TA04a

470pF

Coincident Start-Up

Coincident Tracking Up/Down

V

OUT1

V

OUT1

V

OUT2

500mV/

DIV

500mV/

DIV

V

OUT2

3615 TA04b

3615 TA04c

2ms/DIV

200ms/DIV

3615f

ꢁꢈ

LTC3615

package DescripTion

FE Package

24-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation AA

7.70 – 7.90*

3.25

(.128)

(.303 – .311)

3.25

(.128)

24 23 22 21 20 19 18 17 16 15 14 13

6.60 p0.10

2.74

(.108)

4.50 p0.10

6.40

(.252)

BSC

2.74

(.108)

SEE NOTE 4

0.45 p0.05

1.05 p0.10

0.65 BSC

5

7

8

1

2

3

4

6

9 10 11 12

RECOMMENDED SOLDER PAD LAYOUT

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0o – 8o

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.195 – 0.30

FE24 (AA) TSSOP 0208 REV Ø

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

3615f

ꢂ0

LTC3615

package DescripTion

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1697)

0.70 ±0.05

4.50 ± 0.05

3.10 ± 0.05

2.45 ± 0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

BOTTOM VIEW—EXPOSED PAD

R = 0.115

PIN 1 NOTCH

R = 0.20 TYP OR

0.35 × 45° CHAMFER

0.75 ± 0.05

4.00 ± 0.10

(4 SIDES)

TYP

23 24

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

1

2

2.45 ± 0.10

(4-SIDES)

(UF24) QFN 0105

0.200 REF

0.25 ± 0.05

0.50 BSC

0.00 – 0.05

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3615f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

ꢂꢀ

LTC3615

Typical applicaTion

V

IN

3.3V

V

47µF

1µF

SW1

SW2

SV

(2s) (2s)

PV PV

IN

RUN1

IN1

IN2

L1

0.47µH

V

OUT

(2s)

SW1

TRACK/SS1

PGOOD1

ITH1

1.2V/6A

47µF

2V/DIV,

1A/DIV

R1

102k

FB1

I

L1

I

L2

LTC3615

R2

102k

20pF

L2

0.47µH

R /SYNC

T

I

+ I

L1 L2

R

C

SRLIM

(2s) SW2

7.5k

3615 F16

200ns/DIV

FB2

C

MODE

C

MODE = FCM

2000pF

R8

226k

R9

174k

PHASE

Figure 16. Reduced Ripple Current

(Waveform I_L1+ I_L2) and Ripple Voltage

(Not Shown) Through 180° Phase Shift

Between SW1 and SW2

RUN2

TRACK/SS2

PGOOD2

ITH2 SGND

PGND

3615 F15

100

90

V

= 1.2V

OUT

MODE = FCM

Figure 15. Single, Low Ripple 6A Output

80

70

60

50

40

30

20

10

0

V

= 2.5V

= 3.3V

= 5V

IN

0.01

0.1

1

10

OUTPUT CURRENT (A)

3615 F17

Figure 17. Efﬁciency vs Load Current

for V_OUT= 1.2V and I_OUTUp to 6A

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

LTC3633

LTC3546

LTC3417A-2

LTC3612

LTC3614

LTC3616

15V, Dual 3A, 4MHz, Synchronous Step-Down DC/DC 95% Efﬁciency, V : 3.60V to 15V, V

= 0.6V, I = 500µA, I < 13µA,

OUT(MIN) Q SD

IN

Converter

4mm × 5mm QFN-28 and TSSOP-28E Packages

5.5V, Dual 3A/1A, 4MHz, Synchronous Step-Down

DC/DC Converter

95% Efﬁciency, V : 2.25V to 5.5V, V

= 0.6V, I = 160µA, I < 1µA,

Q SD

IN

OUT(MIN)

4mm × 5mm QFN-28 Package

5.5V, Dual 1.5A/1A, 4MHz, Synchronous Step-Down

DC/DC Converter

95% Efﬁciency, V : 2.25V to 5.5V, V

= 0.8V, I = 125µA, I < 1µA,

Q SD

IN

TSSOP-16E and 3mm × 5mm DFN-16 Packages

5.5V, 3A, 4MHz, Synchronous Step-Down DC/DC

Converter

95% Efﬁciency, V : 2.25V to 5.5V, V = 0.6V, I = 75µA, I < 1µA,

IN

OUT(MIN)

Q

SD

3mm × 4mm QFN-20 and TSSOP-20E Packages

5.5V, 4A, 4MHz, Synchronous Step-Down DC/DC

Converter

95% Efﬁciency, V : 2.25V to 5.5V, V = 0.6V, I = 75µA, I < 1µA,

IN

OUT(MIN)

Q

SD

3mm × 4mm QFN-20 and TSSOP-20E Packages

5.5V, 6A, 4MHz, Synchronous Step-Down DC/DC

Converter

95% Efﬁciency, V : 2.25V to 5.5V, V

= 0.6V, I = 75µA, I < 1µA,

OUT(MIN) Q SD

IN

3mm × 5mm QFN-24 Package

3615f

LT 0410 • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

ꢂꢁ

●

 LINEAR TECHNOLOGY CORPORATION 2010

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3615EUF-TRPBF
厂家：	Linear
描述：	Dual 4MHz, 3A Synchronous Step-Down DC/DC Converter 双4MHz时， 3A同步降压型DC / DC转换器转换器
文件：	总32页 (文件大小：2949K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3615EUF-TRPBF [Linear]

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