LTC3617_15_技术文档

LTC3617

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Features

Description

TheLTC^®3617isahighefficiencymonolithicsynchronous

buckregulatorutilizingacurrentmode,constantfrequency

architecture. It operates from an input voltage range of

2.25V to 5.5V and provides a regulated output voltage

equal to 0.5 • VDDQIN while sourcing and sinking up to

6A of load current. An internal amplifier provides a VTTR

output voltage equal to 0.5 • VDDQIN with an output cur-

rent capability of 1ꢀmA.

n

6A Output Current

n

2.25V to 5.5V Input Voltage Range

n

±±10V Output Voltage Accuracy

n

Opti0ized for Low Output Voltages Down to 1.5V

n

High Efficiency

n

Integrated Buffer for VTTR = VDDQIN • 0.5

n

Shutdown Current: <1µA

n

Adjustable Switching Frequency: Up to 4MHz

n

Optional Internal Compensation

The operating frequency is externally programmable up to

4MHz, allowing the use of small surface mount inductors.

For switching-noise-sensitive applications, the LTC3617

can be synchronized to an external clock up to 4MHz.

n

Internal Soft-Start

n

Power Good Status Output

n

Input Overvoltage Protected

n

Thermally Enhanced 24-Pin 3mm × 5mm

ForcedcontinuousmodeoperationintheLTC3617reduces

noise and RF interference. Adjustable external compensa-

tion allows the transient response to be optimized over a

wide range of loads and output capacitors.

QFN Package

applications

n

DDR Termination

The internal synchronous switch increases efficiency and

eliminatestheneedforanexternalcatchdiode,minimizing

external component count and board space. The LTC3617

is offered in a leadless 24-pin 3mm × 5mm thermally

enhanced QFN package.

n

Supports DDR, DDR2 and DDR3 Standards

n

Tracking Supplies

L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks

of Linear Technology Corporation. All other trademarks are the property of their respective

owners. Protected by U.S. Patents, including 6580258, 5481178, 6498466, 6611131.

Efficiency and Power Loss

vs Load Current

typical application

100

90

80

70

60

50

40

30

20

10

0

10

V

IN

2.5V

22µF

×4

SV

PV

IN

V

REF

RUN

VDDQIN

RT

VTTR

1.25V

10ꢀm

1

0.1µF

0.15µH

VTT

1.25V

6m

LTC3617

SW

PGOOD

ITH

SGND

PGND

47µF

×2

0.1

0.01

SYNC

V

FB

3617 Tm01a

0.1

1

10

LOAD CURRENT (A)

3617 TA01b

3617fa

1

LTC3617

absolute MaxiMuM ratings

pin conFiguration

(Note ±)

TOP VIEW

PV , SV Voltages ..................................... –ꢀ.3V to 6V

IN

SW Voltage ................................. –0.3V to (PV + ꢀ.3V)

IN

ITH, RT, SYNC Voltages.............. –0.3V to (SV + ꢀ.3V)

IN

24 23 22 21

VTTR, RUN, V Voltages ........... –0.3V to (SV + ꢀ.3V)

FB

IN

RT

SGND

VTTR

SYNC

RUN

1

2

3

4

5

6

7

8

20

19

18

17

16

15

14

13

VDDQIN, PGOOD Voltages........................... –ꢀ.3V to 6V

Operating Junction Temperature Range

SV

IN

(Notes 2, 8)............................................ –4ꢀ°C to 125°C

Storage Temperature.............................. –65°C to 15ꢀ°C

PV

IN

PV

IN

25

PGND

SW

9

10 11 12

UDD PACKAGE

24-LEAD (3mm × 5mm) PLASTIC QFN

= 125°C, θ = 43°C/W

T

JMAX

JA

EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB

orDer inForMation

LEAD FREE FINISH

LTC3617EUDD#PBF

LTC3617IUDD#PBF

TAPE AND REEL

PART MARKING*

LFXC

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3617EUDD#TRPBF

LTC3617IUDD#TRPBF

–4ꢀ°C to 125°C

24-Lead (3mm × 5mm) Plastic QFN

LFXC

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

electrical characteristics ^Thel denotes the specifications which apply over the full operating junction

te0perature range, otherwise specifications are at T_A= 25°C. PV_IN= SV_IN= 3.3V, RT = SV_INunless otherwise specified (Notes ±, 2, 8).

SYMBOL

PARAMETER

CONDITIONS

MIN

2.25

1.7

TYP

MAX

UNITS

l

V

Input Voltage Operating Range

Undervoltage Lockout Threshold

5.5

V

IN

l

SV Ramping Down

V

UVLO

IN

SV Ramping Up

2.2

7

IN

V

Overvoltage Lockout Threshold

SV Ramping Up

6.5

25ꢀ

V

mV

OVLO

IN

Hysteresis

l

VTTR

VTTR Output Voltage with Line and Load VDDQIN = 1.5V, Load = ±10mA

Regulation

0.49 • VDDQIN 0.5 • VDDQIN 0.51 • VDDQIN

V

VTTR Maximum Output Current

1ꢀ

mA

mV

nA

l

V

Feedback Voltage Accuracy

Feedback Input Current

VDDQIN = 1.5V (Note 3)

V = ꢀ.75V

FB

VTTR – 1ꢀ

VTTR

VTTR + 1ꢀ

3ꢀ

FB

I

FB

3617fa

2

LTC3617

electrical characteristics ^Thel denotes the specifications which apply over the full operating junction

te0perature range, otherwise specifications are at T_A= 25°C. PV_IN= SV_IN= 3.3V, RT = SV_INunless otherwise specified (Notes ±, 2, 8).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Feedback Voltage Line Regulation

SV = PV = 2.25V to 5.5V,

ꢀ.2

%/V

∆V

IN

FB(LINEREG)

VDDQIN = 1.5V (Notes 3, 4)

Feedback Voltage Load Regulation

ITH from 0.5V to 0.9V (Notes 3, 4)

ITH

ꢀ.25

%

∆V

FB(LOADREG)

V

= SV (Note 5)

IN

I

Input DC Supply Current

Active Mode

Q

V

= 0.6V, VDDQIN = 1.5V (Note 6)

11ꢀꢀ

ꢀ.1

µA

FB

Shutdown

SV = PV = 5.5V, V = ꢀV

RUN

1

IN

R

Top Switch On-Resistance

PV = 3.3V

35

25

mΩ

A

DS(ON)

IN

Bottom Switch On-Resistance

Top Switch Positive Peak Current Limit

PV = 3.3V

IN

I

Sourcing (Note 7), V = ꢀ.5V

8

1ꢀ

14

–5

LIM

FB

Top Switch Negative Peak Current Limit Sinking (Note 7)

Error Amplifier Transconductance –5µA < I < 5µA (Note 4)

Error Amplifier Maximum Output Current (Note 4)

–12

–8

A

g

2ꢀꢀ

3ꢀ

µS

µA

ms

m(EA)

ITH

I

t

EAO

Internal Soft-Start Time

V

from ꢀ.ꢀ75V to ꢀ.675V,

FB

ꢀ.4

0.85

2

SS

VDDQIN = 1.5V

l

f

Oscillator Frequency

Internal Oscillator Frequency

R = 37ꢀk

0.8

1.8

1

2.25

1.2

2.7

MHz

OSC

T

V

= SV

RT

IN

f

Synchronization Frequency Range

ꢀ.3

1.2

4

MHz

SYNC

V

SYNC Input Threshold High Voltage

SYNC Input Threshold Low Voltage

V

SYNC

ꢀ.3

1

I

Switch Leakage Current

SV = PV = 5.5V, V = ꢀV

RUN

ꢀ.1

µA

SW(LKG)

IN

PGOOD

Power Good Voltage Windows

VDDQIN = 1.5V, Entering Window

V

Ramping Up

–3.5

3.5

–5

5

%

FB

Ramping Down

VDDQIN = 1.5V, Leaving Window

V

Ramping Up

8

–8

1ꢀ

–1ꢀ

%

FB

Ramping Down

t

Power Good Blanking Time

Power Good Pull-Down On-Resistance

RUN voltage

Entering and Leaving Window

7ꢀ

8

1ꢀ5

17

14ꢀ

33

µs

PGOOD

R

Ω

PGOOD

l

V

Input High

Input Low

1

V

RUN

ꢀ.4

Note ±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: This parameter is tested in a feedback loop which servos V to

FB

the midpoint for the error amplifier (V = ꢀ.75V).

ITH

Note 4: External compensation on ITH pin.

Note 5: Tying the ITH pin to SV enables the internal compensation.

IN

Note 2: The LTC3617 is tested under pulsed load conditions such that

Note 6: Dynamic supply current is higher due to the internal gate charge

being delivered at the switching frequency.

T ≈ T . The LTC3617E is guaranteed to meet performance specifications

J

A

over the 0°C to 85°C operating junction temperature range. Specifications

over the –4ꢀ°C to 125°C operating junction temperature range are

assured by design, characterization and correlation with statistical process

controls. The LTC3617I is guaranteed to meet specifications over the

full –40°C to 125°C operating junction temperature range. Note that

the maximum ambient temperature is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

resistance and other environmental factors. The junction temperature

Note 7: In sourcing mode the average output current is flowing out of the

SW pin. In sinking mode the average output current is flowing into the SW

Pin.

Note 8: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

(T , in °C) is calculated from the ambient temperature (T , in °C) and

J

A

power dissipation (P , in watts) according to the formula:

D

T = T + (P • θ ), where θ (in °C/W) is the package thermal

J

A

D

JA

impedance.

3617fa

3

LTC3617

typical perForMance characteristics

T_A= 25°C, V_IN= 3.3V, f_O= ±MHz unless otherwise noted.

Efficiency vs Load Current

Efficiency vs Input Voltage

Efficiency vs Frequency

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

100

95

90

85

80

75

70

65

60

V

= 1.25V

V

= 1.25V

V

= 1.25V

OUT

I

= 600mA

= 2A

V

= 2.5V

= 3.3V

= 5V

150nH

330nH

470nH

LOAD

OUT

IN

= 6A

2.25 2.75 3.25 3.75 4.25 4.75 5.25

0.1

1

10

1

1.5

2

2.5

3

3.5

4

INPUT VOLTAGE (V)

LOAD CURRENT (A)

FREQUENCY (MHz)

3617 G01

3617 G02

3617 G03

Load Regulation

Line Regulation

Output Voltage vs Ti0e

0.3

0.2

0.3

V

= 1.25V

OUT

0.2

0.1

SW

2V/DIV

0.1

0

V

OUT

20mV/DIV

–0.1

–0.2

–0.3

–0.1

–0.2

–0.3

I

L

1A/DIV

3617 G06

V

LOAD

= 1.25V

= 100mA

2µs/DIV

–6

–4

–2

0

2

4

6

2.20

3.30 3.85 4.40

INPUT VOLTAGE (V)

4.95 5.50

2.75

OUT

I

LOAD CURRENT (A)

3617 G04

3617 G05

Load Step Transient

V

OUT

200mV/DIV

100mV/DIV

I

L

I

L

5A/DIV

4A/DIV

3617 G07

3617 G09

40µs/DIV

V

LOAD

= 1.25V

V

LOAD

= 1.25V

OUT

I

= 100mA TO 6A

COMPENSATION FIGURE 1

I

= –6A TO 6A

COMPENSATION FIGURE 1

3617fa

4

LTC3617

typical perForMance characteristics

T_A= 25°C, V_IN= 3.3V, f_O= ±MHz unless otherwise noted.

Sinking Current Internal Start-Up

Tracking Up/Down

RUN

5V/DIV

PGOOD

5V/DIV

PGOOD

5V/DIV

SW

2V/DIV

V

/VTTR

OUT

500mV/DIV

V

OUT

V

OUT

500mV/DIV

20mV/DIV

VDDQIN

2V/DIV

I

L

I

L

2A/DIV

3617 G10

3617 G11

3617 G12

2ms/DIV

2µs/DIV

500µs/DIV

V

I

= 1.25V

= –3A

V

I

= 1.25V

= 0A

OUT

LOAD

OUT

LOAD

V

LOAD

= 1.25V

= 3A

OUT

I

Switch On-Resistance

vs Input Voltage

Switch On-Resistance

vs Te0perature

50

40

30

20

10

0

50

40

30

20

10

0

MAIN SWITCH

SYNCHRONOUS SWITCH

2.5

3.0

3.5

4.0

4.5

5.0

5.5

–50 –30 –10 10 30 50

130

70 90 110

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3617 G15

3617 G14

Frequency vs R_TResistor

Frequency vs Te0perature

0.8

0.6

4.5

R

= SV

IN

R

T

= SV

IN

T

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

0

–50 –30 –10 10 30 50 70 90 100 130

0

200 400 600

1400

800 1000 1200

TEMPERATURE (°C)

RESISTOR ON RT/SYNC PIN (kΩ)

3617 G17

3617 G16

3617fa

5

LTC3617

typical perForMance characteristics

T_A= 25°C, V_IN= 3.3V, f_O= ±MHz unless otherwise noted.

Switch Leakage Current

vs Te0perature, Main Switch

Frequency vs Input Voltage

1.0

0.5

8

7

6

5

4

3

2

1

0

V

= 2.25V

= 3.3V

= 5.5V

IN

0

–0.5

–1.0

–1.5

–2.0

–2.5

2.25

3.75 4.25 4.75 5.25

30 50

2.75 3.25

–50 –30 –10 10

70 90 110 130

INPUT VOLTAGE (V)

TEMPERATURE (°C)

3617 G18

3617 G19

Dyna0ic Supply Current

vs Te0perature

Switch Leakage Current vs

Te0perature, Synchronous Switch

50

40

30

20

10

0

8

7

6

5

4

3

2

1

0

V

= 2.25V

= 3.3V

= 5.5V

IN

V

= 2.5V

= 3.3V

= 5V

IN

30 50

TEMPERATURE (°C)

–50 –30 –10 10

70 90 110 130

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

3617 G20

3617 G21

3617fa

6

LTC3617

pin Functions

RT (Pin ±): Oscillator Frequency. This pin provides two

ways of setting the constant switching frequency:

SYNC (Pin 21): External Synchronization Input. When

a clock signal is applied to this pin, the switching fre-

quency synchronizes to this clock signal. This pin can

be either floating or tied to ground if an external clock

is not being used.

1. Connecting a resistor from RT to ground will set the

switching frequency based on the resistor value.

2. Tying the RT pin to SV enables the internal 2.25MHz

IN

PGOOD (Pin 2±): Power Good. This open-drain output

is pulled down to SGND on start-up and when the FB

voltage is outside the power good voltage window. If the

FB voltage increases and stays inside the power good

window for more than 100µs the PGOOD pin is released.

If the FB voltage leaves the power good window for more

than 100µs the PGOOD pin is pulled low.

oscillator frequency.

SGND (Pin 2): Signal Ground. All small-signal and com-

pensation components should connect to this ground,

which in turn should connect to PGND at a single point.

VTTR (Pin 3): Voltage Buffer Output. This pin is the output

of an internal voltage buffer whose voltage is equal to

VDDQIN • 0.5. Output current capability is ±10mA. VTTR

is also the reference voltage of the error amplifier, which

sets the output voltage. V will regulate to VTTR. Do not

exceed 0.1µF capacitance on this pin.

The power good window moves in relation to the VDDQIN

pin voltage. In shutdown the PGOOD output will actively

pull low and may be used to discharge the output capaci-

tors via an external resistor.

FB

PV (Pins 4, ±1, ±±, ±7): Power Input Supply. PV con-

V

(Pin 22): Voltage Feedback Input Pin. Senses the

IN

FB

nectstothesourceoftheinternalP-channelpowerMOSFET.

feedbackvoltagefromtheexternalresistivedivideracross

This pin is independent of SV and may be connected to

the output.

IN

the same supply or to a lower voltage.

ITH (Pin 23): Error Amplifier Compensation. The current

comparator’sthresholdincreaseswiththiscontrolvoltage.

Tying this pin to SV_INenables internal compensation.

SW (Pins 5, 6, 7, 8, ±3, ±4, ±5, ±6): Switch Node. Con-

nection to the inductor. These pins connect to the drains

of the internal power MOSFET switches.

VDDQIN (Pin 24): External Reference Input. An internal

NC (Pins 9, ±2): Can be connected to ground or left open.

resistor divider sets the VTTR and V regulated voltages

FB

to be equal to half the voltage applied to this input.

SV (Pin ±8): Signal Input Supply. This pin powers the

IN

internal control circuitry and is monitored by the under-

PGND (Exposed Pad Pin 25): Power Ground. This pin

connects to the source of the internal N-channel power

MOSFET. This pin should be connected close to the (–)

voltage lockout comparator.

RUN (Pin ±9): Enable Input. Pulling this pin high enables

the LTC3617 and forcing it to ground shuts the regulator

down. In shutdown, all functions are disabled and the chip

draws <1µA of supply current.

terminal of C and C

.

IN

OUT

3617fa

7

LTC3617

Functional block DiagraM

18

2

1

20

23

4

10

PV PV PV PV

IN

11

17

SV

SGND

RT

SYNC

ITH

IN

ITH SENSE

COMPARATOR

+

–

BANDGAP

AND

BIAS

RUN

INTERNAL

COMPENSATION

CURRENT

SENSE

19

OSCILLATOR

SV – 0.3V

IN

VTTR

3

PMOS CURRENT

COMPARATOR

–

VDDQIN

ITH

LIMIT

24

+

–

+

SOFT-START

SLOPE

COMPENSATION

SW

5

6

+

–

DRIVER

V

FB

22

7

ERROR

AMPLIFIER

8

1.08V

/2

DDQIN

+

–

13

14

15

16

LOGIC

+

–

REVERSE CURRENT

COMPARATOR

0.92V

/2

DDQIN

+

–

I

REV

PGND

25

V

+

–

TTR

EXPOSED PAD

0.45V

PGOOD

21

3617 BD

3617fa

8

LTC3617

operation

Main Control Loop

reference voltage of the error amplifier which controls the

output voltage. Therefore, large transients on this pin will

impact the behavior of the output.

The LTC3617 is a monolithic, constant frequency, current

mode step-down DC/DC converter. During normal opera-

tion, the internal top power switch (P-channel MOSFET) is

turned on at the beginning of each clock cycle. Current in

the inductor increases until the current comparator trips

and turns off the top power switch. The peak inductor

current when the current comparator trips is controlled

by the voltage on the ITH pin. The error amplifier adjusts

the voltage on the ITH pin by comparing the feedback

V Overvoltage Protection

IN

In order to protect the internal power MOSFET devices

against transient voltage spikes, the LTC3617 constantly

monitors the V pin for an overvoltage condition. When

IN

V rises above 6.5V, the regulator suspends operation by

IN

shutting off both MOSFETS. The regulator executes its

soft-start function when exiting an overvoltage condition.

signal from a resistor divider on the V pin with a refer-

FB

ence voltage on the VTTR pin. VTTR is the output of an

op amp buffer that expresses one-half the voltage on the

VDDQIN pin. When the load current increases, it causes a

reduction in the feedback voltage relative to the reference.

The error amplifier raises the ITH voltage until the average

inductor current matches the new load current. Typical

voltage range for the ITH pin is from 0.2V to 1.05V with

ꢀ.575V corresponding to zero current.

Low Supply Operation

The LTC3617 is designed to operate down to an input

supplyvoltageof2.25V. Animportantconsiderationatlow

input supply voltages is that the R

andN-channelpowerswitchesincreases. Theusershould

calculate the power dissipation when the LTC3617 is used

at 100% duty cycle with low input voltages to ensure that

thermal limits are not exceeded. See the Typical Perfor-

mance Characteristics graphs.

of the P-channel

DS(ON)

When the top power switch shuts off, the synchronous

bottom power switch (N-channel MOSFET) turns on until

either the bottom current limit is reached or the next clock

cycle begins. The bottom current limit is typically set at

–1ꢀA.

Short-Circuit Protection

The peak inductor current when the current comparator

shuts off the top power switch is controlled by the voltage

on the ITH pin.

The operating frequency defaults to 2.25MHz when RT is

connected to SV , or can be set by an external resistor

IN

Iftheoutputcurrentincreases, theerroramplifierraisesthe

ITH pin voltage until the average inductor current matches

the new load current. In normal operation the LTC3617

clampsthemaximumITHpinvoltageatapproximately1.ꢀ5V

which corresponds typically to 10A peak inductor current.

connected between the RT pin and ground, or by a clock

signal applied to the RT pin. The switching frequency can

be set from 3ꢀꢀkHz to 4MHz.

Overvoltage and undervoltage comparators pull the

PGOOD output low if the output voltage varies more than

±8% (typical) from the set point.

When the output is shorted to ground, the inductor cur-

rent decays very slowly during a single switching cycle.

To prevent current runaway from occurring, a secondary

current limit is imposed on the inductor current. If the

inductor current measured through the bottom MOSFET

increases beyond 12A typical, the top power MOSFET will

be held off and switching cycles will be skipped until the

inductor current decreases below this limit.

VTTR Voltage Buffer Output

An internal high accuracy op amp buffer generates a VTTR

pin voltage that is equal to VDDQIN • 0.5. VTTR can source

and sink up to 10mA and is stable with a maximum bypass

capacitor of 0.1µF. Short-circuit current limit is set around

2ꢀmA to prevent damage to the op amp. VTTR is also the

3617fa

9

LTC3617

applications inForMation

The basic LTC3617 application circuit is shown in Figure 1.

Tying the RT pin to SV sets the default internal operating

IN

frequency to 2.25MHz 2ꢀ%.

Operating Frequency

Frequency Synchronization

Selectionoftheoperatingfrequencyisatrade-offbetween

efficiency and component size. High frequency operation

allows the use of smaller inductor and capacitor values.

The LTC3617’s internal oscillator can be synchronized to

an external frequency by applying a square wave clock

signal to the SYNC pin. During synchronization, the top

switch turn-on is locked to the falling edge of the external

frequency source. The synchronization frequency range

is 3ꢀꢀkHz to 4MHz.

Operation at lower frequencies improves efficiency by

reducing internal gate charge losses but requires larger

inductance values and/or capacitance to maintain low

output voltage ripple.

The frequency set by the resistor on the RT pin should be

the same as the external clock frequency to ensure the

internal oscillator properly adjusts when the clock signal

is applied or removed.

The operating frequency of the LTC3617 is determined

by an external resistor that is connected between the RT

pin and ground. The value of the resistor sets the ramp

current that is used to charge and discharge an internal

timingcapacitorwithintheoscillatorandcanbecalculated

by using the following equation:

V

IN

LTC3617

SV

IN

f

OSC

RT

SYNC

SGND

3.82•10¹¹Hz

2.25MHz

R_T=

Ω –16kΩ

f_OSCHz

( )

Although frequencies as high as 4MHz are possible, the

minimum on-time of the LTC3617 imposes a minimum

limit on the operating duty cycle. The minimum on-time

is typically 80ns; therefore, the minimum duty cycle is

V

IN

LTC3617

SV

IN

0.4V

RT

SYNC

SGND

f

∝1/R

T

OSC

equal to 80ns•f (Hz)•100%.

R

OSC

T

V

IN

2.5V

C

V

IN

LTC3617

SV

22µF

SV

IN

PV

IN

×4

R

T

IN

f

RUN

VDDQIN

RT

VTTR

1.25V

10ꢁꢀ

OSC

P

RT

SYNC

SGND

1.2V

R

1/T

PG

VTTR

100k

0.1µF

R

T

L1

0.33µH

LTC3617

365k

V

OUT

1.25V

6ꢀ

SW

SGND

0.3V

C

OUT

PGOOD

T

P

100µF

R

C

10k

3617 F02

ITH

PGND

FB

C

C1

C

V

C

SYNC

10pF

Figure 2. Setting Switching Frequency

680pF

(OPT)

3617 F01

Figure ±. ±.25V, ±6A at ±MHz fro0 2.5V

3617fa

10

LTC3617

applications inForMation

Inductor Selection

exceeded. This results in an abrupt increase in inductor

ripple current and consequently output voltage ripple. Do

not allow a ferrite core to saturate!

For a given input and output voltage, the inductor value

and operating frequency determine the ripple current. The

ripple current ∆I increases with higher V and decreases

Different core materials and shapes will change the size/

currentandprice/currentrelationshipofaninductor.Toroid

or shielded pot cores in ferrite or permalloy materials are

small and don’t radiate much energy, but generally cost

more than powdered iron core inductors with similar

characteristics. The choice of which style inductor to use

mainly depends on the price versus size requirements

and any radiated field/EMI requirements. Table 1 shows

some typical surface mount inductors that work well in

LTC3617 applications.

L

IN

with higher inductance:









V_OUT

V_IN

∆I_L=

• 1–











f

•L







SW

Having a lower ripple current reduces the core losses

in the inductor, the ESR losses in the output capacitors

and the output voltage ripple. A reasonable starting point

for selecting the ripple current is ∆I = 0.3 • I

The largest ripple current occurs at the highest V . To

.

L

OUT(MAX)

IN

guarantee that the ripple current stays below a specified

maximum, theinductorvalueshouldbechosenaccording

to the following equation:

Input Capacitor (C ) Selection

IN

In continuous mode, the source current of the top P-

channel MOSFET is a square wave of duty cycle V

/

OUT



 





V . To prevent large input voltage transients, a low ESR

V_OUT

_SW• ∆I

V_OUT

IN

L =

• 1–



 

capacitor sized for the maximum RMS current must be

f

V



_L(MAX) 

_IN(MAX)

used at V .

IN

The maximum RMS capacitor current is given by:

Inductor Core Selection





V_OUT

V_IN

Oncethevalue forL isknown, thetypeofinductormust be

selected. Actual core loss is independent of core size for a

fixed inductor value, but it is very dependent on the induc-

tanceselected.Astheinductanceincreases,corelossesde-

crease.Unfortunately,increasedinductancerequiresmore

turnsof wireand therefore, copperlosseswillincrease.

I_RMS=I_OUT(MAX)

•

–1





V





OUT

ThisformulahasamaximumatV = 2 • V ,whereI =

RMS

IN

OUT

I

/2.Thissimpleworst-caseconditioniscommonlyused

OUT

fordesignbecauseevensignificantdeviationsdonotoffer

muchrelief.Notethatripplecurrentratingsfromcapacitor

manufacturers are often based on only 2ꢀꢀꢀ hours of life

which makes it advisable to further derate the capacitor,

or choose a capacitor rated at a higher temperature than

required.Severalcapacitorsmayalsobeparalleledtomeet

size or height requirements in the design.

Ferrite designs have very low core losses and are pre-

ferred at high switching frequencies, so design goals can

concentrate on copper loss and preventing saturation.

Ferritecorematerialsaturates“hard,”meaningthatinduc-

tance collapses abruptly when the peak design current is

3617fa

11

LTC3617

applications inForMation

Table ±. Representative Surface Mount Inductors

where f

= operating frequency, C

L

= output capaci-

OUT

OSC

tance and ∆I = ripple current in the inductor. The output

INDUCTANCE

(μH)

DCR

(0Ω)

SATURATION

CURRENT (A)

DIMENSIONS

(00)

HEIGHT

(00)

ripple is highest at maximum input voltage since ∆I

increases with input voltage.

L

Vishay IHLP-2525CZ-1±

ꢀ.1ꢀ

ꢀ.15

ꢀ.2ꢀ

ꢀ.22

ꢀ.33

ꢀ.47

1.5

1.9

2.4

2.5

3.5

4

6ꢀ

52

41

4ꢀ

3ꢀ

26

3

6.5 × 6.9

In surface mount applications, multiple capacitors may

have to be paralleled to meet the capacitance, ESR or RMS

currenthandlingrequirementoftheapplication.Aluminum

electrolytic, special polymer, ceramic and dry tantalum

capacitors are all available in surface mount packages.

Tantalumcapacitorshavethehighestcapacitancedensity,

but can have higher ESR and must be surge tested for

use in switching power supplies. Aluminum electrolytic

capacitors have significantly higher ESR, but can often

be used in extremely cost-sensitive applications provided

that consideration is given to ripple current ratings and

long-term reliability.

Su0ida CDMC6D28 Series

ꢀ.2

ꢀ.3

2.5

3.2

4.2

21.7

15.4

13.6

3

7.25 × 6.5

ꢀ.47

Cooper HCM1713 Series

ꢀ.22

ꢀ.47

0.68

2.8

4.2

5.5

4ꢀ

26

25

3.ꢀ

6.8 × 7.1

Cera0ic Input and Output Capacitors

Würth Electronik WE-HC7443±1 Series

Ceramic capacitors have the lowest ESR and can be cost

effective, but also have the lowest capacitance density,

havehighvoltageandtemperaturecoefficients,andexhibit

audible piezoelectric effects. In addition, the high Q of

ceramic capacitors along with trace inductance can lead

to significant ringing.

ꢀ.24

ꢀ.52

1.8

4ꢀ

2ꢀ

3.ꢀ

7 × 6.9

3.7

Coilcraft SLC7531 Series

ꢀ.1ꢀꢀ

0.188

ꢀ.272

ꢀ.35ꢀ

ꢀ.4ꢀꢀ

ꢀ.123

ꢀ.1ꢀꢀ

2ꢀ

21

14

11

8

3

7.5 × 6.7

They are attractive for switching regulator use because of

their very low ESR, but care must be taken when using

only ceramic input and output capacitors.

Ceramic capacitors are prone to temperature effects

which require the designer to check loop stability over

the operating temperature range. To minimize their large

temperature and voltage coefficients, only X5R or X7R

ceramic capacitors should be used.

Output Capacitor (C ) Selection

OUT

The selection of C

is typically driven by the required

OUT

ESR to minimize voltage ripple and load step transients

(low ESR ceramic capacitors are discussed in the next

section). Typically, once the ESR requirement is satisfied,

the capacitance is adequate for filtering. The output ripple

Whenaceramiccapacitorisusedattheinputandthepower

is being supplied through long wires, such as from a wall

adapter, a load step at the output can induce ringing at the

∆V

is determined by:

OUT

V pin. At best, this ringing can couple to the output and









1

IN

∆V_OUT≤ ∆I_L• ESR+

be mistaken as loop instability. At worst, the ringing at the



8 • f_SW•C

_OUT

input can be large enough to damage the part.

3617fa

12

LTC3617

applications inForMation

V

OUT

Since the ESR of a ceramic capacitor is so low, the input

and output capacitor must instead fulfill a charge storage

requirement.Duringaloadstep,theoutputcapacitormust

instantaneously supply the current until the feedback loop

raises the switch current enough to support the load. The

timerequiredforthefeedbacklooptorespondisdependent

on the compensation components and the output capaci-

tor size. Typically, 3 to 4 switching cycles are required to

respond to a load step, but only in the first cycle does the

R2

V

FB

LTC3617

SGND

R1

3617 F03

Figure 3. Setting the Output Voltage

Internal and External Co0pensation

output drop linearly. The output droop, V

, is usually

DROOP

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC load current.

about2to4timesthelineardropofthefirstcycle;however,

this behavior can vary depending on the compensation

component values. Thus, a good place to start is with the

output capacitor size of approximately:

When a load step occurs, V

shifts by an amount equal

OUT

to ∆I

• ESR, where ESR is the effective series resis-

LOAD

tance of C . ∆I

3.5• ∆I_OUT

f_SW• V_DROOP

also begins to charge or discharge

OUT

LOAD

C_OUT

≈

C

, generating the feedback error signal that forces the

OUT

regulatortoadapttothecurrentchangeandreturnV

to

OUT

This is only an approximation; more capacitance may

be needed depending on the duty cycle and load step

requirements.

its steady-state value. During this recovery time V

can

OUT

be monitored for excessive overshoot or ringing, which

would indicate a stability problem. The availability of the

ITH pin allows the transient response to be optimized over

a wide range of output capacitance.

Inmostapplications,theinputcapacitorismerelyrequired

to supply high frequency bypassing, since the impedance

to the supply is very low.

The ITH external components (R and C ) shown in Fig-

C

ure 1 provide adequate compensation as a starting point

for most applications. The values can be modified slightly

to optimize transient response once the final PCB layout

is done and the particular output capacitor type and value

have been determined. The output capacitors need to be

selected because the various types and values determine

the loop gain and phase. The gain of the loop will be in-

Output Voltage Progra00ing

In most applications, V

is connected directly to V .

FB

OUT

The output voltage will be equal to one-half of the voltage

on the VDDQIN pin for this case.

VDDQIN

V_OUT

=

2

creased by increasing R and the bandwidth of the loop

C

will be increased by decreasing C . If R is increased by

C

If a different output relationship is desired, an external

resistor divider from V to V can be used. The output

the same factor that C is decreased, the zero frequency

C

OUT

FB

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system. The external capaci-

voltagewillthenbesetaccordingtothefollowingequation:

VDDQIN

2

R2

R1







V_OUT

=

• 1+







tor, C , (Figure 1) is not needed for loop stability, but it

C1

helps filter out any high frequency noise that may couple

onto that node.

3617fa

13

LTC3617

applications inForMation

The first circuit in the Typical Applications section uses

faster compensation to improve step response.

pin to SV . However, selecting the internal compensation

IN

might result in an unstable output voltage when tracking

down to 0V.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

Shutdown and Soft-Start

The RUN pin provides a means to shut down the LTC3617.

Tying the RUN pin to SGND places the regulator in a low

with C , causing a rapid drop in V . No regulator can

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. More output

capacitance may be required depending on the duty cycle

and load step requirements.

quiescent current shutdown state (I < 1µA).

Q

PullingtheRUNpinhighenablestheregulatorwhichallows

an internal soft-start to slowly ramp the VTTR pin voltage

at a rate of approximately 850mV/ms. During this start-

up time, the regulator will operate in discontinuous mode

until the VTTR pin voltage exceeds approximately ꢀ.45V.

Internal Co0pensation

The LTC3617 provides the option to use a fixed internal

loopcompensationnetworktoreducetherequiredexternal

component count and design time. The internal loop com-

pensation network can be selected by connecting the ITH

When RUN is pulled low, the regulator will force the peak

inductorcurrenttodischargetoaroundꢀAbeforeshutting

off both power MOSFETs.

Output Power Good

V

OUT

The PGOOD output of the LTC3617 is driven by a 17Ω

(typical) open-drain pull-down MOSFET. This MOSFET

turns off approximately 3ms to 4ms after the beginning

of start-up and once the output voltage is within 5% (typi-

cal) of 0.5 • VDDQIN, allowing the voltage at PGOOD to

rise via an external pull-up resistor (1ꢀꢀk typical). If the

output voltage exits an 8% (typical) regulation window

of 0.5 • VDDQIN or the VTTR pin is lower than 0.45V, the

open-drain output will pull low, thus dropping the PGOOD

pin voltage. To prevent unwanted PGOOD glitches during

50mV/DIV

I

L

2A/DIV

3617 F04

V

LOAD

= 3.3V

40µs/DIV

IN

= 1.25V

OUT

I

= 100mA TO 3A

COMPENSATION FIGURE 1

Figure 4. Load Step Transient with

External Co0pensation

transientsordynamicV

changes,theLTC3617PGOOD

OUT

falling edge includes a filter time of approximately 105μs.

V

OUT

50mV/DIV

Efficiency Considerations

I

Theefficiencyofaswitchingregulatorisequaltotheoutput

power divided by the input power times 100%. It is often

useful to analyze individual losses to determine what is

limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as:

L

2A/DIV

3617 F05

V

LOAD

= 3.3V

40µs/DIV

IN

= 1.25V

OUT

I

= 100mA TO 3A

= 3.3V

V

ITH

OUTPUT CAPACITOR VALUE FIGURE 1

Efficiency = 1ꢀꢀ% – (L1 + L2 + L3 + ...)

Figure 5. Load Step Transient with

Internal Co0pensation

where L1, L2, etc. are the individual losses as a percent-

age of input power.

3617fa

14

LTC3617

applications inForMation

Although all dissipative elements in the circuit produce

However, in high current applications where the LTC3617

is running at high ambient temperature with low supply

voltage and high duty cycles, such as in dropout, the heat

generatedmayexceedthemaximumjunctiontemperature

of the part. If the junction temperature reaches approxi-

mately 160°C, both power switches will be turned off and

the SW node will become high impedance.

losses, two main sources usually account for most of

2

the losses: V quiescent current and I R losses. The V

IN

quiescent current loss dominates the efficiency loss at

2

very low load currents whereas the I R loss dominates

the efficiency loss at medium to high load currents. In a

typical efficiency plot, the efficiency curve at very low load

currents can be misleading since the actual power lost is

usually of no consequence.

To prevent the LTC3617 from exceeding the maximum

junction temperature, some thermal analysis is required.

The temperature rise is given by:

1. TheV quiescentcurrentisduetotwocomponents:the

IN

DCbiascurrentasgivenintheElectricalCharacteristics

and the internal main switch and synchronous switch

gate charge currents. The gate charge current results

fromswitchingthegatecapacitanceoftheinternalpower

MOSFET switches. Each time the gate is switched from

low to high to low again, a packet of charge dQ moves

T

= (P ) • (θ )

D JA

RISE

where P is the power dissipated by the regulator and θ

D

JA

is the thermal resistance from the junction of the die to

the ambient temperature. The junction temperature, T ,

J

is given by:

from V to ground. The resulting dQ/dt is the current

IN

T = T + T

RISE

J

A

intoV dueto gate charge, and itistypically largerthan

IN

where T is the ambient temperature.

A

the DC bias current. Both the DC bias and gate charge

losses are proportional to V ; thus, their effects will

As an example, consider the case when the LTC3617 is

used in a DDR application where V = 3.3V, I

IN

be more pronounced at higher supply voltages.

= 6A,

IN

OUT

2

f = 1MHz, V

= 1.25V. The equivalent power MOSFET

OUT

2. I R losses are calculated from the resistances of the

resistance R is:

SW

internal switches, R , and external inductor, R . In

SW

L

continuous mode the average output current flowing

through inductor L is “chopped” between the main

switch and the synchronous switch. Thus, the series

resistance looking into the SW pin is a function of both





V_OUT

R_SW=R_DS(ON)TOP •

+R_DS(ON)BOT • 1–







V



IN

1.25

= 35mΩ•

3.3

1.25

3.3







+25mΩ• 1–

= 28.79mΩ

top and bottom MOSFET R

(DC) as follows:

and the duty cycle

DS(ON)







The V current during 1MHz with no load is about 22mA,

R

SW

= (R )(DC) + (R )(1 – DC)

DS(ON)TOP DS(ON)BOT

IN

which includes switching and internal biasing current

loss, transition loss, inductor core loss and other losses

in the application. Therefore, the total power dissipated

by the part is:

The R

for both the top and bottom MOSFETs can

DS(ON)

be obtained from the Typical Performance Character-

2

istics curves. To obtain I R losses, simply add R to

SW

R and multiply the result by the square of the average

L

2

P = I

D

• R + V • I (No Load)

SW IN VIN

output current.

OUT

2

= 36A • 28.79mΩ + 3.3V • 22mA = 1.11W

Other losses including C and C

ESR dissipative

OUT

IN

losses and inductor core losses generally account for

TheQFN3mm× 5mmpackagejunction-to-ambientthermal

less than 2% of the total loss.

resistance, θ , is around 43°C/W. Therefore, the junction

JA

temperature of the regulator operating in a 25°C ambient

Ther0al Considerations

temperature is approximately:

Inmostapplications,theLTC3617doesnotgeneratemuch

heat due to its high efficiency.

T = 1.11W • 43°C/W + 25°C = 73°C

J

3617fa

15

LTC3617

applications inForMation

Remembering that the above junction temperature is

C should be selected for a maximum current rating of:

IN

obtained from the R

at 25°C, we might recalculate

DS(ON)

1.25V

2.5V

1.25V







the junction temperature based on a higher R

since

DS(ON)

I_RMS= 6A •

•

–1 = 3A

RMS







it increases with temperature. Redoing the calculation

assuming that R increased 15% at 73°C yields a new

SW

Decoupling PV with four 10µF to 22µF capacitors is

IN

junctiontemperatureof79°C. Therefore, wecansafelyas-

sume that the actual junction temperature will not exceed

the absolute maximum junction temperature of 125°C.

adequate for most applications. Connecting the V pin

FB

directlytoV

willsettheoutputvoltageequaltoone-half

of the voltage on the VDDQIN pin. The complete circuit of

OUT

Note that for very low input voltage, the junction tempera-

ture will be higher due to increased switch resistance,

this design example is illustrated in Figure 1.

PC Board Layout Checklist

R

. It is not recommended to use full load current

DS(ON)

with high ambient temperature and low input voltage.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3617:

To maximize the thermal performance of the LTC3617 the

exposed pad must be soldered to a ground plane. See the

PCB Layout Board Checklist.

1. Agroundplaneisrecommended.Ifagroundplanelayer

is not used, the signal and power grounds should be

segregated with all small-signal components returning

to the SGND pin at one point which is then connected

to the PGND pin close to the LTC3617.

Design Exa0ple

As a design example, consider the LTC3617 in an applica-

tion with the following specifications:

2. Connect the (+) terminal of the input capacitor(s), C ,

V

= 2.5V, V

= 1.25V, I

= 6A, I

=

OUT(MIN)

IN

OUT

OUT(MAX)

ascloseaspossibletothePV pin, andthe(–)terminal

2ꢀꢀmA, f = 2.6MHz.

IN

as close as possible to the exposed pad, PGND. This

capacitorprovidestheACcurrentintotheinternalpower

MOSFETs.

First, calculate the timing resistor:

3.82¹¹Hz

2.6MHz

R_T=

–16k =130kΩ

3. Keep the switching node, SW, away from all sensitive

small-signal nodes.

Next, calculate the inductor value for about 33% ripple

current at maximum V :

4. Flood all unused areas on all layers with copper. Flood-

ing with copper will reduce the temperature rise of

powercomponents. ConnectthecopperareastoPGND

(exposed pad) for best performance.

IN

1.25V

2.6MHz •2A

1.25V

2.5V



 



L =

• 1–

= 0.12µH





 

 





5. Connect the V pin directly to V

.

FB

OUT

Using a standard value of 0.1µH inductor results in a

maximum ripple current of:



1.25V

2.6MHz•0.1µH



1.25V

2.5V







∆I_L=

• 1–

= 2.4A















C

will be selected based on the ESR that is required

OUT

to satisfy the output voltage ripple requirement and the

bulk capacitance needed for loop stability. For this design,

a 100µF ceramic capacitor is used with a X5R or X7R

dielectric.

3617fa

16

LTC3617

typical applications

±.25V, ±6A DDR Me0ory Ter0ination Supply, 2.25MHz

V

IN

2.5V TO 5.5V

C

IN

R

F

22µF

24Ω

×4

C

1µF

F

SV

RUN

VDDQIN

RT

PV

IN

VTTR

IN

V

REF

1.25V

10ꢀA

VDDQ

2.5V

C

O1

0.1µF

L1

0.15µH

R1

LTC3617

VTT

100k

1.25V

6A

SW

SGND

PGND

R

C

O2

PGOOD

ITH

20k

100µF

C

C1

V

FB

SYNC

470pF

10pF

3617 TA02a

L1: VISHAY IHLP-2525CZ-01 150nH

Efficiency vs Load Current

Load Step Response

100

90

80

70

60

50

40

30

20

10

0

V

TT

50mV/DIV

I

L

4A/DIV

3617 TA02c

V

= 3.3V

40µs/DIV

V

= 2.5V

= 3.3V

= 5V

IN

VTT = 1.25V

= 100mA TO 6A

I

LOAD

0.1

1

10

LOAD CURRENT (A)

3617 TA02b

3617fa

17

LTC3617

typical applications

1.75V, ±6A DDR Ter0ination Using a ±MHz External Clock

V

IN

2.5V TO 5.5V

C

IN

R

F

22µF

24Ω

×4

C

1µF

F

SV

RUN

VDDQIN

RT

PV

IN

VTTR

V

REF

0.75V

10ꢀA

VDDQ

1.5V

C

O1

0.1µF

L1

0.33µH

R1

365k

R2

100k

VTT

0.75V

6A

LTC3617

SW

C

O2

100µF

R

C

PGOOD

ITH

SGND

PGND

6k

C

C1

V

FB

SYNC

1.5nF

10pF

1MHz CLOCK

3617 TA03a

L1: VISHAY IHLP-2525CZ-01 330nH

External Start-Up

Output Tracking Up/Down

VDDQ

500mV/DIV

V

/VTT

REF

V

/VTT

REF

3617 TA03b

3617 TA03c

2ms/DIV

4ms/DIV

package Description

UDD Package

24-Lead Plastic QFN (300 × 500)

(Reference LTC DWG # 05-08-1833 Rev Ø)

PIN ꢀ NOTCH

R = 0.20 OR 0.25

× 45° CHAMFER

0.75 0.05

ꢀ.50 REF

R = 0.05 TYP

3.00 0.ꢀ0

23

24

0.70 0.05

0.40 0.ꢀ0

3.50 0.05

PIN ꢀ

TOP MARK

(NOTE 6)

ꢀ

2

2.ꢀ0 0.05

3.65 0.05

ꢀ.65 0.05

ꢀ.50 REF

3.65 0.ꢀ0

ꢀ.65 0.ꢀ0

5.00 0.ꢀ0

PACKAGE OUTLINE

3.50 REF

0.25 0.05

0.50 BSC

3.50 REF

4.ꢀ0 0.05

5.50 0.05

(UDD24) QFN 0808 REV

Ø

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.200 REF

0.00 – 0.05

0.25 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

R = 0.ꢀꢀ5

TYP

NOTE:

ꢀ. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3617fa

18

LTC3617

revision history

REV

DATE

DESCRIPTION

PAGE NUMBER

A

7/11

Updated Main Control section

Updated Output Power Good section

Updated Typical Application and scale on graphs

9

14

18, 20

3617fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LTC3617

typical application

DDR2 Ter0ination, ±MHz

External Start-Up

V

IN

2.25V TO 5.5V

22µF

×4

SV

RUN

VDDQIN

RT

PV

IN

VTTR

VDDQ

IN

V

REF

0.9V

10ꢀA

VDDQ

1.8V

0.1µF

L1

0.33µH

500mV/DIV

R1

365k

R2

100k

VTT

0.9V

6A

V

/VTT

REF

LTC3617

SW

R

C

100µF

47µF

PGOOD

ITH

SYNC

SGND

PGND

6k

C

C1

10pF

C

V

FB

2.2nF

3617 TA04b

400µs/DIV

3617 TA04a

L1: COILCRAFT D03316T

relateD parts

PART NUMBER DESCRIPTION

COMMENTS

95% Efficiency, V

LTC3616

LTC3612

LTC3418

LTC3415

LTC3416

LTC3413

LTC3412A

5.5V, 6A (I ) 4MHz Synchronous Step-Down DC/DC

= 2.25V, V

= 5.5V, V

OUT(MIN)

= ꢀ.6V,

OUT

IN(MIN)

IN(MAX)

Converter

I = 70µA, I < 1µA, 3mm × 5mm QFN24 Package

Q SD

5.5V, 3A (I ), 4MHz, Synchronous Step-Down DC/DC

95% Efficiency, V

I = 70µA, I <1µA, 3mm × 4mm QFN-20 TSSOP20E Package

Q SD

= 2.25V, V

= 5.5V, V

IN(MAX) OUT(MIN)

OUT

IN(MIN)

Converter

5.5V, 8A (I ), 4MHz, Synchronous Step-Down DC/DC

95% Efficiency, V

I = 380µA, I <1µA, 5mm × 7mm QFN-38 Package

Q SD

= 2.25V, V

= 5.5V, V = 0.8V,

OUT(MIN)

OUT

IN(MIN)

IN(MAX)

Converter

5.5V, 7A (I ), 1.5MHz, Synchronous Step-Down DC/DC

95% Efficiency, V

I = 450µA, I <1µA, 5mm × 7mm QFN-38 Package

Q SD

= 2.5V, V

= 5.5V, V = ꢀ.6V,

OUT(MIN)

OUT

IN(MIN)

IN(MAX)

Converter

5.5V, 4A (I ), 4MHz, Synchronous Step-Down DC/DC

95% Efficiency, V

I = 64µA, I <1µA, TSSOP20E Package

Q SD

= 2.25V, V

= 5.5V, V

= 0.8V,

OUT

IN(MIN)

IN(MAX)

OUT(MIN)

Converter

5.5V, 3A (I

Sink/Source), 2MHz, Monolithic Synchronous

90% Efficiency, V

I = 280µA, I <1µA, TSSOP16E Package

Q SD

= 2.25V, V

= 5.5V, V

= V /2,

REF

OUT

IN(MIN)

IN(MAX)

Regulator for DDR/QDR Memory Termination

5.5V, 2.5A (I ), 4MHz, Synchronous Step-Down DC/DC

95% Efficiency, V

I = 60µA, I <1µA, 4mm × 4mm QFN-16 TSSOP16E Package

Q SD

= 2.5V, V

= 5.5V, V

= 0.8V,

OUT(MIN)

OUT

IN(MIN)

IN(MAX)

Converter

3617fa

LT 0711 REV A • PRINTED IN USA

20 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

 LINEAR TECHNOLOGY CORPORATION 2011

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3617_15
厂家：	Linear
描述：	6A Monolithic Synchronous Step-Down Regulator for DDR Termination 双倍数据速率
文件：	总20页 (文件大小：481K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3617_15 [Linear]

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