LTC3618EUF#PBF [Linear]
LTC3618 - Dual 4MHz, ±3A Synchronous Buck Converter for DDR Termination; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC3618EUF#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3618 - Dual 4MHz, ±3A Synchronous Buck Converter for DDR Termination; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C 双倍数据速率 开关 |
| 文件： | 总24页 (文件大小：614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3618
Dual 4MHz, ±±3
Synchronous Buck Converter
for DDR Termination
FeaTures
DescripTion
DDR Power Supply, Termination and Reference
The LTC®3618 is a dual synchronous step-down regulator
using a current mode, constant-frequency architecture. It
provides a complete DDR solution with an input voltage
range from 2.25V to 5.5V.
n
n
High Efficiency: Up to 94%
n
Dual Outputs with ±±3 Output Current Capaꢀility
n
2.25V to 5.5V Input Voltage Range
±ꢁ% Output Voltage 3ccuracy
n
The output of the first step-down regulator offers a high
n
V
Output Voltage Down to 0.5V
TT
accuracy V
supply. A buffered reference generates
DDQ
n
n
n
n
n
n
Shutdown Current ≤1µA
VTTR at 50% of VDDQIN and drives loads up to 10mA.
The second regulator generates the DDR termination volt-
VTTR = VDDQIN/2, V = VTTR
FB2
Adjustable Switching Frequency Up to 4MHz
Internal or External Compensation
age (V ) equal to VTTR. Both regulators are capable of
TT
delivering 3Aofloadcurrentat1MHzswitchingfrequency.
Selectable 0°/90°/180° Phase Shift Between Channels
The operating frequency is externally programmable up to
4MHz, allowing the use of small surface mount inductors.
0°, 90°, or 180° of phase shift between the two channels
can be selected to minimize input current ripple. For
switching noise-sensitive applications, the LTC3618 can
be synchronized to an external clock up to 4MHz.
Internal or External Soft-Start for V , Internal
DDQ
Soft-Start for V
TT
n
n
Power Good Status Outputs
Low Profile 4mm × 4mm QFN-24 and TSSOP-24
Packages
applicaTions
The LTC3618 is offered in leadless 24-pin 4mm × 4mm
QFN and thermally enhanced 24-pin TSSOP packages.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6498466, 6580258, 6611131.
n
DDR Memory
Supports DDR, DDR2, and DDR3 Standards
n
n
Tracking Supplies
Typical applicaTion
V
IN
Efficiency and Power Loss vs Load Current
3.3V
100µF
100
90
80
70
60
50
40
30
20
10
0
10
SV
PV
PV
IN2
IN
IN1
VDDQIN
V
= 1.8V
RUN1
DDQ
1µH
1µH
V
DDQ
1.8V/3A
47µF
TRACK/SS1
PGOOD1
ITH1
SW1
1
422k
210k
LTC3618
V
TT
= 0.9V
FB1
RT
MODE/SYNC
PHASE
392k
V
TT
0.1
SW2
FB2
0.9V/ 3A
47µF
RUN2
PGOOD2
ITH2
0.01
10
0.01
0.1
1
V
DDQ
V
=
LOAD CURRENT (A)
VTTR
REF
3618 TA01b
2
SGND
PGND
3618 TA01a
0.01µF
3618fc
1
For more information www.linear.com/LTC3618
LTC3618
absoluTe MaxiMuM raTings
(Notes ꢁ, ꢁ0)
PV , PV Voltages .................................. –0.3V to 6V
Operating Junction Temperature
IN1
IN2
SV Voltage ................................................ –0.3V to 6V
Range (Note 2)....................................... –40°C to 125°C
Storage Temperature.............................. –65°C to 150°C
Lead Soldering Temperature (TSSOP) ..................300°C
Reflow Peak Body Temperature (QFN)..................260°C
IN
SW1 Voltage .............................–0.3V to (PV + 0.3V)
IN1
SW2 Voltage ..............................–0.3V to (PV + 0.3V)
IN2
RUN1 Voltage.............................. –0.3V to (SV + 0.6V)
IN
All Other Pins............................................... –0.3V to 6V
pin conFiguraTion
TOP VIEW
TOP VIEW
1
2
MODE/SYNC
ITH1
24
23
22
21
20
19
18
17
16
15
14
13
PHASE
FB2
24 23 22 21 20 19
3
FB1
ITH2
FB1
ITH1
1
2
3
4
5
6
18 PGOOD1
4
TRACK/SS1
VDDQIN
SGND
VTTR
17
16
5
SV
IN
25
PGND
MODE/SYNC
PHASE
FB2
PGOOD2
25
PGND
6
PV
IN1
PV
IN2
15 RT
7
PV
IN1
PV
IN2
14
RUN1
8
SW1
SW2
SW2
RUN2
RUN1
RT
ITH2
13 RUN2
9
SW1
7
8
9 10 11 12
10
11
12
PGOOD1
VTTR
PGOOD2
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
FE PACKAGE
24-LEAD PLASTIC TSSOP
T
= 125°C, θ = 33°C/W
JA
T
= 125°C, θ = 46.9°C/W
JA
JMAX
JMAX
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LE3D FREE FINISH
LTC3618EFE#PBF
LTC3618IFE#PBF
LTC3618EUF#PBF
LTC3618IUF#PBF
T3PE 3ND REEL
P3RT M3RKING*
LTC3618FE
LTC3618FE
3618
P3CK3GE DESCRIPTION
TEMPER3TURE R3NGE
LTC3618EFE#TRPBF
LTC3618IFE#TRPBF
LTC3618EUF#TRPBF
LTC3618IUF#TRPBF
24-Lead Plastic TSSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
24-Lead Plastic TSSOP
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
3618
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3618fc
2
For more information www.linear.com/LTC3618
LTC3618
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at T3 = 25°C (Note 2), SVIN = PVINx = ±.±V, RT = ꢁ78k, unless otherwise
specified.
SYMBOL
P3R3METER
CONDITIONS
MIN
2.25
1.8
TYP
M3X
UNITS
l
V
Operating Voltage Range
Undervoltage Lockout Threshold
5.5
V
V
V
IN
V
UVLO
SV Ramping Down
IN
SV Ramping Up
IN
2.2
OVLO
Overvoltage Lockout Threshold
SV Ramping Down
6.2
300
V
mV
IN
Hysteresis
V
V
Feedback Voltage Internal
(Note 3) V
= SV
FB1
DDQ
TRACK/SS1 IN
Reference with Line and Load
Regulation
0°C < T < 85°C
0.592
0.590
0.6
0.608
0.610
V
V
J
l
–40°C < T < 125°C
J
Feedback Voltage External Reference (Note 3) V
= 0.3V
= 0.5V
0.289
0.489
0.3
0.5
0.311
0.511
V
V
TRACK/SS1
TRACK/SS1
(Note 6)
(Note 3) V
l
l
l
V
V
Feedback Reference Voltage with VDDQIN = 1.5V
VTTR – 6
VTTR
VTTR + 6
mV
FB2
TT
Line and Load Regulation
VTTR
VTTR Output Voltage with Line and
Load Regulation
VDDQIN = 1.5V, I
= 10mA,
0.49 • V
0.5 • V
0.51 • V
DDQ
V
LOAD
DDQ
DDQ
C
LOAD
= < 0.1µF
I
I
Feedback Input Current
V
= 0.6V
0
30
10
nA
mA
mA
FB
S
FBx
VTTR Maximum Output Current
Input Supply Current, Active Mode
V
V
= 0.5V, V
RUN2
= SV , V
= SV ,
2.4
2.8
FB1
MODE
IN RUN1
IN
= 0V, (Note 5)
V
= 0.5V, V
= SV , V
= SV ,
mA
FBx
MODE
IN RUNx
IN
(Note 5)
Input Supply Current, Shutdown
Top Switch On-Resistance
SV = PV = 5.5V, V = 0V
RUNx
0.1
75
55
1
µA
mΩ
mΩ
IN
IN
R
PV = 3.3V (Note 9)
INx
DS(ON)
Bottom Switch On-Resistance
PV = 3.3V (Note 9)
INx
I
Peak Current Limit
Positive Limit
LIMX
Sourcing (Note 7), V = 0.5V
4.2
–2.5
5.5
–3.5
8.0
–5.5
A
A
FBX
Negative Limit
Sinking (Note 7), V = 0.7V
FBX
I
Switch Leakage Current
SV = PV = 5.5V, V = 0V
RUNx
0.01
240
30
1
µA
µmho
µA
SW(LKG)
IN
IN
g
Error Amplifier Transconductance
Error Amplifier Output Current
–5µA < I < 5µA
m(EA)
TH
I
t
(Note 4)
EAO
V
Internal Soft-Start Time
V from 0.06V to 0.54V,
FB1
0.5
1.1
2
ms
SOFT-START1
DDQ
TRACK/SS1 = SV
IN
t
V
Internal Soft-Start Time
V
from 0V to 0.75V
0.25
0.6
1
ms
Ω
SOFT-START2
TT
FB2
R
TRACK/SS1 Pull-Down Resistance
at Start-Up
200
ON(TRACK/SS1_DIS)
t
f
Soft-Start Discharge Time at Start-Up
Oscillator Frequency
65
1.85
1.8
µs
MHz
MHz
MHz
V
TRACK/SS1_DIS
OSC
l
l
R
= 178k
2.25
2.25
2.65
2.7
4
RT
Internal Default Oscillator Frequency
Synchronization Frequency
SYNC Level High Voltage
V
= SV
IN
RT
f
t
, t > 30ns
LOW HIGH
0.4
SYNC
V
1.2
MODE/SYNC
SYNC Level Low Voltage
0.3
V
j
Output Phase Shift Between SW1
and SW2
V
< 0.15 • SV
0
Deg
Deg
Deg
3618fc
SW1–SW2
PHASE
IN
0.35 • SV < V
< 0.65 • SV
IN
90
IN
PHASE
V
> 0.85 • SV
180
PHASE
IN
3
For more information www.linear.com/LTC3618
LTC3618
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at T3 = 25°C (Note 2), SVIN = PVINx = ±.±V, RT = ꢁ78k, unless otherwise
specified.
SYMBOL
P3R3METER
CONDITIONS
MIN
TYP
M3X
UNITS
V
V
V
High Voltage
Low Voltage
Pulse-Skipping Mode
Forced Continuous Mode
1.0
V
V
MODE
MODE
MODE
(Note 8)
0.4
–2
PGOOD1
Power Good Voltage Window of
V
TRACK/SS1 = SV , Entering Window
IN
V
FB1
V
FB1
Ramping Up
–5
5
%
%
DDQ
Ramping Down
2
TRACK/SS1 = SV , Leaving Window
IN
V
V
Ramping Up
8
10.5
–2.5
10.5
%
%
FB1
FB1
Ramping Down
–10.5
2.5
–8
PGOOD2
Power Good Voltage Window of V
Entering Window
TT
V
TT
V
TT
Ramping Up
Ramping Down
–5
5
%
%
Leaving Window
V
FB2
V
FB2
Ramping Up
Ramping Down
8
–8
%
%
–10.5
t
Power Good Blanking Time
Entering/Leaving Window
65
8
105
12
140
30
µs
Ω
PGOOD
R
Power Good Pull-Down On-Resistance I = 10mA
PGOOD
l
l
V
V
Voltage
Input High
Input Low
1
V
V
RUN
RUN
0.4
Pull-Down Resistance
4
MΩ
Note ꢁ: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: External compensation on ITH pin.
Note 5: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 6: See description of the TRACK/SS pin in the Pin Functions section.
Note 7: When sourcing current, the average output current is defined
as flowing out of the SW pin. When sinking current, the average output
current is defined as flowing into the SW pin. Sinking mode requires the
use of forced continuous mode.
Note 8: See description of the MODE pin in the Pin Functions section.
Note 9: Guaranteed by design and correlation to wafer level measurements
Note 2: The LTC3618 is tested under pulsed load conditions such that
T
J
≈ T . The LTC3618E is guaranteed to meet performance specifications
A
over the 0°C to 85°C operating junction temperature range. Specifications
over the –40°C to 125°C operating junction temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTC3618I is guaranteed to meet specifications over the
full –40°C to 125°C operating junction temperature range. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
for QFN packages.
Note ꢁ0: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability or permanently damage the
device.
factors. The junction temperature (T , in °C) is calculated from the ambient
J
temperature (T , in °C) and power dissipation (P , in watts) according to
A
D
the formula:
T = T + (P • θ )
JA
J
A
D
where θ (in °C/W) is the package thermal impedance.
JA
Note ±: This parameter is tested in a feedback loop which servos V to
FB1
the midpoint for the error amplifier (V
= 0.75V).
ITH1
3618fc
4
For more information www.linear.com/LTC3618
LTC3618
Typical perForMance characTerisTics T3 = 25°C, VIN = ±.±V, f = ꢁMHz, Figure ± Circuit,
unless otherwise noted.
Efficiency vs Input Voltage
VDDQ = ꢁ.8V
Efficiency vs Load Current
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= SV
V
= SV
MODE/SYNC
IN
MODE/SYNC IN
V
= SV
IN
MODE/SYNC
I
I
I
I
I
= 200mA
= 300mA
= 1A
= 2A
= 3A
LOAD
LOAD
LOAD
LOAD
LOAD
V
V
V
= 2.5V
= 1.8V
= 1.5V
V
TT
V
TT
V
TT
= 0.75V
= 0.9V
OUT
OUT
OUT
= 1.25V
5.25
2.25 2.75 3.25 3.75 4.25 4.75
INPUT VOLTAGE (V)
10
0.01
0.1
1
10
0.01
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
3618 G01
3618 G02
3618 G03
Efficiency vs Input Voltage
TT = 0.9V
V
VOUT Load Regulation
Input Voltage Line Regulation
100
90
80
70
60
50
40
30
20
10
0
1.0
0.8
0.6
0.4
0.2
0.5
0.4
0.3
0.2
0.1
0
V
= 0.9V
TT
V
= 0.9V
TT
V
= 1.8V
DDQ
V
= 1.8V
DDQ
0
–0.2
–0.4
–0.6
–0.1
–0.2
I
I
I
I
I
= 200mA
= 300mA
= 1A
LOAD
LOAD
LOAD
LOAD
LOAD
–0.3
–0.4
–0.5
= 2A
–0.8
–1.0
= 3A
5.25
2.25 2.75 3.25 3.75 4.25 4.75
INPUT VOLTAGE (V)
–3
–2
–1
0
1
2
3
2.25 2.75 3.25 3.75 4.25 4.75 5.25
LOAD CURRENT (A)
INPUT VOLTAGE (V)
3618 G04
3618 G05
3618 G06
Load Step Transient with
FCM Internal Compensation
Forced Continuous Mode
Operation (FCM)
Pulse-Skipping Mode
V
DDQ
200mV/DIV
SW1
SW1
I
L
L1
1A/DIV
L1
1A/DIV
2A/DIV
SW2
SW2
I
LOAD
L2
1A/DIV
2A/DIV
L2
1A/DIV
3618 G08
3618 G09
3618 G07
V
V
= 1.8V
400ns/DIV
V
V
I
= 5V
10µs/DIV
V
V
= 1.8V
400ns/DIV
DDQ
TT
IN
DDQ
DDQ
TT
= 0.9V
= 1.8V
= 0.9V
NO LOAD
IS ALWAYS IN FORCED CONTINUOUS MODE
= 0A TO 3A
NO LOAD
LOAD
V
TT
3618fc
5
For more information www.linear.com/LTC3618
LTC3618
Typical perForMance characTerisTics T3 = 25°C, VIN = ±.±V, f = ꢁMHz, Figure ± Circuit,
unless otherwise noted.
Load Step Transient in Forced
Continuous Mode, Internal
Compensation
Load Step Transient in
Forced Continuous Mode,
Internal Compensation
Load Step Transient in Forced
Continuous Mode, Internal
Compensation
V
V
V
TT
100mV/DIV
TT
DDQ
100mV/DIV
500mV/DIV
I
I
L
L
I
L
1A/DIV
1A/DIV
2A/DIV
3618 G12
3618 G10
3618 G11
V
V
I
= 5V
20µs/DIV
V
V
I
= 5V
10µs/DIV
V
V
I
= 5V
20µs/DIV
IN
TT
IN
DDQ
IN
TT
= 0.9V
= 1.8V
= 0.9V
= –1A TO 1A
= –3A TO 3A
= 0A TO 2A
LOAD
LOAD
LOAD
Reference Voltage
vs Temperature
Switch On-Resistance
vs Input Voltage
Switch On-Resistance
vs Temperature
100
90
80
70
60
50
40
30
20
10
0
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.606
0.604
MAIN SWITCH
MAIN SWITCH
0.602
0.600
0.598
SYNCHRONOUS SWITCH
SYNCHRONOUS SWITCH
0.596
0.594
–40
–10
5
20 35 50 65 80 95 110 125
–25
2.25
3.25
4.25
5.25
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3618 G15
3618 G14
3618 G13
Switching Frequency vs Input
Voltage
Frequency vs RT
Frequency vs Temperature
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.8
0.6
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
R
T
= SV
IN
R
T
= SV
IN
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
R
T
= 402kΩ
0
0
200 400 600
RESISTOR ON RT/SYNC PIN (kΩ)
1400
–50 –30 –10 10 30 50 70 90 100 130
800 1000 1200
2.25 2.75 3.25 3.75 4.25 4.75 5.25
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3618 G16
3618 G17
3618 G18
3618fc
6
For more information www.linear.com/LTC3618
LTC3618
Typical perForMance characTerisTics T3 = 25°C, VIN = ±.±V, f = ꢁMHz, Figure ± Circuit,
unless otherwise noted.
Switch Leakage Current
vs Temperature
No Load Supply Current
vs Input Voltage
No Load Supply Current
vs Temperature
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
5.0
4.5
V
= 5.5V
IN
4.0
3.5
3.0
2.5
2.0
1.5
1.0
MAIN SWITCH
SYNCHRONOUS SWITCH
–40
–10
5
20 35 50 65 80 95 110 125
–45
5
30
55
80 105
–25
–20
2.25 2.75 3.25 3.75 4.25 4.75 5.25
TEMPERATURE (°C)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3618 G19
3618 G21
3618 G20
Sinking Current
Tracking Up/Down
TRACK/SS
500mV/DIV
SW1
SW2
V
DDQ
500mV
I
L2
PGOOD
5V/DIV
1A/DIV
I
L1
1A/DIV
3618 G22
3618 G23
V
V
= 1.8V
400ns/DIV
= –3A
2ms/DIV
FORCED CONTINUOUS MODE
DDQ
TT
= 0.9V
I
, I
LOAD1 LOAD2
V
= 0V to 0.6V
= 1A
DDQ
LOAD
I
Internal Start-Up VDDQ
Internal Start-Up VTT
RUN
5V/DIV
RUN
5V/DIV
PGOOD
2V/DIV
PGOOD
2V/DIV
V
V
TT
DDQ
500mV/DIV
1V/DIV
I
I
L
L
1A/DIV
1A/DIV
3618 G25
3618 G24
V
= 0.9V
400µs/DIV
V
= 1.8V
1ms/DIV
TT
DDQ
NO LOAD
NO LOAD
3618fc
7
For more information www.linear.com/LTC3618
LTC3618
pin FuncTions (FE/UF)
PH3SE (Pin ꢁ/Pin 4): Phase Shift Selection. If pin is tied
PGOODꢁ (Pin ꢁ5/Pin ꢁ8): Power Good Output Pin for
V .Theopen-drainoutputwillbepulleddowntoground
DDQ
to SGND, the phase between SW1 and SW2 will be 0°.
Tying PHASE to SV will select 180° phase shift. With
if the FB1 voltage of the channel is not within the power
good voltage window. The PGOOD1 will also be pulled
down if the channel is not enabled with the RUN1 pin or an
IN
the PHASE pin tied to half of the SV voltage, 90° phase
IN
shift will be selected.
undervoltage at SV is detected. The power good window
IN
V
(Pin 2/Pin 5): Voltage Feedback Input Pin for V .
TT
FB1
FB2
See V
moves in relation to the actual TRACK/SS1 pin voltage.
.
SWꢁ (Pins ꢁ7, ꢁ6/Pins ꢁ9, 20): V
Switch Node.
DDQ
ITH2 (Pin ±/Pin 6): Error Amplifier Compensation of V .
See ITH1.
TT
Connection to the external inductor. This pin connects
to the drains of the internal synchronous power MOSFET
switches.
VDDQIN (Pin 4 /Pin 7): External Reference Input. An
internal resistor divider to the error amplifier sets the
PV
(Pins ꢁ8, ꢁ9/Pins 2ꢁ, 22): V
Power Supply
DDQ
INꢁ
output voltage of V . V will regulate to VDDQIN • 0.5.
TT FB2
Inputs. These pins connect to the source of the internal
SGND (Pin 5/Pin 8): Signal Ground. All small-signal and
compensationcomponentsshouldconnecttothisground
pin which, in turn, should be connected to PGND at one
point.
power P-channel MOSFET of V . P and P are
DDQ VIN1
VIN2
independent of each other. They may connect to equal or
lower supplies than S
.
VIN
SV (Pin 20/Pin 2±) Signal Input Supply. This pin pow-
IN
PV (Pins 6, 7/Pins 9, ꢁ0) V Power Supply Input.
ers the internal control circuitry and is monitored by the
IN2
See PV
TT
.
undervoltage lockout comparator.
IN1
SW2 (Pins 8, 9/Pins ꢁꢁ, ꢁ2): V Switch Node. See SW1.
TR3CK/SSꢁ (Pin 2ꢁ/Pin 24): Internal, External Soft-Start,
TT
ExternalReferenceInputforV . Thetypeofstart-upbe-
DDQ
RUN2 (Pin ꢁ0/Pin ꢁ±): Enable Pin for V . See RUN1.
TT
haviorforV
isprogrammablewiththeTRACK/SS1pin:
DDQ
RUNꢁ(Pin ꢁꢁ/Pin ꢁ4):Enable Pin for V . Forcing RUN1
DDQ
1. Internal soft-start with fixed timing can be programmed
above the input threshold voltage enables the output SW1
by tying TRACK/SS1 to SV .
IN
of V . Forcing both RUNx pins to ground shuts down
DDQ
the LTC3618. In shutdown, all functions are disabled and
the LTC3618 draws <1µA of supply current.
2. External soft-start can be programmed with the timing
set by a capacitor to ground and a resistor to SV .
IN
RT (Pinꢁ2/Pinꢁ5):OscillatorFrequency.Thispinprovides
3. Tracking the start-up behavior of another supply is
programmable (see the Applications Information
section).
two modes of setting the switching frequency.
1. Connecting a resistor from RT to ground will set the
switching frequency based on the resistor value.
4. The pin can be used as external reference input.
2. Tying this pin to SV enables the internal 2.25MHz
ITHꢁ (Pin 2±/Pin 2): Error Amplifier Compensation. Con-
nection for external compensation from ITH to SGND.
The current comparator’s threshold increases with this
IN
oscillator frequency.
PGOOD2 (Pin ꢁ±/Pin ꢁ6): Power Good Output for
V . See PGOOD1.
TT
control voltage. Tying this pin to SV enables internal
IN
compensation.
VTTR (Pin ꢁ4 /Pin ꢁ7): Voltage Buffer Output. This pin is
the output of an internal voltage buffer whose voltage is
equaltoVDDQIN•0.5.Outputcurrentcapabilityis 10mA.
Do not exceed 0.1µF capacitance on this pin. This output
is enabled/disabled by RUN2.
V
DDQ
(Pin 22/Pin ꢁ): Voltage Feedback Input Pin for
FBꢁ
V
. Receives the feedback voltage for V
from the
DDQ
external resistive divider across the output.
3618fc
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LTC3618
pin FuncTions (FE/UF)
MODE/SYNC (Pin 24/Pin ±): Mode Selection.
PGND (Exposed Pad Pin 25/ Exposed Pad Pin 25): Power
Ground. The exposed pad connects to the sources of the
power N-channel MOSFETs. The PGND pin is common
for both channels. The exposed pad must be soldered
to the PCB for electrical connection and rated thermal
performance. Refer to the Operation and Applications
Information sections for more information.
1. Tying the MODE pin to SV or SGND enables pulse-
IN
skipping mode or forced continuous mode respectively
for V
only. The default operation mode for V is
DDQ
TT
forced continuous mode. The input to the MODE/SYNC
pin should be a digital signal.
2. When a clock signal is applied to this pin, the switching
frequency synchronizes to this clock signal and forced
continuous mode is selected for V
.
DDQ
FuncTional block DiagraM
V
DDQ
ITH1
PGOOD1
PGOOD
WINDOW-
COMPARATOR
DELAY
INTERNAL/
EXTERNAL
COMPENSATION
ITH-VOLTAGE
LIMIT
ERROR
AMPLIFIER
FB1
–
+
V
REF
+
IDEAL
DIODE
PMOS
CURRENT SENSE
PMOS
–
SLOPE
COMPENSATION
CURRENT
PV
IN1
+
–
COMPARATOR
MODE/SYNC
TRACK/SS1
CONTROLLER LOGIC
SW1
SOFT-START
OR
GATE DRIVER
RUN1
RUN2
CLK1
PLL
OSCILLATOR
AND PHASE
SELECTOR
+
RT
NMOS
CURRENT SENSE
PHASE
0A
–
SV
IN
CLK2
UNDERVOLTAGE
LOCKOUT
OVERVOLTAGE
LOCKOUT
REVERSE
SGND
VTTR
SHUTDOWN
CURRENT
COMPARATOR
VDDQIN
PGND
–
+
R
R
DUPLICATE FOR V
TT
ERROR
AMPLIFIER
–
+
PV
IN2
PGOOD2
FB2
SW2
ITH2
3618 FD
3618fc
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LTC3618
operaTion
Main Control Loop
a clock signal applied to the MODE/SYNC pin. The switch-
ing frequency can be set from 400kHz to 4MHz (see the
Applications Information section).
The LTC3618 is a dual monolithic step-down DC/DC con-
verterfeaturingcurrent-mode,constant-frequencyopera-
tion.Theregulatedoutputvoltageofthesecondstep-down
converter is equal to VDDQIN • 0.5. An additional internal
amplifier provides a VTTR output equal to VDDQIN • 0.5,
which is capable of driving a 10mA load.
OvervoltageandundervoltagecomparatorspullthePGOOD
output low if the output voltage varies more than 8%
(typical) from the set point.
V Overvoltage Protection
IN
During normal operation, the internal top power switch
(P-channel MOSFET) of each channel is turned on at
the beginning of its clock cycle. Current in the inductor
increases until the current comparator trips and turns
off the top power MOSFET. The peak inductor current at
which the current comparator shuts off is controlled by
the voltage on the ITH pin. The error amplifier adjusts
the voltage on the ITH pin by comparing the feedback
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTC3618 constantly
monitors the V pin for an overvoltage condition. When
IN
V
rises above 6.5V, the regulator suspends operation
IN
by shutting off the MOSFETs. The regulator executes its
soft-start when exiting an overvoltage condition.
signals V (derived from an external resistor divider on
MODE SELECTION
FBX
the V pin) with a reference (0.6V for V , VDDQIN •
FB1
DDQ
The MODE/SYNC pin is used to select one of two different
0.5 for V ). When the load current increases, it causes a
TT
operating modes for V . When the MODE/SYNC pin
DDQ
reduction in the feedback voltage relative to the reference.
The error amplifier raises the ITH voltage until the average
inductor current matches the new load current. Typical
voltage range for the ITH pin is from 0.55V to 1.05V with
0.55V corresponding to zero current.
is tied to SV , pulse-skipping mode is selected, when
IN
it is tied to ground, forced continuous mode is selected
(Figure 1). V is always in forced continuous mode.
TT
VTTR Voltage Buffer Output
When the top power MOSFET shuts off, the synchronous
power switch (N-channel MOSFET) turns on until either
the current limit is reached or the next clock cycle begins.
The bottom current limit is typically set at –4A for forced
continuous mode and 0A for pulse-skipping mode.
An internal high accuracy op amp buffer generates
a VTTR pin voltage that is equal to VDDQIN • 0.5.
VTTR can source and sink up to 10mA and is stable
with a 0.1µF capacitor. Short circuit current limit is
set around 20mA to prevent damage to the op amp.
The operating frequency defaults to 2.25MHz when
The VTTR output is also the reference voltage for V .
TT
RT is connected to SV , or can be set by an external
Therefore, large transients on this pin will impact the
IN
resistor connected between the RT pin and ground, or by
behavior at the V output.
TT
LTC3618
LTC3618
SV
SV
V
V
IN
IN
IN
IN
MODE
MODE
0V
0V
SGND
SGND
3618 F01
1a. Pulse-Skipping Mode
1b. Forced Continuous Mode
Figure ꢁ. VDDQ Modes of Operation
3618fc
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LTC3618
operaTion
Pulse-Skipping Mode Operation
Slope Compensation and Inductor Peak Current
Connecting the MODE/SYNC pin to SV enables pulse-
Slope compensation provides stability in current mode
constant-frequency architectures by preventing subhar-
monic oscillations at duty cycles greater than 50%. The
LTC3618 implements slope compensation by adding a
compensation ramp to the inductor current signal.
IN
skippingmodeforV
only.Astheloadcurrentdecreases,
DDQ
thepeakinductorcurrentwillbedeterminedbythevoltage
ontheITH1pinuntiltheITH1voltagedropsbelow550mV,
corresponding to 0A. At this point switching cycles will be
skipped to keep the output voltage in regulation.
Short-Circuit Protection
Forced Continuous Mode Operation
Thepeakinductorcurrentatwhichthecurrentcomparator
shuts off the top power switch is controlled by the voltage
on the ITH pin.
In forced continuous mode the inductor current is con-
stantly cycled which creates a minimum output voltage
ripple at all output current levels.
If the output current increases, the error amplifier raises
the ITH pin voltage until the average inductor current
matches the new load current. In normal operation, the
LTC3618 clamps the maximum ITH pin voltage at ap-
proximately 1.05V which corresponds to about 5.5A peak
inductor current.
Connecting the MODE/SYNC pin to ground will select the
forced continuous mode operation for V
.
DDQ
The forced continuous mode must be used if the output
is required to sink current.
Dropout Operation
Whentheoutputisshortedtoground,theinductorcurrent
decays very slowly during a single switching cycle. The
LTC3618 uses two techniques to prevent current runaway
from occurring:
Astheinputsupplyvoltageapproachestheoutputvoltage,
the duty cycle increases toward the maximum on-time.
Further reduction of the supply voltage forces the main
switch to remain on for more than one cycle, eventually
reaching 100% duty cycle. The output voltage will then be
determined by the input voltage minus the voltage drop
across the internal P-channel MOSFET and the inductor.
1. If the output voltage drops below 50% of its nominal
value, the clamp voltage at the ITH pin is lowered,
causing the maximum peak inductor current to lower
graduallywiththeoutputvoltage.Whentheoutputvolt-
age reaches 0V, the clamp voltage at the ITH pin drops
to 40% of the clamp voltage during normal operation.
Theshort-circuitpeakinductorcurrentisdeterminedby
theminimumon-timeoftheLTC3618, theinputvoltage
and the inductor value. This foldback behavior helps
in limiting the peak inductor current when the output
is shorted to ground. It is disabled during internal or
externalsoft-startandtrackingup/downoperation(see
the Applications Information section).
Low Supply Operation
The LTC3618 is designed to operate down to an input
supply voltage of 2.25V. An important consideration
at low input supply voltages is that the R
P-channel and N-channel power switches increases by
50% compared to 5V. The user should calculate the
power dissipation when the LTC3618 is used at 100%
duty cycle with low input voltages to ensure that thermal
limits are not exceeded.
of the
DS(ON)
2. If the inductor current of the bottom MOSFET increases
beyond 6A typical, the top power MOSFET will be held
off and switching cycles will be skipped until the induc-
tor current reduces.
3618fc
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LTC3618
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Operating Frequency
Tying the RT pin to SV sets the default internal operating
IN
frequency to 2.25MHz.
Selectionoftheoperatingfrequencyisatrade-offbetween
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
The minimum on-time also limits the sinking current
capability for high switching frequency applications.
Figure2showsthesinkingcurrentvsswitchingfrequency
at different input voltages.
Lowerfrequenciesimprovesefficiencybyreducinginternal
gate charge losses but requires larger inductance values
and/or capacitance to maintain low output ripple voltage.
–5.0
V
TT
= 0.9V
The operating frequency of the LTC3618 is determined
by an external resistor that is connected between the RT
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timingcapacitorwithintheoscillatorandcanbecalculated
by using the following equation:
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
4 •1011ΩHz
5V
3.3V
2.5V
IN
RT =
IN
IN
fOSC
2.5
0
0.5
1
1.5
2
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3618 imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 80ns, therefore, the minimum duty cycle is
FREQUENCY (MHz)
3618 G03
Figure 2. Sinking Current vs Switching Frequency
equal to 80ns • 100% • f (Hz)
OSC
V
IN
3.3V
47µF
47µF
1µF
SV
IN
(2×) PV
(2×) PV
IN1 IN2
RUN1
VDDQIN
R
SS
1µH
MODE/SYNC
V
DDQ
4.7M
(2×) SW1
1.8V/3A
TRACK/SS1
PGOOD1
R1
C
SS
10pF
47µF
845k
10nF
ITH1
FB1
LTC3618
10pF
R
C
R2
422k
15.8k
C
C
R , 392k
T
470pF
RT
1µH
V
TT
(2×) SW2
VTTR
0.9V/ 3A
47µF
0.01µF
PHASE
FB2
RUN2
PGOOD2
ITH2 SGND
PGND
3618 F03
L: VISHAY 1HLP2525BDERIROMO
Figure ±. Soft-Start and Compensation for VDDQ Externally Programmed,
Compensation for VTT Internally Programmed
3618fc
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LTC3618
applicaTions inForMaTion
V
V
V
IN
IN
IN
LTC3618
SV
LTC3618
SV
LTC3618
SV
f
IN
IN
IN
f
SW
P
SW
f
∝1/R
OSC
0.4V
SW
2.25MHz
1/T
RT
RT
MODE/SYNC
SGND
SGND
1.2V
0.3V
R
T
3618 F04
T
P
Figure 4. Setting the Switching Frequency
Frequency Synchronization
Phase Selection
V will operate in-phase, 180° out-of-phase (anti-phase)
The LTC3618’s internal oscillator can be synchronized to
an external frequency by applying a square wave clock
signal to the MODE/SYNC pin. During synchronization,
TT
or shifted by 90° from V
depending on the state of the
DDQ
PHASE pin—low, midrail or high, respectively. Antiphase
generally reduces input voltage and current ripple. Cross-
talk between switch nodes SW1, SW2 and components
or sensitive lines connected to FBx, ITHx, RT can cause
unstable switching waveforms and unexpectedly large
input and output voltage ripple.
the top MOSFET turn-on of V
is locked to the rising
DDQ
edgeoftheexternalfrequencysource.Thesynchronization
frequency range is 400kHz to 4MHz. The internal slope
compensation is automatically adapted to the external
clock frequency.
The situation improves if rising and falling edges of the
switchnodesaretimedcarefullynottocoincide.Depending
on the duty cycle of the two channels, choose the phase
differencebetweenthechannelstokeepedgesasfaraway
from each other as possible.
In the signal path from the MODE/SYNC clock input to the
SW output, the LTC3618 is processing the external clock
frequency through an internal PLL.
After detecting an external clock on the first rising edge of
MODE/SYNC the PLL starts up with the internal default of
2.25MHz. The internal PLL then requires a certain number
of periods to settle until the frequency at SW matches the
frequency and phase of MODE/SYNC.
Foradutycycleoflessthan40%foronechannelandmore
than 60% for the other channel, choose a phase shift of 0
or 180° (PHASE = SGND or SV ). If both channels have
IN
a duty cycle of around 50%, select a phase difference of
When the external clock signal is removed, the LTC3618
needs approximately 5µs to detect the absence of the
external clock. During this time, the PLL will continue to
provide clock cycles before it is switched back to the de-
fault frequency or selected frequency (set via the external
90° (PHASE = one-half SV ).
IN
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the inductor ripple
R resistor).
T
current. The ripple current ∆I increases with higher V
L
IN
In general, any abrupt clock frequency change of the
regulator will have an effect on the SW pin timing and
may cause equally sudden output voltage changes. This
must be taken into account in particular if the external
clock frequency is significantly different from the internal
default of 2.25MHz.
and decreases with higher inductance.
VOUT
fSW •L
VOUT
IL =
• 1–
V
IN(MAX)
Having a lower ripple current reduces the core losses
in the inductor, the ESR losses in the output capacitors
and the output voltage ripple. A reasonable starting point
for selecting the ripple current is ∆I = 0.3(I
).
L
OUT(MAX)
3618fc
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LTC3618
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The largest ripple current occurs at the highest V . To
IN
Taꢀle ꢁ. Representative Surface Mount Inductors
guarantee that the ripple current stays below a specified
maximum, theinductorvalueshouldbechosenaccording
to the following equation:
INDUCT3NCE DCR
M3X
DIMENSIONS
(mm)
HEIGHT
(mm)
(µH) (mΩ) CURRENT (3)
Vishay IHLP-2020BZ-0ꢁ
0.33
0.47
0.68
1
7.6
8.9
25
21
15
16
5.18 × 5.49
5.18 × 5.49
5.18 × 5.49
5.18 × 5.49
2
2
2
2
VOUT
VOUT
L =
• 1–
11.2
18.9
fSW • IL(MAX)
V
IN(MAX)
Toko DE±5ꢁ8C Series
0.22
Sumida CDMC6D28 Series
8
24
4.3 × 4.7
2
Inductor Core Selection
0.3
0.47
0.68
1
3.2
4.2
5.4
8.8
15.4
13.6
11.3
8.8
6.7 × 7.25
6.7 × 7.25
6.7 × 7.25
6.7 × 7.25
3
3
3
3
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for fixed inductor value, but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire, and therefore, copper losses
will increase.
NEC/Tokin MPLC07±0L Series
0.47
0.75
1.0
4.5
7.5
9.0
16.6
12.2
10.6
6.9 × 7.7
6.9 × 7.7
6.9 × 7.7
3.0
3.0
3.0
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates hard, which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow a ferrite core to saturate!
Coilcraft DOꢁ8ꢁ±H Series
0.33
0.56
4
10
8.9 × 6.1
8.9 × 6.1
5
5
10
7.7
Coilcraft SLC75±0 Series
0.27
0.35
0.4
0.1
0.1
0.1
14
11
8
7.5 × 6.7
7.5 × 6.7
7.5 × 6.7
3
3
3
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroidorshieldedpotcoresinferriteorpermalloymaterials
are small and do not radiate much energy, but generally
cost more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. Table 1 shows
some typical surface mount inductors that work well in
LTC3618 applications.
Input Capacitor C Selection
IN
In continuous mode, the source current of the top P-
channel MOSFET is a square wave of duty cycle V /V .
OUT IN
To prevent large voltage transients, a low ESR capacitor
sized for the maximum RMS current must be used for C .
IN
The maximum RMS capacitor current is given by:
VOUT
V
V
OUT
IN
IRMS =IOUT(MAX)
•
•
– 1
V
IN
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This formula has a maximum at V = 2V , where I =
audible piezoelectric effects. In addition, the high-Q of
ceramic capacitors along with trace inductance can lead
to significant ringing.
IN
OUT
RMS
I
/2.Thissimpleworst-caseconditioniscommonlyused
OUT
fordesignbecauseevensignificantdeviationsdonotoffer
muchrelief.Notethatripplecurrentratingsfromcapacitor
manufacturers are often based on only 2000 hours of life
which makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required.Severalcapacitorsmayalsobeparalleledtomeet
size or height requirements in the design.
Ceramic capacitors are tempting for switching regulator
use because of their very low ESR. Great care must be
takenwhenusingonlyceramicinputandoutputcapacitors.
Ceramic caps are prone to temperature effects which re-
quirethedesignertocheckloopstabilityovertheoperating
temperature range. To minimize their large temperature
and voltage coefficients, only X5R or X7R ceramic capaci-
tors should be used.
Output Capacitor C
Selection
OUT
The selection of C
is typically driven by the required
OUT
ESR to minimize voltage ripple and load step transients
(low-ESR ceramic capacitors are discussed in the next
section). Typically, once the ESR requirement is satisfied,
the capacitance is adequate for filtering. The output ripple
When a ceramic capacitor is used at the input, and the
power is being supplied through long wires, such as from
a wall adapter, a load step at the output can induce ringing
at the V pin. At best, this ringing can couple to the output
IN
∆V
is determined by:
OUT
and be mistaken as loop instability. At worst, the ringing
at the input can be large enough to damage the part.
1
ΔVOUT ≤ ΔI • ESR+
L
8 • fSW •COUT
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation com-
ponents and the output capacitor size. Typically, three to
four cycles are required to respond to a load step, but
only in the first cycle does the output drop linearly. The
wheref =operatingfrequency,C =outputcapacitance
SW
OUT
and ∆I = ripple current in the inductor. The output ripple
L
is highest at maximum input voltage since ∆I increases
L
with input voltage.
In surface mount applications, multiple capacitors may
be paralleled to meet the capacitance, ESR or RMS cur-
rent handling requirement of the application. Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitors are all available in surface mount packages.
output droop, V
, is usually about two to three times
DROOP
the linear drop of the first cycle. Thus, a good place to
Tantalumcapacitorshavethehighestcapacitancedensity,
but can have higher ESR and must be surge tested for
use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can often
be used in extremely cost-sensitive applications provided
that consideration is given to ripple current ratings and
long term reliability.
start is with the output capacitor size of approximately:
2.5 • ΔIOUT
fSW • VDROOP
COUT
≈
More capacitance may be required depending on the duty
cycleandloadsteprequirements.Inmostapplications,the
inputcapacitorismerelyrequiredtosupplyhighfrequency
bypassing, since the impedance to the supply is very low.
Ceramic Input and Output Capacitors
Ceramic capacitors have the lowest ESR and can be cost
effective, but also have the lowest capacitance density,
high voltage and temperature coefficients, and exhibit
3618fc
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Output Voltage Programming
feedback error signal that forces the regulator to adapt
to the current change and return V
to its steady-state
can be monitored
OUT
The output voltage of V
dividers. For example, V
following equation:
is set by external resistive
can be set according to the
DDQ
DDQ
value. During this recovery time, V
OUT
for excessive overshoot or ringing, which would indicate
a stability problem. The availability of the ITH pin allows
the transient response to be optimized over a wide range
of output capacitance.
R1
R2
VDDQ = 0.6V • 1+
TheITH1externalcomponents(15.8k and470pF)shown
in Figure 3 will provide an adequate compensation as
well as a starting point for most applications. The values
can be modified slightly to optimize transient response
once the final PCB layout is complete and the particular
output capacitor type and value have been determined.
The output capacitors need to be selected because the
various types and values determine the loop gain and
phase. The gain of the loop will be increased by increas-
The resistive divider allows pin V
to sense a fraction
FB1
of the output voltage as shown in Figure 3.
Pulse-Skipping Mode
V
pulse-skipping mode, which is a compromise
DDQ
between low output voltage ripple and efficiency, can be
implemented by connecting the MODE/SYNC pin to SV .
IN
In this condition, the peak inductor current is limited by
the minimum on-time of the current comparator. The low-
est output voltage ripple is achieved while still operating
discontinuously. During very light output loads, pulse-
skipping allows only a few switching cycles to skip while
maintaining the output voltage in regulation.
ing R and the bandwidth of the loop will be increased
C
by decreasing C . If R is increased by the same factor
C
C
that C is decreased, the zero frequency will be kept the
C
same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stabil-
ity of the closed-loop system. The external compensa-
tion, forced continuous operation circuit in the Typical
Applicationssectionusesfastercompensationtoimprove
load step response.
Internal and External Compensation
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC load current.
When a load step occurs, like the one shown in Figure 5,
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
V
OUT
shifts by an amount equal to ∆I
• ESR, where
LOAD
ESR is the effective series resistance of C . ∆I
OUT
LOAD
also begins to charge or discharge C , generating the
OUT
with C , causing a rapid drop in V . No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. More output
capacitance may be required depending on the duty cycle
and load step requirements.
V
OUT
200mV/DIV
If the ITH pin is tied to SV , the internal compensation
IN
I
L
1A/DIV
is selected.
3618 F05
V
V
LOAD
= 3.3V
IN
= 1.8V
OUT
I
= 600mA TO 2A
COMPENSATION AND OUTPUT
CAPACITOR VALUES OF FIGURE 3
Figure 5. Load Step Transient in FCM with
External Compensation
3618fc
16
For more information www.linear.com/LTC3618
LTC3618
applicaTions inForMaTion
Run and Soft-Start
Output Voltage Tracking Input
In the run state, the TRACK/SS1 pin can be used to track
down/up the output voltage of another supply for V . If
The RUNx pins provide a means to shut down each chan-
nel of the LTC3618. Pulling both pins below 0.3V places
the LTC3618 in a low quiescent current shutdown state
DDQ
V
again drops below 0.6V, the LTC3618 enters
TRACK/SS1
the down-tracking state and V
TRACK/SS1 voltage. If V
(I < 1µA).
Q
is referenced to the
reaches 0.1V value
DDQ
TRACK/SS1
After enabling the LTC3618 by bringing the RUNx pins
above the threshold, the enabled channels enter a soft-
start-up state. The type of soft-start behavior of V
setbytheTRACK/SS1pin. Thesoft-startcyclebeginswith
an initial discharge pulse pulling down the TRACK/SS1
pin to SGND and discharging the external capacitor C
(see Figure 3).
the switching frequency is reduced by 4x to ensure that
the minimum duty cycle limit does not prevent the output
from following TRACK/SS1 pin. The run state will resume
is
DDQ
if V
again exceeds 0.6V and V
is referenced
TRACK/SS1
to the internal reference.
DDQ
SS
Efficiency Considerations
The initial discharge is adequate to discharge capacitors
up to 33nF. If a larger capacitor is required, connect the
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc.
are the individual losses as a percentage of input power.
external soft-start resistor R to the RUN pin to fully
SS
discharge the capacitor.
1. Tying this pin to SV selects the internal soft-start
IN
circuit for V
to the final value within 1ms.
DDQ
2. If a longer soft-start period is desired, it can be
set externally with a resistor and capacitor on the
TRACK/SS1 pin as shown in Figure 3. The voltage ap-
pliedat theTRACK/SS1pinsetsthevalueoftheinternal
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
2
the losses: V quiescent current and I R losses. The V
IN
IN
referenceatV untilTRACK/SS1ispulledabove0.6V.
quiescent current loss dominates the efficiency loss at
FB1
2
The external soft-start duration can be calculated by
using the following equation:
very low load currents whereas the I R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
of little consequence.
SV
IN
t
SS1 =RSS •CSS •In
SV – 0.6V
IN
3. The TRACK/SS1 pin can be used to track the output
voltage of another supply.
1. TheV quiescentcurrentisduetotwocomponents:the
IN
DCbiascurrentasgivenintheElectricalCharacteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
fromswitchingthegatecapacitanceoftheinternalpower
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
The VTTR voltage follows the soft-start behavior of
V
at the same rate and ramps up V output voltage.
DDQ
TT
If RUN2 is pulled high later than RUN1, VTTR will follow
its internal soft-start, and ramps output voltage of V
at a rate of approximately 850mV/ms.
TT
from V to ground. The resulting dQ/dt is the current
IN
Regardless of either the internal or external soft-start
state,theMODE/SYNCpinisignoredduringstart-upand
defaultstopulse-skippingmode.Inaddition,thePGOOD
pin is kept low, and the frequency foldback function is
disabled.
out of V due to gate charge, and it is typically larger
IN
than the DC bias current. Both the DC bias and gate
chargelossesareproportionaltoV , thus, theireffects
IN
will be more pronounced at higher supply voltages.
3618fc
17
For more information www.linear.com/LTC3618
LTC3618
applicaTions inForMaTion
2
2. I R losses are calculated from the resistances of the
As an example, consider this case: the LTC3618 is in
dropout at an input voltage of 3.3V with a load current for
each channel of 2A at an ambient temperature of 70°C.
Assuming a 20°C rise in junction temperature, to 90°C,
internal switches, R , and external inductor R . In
SW
L
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
results in an R
of 0.086Ω (see the graph in the
DS(ON)
Typical Performance Characteristics section). Therefore,
the power dissipated by the part is:
top and bottom MOSFET R
(DC), as follows:
and the duty cycle
DS(ON)
2
2
P = (I + I ) • R = 0.69W
DS(ON)
D
1
2
R
= (R )(DC) + (R )(1 – DC)
DS(ON)TOP DS(ON)BOT
SW
For the QFN package, the θ is 46.9°C/W.
JA
The R
for both the top and bottom MOSFETs can
DS(ON)
Therefore, the junction temperature of the regulator op-
erating at 70°C ambient temperature is approximately:
be obtained from the Typical Performance Characteristics
2
curves. To obtain I R losses, simply add R to R and
SW
L
T = 0.69W • 46.9°C/W + 70°C = 102.4°C
J
multiply the result by the square of the average output
current.
Note that for very low input voltage, the junction tem-
perature will be higher due to increased switch resistance
Otherlosses,includingC andC ESRdissipativelosses
IN
OUT
R
. It is not recommended to use full load current at
and inductor core losses, generally account for less than
DS(ON)
high ambient temperature and low input voltage.
2% of the total loss.
To maximize the thermal performance of the LTC3618,
the exposed pad should be soldered to a ground plane.
See the PC Board Layout Checklist.
Thermal Considerations
In most applications, the LTC3618 does not dissipate
much heat due to its high efficiency. However, in ap-
plications where the LTC3618 is running at high ambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 160°C, all four power
switches will be turned off and the SW node will become
high impedance.
Design Example
As a design example, consider using the LTC3618 in an
application with the following specifications:
V = 3.3V to 5.5V
IN
V
V
= 1.8V
DDQ
TT
= 0.9V
I
I
I
= 3A
OUT1(MAX)
OUT2(MAX)
OUT1(MIN)
To prevent the LTC3618 from exceeding the maximum
junction temperature, the user will need to do some ther-
mal analysis to determine whether the power dissipated
exceeds the maximum junction temperature of the part.
The temperature rise is given by:
= 3A
= 200mA
f = 2.25MHz
First, calculate the timing resistor:
11
4• 10 Ω • Hz
T
RISE
= P • θ
D JA
RRT
=
= 178k
2.25MHz
where P is the power dissipated by the regulator, and
D
θ
is the thermal resistance from the junction of the die
JA
to the ambient temperature. The junction temperature,
T , is given by:
J
T = T + T
RISE
J
A
where T is the ambient temperature.
A
3618fc
18
For more information www.linear.com/LTC3618
LTC3618
applicaTions inForMaTion
The standard value of 10nF and 4.7M guarantees the
Next, calculate the inductor values for approximately 1A
minimum soft-start time of 5ms. In Figure 3, V
the schematic for this design example.
shows
ripple current at maximum V :
DDQ
IN
1.8V
2.25MHz •1A
1.8V
5.5V
L1=
L2 =
• 1–
• 1–
= 0.54µH
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3618:
0.9V
2.25MHz •1A
0.9V
5.5V
=
0.33µH
1. A ground plane is recommended. If a ground plane
layer is not used, the signal and power grounds should
besegregatedwithallsmallsignalcomponentsreturning
to the SGND pin at one point which is then connected to
thePGNDnodeattheexposedpadclosetotheLTC3618.
Using a standard value of 0.45µH inductor for both chan-
nels results in maximum ripple currents of:
1.8V
1.8V
5.5V
IL1
=
=
• 1–
• 1–
= 1.2A
2.25MHz • 0.45µH
2. Connect the (+) terminal of the input capacitors, C ,
IN
as close as possible to the PV pins, and the (–) ter-
INx
0.9V
2.25MHz • 0.45µH
0.9V
5.5V
minal as close as possible to the exposed pad PGND.
This capacitor provides the AC current into the internal
power MOSFETs.
IL2
=
0.71A
C
will be selected based on the ESR that is required to
OUT
3. Keep the switching nodes, SWx, away from all sensitive
small signal nodes FBx, ITHx, RT.
satisfy the output voltage ripple requirement and the bulk
capacitanceneededforloopstability.Forthisdesign,47µF
ceramiccapacitorswillbeusedwithX5RorX7Rdielectric.
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
powercomponents. ConnectthecopperareastoPGND
(exposed pad) for best performance.
C should be sized for a maximum current rating of:
IN
IOUT2
IOUT1
2
IRMS(MAX)
=
+
= 2ARMS
2
5. Connect the V pins directly to the feedback resis-
FBx
tors. The resistor divider must be connected between
Decoupling the PV with two 47µF X5R or X7R ceramic
capacitors is adequate for most applications.
IN
V
OUTx
and SGND.
Finally, itispossibletodefinethesoft-startuptimechoos-
ing the proper value for the capacitor and the resistor
connected to TRACK/SS1 pin. If one sets minimum T
SS
= 5ms and a resistor of 4.7M, the following equation can
be solved with the maximum SV = 5.5V:
IN
5ms
CSS
=
= 9.2nF
5.5V
4.7M •In
5.5V – 0.6V
3618fc
19
For more information www.linear.com/LTC3618
LTC3618
Typical applicaTions
External Compensation, Forced Continuous Operation,
In-Phase Switching, Common PGOOD Output
V
IN
3.3V
47µF
47µF
1µF
SV
IN
(2×) PV
(2×) PV
IN2
IN1
RUN1
VDDQIN
0.47µH
0.47µH
TRACK/SS1
V
DDQ
(2×) SW1
1.8V/ 3A
PGOOD1
ITH1
R1
10pF
47µF
845k
R
178k
LTC3618
T
10pF
R
C1
FB1
15.8k
R2
422k
RT
C
C1
470pF
VTTR
V
TT
(2×) SW2
0.01µF
0.9V/ 3A
47µF
MODE/SYNC
FB2
PHASE
RUN2
100k
PGOOD2
PGOOD
ITH2 SGND
PGND
3618 TA02a
R
10pF
C2
6.81k
C
C2
680pF
Load Step Transient VDDQ
Load Step Transient VTT
V
V
OUT
100mV/DIV
OUT
200mV/DIV
I
I
L
1A/DIV
L
1A/DIV
3618 TA02b
3618 TA02c
V
V
= 3.3V
V
V
= 3.3V
IN
IN
= 1.8V
= 0.9V
OUT
LOAD
OUT2
LOAD
I
= 200mA TO 2A
I
= –1A TO 1A
3618fc
20
For more information www.linear.com/LTC3618
LTC3618
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
24-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1771 Rev B)
Exposed Pad Variation 33
7.70 – 7.90*
3.25
(.128)
(.303 – .311)
3.25
(.128)
24 23 22 21 20 19 18 17 16 15 14 13
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10 11 12
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE24 (AA) TSSOP REV B 0910
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3618fc
21
For more information www.linear.com/LTC3618
LTC3618
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 0.05
4.50 0.05
3.ꢀ0 0.05
2.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.ꢀꢀ5
PIN ꢀ NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
0.75 0.05
4.00 0.ꢀ0
(4 SIDES)
TYP
23 24
PIN ꢀ
TOP MARK
(NOTE 6)
0.40 0.ꢀ0
ꢀ
2
2.45 0.ꢀ0
(4-SIDES)
(UF24) QFN 0ꢀ05 REV B
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3618fc
22
For more information www.linear.com/LTC3618
LTC3618
revision hisTory
REV
D3TE
DESCRIPTION
P3GE NUMBER
A
11/11 Added DDR Power Supply, Termination and Reference to Features
1
3
4
2
Added conditions to I
Removed Note 5
specification in Electrical Characteristics
LIMX
B
C
12/11 Inserted RUN1 Absolute Maximum Ratings
10/13 Modified Thermal Considerations section.
18
3618fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC3618
Typical applicaTion
External Compensation, 500kHz Sync ꢁ80° Phasing
V
IN
2.5V~5V
1µF
47µF
47µF
SV
(2×) PV
(2×) PV
IN2
IN
IN1
RUN1
VDDQIN
2.2µH
2.2µH
TRACK/SS1
V
DDQ
(2×) SW1
1.5V/ 3A
PGOOD1
ITH1
R1
10pF
47µF
845k
R
750k
LTC3618
T
10pF
R
C1
FB1
10k
R2
562k
RT
C
C1
V
REF
1000pF
VTTR
0.01µF
V
TT
(2×) SW2
0.75V/ 3A
47µF
×2
500kHz
MODE/SYNC
PHASE
FB2
RUN2
100k
PGOOD2
ITH2
PGOOD
10pF
SGND PGND
R
3618 TA03a
C2
6.49k
C
C2
1000pF
Efficiency vs Output Current of VDDQ
Efficiency vs Output Current of VTT
100
90
80
70
60
50
40
30
20
10
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100
90
80
70
60
50
40
30
20
10
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
V
V
= 2.5V
= 3.3V
= 5V
V
V
V
= 2.5V
= 3.3V
= 5V
IN
IN
IN
IN
IN
IN
10
10
0.001
0.01
0.1
1
0.001
0.01
0.1
1
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3618 TA03b
3618 TA03c
relaTeD parTs
P3RT NUMBER DESCRIPTION
COMMENTS
LTC3546
LTC3417A-2
LTC3612
LTC3614
LTC3616
LTC3617
5.5V, Dual 3A/1A, 4MHz, Synchronous Step-Down DC/ 95% Efficiency, V : 2.25V to 5.5V, V
= 0.6V, I = 160µA, I < 1µA,
Q SD
IN
OUT(MIN)
DC Converter
4mm × 5mm QFN-28 Package
5.5V, Dual 1.5A/1A, 4MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, V : 2.25V to 5.5V, V
= 0.8V, I = 125µA, I < 1µA,
Q SD
IN
OUT(MIN)
TSSOP-16E and 3mm × 5mm DFN-16 Packages
5.5V, 3A, 4MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, V : 2.25V to 5.5V, V = 0.6V, I = 75µA, I < 1µA,
IN
OUT(MIN)
Q
SD
3mm × 4mm QFN-20 and TSSOP-20E Packages
5.5V, 4A, 4MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, V : 2.25V to 5.5V, V = 0.6V, I = 75µA, I < 1µA,
IN
OUT(MIN)
Q
SD
3mm × 4mm QFN-20 and TSSOP-20E Packages
5.5V, 6A, 4MHz, Synchronous Step-Down DC/DC
Converter
95% Efficiency, V : 2.25V to 5.5V, V
= 0.6V, I = 75µA, I < 1µA,
OUT(MIN) Q SD
IN
3mm × 5mm QFN-24 Package
6A Monolithic Synchronous Buck for DDR Termination Over 90% Efficiency, V : 2.25V to 5.5V, 5k V
= 0.5V, 3mm × 5mm
IN
OUT(MIN)
QFN-24 Package
3618fc
LT 1013 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
LINEAR TECHNOLOGY CORPORATION 2013
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3618
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