LTC3624EDD-2#PBF [Linear]
LTC3624 - 17V, 2A Synchronous Step-Down Regulator with 3.5µA Quiescent Current; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C;型号: | LTC3624EDD-2#PBF |
厂家: | Linear |
描述: | LTC3624 - 17V, 2A Synchronous Step-Down Regulator with 3.5µA Quiescent Current; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C 开关 光电二极管 输出元件 |
文件: | 总18页 (文件大小:273K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3624/LTC3624-2
17V, 2A Synchronous
Step-Down Regulator with
3.5µA Quiescent Current
FeaTures
DescripTion
The LTC®3624/LTC3624-2 is a high efficiency 17V, 2A
synchronousmonolithicstep-downregulator.Theswitch-
ing frequency is fixed to 1MHz (LTC3624) or 2.25MHz
(LTC3642-2) with a 4ꢀ0 synchronization range. The
regulator features ultralow quiescent current and high
n
Wide V Range: 2.7V to 17V
IN
n
Wide V
Range: 0.6V to V
OUT
IN
n
n
n
n
n
95% Max Efficiency
Low I : 3.5µA, Zero-Current Shutdown
Q
Constant Frequency (1MHz/2.25MHz)
Fixed V
Options Available
efficiency over a wide V
range.
OUT
OUT
Low Dropout Operation (1ꢀꢀ0 Duty Cycle) with
The step-down regulator operates from an input voltage
range of 2.7V to 17V and provides an adjustable output
Ultralow I
Q
n
n
n
2A Rated Output Current
range from ꢀ.6V to V while delivering up to 2A of output
IN
10 Output Voltage Accuracy
current. A user-selectable mode input is provided to allow
the user to trade off ripple noise for light load efficiency;
Burst Mode operation provides the highest efficiency at
lightloads,whilepulse-skippingmodeprovidesthelowest
voltage ripple. The MODE pin can also be used to sync the
switching frequency to an external clock.
Current Mode Operation for Excellent Line and Load
Transient Response
n
n
Synchronizable to External Clock
Pulse-Skipping, Forced Continuous, Burst Mode®
Operation
Internal Compensation and Soft-Start
Overtemperature Protection
Compact 8-Lead DFN (3mm × 3mm) Package
n
n
n
LTC3624/LTC3624-2 Options
PART NAME
FREQUENCY
V
OUT
LTC3624
1MHz
Adjustable
3.3V
LTC3624-3.3
LTC3624-5
LTC3624-2
LTC3624-23.3
LTC3624-25
1MHz
applicaTions
1MHz
5V
n
Battery Powered Equipment
2.25MHz
2.25MHz
2.25MHz
Adjustable
3.3V
n
Portable Instrumentation
n
Emergency Radios
General Purpose Step-Down Supplies
5V
n
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 5481178, 658ꢀ258,
6498466, 6611131, 6177787, 57ꢀ5919, 5847554.
Typical applicaTion
Efficiency and Power Loss vs Load
100
90
80
70
60
50
40
30
20
10
0
1.2
1.0
0.8
0.6
0.4
0.2
0
5V VOUT with 800mA Burst Clamp, fSW = 1MHz
V
= 5V
OUT
3.3µH
V
5V
2A
OUT
V
IN
5.6V TO 17V
V
SW
LTC3624-5
RUN
MODE/SYNC
INTV
BURST MODE OPERATION
IN
10µF
V
47µF
OUT
36242 TA01a
CC
GND
2.2µF
V
V
V
= 12V
= 8V
= 6V
IN
IN
IN
FREQ = 1MHz
2
1.5
0
0.5
1
LOAD CURRENT (A)
3624 TA01b
36242fa
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For more information www.linear.com/LTC3624
LTC3624/LTC3624-2
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V Voltage................................................. –ꢀ.3V to 17V
IN
RUN Voltage............................................... –ꢀ.3V to 17V
MODE/SYNC, FB Voltages............................ –ꢀ.3V to 6V
SW
1
2
3
4
8
7
6
5
GND
V
IN
MODE/SYNC
9
GND
INTV , PGOOD Voltages ............................ –ꢀ.3V to 6V
RUN
INTV
CC
CC
PGOOD
FB (V
)
Operating Junction Temperature Range
OUT
(Notes 2, 5)............................................ –4ꢀ°C to 125°C
Storage Temperature Range .................. –65°C to 15ꢀ°C
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
T
= 125°C, θ = 43°C/W, θ = 5.5°C/W
JA JC
JMAX
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LGJF
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3624EDD#PBF
LTC3624EDD#TRPBF
LTC3624IDD#TRPBF
–4ꢀ°C to 125°C
–4ꢀ°C to 125°C
–4ꢀ°C to 125°C
–4ꢀ°C to 125°C
–4ꢀ°C to 125°C
–4ꢀ°C to 125°C
–4ꢀ°C to 125°C
–4ꢀ°C to 125°C
–4ꢀ°C to 125°C
–4ꢀ°C to 125°C
–4ꢀ°C to 125°C
–4ꢀ°C to 125°C
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
LTC3624IDD#PBF
LGJF
LTC3624EDD-3.3#PBF
LTC3624IDD-3.3#PBF
LTC3624EDD-5#PBF
LTC3624IDD-5#PBF
LTC3624EDD-2#PBF
LTC3624IDD-2#PBF
LTC3624EDD-23.3#PBF
LTC3624IDD-23.3#PBF
LTC3624EDD-25#PBF
LTC3624IDD-25#PBF
LTC3624EDD-3.3#TRPBF
LTC3624IDD-3.3#TRPBF
LTC3624EDD-5#TRPBF
LTC3624IDD-5#TRPBF
LTC3624EDD-2#TRPBF
LTC3624IDD-2#TRPBF
LTC3624EDD-23.3#TRPBF
LTC3624IDD-23.3#TRPBF
LTC3624EDD-25#TRPBF
LTC3624IDD-25#TRPBF
LGRG
LGRG
LGRD
LGRD
LGMN
LGMN
LGRH
LGRH
LGRF
LGRF
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
36242fa
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For more information www.linear.com/LTC3624
LTC3624/LTC3624-2
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C. (Note 2) VIN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
2.7
TYP
MAX
UNITS
V
V
Operating Voltage
Output Voltage Range
Input Quiescent Current
17
V
V
IN
ꢀ.6
V
IN
OUT
VIN
I
Shutdown Mode, V
= ꢀV
ꢀ.1
3.5
1.8
1.ꢀ
7
µA
µA
mA
RUN
Burst Mode Operation
Forced Continuous Mode (Note 3)
V
V
Regulated Feedback Voltage
ꢀ.594
ꢀ.591
ꢀ.6
ꢀ.6
ꢀ.6ꢀ6
ꢀ.6ꢀ9
V
V
FB
l
l
l
Regulated Fixed Output Voltage
LTC3624-3.3/LTC3624-23.3
LTC3624-5/LTC3624-25
3.267
3.25ꢀ
3.3
3.3
3.333
3.35ꢀ
V
V
OUT
4.95ꢀ
4.925
5.ꢀ
5.ꢀ
5.ꢀ5ꢀ
5.ꢀ75
V
V
ΔV
ΔV
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 2.7V to 17V (Note 4)
IN
ꢀ.ꢀ1
ꢀ.1
ꢀ.ꢀ15
0/V
0
LINE(REG)
LOAD(REG)
(Note 4)
I
NMOS Switch Leakage
PMOS Switch Leakage
ꢀ.1
ꢀ.1
1
1
µA
µA
LSW
R
NMOS On-Resistance
PMOS On-Resistance
Maximum Duty Cycle
Minimum On-Time
115
2ꢀꢀ
1ꢀꢀ
6ꢀ
mΩ
mΩ
0
DS(ON)
V
V
= 5V
IN
l
D
= ꢀ.5V, V = 1.5V
MODE/SYNC
MAX
FB
t
ns
ON(MIN)
V
RUN Input High
RUN Input Low
1.ꢀ
V
V
RUN
ꢀ.35
I
RUN Input Current
V
= 12V
ꢀ
1ꢀꢀ
ꢀ.3
nA
RUN
RUN
V
Pulse-Skipping Mode
Burst Mode Operation
Forced Continuous Mode
V
V
V
MODE/SYNC
V
– ꢀ.4
INTVCC
1.ꢀ
V
– 1.2
INTVCC
I
t
I
I
I
MODE/SYNC Input Current
Internal Soft-Start Time
Peak Current Limit
ꢀ
1
3
1ꢀꢀ
nA
ms
A
MODE/SYNC
SS
l
2.4
3.6
1ꢀ
LIM
FB Input Current
nA
µA
V
FB
Feedback Input Leakage Current
Fixed Output Versions
Ramping Up
2
1ꢀ
FB(VOUT)
V
V
V
V
V
V
V
V
Undervoltage Lockout
V
IN
2.4
18
2.6
175
19
2.7
UVLO
INTVCC
INTVCC
Undervoltage Lockout Hysteresis
mV
V
UVLO(HYS)
OVLO
l
Overvoltage Lockout Rising
2ꢀ
IN
IN
Overvoltage Lockout Hysteresis
5ꢀꢀ
mV
OVLO(HYS)
36242fa
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For more information www.linear.com/LTC3624
LTC3624/LTC3624-2
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C. (Note 2) VIN = 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1.ꢀꢀ
2.25
MAX
UNITS
f
Oscillator Frequency
LTC3624/LTC3624-3.3/LTC3624-5
ꢀ.92
ꢀ.82
1.ꢀ8
1.16
MHz
MHz
OSC
l
l
LTC3624-2/LTC3624-23.3/LTC3624-25
2.ꢀ5
1.8
2.45
2.6
MHz
MHz
f
SYNC Capture Range
LTC3624/LTC3624-3.3/LTC3624-5
5ꢀ
5ꢀ
15ꢀ
14ꢀ
4.ꢀ
0
0
V
SYNC
LTC3624-2/LTC3624-23.3/LTC3624-25
V
V
LDO Output Voltage
V > 4V
IN
3.2
3.6
7.5
7.5
INTVCC
INTVCC
ΔV
Power Good Range
LTC3624/LTC3624-2
11.5
13
0
0
PGOOD
LTC3624-3.3/LTC3624-5/LTC3624-23.3/
LTC3624-25
R
Power Good Resistance
PGOOD Delay
28ꢀ
35ꢀ
Ω
PGOOD
t
PGOOD Low to High
PGOOD High to Low
ꢀ
32
Cycles
Cycles
PGOOD
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
the ambient, T , and power dissipation, P , according to the following
A D
formula:
T = T + (P • θ )
JA
J
A
D
Note 3: The quiescent current in forced continuous mode does not include
switching loss of the power FETs.
Note 4: The LTC3624/LTC3624-2 is tested in a proprietary test mode that
Note 2: The LTC3624/LTC3624-2 is tested under pulsed load conditions
such that T ≈ T . The LTC3624E/LTC3624E-2 is guaranteed to meet
J
A
specifications from ꢀ°C to 85°C junction temperature. Specifications over
the –4ꢀ°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3624I/LTC3624I-2 is guaranteed over the –4ꢀ°C to 125°C
operating junction temperature range. Note that the maximum ambient
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
connects V to the output of error amplifier.
FB
Note 5: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when overtemperature
protection is active Continuous operation above the specified maximum
operating junction temperature may impair device reliability. The
overtemperature protection level is not production tested but guaranteed
by design.
thermal impedance and other environmental factors. T is calculated from
J
36242fa
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For more information www.linear.com/LTC3624
LTC3624/LTC3624-2
Typical perForMance characTerisTics TJ = 25°C, unless otherwise noted.
Efficiency vs Load Current in
Dropout
Efficiency vs Load Current in
Efficiency vs Load Current at 1MHz
Burst Mode Operation at 2.25MHz
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Burst Mode
OPERATION
FORCE CONTINUOUS
MODE
Burst Mode OPERATION
Burst Mode OPERATION
V
V
V
= 5V
= 3.3V
= 2.5V
V
V
V
= 5V
OUT
OUT
OUT
OUT
OUT
OUT
V
= 5V
IN
= 3V
100% DUTY CYCLE
FREQ = 1MHz
V
= 12V
= 2.5V
IN
V
= 12V
IN
0.0001
0.001
0.01
0.1
1 2
0.0001
0.001
0.01
0.1
1
2
0.001
0.01
0.1
1
2
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
36242 G03
36242 G01
36242 G02
Burst Mode Operation
IQ vs VIN
IQ vs Temperature
10
8
10
9
8
7
6
5
4
3
2
1
0
V
= 12V
IN
SW
5V/DIV
6
V
OUT
AC-COUPLED
50mV/DIV
SLEEP
SLEEP
4
I
L
1A/DIV
2
0
36242 G06
4µs/DIV
SHUTDOWN
V
V
= 12V
SHUTDOWN
75 100 125
TEMPERATURE (°C)
IN
OUT
= 2.5V
–50 –25
0
25
50
Burst Mode OPERATION
0
2
4
6
8
10 12 14 16 18 20
(V)
I
= 30mA
OUT
V
IN
L = 2.2µH
36242 G05
36242 G04
Pulse-Skipping Mode Operation
Load Transient Response
Soft-Start Operation
V
RUN
10V/DIV
OUT
SW
5V/DIV
200mV/DIV
V
I
OUT
L
I
L
AC-COUPLED
50mV/DIV
2A/DIV
0.5A/DIV
PGOOD
5V/DIV
V
OUT
1V/DIV
I
I
LOAD
2A/DIV
L
1A/DIV
36242 G07
36242 G08
36242 G09
4µs/DIV
40µs/DIV
1ms/DIV
V
V
= 12V
V
V
LOAD
= 12V
V
V
= 12V
IN
OUT
I
LOAD
IN
OUT
IN
= 2.5V
= 2.5V
= 2.5V
= 1A
OUT
PULSE-SKIPPING MODE
= 10mA
I
= 0A to 1.8A
I
FORCED CONTINUOUS MODE
OUT
L = 2.2µH
36242fa
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For more information www.linear.com/LTC3624
LTC3624/LTC3624-2
Typical perForMance characTerisTics TJ = 25°C, unless otherwise noted.
Oscillator Frequency
vs Temperature
Oscillator Frequency
vs Supply Voltage
Efficiency vs Input Voltage
100
90
80
70
60
50
40
30
2.0
1.5
2.0
1.5
1.0
0.5
0
I
= 1A
LOAD
I
= 10mA
LOAD
1.0
0.5
0
20
10
0
Burst Mode OPERATION
= 5V
V
OUT
FREQ = 1MHz
0
5
10
(V)
15
20
50
100 125
–50 –25
0
25
75
12
2
7
17
V
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
IN
36242 G10
36242 G11
36242 G12
Reference Voltage
vs Temperature
RDS(ON) vs Temperature
R
DS(ON) vs Input Voltage
600
500
600
500
400
300
200
100
0
600.5
600.0
599.5
599.0
V
= 12V
IN
400
300
TOP FET
TOP FET
200
100
0
598.5
598.0
597.5
BOTTOM FET
BOTTOM FET
50
100
150
2
4
6
8
10 12
(V)
14
16
–40
0
50
TEMPERATURE (°C)
–50
0
25
75 100 125
–25
V
TEMPERATURE (°C)
IN
36242 G14
36242 G13
36242 G15
Load Regulation
Line Regulation
VIN vs Peak Current Limit
0.80
0.60
0.40
0.20
0
0.80
0.60
0.40
0.20
0
5
4
3
2
1
0
FORCED CONTINUOUS MODE
–0.20
–0.40
–0.60
–0.80
–0.20
–0.40
–0.60
–0.80
0
1
1.5
2
0.5
2
8
10
(V)
12
14
16
0
2
4
6
8
10
4
6
12 14 16 18 20
36242 G18
LOAD CURRENT (A)
V
V
(V)
IN
IN
36242 G16
36242 G17
36242fa
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For more information www.linear.com/LTC3624
LTC3624/LTC3624-2
pin FuncTions
SW (Pin 1): Switch Node Connection to the Inductor of
the Step-Down Regulator.
INTV (Pin 6): Low Dropout Regulator. Bypass with at
CC
least 2.2µF to Ground.
V (Pin 2): Input Voltage of the Step-Down Regulator.
MODE/SYNC (Pin 7): Burst Mode Select and External
IN
Clock Synchronization of the Step-Down Regulator. Tie
RUN(Pin3):LogicControlledRUNInput.Donotleavethis
pin floating. Logic high activates the step-down regulator.
MODE/SYNC to INTV for Burst Mode operation with a
CC
8ꢀꢀmA peak current clamp, tie MODE/SYNC to GND for
PGOOD (Pin 4): V
within Regulation Indicator.
pulse skipping operation, and tie MODE/SYNC to a volt-
OUT
age between 1V and V
– 1.2V for forced continuous
INTVCC
FB (Pin 5): Feedback Input to the Error Amplifier of the
Step-Down Regulator. Connect a resistor divider tap to
this pin. The output voltage can be adjusted from ꢀ.6V
mode.Furthermore,connectingMODE/SYNCtoanexternal
clock will sync the system clock to the external clock and
put the part in forced continuous mode.
to V by:
IN
GND(Pin8,ExposedPadPin9):PowerandSignalGround.
Must be soldered to PCB ground for electrical and rated
thermal performance.
V
= ꢀ.6V • [1 + (R2/R1)]
OUT
See Figure 1.
ForfixedV
options, connecttheFBpindirectlytoV
.
OUT
OUT
block DiagraM
V
IN
1ms
SOFT-START
SLOPE
COMPENSATION
ERROR
AMPLIFIER
BURST
AMPLIFIER
MAIN
I-COMPARATOR
+
ITH
+
–
+
–
+
–
0.6V
FB
FIXED
OUT
V
V
CLK
MODE/SYNC
OSCILLATOR
LDO
OVERCURRENT
COMPARATOR
V
– 5V
IN
INTV
CC
SW
BUCK
LOGIC
+
–
AND
GATE DRIVE
RUN
INTV
CC
PGOOD
+
–
REVERSE
CURRENT
COMPARATOR
GND
36242 BD
36242fa
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For more information www.linear.com/LTC3624
LTC3624/LTC3624-2
operaTion
The LTC3624/LTC3624-2 uses a constant-frequency, peak
current mode architecture. It operates through a wide V
Tooptimizeefficiency,BurstModeoperationcanbeselected
by tying the MODE/SYNC pin to INTV . In Burst Mode
IN
CC
range and regulates with ultralow quiescent current. The
operation frequency is set at either 1MHz or 2.25MHz and
can be synchronized to an external oscillator 4ꢀ0 of the
inherent frequency. To suit a variety of applications, the
selectable MODE/SYNC pin allows the user to trade off
output ripple for efficiency.
operation, the peak inductor current is set to be at least
8ꢀꢀmA, even if the output of the error amplifier demands
less.Thus,whentheswitcherisonatrelativelylightoutput
loads, FB voltage will rise and cause the ITH voltage to
drop. Once the ITH voltage goes below ꢀ.2V, the switcher
goes into its sleep mode with both power switches off.
The switcher remains in this sleep state until the external
load pulls the output voltage below its regulation point.
During sleep mode, the part draws an ultralow 3.5µA of
The output voltage is set by an external divider returned to
the FB pin. An error amplifier compares the divided output
voltage with a reference voltage of ꢀ.6V and adjusts the
peak inductor current accordingly. Overvoltage and un-
dervoltage comparators will pull the PGOOD output low if
the output voltage is not within 7.50 of the programmed
value. The PGOOD output will go low 32 clock cycles after
falling out of regulation and will go high immediately after
achieving regulation.
quiescent current from V .
IN
To minimize V
ripple, pulse-skipping mode can be se-
OUT
lected by grounding the MODE/SYNC pin. In the LTC3624/
LTC3624-2,pulse-skippingmodeisimplementedsimilarly
to Burst Mode operation with the peak inductor current
set to be at least 132mA. This results in lower ripple than
in Burst Mode operation with the trade-off being slightly
lower efficiency.
Main Control Loop
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle.
The inductor current is allowed to ramp up to a peak level.
Once that level is reached, the top power switch is turned
off and the bottom switch (N-channel MOSFET) is turned
on until the next clock cycle. The peak current level is con-
trolledbytheinternallycompensatedITHvoltage,whichis
the output of the error amplifier. This amplifier compares
the FB voltage to the ꢀ.6V internal reference. When the
load current increases, the FB voltage decreases slightly
below the reference, which causes the error amplifier to
increase the ITH voltage until the average inductor current
matches the new load current.
Forced Continuous Mode Operation
Aside from the two discontinuous-conduction modes, the
LTC3624/LTC3624-2 also has the ability to operate in the
forced continuous mode by setting the MODE/SYNC volt-
age between 1V and V
– 1.2V. In forced continuous
INTVCC
mode, the switcher will switch cycle by cycle regardless
of what the output load current is. If forced continuous
mode is selected, the minimum peak current is set to
be –266mA in order to ensure that the part can operate
continuously at zero output load.
High Duty Cycle/Dropout Operation
When the input supply voltage decreases towards the
output voltage, the duty cycle increases and slope com-
pensation is required to maintain the fixed switching
frequency. The LTC3624/LTC3624-2 has internal circuitry
The main control loop is shut down by pulling the RUN
pin to ground.
Low Current Operation
to accurately maintain the peak current limit (I ) of 3A
LIM
Twodiscontinuous-conductionmodes(DCMs)areavailable
to control the operation of the LTC3624/LTC3624-2 at low
currents. Both modes, Burst Mode operation and pulse-
skipping, automatically switchfromcontinuousoperation
to the selected mode when the load current is low.
even at high duty cycles.
As the duty cycle approaches 1ꢀꢀ0, the LTC3624/
LTC3624-2 enters dropout operation. During dropout, if
force continuous mode is selected, the top PMOS switch
is turned on continuously, and all active circuitry is kept
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LTC3624/LTC3624-2
operaTion
alive. However, if Burst Mode operation or pulse-skipping
mode is selected, the part will transition in and out of
sleep mode depending on the output load current. This
significantly reduces the quiescent current, thus prolong-
ing the use of the input supply.
LTC3624-2 (F = 2.25MHz). In the rare cases that this
SW
minimum on-time is violated, the output voltage may lose
regulation. In such situation, the user must choose either
Burst Mode or pulse-skipping mode operation, or apply a
slowerexternalclocktoforceaslowerswitchingfrequency
in order to adhere to the minimum on-time limitation.
V Overvoltage Protection
IN
Low Supply Operation
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTC3624/LTC3624-2
TheLTC3624incorporatesanundervoltagelockoutcircuit
which shuts down the part when the input voltage drops
below 2.7V. As the input voltage rises slightly above the
undervoltage threshold, the switcher will begin its basic
constantly monitors the V pin for an overvoltage condi-
IN
tion. When V rises above 19V, the regulator suspends
IN
operation by shutting off both power MOSFETs. Once V
IN
drops below 18.5V, the regulator immediately resumes
normal operation. The regulator executes its soft-start
function when exiting an overvoltage condition.
operation. However, the R
of the top and bottom
DS(ON)
switch will be slightly higher than that specified in the
electrical characteristics due to lack of gate drive. Refer
to graph of R
versus V for more details.
DS(ON)
IN
Minimum On-Time
Soft-Start
The minimum on-time is the smallest duration of the time
the top power switch is allowed to be in its on state. This
timeistypically6ꢀns.Inforcedcontinuousmodeoperation,
theminimumon-timelimitimposesaminimumdutycycle
The LTC3624/LTC3624-2 has an internal 1ms soft-start
ramp. During start-up soft-start operation, the switcher
will operate in pulse-skipping mode.
of 60 for the LTC3624 (F = 1MHz) and 13.50 for the
SW
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LTC3624/LTC3624-2
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Output Voltage Programming
Output Capacitor (C ) Selection
OUT
The output voltage is set by external resistive divider ac-
cording to the following equation:
The selection of C
is determined by the effective series
OUT
resistance(ESR)thatisrequiredtominimizevoltageripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
R2
R1
VOUT =0.6V • 1+
the load transient response. The output ripple, ∆V , is
determined by:
OUT
The resistive divider allows the FB pin to sense a fraction
of the output voltage as shown in Figure 1.
1
∆VOUT <∆I
L
+ESR
V
OUT
8•f•COUT
R2
C
FF
The output ripple is highest at maximum input voltage
FB
since ∆I increases with input voltage. Multiple capaci-
R1
LTC3624
SGND
L
tors placed in parallel may be needed to meet the ESR
and RMS current handling requirements. Dry tantalum,
special polymer, aluminum electrolytic, and ceramic
capacitors are all available in surface mount packages.
Special polymer capacitors are very low ESR but have
lower capacitance density than other types. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
foruseinswitchingpowersupplies.Aluminumelectrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
CeramiccapacitorshaveexcellentlowESRcharacteristics
and small footprints.
36242 F01
Figure 1. Setting the Output Voltage
Input Capacitor (C ) Selection
IN
The input capacitance, C , is needed to filter the square
IN
wave current at the drain of the top power MOSFET. To
prevent large voltage transients from occurring, a low
ESR input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
VOUT
V
IN
VOUT
IRMS ≅IOUT(MAX)
–1
V
IN
This formula has a maximum at V = 2V , where:
IN
OUT
Using Ceramic Input and Output Capacitors
IOUT
2
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
IRMS
≅
This simple worst-case condition is commonly used for
design because even significant deviations do not offer
muchrelief.Notethatripplecurrentratingsfromcapacitor
manufacturers are often based on only 2ꢀꢀꢀ hours of life
which makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required.Severalcapacitorsmayalsobeparalleledtomeet
size or height requirements in the design. For low input
voltage applications, sufficient bulk input capacitance is
needed to minimize transient effects during output load
changes.
V input. Atbest, thisringingcancoupletotheoutputand
IN
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause
a voltage spike at V large enough to damage the part.
IN
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LTC3624/LTC3624-2
applicaTions inForMaTion
When choosing the input and output ceramic capacitors,
choose the X5R and X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-
acteristics of all the ceramics for a given value and size.
ize that the sync signal is gone. Once engaged in sync,
the LTC3624/LTC3624-2 immediately runs at the external
clock frequency.
Inductor Selection
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. Typically, five cycles are required to
respond to a load step, but only in the first cycle does the
Given the desired input and output voltages, the inductor
valueandoperatingfrequencydeterminetheripplecurrent:
V
V
OUT
OUT
∆I =
1–
L
V
f •L
IN(MAX)
Lower ripple current reduces power losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a trade-off between
component size, efficiency and operating frequency.
output voltage drop linearly. The output droop, V
, is
DROOP
usually about three times the linear drop of the first cycle.
Thus, a good place to start with the output capacitor value
is approximately:
ΔIOUT
COUT =3
f•VDROOP
A reasonable starting point is to choose a ripple current
that is about 4ꢀ0 of I
. To guarantee that ripple
OUT(MAX)
More capacitance may be required depending on the duty
cycle and load-step requirements. In most applications,
the input capacitor is merely required to supply high
frequency bypassing, since the impedance to the supply
is very low. A 1ꢀμF ceramic capacitor is usually enough
for these conditions. Place this input capacitor as close
current does not exceed a specified maximum, the induc-
tance should be chosen according to:
V
V
OUT
OUT
L =
1–
V
f • ∆I
IN(MAX)
L(MAX)
to the V pin as possible.
IN
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but is very dependent on the
inductance selected. As the inductance or frequency in-
creases, core losses decrease. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Output Power Good
When the LTC3624/LTC3624-2’s output voltage is within
the 7.50 window of the regulation point, the output
voltage is good and the PGOOD pin is pulled high with
an external resistor. Otherwise, an internal open-drain
pull-down device (28ꢀΩ) will pull the PGOOD pin low. To
prevent unwanted PGOOD glitches during transients or
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard”, which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
dynamicV changes,theLTC3624/LTC3624-2’sPGOOD
OUT
falling edge includes a blanking delay of approximately 32
switching cycles.
Frequency Sync Capability
The LTC3624/LTC3624-2 has the capability to sync to a
4ꢀ0 range of the internal programmed frequency. It
takes 2 to 3 cycles of external clock to engage the sync
mode, and roughly 2µs of no clocks for the part to real-
Different core materials and shapes will change the size/
currentandprice/currentrelationshipofaninductor.Toroid
or shielded pot cores in ferrite or permalloy materials are
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LTC3624/LTC3624-2
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small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. New designs for
surface mount inductors are available from Toko, Vishay,
Coilcraft, NEC/Tokin, Cooper, TDK and Würth Electronik.
Refer to Table 1 for more details.
Checking Transient Response
Theregularloopresponsecanbecheckedbylookingatthe
loadtransientresponse. Switchingregulatorstakeseveral
cyclestorespondtoastepinloadcurrent.Whenaloadstep
occurs, V
immediatelyshiftsbyanamountequaltothe
OUT
∆I
• ESR, where ESR is the effective series resistance
LOAD
of C . ∆I
also begins to charge or discharge C
OUT
LOAD
OUT
generatingafeedbackerrorsignalusedbytheregulatorto
Table 1. Inductor Selection Table
INDUCTANCE
(µH)
DCR
(mΩ)
MAX CURRENT
(A)
DIMENSIONS
(mm)
HEIGHT
(mm)
INDUCTOR
MANUFACTURER
XAL4ꢀ2ꢀ Series
1.ꢀ
1.5
2.2
13.25
21.45
35.2ꢀ
8.7
7.1
5.6
4.3 × 4.3
4.3 × 4.3
4.3 × 4.3
2.1
2.1
2.1
Coilcraft
www.coilcraft.com
XAL4ꢀ3ꢀ Series
3.3
4.7
6.8
26.ꢀ
4ꢀ.1
67.4
5.5
4.5
3.6
4.3 × 4.3
4.3 × 4.3
4.3 × 4.3
3.1
3.1
3.1
IHLP-1616BZ-11 Series
IHLP-2ꢀ2ꢀBZ-ꢀ1 Series
1.ꢀ
2.2
1
2.2
3.3
4.7
5.6
6.8
24
61
4.5
4.3 × 4.7
4.3 × 4.7
2
2
Vishay
www.vishay.com
3.25
18.9
45.6
79.2
1ꢀ8
113
139
7
5.4 × 5.7
5.4 × 5.7
5.4 × 5.7
5.4 × 5.7
5.4 × 5.7
5.4 × 5.7
2
2
2
2
2
2
4.2
3.3
2.8
2.5
2.4
FDVꢀ62ꢀ Series
1
18
37
51
68
5.7
4
3.2
2.8
6.7 × 7.4
6.7 × 7.4
6.7 × 7.4
6.7 × 7.4
2
2
2
2
Toko
www.toko.com
2.2
3.3
4.7
MPLCꢀ525L Series
HCPꢀ7ꢀ3 Series
1
16
24
4ꢀ
6.4
5.2
4.1
11
9
8
6
5.5
4.5
4
6.2 × 5.4
6.2 × 5.4
6.2 × 5.4
7 × 7.3
7 × 7.3
7 × 7.3
7 × 7.3
7 × 7.3
7 × 7.3
7 × 7.3
2.5
2.5
2.5
3
3
3
3
3
3
3
NEC/Tokin
1.5
2.2
www.nec-tokin.com
1
9
Cooper Bussmann
www.cooperbussmann.com
1.5
2.2
3.3
4.7
6.8
8.2
14
18
28
37
54
64
RLF7ꢀ3ꢀ Series
1
8.8
9.6
12
2ꢀ
31
45
6.4
6.1
5.4
4.1
3.4
2.8
6.9 × 7.3
6.9 × 7.3
6.9 × 7.3
6.9 × 7.3
6.9 × 7.3
6.9 × 7.3
3.2
3.2
3.2
3.2
3.2
3.2
TDK
www.tdk.com
1.5
2.2
3.3
4.7
6.8
WE-TPC 4828 Series
1.2
1.8
2.2
2.7
3.3
17
2ꢀ
23
27
3ꢀ
3.1
2.7
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
2.8
2.8
2.8
2.8
2.8
Würth Elektronik
www.we-online.com
2.5
2.35
2.15
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LTC3624/LTC3624-2
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2
return V
to its steady-state value. During this recovery
1. I R losses are calculated from the DC resistances of
the internal switches, R , and external inductor, R .
OUT
time, V
can be monitored for overshoot or ringing that
OUT
SW
L
would indicate a stability problem.
In continuous mode, the average output current flows
through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both top and bottom MOSFET R
cycle (DC) as follows:
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. In addition, a feedforward capacitor can
be added to improve the high frequency response, as
and the duty
DS(ON)
shown in Figure 1. Capacitor C provides phase lead by
R
SW
= (R )(DC) + (R )(1 – DC)
DS(ON)TOP DS(ON)BOT
FF
creating a high frequency zero with R2, which improves
TheR
forboththetopandbottomMOSFETscanbe
DS(ON)
the phase margin.
obtained from the Typical Performance Characteristics
2
Theoutputvoltagesettlingbehaviorisrelatedtothestability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to application Note 76.
curves. Thus to obtain I R losses:
2
2
I R losses = I
(R + R )
SW L
OUT
2. The switching current is the sum of the MOSFET driver
andcontrolcurrents.ThepowerMOSFETdrivercurrent
resultsfromswitchingthegatecapacitanceofthepower
MOSFETs. Each time a power MOSFET gate is switched
from low to high to low again, a packet of charge dQ
moves from IN to ground. The resulting dQ/dt is a cur-
rent out of IN that is typically much larger than the DC
Insomeapplications,amoreseveretransientcanbecaused
by switching in loads with large (>1µF) input capacitors.
The discharge input capacitors are effectively put in paral-
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
can deliver enough current to prevent this problem if the
switchconnectingtheloadhaslowresistanceandisdriven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates
currentlimiting, short-circuitprotectionandsoft-starting.
control bias current. In continuous mode, I
=
GATECHG
f(Q + Q ), where Q and Q are the gate charges of
T
B
T
B
the internal top and bottom power MOSFETs and f is
the switching frequency. The power loss is thus:
Switching Loss = I
• V
IN
GATECHG
The gate charge loss is proportional to V and f and
IN
Efficiency Considerations
thus their effects will be more pronounced at higher
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 1ꢀꢀ0.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
supply voltages and higher frequencies.
3. Other “hidden” losses such as transition loss and cop-
per trace and internal load resistances can account for
additional efficiency degradations in the overall power
system. It is very important to include these “system”
level losses in the design of a system. Transition loss
arises from the brief amount of time the top power
MOSFET spends in the saturated region during switch
node transitions. The LTC3624/LTC3624-2 internal
power devices switch quickly enough that these losses
are not significant compared to other sources. These
losses plus other losses, including diode conduction
losses during dead-time and inductor core losses,
generally account for less than 20 total additional loss.
0 Efficiency = 1ꢀꢀ0 – (L1 + L2 + L3 +…)
where L1, L2, etc. are the individual losses as a percent-
age of input power. Although all dissipative elements in
the circuit produce losses, three main sources usually
account for most of the losses in LTC3624/LTC3624-2
2
circuits: 1) I R losses, 2) switching and biasing losses,
3) other losses.
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Thermal Conditions
TheDFN3mm× 3mmpackagejunction-to-ambientthermal
resistance, θ , is around 43°C/W. Therefore, the junction
JA
Inamajorityofapplications,theLTC3624/LTC3624-2does
not dissipate much heat due to its high efficiency and
low thermal resistance of its exposed pad DFN package.
However, in applications where the LTC3624/LTC3624-2
temperature of the regulator operating in a 25°C ambient
temperature is approximately:
T = T + T = 25°C + ꢀ.556W • 43°C/W = 49°C
J
A
rise
is running at high ambient temperature, high V , high
IN
Remembering that the above junction temperature is
obtained from an R at 25°C, we might recalculate
switching frequency, and maximum output current load,
the heat dissipated may exceed the maximum junction
temperatureofthepart.Ifthejunctiontemperaturereaches
approximately 16ꢀ°C, both power switches will be turned
off until the temperature drops about 15°C cooler.
DS(ON)
the junction temperature based on a higher R
since
DS(ON)
it increases with temperature. Redoing the calculation
assuming that R increased 50 at 49°C yields a new
SW
junction temperature of 5ꢀ°C. If the application calls for
a higher ambient temperature and/or higher switching
frequency, care should be takentoreducethe temperature
rise of the part by using a heat sink or forced air flow.
To avoid the LTC3624/LTC3624-2 from exceeding the
maximum junction temperature, the user will need to do
some thermal analysis. The goal of the thermal analysis
is to determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3624/LTC3624-2 (refer to Figure 2). Check the
following in your layout:
T
RISE
= P • θ
D JA
As an example, consider the case when the LTC3624/
LTC3624-2isusedinapplicationswhereV =12V,I =2A,
IN
OUT
1. Do the capacitors C connect to the V and GND as
f = 1MHz, V
= 1.8V. The equivalent power MOSFET
IN
IN
OUT
close as possible? These capacitors provide the AC
resistance R is:
SW
currenttotheinternalpowerMOSFETsandtheirdrivers.
V
V
V
OUT
IN
RSW =RDS(ON)TOP
•
OUT +RDS(ON)BOT • 1–
2. Are C
and L closely connected? The (–) plate of
OUT
V
IN
C
returns current to GND and the (–) plate of C .
OUT
IN
1.8V
12V
1.8V
12V
+100mΩ • 1–
3. The resistive divider, R1 and R2, must be connected
=200mΩ•
between the (+) plate of C
and a ground line ter-
OUT
minated near GND. The feedback signal V should be
FB
=115mΩ
routed away from noisy components and traces, such
astheSWline,anditstracelengthshouldbeminimized.
Keep R1 and R2 close to the IC.
The V current during 1MHz force continuous operation
IN
with no load is about 8mA, which includes switching and
internal biasing current loss, transition loss, inductor core
loss and other losses in the application. Therefore, the
total power dissipated by the part is:
4. Solder the exposed pad (Pin 9) on the bottom of the
package to the GND plane. Connect this GND plane to
other layers with thermal vias to help dissipate heat
from the LTC3624/LTC3624-2.
2
P = I
• R + V • I
SW IN IN(Q)
D
OUT
2
= 2A • 115mΩ + 12V • 8mA
= 556mW
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5. Keep sensitive components away from the SW pin. The
Given the internal oscillator of 2.25MHz, we can calcu-
late the inductor value for about 4ꢀ0 ripple current at
input capacitor, C , feedback resistors, and INTV
IN
CC
bypass capacitors should be routed away from the SW
maximum V :
IN
trace and the inductor.
3.3V
2.25MHz •0.8A
3.3V
13.2V
1–
L=
=1.38µH
6. A ground plane is preferred.
7. Flood all unused areas on all layers with copper, which
reduces the temperature rise of power components.
These copper areas should be connected to GND.
Given this, a 1.5µH inductor would suffice.
will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, a
47µF ceramic capacitor will be used.
C
OUT
Design Example
Asadesignexample,considerusingtheLTC3624/LTC3624-2
in an application with the following specifications:
C should be sized for a maximum current rating of:
IN
V = 1ꢀ.8V to 13.2V
1/2
IN
3.3V 13.2V
IRMS =2A
–1 =0.86A
V
OUT
= 3.3V
13.2V 3.3V
I
I
f
= 2A
= ꢀA
OUT(MAX)
OUT(MIN)
BypassingtheV pintogroundwith1ꢀµFceramiccapaci-
IN
tors is adequate for most applications.
= 2.25MHz
SW
Because efficiency and quiescent current are important at
both 5ꢀꢀmA and ꢀA current states, Burst Mode operation
will be utilized.
TOP LAYER
BOTTOM LAYER
GND
V
GND
OUT
V
OUT
C
C
OUT
(OPT)
OUT
L1
(OPT)
C
OUT
LTC3624
C_INTVCC
V
IN
GND
C
IN
V
IN
C
IN
GND
C
IN
GND
GND
36242 F02a
36242 F02b
Figure 2a. Sample PCB Layout-Top Side
Figure 2b. Sample PCB Layout-Bottom Side
36242fa
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For more information www.linear.com/LTC3624
LTC3624/LTC3624-2
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
0.70 ±0.05
3.5 ±0.05
2.10 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50
BSC
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.125
0.40 ±0.10
TYP
5
8
3.00 ±0.10
(4 SIDES)
1.65 ±0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 0509 REV C
4
1
0.25 ±0.05
0.75 ±0.05
0.200 REF
0.50 BSC
2.38 ±0.10
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
36242fa
16
For more information www.linear.com/LTC3624
LTC3624/LTC3624-2
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
ꢀ4/14 Added fixed output options.
Clarified Ordering Information.
Clarified Electrical Specifications.
Clarified Pin Functions.
1
2
3, 4
7
36242fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC3624/LTC3624-2
Typical applicaTion
4.2VOUT, 1MHz, Burst Mode Operation
L1
2.2µH
V
OUT
V
IN
5V TO 17V
4.2V
V
SW
FB
IN
C
OUT
47µF
C
IN
10µF
2A MAX
604k
100k
22pF
LTC3624
RUN
MODE/SYNC
INTV
36242 TA02
CC
GND
2.2µF
L1: COILCRAFT XAL4020 -222ME
1.2VOUT, Synced to 500kHz, Forced Continuous Mode
L1
2.2µH
V
OUT
V
IN
2.7V TO 17V
V
SW
FB
1.2V
IN
C
OUT
47µF
C
IN
10µF
2A MAX
604k
604k
22pF
LTC3624
36242 TA03
RUN
MODE/SYNC
500kHz CLK
2.2µF
INTV
CC
GND
L1: COILCRAFT XAL4020 -222ME
12V Step-Down with 2A Output Current Limit, 2.25MHz
L1
1.5µH
V
V
IN
OUT
V
SW
FB
IN
13V TO 17V
12V
C
OUT
47µF
C
IN
10µF
619k
15pF
LTC3624
RUN
36242 TA04
MODE/SYNC
INTV
32.4k
CC
GND
2.2µF
L1: COILCRAFT XAL4020-152ME
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
950 Efficiency, V : 2.7V to 17V, V
LTC3621
17V, 1A, 2.25MHz/1MHz Synchronous Step-Down
DC/DC Converter
= ꢀ.6V, I = 3.5µA, I < 1µA,
OUT(MIN) Q SD
IN
2mm × 3mm DFN-6, MSOP-8E Packages
950 Efficiency, V : 4V to 15V, V = ꢀV, I = 7ꢀꢀµA, I < 1µA,
OUT(MIN) Q SD
LTC36ꢀꢀ
LTC36ꢀ1
LTC36ꢀ3
15V, 1.5A, 4MHz Synchronous Rail-to-Rail Single
Resistor Step-Down Regulator
IN
3mm × 3mm DFN-12, MSOP-12E Packages
15V, 1.5A (I ) 4MHz Synchronous Step-Down
950 Efficiency, V : 4.5V to 15V, V = ꢀ.6V, I = 3ꢀꢀµA, I < 1µA,
OUT
IN
OUT(MIN)
Q
SD
DC/DC Converter
4mm × 4mm QFN-2ꢀ, MSOP-16E Packages
15V, 2.5A (I ) 3MHz Synchronous Step-Down
950 Efficiency, V : 4.5V to 15V, V = ꢀ.6V, I = 75µA, I < 1µA,
OUT
IN
OUT(MIN)
Q
SD
DC/DC Converter
4mm × 4mm QFN-2ꢀ, MSOP-16E Packages
LTC3633/LTC3633A 15V/2ꢀV, Dual 3A (I ) 4MHz Synchronous
950 Efficiency, V : 3.6V to 15V/2ꢀV, V
= ꢀ.6V, I = 5ꢀꢀµA,
Q
OUT
IN
OUT(MIN)
Step-Down DC/DC Converter
I
< 15µA, 4mm × 5mm QFN-28, TSSOP-28E Packages
SD
LTC36ꢀ5/LTC36ꢀ5A 15V/2ꢀV, 5A (I ) 4MHz Synchronous Step-Down
950 Efficiency, V : 4V to 15V/2ꢀV, V
= ꢀ.6V, I = 2mA, I < 15µA,
OUT(MIN) Q SD
OUT
IN
DC/DC Converter
4mm × 4mm QFN-24 Package
LTC36ꢀ4
15V, 2.5A (I ) 4MHz Synchronous Step-Down
950 Efficiency, V : 3.6V to 15V, V
= ꢀ.6V, I = 3ꢀꢀµA, I < 14µA,
OUT(MIN) Q SD
OUT
IN
DC/DC Converter
3mm × 3mm QFN-16, MSOP-16E Packages
36242fa
LT 0614 REV A • PRINTED IN USA
18 LinearTechnology Corporation
163ꢀ McCarthy Blvd., Milpitas, CA 95ꢀ35-7417
●
●
(4ꢀ8)432-19ꢀꢀ FAX: (4ꢀ8) 434-ꢀ5ꢀ7 www.linear.com/LTC3624
LINEAR TECHNOLOGY CORPORATION 2014
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