LTC3625EDE#TRPBF [Linear]
LTC3625 - 1A High Efficiency 2-Cell Supercapacitor Charger with Automatic Cell Balancing; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C;
| 型号： | LTC3625EDE#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3625 - 1A High Efficiency 2-Cell Supercapacitor Charger with Automatic Cell Balancing; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C 光电二极管 |
| 文件： | 总16页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3625/LTC3625-1
1A High Efficiency 2-Cell
Supercapacitor Charger
with Automatic Cell
Balancing
FeaTures
DescripTion
TheLTC®3625/LTC3625-1areprogrammablesupercapaci-
tor chargers designed to charge two supercapacitors in
series to a fixed output voltage (4.8V/5.3V or 4V/4.5V
selectable) from a 2.7V to 5.5V input supply. Automatic
cell balancing prevents overvoltage damage to either
supercapacitorwhilemaximizingchargerate.Nobalancing
resistors are required.
n
High Efficiency Step-Up/Step-Down Charging of Two
Series Supercapacitors
n
Automatic Cell Balancing Prevents Capacitor
Overvoltage During Charging
n
Programmable Charging Current Up to 500mA
(Single Inductor), 1A (Dual Inductor)
n
V = 2.7V to 5.5V
IN
n
Selectable 2.4V/2.65V Regulation per Cell (LTC3625)
High efficiency, high charging current, low quiescent cur-
rent and low minimum external parts count (one inductor,
n
Selectable 2V/2.25V Regulation per Cell (LTC3625-1)
n
Low No-Load Quiescent Current: 23µA
onebypasscapacitoratV andoneprogrammingresistor)
IN
n
I
, I < 1µA in Shutdown
VOUT VIN
maketheLTC3625/LTC3625-1ideallysuitedforsmallform
n
Low Profile 12-lead 3mm × 4mm DFN Package
factor backup or high peak power systems.
applicaTions
Charging current/maximum input current level is pro-
grammedwithanexternalresistor.Whentheinputsupplyis
removedand/ortheENpinislow, theLTC3625/LTC3625-1
automatically enter a low current state, drawing less than
1µA from the supercapacitors.
n
Servers, RAID Systems, Mass Storage, High Current
Backup Supplies
n
Solid State Hard Drives
n
Wireless Power Meters
High Peak Power Boosted Supplies
n
The LTC3625/LTC3625-1 are available in a compact
12-lead 3mm × 4mm × 0.75mm DFN package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
Typical applicaTion
1A SCAP Charger
Charging Two 2:1 Mismatched Supercapacitors
6
LTC3625
V
V
OUT
C
C
= 50F
IN
TOP
BOT
V
IN
V
OUT
= 100F
2.7V TO 5.5V
4.8V
5
R
= 61.9k
10µF
PROG
3.3µH
3.3µH
SW2
SW1
CTL = 0
= 0
C
C
≥ 0.1F
TOP
BOT
V
SEL
4
3
V
OUT
V
MID
PROG
≥ 0.1F
61.9k
V
MID
2
1
0
PFI
EN
PGOOD
PFO
CTL
V
SEL
3625 TA01a
0
20 40 60 80 100 120 140 160 180 200
TIME (SECONDS)
3625 TA01b
3625f
ꢀ
LTC3625/LTC3625-1
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V , V
(Transient) t < 1ms,
IN OUT
Duty Cycle < 1% .......................................... –0.3V to 7V
SW1
1
2
3
4
5
6
12 SW2
V , V , V , PGOOD,
IN OUT MID
V
11
10
9
V
V
IN
OUT
MID
CTL, PROG, PFI, PFO ................................... –0.3V to 6V
CTL
13
GND
EN, V ........................................... –0.3V to V + 0.3V
V
PGOOD
PFO
SEL
IN
SEL
V
I
Short-Circuit Duration............................. Indefinite
EN
8
OUT
, I ............................................................50mA
PROG
7
PFI
PGOOD PFO
I
........................................................................1mA
VIN SW1 SW2 VOUT
Operating Junction Temperature Range
PROG
DE PACKAGE
12-LEAD (4mm s 3mm) PLASTIC DFN
I
, I , I
, I
(Note 2) ...................................3A
T
= 125°C, θ = 43°C/W
JA
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
JMAX
(Notes 3, 4)............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
orDer inForMaTion
LEAD FREE FINISH
LTC3625EDE#PBF
LTC3625EDE-1#PBF
LTC3625IDE#PBF
LTC3625IDE-1#PBF
TAPE AND REEL
PART MARKING*
3625
36251
3625
36251
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3625EDE#TRPBF
LTC3625EDE-1#TRPBF
LTC3625IDE#TRPBF
LTC3625IDE-1#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
12-Lead (4mm × 3mm) Plastic DFN
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, RPROG = 143k, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
V
Input Voltage Range
V
5.5
V
IN
IN(UVLO)
l
l
l
Input Undervoltage Lockout
(V Rising)
IN
V
SEL
V
SEL
V
SEL
= V (LTC3625)
2.8
2.53
2.53
2.9
2.63
2.63
3.0
2.73
2.73
V
V
V
IN(UVLO)
IN
= 0V (LTC3625)
= 0V or V (LTC3625-1)
IN
Input UVLO Hysteresis
100
mV
l
l
l
l
V
Charger Termination Voltage
V
SEL
V
SEL
V
SEL
V
SEL
= V (LTC3625)
5.2
4.7
4.4
3.9
5.3
4.8
4.5
4.0
5.4
4.9
4.6
4.1
V
V
V
V
OUT(SLEEP)
IN
= 0V (LTC3625)
= V (LTC3625-1)
IN
= 0V (LTC3625-1)
Recharge Hysteresis
Below V
135
mV
OUT(SLEEP)
l
l
l
l
V
, V
Maximum Voltage Across Either of
the Supercapacitors After Charging
V
SEL
V
SEL
V
SEL
V
SEL
= V , V = 5.3V (LTC3625)
IN OUT
2.7
2.45
2.3
2.75
2.5
2.35
2.1
V
V
V
V
TOP BOT
= 0V, V
= 4.8V (LTC3625)
= 4.5V (LTC3625-1)
= 4V (LTC3625-1)
OUT
IN OUT
= V , V
= 0V, V
2.05
OUT
Maximum Supercapacitor Offset
After Charging
CTL = 0V
CTL = V
100
50
180
120
mV
mV
IN
3625f
ꢁ
LTC3625/LTC3625-1
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, RPROG = 143k, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
CTL = V , V
MIN
TYP
MAX
UNITS
I
Input Operating Current,
= 1.5V, V
= 1.5V, V
= 2.5V (Boost Only)
= 3.5V (Buck Only)
135
275
365
200
400
530
µA
µA
µA
VIN
IN MID
OUT
OUT
I
= I
= 0µA, No Switching
CTL = V , V
IN MID
SW1
SW2
CTL = 0, V
= 1.5V, V
= 2.5V (Buck and Boost)
OUT
MID
Input Sleep Current
Input SD Current
V
V
= 5.5V, V
= 5.4V
= 5.4V
23
8
35
15
µA
µA
IN
IN
OUT
OUT
= 3.6V, V
V
OUT
V
OUT
= 0V
0
0
1
1
µA
µA
I
V
V
SD Current
= 5.4V
VOUT
OUT
OUT
Sleep Current
V
V
= 5.4V, V = 3.6V, EN = V
= 5.4V, V = 5.5V, EN = V
17
1
25
2.5
µA
µA
OUT
OUT
IN
IN
IN
IN
l
V
PROG Servo Voltage
Ratio of Measured I
V
OUT
= 3.5V, V = 1.5V
MID
1.17
1.2
1.23
V
PROG
h
Current to
118,000
PROG
PROG
I
Programmed Current
BUCK
I
Programmed Buck Charge Current
R
R
= 143k (Note 5)
= 71.5k (Note 5)
0.88
1.76
0.99
1.98
1.10
2.20
A
A
BUCK
MAX
PROG
PROG
I
Maximum Programmed Charge
Current
R
PROG
= 0Ω (Fault Condition) (Note 5)
1.98
2.65
1.35
150
3.31
A
V
V
Voltage Where the Boost
MID
V
MID(GOOD)
Regulator is Enabled
V
V
Hysteresis
mV
V
MID(GOOD)
V
Voltage Above Which Boost
V
Rising
V
MID
TRICKLE
OUT
OUT
Regulator Will Exit Trickle Charge
Mode and Enter Normal Charge
Mode
V
Falling Hysteresis
50
mV
A
TRICKLE
I
I
I
Buck Charge Current Peak
Buck Charge Current Valley
Boost Charge Current Peak
1.1 • I
0.9 • I
PEAK(BUCK)
VALLEY(BUCK)
PEAK(BOOST)
BUCK
BUCK
A
V
V
= 3V, V
= 1V, V
= 2V (Note 5)
= 2V (Note 5)
1.59
1.41
2.12
200
2.65
2.35
A
mA
OUT
OUT
MID
MID
I
Boost Charge Current Valley
V
OUT
V
OUT
= 3V, V
= 1V, V
= 2V
= 2V
1.88
0
A
mA
VALLEY(BOOST)
MID
MID
Maximum Boost Valley Time
PMOS On-Resistance
V
= 1V, V
= 2V
6.5
120
100
µs
mΩ
mΩ
µA
OUT
MID
R
R
PMOS
NMOS
LEAK
NMOS On-Resistance
I
SW Pin Leakage Current for SW1, EN = 0V
SW2
1
l
V
PFI Falling Threshold
PFI Hysteresis
1.17
1.2
1.2
15
0
1.23
V
mV
nA
PFI
I
Pin Leakage Current for PFI Pin
30
0.4
1
PFI
Logic (EN, CTL, V , PGOOD, PFO)
SEL
l
l
V
V
Input Low Logic Voltage
EN, CTL, V Pins
V
V
IL
SEL
Input High Logic Voltage
EN, CTL, V Pins
IH
SEL
I , I
IL IH
Input Low, High Current for CTL
EN Pin Pull-Down Resistance
CTL
µA
R
4.5
4.5
70
MΩ
MΩ
mV
µA
PD
V
SEL
Pin Pull-Down Resistance
EN = V
IN
l
V
OL
Output Low Logic Voltage
Logic High Leakage Current
PGOOD Rising Threshold
PGOOD Hysteresis
PGOOD, PFO Pins; Sinking 5mA
200
1
I
PGOOD, PFO Pins; Pin Voltage = 5V
OH
V
OUT
as a Percentage of Final Target
90
92.5
3
95
%
%
3625f
∆V
as a Percentage of Final Target
OUT
ꢂ
LTC3625/LTC3625-1
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
The junction temperature (T in °C) is calculated from the ambient
J
temperature (T in °C) and power dissipation (P in Watts) according to
A
D
the formula:
T = T + (P • θ )
JA
J
A
D
Note 2: The LTC3625/LTC3625-1 internal switches are guaranteed to
survive up to 3A of peak current. Internal current limits will restrict peak
current to lower levels.
where θ (in °C/W) is the package thermal impedance.
JA
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability or permanently damage the
device.
Note 3: The LTC3625/LTC3625-1 are tested under pulsed load conditions
such that T ≈ T . The LTC3625E/LTC3625E-1 are guaranteed to meet
J
A
specifications from 0°C to 85°C junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3625I/LTC3625I-1 are guaranteed over the –40°C to 125°C
operating junction temperature range.
Note 5: Measurements are tested with CTL = 0V.
Typical perForMance characTerisTics
TA = 25°C, L1 = 3.3µH, L2 = 3.3µH, CIN = 10µF, CTOP = CBOT, LTC3625 unless otherwise specified.
Charge Termination Error
vs Temperature
Input and Output Sleep Currents
vs Temperature
Sleep Current vs VIN
2.0
1.5
25
20
15
10
5
25
20
15
10
5
V
= 3.6V
V
V
= 3.6V
SEL
V
V
= 4.8V
= 0V
IN
IN
OUT
SEL
= 3.6V
LTC3625 I
OUT
VOUT
V
= 5.3V
1.0
I
VOUT
0.5
SLEEP THRESHOLD
WAKE THRESHOLD
LTC3625-1 I
VOUT
0
V
= 4.5V
OUT
–0.5
–1.0
–1.5
–2.0
I
VIN
I
VIN
0
0
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
3625 G13
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
3625 G14
2.7 3.1 3.5 3.9 4.3
(V)
4.7 5.1 5.5
V
IN
3625 G01
PROG Voltage and PFI Falling
Threshold vs Temperature
Buck Current Limits
vs Temperature
Buck Output Current vs RPROG
1200
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
1.180
3000
2500
V
= 3.6V
PROG
I
IN
V
V
= 3.6V
MID
CTL = 0V
PEAK
IN
R
= 143k
1150
1100
1050
1000
950
= 2V
I
PROG
CLAMPED
2000
1500
I
1000
500
0
VALLEY
900
850
V
= 3.6V
PROG
IN
R
= 143k
800
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
50 100 150 200 250 300 350 400 450 500
(kΩ)
R
PROG
3625 G02
3625 G03
3625 G04
3625f
ꢃ
LTC3625/LTC3625-1
Typical perForMance characTerisTics
TA = 25°C, L1 = 3.3µH, L2 = 3.3µH, CIN = 10µF, CTOP = CBOT, LTC3625 unless otherwise specified.
Buck Input Power vs RPROG
Buck Efficiency vs IBUCK
Buck Input Power vs VMID
8
7
6
5
4
3
2
1
0
100
95
90
85
80
75
70
65
60
55
50
6
5
4
3
2
1
0
V
V
= 5.5V
MID
V
V
= 5.5V
= V
IN
IN
IN
SEL
CTL = 0
I
PROG
= 2.65V
CLAMPED
CTL = 0V
= V
V
SEL
IN
R
PROG
= 71.5k
R
PROG
= 143k
R
PROG
= 286k
2.2
V
V
= 3.6V
MID
CTL = 0V
IN
= 2V
0
50 100 150 200 250 300 350 400 450 500
(kΩ)
200
700
1200
1700
(mA)
2200
0.2
1.0
1.4
(V)
1.8
2.6
0.6
V
R
I
MID
PROG
BUCK
3625 G05
3625 G06
3625 G07
Buck Efficiency vs VMID
Buck Output Current vs VMID
Boost Input Current vs VTOP
100
90
80
70
60
50
40
2500
2250
2000
1750
1500
1250
1000
750
2500
V
V
= 5.5V
= V
IN
SEL
CTL = 0
R
PROG
= 71.5k
IN
NORMAL OPERATION
2000
1500
R
= 71.5k
PROG
R
PROG
= 143k
R
= 143k
= 286k
PROG
R
PROG
= 286k
1000
500
0
R
PROG
V
OUT
V
V
V
= 3.6V
IN
500
TRICKLE
CHARGE
= 2.5V
V
V
= 5.5V
= V
MID
TOP
IN
SEL
CTL = 0
= V
OUT
– V
MID
250
IN
OPERATION
CTL = 0
0
0.2
1.0
1.4
(V)
1.8
2.2
2.6
0.6
0.2 0.6
1.4
(V)
1.8
2.2
2.6
0.5
(V)
1.0
–1.5 –1.0 –0.5
0
1.0 1.5 2.0 2.5
V
V
V
MID
MID
TOP
3625 G08
3625 G09
3625 G10
Boost Efficiency vs VTOP
RFET vs Temperature
Charge Time vs RPROG
400
350
300
250
200
150
100
50
90
80
0.20
0.15
0.10
0.05
0
0.25
V
V
V
C
= 3.6V
= 3.6V
IN
NORMAL OPERATION
SEL
OUT
TOP
INITIAL = 0V
= C = 10F
BOT
0.20
0.15
0.10
0.05
70
PMOS
NMOS
SINGLE
60
50
40
30
V
TRICKLE
OUT
INDUCTOR
CHARGE OPERATION
APPLICATION
DUAL
INDUCTOR
APPLICATION
V
V
V
= 3.6V
IN
I
PROG
CLAMPED
= 2.5V
MID
TOP
V
V
= 2.7V
= 5.5V
IN
IN
= V
– V
MID
OUT
CTL = 0
0
20
–0.5
0
0.5 1.0
(V)
2.5
–1.5 –1.0
1.5 2.0
–40 –25 –10
5
20 35 50 65 80 95 110
TEMPERATURE (°C)
0
50 100 150 200 250 300 350 400 450 500
(kΩ)
125
V
R
PROG
TOP
3625 G11
3625 G12
3625 G15
3625f
ꢄ
LTC3625/LTC3625-1
Typical perForMance characTerisTics
TA = 25°C, L1 = 3.3µH, L2 = 3.3µH, CIN = 10µF, CTOP = CBOT, LTC3625 unless otherwise specified.
Charge Profile Into Matched
SuperCaps
Charge Profile with CBOT > CTOP
Charge Profile with CTOP > CBOT
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
V
V
R
C
= 3.6V, V
= 3.6V
V
R
C
= 3.6V, V
SEL
= 3.6V
V
R
C
= 3.6V, V
= 3.6V
OUT
IN
SEL
IN
IN
SEL
V
V
V
OUT
OUT
= 143k
= 143k
PROG
= 143k
PROG
PROG
= 10F, C
= 50F
= 50F, C
BOT
= 10F
= C
= 10F
TOP
BOT
TOP
TOP
BOT
V
MID
V
MID
MID
SINGLE INDUCTOR APPLICATION
SINGLE INDUCTOR APPLICATION
SINGLE INDUCTOR APPLICATION
V
OUT
V
MID
V
OUT
V
MID
V
OUT
V
MID
DUAL INDUCTOR APPLICATION
DUAL INDUCTOR APPLICATION
100 150
200
TIME (SECONDS)
DUAL INDUCTOR APPLICATION
20 40 60 80 100
TIME (SECONDS)
120
140
50
250
50 100 150 200 250 300 350
0
0
0
TIME (SECONDS)
3625 G16
3625 G17
3625 G18
pin FuncTions
SW1 (Pin 1): Switch Pin for the Buck Regulator. External
inductor connects between SW1 pin and V
PROG (Pin 6): Charge Current Program Pin. Connecting a
resistor from PROG to ground programs the buck output
current. This pin servos to 1.2V.
.
MID
V (Pin 2): Input Voltage Pin. Bypass to GND with a 10µF
IN
or larger ceramic capacitor.
PFI (Pin 7): Input to the Power Fail Comparator. This pin
connects to an external resistor divider between V and
IN
CTL (Pin 3): Logic Input. CTL sets the charge mode of the
LTC3625/LTC3625-1.AlogichighatCTLprogramsthepart
to operate with a single inductor; a logic low programs
the part to operate with two inductors. In the 2-inductor
application the capacitor stack will charge approximately
twice as quickly. CTL is a high impedance input and must
GND. If this functionality is not desired, PFI should be
tied to V .
IN
PFO(Pin8):Open-DrainOutputofthePower-FailCompara-
tor. The part pulls this pin low if V is less than a value
IN
programmed by an external divider. This pin is active low
in shutdown mode. If this functionality is not desired PFO
should be left unconnected.
be tied to either V or GND. Do not float.
IN
V
(Pin 4): Logic Input. V
selects the output volt-
SEL
SEL
age of the LTC3625/LTC3625-1. A logic low at V
sets
OUT
PGOOD (Pin 9): Logic Output. This is an open-drain
SEL
the per-cell maximum voltage to 2.45V/2.05V (V
=
output which indicates that V
has settled to its final
OUT
4.8V/4.0V); a logic high sets the per-cell maximum volt-
age to 2.70V/2.30V (V = 5.3V/4.5V). When the part is
value. Upon start-up, this pin remains low until the output
voltage, V , is within 92.5% (typical) of its final value.
OUT
OUT
enabled, V has a 4.5MΩ internal pull-down resistor; if
Once V
is valid, PGOOD becomes high impedance. If
SEL
OUT
EN is low, then V is a high impedance input pin.
V
falls to 89.5% (typical) of its correct regulation level,
SEL
OUT
PGOOD is pulled low. PGOOD may be pulled up through
an external resistor to an appropriate reference level. This
pin is active low in shutdown mode.
EN (Pin 5): Logic Input. Enables the LTC3625/LTC3625-1.
Active high. Has a 4.5MΩ internal pull-down resistor.
3625f
ꢅ
LTC3625/LTC3625-1
pin FuncTions
V
(Pin 10): Midpoint of Two Series Supercapacitors.
SW2(Pin12):SwitchPinfortheBoostRegulator. External
MID
The pin voltage is monitored and used, along with V
,
inductor connects between the SW2 pin and V . If CTL
OUT
MID
to enable or shut down the buck and boost converters
during charging to achieve voltage balancing of the top
and bottom supercapacitors.
is logic high, then SW2 must be connected to SW1.
GND (Exposed Pad Pin 13): Ground. The exposed pad
must be connected to a continuous ground plane on
the printed circuit board directly under the LTC3625/
LTC3625-1 for electrical contact and to achieve rated
thermal performance.
V
OUT
(Pin 11): Output Voltage Pin. Connect V
to the
OUT
positive terminal of the top supercapacitor. The pin volt-
age is monitored and used, along with V , to enable or
MID
shut down the buck and boost converters during charg-
ing to achieve voltage balancing of the top and bottom
supercapacitors.
block DiagraM
PFI
7
+
PFO
8
1.20V
–
BOOST REGULATOR
V
OUT
11
12
+
2A AVG
D
C
INPUT CURRENT
SYNCHRONOUS
BOOST CURRENT
REGULATOR
PGOOD
SD_BOOST
SW2
9
–
4.44V/4.90V (LTC3625)
3.7V/4.16V (LTC3625-1)
V
V
SEL
MID
THRESHOLD
DETECTOR
V
OUT
4
IN
V
MAXER
V
10
V
IN
BUCK REGULATOR
2
1
REF/R PROGRAMMED
AVG OUTPUT CURRENT
SYNCHRONOUS
A
B
EN
5
3
SW1
MASTER
LOGIC
V
MID_GOOD
SD_BUCK
CTL
BUCK CURRENT
REGULATOR
OVERTEMPERATURE
SHUTDOWN
1.2V
+
–
PROG
6
+
–
GND
13
3625 BD
3625f
ꢆ
LTC3625/LTC3625-1
operaTion
TheLTC3625/LTC3625-1aredualcellsupercapacitorchar-
gers. Their unique topology charges two series connected
capacitors to a fixed output voltage with programmable
charging current without overvoltaging either of the cells
—even if they are severely mismatched. No balancing
resistorsarerequired.TheLTC3625/LTC3625-1includean
The buck converter regulates the current hysteretically by
switching on the buck PMOS until a peak current limit is
reached and then turning on the buck NMOS until a valley
current limit is reached. In the single inductor application
the boost NMOS is used in conjunction with the buck
NMOS to increase efficiency at high currents. The forward
internal buck converter between V and V
to regulate
current limit is set to 1.1 • I
(typical) and the valley
IN
MID
BUCK
the voltage on C
(across the bottom capacitor) as well
current limit is set to 0.9 • I
(typical). Because of this
BOT
BUCK
as an internal boost converter between V
and V
to
methodofregulation,overcurrentlimitandreverse-current
limit protection is automatically provided. The LTC3625/
LTC3625-1 will continue to regulate its programmed cur-
rent even into a grounded output.
MID
OUT
regulatethevoltageonC (acrossthetopcapacitor).The
TOP
output current of the buck converter is user-programmed
via the PROG pin and the input current of the boost con-
verter is set at 2A (typical).
InfaultconditionswherethePROGpinisshortedtoground,
Table 1 indicates the various functions of the LTC3625/
LTC3625-1 that can be digitally controlled.
orR
isconductiveenoughtoprogramI
tooperate
PROG
BUCK
outside of specification, the current out of the PROG pin
will be clamped to 22.5µA (typical) and I will be set to
BUCK
Table 1. Digital Input Functions
2.65A (typical). If input current limit is not a concern, the
PROG pin may be grounded to minimize charge times.
PIN
VALUE
FUNCTION
CTL*
0
1
0
1
0
Part runs in 2-inductor application
Part runs in 1-inductor application
4.8V/4.0V sleep threshold
5.3V/4.5V sleep threshold
Boost Converter
V
SEL
Theboostconverterregulatesafixedaverageinputcurrent
of 2A (typical). The current is regulated hysteretically by
switchingontheboostNMOSuntilthepeakcurrentlimitof
2.12A(typical)isreached, andturningontheboostPMOS
until the valley current limit of 1.88A (typical) is reached.
In the single inductor application the buck NMOS is used
inconjunctionwiththeboostNMOStoincreaseefficiency.
Becauseofthismethodofregulation,overcurrentlimitand
reverse-current limitprotection is automatically provided.
EN
Part shuts down, V
becomes high
OUT
impedance
1
Part enables and regulates the output
*CTL pin must be hard tied to either V or GND.
IN
V Undervoltage Lockout (UVLO)
IN
An internal undervoltage lockout circuit monitors V and
IN
IN
keeps the LTC3625/LTC3625-1 disabled until V rises
above 2.90V/2.63V (typical) if V is high or 2.63V/2.63V
In normal operation V
will increase with V
MID
due to a faulty precondition or a
so V
SEL
OUT
MID OUT
(typical) if V
is low. Hysteresis on the UVLO turns off
should never be below V . In the case where there is a
SEL
the LTC3625/LTC3625-1 if V drops by approximately
reverse voltage on C
IN
TOP
100mV below the UVLO rising threshold. When in UVLO,
large load on the output, the boost converter will operate
in trickle charge mode. In this mode the boost PMOS
gate will remain high and instead allow the SW2 node to
only current needed to detect a valid input will be drawn
from V and V
.
IN
OUT
increase until SW2 ≈ V
+ 1V to allow a higher reverse
MAX
Buck Converter
voltageacrosstheinductor,andthecurrentisrampeddown
to 0mA. This will result in a less efficient charge delivery
Thebuckconverterregulatesauser-programmedaverage
output current given by:
throughthePMOS.Tokeepdissipationlow,I
islimited
PEAK
to 200mA (typical). In this mode the discharge phase is
terminated if it lasts longer than 6.5µs (typical).
1.2V
RPROG
IBUCK =hPROG
•
The boost converter is disabled if V
MID(GOOD)
falls below the
MID
V
hysteresis threshold of 1.2V (typical).
where h
= 118,000 (typical).
PROG
3625f
ꢇ
LTC3625/LTC3625-1
operaTion
Single Inductor Operation
the inductor current reaches 0mA. This optimizes charge
delivery to the output capacitors.
With the CTL pin tied to V the LTC3625/LTC3625-1 will
IN
operate in single inductor mode. In this mode the same
inductor serves in the power path for both the buck and
the boost converters. Thus, the buck converter and boost
converter will never run simultaneously.
Chargetimeisdependantontheprogrammedbuckoutput
current as well as the value of the supercapacitors being
charged.Forestimatingchargeprofilesinthesingleinduc-
torapplication,seetheTypicalPerformanceCharacteristics
graph Charge Time vs R
.
PROG
Under certain conditions with a single inductor, a small
amountofcurrentcanflowfromthesupercapacitorstoV
The effective average V
be approximated as:
referred charge current can
OUT
IN
when the boost charger is active. A 25mA load is required
on V to prevent the V supply from being pumped to
IN
IN
2A
IBUCK +2A
a higher voltage while the boost is active. This minimum
load is not needed in the two inductor application and it
is also not needed when the charger is disabled.
ICHARGE ≅ 0.5•IBUCK •εBOOST
•
where ε
is the boost converter efficiency, which is
BOOST
Atypicalchargecycleforafullydischargedcapacitorstack
will proceed as follows:
typically about 85% (see the Typical Performance Char-
acteristics graph Boost Efficiency vs V ).
TOP
1. The buck converter will turn on and regulate its output
Seen another way, this is the maximum steady-state load
current ramping hysteretically between 1.1 • I
and
the part can support without losing V
regulation.
BUCK
OUT
0.9 • I
until the V
threshold is met (1.35V
BUCK
typical).
MID(GOOD)
Dual Inductor Operation
With the CTL pin tied to GND, the LTC3625/LTC3625-1
will operate in dual inductor mode. In this mode two
inductors will serve as the power path for the buck and
the boost converters. This will allow both the buck and
the boost converter to run simultaneously. As a result, the
total charge time will be greatly reduced at the cost of an
additional board component.
2. Once the V
threshold is reached, the boost
MID(GOOD)
converter will turn on and regulate its input current
ramping hysteretically between 2.12A and 1.88A until
V
falls below the V
hysteresis threshold
MID
MID(GOOD)
(1.2V typical).
3. Phases1and2willalternateuntilV
isapproximately
OUT
2.4V.WhenV (equaltoV –V )isapproximately
TOP
OUT
MID
Atypicalchargecycleforafullydischargedcapacitorstack
will proceed as follows:
50mV > V , the boost regulator will turn off and the
MID
buck regulator will turn on. Likewise, when V
is
MID
approximately 50mV > V , the boost regulator will
TOP
1. The buck converter will turn on and regulate its output
turn on and the buck regulator will turn off.
current ramping hysteretically between 1.1 • I
BUCK
threshold is met
and 0.9 • I
until the V
4. Phase 3 will continue until V
has reached its pro-
BUCK
MID(GOOD)
OUT
(1.35V typical).
grammed output voltage. Once this happens, the part
will enter sleep mode and only minimal power will be
consumed (see the Electrical Characteristics table).
2. Once the V
threshold is reached, the boost
MID(GOOD)
converter will turn on and regulate its input current
ramping hysteretically between 2.12A and 1.88A. The
buck converter will continue to run at the same time. In
5. Ifthesupercapacitors’selfdischargeoranexternalload
cause the output to drop by more than 135mV (typical),
then the LTC3625/LTC3625-1 will exit sleep mode and
begin charging the appropriate supercapacitor.
some cases (I
~ <1A) the boost converter’s input
BUCK
current will exceed the current delivered to C ; even
BOT
though the buck converter is running, charge will be
In all cases whenever either of the converters is shut
down, it will switch to its appropriate discharge phase
(NMOS on for the buck and PMOS on for the boost) until
removed and V
may decrease. Thus, if V
falls
MID
MID
below the V
hysteresis threshold, the boost
MID(GOOD)
3625f
ꢈ
LTC3625/LTC3625-1
operaTion
converter will turn off. Once V has again risen above
where ε
is the boost converter efficiency which is
MID
BOOST
the V
threshold, the boost converter will be
typically around 85% (see the Typical Performance Char-
MID(GOOD)
re-enabled. In the case where V
< V , the boost
acteristics graph Boost Efficiency vs V ).
OUT
MID
TOP
converter will operate in trickle charge mode until V
OUT
Seen another way this is the maximum steady-state load
the part can support without losing V
exceeds V
(see Boost Converter).
MID
regulation.
OUT
3. During phase 2, if C exceeds its individual maximum
BOT
PGOOD PIN
threshold voltage (2.45V/2.05V typical if V
or 2.7V/2.3V typical if V is high) or if V
is low
SEL
exceeds
SEL
TOP
The PGOOD pin is an open-drain output used to indicate
thatV hasapproacheditsfinalregulationvalue.PGOOD
V
BOT
by more than 50mV (typical), then the appropri-
OUT
ate converter will turn off until the capacitor has fallen
remains active low until V
reaches 92.5% of its regula-
OUT
below its hysteresis threshold (2.40V/2V typical if V
SEL
tion value at which point it will become high impedance.
If V falls below 89.5% of its regulation voltage after
is low and 2.65V/2.25V typical if V
is high for the
– 50mV typical for the
SEL
OUT
buck converter or V
boost converter).
< V
TOP
MID
PGOOD has been asserted, PGOOD will once again pull
active low. PGOOD is an open-drain output and requires
a pull-up resistor to the input voltage of the monitoring
microprocessor or another appropriate power source.
PGOOD is pulled active low in shutdown or input UVLO.
4. Once V
has reached its programmed output voltage,
OUT
the part will enter sleep mode, and only minimal power
will be consumed (see the Electrical Characteristics
table).
Power-Fail Input Comparator
5. Ifthesupercapacitors’selfdischargeoranexternalload
cause the output to drop by more than 135mV (typical),
then the LTC3625/LTC3625-1 will exit sleep mode and
begin recharging the supercapacitor stack.
The PFI/PFO pins provide an input failure notification to
the user. The PFI pin is a high impedance input pin that
should be tied to a resistive divider from V . PFO is an
IN
open-drain output and requires a pull-up resistor to the
inputvoltageofthemonitoringmicroprocessororanother
appropriate power source. When PFI is above 1.2V, PFO is
high impedance and will be pulled up through the external
resistor. If PFI drops below 1.2V, PFO will be pulled low
indicating a power failure. This allows the user to program
anydesiredinputpowerfailureindicationthreshold.There
is 15mV of hysteresis on the PFI pin. If this functionality
In all cases, whenever either of the converters is shut
down, it will switch to its appropriate discharge phase
(NMOS on for the buck and PMOS on for the boost) until
the inductor current reaches 0mA. This optimizes charge
delivery to the output capacitors.
Charge time is dependent on the programmed buck out-
put current as well as the value of supercapacitors being
charged.Forestimatingchargeprofilesinthedualinductor
application, see the Typical Performance Characteristics
is not desired the PFI pin should be tied to V . PFO is
IN
pulled active low in shutdown or input UVLO
graph Charge Time vs R
.
PROG
Shutdown Operation
The effective average V
referred charge current, while
OUT
When the EN pin is pulled low the LTC3625/LTC3625-1 are
put into shutdown. In this case, all of the active circuitry is
powered down and there will be less than 1µA of leakage
both converters are continuously active, can be approxi-
mated as:
VMID
current from both V and V . This allows the input to
IN
OUT
ICHARGE ≅ 0.5•IBUCK –1A • 1–2•εBOOST
•
be present or absent as well as the capacitor stacks to be
V
OUT
fully charged or discharged in shutdown without leakage
between V , V
and GND.
And, while both supercapacitors are in balance and V
IN OUT
MID
is above the V
threshold as:
MID(GOOD)
I
≅ 0.5 • I
• ε
CHARGE
BUCK BOOST
3625f
ꢀ0
LTC3625/LTC3625-1
applicaTions inForMaTion
Programming Charge Current/Maximum Input Current
V Capacitor Selection
IN
The C
charge current is programmed with a single
The style and value of capacitors used with the LTC3625/
LTC3625-1 determine input voltage ripple. Because the
LTC3625/LTC3625-1useastep-downswitchingpowersup-
BOT
resistor connecting the PROG pin to ground. The program
resistor and buck output current are calculated using the
following equation:
ply from V to V , its input current waveform contains
IN
MID
high frequency components. It is strongly recommended
1.2V
that a low equivalent series resistance (ESR) multilayer
RPROG =hPROG
•
IBUCK
ceramic capacitor be used to bypass V .
IN
Tantalum and aluminum capacitors are not recommended
because of their high ESR. The value of the capacitor on
whereh
BUCK
current. An R
=118,000(typical). Excludingquiescentcur-
PROG
rent, I
is always greater than the average buck input
V directly controls the amount of input ripple for a given
resistor value of less than 53.6k will
IN
PROG
I
. Increasing the size of this capacitor will reduce the
causetheLTC3625/LTC3625-1toenterovercurrentprotec-
tion mode and proceed to charge at 2.65A (typical).
BUCK
input ripple.
Multilayer ceramic chip capacitors typically have excep-
tional ESR performance. MLCCs combined with a tight
board layout and an unbroken ground plane will yield
very good performance and low EMI emissions. There are
several types of ceramic capacitors available, each having
considerably different characteristics. For example, X7R
ceramic capacitors have the best voltage and temperature
stability. X5R ceramic capacitors have higher packing
density but poorer performance over their rated voltage
and temperature ranges. Y5V ceramic capacitors have
the highest packing density, but must be used with cau-
tion because of their extreme non-linear characteristic of
capacitance verse voltage.
The effective buck input current can be calculated as:
IBUCK
εBUCK
VMID
IVIN
=
•
V
IN
where ε
is the buck converter efficiency (see the
BUCK
TypicalPerformanceCharacteristicsgraphBuckEfficiency
vs V ).
MID
Output Voltage Programming
The LTC3625/LTC3625-1 have a V
input pin that
SEL
allows the user to set the output threshold voltage to
either 4.8V/4.0V or 5.3V/4.5V by forcing a low or high at
theV pinrespectively. Inthesingleinductorapplication
SEL
The actual in-circuit capacitance of a ceramic capacitor
should be measured with a small AC signal as is expected
in-circuit. Many vendors specify the capacitance versus
the chip will balance the supercapacitors to within 50mV
(typical) of each other, resulting in a possible 25mV of
over/undercharge per cell. In the dual inductor application
the chip will balance the supercapacitors to within 100mV
(typical) of each other, resulting in a possible 50mV of
over/undercharge per cell.
voltage with a 1V
AC test signal and as a result,
RMS
overstate the capacitance that the capacitor will present
in the application. Using similar operating conditions as
the application, the user must measure or request from
the vendor the actual capacitance to determine if the
selected capacitor meets the minimum capacitance that
the application requires.
Thermal Management
Ifthejunctiontemperatureincreasesaboveapproximately
150°C, the thermal shutdown circuitry automatically de-
activates the output. To reduce the maximum junction
temperature, a good thermal connection to the PC board
is recommended. Connecting the exposed pad (Pin 13) of
theDFNpackagetoagroundplaneunderthedeviceontwo
layers of the PC board, will reduce the thermal resistance
of the package and PC board considerably.
Inductor Selection
Many different sizes and shapes of inductors are avail-
able from numerous manufacturers. Choosing the right
inductor from such a large selection of devices can be
overwhelming, but following a few basic guidelines will
make the selection process much simpler.
3625f
ꢀꢀ
LTC3625/LTC3625-1
applicaTions inForMaTion
The buck and boost converters are designed to work with
inductors over a wide range of inductances. Choosing a
higher valued inductor will decrease operating frequen-
cies, while a lower valued inductor will increase frequency
but also increase peak current overshoot/undershoot. For
most applications a 3.3µH inductor is recommended. To
maximize efficiency, choose an inductor with a low DC
resistance. Choose an inductor with a DC current rating
good compromise in current rating, DCR and physical
size. Consult each manufacturer for detailed information
on their entire selection of inductors.
Supercapacitor Selection
The LTC3625/LTC3625-1 are designed to charge super-
capacitors of values greater than 0.1F per cell. In general,
lower capacitance cells have higher ESRs, therefore lower
charge currents should be used to help reduce sleep
modulation towards the end of a charge cycle. In general,
the ESR of a supercapacitor cell should not exceed:
at least as large as the maximum I
the application will
PEAK
see according to the specifications table to ensure that the
inductor does not saturate during normal operation. If the
single inductor application is used, make sure to size the
inductor for the higher of buck or boost peak currents.
100mV
ESR≤
IBUCK
Differentcorematerialsandshapeswillchangethesize/cur-
rent and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or Permalloy materials
are small and do not radiate much energy, but generally
cost more than powdered iron core inductors with similar
electrical characteristics. Inductors that are very thin or
have a very small volume typically have much higher core
and DCR losses, and will not give the best efficiency. The
choice of which style inductor to use often depends more
on the price versus size, performance and any radiated
EMI requirements than on what the LTC3625/LTC3625-1
family requires to operate.
where 100mV is the sleep threshold hysteresis. Higher
capacitance cells typically have lower ESRs and can
therefore be charged with higher currents. Typically, the
LTC3625/LTC3625-1 are designed to charge supercapaci-
tors with values up to 100F, but higher capacitance cells
could be used at the expense of greater charge time.
Table 3 shows several supercapacitors that work well with
the LTC3625/LTC3625-1.
Printed Circuit Board Layout Considerations
In order to be able to deliver maximum current under all
conditions,itiscriticalthattheexposedpadonthebackside
of the LTC3625/LTC3625-1 package be soldered to the PC
Table 2 shows several inductors that work well with the
LTC3625/LTC3625-1 regulators. These inductors offer a
Table 2. Inductor Manufacturers
MANUFACTURER
Coiltronics
Coilcraft
PART NUMBER
DR73-3R3-R
INDUCTANCE (µH)
CURRENT (A)
DCR (mΩ)
SIZE (mm)
7 × 7
3.3
3.3
3.3
3.0
3.0
3.0
3.2
6.5
3.0
3.3
20
20
26
24
30
MSS7341-332NL
IHLM2525CZER3R3M11
CDRH6D28P-3RON
B1077AS-3RON
7 × 7
Vishay
6.5 × 6.9
7 × 7
Sumida
TOKO
7.6 × 7.6
Table 3. Supercapacitor Manufacturers
MANUFACTURER
Cooper Bussmann
Illinois Capacitor
NESS Capacitor
Tecate
PART NUMBER
B1860-2R5107-R
107DCN2R7M
VALUE (F)
100
OPERATING VOLTAGE (V) MAXIMUM ESR (mΩ)
SIZE (mm)
18 × 60
22 × 45
22 × 45
22 × 45
26 × 51
2.5
2.7
2.7
2.7
2.5
20
10
9
100
ESHSR-0100C0002R7
TPLS-100//22 X 45F
BCAP120P250
100
100
9
Maxwell
120
2.5
3625f
ꢀꢁ
LTC3625/LTC3625-1
applicaTions inForMaTion
board ground. Failure to make thermal contact between
the exposed pad on the backside of the package and the
copper board will result in higher thermal resistances.
resistance can be kelvined out by a dedicated voltage
sense trace from the V
pin to a point halfway between
MID
the bottom plate of C
and the top plate of C . In the
TOP
BOT
case of C , however, it is even more critical to keep any
TOP
Furthermore, due to its potentially high frequency switch-
ing circuitry, it is imperative that the input capacitor,
inductors, and output bypass capacitors be as close to
the LTC3625/LTC3625-1 as possible, and that there be an
unbroken ground plane under the IC and all of its external
highfrequencycomponents.Highfrequencycurrents,such
resistance in the connection to a minimum. Excessive
series resistance may cause the part to duty cycle in and
out of sleep or prematurely shut down the boost, due to
the voltage seen at the part being equal to V
+ I
•
OUT
OUT
ESR.LikewisetheC supercapacitorshouldbeprovided
BOT
with a low impedance contact to the ground plane with
an unbroken, low impedance, path back to the backside
of the LTC3625/LTC3625-1 package.
as the V and V
currents on the LTC3625/LTC3625-1,
IN
OUT
tendtofindtheirwayalongthegroundplaneinamyriadof
paths ranging from directly back to a mirror path beneath
theincidentpathonthetopoftheboard. Ifthereareslitsor
cuts in the ground plane due to other traces on that layer,
the current will be forced to go around the slits. If high
frequency currents are not allowed to flow back through
their natural least-area path, excessive voltage will build
up and radiated emissions will occur. There should be a
group of vias under the grounded backside of the pack-
age leading directly down to an internal ground plane. To
minimize parasitic inductance, the ground plane should
be on the highest possible layer of the PC board.
When laying out the printed circuit, the following check-
list should be used to ensure proper operation of the
LTC3625/LTC3625-1.
1. Are the bypass capacitors at V and V
as close as
OUT
IN
possible to the LTC3625/LTC3625-1? These capacitors
provide the AC current to the internal power MOSFETs
and their drivers. Minimizing inductance from these
capacitors to the LTC3625/LTC3625-1 is a top priority.
2. AretheC bypasscapacitorandthepowerinductor(s)
BOT
closely connected? The (–) terminal of the C bypass
BOT
Any board resistance between inductor(s) and the posi-
capacitor returns current to the GND plane, and then
tive terminal of C
will add to the capacitors internal
BOT
back to C .
IN
ESR. Likewise, any resistance between the V
pin
OUT
3. Keep sensitive components away from the SW pins.
and the positive terminal of C
will add to its internal
TOP
ESR. Any added resistance to the capacitors will reduce
4. Keep the current carrying traces from V
to C and
OUT
TOP
the effective charging efficiency. In the case of C
this
BOT
the inductors to C
to a minimum.
BOT
Typical applicaTions
450mA Charge Current 1-Inductor Application
V
*
V
IN
OUT
4.0V/4.5V
V
V
OUT
IN
2.7V TO 5.5V
C1
10µF
L1 3.3µH
LTC3625-1
C2 ≥ 0.1F
SW1
SW2
V
IN
V
EN
MID
C3 ≥ 0.1F
CTL
V
IN
V
SEL
PGOOD
PFO
R1
287k
PFI
R2
100k
PROG GND
3625 TA03
R3
71.5k
*25mA MINIMUM LOAD REQUIRED ON V
IN
3625f
ꢀꢂ
LTC3625/LTC3625-1
Typical applicaTions
Solar Powered SCAP Charger with MPPT
D1
CMSH3-40
V
V
OUT
IN
L1 3.3µH
L2 3.3µH
C2
1F
CTL
EN
SW1
SW2
R4
10k
R1
26.7k
LTC3625
C1
10µF
PFI
C3
1F
V
MID
V
SEL
C6
GND
GND
100pF
PROG
R3
D3
SOLAR PANEL
+
C4
6.0V OPEN CIRCUIT
R5
174k
390µF
143k
4.4V MPP
16V
R2
10.0k
4
5
–
+
V
1
LT1784CS5
–
3
V
+
2
C5
10nF
D2
1.2V
3625 TA04
5V Power Ride-Through
Q2
Si4421DY
1.8V
5V
V
V
V
IN1
OUT1
C6
FB1
IN2
100µF
C5
22µF
R5
LTM4616
4.78k
Q1
GND
ITHM1
Si4421DY
V
OUT2
FB2
C7
100µF
C8
100µF
V
V
R6
10k
IN
OUT
L1
3.3µH
C2
CTL
EN
SW1
SW2
ITHM2
GND
R1
LTC3625
100F
C1
10µF
287k
LTC4412
SENSE
C3
100F
3625 TA05
PFI
V
V
IN
MID
R4
470k
R2
100k
V
SEL
GND
GND
GND GATE
CTL STAT
PROG
R3
PFO
143k
3625f
ꢀꢃ
LTC3625/LTC3625-1
Typical applicaTions
12V Power Ride-Through
IDEAL DIODE
DC/DC
V
LTC4355
FDS3672
V
1.8V
GND
12V
IN
OUT
LTM4601A
GND GND
M1
*
FDS3672
IRF7424
LT1737 FLYBACK
4
2
6
V
V
OUT
IN
•
•
•
L1 3.3µH
L2 3.3µH
C1
DC-A
DC-B
DC-C
CTL
EN
SW1
100F
LTC3625
10
7
SW2
GND
UV
DETECTOR
V
MID
C2
100F
V
SEL
11
8
PROG
R1
•
*EXPOSED PAD TO
BE CONNECTED TO A
LT1737
THERMAL PAD ISOLATED
FROM THE SYSTEM GROUND
143k
GND
12
*
V
V
IN
OUT
L3 3.3µH
L4 3.3µH
C3
100F
CTL
EN
SW1
LTC3625
SW2
GND
C4
100F
V
MID
V
SEL
PROG
R2
143k
V
V
IN
OUT
L5 3.3µH
L6 3.3µH
C5
100F
SW1
CTL
EN
LTC3625
SW2
GND
V
C6
100F
MID
V
SEL
PROG
R3
143k
package DescripTion
DE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)
0.40 p 0.10
4.00 p0.10
(2 SIDES)
R = 0.115
TYP
7
12
0.70 p0.05
R = 0.05
TYP
3.30 p0.10
3.30 p0.05
1.70 p 0.05
3.60 p0.05
2.20 p0.05
3.00 p0.10
(2 SIDES)
1.70 p 0.10
PIN 1
TOP MARK
(NOTE 6)
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
PACKAGE
OUTLINE
CHAMFER
(UE12/DE12) DFN 0806 REV D
6
1
0.25 p 0.05
0.75 p0.05
0.200 REF
0.25 p 0.05
2.50 REF
0.50 BSC
0.50 BSC
2.50 REF
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
3. ALL DIMENSIONS ARE IN MILLIMETERS
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3625f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ꢀꢄ
LTC3625/LTC3625-1
Typical applicaTion
Minimum External Component Application (500mA Charge Current)
V
*
V
IN
OUT
4.8V/5.3V
V
V
OUT
IN
2.7V TO 5.5V
C1
L1
10µF
SW1
SW2
C2 ≥ 0.1F
C3 ≥ 0.1F
3.3µH
LTC3625
V
MID
PFI
CTL
EN
V
SEL
NC
NC
PGOOD
PFO
PROG GND
3625 TA02
*25mA MINIMUM LOAD REQUIRED ON V
IN
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LTC3203/LTC3203B/
LTC3203B-1/LTC3203-1
500mA Low Noise High Efficiency Dual Mode
Step-Up Charge Pumps
V : 2.7V to 5.5V, 3mm × 3mm 10-Lead DFN Package
IN
LTC3204/LTC3204B-3.3/
LTC3204-5
Low Noise Regulating Charge Pumps
Micropower Regulated Charge Pump
150mA Supercapacitor Charger
Up to 150mA Output Current (LTC3204-5), Up to 50mA Output Current
(LTC3204-3.3)
LTC3221/LTC3221-3.3/
LTC3221-5
Up to 60mA Output Current
LTC3225/LTC3225-1
Programmable Supercapacitor Charger Designed to Charge Two
Supercapacitors in Series to a Fixed Output Voltage (4.8V/5.3V Selectable)
from a 2.8V/3V to 5.5V Input Supply. Automatic Cell Balancing Prevents
Overvoltage Damage to Either Supercapacitor. No Balancing Resistors are
Required.
LTC3240-3.3/LTC3240-2.5 Step-Up/Step-Down Regulated Charge Pumps
Up to 150mA Output Current
LT®3420/LT3420-1
1.4A/1A Photoflash Capacitor Charger with
Automatic Top-Off
Charges 220µF to 320V in 3.7 Seconds from 5V, V : 2.2V to 16V,
SD
IN
I
< 1µA, 10-Lead MS Package
LT3468/LT3468-1/
LT3468-2
1.4A/1A/0.7A, Photoflash Capacitor Charger
V : 2.5V to 16V, Charge Time = 4.6 Seconds for the LT3468 (0V to 320V,
IN
100µF, V = 3.6V), I < 1µA, ThinSOTTM Package
IN
SD
LTC3484-0/LTC3484-1/
LTC3484-2
1.4A/0.7A/1A, Photoflash Capacitor Charger
V : 1.8V to 16V, Charge Time = 4.6 Seconds for the LT3484-0 (0V to 320V,
IN
100µF, V = 3.6V), I < 1µA, 2mm × 3mm 6-Lead DFN Package
IN
SD
LT3485-0/LT3485-1/
LT3485-2/LT3485-3
1.4A/0.7A/1A/2A Photoflash Capacitor Charger V : 1.8V to 10V, Charge Time = 3.7 Seconds for the LT3485-0 (0V to 320V,
IN
with Output Voltage Monitor and Integrated
IGBT
100µF, V = 3.6V), I < 1µA, 3mm × 3mm 10-Lead DFN Driver
IN SD
LT3750
LT3751
LTC4425
Capacitor Charger Controller
Charges Any Size Capacitor, 10-Lead MS Package
Capacitor Controller with Regulation
Charges Any Size Capacitor, 4mm × 5mm QFN-20 Package
Supercapacitor Charger with Current-Limited
Ideal Diode
CC/CV Linear Charger for 2-Cell Supercapacitor Stack from a Li-Ion/
Polymer Battery, USB Port or a 2.7V to 5.5V Current-Limited Supply,
3mm × 3mm DFN-12 and MSOP-12E Packages
3625f
LT 0710 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
ꢀꢅ
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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