LTC3634EFE#TRPBF_技术文档

LTC3634

15V Dual 3A Monolithic

Step-Down Regulator

for DDR Power

FEATURES

DESCRIPTION

n

3.6V to 15V Input Voltage Range

TheLTC^®3634isahighefficiency,dual-channelmonolithic

synchronous step-down regulator which provides power

supply and bus termination rails for DDR1, DDR2, and

DDR3 SDRAM controllers. The operating input voltage

range is 3.6V to 15V, making it suitable for point-of-load

power supply applications from a 5V or 12V input, as well

as various battery powered systems.

n

3A Output Current per Channel

n

Up to 95% Efficiency

n

Selectable 90°/180° Phase Shift Between Channels

n

Adjustable Switching Frequency: 500kHz to 4MHz

n

VTTR = V

/2 = V Reference

DDQ

TT

n

1.6% Accurate VTTR at 0.75V

Optimal V Range: 0.6V to 3V

OUT

The V regulated output voltage is equal to VDDQIN•0.5.

TT

10mA Buffered Output Supplies V Reference Voltage

REF

An on-chip buffer capable of driving a 10mA load pro-

vides a low noise reference output (VTTR) also equal to

VDDQIN•0.5.

Current Mode Operation for Excellent Line and Load

Transient Response

n

External Clock Synchronization

The operating frequency is programmable and synchro-

nizable from 500kHz to 4MHz with an external resistor.

The two channels can operate 180° out-of-phase, which

relaxestherequirementsforinputandoutputcapacitance.

The unique controlled on-time architecture is ideal for

powering DDR applications from a 12V supply at high

switchingfrequencies,allowingtheuseofsmallerexternal

components.

Short-Circuit Protected

Input Overvoltage and Overtemperature Protection

Power Good Status Outputs

Available in (4mm × 5mm) QFN-28 and Thermally

Enhanced 28-Lead TSSOP Packages

APPLICATIONS

n

DDR Memory Power Supplies

The LTC3634 is offered in both 28-pin 4mm × 5mm QFN

and 28-pin exposed pad TSSOP packages.

L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and PolyPhase are registered

trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks

are the property of their respective owners. Protected by U.S. Patents including 5481178,

5847554, 6580258, 6476589, 6774611.

TYPICAL APPLICATION

V

IN

Efficiency and Power Loss

vs Load Current

3.6V TO 15V

47µF

V

IN1

IN2

×2

100

90

80

70

60

50

40

30

20

10

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

RUN1

RUN2

BOOST1

SW1

V

= 12V

IN

0.1µF

1.5µH

V

DDQ

LTC3634

INTV

CC

1.8V/3A

PHMODE

MODE/SYNC

V

ON1

2.2µF

100µF

×2

VDDQIN

24.3k

12.1k

0.82µH

V

DDQ

V

FB1

(SINKING CURRENT)

TT

RT

ITH1

(SOURCING CURRENT)

BOOST2

324k

26.4k

560pF

V

TT

SW2

0.9V/ 3A

V

FB2

100µF

×4

V

ON2

V

REF

ITH2

VTTR

0.9V

0.01µF

SGND PGND

18k

910pF

2

3

0

0.5

1

1.5

2.5

3634 TA01a

LOAD CURRENT (A)

3634 TA01b

3634fc

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For more information www.linear.com/LTC3034

LTC3634

(Note 1)

ABSOLUTE MAXIMUM RATINGS

V

, V ................................................... –0.3V to 16V

IN1 IN2

SW Source and Sink Current (DC) (Note 3) ................3A

Operating Junction Temperature Range (Notes 4, 5, 8)

LTC3634E, LTC3634I......................... –40°C to 125°C

LTC3634H.......................................... –40°C to 150°C

LTC3634MP....................................... –55°C to 150°C

Storage Temperature Range ..................–65°C to 150°C

Lead Temperature

IN1 IN2

, V Transient (Note 2)......................................18V

PGOOD1, PGOOD2, V , V ................. –0.3V to 16V

ON1 ON2

VTTR, INTV , TRACKSS, VDDQIN .......... –0.3V to 3.6V

ITH1, ITH2, RT, MODE/SYNC.....–0.3V to INTV + 0.3V

CC

V

, V , PHMODE..................–0.3V to INTV + 0.3V

FB1 FB2

CC

BOOST1-SW1, BOOST2-SW2.................... –0.3V to 3.6V

BOOST1, BOOST2....................................–0.3V to 19.6V

(Soldering, 10 sec, TSSOP Package).....................260°C

RUN1, RUN2 .................................... –0.3V to V + 0.3V

IN

PIN CONFIGURATION

TOP VIEW

1

2

V

ON1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ITH1

SW1

TRACKSS

3

V

FB1

28 27 26 25 24 23

4

V

PGOOD1

PHMODE

RUN1

IN1

PGOOD1

PHMODE

RUN1

1

2

3

4

5

6

7

8

22

21

20

19

18

17

16

15

V

IN1

5

V

IN1

6

BOOST1

7

INTV

CC

MODE/SYNC

RT

29

PGND

MODE/SYNC

RT

INTV

CC

29

PGND

8

VTTR

9

BOOST2

RUN2

BOOST2

10

11

12

13

14

V

SGND

IN2

SGND

V

IN2

V

PGOOD2

IN2

9

10 11 12 13 14

UFD PACKAGE

SW2

V

FB2

VDDQIN

ITH2

V

ON2

FE PACKAGE

28-LEAD (4mm × 5mm) PLASTIC QFN

28-LEAD PLASTIC TSSOP

T

= 150°C, θ = 43°C/W

JMAX

JA

T

= 150°C, θ = 25°C/W

JA

EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB

JMAX

EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB

3634fc

2

For more information www.linear.com/LTC3034

LTC3634

ORDER INFORMATION

LEAD FREE FINISH

LTC3634EUFD#PBF

LTC3634IUFD#PBF

LTC3634HUFD#PBF

LTC3634MPUFD#PBF

LTC3634EFE#PBF

LTC3634IFE#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

LTC3634EUFD#TRPBF

LTC3634IUFD#TRPBF

LTC3634HUFD#TRPBF

3634

28-Lead (5mm × 4mm) Plastic QFN

28-Lead Plastic TSSOP

LTC3634MPUFD#TRPBF 3634

LTC3634EFE#TRPBF

LTC3634IFE#TRPBF

LTC3634HFE#TRPBF

LTC3634MPFE#TRPBF

LTC3634FE

28-Lead Plastic TSSOP

LTC3634HFE#PBF

LTC3634MPFE#PBF

28-Lead Plastic TSSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified junction

temperature range, otherwise specifications are at T_A= 25°C (Note 4). V_IN= 12V, INTV_CC= 3.3V, unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

, Operating Supply Range

3.6

1.4

15

V

IN

IN1

IN2

V

> 3.6V

IN1

ON

Output Voltage Range

= V

(Note 6)

0.6

3

V

OUT

I

Input DC Supply Current (V + V

)

IN2

Q

IN1

Active (Note 7)

Shutdown

RUN1 = RUN2 = V

1.3

15

mA

µA

IN

RUN1 = RUN2 = 0V

V

Feedback Reference Voltage

3.6V < V < 15V, 0.5V < ITH < 1.8V

FBREG1

FBREG2

IN

l

0°C < T < 85°C

0.594

0.592

0.6

0.606

V

A

–55°C < T < 150°C

A

l

V

Feedback Reference Voltage

VTTR Voltage Reference

3.6V < V < 15V, 0.5V < ITH < 1.8V

VTTR – 6

0.492 •

VDDQIN VDDQIN VDDQIN

VTTR

VTTR + 6

0.508 •

mV

V

IN

VTTR

1.5V < VDDQIN < 2.6V

0.50 •

I

=

10mA, C

< 10nF

LOAD

I

Feedback Pin Input Current

Error Amplifier Transconductance

Minimum On-Time

30

nA

mS

ns

FB

g

ITH = 1.2V

1.0

20

m(EA)

ON(MIN)

OFF(MIN)

OSC

t

f

V

= 0.5V, V = 4V

IN

ON

IN

Minimum Off-Time

= 6V

40

60

ns

Oscillator Frequency

= INTV

R = 162k

1.4

1.7

3.4

2

4

2.6

2.3

4.6

MHz

RT

T

CC

R = 80.6k

T

I

Channel 1 Valley Switch Current Limit

Positive Limit

LIM1

LIM2

3.3

4.4

8

5.5

A

Negative Limit

Channel 2 Valley Switch Current Limit

Positive Limit

Negative Limit

4.4

8

A

R

DS(ON)

Channel 1

Top Switch On-Resistance

Bottom Switch On-Resistance

Channel 2

130

65

mΩ

Top Switch On-Resistance

Bottom Switch On-Resistance

130

65

mΩ

3634fc

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For more information www.linear.com/LTC3034

LTC3634

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

temperature range, otherwise specifications are at T_A= 25°C (Note 4). V_IN= 12V, INTV_CC= 3.3V, unless otherwise noted.

SYMBOL PARAMETER

Switch Leakage Current

Overvoltage Lockout Threshold

CONDITIONS

MIN

TYP

MAX

UNITS

V

IN

= 15V, V

= 0V

RUN

0.01

1

µA

V

IN

V

IN

Rising

Falling

16.8

15.8

17.5

16.5

18

17

V

IN

INTV Voltage

3.6V < V < 15V, 0mA Load

3.1

3.3

0.7

3.5

V

CC

IN

INTV Load Regulation

0mA to 50mA Load, V = 4V to 15V

%

CC

IN

l

RUN Threshold Rising

RUN Threshold Falling

1.18

0.98

1.22

1.01

1.26

1.04

V

RUN Leakage Current

0

1

µA

PGOOD Good-to-Bad Threshold

V

FB

V

FB

Rising

Falling

8

–8

10

–10

%

PGOOD Hysteresis

V

from Bad-to-Good

15

mV

Ω

FB

R

PGOOD Pull-Down Resistance

Power Good Filter Time

10mA Load

PGOOD

20

0.7

40

µs

t

Channel 1 Internal Soft-Start Ramp Rate

Channel 2 Internal Soft-Start Ramp Rate

1.2

2.2

0.3

1.4

V/ms

V

SS1

1.5

SS2

V

FB1

During Tracking

TRACKSS = 0.3V

PHMODE = 0V

0.28

0.315

I

TRACKSS Pull-Up Current

µA

TRACKSS

Phase Shift Between Channel 1 and

Channel 2

90

180

deg

PHMODE = INTV

CC

PHMODE Threshold Voltage

V

1

V

IH

IL

0.3

0.4

MODE/SYNC Threshold Voltage

V

IH

V

IL

V

SYNC Threshold Voltage

MODE/SYNC Input Current

V

0.95

V

IH

MODE = 0V

MODE = INTV

1.5

–1.5

µA

CC

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

these specifications is determined by specific operating conditions in

conjunction with board layout, the rated package thermal impedance and

other environmental factors.

Note 5: The junction temperature (T , in °C) is calculated from the ambient

J

Note 2: Transient event duration must be < 1% of total lifetime of the part.

Note 3: Guaranteed by long term current density limitations.

Note 4: The LTC3634 is tested under pulsed load conditions such that

temperature (T , in °C), package thermal impedance (θ , in °C/W), and

A

J

A

power dissipation (P , in Watts) according to the formula: T = T + P • θ .

JA

D

J

A

D

Note 6: Output voltage settings above 3V are not optimized for controlled

on-time operation. For designs that set output voltages above 3V, please

refer to the Applications Information section for information on device

operation outside the optimized range.

Note 7: Dynamic supply current is higher due to the internal gate charge

being delivered at the switching frequency.

Note 8: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

T ≈ T . The LTC3634E is guaranteed to meet specified performance

J

A

from 0°C to 85°C junction temperature. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3634I is guaranteed to meet specifications over the –40°C to 125°C

operating junction temperature range. The LTC3634H is guaranteed

over the –40°C to 150°C operating junction temperature range and the

LTC3634MP is tested and guaranteed over the –55°C to 150°C operating

junction temperature range. High junction temperatures degrade operating

lifetimes; operating lifetime is derated for junction temperatures greater

than 125°C. Note that the maximum ambient temperature consistent with

3634fc

4

For more information www.linear.com/LTC3034

LTC3634

T_A= 25°C, V_IN= 12V, f_SW= 1MHz, L = 1.5μH unless

TYPICAL PERFORMANCE CHARACTERISTICS

otherwise noted.

Efficiency vs Load Current

(Burst Mode Operation)

Efficiency vs Load Current

(Forced Continuous)

Efficiency vs Load Current

(Forced Continuous)

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V

OUT

= 1.8V

V

OUT

= 1.8V

V

OUT

= 1.5V

90

80

70

60

50

40

30

20

10

0

V

IN

V

IN

V

IN

V

IN

= 4V

= 8V

= 12V

= 15V

V

IN

V

IN

V

IN

V

IN

= 4V

= 8V

= 12V

= 15V

V

IN

V

IN

V

IN

V

IN

= 4V

= 8V

= 12V

= 15V

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

LOAD CURRENT (A)

3634 G01

3634 G02

3634 G03

V_TTPower Loss vs Load Current,

Sourcing and Sinking

Efficiency vs Input Voltage

V_TTPower Loss vs Load Current

1.2

1.0

0.8

0.6

0.4

0.2

0

95

90

85

80

75

70

65

60

1.2

1.0

0.8

0.6

0.4

0.2

0

V

IN

V

IN

V

IN

= 12V

= 8V

= 4V

V

= 0.75V

V

IN

V

IN

V

IN

V

IN

= 15V

= 12V

= 8V

V

= 0.9V

TT

L = 0.82µH

= 4V

I

= 10mA

= 100mA

= 1A

OUT

= 3A

–3

–2

–1

0

1

2

3

4

6

8

10

12

14

16

–3

–2

–1

0

1

2

3

OUTPUT CURRENT (A)

INPUT VOLTAGE (V)

OUTPUT CURRENT (A)

3634 G04

3634 G05

3634 G06

Reference Voltage

vs Temperature

Oscillator Frequency

vs Temperature

Oscillator Internal Set Frequency

vs Temperature

0.605

0.603

0.601

0.599

0.597

0.595

10

8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

6

4

2

0

–2

–4

–6

–8

–10

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3634 G07

3634 G08

3634 G09

3634fc

5

For more information www.linear.com/LTC3034

LTC3634

T_A= 25°C, V_IN= 12V, f_SW= 1MHz, L = 1.5μH unless

Switch Leakage vs Temperature

TYPICAL PERFORMANCE CHARACTERISTICS

otherwise noted.

R_DS(ON)vs Temperature

Shutdown Current vs V_IN

180

160

140

120

100

80

20

18

16

14

12

10

8

20000

MAIN SWITCH

SYNCHRONOUS SWITCH

TOP SWITCH

16000

12000

8000

4000

0

BOTTOM SWITCH

60

6

40

4

20

2

0

4

6

8

10

(V)

12

14

16

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

0

25 50 75 100

TEMPERATURE (°C)

125 150

V

IN

3634 G11

3634 G10

3634 G12

Valley Current Positive Limit

vs Temperature

Valley Current Negative Limit

vs Temperature

TRACKSS Pull-Up Current

vs Temperature

–4

–5

2.0

1.8

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

–6

1.6

1.4

1.2

1.0

0.8

–7

–8

–9

–10

0.6

–11

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3634 G15

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3634 G14

3634 G13

3634fc

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For more information www.linear.com/LTC3034

LTC3634

T_A= 25°C, V_IN= 12V, f_SW= 1MHz, L = 1.5μH unless

TYPICAL PERFORMANCE CHARACTERISTICS

otherwise noted.

Load Regulation

VTTR Load Regulation

V_DDQLoad Step

0.2

0.1

0.3

0.2

VDDQ

TT

V

OUT

100mV/DIV

AC-COUPLED

0.1

0

–0.1

–0.2

–0.3

I

L

–0.1

2A/DIV

–0.2

3634 G18

–4

6

10

20µs/DIV

0

2

3

–10 –8 –6

–2

0

2

4

8

–3

–2

–1

1

V

LOAD

= 1.8V

= 0A TO 3A

OUT

VTTR LOAD CURRENT (mA)

LOAD CURRENT (A)

I

3634 G17

3634 G16

V

_TTLoad Step

Start-Up

Start-Up (Channel 2)

RUN2

5V/DIV

V

RUN1 = RUN2

5V/DIV

OUT

100mV/DIV

AC-COUPLED

V

DDQ

V

DDQ

V

TT

DDQ

TT

V

DDQ

TT

V

1V/DIV

I

L

2A/DIV

VTTR

1V/DIV

VTTR

1V/DIV

3634 G19

3634 G20

3634 G21

20µs/DIV

200µs/DIV

RUN1 = 5V

V

LOAD

= 0.9V

= –2A TO 2A

OUT

I

3634fc

7

For more information www.linear.com/LTC3034

LTC3634

PIN FUNCTIONS ^(QFN/TSSOP)

PGOOD1(Pin1/Pin4):Channel1Open-DrainPowerGood

PGOOD2 (Pin 8/Pin 11): Channel 2 Open-Drain Power

Output Pin. PGOOD1 is pulled to ground when the voltage

Good Output Pin. PGOOD2 is pulled to ground when

on the V pin is not within 8% (typical) of the internal

the voltage on the V pin is not within 8% (typical) of

FB1

FB2

0.6V reference. This threshold has 15mV of hysteresis.

VDDQIN • 0.5. This threshold has 15mV of hysteresis.

PHMODE (Pin 2/Pin 5): Phase Select Input. Tie this pin to

V

(Pin 9/Pin 12): Channel 2 Output Feedback Voltage

FB2

ground to forceboth channels to switch 90° out-of-phase.

Pin.Inputtotheerroramplifierthatcomparesthefeedback

voltage to VTTR. Connect this pin directly to the output in

Tie this pin to INTV to force both channels to switch

CC

180° out-of-phase. Do not float this pin.

order to set V

equal to VTTR.

OUT2

RUN1 (Pin 3/Pin 6): Channel 1 Regulator Enable Pin.

Enables channel 1 operation by tying RUN1 above 1.22V.

Tying it below 1V places Channel 1 into shutdown. Do not

float this pin.

VDDQIN (Pin 10/Pin 13): External Reference Input for

Channel 2. An internal resistor divider sets the VTTR pin

voltage to be equal to half the voltage applied to this input.

Channel 2 uses the VTTR pin voltage as its error amplifier

reference.

MODE/SYNC (Pin 4/Pin 7): Channel 1 Mode Select and

External Synchronization Input. Tie this pin to ground to

force continuous synchronous operation on Channel 1.

ITH2 (Pin 11/Pin 14): Channel 2 Error Amplifier Output

and Switching Regulator Compensation Pin. Connect this

pintoappropriateexternalcomponentstocompensatethe

regulator loop frequency response. See the Applications

Informationsectionforguidelinesoncomponentselection.

Floating this pin or tying it to INTV enables high

CC

efficiency Burst Mode^®operation at light loads. Channel 2

operation is forced continuous regardless of the state of

this pin. Drive this pin with a clock to synchronize the

LTC3634 switching frequency. An internal phase-locked

loopwillforcethebottompowerNMOS’sturn-onsignalto

be synchronized with the rising edge of the CLKIN signal.

When this pin is driven with a clock, forced continuous

mode is automatically selected.

V

(Pin 12/Pin 15): On-Time Voltage Input for Chan-

ON2

nel 2. This pin sets the voltage trip point for the on-time

comparator. Tying this pin to the output voltage makes the

on-time proportional to V

OUT2

the set frequency (see the Applications Information sec-

tion). The pin impedance is nominally 150kΩ.

when V

< 3V. When

OUT2

V

> 3V, switching frequency may become higher than

RT (Pin 5/Pin 8): Oscillator Frequency Program Pin.

Connect an external resistor (between 80k to 640k) from

this pin to SGND in order to program the frequency from

SW2 (Pins 13, 14/Pins 16, 17): Channel 2 Switch Node

Connection to External Inductor. Voltage swing of SW is

from a diode voltage below ground to a diode voltage

500kHz to 4MHz. When RT is tied to INTV , the switch-

CC

ing frequency will default to 2MHz. See the Applications

above V

.

IN2

Information section.

V

(Pins 15, 16/Pins 18, 19): Power Supply Input for

IN2

RUN2 (Pin 6/Pin 9): Channel 2 Regulator Enable Pin.

Enables channel 2 operation by tying RUN2 above 1.22V.

Tying it below 1V places Channel 2 into shutdown. Do not

float this pin.

Channel 2. Input voltage to the on-chip power MOSFETs

on channel 2. This input is capable of operating from a

supply voltage separate from V

.

IN1

BOOST2 (Pin 17/Pin 20): Boosted Floating Driver Supply

for Channel 2. The (+) terminal of the bootstrap capacitor

connects to this pin while the (–) terminal connects to

the SW pin. The normal operation voltage swing of this

SGND (Pin 7/Pin 10): Signal Ground Pin. This pin should

have a low noise connection to reference ground. The

feedbackresistornetwork,externalcompensationnetwork,

and R resistor should be connected to this ground.

T

pin ranges from a diode voltage drop below INTV up

CC

to V + INTV .

IN2

CC

3634fc

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LTC3634

PIN FUNCTIONS ^(QFN/TSSOP)

VTTR (Pin 18/Pin 21): Reference Output. This output is

higher than the set frequency (see the Applications Infor-

mation section). The pin impedance is nominally 150kΩ.

used to supply the V voltage for DDR memory. An on-

REF

chip buffer amplifier outputs a low noise reference voltage

equal to VDDQIN/2. This output is capable of supplying

10mA. The buffer output can drive capacitive loads up to

0.01µF. Asmallseriesresistance(1Ω)betweentheoutput

and the load further increases the amount of capacitance

that the amplifier can drive. The error amplifier for channel

2 uses this voltage as its reference voltage.

ITH1 (Pin 26/Pin 1): Channel 1 Error Amplifier Output and

Switching Regulator Compensation Pin. Connect this pin

to appropriate external components to compensate the

regulator loop frequency response. See the Applications

Informationsectionforguidelinesoncomponentselection.

TRACKSS (Pin 27/Pin 2): Output Tracking and Soft-Start

Input Pin for Channel 1. Forcing a voltage below 0.6V on

this pin bypasses the internal reference input to the error

amplifier. The LTC3634 will servo the FB pin to the TRACK

voltage. Above 0.6V, the tracking function stops and the

internal reference resumes control of the error amplifier.

INTV (Pin 19/Pin 22): Internal 3.3V Regulator Output.

CC

The internal gate drivers and control circuits are powered

from this voltage. Decouple this pin to power ground with

a minimum of 1μF low ESR ceramic capacitor. The internal

regulator is disabled when both Channel 1 and Channel 2

are disabled with the RUN1/RUN2 inputs.

An internal 1.4μA pull-up current from INTV allows a

CC

soft-start function to be implemented by connecting a

BOOST1 (Pin 20/Pin 23): Boosted Floating Driver Supply

for Channel 1. The (+) terminal of the bootstrap capacitor

connects to this pin while the (–) terminal connects to

the SW pin. The normal operation voltage swing of this

capacitor between this pin and SGND.

V

(Pin 28/Pin 3): Channel 1 Output Feedback Voltage

FB1

Pin.Inputtotheerroramplifierthatcomparesthefeedback

voltagetotheinternal0.6Vreferencevoltage. Connectthis

pin to a resistor divider network to program the desired

pin ranges from a diode voltage drop below INTV up

CC

to V + INTV .

IN1

CC

output voltage. Connecting this pin to INTV configures

CC

V

(Pins 21, 22/Pins 24, 25): Power Supply Input for

the LTC3634 for 2-phase, single output operation; see

IN1

Channel 1. Input voltage to the on-chip power MOSFETs

the Applications Information section for full discussion.

on channel 1. The internal LDO for INTV is powered

from this pin.

CC

PGND (Exposed Pad Pin 29/Exposed Pad Pin 29): Power

GroundPin. The(–)terminaloftheinputbypasscapacitor,

SW1 (Pins 23, 24/Pins 26, 27): Channel 1 Switch Node

Connection to External Inductor. Voltage swing of SW is

from a diode voltage drop below ground to a diode volt-

, and the (–) terminal of the output capacitor, C

,

C

IN

OUT

should be tied to this pin with a low impedance connec-

tion. This pin must be soldered to the PCB to provide a

low impedance electrical contact to power ground and

good thermal contact to the PCB.

age above V

.

IN1

V

(Pin 25/Pin 28): On-Time Voltage Input for Chan-

ON1

nel 1. This pin sets the voltage trip point for the on-time

comparator. Tying this pin to the regulated output voltage

makes the on-time proportional to V

3V. When V

when V

<

OUT1

> 3V, switching frequency may become

OUT1

3634fc

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For more information www.linear.com/LTC3034

LTC3634

BLOCK DIAGRAM

C

IN

V

RUN

1.22V

V

CHANNEL 1

ON

IN

+

–

A

V

= 1

150k

RUN

INTV

CC

V

I

IN

3V

I

ON

V

I

ON

VON

t

ON

=

OSC1

R

S

BOOST

CONTROLLER

ON

Q

SWITCH

LOGIC

AND

TG

C

BOOST

M1

M2

SW

L1

ANTI-

SHOOT

THROUGH

I

REV

CMP

BG

C

OUT

PGND

+

–

+

SENSE

R2

R1

V

FB1

IDEAL DIODES

ITH1

0.6V

REF

+

–

EA

–

R

C1

0.648V

C

C1

OV

PGOOD1

INTERNAL

SOFT-START

+

INTV

CC

–

+

TRACKSS

0.552V

–

+

FC BURST

1.4µA

MODE

SELECT

TRACKSS

UV

C

SS

OSC1

OSC

0.48V AT START-UP

0.10V AFTER START-UP

RT

MODE/SYNC

VDDQIN

OSC

PLL-SYNC

R

RT

PHMODE

PHASE

SELECT

INTV

CC

–

VDDQIN • 0.54

3.3V

REG

PV

IN1

C

VCC

OV

UV

OSC2

PGOOD2

+

VDDQIN • 0.5

–

+

VTTR

–

+

IDEAL DIODES

VDDQIN • 0.46

INTERNAL

+

–

SOFT-START

ITH2

EA

V

FB2

R

C2

C

C2

CHANNEL 2 (SAME AS CHANNEL 1)

3634 BD

3634fc

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For more information www.linear.com/LTC3034

LTC3634

OPERATION

drive. The error amplifier for channel 2 uses this voltage

as its reference voltage.

The LTC3634 is a dual-channel, current mode monolithic

step-down regulator designed to provide high efficiency

power conversion for DDR memory supplies and bus ter-

mination.Itsuniquecontrolledon-timearchitectureallows

extremely low step-down ratios while maintaining a fast,

constant switching frequency. Each channel is enabled by

raising the voltage on the RUN pin above 1.22V nominally.

High Efficiency Burst Mode Operation

At light load currents, the inductor current can drop to zero

and become negative. In Burst Mode operation (available

only on channel 1), a current reversal comparator (I

)

REV

detects the negative inductor current and shuts off the bot-

tom power MOSFET, resulting in discontinuous operation

and increased efficiency. Both power MOSFETs will remain

off until the ITH voltage rises above the zero current level to

initiate another cycle. During this time, the output capacitor

supplies the load current and the part is placed into a low

currentsleepmode. BurstModeoperationisdisabledbyty-

ingtheMODE/SYNCpintoground,whichforcescontinuous

synchronous operation regardless of output load current.

Main Control Loop

In normal operation, the internal top power MOSFET is

turned on for a fixed interval determined by a one-shot

timer (ON signal in the Block Diagram). When the top

powerMOSFETturnsoff, thebottompowerMOSFETturns

on until the current comparator I

trips, thus restarting

CMP

the one-shot timer and initiating the next cycle. Inductor

current is measured by sensing the voltage drop across

the bottom power MOSFET. The voltage on the ITH pin sets

thecomparatorthresholdcorrespondingtoinductorvalley

current. The error amplifier EA adjusts this ITH voltage

Power Good Status Output

The PGOOD open-drain output will be pulled low if the

regulatoroutputexitsa 8%windowaroundtheregulation

point. This threshold has 15mV of hysteresis relative to

by comparing the feedback signal V (derived from the

FB

outputvoltage)toaninternal0.6Vreferencevoltage(chan-

nel 1) or the VTTR voltage (channel 2). If the load current

increases, it causes a drop in the feedback voltage relative

tothereferencevoltage. TheITHvoltagethenrisesuntilthe

average inductor current matches that of the load current.

the V pin. To prevent unwanted PGOOD glitches during

FB

transientsordynamicV changes,theLTC3634PGOOD

OUT

falling edge includes a filter time of approximately 40μs.

For the V output (channel 2), VTTR is the regulation

TT

point. The PGOOD2 pin will always be low when the VTTR

The switching frequency is determined by the value of the

output voltage is less than 300mV.

R resistor, which programs the current for the internal

T

oscillator. An internal phase-locked loop servos the one-

shot timer (ON signal) such that the internal oscillator

edge phase-locks to the SW node edge, thus forcing a

constant switching frequency. This unique controlled

on-time architecture also allows the switching frequency

to be synchronized to an external clock source when it

is applied to the MODE/SYNC pin. Channel 1 defaults to

forced continuous operation once the clock signal is ap-

plied(channel2isalwaysinforcedcontinuousoperation).

V Overvoltage Protection

IN

In order to protect the internal power MOSFET devices

against long transient voltage events, the LTC3634 con-

stantly monitors each V pin for an overvoltage condi-

IN

tion. When V rises above 17.5V, the regulator suspends

IN

operation by shutting off both power MOSFETs on the

corresponding channel. Once V drops below 16.5V, the

IN

regulator immediately resumes normal operation. The

regulator does not execute its soft-start function when

exiting an overvoltage condition.

VTTR Output Buffer

The VTTR pin outputs a voltage equal to one half of

VDDQIN. It is capable of sourcing/sinking 10mA and

driving capacitive loads up to 0.01µF. A small series

resistance (1Ω) between the output and the load further

increases the amount of capacitance that the amplifier can

Out-Of-Phase Operation

Tying the PHMODE pin high sets the SW2 falling edge to

be 180° out-of-phase with the SW1 falling edge. There is

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LTC3634

OPERATION

capacitors and reduces the voltage noise on the supply

line.Onepotentialdisadvantagetothisconfigurationoccurs

when one channel is operating at 50% duty cycle. In this

situation, SW node transitions can potentially couple from

one channel to the other, resulting in frequency jitter on one

or both channels. This effect can be mitigated with a well

designed board layout. Alternatively, tying PHMODE low

changes the phase difference to be 90°, which may prevent

SW1 and SW2 from transitioning at the same point in time.

a significant advantage to running both channels out-of-

phase. When running the channels in phase, both topside

MOSFETs are on simultaneously, causing large current

pulses to be drawn from the input capacitor and supply

at the same time. When running the LTC3634 channels

out-of-phase, the large current pulses are interleaved,

effectively reducing the amount of time the pulses overlap.

Thus, the total RMS input current is decreased, which both

relaxes the capacitance requirements for the V bypass

IN

APPLICATIONS INFORMATION

AgeneralLTC3634applicationcircuitisshowninFigure1.

External component selection is largely driven by the load

requirement and switching frequency. Component selec-

tion typically begins with selecting the feedback resistors

to set the desired output voltage. Next the inductor L and

Programming Switching Frequency

Selectionoftheswitchingfrequencyisatrade-offbetween

efficiency and component size. High frequency operation

allows the use of smaller inductor and capacitor values.

Operation at lower frequencies improves efficiency by

reducinginternalgatechargelossesbutgenerallyrequires

larger inductance and capacitance values to maintain low

output ripple voltage. Connecting a resistor from the RT

pintoSGNDprogramstheswitchingfrequency(f)between

500kHz and 4MHz according to the following formula:

resistor R are selected. Once the inductor is chosen, the

T

input capacitor (C ) and the output capacitor (C ) can

IN

OUT

be selected. Finally, the loop compensation components

may be selected to stabilize the step-down regulator. The

remaining optional external components can then be se-

lectedforfunctionssuchasloopcompensation,TRACKSS,

3.2E¹¹

V , UVLO, and PGOOD.

IN

R_RT=

f

where R is in Ω and f is in Hz.

RT

V

IN

3.6V TO 15V

C1

V

IN1

IN2

RUN1

RUN2

RT

BOOST1

0.1µF

L1

LTC3634

SW1

V

ON1

VDDQIN

V

C

DDQ

INTV

CC

C2

2.2µF

R

RT

PHMODE

MODE/SYNC

R2

R1

OUT1

V

FB1

ITH1

BOOST2

SW2

0.1µF

C4

(OPT)

L2

R

COMP1

C

V

C

TT

V

COMP1

FB2

V

ON2

OUT2

ITH2

VTTR

V

REF

SGND PGND

C5

(OPT)

C3

R

COMP2

3634 F01

0.01µF

C

COMP2

Figure 1. Typical Application Circuit for DDR Memory Supply

3634fc

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For more information www.linear.com/LTC3034

LTC3634

APPLICATIONS INFORMATION

6000

The buffered output voltage on the VTTR pin is nominally

equaltohalfoftheVDDQINvoltage;thusconfiguringV

OUT2

5000

4000

3000

2000

1000

as a V bus termination supply for DDR memory is as

TT

simple as shorting V

directly to the V

to V and connecting VDDQIN

DDQ

OUT2

FB2

(the V

supply).

OUT1

Choosing large values for R1 and R2 will result in im-

proved zero-load efficiency but may lead to undesirable

noise coupling or phase margin reduction due to stray

capacitances at the V node. Care should be taken to

FB

0

route the V trace away from any noise source, such as

FB

0

100 200 300 400 500 600 700

R RESISTOR (kΩ)

T

the SW trace.

3634 F02

The LTC3634 controlled on-time architecture is optimized

for an output voltage range of 0.6V to 3V, which is suit-

able for powering DDR memory. The LTC3634 is capable

of regulating higher output voltages; however, controlled

on-time behavior is not ensured. When the output voltage

is greater than 3V, the step-down regulator is forced to

increasetheswitchingfrequencyinordertoachieveoutput

regulation. Furthermore,externalclocksynchronizationis

nolongerpossible,andchannel2cannotmaintain90°/180°

phase operation with respect to channel 1. In short, the

LTC3634 will behave like a constant on-time regulator

insteadofacontrolledon-timeregulator.Therefore,output

voltages greater than 3V should only be used in applica-

tions where switching frequency and channel-to-channel

phase-lockingarenotcriticalperformancecharacteristics.

Figure 2. Switching Frequency vs R_T

When RT is tied to INTV , the switching frequency will

CC

default to approximately 2MHz, as set by an internal resis-

tor. This internal resistor is more sensitive to process and

temperature variations than an external resistor (see the

Typical Performance Characteristics section) and is best

usedforapplicationswhereswitchingfrequencyaccuracy

is not critical.

Output Voltage Programming

Each regulator’s output voltage is set by an external resis-

tive divider according to the following equation:

R2

R1





V

_OUT= V

1+

_FBREG







Inductor Selection

Foragiveninputandoutputvoltage,theinductorvalueand

operatingfrequencydeterminetheinductorripplecurrent.

More specifically, the inductor ripple current decreases

with higher inductor value or higher operating frequency

according to the following equation:

where V

is the reference voltage as specified in the

FBREG

Electrical Characteristics Table. The reference voltage is

600mV for channel 1; for channel 2 the reference voltage

is equal to the VTTR pin voltage. The desired output volt-

age is set by appropriate selection of resistors R1 and R2

as shown in Figure 3.





V

f•L

V_OUT



_OUT

∆I =

1−







L







V





V

OUT

IN

C

F

R2

R1

whereΔI =inductorripplecurrent,f=operatingfrequency

(OPTIONAL)

L

V

FB

and L = inductor value. A trade-off between component

size, efficiency and operating frequency can be seen from

LTC3634

SGND

this equation. Accepting larger values of ΔI allows the

L

3634 F03

useoflowervalueinductorsbutresultsingreaterinductor

Figure 3. Setting the Output Voltage

3634fc

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LTC3634

APPLICATIONS INFORMATION

Table 1. Inductor Selection Table

INDUCTANCE DCR MAX

(µH) (mΩ) CURRENT (A)

Würth Electronik WE-HC 744310 Series

core loss, greater ESR loss in the output capacitor, and

larger output voltage ripple. Generally, highest efficiency

operation is obtained at low operating frequency with

small ripple current.

DIMENSIONS

(mm)

HEIGHT

(mm)

0.24

0.55

0.95

1.15

2.00

2.1

3.8

18.0

14.0

11.0

8.5

7 × 7

3.3

A reasonable starting point is to choose a ripple current

somewhere between 600mA and 1.2A peak-to-peak. Note

that the largest ripple current occurs at the highest V .

Exceeding 1.8A is not recommended in order to minimize

outputvoltageripple.Toguaranteethatripplecurrentdoes

not exceed a specified maximum, the inductance should

be chosen according to:

6.4

9.0

14.0

6.5

IN

Vishay IHLP-2020BZ-01 Series

0.22

0.33

0.47

0.68

1

5.2

8.2

8.8

12.4

20

15

12

5.2 × 5.5

2

11.5

10

7

Toko FDV0620 Series













V_OUT

f•∆I_{L(MAX) }

V_OUT

0.20

0.47

1.0

4.5

8.3

18.3

12.4

9.0

7 × 7.7

6 × 8.9

2.0

5.0

3.2

L =

1−



V



_IN(MAX)



5.7

Coilcraft D01813H Series

0.33

0.56

1.2

4

10

7.7

5.3

Once the value for L is known, the type of inductor must

be selected. Actual core loss is independent of core size

for a fixed inductor value, but is very dependent on the

inductance selected. As the inductance increases, core

losses decrease. Unfortunately, increased inductance

requires more turns of wire, leading to increased DCR

and copper loss.

10

17

TDK RLF7030 Series

1.0

1.5

8.8

9.6

6.4

6.1

6.9 × 7.3

C and C

Selection

IN

OUT

Ferrite designs exhibit very low core loss and are pre-

ferred at high switching frequencies, so design goals

can concentrate on copper loss and preventing satura-

tion. Ferrite core material saturates “hard”, which means

that inductance collapses abruptly when the peak design

current is exceeded. This results in an abrupt increase in

inductor ripple current, so it is important to ensure that

the core will not saturate.

The input capacitance, C , is needed to filter the trapezoi-

IN

dal wave current at the drain of the top power MOSFET.

To prevent large voltage transients from occurring, a low

ESR input capacitor sized for the maximum RMS current

is recommended. The maximum RMS current for a single

regulator is given by:

V_OUTV − V

(

)

IN

OUT

I

_RMS= I_OUT(MAX)

V

IN

Different core materials and shapes will change the size/

currentandprice/currentrelationshipofaninductor.Toroid

or shielded pot cores in ferrite or permalloy materials are

small and don’t radiate much energy, but generally cost

more than powdered iron core inductors with similar

characteristics. The choice of which style inductor to use

mainly depends on the price versus size requirements

and any radiated field/EMI requirements. Table 1 gives a

sampling of available surface mount inductors.

When both regulators are active, the input current wave-

formissignificantlydifferent. Furthermore,theinputRMS

current varies depending on each output’s load current as

well as whether V is sinking or sourcing current.

TT

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LTC3634

APPLICATIONS INFORMATION

mustinstantaneouslysupplythecurrenttosupporttheload

until the feedback loop raises the switch current enough

to support the load. The time required for the feedback

loop to respond is dependent on the compensation and

the output capacitor size. Typically, three to four cycles

are required to respond to a load step, but only in the first

cycle does the output drop linearly. The output droop,

WhenSW1andSW2operate180°out-of-phase,theworst-

case input RMS current occurs when the V supply is

TT

sinking current and V

is sourcing the same amount of

DDQ

current. Knowing that V

= one-half V

in the DDR

OUT2

OUT1

application, the input RMS current in this case is given by:

D1







I

_RMS= I_OUT(MAX)D1 1.5−

for D1 < 0.5







4

V

, is usually about three times the linear drop of

DROOP

the first cycle, provided the loop crossover frequency is

maximized. Thus, a good place to start is with the output

capacitor size of approximately:

3

4

_RMS= I_OUT(MAX)1− D1 for D1 > 0.5

where D1 is the duty cycle of channel 1 (V

supply).

3•∆I_OUT

f•V_DROOP

DDQ

C_OUT

≈

These equations show that maximum I

occurs at

RMS

50% duty cycle (V = 2 • V

). This simple worst-case

OUT1

IN

Thoughthisequationprovidesagoodapproximation,more

capacitance may be required depending on the duty cycle

condition may be used for design as deviations in duty

cycle do not offer significant relief. Note that ripple current

ratings from capacitor manufacturers are often based on

only 2000 hours of life which makes it advisable to further

deratethecapacitor,orchooseacapacitorratedatahigher

temperature than required.

and load step requirements. The actual V

should be

DROOP

verified by applying a load step to the output.

Using Ceramic Input and Output Capacitors

Higher values, lower cost ceramic capacitors are available

in small case sizes. Their high ripple current, high voltage

ratingandlowESRmakethemidealforswitchingregulator

applications. However, due to the self-resonant and high-

Q characteristics of some types of ceramic capacitors,

care must be taken when these capacitors are used at

the input. When a ceramic capacitor is used at the input

and the power is supplied by a wall adapter through long

wires, a load step at the output can induce ringing at the

Several capacitors may also be paralleled to meet size or

height requirements in the design. For low input voltage

applications, sufficient bulk input capacitance is needed

to minimize transient effects during output load changes.

Even though the LTC3634 design includes an overvoltage

protection circuit, care must always be taken to ensure

input voltage transients do not pose an overvoltage haz-

ard to the part.

The selection of C

is determined by the effective series

OUT

V input. Atbest, thisringingcancoupletotheoutputand

IN

resistance(ESR)thatisrequiredtominimizevoltageripple

and load step transients as well as the amount of bulk

capacitance that is necessary to ensure that the control

loop is stable. Loop stability can be checked by viewing

be mistaken as loop instability. At worst, a sudden inrush

of current through the long wires can potentially cause a

voltage spike at V large enough to damage the part. For

IN

a more detailed discussion, refer to Application Note 88.

the load transient response. The output ripple, ΔV , is

OUT

When choosing the input and output ceramic capacitors,

choose the X5R and X7R dielectric formulations. These

dielectrics have the best temperature and voltage char-

acteristics of all the ceramics for a given value and size.

approximated by:





1

∆V_OUT< ∆I_LESR+







8•f•C

_OUT

When using low-ESR ceramic capacitors, it is more use-

ful to choose the output capacitor value to fulfill a charge

storage requirement. During a load step, the output capacitor

3634fc

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LTC3634

APPLICATIONS INFORMATION

Choosing Compensation Components

The first step is to choose the crossover frequency f .

C

Higher crossover frequencies will result in a faster loop

transient response; however, in order to avoid higher or-

der loop dynamics from the switching power stage, it is

Loop compensation is a complicated subject and Applica-

tion Note 76 is recommended reading for a full discussion

on maximizing loop bandwidth in a current mode switch-

ing regulator. This section will provide a quick method on

choosingpropercomponentstocompensatetheLTC3634

regulators.

recommended that f not exceed one-tenth the switching

C

frequency (f ).

SW

Once f is chosen, the value of R

that sets this cross-

COMP

C

overfrequencycanbecalculatedbythefollowingequation:

Figure 4 shows the recommended components to be con-

nected to the ITH pin, and Figure 5 shows an approximate

bode plot of the buck regulator loop using these compo-

nents. It is assumed that the major poles in the system

(the output capacitor pole and the error amplifier output

pole) are located at a frequency lower than the crossover

frequency.



 

 





2π •f_C•C_OUT

V_OUT

R_COMP

=



g_m(EA)•g_{m(MOD)  }V_{FBREG }



where g

is the error amplifier transconductance

m(EA)

(see the Electrical Characteristics section), and g

m(MOD)

is the modulator transconductance (the transfer function

from ITH voltage to current comparator threshold). For

–1

the LTC3634, this transconductance is nominally 7Ω .

ITH

R

Once R

is determined, C

can be chosen to set

COMP

LTC3634

C

BYP

the zero frequency (f ):

Z

C

COMP

SGND

1

f_Z=

3634 F04

2π •C_COMP•R_COMP

Figure 4. Compensation and Filtering Components

For 90° of phase margin, f should be chosen to be less

Z

than one-tenth of f .

C

Since the ITH node is sensitive to noise coupling, a small

|H(s)|

bypass capacitor (C ) may be used to filter out board

BYP

–2

noise. However, this cap contributes a pole at f and may

P

introduce some phase loss at the crossover frequency:

1

f_P=

2π •C_BYP•R_COMP

–1

ƒ

P

0dB

For best results, f should be set high enough such that

LOG (ƒ)

P

ƒ

C

Z

phase margin is not significantly affected.

3634 F05

If necessary, a capacitor C (as shown in Figure 3) may

F

Figure 5. Bode Plot of Regulator Loop

be used to add some phase lead.

3634fc

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LTC3634

APPLICATIONS INFORMATION

Checking Transient Response

Insomeapplications,amoreseveretransientcanbecaused

by switching in loads with large (>10μF) input capacitors.

Thedischargedinputcapacitorsareeffectivelyputinparal-

The regulator loop response can be checked by observing

the response of the system to a load step. The ITH pin not

only allows optimization of the control loop behavior but

also provides a DC-coupled and AC filtered closed loop

response test point. The DC step, rise time, and settling

behavioratthistestpointreflecttheclosedloopresponse.

Assuming a predominantly second order system, phase

margin and/or damping factor can be estimated using the

percentage of overshoot seen at this pin.

lel with C , causing a rapid drop in V . No regulator

OUT

can deliver enough current to prevent this problem, if the

switchconnectingtheloadhaslowresistanceandisdriven

quickly. The solution is to limit the turn-on speed of the

load switch driver. A Hot Swap™ controller is designed

specifically for this purpose and usually incorporates cur-

rent limiting, short-circuit protection, and soft-starting.

After choosing compensation values as discussed in the

previous section, the design should be tested to verify

stability. The component values may be modified slightly

to optimize transient response once the final PC layout is

done and the particular output capacitor type and value

have been determined. The output capacitors need to be

selectedbecausetheirvarioustypesandvaluesdetermine

the loop gain and phase. An output current pulse of 20%

to 100% of full load current having a rise time of ~1μs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop.

INTV Regulator Bypass Capacitor

CC

Aninternallowdropout(LDO)regulatorproducesthe3.3V

supply that powers the internal bias circuitry and drives

the gate of the internal MOSFET switches. The INTV pin

CC

connects to the output of this regulator and must have a

minimum of 1μF ceramic bypass capacitance to ground.

This capacitor should have low impedance electrical

connections to the INTV and PGND pins to provide the

CC

transient currents required by the LTC3634. This supply

is intended only to supply additional DC load currents as

desired and not intended to regulate large transient or AC

behavior, as this may impact LTC3634 operation.

Switching regulators take several cycles to respond to a

Boost Capacitor

step in load current. When a load step occurs, V

im-

OUT

•ESR,where

mediatelyshiftsbyanamountequaltoΔI

LOAD

The LTC3634 uses a bootstrap circuit to create a voltage

ESR is the effective series resistance of C . ΔI

also

OUT

LOAD

railabovetheappliedinputvoltageV .Specifically,aboost

IN

beginstochargeordischargeC ,generatingafeedback

OUT

capacitor, C

, is charged to a voltage approximately

equal to INTV each time the bottom power MOSFET is

BOOST

CC

error signal used by the regulator to return V

to its

can

OUT

steady-state value. During this recovery time, V

OUT

turned on. The charge on this capacitor is then used to

supplytherequiredtransientcurrentduringtheremainder

oftheswitchingcycle. WhenthetopMOSFETisturnedon,

be monitored for overshoot or ringing that would indicate

a stability problem.

the BOOST pin voltage will be equal to approximately V

When observing the response of V

to a load step, the

IN

OUT

+ 3.3V. For most applications, a 0.1μF ceramic capacitor

closely connected between the BOOST and SW pins will

provide adequate performance.

initialoutputvoltagestepmaynotbewithinthebandwidthof

thefeedbackloop,sothestandardsecondorderovershoot/

DC ratio cannot be used to determine phase margin. The

output voltage settling behavior is related to the stability

of the closed-loop system and will demonstrate the actual

overall supply performance. For a detailed explanation of

optimizing the compensation components, including a

review of control loop theory, refer to Application Note 76.

3634fc

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LTC3634

APPLICATIONS INFORMATION

Minimum Off-Time/On-Time Considerations

MODE/SYNC Operation

The MODE/SYNC pin is a multipurpose pin allowing both

mode selection and operating frequency synchronization.

The minimum off-time is the smallest amount of time that

the LTC3634 can turn on the bottom power MOSFET, trip

the current comparator and turn the power MOSFET back

off. This time is typically 40ns. For the controlled on-time

control architecture, the minimum off-time limit imposes

a maximum duty cycle of:

Floating this pin or connecting it to INTV enables Burst

CC

Mode operation on channel 1 for superior efficiency at

light load currents at the expense of slightly higher out-

put voltage ripple. When the MODE/SYNC pin is tied to

ground, forced continuous mode operation is selected,

creating the lowest fixed output ripple at the expense of

light load efficiency.

DC

= 1– f • (t

+ 2 • t

)

MAX

OFF(MIN)

DEAD

wherefistheswitchingfrequency, t

isthenonoverlap

DEAD

time of the switches, or dead time (typically 15ns), and

is the minimum off-time. If the maximum duty

The LTC3634 will detect the presence of the external

clock signal on the MODE/SYNC pin and synchronize the

internal oscillator to the phase and frequency of the in-

coming clock. The presence of an external clock will place

both regulators into forced continuous mode operation.

t

OFF(MIN)

cycle is surpassed, due to a decreasing input voltage

for example, the output will drop out of regulation. The

minimum input voltage to avoid this dropout condition is:

V_OUT

Although the R resistor is not strictly necessary when

T

V_IN(MIN)

=

synchronizing to an external clock, it is recommended to

1− f• t

+2•t_DEAD

(

)

OFF(MIN)

use a R resistor that matches the nominal external clock

T

Conversely, the minimum on-time is the smallest dura-

tion of time in which the top power MOSFET can be in

its ON state. This time is typically 20ns. In continuous

mode operation, the minimum on-time limit imposes a

minimum duty cycle of:

frequency in order to keep the switching regulator biased

correctly whenever the external clock signal is suddenly

removed or reapplied.

Channel 1 Output Voltage Tracking and Soft-Start

The LTC3634 allows the user to control the output voltage

ramp rate of channel 1 by means of the TRACKSS pin.

From 0 to 0.6V, the TRACKSS voltage will override the

internal 0.6V reference input to the error amplifier, thus

regulating the feedback voltage to that of the TRACKSS

pin. When TRACKSS is above 0.6V, tracking is disabled

and the feedback voltage will regulate to the internal

reference voltage.

DC

= (f • t

)

MIN

ON(MIN)

where t

is the minimum on-time. As the equation

ON(MIN)

shows, reducing the operating frequency will alleviate the

minimum duty cycle constraint.

When the regulator output is sinking current, the effective

minimumon-timeoftheconverterwillbeincreasedbythe

non-overlap time of the power MOSFETs (or the “dead-

time”) during each SW node transition. This “dead-time”

is nominally 15ns, so when sinking current, the minimum

on-time is effectively 15ns + 15ns + 20ns = 50ns.

The voltage at the TRACKSS pin may be driven from an

external source, or alternatively, the user may leverage

the internal 1.4μA pull-up current source to implement

a soft-start function by connecting an external capacitor

Iftheminimumon-timeconstraintisviolated,theconverter

will automatically reduce its own switching frequency in

order to maintain output regulation. Once the converter

reduces its switching frequency, the phase information

is lost and the two channels will switch asynchronously.

(C ) from the TRACKSS pin to ground. The relationship

SS

between output rise time and TRACKSS capacitance is

given by:

t

SS

= 430000Ω • C

SS

Furthermore, the regulator may need to be compensated

moreconservativelyduetothelowerswitchingfrequency.

3634fc

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LTC3634

APPLICATIONS INFORMATION

ficientvoltagetodischargetheinductorincontinuousmode

and prevent excessive build-up of energy in the inductor.

A default internal soft-start ramp forces a minimum soft-

start time of 400μs by overriding the TRACKSS pin input

during this time period. Hence, capacitance values less

than approximately 1000pF will not significantly affect

soft-start behavior.

Output Power Good

The PGOOD output of the LTC3634 is driven by a 15Ω

(typical) open-drain pull-down device. If the output volt-

age exits an 8% (typical) regulation window around the

targetregulationpoint,theopen-drainoutputwillpulldown

with 15Ω output resistance to ground, thus dropping the

PGOOD pin voltage. This pull-down device will not shut

off until the output re-enters this window and overcomes

a small amount of hysteresis. This behavior is described

in Figure 6.

Start-Up Behavior

Upon start-up, both channels immediately default to

discontinuous operation. Channel 1 will remain in dis-

continuous Burst Mode operation until its output rises to

greater than 80% of its final value (V > 480mV). Once

FB

the output exceeds this voltage, the operating mode of

the regulator switches to the mode selected by the MODE/

SYNC pin as described above. During normal operation,

if the output drops below 10% of its final value (as it may

when tracking down, for instance), the regulator will

automatically switch to Burst Mode operation to prevent

inductor saturation and improve TRACKSS pin accuracy.

A filter time of 40μs (typical) acts to prevent unwanted

PGOOD output changes during V

transient events. As

OUT

a result, the output voltage must exit the 8% regulation

window for 40μs before the PGOOD pin pulls to ground.

Conversely, the output voltage must be within the target

regulation window for 40μs before the PGOOD pin pulls

high.

Channel 2 (the V termination supply) remains in discon-

TT

tinuous operation until its output rises above 300mV, at

whichpointitwillautomaticallyswitchtoforcedcontinuous

operation. This ensures that the regulator output has suf-

NOMINAL OUTPUT

V

: 2.5%

HYS(CH1)

15mV

:

• 100%

V

HYS

HYS(CH2)

HYS

VTTR

PGOOD

VOLTAGE

–8%

0%

8%

OUTPUT VOLTAGE

3634 F06

Figure 6. PGOOD Pin Behavior

3634fc

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LTC3634

APPLICATIONS INFORMATION

2-Phase, Single V Output Configuration

V

and V may be powered from separate supply volt-

IN1 IN2

TT

ages (see Figure 12). This is useful in cases where power

needs to be shared between two different sources. It is

The two regulators on the LTC3634 can be easily com-

bined to provide a single 2-phase V termination supply

TT

important to note that when the V output sinks current,

TT

capable of sourcing and sinking up to 6A. The circuit is

shown in Figure 7.

it will backfeed through the converter and out of the V

IN

pins. Care must be taken to ensure that the input supplies

In this circuit, V is tied to INTV to put the LTC3634

are able to handle this condition.

FB1

CC

into2-phaseoperation.Whensetupfor2-phaseoperation,

the inputs to channel 1’s transconductance error amplifier

Efficiency Considerations

are switched to be the same as channel 2’s inputs (V

FB2

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

and VTTR), allowing it to be paralleled with channel 2’s

error amplifier. The ITH1 and ITH2 pins should be tied

together externally to force equal current sharing between

both channels.

Only one compensation network is needed on the ITH

node, although separate filter caps for each ITH pin may

be helpful depending on the board layout. In this parallel

% Efficiency = 100% – (L1 + L2 + L3 +…)

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power. Although all dissipative elements in the

circuitproducelosses,threemainsourcesusuallyaccount

for most of the losses in LTC3634 circuits: 1) conduction

losses, 2) switching losses and quiescent power loss 3)

transition losses and other losses.

configuration,itisimportanttonotethattheeffectiveg

m(EA)

and g

are twice as large as that of a single channel.

m(MOD)

One advantage to this 2-phase configuration is that both

input and output current ripple is significantly reduced

comparedtoasinglephase6Aconvertersolution,because

thecurrentwaveformsfromeachregulatorareinterleaved.

Refer to Application Note 77 for a full discussion and

analysis on PolyPhase^®converters.

V

IN

3.6V TO 15V

C1

V

IN1

47µF

×2

IN2

RUN1

RUN2

RT

BOOST1

L1

0.1µF

0.47µH

LTC3634

V

TT

DDQ

SW1

BOOST2

/2 AT 6A

INTV

PHMODE

CC

L2

0.47µH

R1

160k

C2

2.2µF

0.1µF

V

SW2

FB1

V

FB2

V

DDQ

C

OUT2

VDDQIN

ITH1

V

ON2

ON1

SUPPLY

100µF

×4

10pF

6k

1000pF

VTTR

V

REF

DDQ

/2 AT 10ꢀA

0.01µF

ITH2

MODE/SYNC

SGND PGND

10pF

3634 F07

Figure 7. Application Circuit for a 2-Phase, 6A Single V_TTOutput

3634fc

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LTC3634

APPLICATIONS INFORMATION

1. Conduction losses are calculated from the DC resis-

Thermal Considerations

tances of the internal switches, R , and external

SW

The LTC3634 requires the exposed package back-plane

metal (PGND) to be well soldered to the PC board to

provide good thermal contact. This gives the QFN and

TSSOP packages exceptional thermal properties, which

are necessary to prevent excessive self-heating of the part

in normal operation.

inductor, R . In continuous mode, the average output

L

current flows through inductor L but is “chopped”

between the internal top and bottom power MOSFETs.

Thus, the series resistance looking into the SW pin is a

function of both top and bottom MOSFET R

the duty cycle (DC) as follows:

and

DS(ON)

In a majority of applications, the LTC3634 does not dis-

sipatemuchheatduetoitshighefficiencyandlowthermal

resistance of its exposed-back QFN package. However, in

applications where the LTC3634 is running at high ambi-

R

= (R

)(DC) + (R

)(1 – DC)

SW

DS(ON)TOP

DS(ON)BOT

TheR

forboththetopandbottomMOSFETscanbe

DS(ON)

obtained from the Typical Performance Characteristics

curves. So to calculate conduction losses:

ent temperature, high V , high switching frequency, and

IN

maximum output current load, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 170°C,

bothpowerswitcheswillbeturnedoffuntilthetemperature

returns to 160°C.

2

Conduction Loss = I

(R + R )

SW L

OUT

2. The internal LDO supplies the power to the INTV rail.

CC

The total power loss here is the sum of the switching

losses and quiescent current losses from the control

circuitry.

To prevent the LTC3634 from exceeding the maximum

junction temperature of 125°C, the user will need to do

some thermal analysis. The goal of the thermal analysis

is to determine whether the power dissipated exceeds the

maximum junction temperature of the part. The tempera-

ture rise is given by:

Each time a power MOSFET gate is switched from low

to high to low again, a packet of charge dQ moves from

V

to ground. The resulting dQ/dt is a current out of

IN

INTV that is typically much larger than the DC control

CC

bias current. In continuous mode, I

= f • (Q +

GATECHG

T

Q ),whereQ andQ arethegatechargesoftheinternal

B

T

B

T

RISE

= P • θ

D JA

top and bottom power MOSFETs and f is the switching

frequency. For estimation purposes, (Q + Q ) on each

As an example, consider the case when the LTC3634 is

used to power DDR2 SDRAM and is used in an application

T

B

LTC3634 regulator channel is approximately 2.3nC.

where maximum ambient temperature is 70°C, V = 12V,

IN

To calculate the total power loss from the LDO load,

simply add the gate charge current and quiescent cur-

frequency = 1MHz, V

= 1.8V, V = 0.9V, and I

=

DDQ

TT

LOAD

2A for both channels.

rent and multiply by V :

IN

From the R graphs in the Typical Performance

DS(ON)

P

= (I

+ I ) • V

LDO

GATECHG Q IN

Characteristics section, the top switch on-resistance is

3.Otherhiddenlossessuchastransitionloss,coppertrace

resistances, and internal load currents can account for

additional efficiency degradations in the overall power

system. Transition loss arises from the brief amount of

time the top power MOSFET spends in the saturated

region during switch node transitions. The LTC3634

internalpowerdevicesswitchquicklyenoughthatthese

losses are not significant compared to other sources.

Other losses, including diode conduction losses during

dead-time and inductor core losses, generally account

for less than 2% total additional loss.

nominally 140mΩ and the bottom switch on-resistance

is nominally 75mΩ at 70°C ambient. For the V

supply,

DDQ

the equivalent power MOSFET resistance R

is:

SW1

1.8V

12V

10.2V

12V

R_DS(ON)TOP

•

+R_DS(ON)BOT

•

= 84.8mΩ

The same calculation to the V supply (0.9V), yields

TT

R

SW2

= 79.9mΩ.

From the previous section’s discussion on gate drive, we

estimate the total gate charge current for each regulator to

3634fc

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LTC3634

APPLICATIONS INFORMATION

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

be 1MHz • 2.3nC = 2.3mA, and the total I of both chan-

Q

nels is 1.3mA (see the Electrical Characteristics section).

Therefore,thetotalpowerdissipatedbybothregulatorsis:











P = I

²•R

+ I

²•R

(

)

(

)

D





OUT1

OUT2

^SW1





^SW2



+ V • I_GATECHG+I_Q

(

)

IN

CH2 LOAD = 0A

CH2 LOAD = 1A

CH2 LOAD = 2A

CH2 LOAD = 3A

P_D=(2A)²•0.0848Ω+(2A)²•0.0799Ω

+12V • 2.3mA •2 +1.3mA = 0.730W





(

)





0

25

50

75

100

125

MAXIMUM ALLOWABLE AMBIENT

TheQFN4mm×5mmpackagejunction-to-ambientthermal

TEMPERATURE (°C)

3634 F08

resistance, θ , is around 43°C/W. Therefore, the junction

JA

Figure 8. Temperature Derating Curve for DC1708 Demo Circuit

temperature of the regulator operating in a 70°C ambient

temperature is approximately:

temperature directly is to use the internal junction diode

on one of the PGOOD pins to measure its diode voltage

change based on ambient temperature change.

T = 0.730W • 43°C/W + 70°C = 101°C

J

which is below the maximum junction temperature of

125°C. With higher ambient temperatures, a heat sink or

cooling fan should be considered to drop the junction-to-

ambientthermalresistance.Alternatively,theexposedpad

TSSOP package may be a better choice for high power

applications, since it has better thermal properties than

the QFN package.

FirstremoveanyexternalpassivecomponentonthePGOOD

pin, then pull out 100μA from the PGOOD pin to turn on

its internal junction diode and bias the PGOOD pin to a

negativevoltage.Withnooutputcurrentload,measurethe

PGOOD voltage at an ambient temperature of 25°C, 75°C

and 125°C to establish a slope relationship between the

voltage on PGOOD and ambient temperature. Once this

slopeisestablished,thenthejunctiontemperaturerisecan

be measured as a function of power loss in the package

with corresponding output load current. Although making

this measurement with this method does violate absolute

maximum voltage ratings on the PGOOD pin, the applied

power is so low that there should be no significant risk

of damaging the device.

Remembering that the above junction temperature is ob-

tained from a R

at 70°C, we might recalculate the

DS(ON)

junction temperature based on a higher R

since it

DS(ON)

increases with temperature. Redoing the calculation as-

suming that R increased 12% at 101°C yields a new

SW

junction temperature of 105°C.

Figure 8 is a temperature derating curve based on the

DC1708 demo board (QFN package). It can be used as

a guideline to estimate the maximum allowable ambient

temperature for given DC load currents in order to avoid

exceeding the maximum operating junction temperature

of 125°C.

Board Layout Considerations

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3634. Check the following in your layout:

Junction Temperature Measurement

1. Do the input capacitors connect to the V and PGND

IN

pins as close as possible? These capacitors provide

the AC current to the internal power MOSFETs and their

drivers.

The junction-to-ambient thermal resistance will vary de-

pending on the size and amount of heat sinking copper

on the PCB board where the part is mounted, as well as

the amount of air flow on the device. In order to properly

evaluate this thermal resistance, the junction temperature

needstobemeasured.Acleverwaytomeasurethejunction

2. The output capacitor, C , and inductor L should be

OUT

closely connected to minimize loss. The (–) plate of

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LTC3634

APPLICATIONS INFORMATION

C

should be closely connected to both PGND and

Next, select values for R1 and R2 to set channel 1 (V

to be 1.8V for DDR2 SDRAM. Choosing R1 to be 12.1k,

R2 is calculated to be:

)

OUT

DDQ

the (–) plate of C .

IN

3. The resistive divider, (e.g. R1 and R2 in Figure 1) must

be connected between the (+) plate of C

and a

1.8V

0.6V







OUT

R2=12.1k •

−1 = 24.2k







groundlineterminatednearSGND. Thefeedbacksignal

V

should be routed away from noisy components

FB

and traces, such as the SW line, and its trace length

The closest standard value is 24.3k. Tying VDDQIN to

sets V to be half of V

should be minimized. In addition, the R resistor and

loop compensation components should be terminated

V

OUT1

.

OUT1

T

OUT2

Next, we can pick inductor values for both the V

TT

and

DDQ

to SGND.

V

outputs. Choosing inductor current ripple to be 1A

4. Keep sensitive components away from the SW pin. The

at maximum V :

IN

R resistor,thecompensationcomponents,thefeedback

T





1.8V

1MHz •1A

1.8V

13.2V





resistors, and the INTV bypass capacitor should all

CC

L1=

L2=

1−

=1.55µH

















be routed away from the SW trace and the inductor L.







5. A ground plane is preferred, but if not available, the

signal and power grounds should be segregated with

bothconnectingtoacommon,lownoisereferencepoint.

The connection to the PGND pin should be made with

a minimal resistance trace from the reference point.

0.9V

13.2V



1−

= 0.838µH













1MHz •1A





Standard values of 1.5μH and 0.82µH should be used.

Ceramic caps will be used for C and will be selected

OUT

based on the charge storage requirement. Assuming a

worst case 4A load step (–2A to 2A):

6. Flood all unused areas on all layers with copper in order

to reduce the temperature rise of power components.

Thesecopperareasshouldbeconnectedtotheexposed

backside of the package (PGND). Refer to Figures 10

and 11 for board layout examples.

3•4A

1MHz •60mV

C_OUT1

≈

= 200µF

= 400µF

3•4A

1MHz •30mV

C_OUT2

Design Example

As a design example, consider using the LTC3634 (as

shown in Figure 1) to power DDR2 SDRAM with the fol-

Lastly,wewillchoosecompensationcomponents.Choos-

ing the crossover frequency f = 50kHz:

C

lowing specifications: V

f = 1MHz, V

= 13.2V, I

= 2A,

IN(MAX)

OUT(MAX)

< 60mV, V

) < 30mV.

DROOP(VTT





DROOP(VDDQ)

2π •50kHz •200µF 1.8V





R_{COMP1 }

=

= 27kΩ

=18kΩ

The following discussion will use equations from the

previous sections.









1mΩ⁻¹•7Ω⁻¹



0.6V









2π •50kHz •400µF 0.9V







First, the correct R resistor value for 1MHz switching

T

R_{COMP2 }

=





1mΩ⁻¹•7Ω⁻¹



frequency must be chosen. Based on previous discus-

0.9V





sions, R is calculated to be

T

Choosing the zero frequency to be 10kHz yields C

=

COMP1



¹¹

3.2E

f

589pF and C

= 884pF. The closest standard values

COMP2

R_T=

= 320kΩ





for the compensation components are 26.7k, 18k, 560pF

and 910pF, respectively.





The closest standard value is 324k.

The final circuit is shown in Figure 9.

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LTC3634

APPLICATIONS INFORMATION

V

IN

3.6V TO 15V

C1

V

IN1

47µF

×2

IN2

RUN1

RUN2

RT

BOOST1

SW1

L1

1.5µH

0.1µF

V

DDQ

LTC3634

1.8V

INTV

PHMODE

MODE/SYNC

V

ON1

VDDQIN

CC

R3

324k

C2

2.2µF

C

OUT1

100µF

V

FB1

×2

R1

12.1k

R2

24.3k

ITH1

BOOST2

R

COMP1

C4

10pF

L2

26.7k

0.82µH

0.1µF

V

C

TT

COMP1

SW2

0.9V

560pF

V

FB2

C

ITH2

V

ON2

VTTR

OUT2

V

100µF

REF

C5

10pF

R

0.9V

0.01µF

COMP2

×4

SGND PGND

18k

3634 F09

C

COMP2

910pF

Figure 9. Design Example Circuit

VIA TO BOOST1 VIA TO V /R2 (NOT SHOWN)

ON1

V

OUT1

C

VIA TO V

AND R2 (NOT SHOWN)

ON1

OUT1

L1

C

OUT1

GND

V

OUT1

VIAS TO GROUND

PLANE

VIAS TO GROUND

PLANE

SW1

C

BOOST1

GND

C

IN

L1

VIAS TO GROUND

PLANE

C

IN

VIA TO BOOST1

V

IN

SW1

VIAS TO GROUND

PLANE

SGND (TO NONPOWER

COMPONENTS)

C

BOOST1

BOOST2

V

IN

SGND (TO NONPOWER

COMPONENTS)

SW2

L2

IN

BOOST2

VIA TO BOOST2

SW2

IN

GND

VIAS TO GROUND

PLANE

GND

L2

VIAS TO GROUND

PLANE

C

OUT2

V

OUT2

C

OUT2

V

OUT2

3634 F11

3634 F10

VIA TO V

AND V

(NOT SHOWN)

ON2

FB2

VIA TO BOOST2

VIA TO V

AND V

(NOT SHOWN)

ON2

FB2

Figure 10. Example of Power Component Layout

for QFN Package

Figure 11. Example of Power Component Layout

for TSSOP Package

3634fc

24

For more information www.linear.com/LTC3034

LTC3634

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC3634#packaging for the most recent package drawings.

UFD Package

28-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1712 Rev B)

0.70 ±0.05

4.50 ±0.05

3.10 ±0.05

2.50 REF

2.65 ±0.05

3.65 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

3.50 REF

4.10 ±0.05

5.50 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.20 OR 0.35

× 45° CHAMFER

2.50 REF

R = 0.115

TYP

R = 0.05

TYP

0.75 ±0.05

4.00 ±0.10

(2 SIDES)

27

28

0.40 ±0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

5.00 ±0.10

(2 SIDES)

3.50 REF

3.65 ±0.10

2.65 ±0.10

(UFD28) QFN 0506 REV B

0.25 ±0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

0.200 REF

0.00 – 0.05

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3634fc

25

For more information www.linear.com/LTC3034

LTC3634

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC3634#packaging for the most recent package drawings.

FE Package

28-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663 Rev J)

Exposed Pad Variation EB

9.60 – 9.80*

(.378 – .386)

4.75

(.187)

4.75

(.187)

28 27 26 2524 23 22 21 20 1918 17 16 15

2.74

(.108)

EXPOSED

PAD HEAT SINK

ON BOTTOM OF

PACKAGE

6.60 ±0.10

4.50 ±0.10

SEE NOTE 4

6.40

(.252)

BSC

2.74

(.108)

0.45 ±0.05

1.05 ±0.10

0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT

5

7

1

2

3

4

6

8

9 10 12 13 14

11

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

FE28 (EB) TSSOP REV J 1012

0.195 – 0.30

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

2. DIMENSIONS ARE IN

FOR EXPOSED PAD ATTACHMENT

MILLIMETERS

(INCHES)

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3. DRAWING NOT TO SCALE

3634fc

26

For more information www.linear.com/LTC3034

LTC3634

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

09/13 Clarified Absolute Maximum Ratings, added H and MP grades to Order Information.

2

Clarified parametric data.

Clarified graphs.

3, 4

5, 6

7, 8

18

Clarified RUN1, RUN2 pin function, INTV

Clarified minimum on-time description.

.

CC

Clarified maximum junction temperature in Thermal Considerations.

Clarified Related Parts, added LTC3786 and LTC3633A.

12/13 Clarified dead-time from 10ns to 15ns.

21

28

B

C

18

01/16 Added package option for mini reels

Expanded VTTR pin description

2

9

11

Expanded description in VTTR Output Buffer

3634fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

For more information www.linear.com/LTC3034

LTC3634

TYPICAL APPLICATION

V

IN

12V

5V

3.6V TO

15V

C6

22µF

C1

22µF

C3

47µF

C1

22µF

V

IN2

V

IN1

V

IN1

IN2

RUN1

RUN2

RT

BOOST1

RUN1

RUN2

RT

BOOST1

SW1

L1

0.1µF

1.5µH

1µH

V

TT

DDQ

AT 6A

LTC3634

SW1

BOOST2

V

DDQ

/2

R1

1.5V

INTV

V

ON1

CC

L2

1.5µH

R

T

324k

C2

2.2µF

R2

18.2k

C

OUT1

PHMODE

VDDQIN

162k

C2

2.2µF

100µF

×2

V

FB1

SW2

MODE/SYNC

ITH1

V

FB1

R1

12.1k

V

FB2

C

V

OUT2

DDQ

SUPPLY

VDDQIN

ITH1

V

ON2

V

ON1

BOOST2

100µF

×4

L2

0.47µH

R

COMP1

C4

10pF

0.1µF

C3

26.4k

SW2

V

TT

10k

10pF

C

COMP1

0.75V

V

FB2

560pF

V

680pF

REF

C

VTTR

MODE/SYNC

SGND PGND

V

ON2

OUT2

V

/2

DDQ

AT 10ꢀA

100µF

×4

ITH2

VTTR

0.01µF

V

REF

SGND PGND

R

C5

10pF

COMP2

3634 TA02b

3634 TA02a

18k

0.01µF

C

COMP2

910pF

Figure 12a. V_TTPowered from V_DDQ

Figure 12b. 2-Phase V_TTTermination Using Two Input Supplies

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

95% Efficiency, V

LTC3633

LTC3605

LTC3604

LTC3603

LTC3601

LTC3413

LTC3612

LTC3614

LTC3616

LTC3615

LTC3876

LTC3633A

15V, Dual 3A (I ), 4MHz, Synchronous Step-Down

= 3.6V, V

= 15V, V

= 0.6V,

OUT

IN(MIN)

IN(MAX)

OUT(MIN)

DC/DC Converter

I = 500µA, I <15µA, 4mm × 5mm QFN-28, TSSOP-28E Package

Q SD

15V, 5A (I ), 4MHz, Synchronous Step-Down

95% Efficiency, V

= 4V, V

= 15V, V

= 0.6V,

OUT

IN(MIN)

IN(MAX)

OUT(MIN)

DC/DC Converter

I = 2mA, I <15µA, 4mm × 4mm QFN-24 Package

Q SD

15V, 2.5A (I ), 4MHz, Synchronous Step-Down

95% Efficiency, V

= 3.6V, V

= 15V, V

= 0.6V,

OUT

IN(MIN)

IN(MAX)

OUT(MIN)

DC/DC Converter

I = 300µA, I <15µA, 4mm × 4mm QFN-20, MSOP-16E Package

Q SD

15V, 2.5A (I ), 3MHz, Synchronous Step-Down

95% Efficiency, V

= 4.5V, V

= 15V, V

= 0.6V,

OUT

IN(MIN)

IN(MAX)

OUT(MIN)

DC/DC Converter

I = 75µA, I <1µA, 4mm × 4mm QFN-20 MSOP-16E Package

Q SD

15V, 1.5A (I ), 4MHz, Synchronous Step-Down

95% Efficiency, V

= 4V, V

= 15V, V

= 0.6V,

OUT

IN(MIN)

IN(MAX)

OUT(MIN)

DC/DC Converter

I = 300µA, I <15µA, 4mm × 4mm QFN-20, MSOP-16E Package

Q SD

5.5V, 3A (I

Sink/Source), 2MHz, Monolithic Synchronous 90% Efficiency, V

= 2.25V, V

= 5.5V, V

= V /2,

OUT

IN(MIN)

IN(MAX)

OUT(MIN)

REF

Regulator for DDR/QDR Memory Termination

I = 280µA, I <1µA, TSSOP16E Package

Q SD

5.5V, 3A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, V

= 2.25V, V

= 5.5V, V

= 0.6V,

IN(MIN)

IN(MAX)

OUT(MIN)

I = 75µA, I <1µA, 3mm × 4mm QFN-20 TSSOP-20E Package

Q

SD

5.5V, 4A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, V

= 2.25V, V

= 5.5V, V

= 0.6V,

IN(MIN)

IN(MAX)

OUT(MIN)

I = 75µA, I <1µA, 3mm × 5mm QFN-24 Package

Q

SD

5.5V, 6A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, V

= 2.25V, V

= 5.5V, V

IN(MAX)

IN(MIN)

I = 75µA, I <1µA, 3mm × 5mm QFN-24 Package

Q

SD

5.5V, Dual 3A, 4MHz, Synchronous Step-Down

DC/DC Converter

95% Efficiency, V

= 2.25V, V

= 5.5V, V

IN(MIN)

IN(MAX)

I = 130µA, I <1µA, 4mm × 4mm QFN-24 TSSOP-24E Package

Q

SD

38V Dual DC/DC Controller for DDR Power with

95% Efficiency, V

= 4.5V, V

= 38V, V

= 1V to 2.5V,

IN(MIN)

IN(MAX)

PPQ

V

Reference

V

= 1/2 V , 5mm × 7mm QFN-38, TSSOP-38

TT PPQ

TT

20V, Dual 3A (I ), 4MHz, Synchronous Step-Down

95% Efficiency, V

= 3.6V, V

= 20V, I = 500µA, I <15µA,

IN(MAX) Q SD

OUT

IN(MIN)

DC/DC Converter

4mm × 5mm QFN-28, TSSOP-28E Package

3634fc

LT 0116 REV C • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

For more information www.linear.com/LTC3034

●

 LINEAR TECHNOLOGY CORPORATION 2011

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3634


型号：	LTC3634EFE#TRPBF
厂家：	Linear
描述：	LTC3634 - 15V Dual 3A Monolithic Step-Down Regulator for DDR Power; Package: TSSOP; Pins: 28; Temperature Range: -40°C to 85°C 双倍数据速率开关光电二极管
文件：	总28页 (文件大小：496K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3634EFE#TRPBF [Linear]

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