LTC3677EUFF-3-PBF [Linear]
Highly Integrated Portable Product PMIC; 高集成度便携式产品PMIC
| 型号： | LTC3677EUFF-3-PBF |
| 厂家： | 
Linear |
| 描述： | Highly Integrated Portable Product PMIC |
| 文件： | 总44页 (文件大小：4109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3677-3
Highly Integrated
Portable Product PMIC
FeaTures
DescripTion
TheꢀLTC®3677-3ꢀisꢀaꢀhighlyꢀintegratedꢀpowerꢀmanagementꢀ
ICꢀ forꢀ single-cellꢀ Li-Ion/Polymerꢀ batteryꢀ applications.ꢀ
ItꢀincludesꢀaꢀPowerPathꢀmanagerꢀwithꢀautomaticꢀloadꢀ
prioritization,ꢀaꢀbatteryꢀcharger,ꢀanꢀidealꢀdiode,ꢀinputꢀover-
voltageꢀprotectionꢀandꢀnumerousꢀotherꢀinternalꢀprotectionꢀ
features.ꢀTheꢀLTC3677-3ꢀisꢀdesignedꢀtoꢀaccuratelyꢀchargeꢀ
fromꢀcurrentꢀlimitedꢀsuppliesꢀsuchꢀasꢀUSBꢀbyꢀautomaticallyꢀ
reducingꢀchargeꢀcurrentꢀsuchꢀthatꢀtheꢀsumꢀofꢀtheꢀloadꢀ
currentꢀandꢀtheꢀchargeꢀcurrentꢀdoesꢀnotꢀexceedꢀtheꢀpro-
grammedꢀinputꢀcurrentꢀlimitꢀ(100mAꢀorꢀ500mAꢀmodes).ꢀ
TheꢀLTC3677-3ꢀreducesꢀtheꢀbatteryꢀvoltageꢀatꢀelevatedꢀ
temperaturesꢀtoꢀimproveꢀsafetyꢀandꢀreliability.ꢀTheꢀthreeꢀ
step-downꢀswitchingꢀregulatorsꢀandꢀtwoꢀLDOsꢀprovideꢀ
aꢀwideꢀrangeꢀofꢀavailableꢀsupplies.ꢀTheꢀLTC3677-3ꢀalsoꢀ
includesꢀaꢀpushbuttonꢀinputꢀtoꢀcontrolꢀpowerꢀsequencingꢀ
andꢀsystemꢀreset.ꢀTheꢀLTC3677-3ꢀhasꢀpushbuttonꢀtim-
ingꢀandꢀsequencingꢀdesignedꢀtoꢀsupportꢀtheꢀSiRFꢀAtlasꢀ
IVꢀprocessor.ꢀTheꢀLTC3677-3ꢀisꢀavailableꢀinꢀaꢀlowꢀprofileꢀ
4mmꢀ×ꢀ7mmꢀ×ꢀ0.75mmꢀ44-pinꢀQFNꢀpackage.
n
ꢀ Full Featured Li-Ion/Polymer Charger/PowerPath™
Controller with Instant-On Operation
n
ꢀ Triple Adjustable High Efficiency Step-Down
Switching Regulators (800mA, 500mA, 500mA I
)
OUT
2
n
n
ꢀ I C Adjustable SW Slew Rates for EMI Reduction
ꢀ High Temperature Battery Voltage Reduction
Improves Safety and Reliability
n
ꢀ OvervoltageꢀProtectionꢀControllerꢀforꢀUSBꢀ(V )/Wallꢀ
BUS
InputsꢀProvideꢀProtectionꢀtoꢀ30V
ꢀ 1.5AꢀMaximumꢀChargeꢀCurrentꢀwithꢀThermalꢀLimiting
ꢀ BatteryꢀFloatꢀVoltage:ꢀ4.2V
n
n
n
n
n
ꢀ PushbuttonꢀON/OFFꢀControlꢀwithꢀSystemꢀReset
ꢀ Dualꢀ150mAꢀCurrentꢀLimitedꢀLDOs
ꢀ Start-UpꢀTimingꢀCompatibleꢀwithꢀSiRFꢀAtlasꢀIVꢀ
Processor
n
ꢀ Smallꢀ4mmꢀ×ꢀ7mmꢀꢀ44-PinꢀQFNꢀPackage
applicaTions
n
ꢀ PNDs,ꢀDMB/DVB-H,ꢀDigital/SatelliteꢀRadio,ꢀꢀ
MediaꢀPlayers
L,ꢀLT,ꢀLTC,ꢀLTM,ꢀLinearꢀTechnology,ꢀPowerPath,ꢀBurstꢀModeꢀandꢀtheꢀLinearꢀlogoꢀareꢀregisteredꢀ
trademarksꢀandꢀBat-TrackꢀandꢀHotꢀSwapꢀareꢀtrademarksꢀofꢀLinearꢀTechnologyꢀCorporation.ꢀ
Allꢀotherꢀtrademarksꢀareꢀtheꢀpropertyꢀofꢀtheirꢀrespectiveꢀowners.ꢀProtectedꢀbyꢀU.S.ꢀPatents,ꢀ
includingꢀ6522118,ꢀ6700364,ꢀ7511390,ꢀ5481178,ꢀ6580258.ꢀOtherꢀpatentsꢀpending.
n
ꢀ PortableꢀIndustrial/MedicalꢀProducts
ꢀ OtherꢀUSB-BasedꢀHandheldꢀProducts
n
Typical applicaTion
High Temperature BAT Discharge
5V
ADAPTER
OPTIONAL
200
100mA/500mA
V
V
< V
TOO_HOT
= 0V
NTC
BUS
USB
1000mA
180
160
140
120
100
80
V
OUT
0V
OVERVOLTAGE
PROTECTION
CC/CV
CHARGER
+
SINGLE-CELL
Li-Ion
CHARGE
NTC
LTC3677-3
2
0.8V to 3.6V/150mA
0.8V to 3.6V/150mA
DUAL LDO
2
I C PORT
REGULATORS
60
TRIPLE HIGH
EFFICIENCY
STEP-DOWN
SWITCHING
REGULATORS
40
0.8V to 3.6V/800mA
0.8V to 3.6V/500mA
0.8V to 3.6V/500mA
PUSHBUTTON
CONTROL
20
PB
0
36773 TA01a
3.8
3.9
4.0
(V)
4.2
4.1
V
BAT
36773 TA01b
36773f
ꢀ
PushbuttonꢀInterfaceꢀOperation............................................................................................................................ 36
Step-DownꢀSwitchingꢀRegulatorꢀOperation
........................................................................................................... 28
LTC3677-3
Table oF conTenTs
Features............................................................................................................................ 1
Applications ....................................................................................................................... 1
Typical Application ............................................................................................................... 1
Description......................................................................................................................... 1
Absolute Maximum Ratings..................................................................................................... 3
Order Information................................................................................................................. 3
Pin Configuration ................................................................................................................. 3
Electrical Characteristics........................................................................................................ 4
Typical Performance Characteristics .........................................................................................10
Pin Functions.....................................................................................................................15
Block Diagram....................................................................................................................18
Operation..........................................................................................................................19
PowerPathꢀOPERATIONꢀ........................................................................................................................................ 19
LowꢀDropoutꢀLinearꢀRegulatorꢀOperationꢀ............................................................................................................. 27
2
I CꢀOperationꢀ........................................................................................................................................................ 32
LayoutꢀandꢀThermalꢀConsiderationsꢀ..................................................................................................................... 40
Typical Application ..............................................................................................................42
Package Description ............................................................................................................43
Typical Application ..............................................................................................................44
Related Parts.....................................................................................................................44
36773f
ꢁ
(Noteꢀ4)........................................... –0.3VꢀtoꢀV ꢀ+ꢀ0.3V
I
I
I
,ꢀI
,ꢀI ,ꢀContinuousꢀ(Noteꢀ16)
.....................2A
................................. 850mA
,ꢀContinuousꢀ(Noteꢀ16)
,ꢀI ,ꢀContinuousꢀ(Noteꢀ16)........................ 600mA
I
I
I
,ꢀI
,ꢀI
,ꢀI
,ꢀI
...................75mA
ꢀ tꢀ<ꢀ1msꢀandꢀDutyꢀCycleꢀ<ꢀ1%
................... –0.3Vꢀtoꢀ7V
LTC3677-3
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2, 3)
V
,ꢀV ,ꢀV ,ꢀV ,ꢀV
,ꢀV
,ꢀWALL
BUS OUTꢀ IN12 IN3 INLDO1 INLDO2
TOP VIEW
ꢀ SteadyꢀStateꢀ............................................ –0.3Vꢀtoꢀ6V
CHRG,ꢀBAT,ꢀPWR_ON,ꢀEXTPWR,ꢀPBSTAT,ꢀPGOOD,ꢀ
FB1,ꢀFB2,ꢀFB3,ꢀLDO1,ꢀLDO1_FB,ꢀLDO2,ꢀ
I
I
1
2
37 IDGATE
36 PROG
35 NTC
34 NTCBIAS
33 SW1
LIM0
LDO2_FB,ꢀDV ,ꢀSCL,ꢀSDA,ꢀEN3ꢀ................. –0.3Vꢀtoꢀ6V
CC
LIM1
NC 3
WALL 4
SW3 5
NTC,ꢀPROG,ꢀCLPROG,ꢀON,ꢀI
,ꢀI
ꢀ
LIM0 LIM1
CC
V
6
32 V
IN3
IN12
45
GND
VBUS VOUTꢀ BAT
FB3 7
OVSENS 8
NC 9
DV 10
SDA 11
SCL 12
OVGATE 13
PWR_ON 14
ON 15
31 SW2
30 V
INLD02
SW3
29 LDO2
28 LDO1
27 V
INLDO1
26 FB1
25 FB2
24 LDO2_FB
23 LDO1_FB
SW2 SW1
CC
I
,ꢀI
,ꢀContinuousꢀ(Noteꢀ16)ꢀ..................... 200mA
LDO1 LDO2
CHRG ACPR EXTPWR PBSTAT PGOOD
ꢀ..................................................................10mA
OVSENS
CLPROG PROG
OperatingꢀJunctionꢀTemperatureꢀRangeꢀ
,ꢀI
ꢀ.........................................................2mA
(Noteꢀ2)ꢀ...............................................–40°Cꢀtoꢀ85°C
MaximumꢀJunctionꢀTemperatureꢀ...........................110°C
StorageꢀTemperatureꢀRangeꢀ.................. –65°Cꢀtoꢀ125°C
UFF PACKAGE
44-LEAD (7mm s 4mm) PLASTIC QFN
ꢀ
T
ꢀ=ꢀ110°C,ꢀθ ꢀ=ꢀ45°C/W
JA
JMAX
EXPOSEDꢀPADꢀ(PINꢀ45)ꢀISꢀGND,ꢀMUSTꢀBEꢀSOLDEREDꢀTOꢀPCB
orDer inForMaTion
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3677EUFF-3#PBF
LTC3677EUFF-3#TRPBF
36773
–40°Cꢀtoꢀ85°C
44-Leadꢀ(4mmꢀ×ꢀ7mm)ꢀPlasticꢀQFN
ConsultꢀLTCꢀMarketingꢀforꢀpartsꢀspecifiedꢀwithꢀwiderꢀoperatingꢀtemperatureꢀranges.ꢀꢀ
ConsultꢀLTCꢀMarketingꢀforꢀinformationꢀonꢀnon-standardꢀleadꢀbasedꢀfinishꢀparts.
Forꢀmoreꢀinformationꢀonꢀleadꢀfreeꢀpartꢀmarking,ꢀgoꢀto:ꢀhttp://www.linear.com/leadfree/ꢀꢀ
Forꢀmoreꢀinformationꢀonꢀtapeꢀandꢀreelꢀspecifications,ꢀgoꢀto:ꢀhttp://www.linear.com/tapeandreel/
36773f
ꢂ
LTC3677-3
Power Manager. The l denotes the specifications which apply over the
elecTrical characTerisTics
full operating junction temperature range, otherwise specifications are at TJ = 25°C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = 5V,
WALL = 0V, VINLDO2 = VINLOD1 = VIN12 = VIN3 = VOUT, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Power Supply
V
InputꢀSupplyꢀVoltage
4.35
5.5
V
BUS
l
l
l
I
TotalꢀInputꢀCurrentꢀ(Noteꢀ5)
I
I
I
ꢀ=ꢀ5V,ꢀI
ꢀ=ꢀ0V,ꢀI
ꢀ=ꢀ0V,ꢀI
ꢀ=ꢀ5Vꢀ(1xꢀMode)ꢀ
ꢀ=ꢀ0Vꢀ(5xꢀMode)ꢀ
ꢀ=ꢀ5Vꢀ(10xꢀMode)
80ꢀ
450ꢀ
900
90ꢀꢀ
475ꢀ
950
100ꢀ
500ꢀ
1000
mAꢀ
mAꢀ
mA
BUS_LIM
LIM0
LIM0
LIM0
LIM1
LIM1
LIM1
I
InputꢀQuiescentꢀCurrent,ꢀPOFFꢀState
1x,ꢀ5x,ꢀ10xꢀModesꢀ
ꢀ=ꢀ5V,ꢀI ꢀ=ꢀ0Vꢀ(SuspendꢀMode)
0.42ꢀ
0.05
ꢀ
mAꢀ
mA
BUSQ
ꢀ
I
0.1
LIM0
LIM1
h
RatioꢀofꢀMeasuredꢀV ꢀCurrentꢀtoꢀ
1000
mA/mA
CLPROG
BUS
CLPROGꢀProgramꢀCurrent
V
CLPROGꢀServoꢀVoltageꢀinꢀCurrentꢀ
Limit
1xꢀModeꢀ
5xꢀModeꢀ
10xꢀMode
0.2ꢀ
1.0ꢀ
2.0
Vꢀ
Vꢀ
V
CLPROG
V
V
V
V
ꢀUndervoltageꢀLockout
RisingꢀThresholdꢀ
FallingꢀThreshold
ꢀ
3.8ꢀ
3.7
3.9
Vꢀ
V
UVLO
BUS
3.5
ꢀtoꢀV ꢀDifferentialꢀUndervoltageꢀ RisingꢀThresholdꢀ
BUS
ꢀ50ꢀ
–50
100
mVꢀ
mV
DUVLO
OUT
Lockout
FallingꢀThreshold
R
InputꢀCurrentꢀLimitꢀPowerꢀFETꢀꢀ
200
mΩ
ON_ILIM
On-Resistanceꢀ(BetweenꢀV ꢀandꢀV
)
BUS
OUT
Battery Charger
V
V
ꢀRegulatedꢀOutputꢀVoltage
BAT
LTC3677-3ꢀ
LTC3677-3,ꢀ0ꢀ≤ꢀTJꢀ≤ꢀ85°C
4.179ꢀ
4.165
4.200ꢀ
4.200
4.221ꢀ
4.235
Vꢀ
V
FLOAT
l
l
l
ICHG
Constant-CurrentꢀModeꢀChargeꢀCurrentꢀ R
ꢀ=ꢀ1k,ꢀInputꢀCurrentꢀLimitꢀ=ꢀ2Aꢀ
ꢀ=ꢀ2k,ꢀInputꢀCurrentꢀLimitꢀ=ꢀ1Aꢀ
ꢀ=ꢀ5k,ꢀInputꢀCurrentꢀLimitꢀ=ꢀ0.4A
950ꢀ
465ꢀ
180
1000ꢀ
500ꢀ
200
1050ꢀ
535ꢀ
220
mAꢀ
mAꢀ
mA
PROG
PROG
PROG
ICꢀNotꢀinꢀThermalꢀLimit
R
R
IBATQ_OFF
IBATQ_ON
Battery-DrainꢀCurrent,ꢀPOFFꢀState,ꢀ
Buck3ꢀDisabled,ꢀNoꢀLoadꢀ(Noteꢀ14)
V
V
ꢀ=ꢀ4.3V,ꢀChargerꢀTimeꢀOutꢀ
BUS
6ꢀ
27ꢀ
µAꢀ
µA
BAT
ꢀ=ꢀ0V
55
100
Battery-DrainꢀCurrent,ꢀPONꢀState,ꢀꢀ
Buck3ꢀEnabledꢀ(Notesꢀ10,ꢀ14)
V
ꢀ=ꢀ0V,ꢀI ꢀ=ꢀ0µA,ꢀNoꢀLoadꢀOnꢀ
130
200
µA
BUS
OUT
Supplies,ꢀBurstꢀMode®ꢀOperation
V
V
PROGꢀPinꢀServoꢀVoltage
V
V
ꢀ>ꢀV
ꢀ<ꢀV
1.000
0.100
V
V
PROG,CHG
PROG,TRKL
BAT
BAT
TRKL
TRKL
PROGꢀPinꢀServoꢀVoltageꢀinꢀTrickleꢀ
Charge
h
RatioꢀofꢀI ꢀtoꢀPROGꢀPinꢀCurrent
BAT
1000
50
mA/mA
mA
PROG
I
TrickleꢀChargeꢀCurrent
V
ꢀ<ꢀV
40
60
TRKL
BAT
TRKL
V
TrickleꢀChargeꢀRisingꢀThresholdꢀꢀ
TrickleꢀChargeꢀFallingꢀThreshold
V
V
ꢀRisingꢀ
ꢀFalling
ꢀ
2.9ꢀ
2.75
3.0
Vꢀ
V
TRKL
BAT
BAT
2.5
∆V
RechargeꢀBatteryꢀThresholdꢀVoltage
SafetyꢀTimerꢀTerminationꢀPeriod
BadꢀBatteryꢀTerminationꢀTime
ThresholdꢀVoltageꢀRelativeꢀtoꢀV
–75
3.2
–100
4
–125
4.8
mV
Hour
RECHRG
FLOAT
t
t
TimerꢀStartsꢀwhenꢀV ꢀ=ꢀV
ꢀ–ꢀ50mV
TERM
BADBAT
BAT
FLOAT
V
ꢀ<ꢀV
0.4
0.5
0.1
200
0.6
Hour
BAT
TRKL
h
End-of-ChargeꢀIndicationꢀCurrentꢀRatio (Noteꢀ6)
0.085
0.11
mA/mA
mΩ
C/10
R
BatteryꢀChargerꢀPowerꢀFETꢀꢀ
ON_CHG
On-Resistanceꢀ(BetweenꢀV ꢀandꢀBAT)
OUT
T
JunctionꢀTemperatureꢀinꢀConstant-
TemperatureꢀMode
110
°C
LIM
36773f
ꢃ
LTC3677-3
elecTrical characTerisTics Power Manager. The l denotes the specifications which apply over the
full operating junction temperature range, otherwise specifications are at TJ = 25°C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = 5V,
WALL = 0V, VINLDO2 = VINLOD1 = VIN12 = VIN3 = VOUT, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NTC, Battery Discharge Protection
V
V
ColdꢀTemperatureꢀFaultꢀThresholdꢀ
Voltage
RisingꢀNTCꢀVoltageꢀ
Hysteresis
75
34
76ꢀ
1.3
77
36
%V
%V
ꢀ
ꢀ
ꢀ
COLD
HOT
NTCBIAS
NTCBIAS
HotꢀTemperatureꢀFaultꢀThresholdꢀ
Voltage
FallingꢀNTCꢀVoltageꢀ
Hysteresis
35ꢀ
1.3
%V
%V
NTCBIAS
NTCBIAS
V
_
NTCꢀDischargeꢀThresholdꢀVoltage
FallingꢀNTCꢀVoltageꢀ
Hysteresis
24.5
–50
25.5ꢀ
50
26.5
50
%V
TOO HOT
NTCBIAS
mV
I
I
NTCꢀLeakageꢀCurrent
BATꢀDischargeꢀCurrent
BATꢀDischargeꢀThreshold
V
V
ꢀ=ꢀV ꢀ=ꢀ5V
nA
mA
V
NTC
NTC
BUS
ꢀ=ꢀ4.1V,ꢀNTCꢀ<ꢀV
TOO_HOT
170
3.9
BAT2HOT
BAT
V
I
ꢀ<ꢀ0.1mA,ꢀNTCꢀ<ꢀV
BAT TOO_HOT
BAT2HOT
Ideal Diode
V
ForwardꢀVoltageꢀDetection
DiodeꢀOn-Resistance,ꢀDropout
DiodeꢀCurrentꢀLimit
I
I
ꢀ=ꢀ10mA
5
15
200
3.6
25
mV
mΩ
A
FWD
OUT
R
ꢀ=ꢀ200mA
OUT
DROPOUT
MAX
I
(Noteꢀ7)
Overvoltage Protection
V
V
OvervoltageꢀProtectionꢀThreshold
OVGATEꢀOutputꢀVoltageꢀ
RisingꢀThreshold,ꢀR
ꢀ=ꢀ6.2k
OVSENS
6.10
6.35
6.70
12ꢀ
V
OVCUTOFF
OVGATE
InputꢀBelowꢀV
InputꢀAboveꢀV
ꢀ
1.88ꢀ•ꢀV
0
Vꢀ
V
OVCUTOFFꢀ
OVCUTOFF
OVSENSꢀ
I
t
OVSENSꢀQuiescentꢀCurrent
V
C
ꢀ=ꢀ5V
40
µA
ms
OVSENSQ
RISE
OVSENS
OVGATE
OVGATEꢀTimeꢀtoꢀReachꢀRegulation
ꢀ=ꢀ1nF
2.5
Wall Adapter and High Voltage Buck Output Control
V
ACPRꢀPinꢀOutputꢀHighꢀVoltageꢀ
ACPRꢀPinꢀOutputꢀLowꢀVoltage
I
I
ꢀ=ꢀ0.1mAꢀ
ACPR
ꢀ=ꢀ1mA
ACPR
V –ꢀ0.3ꢀ
OUTꢀ
V
ꢀ
ꢀ
Vꢀ
V
ACPR
OUT
0
0.3
V
W
AbsoluteꢀWallꢀInputꢀThresholdꢀVoltage
V
WALL
ꢀRisingꢀ
ꢀFalling
ꢀ
4.3ꢀ
3.2
4.45
Vꢀ
V
WALL
V
3.1
DifferentialꢀWallꢀInputꢀThresholdꢀ
Voltage
V
WALL
ꢀ–ꢀV ꢀFallingꢀ
0
25ꢀ
75
ꢀ
mVꢀ
mV
∆V
W
WALL
BAT
V
ꢀ–ꢀV ꢀRising
100
BAT
I
WallꢀOperatingꢀQuiescentꢀCurrent
I
ꢀ+ꢀI ,ꢀI ꢀ=ꢀ0mA,ꢀꢀ
VOUTꢀ BAT
440
µA
QWALL
WALL
WALLꢀ=ꢀV ꢀ=ꢀ5V
OUT
Logic (I
, I
and CHRG)
LIM0 LIM1
V
V
InputꢀLowꢀVoltage
I
I
I
I
,ꢀI
0.4
V
V
IL
IH
LIM0 LIM1
InputꢀHighꢀVoltage
,ꢀI
1.2
LIM0 LIM1
I
StaticꢀPull-DownꢀCurrent
CHRGꢀPinꢀOutputꢀLowꢀVoltage
CHRGꢀPinꢀInputꢀCurrent
,ꢀI ;ꢀV ꢀ=ꢀ1V
LIM0 LIM1 PIN
2
0.15
0
µA
V
PD
V
ꢀ=ꢀ10mA
CHRG
0.4
1
CHRG
CHRG
I
V
ꢀ=ꢀ4.5V,ꢀV
ꢀ=ꢀ5V
CHRG
µA
BAT
36773f
ꢄ
LTC3677-3
2
I C Interface. The l denotes the specifications which apply over the full
elecTrical characTerisTics
operating junction temperature range, otherwise specifications are at TJ = 25°C. DVCC = 3.3V, VOUT = 3.8V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DV
CC
InputꢀSupplyꢀVoltage
1.6
5.5
V
I
DV ꢀSupplyꢀCurrent
CC
SCLꢀ=ꢀ400kHzꢀ
SCLꢀ=ꢀSDAꢀ=ꢀ0kHz
10ꢀ
1
µAꢀ
µA
DVCC
V
V
V
DV ꢀUVLO
1.0
50
50
V
DVCC,UVLO
CC
InputꢀHighꢀVoltage
70
%DV
%DV
IH
IL
CC
CC
InputꢀLowꢀVoltage
30
–1
–1
I
I
InputꢀHighꢀLeakageꢀCurrent
InputꢀLowꢀLeakageꢀCurrent
SDAꢀOutputꢀLowꢀVoltage
SDAꢀ=ꢀSCLꢀ=ꢀDV ꢀ=ꢀ5.5V
1
1
µA
µA
V
IH
IL
CC
SDAꢀ=ꢀSCLꢀ=ꢀ0V,ꢀDV ꢀ=ꢀ5.5V
CC
V
I ꢀ=ꢀ3mA
SDA
0.4
OL
Timing Characteristics (Note 8) (All Values Are Referenced to V and V )
IH
IL
f
t
t
t
t
t
t
t
t
t
t
SCLꢀClockꢀFrequency
400
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
SCL
LowꢀPeriodꢀofꢀtheꢀSCLꢀClock
HighꢀPeriodꢀofꢀtheꢀSCLꢀClock
BusꢀFreeꢀTimeꢀBetweenꢀStopꢀandꢀStartꢀCondition
HoldꢀTimeꢀAfterꢀ(Repeated)ꢀStartꢀCondition
Set-UpꢀTimeꢀforꢀaꢀRepeatedꢀStartꢀCondition
StopꢀConditionꢀSet-UpꢀTime
1.3
0.6
1.3
0.6
0.6
0.6
0
LOW
HIGH
BUF
HD,STA
SU,STA
SU,STO
HD,DATO
HD,DATI
SU,DAT
SP
OutputꢀDataꢀHoldꢀTimeꢀ
900
50
InputꢀDataꢀHoldꢀTime
0
DataꢀSet-UpꢀTime
100
InputꢀSpikeꢀSuppressionꢀPulseꢀWidth
36773f
ꢅ
LTC3677-3
elecTrical characTerisTics Step-Down Switching Regulators. The l denotes the specifications
which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VOUT = VIN12 = VIN3 = 3.8V,
all regulators enabled unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Step-Down Switching Regulators (Buck1, Buck2 and Buck3)
l
V
V
,ꢀV
InputꢀSupplyꢀVoltage
(Noteꢀ9)
ꢀandꢀV ꢀConnectedꢀtoꢀV ꢀThroughꢀ
2.7
2.5
5.5
V
IN12 IN3
ꢀUVLO
V
V
ꢀFallingꢀ
OUT
ꢀRising
OUT
V
2.7ꢀ
2.8
ꢀ
Vꢀ
V
OUT
IN12
IN3
OUT
LowꢀImpedance.ꢀSwitchingꢀRegulatorsꢀAreꢀ
2.9
DisabledꢀBelowꢀV ꢀUVLO
OUT
f
OscillatorꢀFrequency
ꢀ
1.91
2.25
2.59
MHz
OSC
800mA Step-Down Switching Regulator 3 (Buck3-Enabled via EN3, Disabled in PDN and POFF States)
I
Pulse-SkippingꢀModeꢀInputꢀCurrentꢀ
BurstꢀModeꢀOperationꢀInputꢀCurrent
ShutdownꢀInputꢀCurrent
(Noteꢀ10)
(Noteꢀ10)
EN3ꢀ=ꢀ0
100
20
µA
µA
VIN3Q
35
1
0.01
1400
µA
I
PeakꢀP-ChannelꢀMOSFETꢀCurrentꢀLimit
FeedbackꢀVoltage
(Noteꢀ7)
1000
1700
mA
LIM3
l
l
V
Pulse-SkippingꢀModeꢀ
BurstꢀModeꢀOperation
0.78ꢀ
0.78
0.8ꢀ
0.8
0.82ꢀ
0.824
Vꢀ
FB3
V
µA
%
Ω
I
FB3ꢀInputꢀCurrent
MaxꢀDutyꢀCycle
(Noteꢀ10)
FB3ꢀ=ꢀ0V
–0.05
100
0.05
FB3
D3
R
R
R
R
R
ꢀofꢀP-ChannelꢀMOSFET
ꢀofꢀN-ChannelꢀMOSFET
0.3
0.4
10
P3
DS(ON)
Ω
N3
DS(ON)
SW3ꢀPull-DownꢀinꢀShutdown
EN3ꢀInputꢀLowꢀVoltage
EN3ꢀInputꢀHighꢀVoltage
EN3ꢀ=ꢀ0
ꢀ
kΩ
V
SW3_PD
IL,EN3
IH,EN3
V
V
0.4
1.2
V
500mA Step-Down Switching Regulator 2 (Buck2-Pushbutton Enabled, Third in Sequence)
I
Pulse-SkippingꢀModeꢀInputꢀCurrentꢀ
BurstꢀModeꢀOperationꢀInputꢀCurrent
ShutdownꢀInputꢀCurrent
(Noteꢀ10)
(Noteꢀ10)
POFFꢀState
(Noteꢀ7)
100
20
µA
µA
VIN12Q
0.01
900
1
µA
I
PeakꢀP-ChannelꢀMOSFETꢀCurrentꢀLimit
FeedbackꢀVoltage
650
1200
mA
LIM2
l
l
V
Pulse-SkippingꢀModeꢀ
BurstꢀModeꢀOperation
0.78ꢀ
0.78
0.8ꢀ
0.8
0.82ꢀ
0.824
Vꢀ
FB2
V
µA
%
I
FB2ꢀInputꢀCurrent
MaxꢀDutyꢀCycle
(Noteꢀ10)
FB2ꢀ=ꢀ0V
–0.05
100
0.05
FB2
D2
R
R
R
R
R
ꢀofꢀP-ChannelꢀMOSFET
ꢀofꢀN-ChannelꢀMOSFET
I
I
ꢀ=ꢀ100mAꢀ
ꢀ=ꢀ–100mA
0.6
0.6
10
Ω
P2
DS(ON)
SW2
SW2
Ω
N2
DS(ON)
SW2ꢀPull-DownꢀinꢀShutdown
POFFꢀState
kΩ
SW2_PD
500mA Step-Down Switching Regulator 1 (Buck1-Pushbutton Enabled, Second in Sequence)
I
Pulse-SkippingꢀModeꢀInputꢀCurrentꢀ
BurstꢀModeꢀOperationꢀInputꢀCurrent
ShutdownꢀInputꢀCurrent
(Noteꢀ10)
(Noteꢀ10)
100
20
µA
µA
VIN12Q
0.01
900
1
µA
I
PeakꢀP-ChannelꢀMOSFETꢀCurrentꢀLimit
FeedbackꢀVoltage
(Noteꢀ7)
650
1200
mA
LIM1
l
l
V
Pulse-SkippingꢀModeꢀ
BurstꢀModeꢀOperation
0.78ꢀ
0.78
0.8ꢀ
0.8
0.82ꢀ
0.824
Vꢀ
V
FB1
I
FB1ꢀInputꢀCurrent
MaxꢀDutyꢀCycle
(Noteꢀ10)
FB1ꢀ=ꢀ0V
–0.05
100
0.05
µA
FB1
D1
%
R
R
R
R
R
ꢀofꢀP-ChannelꢀMOSFET
ꢀofꢀN-ChannelꢀMOSFET
I
I
ꢀ=ꢀ100mAꢀ
ꢀ=ꢀ–100mA
0.6
0.6
10
Ω
P1
DS(ON)
SW1
SW1
Ω
N1
DS(ON)
SW1ꢀPull-DownꢀinꢀShutdown
POFFꢀState
kΩ
36773f
SW1_PD
ꢆ
LTC3677-3
elecTrical characTerisTics LDO Regulators. The l denotes the specifications which apply over the
full operating junction temperature range, otherwise specifications are at TJ = 25°C. VINLDO1 = VINLDO2 = VOUT = 3.8V, LDO1 and LDO2
enabled unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LDO Regulator 1 (LDO1-Always On)
l
l
V
V
InputꢀVoltageꢀRange
V
ꢀ≤ꢀV ꢀ+ꢀ0.3V
1.65
2.5
5.5
V
INLDO1
INLDO1
OUT
V
V
ꢀFallingꢀ
OUT
ꢀRising
OUT
LDO1ꢀIsꢀDisabledꢀBelowꢀV UVLO
OUTꢀ
2.7ꢀ
2.8
ꢀ
Vꢀ
V
OUT_UVLO
2.9
V
LDO1_FBꢀRegulatedꢀFeedbackꢀVoltage
LDO1_FBꢀLineꢀRegulationꢀ(Noteꢀ11)
LDO1_FBꢀLoadꢀRegulationꢀ(Noteꢀ11)
AvailableꢀOutputꢀCurrent
I
I
I
ꢀ=ꢀ1mA
0.78
0.8
0.4
5
0.82
V
LDO1_FB
LDO1
LDO1
LDO1
ꢀ=ꢀ1mA,ꢀV ꢀ=ꢀ1.65Vꢀtoꢀ5.5V
mV/V
µV/mA
mA
IN
ꢀ=ꢀ1mAꢀtoꢀ150mA
l
I
I
150
LDO1_OC
LDO1_SC
Short-CircuitꢀOutputꢀCurrentꢀ(Noteꢀ7)
DropoutꢀVoltageꢀ(Noteꢀ12)
270
mA
V
I
I
I
ꢀ=ꢀ150mA,ꢀV
ꢀ=ꢀ150mA,ꢀV
ꢀ=ꢀ3.6Vꢀ
ꢀ=ꢀ2.5Vꢀ
160ꢀ
200ꢀ
170
260ꢀ
320ꢀ
280
mVꢀ
mVꢀ
mV
DROP1
LDO1
LDO1
LDO1
INLDO1
INLDO1
ꢀ=ꢀ75mA,ꢀV
ꢀ=ꢀ1.8V
INLDO1
R
OutputꢀPull-DownꢀResistanceꢀinꢀShutdown LDO1ꢀDisabled
LDO_FB1ꢀInputꢀCurrent
10
kΩ
nA
LDO1_PD
I
–50
50
LDO_FB1
LDO Regulator 2 (LDO2-Pushbutton Enabled, First in Sequence)
l
l
V
V
InputꢀVoltageꢀRange
V
ꢀ≤ꢀV ꢀ+ꢀ0.3V
1.65
2.5
5.5
V
INLDO2
INLDO2
OUT
V
V
ꢀFallingꢀ
OUT
ꢀRising
OUT
LDO2ꢀisꢀDisabledꢀBelowꢀV UVLO
OUTꢀ
2.7ꢀ
2.8
ꢀ
Vꢀ
V
OUT_UVLO
2.9
V
LDO2_FBꢀRegulatedꢀOutputꢀVoltage
LDO2_FBꢀLineꢀRegulationꢀ(Noteꢀ11)
LDO2_FBꢀLoadꢀRegulationꢀ(Noteꢀ11)
AvailableꢀOutputꢀCurrent
I
I
I
ꢀ=ꢀ1mA
0.78
0.8
0.4
5
0.82
V
mV/V
µV/mA
mA
LDO2_FB
LDO2
LDO2
LDO2
ꢀ=ꢀ1mA,ꢀV ꢀ=ꢀ1.65Vꢀtoꢀ5.5V
IN
ꢀ=ꢀ1mAꢀtoꢀ150mA
l
I
I
150
LDO2_OC
LDO2_SC
Short-CircuitꢀOutputꢀCurrentꢀ(Noteꢀ7)
DropoutꢀVoltageꢀ(Noteꢀ12)
270
mA
V
I
I
I
ꢀ=ꢀ150mA,ꢀV
ꢀ=ꢀ150mA,ꢀV
ꢀ=ꢀ3.6Vꢀ
ꢀ=ꢀ2.5Vꢀ
160ꢀ
200ꢀ
170
260ꢀ
320ꢀ
280
mVꢀ
mVꢀ
mV
DROP2
LDO2
LDO2
LDO1
INLDO2
INLDO2
ꢀ=ꢀ75mA,ꢀV
ꢀ=ꢀ1.8V
INLDO1
R
OutputꢀPull-DownꢀResistanceꢀinꢀShutdown LDO2ꢀDisabled
LDO_FB2ꢀInputꢀCurrent
14
kΩ
nA
LDO2_PD
I
–50
50
LDO_FB2
36773f
ꢇ
LTC3677-3
elecTrical characTerisTics Pushbutton Controller. The l denotes the specifications which apply
over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VOUT = 3.8V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Pushbutton Pin (ON)
l
V
V
PushbuttonꢀOperatingꢀSupplyꢀRange
(Noteꢀ9)
2.7
2.5
5.5
V
OUT
OUT
ꢀUVLO
V
V
ꢀFallingꢀ
OUT
ꢀRising
OUT
PushbuttonꢀisꢀDisabledꢀBelowꢀV ꢀUVLO
2.7ꢀ
2.8
ꢀ
Vꢀ
V
OUT
2.9
V
ONꢀThresholdꢀRisingꢀ
ONꢀThresholdꢀFalling
ꢀ
0.8ꢀ
0.7
1.2
Vꢀ
V
ON_TH
0.4
I
ONꢀInputꢀCurrent
V
V
ꢀ=ꢀV
ꢀ
–1ꢀ
–4
ꢀ
–9
ꢀ1ꢀ
–14
μAꢀ
μA
ON
ON
ON
OUT
ꢀ=ꢀ0V
Power-On Input Pin (PWR_ON)
V
PWR_ONꢀThresholdꢀRisingꢀ
PWR_ONꢀThresholdꢀFalling
ꢀ
0.8ꢀ
0.7
1.2
1
Vꢀ
V
PWR_ON
0.4
I
PWR_ONꢀInputꢀCurrent
V
V
ꢀ=ꢀ3V
–1
μA
PWR_ON
PWR_ON
Status Output Pins (PBSTAT, EXTPWR, PGOOD)
I
PBSTATꢀOutputꢀHighꢀLeakageꢀCurrent
PBSTATꢀOutputꢀLowꢀVoltage
EXTPWRꢀPinꢀInputꢀCurrent
ꢀ=ꢀ3V
PBSTAT
–1
1
0.4
1
μA
V
PBSTAT
V
I
ꢀ=ꢀ3mA
PBSTAT
0.1
0
PBSTAT
I
V
ꢀ=ꢀ3V
EXTPWR
μA
V
EXTPWR
V
EXTPWRꢀPinꢀOutputꢀLowꢀVoltage
PGOODꢀOutputꢀHighꢀLeakageꢀCurrent
PGOODꢀOutputꢀLowꢀVoltage
I
ꢀ=ꢀ2mA
ꢀ=ꢀ3V
PGOOD
0.15
0.4
1
EXTPWR
EXTPWR
I
V
–1
μA
V
PGOOD
V
I
ꢀ=ꢀ3mA
PGOOD
0.1
–8
0.4
PGOOD
V
PGOODꢀThresholdꢀVoltage
(Noteꢀ13)
%
THPGOOD
Pushbutton Timing Parameters
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ONꢀLowꢀTimeꢀtoꢀPBSTATꢀLowꢀ
ONꢀHighꢀtoꢀPBSTATꢀHigh
50
900
50
50
14
1.8
1
ms
μs
ON_PBSTAT1
ON_PBSTAT2
PBSTAT_PW
ON_PUP
PBSTATꢀLowꢀ>ꢀt
PBSTAT_PW
PBSTATꢀMinimumꢀPulseꢀWidth
ONꢀLowꢀTimeꢀforꢀPower-Up
40
12
ms
ms
ONꢀLowꢀtoꢀPGOODꢀResetꢀLow
PGOODꢀResetꢀLowꢀPulseꢀWidth
MinimumꢀTimeꢀfromꢀPowerꢀUpꢀtoꢀDown
MinimumꢀTimeꢀfromꢀPowerꢀDownꢀtoꢀUp
PWR_ONꢀHighꢀtoꢀPower-Up
16.5
Seconds
ms
ON_RST
ON_RST_PW
PUP_PDN
Seconds
Seconds
ms
1
PDN_PUP
50
50
1
PWR_ONH
PWR_ONL
PWR_ONBK1
PWR_ONBK2
PGOODH
PWR_ONꢀLowꢀtoꢀPower-Down
PWR_ONꢀPower-UpꢀBlanking
PWR_ONꢀPower-DownꢀBlanking
FromꢀRegulationꢀtoꢀPGOODꢀHigh
BucksꢀDisabledꢀtoꢀPGOODꢀLow
LDO2ꢀEnableꢀtoꢀBuckꢀꢀEnable
ms
PWR_ONꢀLowꢀRecognizedꢀfromꢀPower-Up
PWR_ONꢀHighꢀRecognizedꢀfromꢀPower-Down
Buck1,ꢀ2ꢀandꢀLDO1ꢀWithinꢀPGOODꢀThreshold
BucksꢀDisabled
Seconds
Seconds
ms
1
230
44
14.5
µs
PGOODL
12.5
17.5
ms
LDO2_BK1
Note 1:ꢀStressesꢀbeyondꢀthoseꢀlistedꢀunderꢀAbsoluteꢀMaximumꢀRatingsꢀ
mayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀExposureꢀtoꢀanyꢀAbsoluteꢀ
MaximumꢀRatingꢀconditionꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀdeviceꢀ
reliabilityꢀandꢀlifetime.
Note 2:ꢀTheꢀLTC3677-3ꢀisꢀguaranteedꢀtoꢀmeetꢀperformanceꢀspecificationsꢀ
fromꢀ0°Cꢀtoꢀ85°C.ꢀSpecificationsꢀoverꢀtheꢀ–40°Cꢀtoꢀ85°Cꢀoperatingꢀ
junctionꢀtemperatureꢀrangeꢀareꢀassuredꢀbyꢀdesign,ꢀcharacterizationꢀandꢀ
correlationꢀwithꢀstatisticalꢀprocessꢀcontrols.ꢀNoteꢀthatꢀtheꢀmaximumꢀ
ambientꢀtemperatureꢀisꢀdeterminedꢀbyꢀspecificꢀoperatingꢀconditionsꢀinꢀ
conjunctionꢀwithꢀboardꢀlayout,ꢀtheꢀratedꢀpackageꢀthermalꢀresistanceꢀandꢀ
otherꢀenvironmentalꢀfactors.
Note 3:ꢀThisꢀICꢀincludesꢀoverꢀtemperatureꢀprotectionꢀthatꢀisꢀintendedꢀ
toꢀprotectꢀtheꢀdeviceꢀduringꢀmomentaryꢀoverloadꢀconditions.ꢀJunctionꢀ
temperaturesꢀwillꢀexceedꢀ110°Cꢀwhenꢀoverꢀtemperatureꢀprotectionꢀisꢀ
active.ꢀContinuousꢀoperationꢀaboveꢀtheꢀspecifiedꢀmaximumꢀoperatingꢀ
junctionꢀtemperatureꢀmayꢀresultꢀinꢀdeviceꢀdegradationꢀorꢀfailure.
36773f
ꢈ
LTC3677-3
elecTrical characTerisTics
Note 4:ꢀV ꢀisꢀtheꢀgreaterꢀofꢀV ,ꢀV ꢀorꢀBAT.
Note 11:ꢀMeasuredꢀwithꢀtheꢀLDOꢀrunningꢀunityꢀgainꢀwithꢀoutputꢀtiedꢀtoꢀ
CC
BUS OUT
feedbackꢀpin.
Note 5:ꢀTotalꢀinputꢀcurrentꢀisꢀtheꢀsumꢀofꢀquiescentꢀcurrent,ꢀI
,ꢀandꢀ
BUSQ
measuredꢀcurrentꢀgivenꢀbyꢀV
/R
ꢀ•ꢀ(h
ꢀ+ꢀ1).
Note 12:ꢀDropoutꢀvoltageꢀisꢀtheꢀminimumꢀinputꢀtoꢀoutputꢀvoltageꢀ
differentialꢀneededꢀforꢀanꢀLDOꢀtoꢀmaintainꢀregulationꢀatꢀaꢀspecifiedꢀoutputꢀ
current.ꢀWhenꢀanꢀLDOꢀisꢀinꢀdropout,ꢀitsꢀoutputꢀvoltageꢀwillꢀbeꢀequalꢀtoꢀꢀ
CLPROG CLPROG
CLPROG
Note 6:ꢀh ꢀisꢀexpressedꢀasꢀaꢀfractionꢀofꢀmeasuredꢀfullꢀchargeꢀcurrentꢀ
C/10
withꢀindicatedꢀPROGꢀresistor.
V ꢀ–ꢀV
.
IN
DROPꢀ
Note 7:ꢀTheꢀcurrentꢀlimitꢀfeaturesꢀofꢀthisꢀpartꢀareꢀintendedꢀtoꢀprotectꢀtheꢀ
ICꢀfromꢀshortꢀtermꢀorꢀintermittentꢀfaultꢀconditions.ꢀContinuousꢀoperationꢀ
aboveꢀtheꢀmaximumꢀspecifiedꢀpinꢀcurrentꢀratingꢀmayꢀresultꢀinꢀdeviceꢀ
degradationꢀorꢀfailure.
Note 13:ꢀPGOODꢀthresholdꢀisꢀexpressedꢀasꢀaꢀpercentageꢀdifferenceꢀ
fromꢀtheꢀBuck1,ꢀBuck2ꢀandꢀLDO1ꢀregulationꢀvoltages.ꢀTheꢀthresholdꢀisꢀ
measuredꢀfromꢀBuck1,ꢀBuck2ꢀandꢀLDO1ꢀoutputꢀrising.
Note 8:ꢀTheꢀserialꢀportꢀisꢀtestedꢀatꢀratedꢀoperatingꢀfrequency.ꢀTimingꢀ
parametersꢀareꢀtestedꢀand/orꢀguaranteedꢀbyꢀdesign.
Note 14:ꢀTheꢀI
ꢀspecificationsꢀrepresentꢀtheꢀtotalꢀbatteryꢀloadꢀassumingꢀ
BATQ
V
,ꢀV
,ꢀV
ꢀandꢀV ꢀareꢀtiedꢀdirectlyꢀtoꢀV
.
INLDO1 INLDO2 IN12
IN3
OUTꢀ
Note 9:ꢀV ꢀnotꢀinꢀUVLO.
Note 15:ꢀLong-termꢀcurrentꢀdensityꢀratingꢀforꢀtheꢀpart.
OUT
Note 10:ꢀBuckꢀFBꢀhigh,ꢀnotꢀswitching.
Typical perForMance characTerisTics TJ = 25°C unless otherwise specified
Input Supply Current
vs Temperature
Input Supply Current
Battery-Drain Current
vs Temperature
vs Temperature (Suspend Mode)
0.10
0.08
0.06
0.04
0.02
0
450
400
350
300
250
200
150
100
50
0.8
ALL SUPPLIES ENABLED
PULSE-SKIPPING MODE
V
= 5V
V
= 5V
BUS
BUS
1x MODE
0.7
0.6
NO LOAD ON
ALL SUPPLIES
V
BAT
V
BUS
= 3.8V
= 0V
0.5
0.4
0.3
0.2
0.1
ALL SUPPLIES ENABLED
Burst Mode OPERATION
ALL SUPPLIES DISABLED EXCEPT LDO1
25 75 100 125
50
TEMPERATURE (°C)
0
0
–25
0
50
TEMPERATURE (°C)
75 100 125
–50 –25
0
25
TEMPERATURE (°C)
50
75
125
–50
0
–50
25
100
–25
36773 G03
36773 G02
36773 G01
36773f
ꢀ0
LTC3677-3
Typical perForMance characTerisTics TJ = 25°C unless otherwise specified
Input Current Limit
vs Temperature
Charge Current vs Temperature
(Thermal Regulation)
Input RON vs Temperature
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
600
500
400
300
300
280
260
240
220
180
160
140
120
100
0
V
R
= 5V
CLPROG
I
= 400mA
BUS
OUT
= 2.1k
10x MODE
5x MODE
V
= 4.5V
BUS
V
BUS
= 5V
V
BUS
= 5.5V
200
100
0
V
= 5V
BUS
1x MODE
10x MODE
= 2k
R
PROG
50
75 100 125
–50 –25
25
50
TEMPERATURE (°C)
75
100 125
–50
0
25
0
–25
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
36773 G04
357734 G06
36773 G05
Battery Current and Voltage
vs Time
Battery Regulation (Float)
Voltage vs Temperature
Battery Float Voltage
Load Regulation
600
500
400
300
200
100
0
6
4.24
4.22
4.24
4.22
4.20
4.18
4.16
4.14
4.12
4.10
4.08
4.06
4.04
V
= 5V
I
= 2mA
BUS
BAT
10x MODE
CHRG
5
4
3
2
1
0
V
BAT
4.20
4.18
4.16
4.14
4.12
4.10
SAFETY
TIMER
TERMINATION
1450mAhr
CELL
C/10
V
= 5V
BUS
PROG
R
R
= 2k
= 2k
I
BAT
CLPROG
0
2
3
4
5
6
0
200
400
I
600
(mA)
800
1000
1
–50 –25
0
25
50
75 100 125
TIME (HOUR)
TEMPERATURE (°C)
BAT
36773 G07
357734 G08
36773 G09
Forward Voltage vs Ideal Diode
Current (No External FET)
Forward Voltage vs Ideal Diode
Current (with Si2333DS External FET)
IBAT vs VBAT
600
500
400
300
200
100
0
0.25
0.20
0.15
0.10
40
35
30
25
V
T
= 0V
V
V
A
= 3.8V
= 0V
BUS
A
BAT
BUS
= 25°C
= 25°C
V
= 3.2V
BAT
T
V
= 3.6V
BAT
V
BAT
= 4.2V
RISING
BAT
V
20
15
FALLING
V
BAT
10
5
V
= 5V
BUS
10x MODE
0.05
0
R
R
= 2k
= 2k
PROG
CLPROG
0
2.0
2.8
3.2
(V)
3.6
4.0
4.4
2.4
0
0.4
0.6
(A)
0.8
1.0
1.2
0
0.2
0.4
I
0.8
1.0
0.2
0.6
(A)
V
I
BAT
BAT
BAT
36773 G10
36773 G11
36773 G12
36773f
ꢀꢀ
LTC3677-3
Typical perForMance characTerisTics TJ = 25°C unless otherwise specified
Input Disconnect Waveform
Input Connect Waveform
Switching from 1x to 5x Mode
V
V
BUS
BUS
5V/DIV
5V/DIV
I
/I
LIM0 LIM1
V
5V/DIV
OUT
V
OUT
5V/DIV
5V/DIV
I
I
I
BUS
BUS
BUS
0.5A/DIV
0.5A/DIV
0.5A/DIV
I
I
I
BAT
BAT
BAT
0.5A/DIV
0.5A/DIV
0.5A/DIV
36773 G14
36773 G15
36773 G13
V
I
= 3.75V
= 100mA
= 2k
1ms/DIV
V
I
= 3.75V
= 50mA
= 2k
1ms/DIV
V
I
= 3.75V
= 100mA
= 2k
1ms/DIV
BAT
OUT
R
CLPROG
R
= 2k
R
= 2k
R
= 2k
PROG
PROG
PROG
Switching from Suspend Mode
to 5x Mode
WALL Connect Waveform
WALL Disconnect Waveform
WALL
5V/DIV
I
WALL
5V/DIV
LIM0
5V/DIV
V
V
V
OUT
OUT
OUT
5V/DIV
5V/DIV
5V/DIV
I
I
WALL
I
WALL
BUS
0.5A/DIV
0.5A/DIV
0.5A/DIV
I
I
I
BAT
BAT
BAT
0.5A/DIV
0.5A/DIV
0.5A/DIV
36773 G17
36773 G16
36773 G18
V
I
= 3.75V
= 100mA
= 2k
1ms/DIV
V
I
= 3.75V
= 100mA
= 2k
100µs/DIV
V
I
= 3.75V
= 100mA
= 2k
1ms/DIV
BAT
BAT
OUT
BAT
OUT
OUT
R
PROG
R
R
PROG
CLPROG
R
= 2k
PROG
I
= 5V
LIM1
Oscillator Frequency
vs Temperature
Step-Down Switching Regulator 1
3.3V Output Efficiency vs IOUT1
100
90
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
Burst Mode
OPERATION
80
70
PULSE-SKIPPING
60
50
V
= 5V
OUT
40
30
20
10
0
V
= 3.8V
OUT
V
= 3.3V
OUT1
V
V
= 3.8V
= 5V
IN12
IN12
–50
0
25
50
75 100 125
–25
0.01
0.1
1
10
(mA)
100
1000
TEMPERATURE (°C)
I
OUT
36773 G19
36773 G20
36773f
ꢀꢁ
LTC3677-3
Typical perForMance characTerisTics TJ = 25°C unless otherwise specified
Step-Down Switching Regulator 3
1.2V Output Efficiency vs IOUT3
Step-Down Switching Regulator 2
1.8V Output Efficiency vs IOUT2
Step-Down Switching Regulator 3
2.5V Output Efficiency
100
90
100
90
100
90
Burst Mode
OPERATION
Burst Mode
OPERATION
Burst Mode
OPERATION
80
80
80
70
70
70
PULSE-SKIPPING
PULSE-SKIPPING
60
50
60
50
60
50
PULSE-SKIPPING
40
30
20
10
0
40
30
20
10
0
40
30
20
10
0
V
= 1.2V
= 3.8V
= 5V
V
= 2.5V
= 3.8V
= 5V
OUT3
OUT3
V
= 1.8V
OUT2
V
V
V
V
IN3
IN3
IN3
IN3
V
V
= 3.8V
= 5V
IN12
IN12
0.01
0.1
1
I
10
(mA)
100
1000
0.01
0.1
1
I
10
(mA)
100
1000
0.01
0.1
1
I
10
(mA)
100
1000
OUT
OUT
OUT
36773 G22
36773 G23
36773 G21
Step-Down Switching Regulator
Output Transient (Burst Mode
Operation)
Step-Down Switching Regulator
Output Transient (Pulse-Skipping)
Step-Down Switching Regulator
Short-Circuit Current vs Temperature
1500
1400
1300
1200
1100
1000
900
V
OUT1
V
OUT1
50mV/DIV
(AC)
50mV/DIV
(AC)
V
OUT2
800mA BUCK
V
OUT2
50mV/DIV
(AC)
50mV/DIV
(AC)
V
OUT3
V
OUT3
100mV/DIV
(AC)
100mV/DIV
(AC)
500mA BUCK
800
500mA
500mA
I
I
OUT3
OUT3
700
5mA
5mA
36773 G26
36773 G25
V
I
= 3.3V
= 30mA
= 1.8V
= 20mA
= 1.2V
50µs/DIV
V
I
= 3.3V
= 10mA
= 1.8V
= 20mA
= 1.2V
50µs/DIV
OUT1
OUT1
V
V
= 3.8V
= 5V
OUT1
OUT1
INx
INx
600
V
V
OUT2
OUT2
500
OUT2
OUT2
I
–25
0
50
75 100 125
I
–50
25
V
V
V
V
OUT3
OUT
OUT3
OUT
TEMPERATURE (°C)
36773 G24
= V
= 3.8V
= V
= 3.8V
BAT
BAT
500mA Step-Down Switching
Regulator Feedback Voltage
vs Output Current
800mA Step-Down Switching
Regulator Feedback Voltage
vs Output Current
Step-Down Switching Regulator
Switch Impedance vs Temperature
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.85
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
0.85
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
V
= 3.2V
INX
500mA
PMOS
500mA
NMOS
Burst Mode
OPERATION
Burst Mode
OPERATION
PULSE-SKIPPING
PULSE-SKIPPING
800mA PMOS
800mA NMOS
V
V
= 3.8V
= 5V
V
= 3.8V
= 5V
IN12
IN3
IN3
IN12
V
0
0.1
1
10
(mA)
100
1000
–50 –25
0
25
125
50
75 100
0.1
1
10
(mA)
100
1000
I
TEMPERATURE (°C)
I
OUT
OUT
36773 G27
357732 G29
36773 G29
36773f
ꢀꢂ
LTC3677-3
Typical perForMance characTerisTics TJ = 25°C unless otherwise specified
Step-Down Switching Regulator 3
Soft-Start and Shutdown
OVP Connection Waveform
V
OUT1
100mV/DIV
(AC)
V
BUS
2V
5V/DIV
1V
0V
V
OUT3
OVGATE
5V/DIV
400mA
200mA
0mA
I
L3
OVP INPUT
VOLTAGE
0V TO 5V
STEP 5V/DIV
36773 G31
36773 G30
500µs/DIV
V
= 1.8V
= 100mA
= 3Ω
50µs/DIV
OUT1
OUT1
OUT3
I
R
OVP Protection Waveform
OVP Reconnection Waveform
V
BUS
5V/DIV
V
BUS
5V/DIV
OVGATE
5V/DIV
OVGATE
5V/DIV
OVP INPUT
VOLTAGE
10V TO 5V
STEP 5V/DIV
OVP INPUT
VOLTAGE
5V TO 10V
STEP 5V/DIV
36773 G33
36773 G32
500µs/DIV
500µs/DIV
Rising Overvoltage Threshold
vs Temperature
OVSENS Quiescent Current
vs Temperature
37
35
33
31
29
27
6.280
6.275
6.270
6.265
6.260
6.255
V
= 5V
OVSENS
–40
–15
10
35
60
85
–40
–15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
36773 G34
36773 G35
36773f
ꢀꢃ
LTC3677-3
Typical perForMance characTerisTics TJ = 25°C unless otherwise specified
OVGATE vs OVSENS
LDO Load Step
Too Hot BAT Discharge
12
10
200
180
160
140
120
100
80
OVSENS CONNECTED
TO INPUT THROUGH
6.2k RESISTOR
V
V
< V
TOO_HOT
= 0V
NTC
BUS
LDO1
50mV/DIV
(AC)
8
6
LDO2
20mV/DIV
(AC)
4
2
0
60
100mA
I
OUT1
40
5mA
36773 G37
LDO1 = 1.2V
LDO2 = 2.5V
20µs/DIV
20
I
= 40mA
LDO2
OUT
0
V
= V
= 3.8V
0
2
4
6
8
3.8
3.9
4.0
(V)
4.1
4.2
BAT
INPUT VOLTAGE (V)
V
BAT
36773 G38
36773 G36
Input and Battery Current
vs Output Current
Battery Discharge vs Temperature
600
500
400
300
200
100
0
200
R
R
= 2k
PROG
CLPROG
I
= 2k
IN
175
150
V
V
= 5V
= 0V
BUS
BUS
I
LOAD
125
100
75
I
BAT
(CHARGING)
50
V
V
= 4.1V
BAT
NTC
< V
TOO_HOT
5x MODE
25
I
BAT
I
= 0mA
VOUT
(DISCHARGING)
400
500
WALL = 0V
100
0
–100
60
70
90 100 110 120
0
200
300
(mA)
600
50
80
TEMPERATURE (°C)
I
OUT
36773 G40
36773 G39
pin FuncTions
I
, I
(Pins 1, 2):ꢀInputꢀCurrentꢀControlꢀPins.ꢀI
ꢀ
SW3 (Pin 5):ꢀPowerꢀTransmissionꢀ(Switch)ꢀPinꢀforꢀStep-
LIM0 LIM1
LIM0
andꢀI
ꢀcontrolꢀtheꢀinputꢀcurrentꢀlimit.ꢀSeeꢀTableꢀ1ꢀinꢀtheꢀ DownꢀSwitchingꢀRegulatorꢀ3ꢀ(Buck3).
LIM1
USBꢀPowerPathꢀControllerꢀsection.ꢀBothꢀpinsꢀareꢀpulledꢀ
lowꢀbyꢀaꢀweakꢀcurrentꢀsink.
VIN3 (Pin6):ꢀPowerꢀInputꢀforꢀStep-DownꢀSwitchingꢀRegu-
latorꢀ3.ꢀThisꢀpinꢀshouldꢀbeꢀconnectedꢀtoꢀVOUT
.
NC (Pins 3, 9, 18, 19, 20, 22):ꢀNoꢀConnect.ꢀThisꢀpinꢀhasꢀ
noꢀfunctionꢀandꢀmayꢀbeꢀfloatedꢀorꢀconnectedꢀtoꢀground.
FB3 (Pin 7):ꢀFeedbackꢀInputꢀforꢀStep-DownꢀSwitchingꢀ
Regulatorꢀ3ꢀ(Buck3).ꢀThisꢀpinꢀservosꢀtoꢀaꢀfixedꢀvoltageꢀofꢀ
WALL (Pin 4):ꢀWallꢀAdapterꢀPresentꢀInput.ꢀPullingꢀthisꢀ 0.8Vꢀwhenꢀtheꢀcontrolꢀloopꢀisꢀcomplete.
pinꢀaboveꢀ4.3VꢀwillꢀdisconnectꢀtheꢀpowerꢀpathꢀfromꢀV
ꢀ
BUS
OVSENSE (Pin 8):ꢀOvervoltageꢀProtectionꢀSenseꢀInput.ꢀ
OVSENSEꢀshouldꢀbeꢀconnectedꢀthroughꢀaꢀ6.2kꢀresistorꢀ
toꢀtheꢀinputꢀpowerꢀconnectorꢀandꢀtheꢀdrainꢀofꢀanꢀexternalꢀ
36773f
toꢀV .ꢀTheꢀACPRꢀpinꢀwillꢀalsoꢀbeꢀpulledꢀlowꢀtoꢀindicateꢀ
OUT
thatꢀaꢀwallꢀadapterꢀhasꢀbeenꢀdetected.
ꢀꢄ
LTC3677-3
pin FuncTions
N-channelꢀMOSFETꢀpassꢀtransistor.ꢀWhenꢀtheꢀvoltageꢀonꢀ value.ꢀThereꢀisꢀaꢀ230msꢀdelayꢀfromꢀallꢀregulatorsꢀreachingꢀ
thisꢀpinꢀexceedsꢀaꢀpresetꢀlevel,ꢀtheꢀOVGATEꢀpinꢀwillꢀbeꢀ regulationꢀandꢀPGOODꢀgoingꢀhigh.
pulledꢀtoꢀGNDꢀtoꢀdisableꢀtheꢀpassꢀtransistorꢀandꢀprotectꢀ
LDO1_FB (Pin 23):ꢀFeedbackꢀVoltageꢀInputꢀforꢀLowꢀDrop-
downstreamꢀcircuitry.
outꢀLinearꢀRegulatorꢀ1ꢀ(LDO1).ꢀLDO1ꢀoutputꢀvoltageꢀisꢀ
2
setꢀusingꢀanꢀexternalꢀresistorꢀdividerꢀbetweenꢀLDO1ꢀandꢀ
LDO1_FB.
DV (Pin 10):ꢀSupplyꢀVoltageꢀforꢀI CꢀLines.ꢀThisꢀpinꢀsetsꢀ
CC
theꢀlogicꢀreferenceꢀlevelꢀofꢀtheꢀLTC3677-3.ꢀAꢀUVLOꢀcircuitꢀ
onꢀtheꢀDV ꢀpinꢀforcesꢀallꢀregistersꢀtoꢀallꢀ0sꢀwheneverꢀDV ꢀ
CC
CC
LDO2_FB (Pin 24):ꢀFeedbackꢀVoltageꢀInputꢀforꢀLowꢀDrop-
outꢀLinearꢀRegulatorꢀ2ꢀ(LDO2).ꢀLDO2ꢀoutputꢀvoltageꢀisꢀ
setꢀusingꢀanꢀexternalꢀresistorꢀdividerꢀbetweenꢀLDO2ꢀandꢀ
LDO2_FB.
isꢀ<1V.ꢀBypassꢀtoꢀGNDꢀwithꢀaꢀ0.1µFꢀcapacitor.
2
SDA (Pin 11):ꢀI CꢀDataꢀInput.ꢀSerialꢀdataꢀisꢀshiftedꢀoneꢀ
bitꢀperꢀclockꢀtoꢀcontrolꢀtheꢀLTC3677-3.ꢀTheꢀlogicꢀlevelꢀforꢀ
SDAꢀisꢀreferencedꢀtoꢀDV .
CC
FB2 (Pin 25):ꢀFeedbackꢀInputꢀforꢀStep-DownꢀSwitchingꢀ
Regulatorꢀ2ꢀ(Buck2).ꢀThisꢀpinꢀservosꢀtoꢀaꢀfixedꢀvoltageꢀofꢀ
0.8Vꢀwhenꢀtheꢀcontrolꢀloopꢀisꢀcomplete.
2
SCL (Pin 12):ꢀI CꢀClockꢀInput.ꢀTheꢀlogicꢀlevelꢀforꢀSCLꢀisꢀ
referencedꢀtoꢀDV .
CC
FB1 (Pin 26):ꢀFeedbackꢀInputꢀforꢀStep-DownꢀSwitchingꢀ
Regulatorꢀ1ꢀ(Buck1).ꢀThisꢀpinꢀservosꢀtoꢀaꢀfixedꢀvoltageꢀofꢀ
0.8Vꢀwhenꢀtheꢀcontrolꢀloopꢀisꢀcomplete.
OVGATE (Pin 13):ꢀOvervoltageꢀProtectionꢀGateꢀOutput.ꢀ
ConnectꢀOVGATEꢀtoꢀtheꢀgateꢀpinꢀofꢀanꢀexternalꢀN-channelꢀ
MOSFETꢀpassꢀtransistor.ꢀTheꢀsourceꢀofꢀtheꢀtransistorꢀshouldꢀ
beꢀconnectedꢀtoꢀV ꢀandꢀtheꢀdrainꢀshouldꢀbeꢀconnectedꢀ
BUS
V
(Pin 27):ꢀInputꢀSupplyꢀofꢀLowꢀDropoutꢀLinearꢀ
INLDO1
toꢀtheꢀproduct’sꢀDCꢀinputꢀconnector.ꢀInꢀtheꢀabsenceꢀofꢀanꢀ
overvoltageꢀcondition,ꢀthisꢀpinꢀisꢀconnectedꢀtoꢀanꢀinternalꢀ
chargeꢀpumpꢀcapableꢀofꢀcreatingꢀsufficientꢀoverdriveꢀtoꢀ
fullyꢀenhanceꢀthisꢀtransistor.ꢀIfꢀanꢀovervoltageꢀconditionꢀ
isꢀdetected,ꢀOVGATEꢀisꢀbroughtꢀrapidlyꢀtoꢀGNDꢀtoꢀpreventꢀ
damage.ꢀOVGATEꢀworksꢀinꢀconjunctionꢀwithꢀOVSENSEꢀtoꢀ
provideꢀthisꢀprotection.
Regulatorꢀ1ꢀ(LDO1).ꢀThisꢀpinꢀshouldꢀbeꢀbypassedꢀtoꢀgroundꢀ
withꢀaꢀ1µFꢀorꢀgreaterꢀceramicꢀcapacitor.
LDO1(Pin28):ꢀOutputꢀofꢀLowꢀDropoutꢀLinearꢀRegulatorꢀ1.ꢀ
LDO1ꢀisꢀanꢀalways-onꢀLDOꢀandꢀwillꢀbeꢀenabledꢀwheneverꢀ
theꢀpartꢀisꢀnotꢀinꢀV ꢀUVLO.ꢀThisꢀpinꢀmustꢀbeꢀbypassedꢀ
OUT
toꢀgroundꢀwithꢀaꢀ1µFꢀorꢀgreaterꢀceramicꢀcapacitor.
LDO2(Pin29):ꢀOutputꢀofꢀLowꢀDropoutꢀLinearꢀRegulatorꢀ2.ꢀ
Thisꢀpinꢀmustꢀbeꢀbypassedꢀtoꢀgroundꢀwithꢀaꢀ1µFꢀorꢀgreaterꢀ
ceramicꢀcapacitor.
PWR_ON(Pin14):ꢀLogicꢀInputꢀUsedꢀtoꢀKeepꢀBuck1,ꢀBuck2ꢀ
andꢀLDO2ꢀEnabledꢀAfterꢀPower-Up.ꢀMayꢀalsoꢀbeꢀusedꢀtoꢀ
enableꢀregulatorsꢀdirectlyꢀ(sequenceꢀ=ꢀLDO2ꢀ→ꢀBuck1ꢀ→ꢀ
Buck2).ꢀSeeꢀtheꢀPushbuttonꢀInterfaceꢀOperationꢀsectionꢀ
forꢀmoreꢀinformation.
V
(Pin 30):ꢀInputꢀSupplyꢀofꢀLowꢀDropoutꢀLinearꢀ
INLDO2
Regulatorꢀ2ꢀ(LDO2).ꢀThisꢀpinꢀshouldꢀbeꢀbypassedꢀtoꢀgroundꢀ
withꢀaꢀ1µFꢀorꢀgreaterꢀceramicꢀcapacitor.
ON (Pin 15):ꢀPushbuttonꢀInput.ꢀAꢀweakꢀinternalꢀpull-upꢀ
forcesꢀONꢀhighꢀwhenꢀleftꢀfloating.ꢀAꢀnormallyꢀopenꢀpush-
buttonꢀisꢀconnectedꢀfromꢀONꢀtoꢀgroundꢀtoꢀforceꢀaꢀlowꢀ
stateꢀonꢀthisꢀpin.
SW2 (Pin 31):ꢀPowerꢀTransmissionꢀ(Switch)ꢀPinꢀforꢀStep-
DownꢀSwitchingꢀRegulatorꢀ2ꢀ(Buck2).
V
(Pin 32):ꢀ Powerꢀ Inputꢀ forꢀ Step-Downꢀ Switchingꢀ
IN12
PBSTAT (Pin 16):ꢀ Open-drainꢀ outputꢀ isꢀ aꢀ debouncedꢀ
andꢀbufferedꢀversionꢀofꢀONꢀtoꢀbeꢀusedꢀforꢀprocessorꢀ
interrupts.
Regulatorsꢀ1ꢀandꢀ2.ꢀThisꢀpinꢀwillꢀgenerallyꢀbeꢀconnectedꢀ
toꢀV
.
OUT
SW1 (Pin 33):ꢀPowerꢀTransmissionꢀ(Switch)ꢀPinꢀforꢀStep-
DownꢀSwitchingꢀRegulatorꢀ1ꢀ(Buck1).
EN3 (Pin 17):ꢀ Enableꢀ Pinꢀ forꢀ Step-Downꢀ Switchingꢀ
Regulatorꢀ3ꢀ(Buck3)
.
NTCBIAS (Pin 34):ꢀ Outputꢀ Biasꢀ Voltageꢀ forꢀ NTC.ꢀ Aꢀ
resistorꢀfromꢀthisꢀpinꢀtoꢀtheꢀNTCꢀpinꢀwillꢀbiasꢀtheꢀNTCꢀ
Buck1,ꢀBuck2ꢀandꢀLDO1ꢀareꢀwithinꢀ8%ꢀofꢀfinalꢀregulationꢀ thermistor.
PGOOD(Pin21):ꢀOpen-DrainꢀOutput.ꢀPGOODꢀindicatesꢀthatꢀ
36773f
ꢀꢅ
LTC3677-3
pin FuncTions
wallꢀadapter.ꢀV ꢀshouldꢀbeꢀbypassedꢀwithꢀaꢀlowꢀimped-
NTC (Pin 35):ꢀTheꢀNTCꢀpinꢀconnectsꢀtoꢀaꢀbattery’sꢀtherm-
istorꢀtoꢀdetermineꢀifꢀtheꢀbatteryꢀisꢀtooꢀhotꢀorꢀtooꢀcoldꢀ
toꢀcharge.ꢀIfꢀtheꢀbattery’sꢀtemperatureꢀisꢀoutꢀofꢀrange,ꢀ
chargingꢀisꢀpausedꢀuntilꢀitꢀdropsꢀbackꢀintoꢀrange.ꢀAꢀlowꢀ
driftꢀbiasꢀresistorꢀisꢀrequiredꢀfromꢀNTCBIASꢀtoꢀNTCꢀandꢀ
aꢀthermistorꢀisꢀrequiredꢀfromꢀNTCꢀtoꢀground.ꢀ
BUS
anceꢀmultilayerꢀceramicꢀcapacitor.
ACPR(Pin41):ꢀWallꢀAdapterꢀPresentꢀOutputꢀ(ActiveꢀLow).ꢀ
Aꢀlowꢀonꢀthisꢀpinꢀindicatesꢀthatꢀtheꢀwallꢀadapterꢀinputꢀcom-
paratorꢀhasꢀhadꢀitsꢀinputꢀpulledꢀaboveꢀitsꢀinputꢀthresholdꢀ
(typicallyꢀ4.3V).ꢀThisꢀpinꢀcanꢀbeꢀusedꢀtoꢀdriveꢀtheꢀgateꢀofꢀ
anꢀexternalꢀP-channelꢀMOSFETꢀtoꢀprovideꢀpowerꢀtoꢀV
fromꢀaꢀpowerꢀsourceꢀotherꢀthanꢀaꢀUSBꢀport.
ꢀ
PROG (Pin 36):ꢀ Chargeꢀ Currentꢀ Programꢀ andꢀ Chargeꢀ
CurrentꢀMonitorꢀPin.ꢀConnectingꢀaꢀresistorꢀfromꢀPROGꢀ
toꢀgroundꢀprogramsꢀtheꢀchargeꢀcurrent:
OUT
EXTPWR (Pin 42):ꢀExternalꢀPowerꢀPresentꢀOutputꢀ(Activeꢀ
Low,ꢀOpen-DrainꢀOutput).ꢀAꢀlowꢀonꢀthisꢀpinꢀindicatesꢀthatꢀ
1000V
RPROG
ICHG
=
A
( )
externalꢀpowerꢀisꢀpresentꢀatꢀeitherꢀtheꢀV ꢀorꢀWALLꢀinput.ꢀ
BUS
ꢀ
ForꢀEXTPWRꢀtoꢀsignalꢀV ꢀpresent,ꢀV ꢀmustꢀexceedꢀ
BUS
BUS
Ifꢀsufficientꢀinputꢀpowerꢀisꢀavailableꢀinꢀconstant-currentꢀ
mode,ꢀthisꢀpinꢀservosꢀtoꢀ1V.ꢀTheꢀvoltageꢀonꢀthisꢀpinꢀalwaysꢀ
representsꢀtheꢀactualꢀchargeꢀcurrent.
theꢀV ꢀundervoltageꢀlockoutꢀthreshold.ꢀForꢀEXTPWRꢀtoꢀ
BUS
signalꢀWALLꢀpresent,ꢀWALLꢀmustꢀexceedꢀtheꢀabsoluteꢀandꢀ
differentialꢀWALLꢀinputꢀthresholds.ꢀTheꢀEXTPWRꢀsignalꢀisꢀ
independentꢀofꢀtheꢀI
ꢀandꢀI
LIM1
ꢀpins.ꢀThus,ꢀitꢀisꢀpossibleꢀ
LIM0
IDGATE (Pin 37):ꢀ Idealꢀ Diodeꢀ Gateꢀ Connection.ꢀ Thisꢀ
pinꢀcontrolsꢀtheꢀgateꢀofꢀanꢀoptionalꢀexternalꢀP-channelꢀ
MOSFETꢀtransistorꢀusedꢀtoꢀsupplementꢀtheꢀinternalꢀidealꢀ
diode.ꢀTheꢀsourceꢀofꢀtheꢀP-channelꢀMOSFETꢀshouldꢀbeꢀ
toꢀhaveꢀtheꢀinputꢀcurrentꢀlimitꢀcircuitryꢀinꢀsuspendꢀwithꢀ
EXTPWRꢀshowingꢀaꢀvalidꢀchargingꢀlevelꢀonꢀV
.
BUS
CLPROG (Pin 43):ꢀ Inputꢀ Currentꢀ Programꢀ andꢀ Inputꢀ
CurrentꢀMonitorꢀPin.ꢀAꢀresistorꢀfromꢀCLPROGꢀtoꢀgroundꢀ
determinesꢀtheꢀupperꢀlimitꢀofꢀtheꢀcurrentꢀdrawnꢀfromꢀtheꢀ
connectedꢀtoꢀV ꢀandꢀtheꢀdrainꢀshouldꢀbeꢀconnectedꢀtoꢀ
OUT
BAT.ꢀItꢀisꢀimportantꢀtoꢀmaintainꢀhighꢀimpedanceꢀonꢀthisꢀ
pinꢀandꢀminimizeꢀallꢀleakageꢀpaths.
V
ꢀpinꢀ(i.e.,ꢀtheꢀinputꢀcurrentꢀlimit).ꢀAꢀpreciseꢀfractionꢀ
BUS
ofꢀtheꢀinputꢀcurrent,ꢀh
,ꢀisꢀsentꢀtoꢀtheꢀCLPROGꢀpin.ꢀ
CLPROG
BAT (Pin 38):ꢀSingle-CellꢀLi-IonꢀBatteryꢀPin.ꢀDependingꢀ
TheꢀinputꢀPowerPathꢀdeliversꢀcurrentꢀuntilꢀtheꢀCLPROGꢀ
pinꢀreachesꢀ2Vꢀ(10xꢀmode),ꢀ1Vꢀ(5xꢀmode)ꢀorꢀ0.2Vꢀ(1xꢀ
onꢀavailableꢀpowerꢀandꢀload,ꢀaꢀLi-IonꢀbatteryꢀonꢀBATꢀwillꢀ
eitherꢀdeliverꢀsystemꢀpowerꢀtoꢀV ꢀthroughꢀtheꢀidealꢀ
OUT
mode).ꢀTherefore,ꢀtheꢀcurrentꢀdrawnꢀfromꢀV ꢀwillꢀbeꢀ
BUS
diodeꢀorꢀbeꢀchargedꢀfromꢀtheꢀbatteryꢀcharger.
limitedꢀtoꢀanꢀamountꢀgivenꢀbyꢀh
USBꢀapplicationsꢀtheꢀresistorꢀR
noꢀlessꢀthanꢀ2.1k.
ꢀandꢀR
.ꢀInꢀ
CLPROG
CLPROG
CLPROG
V
(Pin39):ꢀOutputꢀVoltageꢀofꢀtheꢀPowerPathꢀControllerꢀ
OUT
ꢀshouldꢀbeꢀsetꢀtoꢀ
andꢀInputꢀVoltageꢀofꢀtheꢀBatteryꢀCharger.ꢀTheꢀmajorityꢀofꢀ
theꢀportableꢀproductꢀshouldꢀbeꢀpoweredꢀfromꢀV .ꢀTheꢀ
OUT
CHRG (Pin 44):ꢀOpen-DrainꢀChargeꢀStatusꢀOutput.ꢀTheꢀ
CHRGꢀpinꢀindicatesꢀtheꢀstatusꢀofꢀtheꢀbatteryꢀcharger.ꢀIfꢀ
CHRGꢀisꢀhighꢀthenꢀtheꢀchargerꢀisꢀnearꢀtheꢀfloatꢀvoltageꢀ
(chargeꢀcurrentꢀlessꢀthanꢀ1/10thꢀprogrammedꢀchargeꢀcur-
rent)ꢀorꢀchargingꢀisꢀcompleteꢀandꢀchargerꢀisꢀdisabled.ꢀAꢀlowꢀ
onꢀCHRGꢀindicatesꢀthatꢀtheꢀchargerꢀisꢀenabled.ꢀForꢀmoreꢀ
informationꢀseeꢀtheꢀChargeꢀStatusꢀIndicationꢀsection.
LTC3677-3ꢀwillꢀpartitionꢀtheꢀavailableꢀpowerꢀbetweenꢀtheꢀ
externalꢀloadꢀonꢀV ꢀandꢀtheꢀinternalꢀbatteryꢀcharger.ꢀ
OUT
Priorityꢀisꢀgivenꢀtoꢀtheꢀexternalꢀloadꢀandꢀanyꢀextraꢀpowerꢀ
isꢀusedꢀtoꢀchargeꢀtheꢀbattery.ꢀAnꢀidealꢀdiodeꢀfromꢀBATꢀ
toꢀV ꢀensuresꢀthatꢀV ꢀisꢀpoweredꢀevenꢀifꢀtheꢀloadꢀ
OUT
OUT
exceedsꢀtheꢀallottedꢀinputꢀcurrentꢀfromꢀV ꢀorꢀifꢀtheꢀV
ꢀ
BUS
BUS
powerꢀsourceꢀisꢀremoved.ꢀV ꢀshouldꢀbeꢀbypassedꢀwithꢀ
OUT
aꢀlowꢀimpedanceꢀmultilayerꢀceramicꢀcapacitor.
GND (Exposed Pad Pin 45):ꢀTheꢀexposedꢀpackageꢀpadꢀisꢀ
groundꢀandꢀmustꢀbeꢀsolderedꢀtoꢀPCBꢀgroundꢀforꢀelectricalꢀ
contactꢀandꢀratedꢀthermalꢀperformance.ꢀ
V
(Pin 40):ꢀUSBꢀInputꢀVoltage.ꢀV ꢀwillꢀusuallyꢀbeꢀ
BUS
BUS
connectedꢀtoꢀtheꢀUSBꢀportꢀofꢀaꢀcomputerꢀorꢀaꢀDCꢀoutputꢀ
36773f
ꢀꢆ
LTC3677-3
block DiagraM
8
13
42
EXTPWR
4
41
ACPR
OVSENS
OVGATE
WALL
OVERVOLTAGE
PROTECTON
EXTERNAL
POWER DETECT
WALL
DETECT
V
V
OUT
BUS
40
43
39
37
+
–
IDGATE
INPUT
CURRENT
LIMIT
CC/CV
IDEAL
DIODE
CLPROG
CHARGER
–
+
NTCBIAS
NTC
15mV
34
35
BATTERY
TEMP
BAT
OVERTEMP BATTERY
SAFETY DISCHARGER
38
36
MONITOR
PROG
UVLO
I
I
LIM0
1
2
I
LIM
V
INLD02
LIM1
LOGIC
EN
30
–
+
0.8V
CHRG
14ms
RISING
DELAY
LDO2
150mA
LDO2
44
29
24
CHARGE
STATUS
LDO2_FB
V
IN12
EN
32
33
500mA, 2.25MHz
BUCK REGULATOR 1
PWR_ON
ON
SW1
FB1
14
PUSH-
BUTTON
INPUT
0.8V
+
15
16
–
PBSTAT
PG
EN
26
31
EN3
17
DV
CC
500mA, 2.25MHz
BUCK REGULATOR 2
10
11
12
2
SDA
I C
SW2
FB2
LOGIC
0.8V
+
SCL
–
PGOOD
21
PG
EN
25
6
230ms FALLING
DELAY
V
IN3
800mA, 2.25MHz
BUCK REGULATOR 3
SW3
5
0.8V
+
NC
3, 9, 18, 19, 20, 22
–
FB3
7
V
INLD01
ENB
PG
27
–
+
0.8V
LDO1
28
23
150mA
LDO1
LDO1_FB
GND
45
36773 BD
36773f
ꢀꢇ
LTC3677-3
operaTion
PowerPath OPERATION
guaranteesꢀthatꢀampleꢀpowerꢀisꢀalwaysꢀavailableꢀtoꢀV
ꢀ
OUT
evenꢀifꢀthereꢀisꢀinsufficientꢀorꢀabsentꢀpowerꢀatꢀV .ꢀTheꢀ
BUS
Introduction
LTC3677-3ꢀalsoꢀhasꢀtheꢀabilityꢀtoꢀreceiveꢀpowerꢀfromꢀaꢀ
wallꢀadapterꢀorꢀotherꢀnon-current-limitedꢀpowerꢀsource.ꢀ
TheꢀLTC3677-3ꢀisꢀhighlyꢀintegratedꢀpowerꢀmanagementꢀ
ICꢀthatꢀincludesꢀtheꢀfollowingꢀfeatures:
SuchꢀaꢀpowerꢀsupplyꢀcanꢀbeꢀconnectedꢀtoꢀtheꢀV ꢀpinꢀofꢀ
OUT
theꢀLTC3677-3ꢀthroughꢀanꢀexternalꢀdeviceꢀsuchꢀasꢀaꢀpowerꢀ
SchottkyꢀorꢀFET,ꢀasꢀshownꢀinꢀFigureꢀ1.ꢀTheꢀLTC3677-3ꢀhasꢀ
theꢀuniqueꢀabilityꢀtoꢀuseꢀtheꢀoutput,ꢀwhichꢀisꢀpoweredꢀbyꢀanꢀ
externalꢀsupply,ꢀtoꢀchargeꢀtheꢀbatteryꢀwhileꢀprovidingꢀpowerꢀ
toꢀtheꢀload.ꢀAꢀcomparatorꢀonꢀtheꢀWALLꢀpinꢀisꢀconfiguredꢀ
toꢀdetectꢀtheꢀpresenceꢀofꢀtheꢀwallꢀadapterꢀandꢀshutꢀoffꢀtheꢀ
connectionꢀtoꢀtheꢀUSB.ꢀThisꢀpreventsꢀreverseꢀconductionꢀ
ꢀ –ꢀPowerPathꢀcontroller
ꢀ –ꢀBatteryꢀcharger
ꢀ –ꢀIdealꢀdiode
ꢀ –ꢀInputꢀovervoltageꢀprotection
ꢀ –ꢀPushbuttonꢀcontroller
ꢀ –ꢀThreeꢀstep-downꢀswitchingꢀregulators
ꢀ –ꢀTwoꢀlowꢀdropoutꢀlinearꢀregulators
fromꢀV ꢀtoꢀV ꢀwhenꢀaꢀwallꢀadapterꢀisꢀpresent.ꢀ
OUT
BUS
TheꢀLTC3677-3ꢀalsoꢀincludesꢀaꢀpushbuttonꢀꢀinputꢀtoꢀcontrolꢀ
theꢀ powerꢀ sequencingꢀ ofꢀ twoꢀ synchronousꢀ step-downꢀ
switchingꢀregulatorsꢀ(Buck1ꢀandꢀBuck2),ꢀaꢀlowꢀdropoutꢀ
regulatorꢀ(LDO2)ꢀandꢀsystemꢀreset.ꢀTheꢀthreeꢀ2.25MHzꢀ
constant-frequencyꢀcurrentꢀmodeꢀstep-downꢀswitchingꢀ
regulatorsꢀprovideꢀ500mA,ꢀ500mAꢀandꢀ800mAꢀeachꢀandꢀ
DesignedꢀspecificallyꢀforꢀUSBꢀapplications,ꢀtheꢀPowerPathꢀ
controllerꢀ incorporatesꢀ aꢀ precisionꢀ inputꢀ currentꢀ limitꢀ
whichꢀcommunicatesꢀwithꢀtheꢀbatteryꢀchargerꢀtoꢀensureꢀ
thatꢀinputꢀcurrentꢀdoesꢀnotꢀviolateꢀtheꢀUSBꢀaverageꢀinputꢀ
currentꢀspecification.ꢀTheꢀidealꢀdiodeꢀfromꢀBATꢀtoꢀV
ꢀ
OUT
FROM AC ADAPTER
4.3V
–
+
(RISING)
3.2V
(FALLING)
WALL
4
ACPR
41
+
–
75mV (RISING)
+
–
25mV (FALLING)
FROM
ENABLE
V
V
V
OUT
USB
BUS
OUT
40
39
37
SYSTEM
LOAD
USB CURRENT LIMIT
IDEAL
DIODE
OPTIONAL
EXTERNAL
IDEAL DIODE
PMOS
+
–
IDGATE
CONSTANT-CURRENT
CONSTANT-VOLTAGE
BATTERY CHARGER
–
+
15mV
BAT
BAT
38
+
Li-Ion
36773 F01
Figure 1. Simplified PowerPath Block Diagram
36773f
ꢀꢈ
LTC3677-3
operaTion
supportꢀ100%ꢀdutyꢀcycleꢀoperationꢀasꢀwellꢀasꢀoperatingꢀ TheꢀinputꢀcurrentꢀlimitꢀisꢀprogrammedꢀbyꢀtheꢀI
inꢀBurstꢀModeꢀoperationꢀforꢀhighꢀefficiencyꢀatꢀlightꢀload.ꢀ
ꢀandꢀ
LIM0
I
ꢀpins.ꢀTheꢀLTC3677-3ꢀcanꢀbeꢀconfiguredꢀtoꢀlimitꢀinputꢀ
LIM1
Noꢀexternalꢀcompensationꢀcomponentsꢀareꢀrequiredꢀforꢀ currentꢀtoꢀoneꢀofꢀseveralꢀpossibleꢀsettingsꢀasꢀwellꢀasꢀbeꢀ
theꢀswitchingꢀregulators.ꢀTheꢀtwoꢀlowꢀdropoutꢀregulatorsꢀ deactivatedꢀ(USBꢀsuspend).ꢀTheꢀinputꢀcurrentꢀlimitꢀwillꢀbeꢀ
canꢀoutputꢀupꢀtoꢀ150mA.
setꢀbyꢀtheꢀappropriateꢀservoꢀvoltageꢀandꢀtheꢀresistorꢀonꢀ
CLPROGꢀaccordingꢀtoꢀtheꢀfollowingꢀexpression:
Allꢀregulatorsꢀcanꢀbeꢀprogrammedꢀforꢀaꢀminimumꢀoutputꢀ
voltageꢀofꢀ0.8Vꢀandꢀcanꢀbeꢀusedꢀtoꢀpowerꢀaꢀmicrocon-
trollerꢀcore,ꢀmicrocontrollerꢀI/O,ꢀmemoryꢀorꢀotherꢀlogicꢀ
circuitry.ꢀ
0.2V
RCLPROG
IVBUS = IBUSQ
IVBUS = IBUSQ
IVBUS = IBUSQ
+
+
+
•hCLPROG 1x Mode
(
)
1V
RCLPROG
•hCLPROG 5x Mode
(
)
USB PowerPath Controller
Theꢀinputꢀcurrentꢀlimitꢀandꢀchargeꢀcontrolꢀcircuitsꢀofꢀtheꢀ
LTC3677-3ꢀisꢀdesignedꢀtoꢀlimitꢀinputꢀcurrentꢀasꢀwellꢀasꢀ
controlꢀ batteryꢀ chargeꢀ currentꢀ asꢀ aꢀ functionꢀ ofꢀ I
2V
RCLPROG
•hCLPROG 10x Mode
(
)
.ꢀ
VOUTꢀ
ꢀ
V
ꢀ drivesꢀ theꢀ combinationꢀ ofꢀ theꢀ externalꢀ load,ꢀ theꢀ
OUT
Underꢀworst-caseꢀconditions,ꢀtheꢀUSBꢀspecificationꢀforꢀ
averageꢀinputꢀcurrentꢀwillꢀnotꢀbeꢀviolatedꢀwithꢀanꢀR
threeꢀstep-downꢀswitchingꢀregulators,ꢀtwoꢀLDOsꢀandꢀtheꢀ
batteryꢀcharger.
ꢀ
CLPROG
resistorꢀofꢀ2.1kꢀorꢀgreater.ꢀTableꢀ1ꢀshowsꢀtheꢀavailableꢀ
settingsꢀforꢀtheꢀI ꢀandꢀI ꢀpins:
Ifꢀtheꢀcombinedꢀloadꢀdoesꢀnotꢀexceedꢀtheꢀprogrammedꢀ
LIM0
LIM1
inputꢀcurrentꢀlimit,ꢀV ꢀwillꢀbeꢀconnectedꢀtoꢀV ꢀthroughꢀ
OUT
BUS
Table 1. Controlled Input Current Limit
anꢀinternalꢀ200mΩꢀP-channelꢀMOSFET.ꢀIfꢀtheꢀcombinedꢀ
I
I
I
BUS(LIM)
LIM1
LIM0
loadꢀatꢀV ꢀexceedsꢀtheꢀprogrammedꢀinputꢀcurrentꢀlimit,ꢀ
OUT
1
1
100mAꢀ(1x)
1Aꢀ(10x)
theꢀbatteryꢀchargerꢀwillꢀreduceꢀitsꢀchargeꢀcurrentꢀbyꢀtheꢀ
amountꢀnecessaryꢀtoꢀenableꢀtheꢀexternalꢀloadꢀtoꢀbeꢀsatisfiedꢀ
whileꢀmaintainingꢀtheꢀprogrammedꢀinputꢀcurrent.ꢀEvenꢀifꢀ
theꢀbatteryꢀchargeꢀcurrentꢀisꢀsetꢀtoꢀexceedꢀtheꢀallowableꢀ
USBꢀcurrent,ꢀtheꢀaverageꢀinputꢀcurrentꢀUSBꢀspecificationꢀ
1
0
0
0
1
0
Suspend
500mAꢀ(5x)
NoticeꢀthatꢀwhenꢀI
ꢀisꢀlowꢀandꢀI
ꢀisꢀhigh,ꢀtheꢀinputꢀ
LIM0
LIM1
willꢀnotꢀbeꢀviolated.ꢀFurthermore,ꢀloadꢀcurrentꢀatꢀV
ꢀ
OUT
currentꢀlimitꢀisꢀsetꢀtoꢀaꢀhigherꢀcurrentꢀlimitꢀforꢀincreasedꢀ
willꢀalwaysꢀbeꢀprioritizedꢀandꢀonlyꢀexcessꢀavailableꢀcur-
rentꢀwillꢀbeꢀusedꢀtoꢀchargeꢀtheꢀbattery.ꢀTheꢀcurrentꢀoutꢀ
ofꢀtheꢀCLPROGꢀpinꢀisꢀaꢀfractionꢀ(1/h )ꢀofꢀtheꢀV
chargingꢀandꢀcurrentꢀavailabilityꢀatꢀV .ꢀThisꢀmodeꢀisꢀ
OUTꢀ
typicallyꢀusedꢀwhenꢀthereꢀisꢀaꢀhigherꢀpower,ꢀnon-USBꢀ
ꢀ
BUS
CLPROG
sourceꢀavailableꢀatꢀtheꢀV ꢀpin.
BUS
current.ꢀWhenꢀaꢀprogrammingꢀresistorꢀisꢀconnectedꢀfromꢀ
CLPROGꢀtoꢀGND,ꢀtheꢀvoltageꢀonꢀCLPROGꢀrepresentsꢀtheꢀ
inputꢀcurrent:
VCLPROG
RCLPROG
IVBUS = IBUSQ
+
•hCLPROG
ꢀ
whereꢀ I
ꢀ andꢀ h
ꢀ areꢀ givenꢀ inꢀ theꢀ Electricalꢀ
CLPROG
BUSQ
Characteristicsꢀtable.
36773f
ꢁ0
LTC3677-3
operaTion
Ideal Diode from BAT to V
Using the WALL Pin to Detect the Presence of an
OUT
External Power Source
TheꢀLTC3677-3ꢀhasꢀanꢀinternalꢀidealꢀdiodeꢀasꢀwellꢀasꢀaꢀ
controllerꢀforꢀanꢀoptionalꢀexternalꢀidealꢀdiode.ꢀBothꢀtheꢀ
internalꢀ andꢀ theꢀ externalꢀ idealꢀ diodesꢀ respondꢀ quicklyꢀ
TheꢀWALLꢀinputꢀpinꢀcanꢀbeꢀusedꢀtoꢀidentifyꢀtheꢀpresenceꢀ
ofꢀanꢀexternalꢀpowerꢀsourceꢀ(particularlyꢀoneꢀthatꢀisꢀnotꢀ
wheneverꢀV ꢀdropsꢀbelowꢀBAT.ꢀIfꢀtheꢀloadꢀincreasesꢀ
subjectꢀtoꢀaꢀfixedꢀcurrentꢀlimitꢀlikeꢀtheꢀUSBꢀV ꢀinput).ꢀ
OUT
BUS
beyondꢀtheꢀinputꢀcurrentꢀlimit,ꢀadditionalꢀcurrentꢀwillꢀbeꢀ
pulledꢀfromꢀtheꢀbatteryꢀviaꢀtheꢀidealꢀdiodes.ꢀFurthermore,ꢀifꢀ
powerꢀtoꢀV ꢀ(USB)ꢀorꢀV ꢀ(externalꢀwallꢀpowerꢀorꢀhighꢀ
Typically,ꢀsuchꢀaꢀpowerꢀsupplyꢀwouldꢀbeꢀaꢀ5Vꢀwallꢀadapterꢀ
outputꢀorꢀtheꢀlowꢀvoltageꢀoutputꢀofꢀaꢀhighꢀvoltageꢀbuckꢀ
regulator.ꢀWhenꢀtheꢀwallꢀadapterꢀoutputꢀ(orꢀbuckꢀregulatorꢀ
output)ꢀisꢀconnectedꢀdirectlyꢀtoꢀtheꢀWALLꢀpin,ꢀandꢀtheꢀvolt-
ageꢀexceedsꢀtheꢀWALLꢀpinꢀthreshold,ꢀtheꢀUSBꢀpowerꢀpathꢀ
(fromꢀV ꢀtoꢀV )ꢀwillꢀbeꢀdisconnected.ꢀFurthermore,ꢀ
theꢀACPRꢀpinꢀwillꢀbeꢀpulledꢀlow.ꢀInꢀorderꢀforꢀtheꢀpresenceꢀ
ofꢀanꢀexternalꢀpowerꢀsupplyꢀtoꢀbeꢀacknowledged,ꢀbothꢀofꢀ
theꢀfollowingꢀconditionsꢀmustꢀbeꢀsatisfied:
BUS
OUT
voltageꢀregulator)ꢀisꢀremoved,ꢀthenꢀallꢀofꢀtheꢀapplicationꢀ
powerꢀwillꢀbeꢀprovidedꢀbyꢀtheꢀbatteryꢀviaꢀtheꢀidealꢀdiodes.ꢀ
TheꢀidealꢀdiodesꢀareꢀfastꢀenoughꢀtoꢀkeepꢀV ꢀfromꢀdrop-
OUT
BUS
OUT
pingꢀsignificantlyꢀbelowꢀV ꢀwithꢀjustꢀtheꢀrecommendedꢀ
BAT
outputꢀcapacitorꢀ(seeꢀFigureꢀ2).ꢀTheꢀidealꢀdiodeꢀconsistsꢀ
ofꢀaꢀprecisionꢀamplifierꢀthatꢀenablesꢀanꢀon-chipꢀP-channelꢀ
MOSFETꢀwheneverꢀtheꢀvoltageꢀatꢀV ꢀisꢀapproximatelyꢀ
OUT
1.ꢀTheꢀ WALLꢀ pinꢀ voltageꢀ mustꢀ exceedꢀ approximatelyꢀ
4.3V.
15mVꢀ(V )ꢀbelowꢀtheꢀvoltageꢀatꢀBAT.ꢀTheꢀresistanceꢀofꢀ
FWD
theꢀinternalꢀidealꢀdiodeꢀisꢀapproximatelyꢀ200mΩ.ꢀIfꢀthisꢀisꢀ
sufficientꢀforꢀtheꢀapplication,ꢀthenꢀnoꢀexternalꢀcomponentsꢀ
areꢀnecessary.ꢀHowever,ꢀifꢀlowerꢀresistanceꢀisꢀneeded,ꢀanꢀ
externalꢀP-channelꢀMOSFETꢀcanꢀbeꢀaddedꢀfromꢀBATꢀtoꢀ
2.ꢀTheꢀWALLꢀpinꢀvoltageꢀmustꢀbeꢀgreaterꢀthanꢀ75mVꢀaboveꢀ
theꢀBATꢀpinꢀvoltage.ꢀ
Theꢀinputꢀpowerꢀpathꢀ(betweenꢀV ꢀandꢀV )ꢀisꢀre-ꢀ
BUS
OUT
V
.ꢀTheꢀIDGATEꢀpinꢀofꢀtheꢀLTC3677-3ꢀdrivesꢀtheꢀgateꢀofꢀ
OUTꢀ
enabledꢀandꢀtheꢀACPRꢀpinꢀisꢀpulledꢀhighꢀwhenꢀeitherꢀofꢀ
theꢀexternalꢀP-channelꢀMOSFETꢀforꢀautomaticꢀidealꢀdiodeꢀ
control.ꢀTheꢀsourceꢀofꢀtheꢀMOSFETꢀshouldꢀbeꢀconnectedꢀtoꢀ
theꢀfollowingꢀconditionsꢀisꢀmet:
1.ꢀTheꢀWALLꢀpinꢀvoltageꢀfallsꢀtoꢀwithinꢀ25mVꢀofꢀtheꢀBATꢀ
pinꢀvoltage.
V
ꢀandꢀtheꢀdrainꢀshouldꢀbeꢀconnectedꢀtoꢀBAT.ꢀCapableꢀofꢀ
OUT
drivingꢀaꢀ1nFꢀload,ꢀtheꢀIDGATEꢀpinꢀcanꢀcontrolꢀanꢀexternalꢀ
P-channelꢀMOSFETꢀhavingꢀextremelyꢀlowꢀon-resistance.
2.ꢀTheꢀWALLꢀpinꢀvoltageꢀfallsꢀbelowꢀ3.2V.ꢀ
Eachꢀofꢀtheseꢀthresholdsꢀisꢀsuitablyꢀfilteredꢀinꢀtimeꢀtoꢀ
preventꢀtransientꢀglitchesꢀonꢀtheꢀWALLꢀpinꢀfromꢀfalselyꢀ
triggeringꢀanꢀevent.ꢀ
4.0V
V
3.8V
3.6V
OUT
Suspend Mode
Whenꢀ I
ꢀ isꢀ pulledꢀ highꢀ andꢀ I
ꢀ isꢀ pulledꢀ lowꢀ theꢀ
500mA
LIM0
LIM1
CHARGE
LTC3677-3ꢀ entersꢀ suspendꢀ modeꢀ toꢀ complyꢀ withꢀ theꢀ
I
0
BAT
DISCHARGE
USBꢀspecification.ꢀInꢀthisꢀmode,ꢀtheꢀpowerꢀpathꢀbetweenꢀ
–500mA
1A
V
ꢀandꢀV ꢀisꢀputꢀinꢀaꢀhighꢀimpedanceꢀstateꢀtoꢀreduceꢀ
OUT
BUS
BUS
I
VOUT
theꢀV ꢀinputꢀcurrentꢀtoꢀ50μA.ꢀIfꢀnoꢀotherꢀpowerꢀsourceꢀ
LOAD
0A
36773 F02
isꢀavailableꢀtoꢀdriveꢀWALLꢀandꢀV ,ꢀtheꢀsystemꢀloadꢀ
OUTꢀ
V
V
= 3.8V
= 5V
10µs/DIV
BAT
BUS
5x MODE
connectedꢀtoꢀV ꢀisꢀsuppliedꢀthroughꢀtheꢀidealꢀdiodesꢀ
OUT
C
= 10µF
OUT
connectedꢀtoꢀBAT.ꢀ
Figure 2. Ideal Diode Transient Response
36773f
ꢁꢀ
LTC3677-3
operaTion
BUS
Current Limit (UVCL)
V
Undervoltage Lockout (UVLO) and Undervoltage
Charge Termination
Theꢀbatteryꢀchargerꢀhasꢀaꢀbuilt-inꢀsafetyꢀtimer.ꢀWhenꢀ
theꢀ batteryꢀ voltageꢀ approachesꢀ theꢀ floatꢀ voltage,ꢀ theꢀ
chargeꢀ currentꢀ beginsꢀ toꢀ decreaseꢀ asꢀ theꢀ LTC3677-3ꢀ
AnꢀinternalꢀundervoltageꢀlockoutꢀcircuitꢀmonitorsꢀV
andꢀkeepsꢀtheꢀinputꢀcurrentꢀlimitꢀcircuitryꢀoffꢀuntilꢀV
ꢀ
ꢀ
BUS
BUS
risesꢀaboveꢀtheꢀrisingꢀUVLOꢀthresholdꢀ(3.8V)ꢀandꢀatꢀleastꢀ entersꢀconstant-voltageꢀmode.ꢀOnceꢀtheꢀbatteryꢀchargerꢀ
50mVꢀaboveꢀV .ꢀHysteresisꢀonꢀtheꢀUVLOꢀturnsꢀoffꢀtheꢀ detectsꢀthatꢀitꢀhasꢀenteredꢀconstant-voltageꢀmode,ꢀtheꢀ
OUTꢀ
inputꢀcurrentꢀlimitꢀifꢀV ꢀdropsꢀbelowꢀ3.7Vꢀorꢀ50mVꢀbelowꢀ fourꢀhourꢀsafetyꢀtimerꢀisꢀstarted.ꢀAfterꢀtheꢀsafetyꢀtimerꢀ
BUS
V
.ꢀWhenꢀthisꢀhappens,ꢀsystemꢀpowerꢀatꢀV ꢀwillꢀbeꢀ expires,ꢀchargingꢀofꢀtheꢀbatteryꢀwillꢀterminateꢀandꢀnoꢀ
OUTꢀ
OUT
drawnꢀfromꢀtheꢀbatteryꢀviaꢀtheꢀidealꢀdiode.ꢀToꢀminimizeꢀtheꢀ moreꢀcurrentꢀwillꢀbeꢀdelivered.
possibilityꢀofꢀoscillationꢀinꢀandꢀoutꢀofꢀUVLOꢀwhenꢀusingꢀ
Automatic Recharge
resistiveꢀinputꢀsupplies,ꢀtheꢀinputꢀcurrentꢀlimitꢀisꢀreducedꢀ
asꢀV ꢀfallsꢀbelowꢀ4.45Vꢀ(typ).
BUS
Afterꢀ theꢀ batteryꢀ chargerꢀ terminates,ꢀ itꢀ willꢀ remainꢀ offꢀ
drawingꢀonlyꢀmicroamperesꢀofꢀcurrentꢀfromꢀtheꢀbattery.ꢀ
Ifꢀtheꢀportableꢀproductꢀremainsꢀinꢀthisꢀstateꢀlongꢀenough,ꢀ
Battery Charger
Theꢀ LTC3677-3ꢀ includesꢀ aꢀ constant-current/constant-ꢀ theꢀbatteryꢀwillꢀeventuallyꢀselfꢀdischarge.ꢀToꢀensureꢀthatꢀ
voltageꢀbatteryꢀchargerꢀwithꢀautomaticꢀrecharge,ꢀautomaticꢀ theꢀbatteryꢀisꢀalwaysꢀtoppedꢀoff,ꢀaꢀchargeꢀcycleꢀwillꢀau-
terminationꢀbyꢀsafetyꢀtimer,ꢀlowꢀvoltageꢀtrickleꢀcharging,ꢀ tomaticallyꢀ beginꢀ whenꢀ theꢀ batteryꢀ voltageꢀ fallsꢀ belowꢀ
badꢀcellꢀdetectionꢀandꢀthermistorꢀsensorꢀinputꢀforꢀoutꢀofꢀ
temperatureꢀchargeꢀpausing.ꢀWhenꢀaꢀbatteryꢀchargeꢀcycleꢀ thatꢀtheꢀsafetyꢀtimerꢀisꢀrunningꢀwhenꢀtheꢀbatteryꢀvoltageꢀ
begins,ꢀtheꢀbatteryꢀchargerꢀfirstꢀdeterminesꢀifꢀtheꢀbatteryꢀ fallsꢀbelowꢀV ,ꢀtheꢀtimerꢀwillꢀresetꢀbackꢀtoꢀzero.ꢀToꢀ
V
ꢀ (typicallyꢀ 4.1Vꢀ forꢀ LTC3677-3).ꢀ Inꢀ theꢀ eventꢀ
RECHRG
RECHRG
isꢀdeeplyꢀdischarged.ꢀIfꢀtheꢀbatteryꢀvoltageꢀisꢀbelowꢀV
,ꢀ preventꢀbriefꢀexcursionsꢀbelowꢀV
ꢀfromꢀresettingꢀ
TRKL
RECHRG
typicallyꢀ2.85V,ꢀanꢀautomaticꢀtrickleꢀchargeꢀfeatureꢀsetsꢀtheꢀ theꢀsafetyꢀtimer,ꢀtheꢀbatteryꢀvoltageꢀmustꢀbeꢀbelowꢀV
ꢀ
RECHRG
batteryꢀchargeꢀcurrentꢀtoꢀ10%ꢀofꢀtheꢀprogrammedꢀvalue.ꢀIfꢀ forꢀmoreꢀthanꢀ1.3ms.ꢀTheꢀchargeꢀcycleꢀandꢀsafetyꢀtimerꢀ
theꢀlowꢀvoltageꢀpersistsꢀforꢀmoreꢀthanꢀ1/2ꢀhour,ꢀtheꢀbatteryꢀ willꢀalsoꢀrestartꢀifꢀtheꢀV ꢀUVLOꢀcyclesꢀlowꢀandꢀthenꢀhighꢀ
BUS
chargerꢀautomaticallyꢀterminates.ꢀOnceꢀtheꢀbatteryꢀvoltageꢀ (e.g.,ꢀV ,ꢀisꢀremovedꢀandꢀthenꢀreplaced).
BUS
isꢀaboveꢀ2.85V,ꢀtheꢀbatteryꢀchargerꢀbeginsꢀchargingꢀinꢀfullꢀ
Charge Current
powerꢀconstant-currentꢀmode.ꢀTheꢀcurrentꢀdeliveredꢀtoꢀ
theꢀbatteryꢀwillꢀtryꢀtoꢀreachꢀ1000V/R
.ꢀDependingꢀonꢀ
PROG
Theꢀchargeꢀcurrentꢀisꢀprogrammedꢀusingꢀaꢀsingleꢀresistorꢀ
fromꢀPROGꢀtoꢀground.ꢀ1/1000thꢀofꢀtheꢀbatteryꢀchargeꢀcur-
rentꢀisꢀdeliveredꢀtoꢀPROGꢀwhichꢀwillꢀattemptꢀtoꢀservoꢀtoꢀ
1.000V.ꢀThus,ꢀtheꢀbatteryꢀchargeꢀcurrentꢀwillꢀtryꢀtoꢀreachꢀ
1000ꢀtimesꢀtheꢀcurrentꢀinꢀtheꢀPROGꢀpin.ꢀTheꢀprogramꢀ
resistorꢀandꢀtheꢀchargeꢀcurrentꢀareꢀcalculatedꢀusingꢀtheꢀ
followingꢀequations:
availableꢀinputꢀpowerꢀandꢀexternalꢀloadꢀconditions,ꢀtheꢀ
batteryꢀchargerꢀmayꢀorꢀmayꢀnotꢀbeꢀableꢀtoꢀchargeꢀatꢀtheꢀ
fullꢀprogrammedꢀrate.ꢀTheꢀexternalꢀloadꢀwillꢀalwaysꢀbeꢀ
prioritizedꢀoverꢀtheꢀbatteryꢀchargeꢀcurrent.ꢀTheꢀUSBꢀcur-
rentꢀlimitꢀprogrammingꢀwillꢀalwaysꢀbeꢀobservedꢀandꢀonlyꢀ
additionalꢀcurrentꢀwillꢀbeꢀavailableꢀtoꢀchargeꢀtheꢀbattery.ꢀ
Whenꢀsystemꢀloadsꢀareꢀlight,ꢀbatteryꢀchargeꢀcurrentꢀwillꢀ
beꢀmaximized.
1000V
ICHG
1000V
RPROG
RPROG
=
, ICHG =
ꢀ
36773f
ꢁꢁ
LTC3677-3
operaTion
Inꢀeitherꢀtheꢀconstant-currentꢀorꢀconstant-voltageꢀchargingꢀ charger.ꢀEvenꢀthoughꢀchargingꢀisꢀstoppedꢀduringꢀanꢀNTCꢀ
modes,ꢀtheꢀPROGꢀpinꢀvoltageꢀwillꢀbeꢀproportionalꢀtoꢀtheꢀ faultꢀtheꢀCHRGꢀpinꢀwillꢀstayꢀlowꢀindicatingꢀthatꢀchargingꢀ
actualꢀchargeꢀcurrentꢀdeliveredꢀtoꢀtheꢀbattery.ꢀTherefore,ꢀ isꢀnotꢀcomplete.ꢀ
theꢀactualꢀchargeꢀcurrentꢀcanꢀbeꢀdeterminedꢀatꢀanyꢀtimeꢀ
byꢀmonitoringꢀtheꢀPROGꢀpinꢀvoltageꢀandꢀusingꢀtheꢀfol-
lowingꢀequation:
Battery Charger Stability Considerations
TheꢀLTC3677-3’sꢀbatteryꢀchargerꢀcontainsꢀbothꢀaꢀconstant-
voltageꢀandꢀaꢀconstant-currentꢀcontrolꢀloop.ꢀTheꢀconstant-
voltageꢀloopꢀisꢀstableꢀwithoutꢀanyꢀcompensationꢀwhenꢀaꢀ
batteryꢀisꢀconnectedꢀwithꢀlowꢀimpedanceꢀleads.ꢀExcessiveꢀ
leadꢀlength,ꢀhowever,ꢀmayꢀaddꢀenoughꢀseriesꢀinductanceꢀ
toꢀrequireꢀaꢀbypassꢀcapacitorꢀofꢀatꢀleastꢀ1µFꢀfromꢀBATꢀtoꢀ
GND.ꢀFurthermore,ꢀaꢀ4.7µFꢀcapacitorꢀinꢀseriesꢀwithꢀaꢀ0.2Ωꢀ
toꢀ1ΩꢀresistorꢀfromꢀBATꢀtoꢀGNDꢀisꢀrequiredꢀtoꢀkeepꢀrippleꢀ
voltageꢀlowꢀwhenꢀtheꢀbatteryꢀisꢀdisconnected.
VPROG
RPROG
IBAT
=
•1000
ꢀ
Inꢀmanyꢀcases,ꢀtheꢀactualꢀbatteryꢀchargeꢀcurrent,ꢀI ,ꢀwillꢀ
BATꢀ
beꢀlowerꢀthanꢀI ꢀdueꢀtoꢀlimitedꢀinputꢀcurrentꢀavailableꢀandꢀ
CHG
prioritizationꢀwithꢀtheꢀsystemꢀloadꢀdrawnꢀfromꢀV
.
OUTꢀ
Thermal Regulation
Highꢀvalue,ꢀlowꢀESRꢀmultilayerꢀceramicꢀchipꢀcapacitorsꢀ
reduceꢀtheꢀconstant-voltageꢀloopꢀphaseꢀmargin,ꢀpossiblyꢀ
resultingꢀinꢀinstability.ꢀCeramicꢀcapacitorsꢀupꢀtoꢀ22µFꢀmayꢀ
beꢀusedꢀinꢀparallelꢀwithꢀaꢀbattery,ꢀbutꢀlargerꢀceramicsꢀshouldꢀ
beꢀdecoupledꢀwithꢀ0.2Ωꢀtoꢀ1Ωꢀofꢀseriesꢀresistance.
ToꢀpreventꢀthermalꢀdamageꢀtoꢀtheꢀICꢀorꢀsurroundingꢀcompo-
nents,ꢀanꢀinternalꢀthermalꢀfeedbackꢀloopꢀwillꢀautomaticallyꢀ
decreaseꢀtheꢀprogrammedꢀchargeꢀcurrentꢀifꢀtheꢀdieꢀtem-
peratureꢀrisesꢀtoꢀapproximatelyꢀ110°C.ꢀThermalꢀregulationꢀ
protectsꢀtheꢀLTC3677-3ꢀfromꢀexcessiveꢀtemperatureꢀdueꢀtoꢀ
highꢀpowerꢀoperationꢀorꢀhighꢀambientꢀthermalꢀconditionsꢀ
andꢀallowsꢀtheꢀuserꢀtoꢀpushꢀtheꢀlimitsꢀofꢀtheꢀpowerꢀhandlingꢀ
capabilityꢀwithꢀaꢀgivenꢀcircuitꢀboardꢀdesignꢀwithoutꢀriskꢀ
ofꢀdamagingꢀtheꢀLTC3677-3ꢀorꢀexternalꢀcomponents.ꢀTheꢀ
benefitꢀofꢀtheꢀLTC3677-3ꢀthermalꢀregulationꢀloopꢀisꢀthatꢀ
chargeꢀcurrentꢀcanꢀbeꢀsetꢀaccordingꢀtoꢀactualꢀconditionsꢀ
ratherꢀthanꢀworst-caseꢀconditionsꢀwithꢀtheꢀassuranceꢀthatꢀ
theꢀbatteryꢀchargerꢀwillꢀautomaticallyꢀreduceꢀtheꢀcurrentꢀ
inꢀworst-caseꢀconditions.
Inꢀconstant-currentꢀmode,ꢀtheꢀPROGꢀpinꢀisꢀinꢀtheꢀfeed-
backꢀloopꢀratherꢀthanꢀtheꢀbatteryꢀvoltage.ꢀBecauseꢀofꢀtheꢀ
additionalꢀ poleꢀ createdꢀ byꢀ anyꢀ PROGꢀ pinꢀ capacitance,ꢀ
capacitanceꢀonꢀthisꢀpinꢀmustꢀbeꢀkeptꢀtoꢀaꢀminimum.ꢀWithꢀ
noꢀadditionalꢀcapacitanceꢀonꢀtheꢀPROGꢀpin,ꢀtheꢀbatteryꢀ
chargerꢀisꢀstableꢀwithꢀprogramꢀresistorꢀvaluesꢀasꢀhighꢀ
asꢀ 25k.ꢀ However,ꢀ additionalꢀ capacitanceꢀ onꢀ thisꢀ nodeꢀ
reducesꢀtheꢀmaximumꢀallowedꢀprogramꢀresistor.ꢀTheꢀpoleꢀ
frequencyꢀatꢀtheꢀPROGꢀpinꢀshouldꢀbeꢀkeptꢀaboveꢀ100kHz.ꢀ
Therefore,ꢀifꢀtheꢀPROGꢀpinꢀhasꢀaꢀparasiticꢀcapacitance,ꢀ
Charge Status Indication
C
,ꢀtheꢀfollowingꢀequationꢀshouldꢀbeꢀusedꢀtoꢀcalculateꢀ
PROG
theꢀmaximumꢀresistanceꢀvalueꢀforꢀR
:
PROG
TheꢀCHRGꢀpinꢀindicatesꢀtheꢀstatusꢀofꢀtheꢀbatteryꢀcharger.ꢀ
Anꢀopen-drainꢀoutput,ꢀtheꢀCHRGꢀpinꢀcanꢀdriveꢀanꢀindica-
torꢀLEDꢀthroughꢀaꢀcurrentꢀlimitingꢀresistorꢀforꢀhumanꢀ
interfacingꢀorꢀsimplyꢀaꢀpull-upꢀresistorꢀforꢀmicroproces-
sorꢀinterfacing.ꢀWhenꢀchargingꢀbegins,ꢀCHRGꢀisꢀpulledꢀ
lowꢀandꢀremainsꢀlowꢀforꢀtheꢀdurationꢀofꢀaꢀnormalꢀchargeꢀ
cycle.ꢀWhenꢀchargingꢀisꢀcomplete,ꢀi.e.,ꢀtheꢀchargerꢀen-
tersꢀconstant-voltageꢀmodeꢀandꢀtheꢀchargeꢀcurrentꢀhasꢀ
droppedꢀtoꢀone-tenthꢀofꢀtheꢀprogrammedꢀvalue,ꢀtheꢀCHRGꢀ
pinꢀisꢀreleasedꢀ(highꢀimpedance).ꢀTheꢀCHRGꢀpinꢀdoesꢀnotꢀ
respondꢀtoꢀtheꢀC/10ꢀthresholdꢀifꢀtheꢀLTC3677-3ꢀisꢀinꢀinputꢀ
currentꢀlimit.ꢀThisꢀpreventsꢀfalseꢀend-of-chargeꢀindica-
tionsꢀdueꢀtoꢀinsufficientꢀpowerꢀavailableꢀtoꢀtheꢀbatteryꢀ
1
RPROG
≤
2π •100kHz •CPROG
ꢀ
NTC Thermistor and Battery Voltage Reduction
Theꢀbatteryꢀtemperatureꢀisꢀmeasuredꢀbyꢀplacingꢀaꢀnega-
tiveꢀ temperatureꢀ coefficientꢀ (NTC)ꢀ thermistorꢀ closeꢀ toꢀ
theꢀbatteryꢀpack.ꢀToꢀuseꢀthisꢀfeatureꢀconnectꢀtheꢀNTCꢀ
thermistor,ꢀR ,ꢀbetweenꢀtheꢀNTCꢀpinꢀandꢀgroundꢀandꢀaꢀ
NTC
biasꢀresistor,ꢀR
,ꢀfromꢀNTCBIASꢀtoꢀNTC.ꢀR
ꢀshouldꢀ
NOM
NOM
beꢀaꢀ1%ꢀresistorꢀwithꢀaꢀvalueꢀequalꢀtoꢀtheꢀvalueꢀofꢀtheꢀ
chosenꢀNTCꢀthermistorꢀatꢀ25°Cꢀ(R25).ꢀTheꢀLTC3677-3ꢀwillꢀ
36773f
ꢁꢂ
LTC3677-3
operaTion
pauseꢀchargingꢀwhenꢀtheꢀresistanceꢀofꢀtheꢀNTCꢀthermistorꢀ Whenꢀtheꢀchargerꢀisꢀdisabledꢀanꢀinternalꢀwatchdogꢀtimerꢀ
dropsꢀtoꢀ0.54ꢀtimesꢀtheꢀvalueꢀofꢀR25ꢀorꢀapproximatelyꢀ samplesꢀtheꢀNTCꢀthermistorꢀforꢀaboutꢀ150µsꢀeveryꢀ150msꢀ
54kꢀ(forꢀaꢀVishayꢀcurveꢀ1ꢀthermistor,ꢀthisꢀcorrespondsꢀtoꢀ andꢀwillꢀenableꢀtheꢀbatteryꢀmonitoringꢀcircuitryꢀifꢀtheꢀbat-
approximatelyꢀ40°C).ꢀIfꢀtheꢀbatteryꢀchargerꢀisꢀinꢀconstant-
teryꢀtemperatureꢀexceedsꢀtheꢀNTCꢀTOO_HOTꢀthreshold.ꢀ
voltageꢀ(float)ꢀmode,ꢀtheꢀsafetyꢀtimerꢀalsoꢀpausesꢀuntilꢀtheꢀ IfꢀaddingꢀaꢀcapacitorꢀtoꢀtheꢀNTCꢀpinꢀforꢀfilteringꢀtheꢀtimeꢀ
thermistorꢀindicatesꢀaꢀreturnꢀtoꢀaꢀvalidꢀtemperature.ꢀAsꢀtheꢀ constantꢀmustꢀbeꢀmuchꢀlessꢀthanꢀ150µsꢀsoꢀthatꢀtheꢀNTCꢀ
temperatureꢀdrops,ꢀtheꢀresistanceꢀofꢀtheꢀNTCꢀthermistorꢀ pinꢀcanꢀsettleꢀtoꢀitsꢀfinalꢀvalueꢀduringꢀtheꢀsamplingꢀperiod.ꢀ
rises.ꢀTheꢀLTC3677-3ꢀisꢀalsoꢀdesignedꢀtoꢀpauseꢀchargingꢀ Aꢀtimeꢀconstantꢀlessꢀthanꢀ10µsꢀisꢀrecommended.ꢀOnceꢀ
whenꢀtheꢀvalueꢀofꢀtheꢀNTCꢀthermistorꢀincreasesꢀtoꢀ3.25ꢀ theꢀbatteryꢀmonitoringꢀcircuitryꢀisꢀenabledꢀitꢀwillꢀremainꢀ
timesꢀtheꢀvalueꢀofꢀR25.ꢀForꢀaꢀVishayꢀcurveꢀ1ꢀthermistorꢀ enabledꢀandꢀmonitoringꢀtheꢀbatteryꢀvoltageꢀuntilꢀtheꢀbatteryꢀ
thisꢀresistance,ꢀ325k,ꢀcorrespondsꢀtoꢀapproximatelyꢀ0°C.ꢀ temperatureꢀfallsꢀbackꢀbelowꢀtheꢀdischargeꢀtemperatureꢀ
Theꢀhotꢀandꢀcoldꢀcomparatorsꢀeachꢀhaveꢀapproximatelyꢀ threshold.ꢀTheꢀbatteryꢀdischargeꢀcircuitryꢀisꢀonlyꢀenabledꢀ
3°Cꢀofꢀhysteresisꢀtoꢀpreventꢀoscillationꢀaboutꢀtheꢀtripꢀpoint.ꢀ ifꢀtheꢀbatteryꢀvoltageꢀisꢀgreaterꢀthanꢀtheꢀbatteryꢀdischargeꢀ
TheꢀtypicalꢀNTCꢀcircuitꢀisꢀshownꢀinꢀFigureꢀ3.
threshold.ꢀ
Toꢀimproveꢀsafetyꢀandꢀreliabilityꢀtheꢀbatteryꢀvoltageꢀisꢀre-
ducedꢀwhenꢀtheꢀbatteryꢀtemperatureꢀbecomesꢀexcessivelyꢀ
high.ꢀWhenꢀtheꢀresistanceꢀofꢀtheꢀNTCꢀthermistorꢀdropsꢀ
toꢀaboutꢀ0.35ꢀtimesꢀtheꢀvalueꢀofꢀR25ꢀorꢀapproximatelyꢀ
35kꢀ(forꢀaꢀVishayꢀcurveꢀ1ꢀthermistor,ꢀthisꢀcorrespondsꢀtoꢀ
approximatelyꢀ50°C)ꢀtheꢀNTCꢀenablesꢀcircuitryꢀtoꢀmoni-
torꢀtheꢀbatteryꢀvoltage.ꢀIfꢀtheꢀbatteryꢀvoltageꢀisꢀaboveꢀtheꢀ
batteryꢀdischargeꢀthresholdꢀ(aboutꢀ3.9V)ꢀthenꢀtheꢀbatteryꢀ
dischargeꢀcircuitryꢀisꢀenabledꢀandꢀdrawsꢀaboutꢀ140mAꢀfromꢀ
Alternate NTC Thermistors and Biasing
TheꢀLTC3677-3ꢀprovidesꢀtemperatureꢀqualifiedꢀchargingꢀifꢀ
aꢀgroundedꢀthermistorꢀandꢀaꢀbiasꢀresistorꢀareꢀconnectedꢀ
toꢀNTC.ꢀByꢀusingꢀaꢀbiasꢀresistorꢀwhoseꢀvalueꢀisꢀequalꢀtoꢀ
theꢀroomꢀtemperatureꢀresistanceꢀofꢀtheꢀthermistorꢀ(R25)ꢀ
theꢀupperꢀandꢀlowerꢀtemperaturesꢀareꢀpre-programmedꢀ
toꢀapproximatelyꢀ40°Cꢀandꢀ0°C,ꢀrespectivelyꢀ(assumingꢀ
aꢀVishayꢀcurveꢀ1ꢀthermistor).
theꢀbatteryꢀwhenꢀV ꢀ=ꢀ0Vꢀandꢀaboutꢀ180mAꢀwhenꢀV
ꢀ
BUS
BUS
Theꢀupperꢀandꢀlowerꢀtemperatureꢀthresholdsꢀcanꢀbeꢀad-
justedꢀbyꢀeitherꢀaꢀmodificationꢀofꢀtheꢀbiasꢀresistorꢀvalueꢀ
=ꢀ5V.ꢀTheꢀbatteryꢀdischargeꢀcurrentꢀisꢀdisabledꢀbelowꢀtheꢀ
batteryꢀdischargeꢀthreshold.ꢀ
NTCBIAS
34
LTC3677-3
TOO_COLD
NTC BLOCK
0.76 • NTCBIAS
R
NOM
–
+
100k
NTC
35
R
NTC
100k
–
+
TOO_HOT
0.35 • NTCBIAS
0.26 • NTCBIAS
+
–
BATTERY
OVERTEMP
Figure 3. Typical NTC Thermistor Circuit
36773f
ꢁꢃ
LTC3677-3
operaTion
orꢀbyꢀaddingꢀaꢀsecondꢀadjustmentꢀresistorꢀtoꢀtheꢀcircuit.ꢀ SolvingꢀtheseꢀequationsꢀforꢀR
Ifꢀonlyꢀtheꢀbiasꢀresistorꢀisꢀadjusted,ꢀthenꢀeitherꢀtheꢀupperꢀ inꢀtheꢀfollowing:
orꢀtheꢀlowerꢀthresholdꢀcanꢀbeꢀmodifiedꢀbutꢀnotꢀboth.ꢀTheꢀ
otherꢀtripꢀpointꢀwillꢀbeꢀdeterminedꢀbyꢀtheꢀcharacteristicsꢀ
ofꢀtheꢀthermistor.ꢀUsingꢀtheꢀbiasꢀresistorꢀinꢀadditionꢀtoꢀanꢀ
adjustmentꢀresistor,ꢀbothꢀtheꢀupperꢀandꢀtheꢀlowerꢀtempera-
tureꢀtripꢀpointsꢀcanꢀbeꢀindependentlyꢀprogrammedꢀwithꢀ
theꢀconstraintꢀthatꢀtheꢀdifferenceꢀbetweenꢀtheꢀupperꢀandꢀ
lowerꢀtemperatureꢀthresholdsꢀcannotꢀdecrease.ꢀExamplesꢀ
ofꢀeachꢀtechniqueꢀareꢀgivenꢀbelow.
ꢀandꢀR
ꢀresultsꢀ
NTC|COLD
NTC|HOT
ꢀ R
and
ꢀ=ꢀ0.538ꢀ•ꢀR
NTC|HOT
NOM
ꢀ R
ꢀ=ꢀ3.17ꢀ•ꢀR
NTC|COLD
NOM
ByꢀsettingꢀR
ꢀequalꢀtoꢀR25,ꢀtheꢀaboveꢀequationsꢀresultꢀ
NOM
inꢀr ꢀ=ꢀ0.538ꢀandꢀr
ꢀ=ꢀ3.17.ꢀReferencingꢀtheseꢀratiosꢀ
HOT
COLD
toꢀtheꢀVishayꢀresistance-temperatureꢀcurveꢀ1ꢀchartꢀgivesꢀaꢀ
hotꢀtripꢀpointꢀofꢀaboutꢀ40°Cꢀandꢀaꢀcoldꢀtripꢀpointꢀofꢀaboutꢀ
0°C.ꢀTheꢀdifferenceꢀbetweenꢀtheꢀhotꢀandꢀcoldꢀtripꢀpointsꢀ
isꢀapproximatelyꢀ40°C.
NTCꢀthermistorsꢀhaveꢀtemperatureꢀcharacteristicsꢀwhichꢀ
areꢀindicatedꢀonꢀresistance-temperatureꢀconversionꢀtables.ꢀ
TheꢀVishay-DaleꢀthermistorꢀNTHS0603N011-N1003F,ꢀusedꢀ
inꢀtheꢀfollowingꢀexamples,ꢀhasꢀaꢀnominalꢀvalueꢀofꢀ100kꢀ
andꢀfollowsꢀtheꢀVishayꢀcurveꢀ1ꢀresistance-temperatureꢀ
characteristic.
Byꢀusingꢀaꢀbiasꢀresistor,ꢀR
,ꢀdifferentꢀinꢀvalueꢀfromꢀ
NOM
R25,ꢀtheꢀhotꢀandꢀcoldꢀtripꢀpointsꢀcanꢀbeꢀmovedꢀinꢀeitherꢀ
direction.ꢀTheꢀtemperatureꢀspanꢀwillꢀchangeꢀsomewhatꢀdueꢀ
toꢀtheꢀnonlinearꢀbehaviorꢀofꢀtheꢀthermistor.ꢀTheꢀfollowingꢀ
equationsꢀcanꢀbeꢀusedꢀtoꢀeasilyꢀcalculateꢀaꢀnewꢀvalueꢀforꢀ
theꢀbiasꢀresistor:
Inꢀtheꢀexplanationꢀbelow,ꢀtheꢀfollowingꢀnotationꢀisꢀused.
R25ꢀ=ꢀValueꢀofꢀtheꢀthermistorꢀatꢀ25°C
rHOT
0.538
R
R
r
ꢀ=ꢀValueꢀofꢀthermistorꢀatꢀtheꢀcoldꢀtripꢀpoint
NTC|COLD
RNOM
=
•R25
ꢀ=ꢀValueꢀofꢀtheꢀthermistorꢀatꢀtheꢀhotꢀtripꢀpoint
NTC|HOT
r
ꢀ=ꢀRatioꢀofꢀR ꢀtoꢀR25
NTC|COLD
RNOM
=
COLD •R25
3.17
whereꢀ r ꢀ andꢀ r
COLD
ꢀ
r
=ꢀRatioꢀofꢀR ꢀtoꢀR25
NTC|HOT
HOTꢀ
ꢀ areꢀ theꢀ resistanceꢀ ratiosꢀ atꢀ theꢀ
HOT
COLD
desiredꢀꢀhotꢀandꢀcoldꢀtripꢀpoints.ꢀNoteꢀthatꢀtheseꢀequationsꢀ
R ꢀ=ꢀPrimaryꢀthermistorꢀbiasꢀresistorꢀ(seeꢀFigureꢀ3)
NOM
R1ꢀ=ꢀOptionalꢀtemperatureꢀrangeꢀadjustmentꢀresistorꢀ
(seeꢀFigureꢀ4)
NTCBIAS
LTC3677-3
NTC BLOCK
34
TheꢀtripꢀpointsꢀforꢀtheꢀLTC3677-3’sꢀtemperatureꢀqualifica-
0.76 • NTCBIAS
R
NOM
–
+
tionꢀareꢀinternallyꢀprogrammedꢀatꢀ0.35ꢀ•ꢀV ꢀforꢀtheꢀhotꢀ
105k
NTC
TOO_COLD
TOO_HOT
NTC
thresholdꢀandꢀ0.76ꢀ•ꢀV ꢀforꢀtheꢀcoldꢀthreshold.
NTC
35
Therefore,ꢀtheꢀhotꢀtripꢀpointꢀisꢀsetꢀwhen:
RNTC|HOT
R1
12.7k
–
+
•NTCBIAS = 0.35 •NTCBIAS
R
100k
NTC
RNOM + RNTC|HOT
0.35 • NTCBIAS
0.26 • NTCBIAS
ꢀ
andꢀtheꢀcoldꢀtripꢀpointꢀisꢀsetꢀwhen:
RNTC|COLD
+
–
BATTERY
OVERTEMP
•NTCBIAS = 0.76 •NTCBIAS
RNOM + RNTC|COLD
ꢀ
Figure 4. NTC Thermistor Circuit with Additional Bias Resistor
36773f
ꢁꢄ
LTC3677-3
operaTion
areꢀlinked.ꢀTherefore,ꢀonlyꢀoneꢀofꢀtheꢀtwoꢀtripꢀpointsꢀcanꢀ
beꢀchosen,ꢀtheꢀotherꢀisꢀdeterminedꢀbyꢀtheꢀdefaultꢀratiosꢀ
designedꢀinꢀtheꢀIC.ꢀ
Overvoltage Protection (OVP)
Theꢀ LTC3677-3ꢀ canꢀ protectꢀ itselfꢀ fromꢀ theꢀ inadvertentꢀ
applicationꢀofꢀexcessiveꢀvoltageꢀtoꢀV ꢀorꢀWALLꢀwithꢀ
BUS
justꢀtwoꢀexternalꢀcomponents:ꢀanꢀN-channelꢀMOSFETꢀandꢀ
aꢀ6.2kꢀresistor.ꢀTheꢀmaximumꢀsafeꢀovervoltageꢀmagnitudeꢀ
willꢀbeꢀdeterminedꢀbyꢀtheꢀchoiceꢀofꢀtheꢀexternalꢀN-channelꢀ
MOSFETꢀandꢀitsꢀassociatedꢀdrainꢀbreakdownꢀvoltage.ꢀ
Considerꢀanꢀexampleꢀwhereꢀaꢀ60°Cꢀhotꢀtripꢀpointꢀisꢀdesired.ꢀ
FromꢀtheꢀVishayꢀcurveꢀ1ꢀR-Tꢀcharacteristics,ꢀr ꢀisꢀ0.2488ꢀ
HOT
atꢀ60°C.ꢀUsingꢀtheꢀaboveꢀequation,ꢀR
ꢀshouldꢀbeꢀsetꢀ
,ꢀtheꢀcoldꢀtripꢀpointꢀisꢀ
NOM
toꢀ46.4k.ꢀWithꢀthisꢀvalueꢀofꢀR
NOM
aboutꢀ16°C.ꢀNoticeꢀthatꢀtheꢀspanꢀisꢀnowꢀ44°Cꢀratherꢀthanꢀ
theꢀpreviousꢀ40°C.ꢀThisꢀisꢀdueꢀtoꢀtheꢀdecreaseꢀinꢀtem-
peratureꢀgainꢀofꢀtheꢀthermistorꢀasꢀabsoluteꢀtemperatureꢀ
increases.
Theꢀovervoltageꢀprotectionꢀmoduleꢀconsistsꢀofꢀtwoꢀpins.ꢀ
Theꢀfirst,ꢀOVSENS,ꢀisꢀusedꢀtoꢀmeasureꢀtheꢀexternallyꢀappliedꢀ
voltageꢀthroughꢀanꢀexternalꢀresistor.ꢀTheꢀsecond,ꢀOVGATE,ꢀ
isꢀanꢀoutputꢀusedꢀtoꢀdriveꢀtheꢀgateꢀpinꢀofꢀanꢀexternalꢀFET.ꢀ
TheꢀvoltageꢀatꢀOVSENSꢀwillꢀbeꢀlowerꢀthanꢀtheꢀOVPꢀinputꢀ
Theꢀupperꢀandꢀlowerꢀtemperatureꢀtripꢀpointsꢀcanꢀbeꢀinde-
pendentlyꢀprogrammedꢀbyꢀusingꢀanꢀadditionalꢀbiasꢀresistorꢀ
asꢀshownꢀinꢀFigureꢀ4.ꢀTheꢀfollowingꢀformulasꢀcanꢀbeꢀusedꢀ
voltageꢀ byꢀ (I ꢀ •ꢀ 6.2kΩ)ꢀ dueꢀ toꢀ theꢀ OVPꢀ circuit’sꢀ
OVSENS
quiescentꢀcurrent.ꢀTheꢀOVPꢀinputꢀwillꢀbeꢀ200mVꢀtoꢀ400mVꢀ
higherꢀthanꢀOVSENSꢀunderꢀnormalꢀoperatingꢀconditions.ꢀ
WhenꢀOVSENSꢀisꢀbelowꢀ6V,ꢀanꢀinternalꢀchargeꢀpumpꢀwillꢀ
driveꢀ OVGATEꢀ toꢀ approximatelyꢀ 1.88ꢀ •ꢀ OVSENS.ꢀ Thisꢀ
willꢀenhanceꢀtheꢀN-channelꢀMOSFETꢀandꢀprovideꢀaꢀlowꢀ
toꢀcomputeꢀtheꢀvaluesꢀofꢀR ꢀandꢀR1:
NOM
rCOLD –rHOT
2.714
R1= 0.536 •RNOM –rHOT •R25
RNOM
=
•R25
impedanceꢀconnectionꢀtoꢀV ꢀorꢀWALLꢀwhichꢀwill,ꢀinꢀ
BUS
ꢀ
turn,ꢀpowerꢀtheꢀLTC3677-3.ꢀIfꢀOVSENSꢀshouldꢀriseꢀaboveꢀ
6Vꢀ(6.35VꢀOVPꢀinput)ꢀdueꢀtoꢀaꢀfaultꢀorꢀuseꢀofꢀanꢀincorrectꢀ
wallꢀadapter,ꢀOVGATEꢀwillꢀbeꢀpulledꢀtoꢀGND,ꢀdisablingꢀtheꢀ
externalꢀFETꢀtoꢀprotectꢀdownstreamꢀcircuitry.ꢀWhenꢀtheꢀ
voltageꢀdropsꢀbelowꢀ6Vꢀagain,ꢀtheꢀexternalꢀFETꢀwillꢀbeꢀ
re-enabled.
Forꢀexample,ꢀtoꢀsetꢀtheꢀtripꢀpointsꢀtoꢀ0°Cꢀandꢀ45°Cꢀwithꢀ
aꢀVishayꢀcurveꢀ1ꢀthermistorꢀchoose:
3.266 – 0.4368
RNOM
=
•100k = 104.2k
2.714
ꢀ
theꢀnearestꢀ1%ꢀvalueꢀisꢀ105k.
Inꢀ anꢀ overvoltageꢀ condition,ꢀ theꢀ OVSENSꢀ pinꢀ willꢀ beꢀ
clampedꢀ atꢀ 6V.ꢀ Theꢀ externalꢀ 6.2kꢀ resistorꢀ mustꢀ beꢀ
sizedꢀ appropriatelyꢀ toꢀ dissipateꢀ theꢀ resultantꢀ power.ꢀ
Forꢀexample,ꢀaꢀ1/10Wꢀ6.2kꢀresistorꢀcanꢀhaveꢀatꢀmostꢀ
ꢀ R1ꢀ=ꢀ0.536ꢀ•ꢀ105kꢀ–ꢀ0.4368ꢀ•ꢀ100kꢀ=ꢀ12.6k
theꢀnearestꢀ1%ꢀvalueꢀisꢀ12.7k.ꢀTheꢀfinalꢀsolutionꢀisꢀshownꢀ
inꢀFigureꢀ4ꢀandꢀresultsꢀinꢀanꢀupperꢀtripꢀpointꢀofꢀ45°Cꢀandꢀ
aꢀlowerꢀtripꢀpointꢀofꢀ0°C.
√P
ꢀ•ꢀ6.2kꢀ=ꢀ24Vꢀappliedꢀacrossꢀitsꢀterminals.ꢀWithꢀtheꢀ
MAX
6VꢀatꢀOVSENS,ꢀtheꢀmaximumꢀovervoltageꢀmagnitudeꢀthatꢀ
thisꢀresistorꢀcanꢀwithstandꢀisꢀ30V.ꢀAꢀ1/4Wꢀ6.2kꢀresistorꢀ
raisesꢀthisꢀvalueꢀtoꢀ45V.ꢀ
TheꢀchargeꢀpumpꢀoutputꢀonꢀOVGATEꢀhasꢀlimitedꢀoutputꢀ
driveꢀcapability.ꢀCareꢀmustꢀbeꢀtakenꢀtoꢀavoidꢀleakageꢀonꢀ
thisꢀpin,ꢀasꢀitꢀmayꢀadverselyꢀaffectꢀoperation.ꢀ
36773f
ꢁꢅ
LTC3677-3
operaTion
Dual Input Overvoltage Protection
Reverse Input Voltage Protection
TheꢀLTC3677-3ꢀcanꢀalsoꢀbeꢀeasilyꢀprotectedꢀagainstꢀtheꢀ
ItꢀisꢀpossibleꢀtoꢀprotectꢀbothꢀV ꢀandꢀWALLꢀfromꢀover-
BUS
voltageꢀdamageꢀwithꢀseveralꢀadditionalꢀcomponents,ꢀasꢀ applicationꢀofꢀreverseꢀvoltageꢀasꢀshownꢀinꢀFigureꢀ6.ꢀD1ꢀ
shownꢀinꢀFigureꢀ5.ꢀSchottkyꢀdiodesꢀD1ꢀandꢀD2ꢀpassꢀtheꢀ andꢀR1ꢀareꢀnecessaryꢀtoꢀlimitꢀtheꢀmaximumꢀVGSꢀseenꢀbyꢀ
largerꢀofꢀV1ꢀandꢀV2ꢀtoꢀR1ꢀandꢀOVSENS.ꢀIfꢀeitherꢀV1ꢀorꢀV2ꢀ MP1ꢀduringꢀpositiveꢀovervoltageꢀevents.ꢀD1’sꢀbreakdownꢀ
exceedsꢀ6VꢀplusꢀV
,ꢀOVGATEꢀwillꢀbeꢀpulledꢀtoꢀ voltageꢀmustꢀbeꢀsafelyꢀbelowꢀMP1’sꢀBVGS.ꢀTheꢀcircuitꢀ
F(SCHOTTKY)
GNDꢀandꢀbothꢀtheꢀWALLꢀandꢀUSBꢀinputsꢀwillꢀbeꢀprotected.ꢀ shownꢀinꢀFigureꢀ6ꢀoffersꢀforwardꢀvoltageꢀprotectionꢀupꢀ
Eachꢀinputꢀisꢀprotectedꢀupꢀtoꢀtheꢀdrain-sourceꢀbreakdown,ꢀ toꢀMN1’sꢀBVDSSꢀandꢀreverseꢀvoltageꢀprotectionꢀupꢀtoꢀ
BVDSS,ꢀofꢀMN1ꢀandꢀMN2.ꢀR1ꢀmustꢀalsoꢀbeꢀratedꢀforꢀtheꢀ
powerꢀdissipatedꢀduringꢀmaximumꢀovervoltage.ꢀSeeꢀtheꢀ
OvervoltageꢀProtectionꢀsectionꢀforꢀanꢀexplanationꢀofꢀthisꢀ
calculation.ꢀTableꢀ2ꢀshowsꢀsomeꢀN-channelꢀMOSFETsꢀthatꢀ
maybeꢀsuitableꢀforꢀovervoltageꢀprotection.
MP1’sꢀBVDSS.
MP1
MN1
USB/WALL
ADAPTER
V
BUS
C1
D1
LTC3677-3
R1
500k
Table 2. Recommended Overvoltage FETs
R2
6.2k
OVGATE
OVSENS
N-CHANNEL
MOSFET
BVDSS
R
ON
PACKAGE
36773 F06
Si1472DH
Si2302ADS
Si2306BDS
Si2316BDS
IRLML2502
30V
20V
30V
30V
20V
82mΩꢀ
60mΩ
65mΩ
80mΩ
35mΩ
SC70-6
SOT-23
SOT-23
SOT-23
SOT-23
D1: 5.6V ZENER
MP1: Si2323 DS, BVDSS = 20V
V
BUS
V
BUS
POSITIVE PROTECTION UP TO BVDSS OF MN1
NEGATIVE PROTECTION UP TO BVDSS OF MP1
Figure 6. Dual Polarity Voltage Protection
LOW DROPOUT LINEAR REGULATOR OPERATION
LDO Operation and Voltage Programming
MN1
MN2
WALL
LTC3677-3
V1
V2
OVGATE
TheꢀLTC3677-3ꢀcontainsꢀtwoꢀ150mAꢀadjustableꢀoutputꢀ
LDOꢀregulators.ꢀTheꢀfirstꢀLDOꢀ(LDO1)ꢀisꢀalwaysꢀonꢀandꢀ
V
BUS
D2
D1
R1
C1
willꢀ beꢀ enabledꢀ wheneverꢀ V ꢀ isꢀ greaterꢀ thanꢀ V
ꢀ
OUT
OUT
UVLO.ꢀ Theꢀ secondꢀ LDOꢀ (LDO2)ꢀ isꢀ controlledꢀ byꢀ theꢀ
pushbuttonꢀandꢀisꢀtheꢀfirstꢀsupplyꢀtoꢀsequenceꢀupꢀinꢀre-
sponseꢀtoꢀpushbuttonꢀapplication.ꢀBothꢀLDOsꢀareꢀdisabledꢀ
OVSENS
36773 F05
whenꢀV ꢀisꢀlessꢀthanꢀV ꢀUVLOꢀandꢀLDO2ꢀisꢀfurtherꢀ
OUT
OUT
Figure 5. Dual Input Overvoltage Protection
disabledꢀwhenꢀtheꢀpushbuttonꢀcircuityꢀisꢀinꢀtheꢀpowerꢀ
downꢀorꢀpowerꢀoffꢀstates.ꢀBothꢀLDOsꢀcontainꢀaꢀsoft-startꢀ
functionꢀtoꢀlimitꢀinrushꢀcurrentꢀwhenꢀenabled.ꢀTheꢀsoft-startꢀ
functionꢀworksꢀbyꢀrampingꢀupꢀtheꢀLDOꢀreferenceꢀoverꢀaꢀ
200µsꢀperiodꢀ(typical)ꢀwhenꢀtheꢀLDOꢀisꢀenabled.
WhenꢀdisabledꢀallꢀLDOꢀcircuitryꢀisꢀpoweredꢀoffꢀleavingꢀ
onlyꢀaꢀfewꢀnanoampsꢀofꢀleakageꢀcurrentꢀonꢀtheꢀLDOꢀsup-
ply.ꢀBothꢀLDOꢀoutputsꢀareꢀindividuallyꢀpulledꢀtoꢀgroundꢀ
throughꢀinternalꢀresistorsꢀwhenꢀdisabled.
36773f
ꢁꢆ
LTC3677-3
operaTion
TheꢀpowerꢀgoodꢀstatusꢀbitsꢀofꢀLDO1ꢀandꢀLDO2ꢀareꢀavail-
step-downꢀswitchingꢀregulatorsꢀalsoꢀincludeꢀsoft-startꢀtoꢀ
limitꢀinrushꢀcurrentꢀwhenꢀpoweringꢀon,ꢀshort-circuitꢀcur-
rentꢀprotection,ꢀandꢀswitchꢀnodeꢀslewꢀlimitingꢀcircuitryꢀtoꢀ
reduceꢀEMIꢀradiation.ꢀNoꢀexternalꢀcompensationꢀcompo-
nentsꢀareꢀrequiredꢀforꢀtheꢀswitchingꢀregulators.ꢀSwitchingꢀ
regulatorsꢀ1ꢀandꢀ2ꢀ(Buck1ꢀandꢀBuck2)ꢀareꢀsequencedꢀupꢀ
andꢀdownꢀtogetherꢀthroughꢀtheꢀpushbuttonꢀinterfaceꢀ(seeꢀ
theꢀPushbuttonꢀInterfaceꢀsectionꢀforꢀmoreꢀinformation),ꢀ
whileꢀBuck3ꢀhasꢀanꢀindividualꢀenableꢀpinꢀ(EN3)ꢀthatꢀisꢀac-
tiveꢀwhenꢀtheꢀpushbuttonꢀisꢀinꢀtheꢀpower-upꢀorꢀpower-onꢀ
states.ꢀBuck3ꢀisꢀdisabledꢀinꢀtheꢀpowerꢀdownꢀandꢀpowerꢀoffꢀ
states.ꢀItꢀisꢀrecommendedꢀthatꢀtheꢀstep-downꢀswitchingꢀ
2
ableꢀinꢀI Cꢀthroughꢀtheꢀread-backꢀregistersꢀPGLDO[1]ꢀandꢀ
PGLDO[2]ꢀforꢀLDO1ꢀandꢀLDO2ꢀrespectively.ꢀTheꢀpowerꢀ
goodꢀcomparatorsꢀforꢀbothꢀLDOsꢀareꢀsampledꢀwhenꢀtheꢀ
2
2
I CꢀportꢀreceivesꢀtheꢀcorrectꢀI Cꢀreadꢀaddress.
Figureꢀ7ꢀshowsꢀtheꢀLDOꢀapplicationꢀcircuit.ꢀTheꢀfull-scaleꢀ
outputꢀvoltageꢀforꢀeachꢀLDOꢀisꢀprogrammedꢀusingꢀaꢀresistorꢀ
dividerꢀfromꢀtheꢀLDOꢀoutputꢀ(LDO1ꢀorꢀLDO2)ꢀconnectedꢀ
toꢀtheꢀfeedbackꢀpinsꢀ(LDO1_FBꢀorꢀLDO2_FB)ꢀsuchꢀthat:
R1
R2
VLDOx = 0.8V •
+ 1
ꢀ
regulatorꢀinputꢀsuppliesꢀ(V ꢀandꢀV )ꢀbeꢀconnectedꢀtoꢀtheꢀ
IN12
IN3
Forꢀstability,ꢀeachꢀLDOꢀoutputꢀmustꢀbeꢀbypassedꢀtoꢀgroundꢀ
withꢀaꢀminimumꢀ1μFꢀceramicꢀcapacitorꢀ(C ).
systemꢀsupplyꢀpinꢀ(V ).ꢀThisꢀisꢀrecommendedꢀbecauseꢀ
OUT
OUT
theꢀundervoltageꢀlockoutꢀcircuitꢀonꢀtheꢀV ꢀpinꢀ(V
ꢀ
OUT
OUT
UVLO)ꢀdisablesꢀtheꢀstep-downꢀswitchingꢀregulatorsꢀwhenꢀ
V
INLDOx
MP
theꢀV ꢀvoltageꢀdropsꢀbelowꢀtheꢀV ꢀUVLOꢀthreshold.ꢀIfꢀ
OUT
OUT
drivingꢀtheꢀstep-downꢀswitchingꢀregulatorꢀinputꢀsuppliesꢀ
0
1
LDOxEN
fromꢀ aꢀ voltageꢀ otherꢀ thanꢀ V ꢀ theꢀ regulatorsꢀ shouldꢀ
OUT
LDOx
LDOx
OUTPUT
notꢀbeꢀoperatedꢀoutsideꢀtheꢀspecifiedꢀoperatingꢀrangeꢀasꢀ
operationꢀisꢀnotꢀguaranteedꢀbeyondꢀthisꢀrange.
R1
C
OUT
LDOx_FB
0.8V
Output Voltage Programming
R2
GND
Figureꢀ8ꢀshowsꢀtheꢀstep-downꢀswitchingꢀregulatorꢀap-
plicationꢀcircuit.ꢀTheꢀfull-scaleꢀoutputꢀvoltageꢀforꢀeachꢀ
step-downꢀswitchingꢀregulatorꢀisꢀprogrammedꢀusingꢀaꢀ
resistorꢀdividerꢀfromꢀtheꢀstep-downꢀswitchingꢀregulatorꢀ
outputꢀ connectedꢀ toꢀ theꢀ feedbackꢀ pinsꢀ (FB1,ꢀ FB2ꢀ andꢀ
FB3)ꢀsuchꢀthat:
36773 F07
Figure 7. LDO Application Circuit
STEP-DOWN SWITCHING REGULATOR OPERATION
Introduction
R1
R2
VOUTx = 0.8V •
+ 1
ꢀ
TheꢀLTC3677-3ꢀincludesꢀthreeꢀ2.25MHzꢀconstant-frequencyꢀ
currentꢀmodeꢀstep-downꢀswitchingꢀregulatorsꢀprovidingꢀ
500mA,ꢀ500mAꢀandꢀ800mAꢀeach.ꢀAllꢀstep-downꢀswitch-
ingꢀregulatorsꢀcanꢀbeꢀprogrammedꢀforꢀaꢀminimumꢀoutputꢀ
voltageꢀofꢀ0.8Vꢀandꢀcanꢀbeꢀusedꢀtoꢀpowerꢀaꢀmicrocontrollerꢀ
core,ꢀmicrocontrollerꢀI/O,ꢀmemoryꢀorꢀotherꢀlogicꢀcircuitry.ꢀ
Allꢀstep-downꢀswitchingꢀregulatorsꢀsupportꢀ100%ꢀdutyꢀ
cycleꢀoperationꢀ(lowꢀdropoutꢀmode)ꢀwhenꢀtheꢀinputꢀvolt-
ageꢀdropsꢀveryꢀcloseꢀtoꢀtheꢀoutputꢀvoltageꢀandꢀareꢀalsoꢀ
capableꢀofꢀBurstꢀModeꢀoperationꢀforꢀhighestꢀefficienciesꢀ
atꢀlightꢀloads.ꢀBurstꢀModeꢀoperationꢀisꢀindividuallyꢀselect-
ableꢀforꢀeachꢀstep-downꢀswitchingꢀregulatorꢀthroughꢀtheꢀ
V
IN
EN
MP
L
SWx
MODE
SLEW
PWM
CONTROL
V
OUTx
MN
C
OUT
C
R1
FB
FBx
0.8V
R2
GND
36773 F08
Figure 8. Step-Down Switching Regulator Application Circuit
2
I CꢀregisterꢀbitsꢀBK1BRST,ꢀBK2BRSTꢀandꢀBK3BRST.ꢀTheꢀ
36773f
ꢁꢇ
LTC3677-3
operaTion
TypicalꢀvaluesꢀforꢀR1ꢀareꢀinꢀtheꢀrangeꢀofꢀ40kꢀtoꢀ1M.ꢀTheꢀ PWMꢀoperationꢀandꢀhystereticꢀcontrolꢀasꢀaꢀfunctionꢀofꢀ
capacitorꢀC ꢀcancelsꢀtheꢀpoleꢀcreatedꢀbyꢀfeedbackꢀresis- theꢀloadꢀcurrent.ꢀAtꢀlightꢀloadsꢀtheꢀstep-downꢀswitch-
FB
torsꢀandꢀtheꢀinputꢀcapacitanceꢀofꢀtheꢀFBꢀpinꢀandꢀalsoꢀhelpsꢀ ingꢀregulatorsꢀcontrolꢀtheꢀinductorꢀcurrentꢀdirectlyꢀandꢀ
toꢀimproveꢀtransientꢀresponseꢀforꢀoutputꢀvoltagesꢀmuchꢀ useꢀaꢀhystereticꢀcontrolꢀloopꢀtoꢀminimizeꢀbothꢀnoiseꢀ
greaterꢀthanꢀ0.8V.ꢀAꢀvarietyꢀofꢀcapacitorꢀsizesꢀcanꢀbeꢀusedꢀ andꢀswitchingꢀlosses.ꢀWhileꢀoperatingꢀinꢀBurstꢀModeꢀ
forꢀC ꢀbutꢀaꢀvalueꢀofꢀ10pFꢀisꢀrecommendedꢀforꢀmostꢀap-
operation,ꢀtheꢀoutputꢀcapacitorꢀisꢀchargedꢀtoꢀaꢀvoltageꢀ
FB
plications.ꢀExperimentationꢀwithꢀcapacitorꢀsizesꢀbetweenꢀ slightlyꢀhigherꢀthanꢀtheꢀregulationꢀpoint.ꢀTheꢀstep-downꢀ
2pFꢀandꢀ22pFꢀmayꢀyieldꢀimprovedꢀtransientꢀresponse.
switchingꢀregulatorꢀthenꢀgoesꢀintoꢀsleepꢀmode,ꢀduringꢀ
whichꢀtheꢀoutputꢀcapacitorꢀprovidesꢀtheꢀloadꢀcurrent.ꢀInꢀ
sleepꢀmode,ꢀmostꢀofꢀtheꢀswitchingꢀregulator’sꢀcircuitryꢀ
isꢀ poweredꢀ down,ꢀ helpingꢀ conserveꢀ batteryꢀ power.ꢀ
Whenꢀtheꢀoutputꢀvoltageꢀdropsꢀbelowꢀaꢀpre-determinedꢀ
value,ꢀtheꢀstep-downꢀswitchingꢀregulatorꢀcircuitryꢀisꢀ
poweredꢀonꢀandꢀanotherꢀburstꢀcycleꢀbegins.ꢀTheꢀsleepꢀ
timeꢀdecreasesꢀasꢀtheꢀloadꢀcurrentꢀincreases.ꢀBeyondꢀ
aꢀ certainꢀ loadꢀ currentꢀ pointꢀ (aboutꢀ 1/4ꢀ ratedꢀ outputꢀ
loadꢀcurrent)ꢀtheꢀstep-downꢀswitchingꢀregulatorsꢀwillꢀ
switchꢀtoꢀaꢀlowꢀnoiseꢀconstant-frequencyꢀPWMꢀmodeꢀ
ofꢀoperation,ꢀmuchꢀtheꢀsameꢀasꢀpulse-skippingꢀopera-
tionꢀatꢀhighꢀloads.ꢀ
Operating Modes
Theꢀstep-downꢀswitchingꢀregulatorsꢀincludeꢀtwoꢀpossibleꢀ
operatingꢀmodesꢀtoꢀmeetꢀtheꢀnoise/powerꢀneedsꢀofꢀaꢀvarietyꢀ
ofꢀapplications.ꢀInꢀpulse-skippingꢀmode,ꢀanꢀinternalꢀlatchꢀ
isꢀsetꢀatꢀtheꢀstartꢀofꢀeveryꢀcycle,ꢀwhichꢀturnsꢀonꢀtheꢀmainꢀ
P-channelꢀMOSFETꢀswitch.ꢀDuringꢀeachꢀcycle,ꢀaꢀcurrentꢀ
comparatorꢀcomparesꢀtheꢀpeakꢀinductorꢀcurrentꢀtoꢀtheꢀ
outputꢀofꢀanꢀerrorꢀamplifier.ꢀTheꢀoutputꢀofꢀtheꢀcurrentꢀ
comparatorꢀresetsꢀtheꢀinternalꢀlatch,ꢀwhichꢀcausesꢀtheꢀmainꢀ
P-channelꢀMOSFETꢀswitchꢀtoꢀturnꢀoffꢀandꢀtheꢀN-channelꢀ
MOSFETꢀsynchronousꢀrectifierꢀtoꢀturnꢀon.ꢀTheꢀN-channelꢀ
MOSFETꢀsynchronousꢀrectifierꢀturnsꢀoffꢀatꢀtheꢀendꢀofꢀtheꢀ
2.25MHzꢀcycleꢀorꢀifꢀtheꢀcurrentꢀthroughꢀtheꢀN-channelꢀ
MOSFETꢀsynchronousꢀrectifierꢀdropsꢀtoꢀzero.ꢀUsingꢀthisꢀ
methodꢀofꢀoperation,ꢀtheꢀerrorꢀamplifierꢀadjustsꢀtheꢀpeakꢀ
inductorꢀcurrentꢀtoꢀdeliverꢀtheꢀrequiredꢀoutputꢀpower.ꢀAllꢀ
necessaryꢀ compensationꢀ isꢀ internalꢀ toꢀ theꢀ step-downꢀ
switchingꢀregulatorꢀrequiringꢀonlyꢀaꢀsingleꢀceramicꢀoutputꢀ
capacitorꢀforꢀstability.ꢀAtꢀlightꢀloadsꢀinꢀpulse-skippingꢀmode,ꢀ
theꢀinductorꢀcurrentꢀmayꢀreachꢀzeroꢀonꢀeachꢀpulseꢀwhichꢀ
willꢀturnꢀoffꢀtheꢀN-channelꢀMOSFETꢀsynchronousꢀrectifier.ꢀ
Inꢀthisꢀcase,ꢀtheꢀswitchꢀnodeꢀ(SW1,ꢀSW2ꢀorꢀSW3)ꢀgoesꢀ
highꢀimpedanceꢀandꢀtheꢀswitchꢀnodeꢀvoltageꢀwillꢀring.ꢀThisꢀ
Forꢀ applicationsꢀ thatꢀ canꢀ tolerateꢀ someꢀ outputꢀ rippleꢀ
atꢀlowꢀoutputꢀcurrents,ꢀBurstꢀModeꢀoperationꢀprovidesꢀ
betterꢀefficiencyꢀthanꢀpulse-skippingꢀatꢀlightꢀloads.ꢀTheꢀ
step-downꢀ switchingꢀ regulatorsꢀ allowꢀ modeꢀ transitionꢀ
on-the-fly,ꢀprovidingꢀseamlessꢀtransitionꢀbetweenꢀmodesꢀ
evenꢀunderꢀload.ꢀThisꢀallowsꢀtheꢀuserꢀtoꢀswitchꢀbackꢀandꢀ
forthꢀbetweenꢀmodesꢀtoꢀreduceꢀoutputꢀrippleꢀorꢀincreaseꢀ
lowꢀcurrentꢀefficiencyꢀasꢀneeded.ꢀBurstꢀModeꢀoperationꢀ
isꢀindividuallyꢀselectableꢀforꢀeachꢀstep-downꢀswitchingꢀ
2
regulatorꢀthroughꢀtheꢀI CꢀregisterꢀbitsꢀBK1BRST,ꢀBK2BRSTꢀ
andꢀBK3BRST.
isꢀdiscontinuousꢀoperation,ꢀandꢀisꢀnormalꢀbehaviorꢀforꢀaꢀ Shutdown
switchingꢀregulator.ꢀAtꢀveryꢀlightꢀloadsꢀinꢀpulse-skippingꢀ
Theꢀstep-downꢀswitchingꢀregulatorsꢀ(Buck1,ꢀBuck2ꢀandꢀ
mode,ꢀtheꢀstep-downꢀswitchingꢀregulatorsꢀwillꢀautomati-
callyꢀskipꢀpulsesꢀasꢀneededꢀtoꢀmaintainꢀoutputꢀregulation.ꢀ
Buck3)ꢀareꢀshutꢀdownꢀwhenꢀtheꢀpushbuttonꢀcircuitryꢀisꢀinꢀ
theꢀpower-downꢀorꢀpower-offꢀstate.ꢀStep-downꢀswitchingꢀ
regulatorꢀ3ꢀ(Buck3)ꢀcanꢀalsoꢀbeꢀshutꢀdownꢀbyꢀbringingꢀtheꢀ
EN3ꢀinputꢀlow.ꢀInꢀshutdownꢀallꢀcircuitryꢀinꢀtheꢀstep-downꢀ
switchingꢀregulatorꢀisꢀdisconnectedꢀfromꢀtheꢀswitchingꢀ
regulatorꢀinputꢀsupplyꢀleavingꢀonlyꢀaꢀfewꢀnanoampsꢀofꢀ
leakageꢀcurrent.ꢀTheꢀstep-downꢀswitchingꢀregulatorꢀout-
putsꢀareꢀindividuallyꢀpulledꢀtoꢀgroundꢀthroughꢀinternalꢀ10kꢀ
Atꢀhighꢀdutyꢀcycleꢀ(V
ꢀapproachingꢀV )ꢀitꢀisꢀpossibleꢀ
OUTX
INX
forꢀtheꢀinductorꢀcurrentꢀtoꢀreverseꢀatꢀlightꢀloadsꢀcausingꢀ
theꢀsteppedꢀdownꢀswitchingꢀregulatorꢀtoꢀoperateꢀcontinu-
ously.ꢀWhenꢀoperatingꢀcontinuously,ꢀregulationꢀandꢀlowꢀ
noiseꢀoutputꢀvoltageꢀareꢀmaintained,ꢀbutꢀinputꢀoperatingꢀ
currentꢀwillꢀincreaseꢀtoꢀaꢀfewꢀmilliamps.ꢀ
Inꢀ Burstꢀ Modeꢀ operation,ꢀ theꢀ step-downꢀ switchingꢀ resistorsꢀonꢀtheꢀswitchꢀpinꢀ(SW1,ꢀSW2ꢀorꢀSW3)ꢀwhenꢀinꢀ
regulatorsꢀautomaticallyꢀswitchꢀbetweenꢀfixedꢀfrequencyꢀ shutdown.
36773f
ꢁꢈ
LTC3677-3
operaTion
Dropout Operation
Slew Rate Control
Itꢀisꢀpossibleꢀforꢀaꢀstep-downꢀswitchingꢀregulator’sꢀinputꢀ
voltageꢀtoꢀapproachꢀitsꢀprogrammedꢀoutputꢀvoltageꢀ(e.g.,ꢀ
aꢀbatteryꢀvoltageꢀofꢀ3.4Vꢀwithꢀaꢀprogrammedꢀoutputꢀvolt-
ageꢀofꢀ3.3V).ꢀWhenꢀthisꢀhappens,ꢀtheꢀP-ChannelꢀMOSFETꢀ
switchꢀdutyꢀcycleꢀincreasesꢀuntilꢀitꢀisꢀturnedꢀonꢀcontinu-
ouslyꢀatꢀ100%.ꢀInꢀthisꢀdropoutꢀcondition,ꢀtheꢀrespectiveꢀ
outputꢀvoltageꢀequalsꢀtheꢀregulator’sꢀinputꢀvoltageꢀminusꢀ
theꢀvoltageꢀdropsꢀacrossꢀtheꢀinternalꢀP-channelꢀMOSFETꢀ
andꢀtheꢀinductor.
Theꢀ step-downꢀ switchingꢀ regulatorsꢀ containꢀ patentedꢀ
circuitryꢀtoꢀlimitꢀtheꢀslewꢀrateꢀofꢀtheꢀswitchꢀnodeꢀ(SW1,ꢀ
SW2ꢀandꢀSW3).ꢀThisꢀnewꢀcircuitryꢀisꢀdesignedꢀtoꢀtransi-
tionꢀtheꢀswitchꢀnodeꢀoverꢀaꢀperiodꢀofꢀaꢀfewꢀnanoseconds,ꢀ
significantlyꢀreducingꢀradiatedꢀEMIꢀandꢀconductedꢀsupplyꢀ
noiseꢀwhileꢀmaintainingꢀhighꢀefficiency.ꢀSinceꢀslowingꢀtheꢀ
slewꢀrateꢀofꢀtheꢀswitchꢀnodesꢀcausesꢀefficiencyꢀloss,ꢀtheꢀ
slewꢀrateꢀofꢀtheꢀstep-downꢀswitchingꢀregulatorsꢀisꢀadjust-
2
ableꢀviaꢀtheꢀI CꢀregistersꢀSLEWCTL1ꢀandꢀSLEWCTL2.ꢀThisꢀ
allowsꢀtheꢀuserꢀtoꢀoptimizeꢀefficiencyꢀorꢀEMIꢀasꢀnecessaryꢀ
withꢀfourꢀdifferentꢀslewꢀrateꢀsettings.ꢀTheꢀpowerꢀupꢀdefaultꢀ
isꢀtheꢀfastestꢀslewꢀrateꢀ(highestꢀefficiency)ꢀsetting.ꢀFiguresꢀ
9ꢀandꢀ10ꢀshowꢀtheꢀefficiencyꢀandꢀpowerꢀlossꢀgraphꢀforꢀ
Buck3ꢀprogrammedꢀforꢀ1.2Vꢀandꢀ2.5Vꢀoutputs.ꢀNoteꢀthatꢀ
theꢀ powerꢀ lossꢀ curvesꢀ remainꢀ fairlyꢀ constantꢀ forꢀ bothꢀ
graphsꢀyetꢀchangingꢀtheꢀslewꢀrateꢀhasꢀaꢀlargerꢀeffectꢀonꢀ
theꢀ1.2Vꢀoutputꢀefficiency.ꢀThisꢀisꢀmainlyꢀbecauseꢀforꢀaꢀ
givenꢀoutputꢀcurrentꢀtheꢀ2.5Vꢀoutputꢀisꢀdeliveringꢀmoreꢀ
thanꢀ2xꢀtheꢀpowerꢀthanꢀtheꢀ1.2Vꢀoutput.ꢀEfficiencyꢀwillꢀ
alwaysꢀdecreaseꢀandꢀshowꢀmoreꢀvariationꢀtoꢀslewꢀrateꢀasꢀ
theꢀprogrammedꢀoutputꢀvoltageꢀisꢀdecreased.
Soft-Start Operation
Soft-startꢀisꢀaccomplishedꢀbyꢀgraduallyꢀincreasingꢀtheꢀpeakꢀ
inductorꢀcurrentꢀforꢀeachꢀstep-downꢀswitchingꢀregulatorꢀ
overꢀaꢀ500μsꢀperiod.ꢀThisꢀallowsꢀeachꢀoutputꢀtoꢀriseꢀslowly,ꢀ
helpingꢀminimizeꢀinrushꢀcurrentꢀrequiredꢀtoꢀchargeꢀupꢀtheꢀ
switchingꢀregulatorꢀoutputꢀcapacitor.ꢀAꢀsoft-startꢀcycleꢀ
occursꢀwheneverꢀaꢀgivenꢀswitchingꢀregulatorꢀisꢀenabled.ꢀ
Aꢀsoft-startꢀcycleꢀisꢀnotꢀtriggeredꢀbyꢀchangingꢀoperatingꢀ
modes.ꢀ Thisꢀ allowsꢀ seamlessꢀ outputꢀ transitionꢀ whenꢀ
activelyꢀchangingꢀbetweenꢀoperatingꢀmodes.
100
90
80
70
60
50
40
30
20
10
0
1000
100
10
100
90
80
70
60
50
40
30
20
10
0
1000
100
10
Burst Mode
OPERATION
IN
Burst Mode
OPERATION
IN
1
1
V
= 3.8V
V
= 3.8V
SW[1:0] =
SW[1:0] =
00
01
10
11
00
01
10
11
0.1
0.1
0.01
0.001
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
I
(µA)
I
(µA)
OUT3
OUT3
36773 F09
36773 F10
Figure 9. VOUT3 (1.2V) Efficiency and Power Loss vs IOUT3
Figure 10. VOUT3 (2.5V) Efficiency and Power Loss vs IOUT3
36773f
ꢂ0
LTC3677-3
operaTion
Low Supply Operation
upꢀtoꢀ500mAꢀofꢀoutputꢀcurrentꢀwhileꢀaꢀ3.3μHꢀinductorꢀisꢀ
suggestedꢀforꢀstep-downꢀswitchingꢀregulatorsꢀprovidingꢀ
upꢀtoꢀ800mA.ꢀLargerꢀvalueꢀinductorsꢀreduceꢀrippleꢀcurrent,ꢀ
whichꢀimprovesꢀoutputꢀrippleꢀvoltage.ꢀLowerꢀvalueꢀinduc-
torsꢀresultꢀinꢀhigherꢀrippleꢀcurrentꢀandꢀimprovedꢀtransientꢀ
responseꢀtime,ꢀbutꢀwillꢀreduceꢀtheꢀavailableꢀoutputꢀcurrent.ꢀ
Toꢀmaximizeꢀefficiency,ꢀchooseꢀanꢀinductorꢀwithꢀaꢀlowꢀDCꢀ
resistance.ꢀForꢀaꢀ1.2Vꢀoutput,ꢀefficiencyꢀisꢀreducedꢀaboutꢀ
2%ꢀforꢀ100mΩꢀseriesꢀresistanceꢀatꢀ400mAꢀloadꢀcurrent,ꢀ
andꢀaboutꢀ2%ꢀforꢀ300mΩꢀseriesꢀresistanceꢀatꢀ100mAꢀloadꢀ
current.ꢀChooseꢀanꢀinductorꢀwithꢀaꢀDCꢀcurrentꢀratingꢀatꢀ
leastꢀ1.5ꢀtimesꢀlargerꢀthanꢀtheꢀmaximumꢀloadꢀcurrentꢀtoꢀ
ensureꢀthatꢀtheꢀinductorꢀdoesꢀnotꢀsaturateꢀduringꢀnormalꢀ
operation.ꢀIfꢀoutputꢀshortꢀcircuitꢀisꢀaꢀpossibleꢀcondition,ꢀ
theꢀinductorꢀshouldꢀbeꢀratedꢀtoꢀhandleꢀtheꢀmaximumꢀpeakꢀ
currentꢀspecifiedꢀforꢀtheꢀstep-downꢀconverters.ꢀDifferentꢀ
coreꢀmaterialsꢀandꢀshapesꢀwillꢀchangeꢀtheꢀsize/currentꢀ
andꢀprice/currentꢀrelationshipꢀofꢀanꢀinductor.ꢀToroidꢀorꢀ
shieldedꢀpotꢀcoresꢀinꢀferriteꢀorꢀPermalloyꢀmaterialsꢀareꢀ
smallꢀandꢀdoꢀnotꢀradiateꢀmuchꢀenergy,ꢀbutꢀgenerallyꢀcostꢀ
moreꢀ thanꢀ powderedꢀ ironꢀ coreꢀ inductorsꢀ withꢀ similarꢀ
electricalꢀcharacteristics.ꢀInductorsꢀthatꢀareꢀveryꢀthinꢀorꢀ
haveꢀaꢀveryꢀsmallꢀvolumeꢀtypicallyꢀhaveꢀmuchꢀhigherꢀcoreꢀ
andꢀDCRꢀlosses,ꢀandꢀwillꢀnotꢀgiveꢀtheꢀbestꢀefficiency.ꢀTheꢀ
AnꢀundervoltageꢀlockoutꢀcircuitꢀonꢀV ꢀ(V ꢀUVLO)ꢀ
OUT
OUT
shutsꢀdownꢀtheꢀstep-downꢀswitchingꢀregulatorsꢀwhenꢀV
ꢀ
OUT
dropsꢀbelowꢀaboutꢀ2.7V.ꢀItꢀisꢀrecommendedꢀthatꢀtheꢀstep-
downꢀswitchingꢀregulatorꢀinputꢀsuppliesꢀ(V
,ꢀV )ꢀbeꢀ
IN12 IN3
connectedꢀtoꢀtheꢀpowerꢀpathꢀoutputꢀ(V )ꢀdirectly.ꢀThisꢀ
OUT
UVLOꢀpreventsꢀtheꢀstep-downꢀswitchingꢀregulatorsꢀfromꢀ
operatingꢀatꢀlowꢀsupplyꢀvoltagesꢀwhereꢀlossꢀofꢀregula-
tionꢀorꢀotherꢀundesirableꢀoperationꢀmayꢀoccur.ꢀIfꢀdrivingꢀ
theꢀstep-downꢀswitchingꢀregulatorꢀinputꢀsuppliesꢀfromꢀ
aꢀvoltageꢀotherꢀthanꢀtheꢀV ꢀpin,ꢀtheꢀregulatorsꢀshouldꢀ
OUT
notꢀbeꢀoperatedꢀoutsideꢀtheꢀspecifiedꢀoperatingꢀrangeꢀasꢀ
operationꢀisꢀnotꢀguaranteedꢀbeyondꢀthisꢀrange.
Inductor Selection
Manyꢀdifferentꢀsizesꢀandꢀshapesꢀofꢀinductorsꢀareꢀavailableꢀ
fromꢀnumerousꢀmanufacturers.ꢀChoosingꢀtheꢀrightꢀinductorꢀ
fromꢀsuchꢀaꢀlargeꢀselectionꢀofꢀdevicesꢀcanꢀbeꢀoverwhelming,ꢀ
butꢀfollowingꢀaꢀfewꢀbasicꢀguidelinesꢀwillꢀmakeꢀtheꢀselectionꢀ
processꢀmuchꢀsimpler.ꢀTheꢀstep-downꢀswitchingꢀregula-
torsꢀareꢀdesignedꢀtoꢀworkꢀwithꢀinductorsꢀinꢀtheꢀrangeꢀofꢀ
2.2μHꢀtoꢀ10μH.ꢀForꢀmostꢀapplicationsꢀaꢀ4.7μHꢀinductorꢀisꢀ
suggestedꢀforꢀstep-downꢀswitchingꢀregulatorsꢀprovidingꢀ
Table 3. Recommended Inductors for Step-Down Switching Regulators
INDUCTOR TYPE
L (μH)
MAX I (A)
MAX DCR (Ω)
SIZE in mm (L × W × H) MANUFACTURER
DC
DB318Cꢀ
4.7ꢀ
3.3ꢀ
4.7ꢀ
3.3ꢀ
4.7ꢀ
3.3
1.07ꢀ
1.20ꢀ
0.79ꢀ
0.90ꢀ
1.15ꢀ
1.37
0.1ꢀ
0.07ꢀ
Tokoꢀ
www.toko.com
3.8ꢀ×ꢀ3.8ꢀ×ꢀ1.8ꢀ
3.8ꢀ×ꢀ3.8ꢀ×ꢀ1.8ꢀ
3.6ꢀ×ꢀ3.6ꢀ×ꢀ1.2ꢀ
3.6ꢀ×ꢀ3.6ꢀ×ꢀ1.2ꢀ
3.0ꢀ×ꢀ2.8ꢀ×ꢀ1.2ꢀ
3.0ꢀ×ꢀ2.8ꢀ×ꢀ1.2
ꢀ
D312Cꢀ
ꢀ
DE2812C
0.24ꢀ
0.20ꢀ
0.13*ꢀ
0.105*
CDRH3D16ꢀ
4.7ꢀ
3.3ꢀ
4.7ꢀ
3.3ꢀ
4.7
0.9ꢀ
1.1ꢀ
0.5ꢀ
0.6ꢀ
0.75
0.11ꢀ
0.085ꢀ
0.17ꢀ
0.123ꢀ
0.19
Sumidaꢀ
www.sumida.com
4ꢀ×ꢀ4ꢀ×ꢀ1.8ꢀ
4ꢀ×ꢀ4ꢀ×ꢀ1.8ꢀ
3.2ꢀ×ꢀ3.2ꢀ×ꢀ1.2ꢀ
3.2ꢀ×ꢀ3.2ꢀ×ꢀ1.2ꢀ
4.9ꢀ×ꢀ4.9ꢀ×ꢀ1
ꢀ
CDRH2D11ꢀ
ꢀ
CLS4D09
SD3118ꢀ
4.7ꢀ
3.3ꢀ
4.7ꢀ
3.3ꢀ
4.7ꢀ
3.3ꢀ
4.7ꢀ
3.3
1.3ꢀ
1.59ꢀ
0.8ꢀ
0.97ꢀ
1.29ꢀ
1.42ꢀ
1.08ꢀ
1.31
0.162ꢀ
0.113ꢀ
Cooperꢀ
www.cooperet.com
3.1ꢀ×ꢀ3.1ꢀ×ꢀ1.8ꢀ
3.1ꢀ×ꢀ3.1ꢀ×ꢀ1.8ꢀ
3.1ꢀ×ꢀ3.1ꢀ×ꢀ1.2ꢀ
3.1ꢀ×ꢀ3.1ꢀ×ꢀ1.2ꢀ
5.2ꢀ×ꢀ5.2ꢀ×ꢀ1.2ꢀ
5.2ꢀ×ꢀ5.2ꢀ×ꢀ1.2ꢀ
5.2ꢀ×ꢀ5.2ꢀ×ꢀ1.0ꢀ
5.2ꢀ×ꢀ5.2ꢀ×ꢀ1.0
ꢀ
SD3112ꢀ
0.246ꢀ
ꢀ
0.165ꢀ
SD12ꢀ
ꢀ
0.117*ꢀ
0.104*ꢀ
0.153*ꢀ
0.108*
SD10
LPS3015
4.7ꢀ
3.3
1.1ꢀ
1.3
0.2ꢀ
0.13
CoilꢀCraftꢀ
www.coilcraft.com
3.0ꢀ×ꢀ3.0ꢀ×ꢀ1.5ꢀ
3.0ꢀ×ꢀ3.0ꢀ×ꢀ1.5
*TypicalꢀDCR
36773f
ꢂꢀ
LTC3677-3
operaTion
2
choiceꢀofꢀwhichꢀstyleꢀinductorꢀtoꢀuseꢀoftenꢀdependsꢀmoreꢀ I C OPERATION
onꢀtheꢀpriceꢀversusꢀsize,ꢀperformance,ꢀandꢀanyꢀradiatedꢀ
2
I C Interface
EMIꢀrequirementsꢀthanꢀonꢀwhatꢀtheꢀstep-downꢀswitchingꢀ
regulatorsꢀrequiresꢀtoꢀoperate.ꢀTheꢀinductorꢀvalueꢀalsoꢀhasꢀ
anꢀeffectꢀonꢀBurstꢀModeꢀoperation.ꢀLowerꢀinductorꢀvaluesꢀ
willꢀcauseꢀBurstꢀModeꢀswitchingꢀfrequencyꢀtoꢀincrease.ꢀ
Tableꢀ3ꢀshowsꢀseveralꢀinductorsꢀthatꢀworkꢀwellꢀwithꢀtheꢀ
step-downꢀswitchingꢀregulators.ꢀTheseꢀinductorsꢀofferꢀaꢀ
goodꢀcompromiseꢀinꢀcurrentꢀrating,ꢀDCRꢀandꢀphysicalꢀ
size.ꢀConsultꢀeachꢀmanufacturerꢀforꢀdetailedꢀinformationꢀ
onꢀtheirꢀentireꢀselectionꢀofꢀinductors.
TheꢀLTC3677-3ꢀmayꢀcommunicateꢀwithꢀaꢀbusꢀmasterꢀus-
ingꢀtheꢀstandardꢀI Cꢀ2-wireꢀinterface.ꢀTheꢀtimingꢀdiagramꢀ
2
inꢀFigureꢀ11ꢀshowsꢀtheꢀrelationshipꢀofꢀtheꢀsignalsꢀonꢀtheꢀ
bus.ꢀTheꢀtwoꢀbusꢀlines,ꢀSDAꢀandꢀSCL,ꢀmustꢀbeꢀHIGHꢀ
whenꢀtheꢀbusꢀisꢀnotꢀinꢀuse.ꢀExternalꢀpull-upꢀresistorsꢀorꢀ
currentꢀsources,ꢀsuchꢀasꢀtheꢀLTC1694ꢀSMBusꢀaccelerator,ꢀ
areꢀrequiredꢀonꢀtheseꢀlines.ꢀTheꢀLTC3677-3ꢀisꢀbothꢀaꢀslaveꢀ
2
receiverꢀandꢀslaveꢀtransmitter.ꢀTheꢀI Cꢀcontrolꢀsignals,ꢀ
SDAꢀandꢀSCLꢀareꢀscaledꢀinternallyꢀtoꢀtheꢀDV ꢀsupply.ꢀ
CC
Input/Output Capacitor Selection
DV ꢀshouldꢀbeꢀconnectedꢀtoꢀtheꢀsameꢀpowerꢀsupplyꢀasꢀ
CC
LowꢀESRꢀ(equivalentꢀseriesꢀresistance)ꢀceramicꢀcapacitorsꢀ theꢀbusꢀpull-upꢀresistors.
shouldꢀbeꢀusedꢀatꢀbothꢀstep-downꢀswitchingꢀregulatorꢀ
outputsꢀasꢀwellꢀasꢀatꢀeachꢀstep-downꢀswitchingꢀregulatorꢀ
inputꢀsupply.ꢀOnlyꢀX5RꢀorꢀX7Rꢀceramicꢀcapacitorsꢀshouldꢀ
beꢀusedꢀbecauseꢀtheyꢀretainꢀtheirꢀcapacitanceꢀoverꢀwiderꢀ
voltageꢀandꢀtemperatureꢀrangesꢀthanꢀotherꢀceramicꢀtypes.ꢀ
Aꢀ10μFꢀoutputꢀcapacitorꢀisꢀsufficientꢀforꢀtheꢀstep-downꢀ
switchingꢀregulatorꢀoutputs.ꢀForꢀgoodꢀtransientꢀresponseꢀ
andꢀstabilityꢀtheꢀoutputꢀcapacitorꢀforꢀstep-downꢀswitchingꢀ
regulatorsꢀshouldꢀretainꢀatꢀleastꢀ4μFꢀofꢀcapacitanceꢀoverꢀ
operatingꢀtemperatureꢀandꢀbiasꢀvoltage.ꢀEachꢀswitchingꢀ
regulatorꢀinputꢀsupplyꢀshouldꢀbeꢀbypassedꢀwithꢀaꢀ2.2μFꢀ
capacitor.ꢀConsultꢀwithꢀcapacitorꢀmanufacturersꢀforꢀde-
tailedꢀinformationꢀonꢀtheirꢀselectionꢀandꢀspecificationsꢀ
ofꢀ ceramicꢀ capacitors.ꢀ Manyꢀ manufacturersꢀ nowꢀ offerꢀ
2
TheꢀI CꢀportꢀhasꢀanꢀundervoltageꢀlockoutꢀonꢀtheꢀDV ꢀpin.ꢀ
CC
2
WhenꢀDV ꢀisꢀbelowꢀapproximatelyꢀ1V,ꢀtheꢀI Cꢀserialꢀportꢀ
isꢀclearedꢀandꢀregistersꢀareꢀsetꢀtoꢀtheꢀdefaultꢀconfigura-
tionꢀofꢀallꢀzeros.
CC
2
I C Bus Speed
2
TheꢀI Cꢀportꢀisꢀdesignedꢀtoꢀbeꢀoperatedꢀatꢀspeedsꢀofꢀupꢀ
toꢀ400kHz.ꢀItꢀhasꢀbuilt-inꢀtimingꢀdelaysꢀtoꢀensureꢀcorrectꢀ
2
operationꢀwhenꢀaddressedꢀfromꢀanꢀI Cꢀcompliantꢀmasterꢀ
device.ꢀItꢀalsoꢀcontainsꢀinputꢀfiltersꢀdesignedꢀtoꢀsuppressꢀ
glitchesꢀshouldꢀtheꢀbusꢀbecomeꢀcorrupted.
2
I C START and STOP Conditions
veryꢀthinꢀ(<1mmꢀtall)ꢀceramicꢀcapacitorsꢀidealꢀforꢀuseꢀinꢀ Aꢀbusꢀmasterꢀsignalsꢀtheꢀbeginningꢀofꢀcommunicationsꢀbyꢀ
height-restrictedꢀdesigns.ꢀTableꢀ4ꢀshowsꢀaꢀlistꢀofꢀseveralꢀ transmittingꢀaꢀSTARTꢀcondition.ꢀAꢀSTARTꢀconditionꢀisꢀgen-
ceramicꢀcapacitorꢀmanufacturers.
eratedꢀbyꢀtransitioningꢀSDAꢀfromꢀHIGHꢀtoꢀLOWꢀwhileꢀSCLꢀisꢀ
HIGH.ꢀTheꢀmasterꢀmayꢀtransmitꢀeitherꢀtheꢀslaveꢀwriteꢀorꢀtheꢀ
slaveꢀreadꢀaddress.ꢀOnceꢀdataꢀisꢀwrittenꢀtoꢀtheꢀLTC3677-3,ꢀ
theꢀmasterꢀmayꢀtransmitꢀaꢀSTOPꢀconditionꢀwhichꢀcom-
mandsꢀtheꢀLTC3677-3ꢀtoꢀactꢀuponꢀitsꢀnewꢀcommandꢀset.ꢀAꢀ
STOPꢀconditionꢀisꢀsentꢀbyꢀtheꢀmasterꢀbyꢀtransitioningꢀSDAꢀ
fromꢀLOWꢀtoꢀHIGHꢀwhileꢀSCLꢀisꢀHIGH.ꢀTheꢀbusꢀisꢀthenꢀfreeꢀ
Table 4. Ceramic Capacitor Manufacturers
AVX
www.avxcorp.com
Murata
www.murata.com
www.t-yuden.com
www.vishay.com
www.tdk.com
TaiyoꢀYuden
VishayꢀSiliconix
TDK
2
forꢀcommunicationꢀwithꢀanotherꢀI Cꢀdevice.
2
I C Byte Format
EachꢀbyteꢀsentꢀtoꢀorꢀreceivedꢀfromꢀtheꢀLTC3677-3ꢀmustꢀ
beꢀ8ꢀbitsꢀlongꢀfollowedꢀbyꢀanꢀextraꢀclockꢀcycleꢀforꢀtheꢀ
acknowledgeꢀbit.ꢀTheꢀdataꢀshouldꢀbeꢀsentꢀtoꢀtheꢀLTC3677-3ꢀ
mostꢀsignificantꢀbitꢀ(MSB)ꢀfirst.
36773f
ꢂꢁ
LTC3677-3
operaTion
DATA BYTE A
DATA BYTE B
ADDRESS
WR
0
0
0
0
1
0
0
1
1
A7
A6
A5
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
START
STOP
SDA
SCL
0
0
0
1
0
0
0
8
ACK
9
ACK
9
ACK
9
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SDA
t
t
t
BUF
SU, DAT
SU, STA
t
t
t
t
LOW
HD, STA
SU, STO
HD, DAT
SCL
t
t
t
HD, STA
HIGH
SP
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
t
t
f
r
36773 F11
Figure 11. I2C Timing Diagram
2
2
I C Acknowledge
I C Slave Address
Theꢀacknowledgeꢀsignalꢀisꢀusedꢀforꢀhandshakingꢀbetweenꢀ TheꢀLTC3677-3ꢀrespondsꢀtoꢀaꢀ7-bitꢀaddressꢀwhichꢀhasꢀ
theꢀmasterꢀandꢀtheꢀslave.ꢀWhenꢀtheꢀLTC3677-3ꢀisꢀwrittenꢀ beenꢀfactoryꢀprogrammedꢀtoꢀb’0001001[R/W]’.ꢀTheꢀLSBꢀ
toꢀ(writeꢀaddress),ꢀitꢀacknowledgesꢀitsꢀwriteꢀaddressꢀasꢀ ofꢀtheꢀaddressꢀbyte,ꢀknownꢀasꢀtheꢀread/writeꢀbit,ꢀshouldꢀbeꢀ
wellꢀasꢀtheꢀsubsequentꢀtwoꢀdataꢀbytes.ꢀWhenꢀreadꢀfromꢀ 0ꢀwhenꢀwritingꢀdataꢀtoꢀtheꢀLTC3677-3ꢀandꢀ1ꢀwhenꢀreadingꢀ
(readꢀaddress),ꢀtheꢀLTC3677-3ꢀacknowledgesꢀitsꢀreadꢀad-
dataꢀfromꢀit.ꢀConsideringꢀtheꢀaddressꢀanꢀ8-bitꢀword,ꢀthenꢀ
dressꢀonly.ꢀTheꢀbusꢀmasterꢀshouldꢀacknowledgeꢀreceiptꢀ theꢀwriteꢀaddressꢀisꢀ0x12ꢀandꢀtheꢀreadꢀaddressꢀisꢀ0x13.ꢀ
ofꢀinformationꢀfromꢀtheꢀLTC3677-3.
TheꢀLTC3677-3ꢀwillꢀacknowledgeꢀbothꢀitsꢀreadꢀandꢀwriteꢀ
address.
Anꢀacknowledgeꢀ(activeꢀLOW)ꢀgeneratedꢀbyꢀtheꢀLTC3677-3ꢀ
letsꢀtheꢀmasterꢀknowꢀthatꢀtheꢀlatestꢀbyteꢀofꢀinformationꢀwasꢀ
received.ꢀTheꢀacknowledgeꢀrelatedꢀclockꢀpulseꢀisꢀgeneratedꢀ
byꢀtheꢀmaster.ꢀTheꢀmasterꢀreleasesꢀtheꢀSDAꢀlineꢀ(HIGH)ꢀ
duringꢀtheꢀacknowledgeꢀclockꢀcycle.ꢀTheꢀLTC3677-3ꢀpullsꢀ
downꢀtheꢀSDAꢀlineꢀduringꢀtheꢀwriteꢀacknowledgeꢀclockꢀ
pulseꢀsoꢀthatꢀitꢀisꢀaꢀstableꢀLOWꢀduringꢀtheꢀHIGHꢀperiodꢀ
ofꢀthisꢀclockꢀpulse.
2
I C Sub-Addressed Writing
TheꢀLTC3677-3ꢀhasꢀoneꢀcommandꢀregisterꢀforꢀcontrolꢀ
2
input.ꢀItꢀisꢀaccessedꢀbyꢀtheꢀI Cꢀportꢀviaꢀaꢀsub-addressedꢀ
writingꢀsystem.
Eachꢀ writeꢀ cycleꢀ ofꢀ theꢀ LTC3677-3ꢀ consistsꢀ ofꢀ exactlyꢀ
threeꢀbytes.ꢀTheꢀfirstꢀbyteꢀisꢀalwaysꢀtheꢀLTC3677-3’sꢀwriteꢀ
address.ꢀ Theꢀ secondꢀ byteꢀ representsꢀ theꢀ LTC3677-3’sꢀ
sub-address.ꢀTheꢀsub-addressꢀisꢀaꢀpointerꢀwhichꢀdirectsꢀ
theꢀsubsequentꢀdataꢀbyteꢀwithinꢀtheꢀLTC3677-3.ꢀTheꢀthirdꢀ
byteꢀconsistsꢀofꢀtheꢀdataꢀtoꢀbeꢀwrittenꢀtoꢀtheꢀlocationꢀ
pointedꢀtoꢀbyꢀtheꢀsub-address.ꢀTheꢀLTC3677-3ꢀcontainsꢀ
controlꢀregistersꢀatꢀonlyꢀsub-addressꢀlocationꢀ0x00.ꢀSub-
addressesꢀoutsideꢀ0x00ꢀshouldꢀnotꢀbeꢀwrittenꢀtoꢀasꢀtheyꢀ
WhenꢀtheꢀLTC3677-3ꢀisꢀreadꢀfrom,ꢀitꢀreleasesꢀtheꢀSDAꢀlineꢀ
soꢀthatꢀtheꢀmasterꢀmayꢀacknowledgeꢀreceiptꢀofꢀtheꢀdata.ꢀ
SinceꢀtheꢀLTC3677-3ꢀonlyꢀtransmitsꢀoneꢀbyteꢀofꢀdata,ꢀaꢀ
masterꢀnotꢀacknowledgingꢀtheꢀdataꢀsentꢀbyꢀtheꢀLTC3677-3ꢀ
2
hasꢀnoꢀI Cꢀspecificꢀconsequenceꢀonꢀtheꢀoperationꢀofꢀtheꢀ
2
I Cꢀport.ꢀ
accessꢀfunctionalityꢀnotꢀavailableꢀinꢀtheꢀLTC3677-3.ꢀ
36773f
ꢂꢂ
LTC3677-3
operaTion
2
I C Bus Write Operation
allꢀbitsꢀdefaultꢀtoꢀ0.ꢀAdditionally,ꢀallꢀbitsꢀareꢀclearedꢀtoꢀ0ꢀ
whenꢀDV ꢀdropsꢀbelowꢀitsꢀundervoltageꢀlockꢀoutꢀorꢀifꢀtheꢀ
pushbuttonꢀentersꢀtheꢀpowerꢀdownꢀ(PDN)ꢀstate.
CC
TheꢀmasterꢀinitiatesꢀcommunicationꢀwithꢀtheꢀLTC3677-3ꢀ
withꢀaꢀSTARTꢀconditionꢀandꢀtheꢀLTC3677-3’sꢀwriteꢀaddress.ꢀ
IfꢀtheꢀaddressꢀmatchesꢀthatꢀofꢀtheꢀLTC3677-3,ꢀtheꢀLTC3677-3ꢀ
returnsꢀanꢀacknowledge.ꢀTheꢀmasterꢀshouldꢀthenꢀdeliverꢀ
theꢀsub-address.ꢀAgainꢀtheꢀLTC3677-3ꢀacknowledgesꢀandꢀ
theꢀcycleꢀisꢀrepeatedꢀforꢀtheꢀdataꢀbyte.ꢀTheꢀdataꢀbyteꢀisꢀ
transferredꢀtoꢀanꢀinternalꢀholdingꢀlatchꢀuponꢀtheꢀreturnꢀofꢀ
itsꢀacknowledgeꢀbyꢀtheꢀLTC3677-3.ꢀThisꢀprocedureꢀmustꢀbeꢀ
repeatedꢀforꢀeachꢀsub-addressꢀthatꢀrequiresꢀnewꢀdata.ꢀAfterꢀ
oneꢀorꢀmoreꢀcyclesꢀofꢀ[ADDRESS][SUB-ADDRESS][DATA],ꢀ
theꢀmasterꢀmayꢀterminateꢀtheꢀcommunicationꢀwithꢀaꢀSTOPꢀ
condition.ꢀAlternatively,ꢀaꢀREPEAT-STARTꢀconditionꢀcanꢀ
Tableꢀ5ꢀshowsꢀtheꢀbyteꢀofꢀdataꢀthatꢀcanꢀbeꢀwrittenꢀtoꢀatꢀ
sub-addressꢀ0x00.ꢀThisꢀbyteꢀofꢀdataꢀisꢀreferredꢀtoꢀasꢀtheꢀ
buckꢀcontrolꢀregister.ꢀ
Table 5. Buck Control Register
BUCK CONTROL
REGISTER
ADDRESS:ꢀ00010010ꢀ
SUB-ADDRESS:ꢀ00000000
BIT NAME
B0 N/A
FUNCTION
NotꢀUsed—NoꢀEffectꢀOnꢀOperation
NotꢀUsed—NoꢀEffectꢀOnꢀOperation
Buck1ꢀBurstꢀModeꢀEnable
Buck2ꢀBurstꢀModeꢀEnable
Buck2ꢀBurstꢀModeꢀEnable
B1 N/A
B2 BK1BRST
B3 BK2BRST
B4 BK3BRST
B5 SLEWCTL1
B6 SLEWCTL2
B7 N/A
2
beꢀinitiatedꢀbyꢀtheꢀmasterꢀandꢀanotherꢀchipꢀonꢀtheꢀI Cꢀbusꢀ
canꢀbeꢀaddressed.ꢀThisꢀcycleꢀcanꢀcontinueꢀindefinitelyꢀ
andꢀtheꢀLTC3677-3ꢀwillꢀrememberꢀtheꢀlastꢀinputꢀofꢀvalidꢀ
dataꢀthatꢀitꢀreceived.ꢀOnceꢀallꢀchipsꢀonꢀtheꢀbusꢀhaveꢀbeenꢀ
addressedꢀandꢀsentꢀvalidꢀdata,ꢀaꢀglobalꢀSTOPꢀcanꢀbeꢀsentꢀ
andꢀtheꢀLTC3677-3ꢀwillꢀupdateꢀitsꢀcommandꢀlatchesꢀwithꢀ
theꢀdataꢀthatꢀitꢀreceived.
BuckꢀSWꢀSlewꢀRate:ꢀ00ꢀ=ꢀ1ns,ꢀꢀ
01ꢀ=ꢀ2ns,ꢀ10ꢀ=ꢀ4ns,ꢀ11ꢀ=ꢀ8ns
NotꢀUsed—NoꢀEffectꢀOnꢀOperation
BitsꢀB2,ꢀB3,ꢀandꢀB4ꢀsetꢀtheꢀoperatingꢀmodesꢀofꢀtheꢀstep-
downꢀswitchingꢀregulatorsꢀ(bucks).ꢀWritingꢀaꢀ1ꢀtoꢀanyꢀofꢀ
theseꢀthreeꢀregistersꢀwillꢀputꢀthatꢀrespectiveꢀbuckꢀconverterꢀ
inꢀtheꢀhighꢀefficiencyꢀBurstꢀModeꢀoperation,ꢀwhileꢀaꢀ0ꢀwillꢀ
enableꢀtheꢀlowꢀnoiseꢀpulse-skippingꢀmodeꢀofꢀoperation.ꢀ
2
I C Bus Read Operation
TheꢀbusꢀmasterꢀreadsꢀtheꢀstatusꢀofꢀtheꢀLTC3677-3ꢀwithꢀ
aꢀSTARTꢀconditionꢀfollowedꢀbyꢀtheꢀLTC3677-3ꢀreadꢀad-
dress.ꢀIfꢀtheꢀreadꢀaddressꢀmatchesꢀthatꢀofꢀtheꢀLTC3677-3,ꢀ
theꢀ LTC3677-3ꢀ returnsꢀ anꢀ acknowledge.ꢀ Followingꢀ theꢀ
acknowledgementꢀofꢀtheirꢀreadꢀaddress,ꢀtheꢀLTC3677-3ꢀ
returnsꢀoneꢀbitꢀofꢀstatusꢀinformationꢀforꢀeachꢀofꢀtheꢀnextꢀ
8ꢀclockꢀcycles.ꢀAꢀSTOPꢀcommandꢀisꢀnotꢀrequiredꢀforꢀtheꢀ
busꢀreadꢀoperation.
TheꢀB5ꢀandꢀB6ꢀbitsꢀadjustꢀtheꢀslewꢀrateꢀofꢀallꢀSWꢀpinsꢀ
togetherꢀsoꢀtheyꢀallꢀslewꢀatꢀtheꢀsameꢀrate.ꢀItꢀisꢀrecom-
mendedꢀthatꢀtheꢀfastestꢀslewꢀrateꢀ(B6:B5ꢀ=ꢀ00)ꢀbeꢀusedꢀ
unlessꢀEMIꢀisꢀanꢀissueꢀinꢀtheꢀapplicationꢀasꢀslowerꢀslewꢀ
ratesꢀcauseꢀreducedꢀefficiency.ꢀ
2
I C Output Data
2
I C Input Data
Oneꢀ statusꢀ byteꢀ mayꢀ beꢀ readꢀ fromꢀ theꢀ LTC3677-3,ꢀ asꢀ
shownꢀinꢀTableꢀ6.ꢀAꢀ1ꢀreadꢀbackꢀinꢀtheꢀanyꢀofꢀtheꢀbitꢀposi-
Thereꢀisꢀoneꢀbyteꢀofꢀdataꢀthatꢀcanꢀbeꢀwrittenꢀtoꢀonꢀtheꢀ
LTC3677-3.ꢀTheꢀbyteꢀisꢀaccessedꢀthroughꢀtheꢀsub-addressꢀ
0x00.ꢀAtꢀfirstꢀpowerꢀapplicationꢀ(V ,ꢀWALLꢀorꢀBAT)ꢀ
BUS
36773f
ꢂꢃ
LTC3677-3
operaTion
tionsꢀindicatesꢀthatꢀtheꢀconditionꢀisꢀtrue.ꢀForꢀexample,ꢀ1ꢀ catesꢀthatꢀeitherꢀLDO2ꢀisꢀnotꢀenabled,ꢀorꢀthatꢀtheꢀLDO2ꢀisꢀ
readꢀbackꢀfromꢀbitꢀA3ꢀindicateꢀthatꢀLDO1ꢀisꢀenabledꢀandꢀ enabled,ꢀbutꢀisꢀoutꢀofꢀregulationꢀbyꢀmoreꢀthanꢀ8%.
regulatingꢀcorrectly.ꢀAꢀstatusꢀreadꢀfromꢀtheꢀLTC3677-3ꢀ
BitꢀA3ꢀshowsꢀtheꢀpowerꢀgoodꢀstatusꢀofꢀLDO1.ꢀAꢀ1ꢀindicatesꢀ
capturesꢀ theꢀ statusꢀ informationꢀ whenꢀ theꢀ LTC3677-3ꢀ
thatꢀLDO1ꢀisꢀenabledꢀandꢀisꢀregulatingꢀcorrectly.ꢀAꢀ0ꢀindi-
acknowledgeꢀitsꢀreadꢀaddress.ꢀ
catesꢀthatꢀeitherꢀLDO1ꢀisꢀnotꢀenabled,ꢀorꢀthatꢀtheꢀLDO1ꢀisꢀ
enabled,ꢀbutꢀisꢀoutꢀofꢀregulationꢀbyꢀmoreꢀthanꢀ8%.
Table 6. I2C READ Register
ꢀ
ADDRESS:ꢀ00010011ꢀ
BitsꢀA2ꢀandꢀA1ꢀindicateꢀtheꢀfaultꢀstatusꢀofꢀtheꢀchargerꢀ
measurementꢀcircuitꢀandꢀareꢀdecodedꢀinꢀTableꢀ6.ꢀTheꢀtooꢀ
cold/hotꢀstateꢀindicatesꢀthatꢀtheꢀthermistorꢀtemperatureꢀisꢀ
outꢀofꢀtheꢀvalidꢀchargingꢀrangeꢀ(eitherꢀbelowꢀ0°Cꢀorꢀaboveꢀ
40°Cꢀforꢀaꢀcurveꢀ1ꢀthermistor)ꢀandꢀthatꢀchargingꢀhasꢀpausedꢀ
untilꢀtheꢀbatteryꢀreturnsꢀtoꢀvalidꢀchargingꢀtemperature.ꢀTheꢀ
batteryꢀovertemperatureꢀstateꢀindicatesꢀthatꢀtheꢀbattery’sꢀ
thermistorꢀ hasꢀ reachedꢀ aꢀ criticalꢀ temperatureꢀ (aboutꢀ
50°Cꢀforꢀaꢀcurveꢀ1ꢀthermistor)ꢀandꢀthatꢀlong-termꢀbatteryꢀ
capacityꢀmayꢀbeꢀseriouslyꢀcompromisedꢀifꢀtheꢀconditionꢀ
persists.ꢀTheꢀbatteryꢀfaultꢀstateꢀindicatesꢀthatꢀanꢀattemptꢀ
wasꢀmadeꢀtoꢀchargeꢀaꢀlowꢀbatteryꢀ(typicallyꢀ<ꢀ2.85V)ꢀbutꢀ
thatꢀtheꢀlowꢀvoltageꢀconditionꢀpersistedꢀforꢀmoreꢀthanꢀ1/2ꢀ
hour.ꢀInꢀthisꢀcaseꢀchargingꢀhasꢀterminated.
STATUS REGISTER
SUB-ADDRESS:ꢀNone
BIT NAME
FUNCTION
A0 CHARGE
A1 STAT[0]
A2 STAT[1]
ChargeꢀStatusꢀ(1ꢀ=ꢀCharging)
STAT[1:0];ꢀ00ꢀ=ꢀNoꢀFaultꢀ
01ꢀ=ꢀTOOꢀCOLD/HOTꢀ
10ꢀ=ꢀBATTERYꢀOVERTEMPꢀꢀ
11ꢀ=ꢀBATTERYꢀFAULT
A3 PGLDO[1]ꢀ
A4 PGLDO[2]ꢀ
A5 PGBCK[1]ꢀ
A6 PGBCK[2]ꢀ
A7 PGBCK[3]ꢀ
LDO1ꢀPowerꢀGood
LDO2ꢀPowerꢀGood
Buck1ꢀPowerꢀGood
Buck2ꢀPowerꢀGood
Buck3ꢀPowerꢀGood
BitꢀA7ꢀshowsꢀtheꢀpowerꢀgoodꢀstatusꢀofꢀBuck3.ꢀAꢀ1ꢀindicatesꢀ
thatꢀBuck3ꢀisꢀenabledꢀandꢀisꢀregulatingꢀcorrectly.ꢀAꢀ0ꢀindi-
catesꢀthatꢀeitherꢀBuck3ꢀisꢀnotꢀenabled,ꢀorꢀthatꢀtheꢀBuck3ꢀisꢀ
enabled,ꢀbutꢀisꢀoutꢀofꢀregulationꢀbyꢀmoreꢀthanꢀ8%.
BitꢀA0ꢀindicatesꢀtheꢀstatusꢀofꢀtheꢀbatteryꢀcharger.ꢀAꢀ1ꢀ
indicatesꢀthatꢀtheꢀchargerꢀisꢀenabledꢀandꢀisꢀinꢀtheꢀcon-
stant-currentꢀ chargeꢀ state.ꢀ Inꢀ thisꢀ caseꢀ theꢀ batteryꢀ isꢀ
beingꢀchargedꢀunlessꢀtheꢀNTCꢀthermistorꢀisꢀoutsideꢀitsꢀ
validꢀchargeꢀrangeꢀinꢀwhichꢀcaseꢀchargingꢀisꢀtemporarilyꢀ
suspendedꢀbutꢀnotꢀcomplete.ꢀChargingꢀwillꢀcontinueꢀonceꢀ
theꢀbatteryꢀhasꢀreturnedꢀtoꢀaꢀvalidꢀchargingꢀtemperature.ꢀ
Aꢀ0ꢀinꢀbitꢀA0ꢀindicatesꢀthatꢀchargerꢀhasꢀreachedꢀend-of-
BitꢀA6ꢀshowsꢀtheꢀpowerꢀgoodꢀstatusꢀofꢀBuck2.ꢀAꢀ1ꢀindicatesꢀ
thatꢀBuck2ꢀisꢀenabledꢀandꢀisꢀregulatingꢀcorrectly.ꢀAꢀ0ꢀindi-
catesꢀthatꢀeitherꢀBuck2ꢀisꢀnotꢀenabled,ꢀorꢀthatꢀtheꢀBuck2ꢀisꢀ
enabled,ꢀbutꢀisꢀoutꢀofꢀregulationꢀbyꢀmoreꢀthanꢀ8%.
BitꢀA5ꢀshowsꢀtheꢀpowerꢀgoodꢀstatusꢀofꢀBuck1.ꢀAꢀ1ꢀindicatesꢀ
thatꢀBuck1ꢀisꢀenabledꢀandꢀisꢀregulatingꢀcorrectly.ꢀAꢀ0ꢀindi-
catesꢀthatꢀeitherꢀBuck1ꢀisꢀnotꢀenabled,ꢀorꢀthatꢀtheꢀBuck1ꢀisꢀ
enabled,ꢀbutꢀisꢀoutꢀofꢀregulationꢀbyꢀmoreꢀthanꢀ8%.
chargeꢀ(h )ꢀandꢀisꢀnearꢀV
ꢀorꢀthatꢀchargingꢀhasꢀbeenꢀ
FLOAT
C/10
terminated.ꢀChargingꢀcanꢀbeꢀterminatedꢀbyꢀreachingꢀtheꢀ
endꢀofꢀtheꢀchargeꢀtimerꢀorꢀbyꢀaꢀbatteryꢀfaultꢀasꢀdescribedꢀ
previously.ꢀ
BitꢀA4ꢀshowsꢀtheꢀpowerꢀgoodꢀstatusꢀofꢀLDO2.ꢀAꢀ1ꢀindicatesꢀ
thatꢀLDO2ꢀisꢀenabledꢀandꢀisꢀregulatingꢀcorrectly.ꢀAꢀ0ꢀindi-
36773f
ꢂꢄ
LTC3677-3
operaTion
PUSHBUTTON INTERFACE OPERATION
PBSTAT Operation
PBSTATꢀgoesꢀLOWꢀ50msꢀafterꢀtheꢀinitialꢀpushbuttonꢀap-
plicationꢀ(ONꢀLOW)ꢀandꢀwillꢀstayꢀlowꢀforꢀ50msꢀminimum.ꢀ
PBSTATꢀwillꢀgoꢀHIGHꢀcoincidentꢀwithꢀONꢀgoingꢀHIGHꢀunlessꢀ
ONꢀgoesꢀHIGHꢀbeforeꢀtheꢀ50msꢀminimumꢀLOWꢀtime.
State Diagram/Operation
Figureꢀ13ꢀshowsꢀtheꢀLTC3677-3ꢀpushbuttonꢀstateꢀdiagram.ꢀ
Uponꢀfirstꢀapplicationꢀofꢀpowerꢀ(V ,ꢀWALLꢀorꢀBAT)ꢀanꢀ
BUS
internalꢀpower-onꢀresetꢀ(POR)ꢀsignalꢀplacesꢀtheꢀpushbut-
tonꢀcircuitryꢀintoꢀtheꢀpower-offꢀ(POFF)ꢀstate.ꢀTheꢀfollowingꢀ Hard Reset and PGOOD Operation
eventsꢀcauseꢀtheꢀstateꢀmachineꢀtoꢀtransitionꢀoutꢀofꢀPOFFꢀ
intoꢀtheꢀpower-upꢀ(PUP)ꢀstate:
Theꢀhardꢀresetꢀeventꢀisꢀgeneratedꢀbyꢀpressingꢀandꢀholdingꢀ
theꢀpushbuttonꢀ(ONꢀinputꢀLOW)ꢀforꢀ14ꢀseconds.ꢀForꢀaꢀ
validꢀhardꢀresetꢀeventꢀtoꢀoccurꢀtheꢀinitialꢀpushbuttonꢀap-
plicationꢀmustꢀstartꢀinꢀtheꢀPUPꢀorꢀPONꢀstate.ꢀThisꢀavoidsꢀ
causingꢀaꢀhardꢀresetꢀfromꢀoccurringꢀifꢀtheꢀuserꢀhangsꢀonꢀ
theꢀpushbuttonꢀduringꢀinitialꢀpower-up.ꢀIfꢀaꢀvalidꢀhardꢀ
resetꢀeventꢀisꢀpresentꢀthenꢀtheꢀPGOODꢀoutputꢀwillꢀtransi-
tionꢀLOWꢀforꢀaboutꢀ1.8msꢀtoꢀallowꢀtheꢀmicroprocessorꢀtoꢀ
reset.ꢀTheꢀhardꢀresetꢀeventꢀdoesꢀnotꢀaffectꢀtheꢀoperatingꢀ
stateꢀorꢀregulatorꢀoperation.ꢀ
1)ꢀONꢀinputꢀLOWꢀforꢀ50msꢀ(PB50MS)
2)ꢀPWR_ONꢀinputꢀgoingꢀHIGHꢀ(PWR_ON)
UponꢀenteringꢀtheꢀPUPꢀstate,ꢀtheꢀpushbuttonꢀcircuitryꢀ
willꢀsequenceꢀupꢀLDO2,ꢀBuck1ꢀandꢀBuck2ꢀinꢀthatꢀorder.ꢀ
OneꢀsecondꢀafterꢀenteringꢀtheꢀPUPꢀstate,ꢀtheꢀpushbuttonꢀ
circuitryꢀwillꢀtransitionꢀintoꢀtheꢀpower-onꢀ(PON)ꢀstate.ꢀNoteꢀ
thatꢀtheꢀPWR_ONꢀinputꢀmustꢀbeꢀbroughtꢀHIGHꢀbeforeꢀ
enteringꢀtheꢀPONꢀstateꢀifꢀtheꢀpartꢀisꢀtoꢀremainꢀinꢀtheꢀPONꢀ
state.ꢀBuck3ꢀcanꢀbeꢀenabledꢀthroughꢀtheꢀEN3ꢀinputꢀonceꢀ
theꢀpushbuttonꢀisꢀinꢀtheꢀPUPꢀorꢀPONꢀstates.
TheꢀPGOODꢀpinꢀisꢀanꢀopen-drainꢀoutputꢀusedꢀtoꢀindicateꢀ
thatꢀBuck1,ꢀBuck2ꢀandꢀLDO1ꢀareꢀenabledꢀandꢀhaveꢀreachedꢀ
theirꢀfinalꢀregulationꢀvoltage.ꢀAꢀ230msꢀdelayꢀisꢀincludedꢀ
fromꢀtheꢀtimeꢀBuck1,ꢀBuck2ꢀandꢀLDO1ꢀreachꢀ92%ꢀofꢀtheirꢀ
regulationꢀvalueꢀtoꢀallowꢀaꢀsystemꢀcontrollerꢀampleꢀtimeꢀtoꢀ
resetꢀitself.ꢀPGOODꢀisꢀanꢀopen-drainꢀoutputꢀandꢀrequiresꢀaꢀ
pull-upꢀresistorꢀtoꢀanꢀappropriateꢀpowerꢀsource.ꢀOptimallyꢀ
theꢀpull-upꢀresistorꢀisꢀconnectedꢀtoꢀtheꢀoutputꢀofꢀBuck1,ꢀ
Buck2ꢀorꢀLDO2ꢀsoꢀthatꢀpowerꢀisꢀnotꢀdissipatedꢀwhileꢀtheꢀ
regulatorsꢀareꢀdisabled.
PWR_ONꢀgoingꢀLOW,ꢀorꢀV ꢀdroppingꢀtoꢀitsꢀundervoltageꢀ
OUT
lockoutꢀ(V ꢀUVLO)ꢀthresholdꢀwillꢀcauseꢀtheꢀstateꢀmachineꢀ
OUT
toꢀleaveꢀtheꢀPONꢀstateꢀandꢀenterꢀtheꢀpower-downꢀ(PDN)ꢀ
2
state.ꢀTheꢀPDNꢀstateꢀresetsꢀtheꢀI Cꢀregistersꢀasꢀwellꢀasꢀ
disablesꢀBuck1,ꢀBuck2ꢀandꢀLDO2ꢀtogether.ꢀBuck3ꢀisꢀalsoꢀ
disabledꢀinꢀtheꢀPDNꢀandꢀPOFFꢀstates.ꢀTheꢀoneꢀsecondꢀdelayꢀ
beforeꢀleavingꢀtheꢀpower-downꢀstateꢀallowsꢀtheꢀsuppliesꢀtoꢀ
powerꢀdownꢀcompletelyꢀbeforeꢀtheyꢀcanꢀbeꢀre-enabled.ꢀ
Pushbutton Operation and V
UVLO
OUT
PUP
AsꢀstatedꢀearlierꢀV ꢀdroppingꢀtoꢀitsꢀUVLOꢀthresholdꢀ
OUT
PB50ms +
1SEC
PWR_ON
willꢀcauseꢀtheꢀpushbuttonꢀtoꢀleaveꢀtheꢀpower-onꢀstateꢀandꢀ
enterꢀtheꢀpower-downꢀstate,ꢀthusꢀpoweringꢀdownꢀBuck1,ꢀ
Buck2,ꢀBuck3ꢀandꢀLDO2.ꢀAdditionally,ꢀLDO1ꢀisꢀdisabledꢀ
whenꢀinꢀUVLO.ꢀThus,ꢀallꢀLTC3677-3ꢀsuppliesꢀareꢀdisabledꢀ
POR
POFF
PON
UVLO +
PWR_ON
1SEC
andꢀremainꢀdisabledꢀasꢀlongꢀasꢀtheꢀV ꢀUVLOꢀconditionꢀ
OUT
PDN
exists.ꢀItꢀisꢀnotꢀpossibleꢀtoꢀpowerꢀupꢀanyꢀofꢀtheꢀLTC3677-3ꢀ
35773 F13
generatedꢀsuppliesꢀwhileꢀV ꢀisꢀbelowꢀtheꢀV ꢀUVLOꢀ
OUT
OUT
Figure 12. Pushbutton State Diagram
threshold.ꢀ
36773f
ꢂꢅ
LTC3677-3
operaTion
Power-Up via Pushbutton Timing
Power-Up via PWR_ON Timing
Theꢀ timingꢀ diagram,ꢀ Figureꢀ 13,ꢀ showsꢀ theꢀ LTC3677-3ꢀ Theꢀ timingꢀ diagram,ꢀ Figureꢀ 14,ꢀ showsꢀ theꢀ LTC3677-3ꢀ
poweringꢀupꢀthroughꢀapplicationꢀofꢀtheꢀexternalꢀpushbut- poweringꢀupꢀbyꢀdrivingꢀPWR_ONꢀHIGH.ꢀForꢀthisꢀexampleꢀ
ton.ꢀForꢀthisꢀexampleꢀtheꢀpushbuttonꢀcircuitryꢀstartsꢀinꢀ theꢀpushbuttonꢀcircuitryꢀstartsꢀinꢀtheꢀPOFFꢀstateꢀwithꢀV
ꢀ
OUT
theꢀPOFFꢀstateꢀwithꢀV ꢀnotꢀinꢀUVLOꢀandꢀBuck1,ꢀBuck2ꢀ notꢀinꢀUVLOꢀandꢀBuck1,ꢀBuck2ꢀandꢀLDO2ꢀdisabled.ꢀ50msꢀ
OUT
andꢀLDO2ꢀdisabled.ꢀPushbuttonꢀapplicationꢀ(ONꢀLOW)ꢀforꢀ afterꢀPWR_ONꢀgoesꢀHIGHꢀtheꢀpushbuttonꢀcircuitryꢀtransi-
50msꢀtransitionsꢀtheꢀpushbuttonꢀcircuitryꢀintoꢀtheꢀPUPꢀ tionsꢀintoꢀtheꢀPUPꢀstateꢀwhichꢀsequencesꢀupꢀLDO2,ꢀBuck1ꢀ
stateꢀwhichꢀsequencesꢀupꢀLDO2,ꢀBuck1ꢀandꢀBuck2ꢀinꢀthatꢀ andꢀBuck2ꢀinꢀthatꢀorder.ꢀPWR_ONꢀmustꢀbeꢀdrivenꢀhighꢀ
order.ꢀPWR_ONꢀmustꢀbeꢀdrivenꢀHIGHꢀbeforeꢀtheꢀ1ꢀsecondꢀ beforeꢀtheꢀ1ꢀsecondꢀPUPꢀperiodꢀisꢀoverꢀtoꢀkeepꢀsuppliesꢀ
PUPꢀperiodꢀisꢀoverꢀtoꢀkeepꢀsuppliesꢀup.ꢀIfꢀPWR_ONꢀisꢀ up.ꢀIfꢀPWR_ONꢀisꢀLOWꢀorꢀgoesꢀLOWꢀafterꢀtheꢀ1ꢀsecondꢀ
LOWꢀorꢀgoesꢀLOWꢀafterꢀtheꢀ1ꢀsecondꢀPUPꢀperiodꢀBuck1,ꢀ PUPꢀperiodꢀBuck1,ꢀBuck2ꢀandꢀLDO2ꢀwillꢀbeꢀshutꢀdownꢀ
Buck2,ꢀandꢀLDO2ꢀwillꢀbeꢀshutꢀdownꢀtogether.ꢀPGOODꢀisꢀ together.ꢀPGOODꢀisꢀassertedꢀonceꢀBuck1,ꢀBuck2ꢀandꢀLD01ꢀ
assertedꢀonceꢀBuck1,ꢀBuck2ꢀandꢀLDO1ꢀareꢀwithinꢀ8%ꢀofꢀ areꢀwithinꢀ8%ꢀofꢀtheirꢀregulationꢀvoltageꢀforꢀ230ms.ꢀ
theirꢀregulationꢀvoltageꢀforꢀ230ms.ꢀ
Buck3ꢀcanꢀbeꢀenabledꢀandꢀdisabledꢀatꢀanyꢀtimeꢀviaꢀEN3ꢀ
Buck3ꢀcanꢀbeꢀenabledꢀandꢀdisabledꢀatꢀanyꢀtimeꢀviaꢀEN3ꢀ onceꢀinꢀtheꢀPUPꢀorꢀPONꢀstates.ꢀ
onceꢀinꢀtheꢀPUPꢀorꢀPONꢀstates.ꢀTheꢀPWR_ONꢀinputꢀcanꢀ
Poweringꢀ upꢀ viaꢀ PWR_ONꢀ isꢀ usefulꢀ forꢀ applicationsꢀ
beꢀdrivenꢀviaꢀaꢀμP/μCꢀorꢀbyꢀoneꢀofꢀtheꢀsequencedꢀoutputsꢀ
containingꢀanꢀalwaysꢀonꢀmicrocontroller.ꢀThisꢀallowsꢀtheꢀ
throughꢀaꢀhighꢀimpedanceꢀ(100kΩꢀtyp).ꢀPBSTATꢀgoesꢀ
microcontrollerꢀtoꢀpowerꢀtheꢀapplicationꢀupꢀandꢀdownꢀ
LOWꢀ50msꢀafterꢀtheꢀinitialꢀpushbuttonꢀapplicationꢀandꢀ
forꢀhouseꢀkeepingꢀandꢀotherꢀactivitiesꢀoutsideꢀtheꢀuser’sꢀ
willꢀstayꢀLOWꢀforꢀ50msꢀminimum.ꢀPBSTATꢀwillꢀgoꢀHIGHꢀ
control.ꢀ
coincidentꢀwithꢀONꢀgoingꢀHIGHꢀunlessꢀONꢀgoesꢀHIGHꢀ
beforeꢀtheꢀ50msꢀminimumꢀLOWꢀtime.ꢀ
V
UVLO
V
UVLO
OUT
OUT
ON (PB)
ON (PB)
PBSTAT
LDO2
50ms
PBSTAT
1 SEC
PWR_ON
LDO2
14ms
50ms
14ms
BUCK1
BUCK2
PGOOD
BUCK1
BUCK2
230ms
1 SEC
230ms
PWR_ON
STATE
PGOOD
STATE
36773 F14
POFF
PUP
PON
36773 F13
POFF
PUP
PON
Figure 13. Power-Up via Pushbutton
Figure 14. Power-Up via PWR_ON
36773f
ꢂꢆ
LTC3677-3
operaTion
Power Down via Pushbutton Timing
V
UVLO Power-Down Timing
OUT
Theꢀ timingꢀ diagram,ꢀ Figureꢀ 15,ꢀ showsꢀ theꢀ LTC3677-3ꢀ IfꢀV ꢀdropsꢀbelowꢀtheꢀV ꢀUVLOꢀthreshold,ꢀtheꢀpush-
OUT
OUT
poweringꢀdownꢀbyꢀμC/μPꢀcontrol.ꢀForꢀthisꢀexampleꢀtheꢀ buttonꢀcircuitryꢀwillꢀtransitionꢀfromꢀtheꢀPONꢀstateꢀtoꢀtheꢀ
pushbuttonꢀcircuitryꢀstartsꢀinꢀtheꢀPONꢀstateꢀwithꢀV PDNꢀstate.ꢀBuck1,ꢀBuck2ꢀandꢀLDO2ꢀareꢀdisabledꢀtogetherꢀ
ꢀ
OUT
notꢀinꢀUVLOꢀandꢀBuck1,ꢀBuck2ꢀandꢀLDO2ꢀenabled.ꢀInꢀ uponꢀenteringꢀtheꢀPDNꢀstate.ꢀAfterꢀenteringꢀtheꢀPDNꢀstate,ꢀ
thisꢀcaseꢀtheꢀpushbuttonꢀisꢀappliedꢀ(ONꢀLOW)ꢀforꢀatꢀleastꢀ aꢀ1ꢀsecondꢀwaitꢀtimeꢀisꢀinitiatedꢀbeforeꢀenteringꢀtheꢀPOFFꢀ
50ms,ꢀwhichꢀgeneratesꢀaꢀlowꢀimpedanceꢀonꢀtheꢀPBSTATꢀ state.ꢀDuringꢀthisꢀ1ꢀsecondꢀtimeꢀONꢀandꢀPWR_ONꢀinputsꢀ
output.ꢀAfterꢀreceivingꢀtheꢀPBSTATꢀtheꢀμC/μPꢀwillꢀdriveꢀ areꢀignoredꢀtoꢀallowꢀallꢀLTC3677-3ꢀgeneratedꢀsuppliesꢀtoꢀ
theꢀPWR_ONꢀinputꢀLOW.ꢀ50msꢀafterꢀPWR_ONꢀgoesꢀLOWꢀ goꢀLOW.ꢀ
theꢀpushbuttonꢀcircuitryꢀwillꢀenterꢀtheꢀPDNꢀstate.ꢀBuck1,ꢀ
UponꢀenteringꢀtheꢀPDNꢀstateꢀtheꢀBuck3ꢀisꢀdisabledꢀandꢀ
Buck2ꢀandꢀLDO2ꢀareꢀdisabledꢀtogetherꢀuponꢀenteringꢀtheꢀ
PDNꢀstate.ꢀAfterꢀenteringꢀtheꢀPDNꢀstate,ꢀaꢀ1ꢀsecondꢀwaitꢀ
timeꢀisꢀinitiatedꢀbeforeꢀenteringꢀtheꢀPOFFꢀstate.ꢀDuringꢀ
thisꢀ1ꢀsecondꢀtimeꢀONꢀandꢀPWR_ONꢀinputsꢀareꢀignoredꢀ
toꢀallowꢀallꢀLTC3677-3ꢀgeneratedꢀsuppliesꢀtoꢀgoꢀLOW.ꢀ
2
theꢀI Cꢀregistersꢀareꢀcleared.ꢀLDO1ꢀisꢀalsoꢀdisabledꢀbyꢀ
theꢀV ꢀUVLOꢀandꢀstaysꢀdisabledꢀasꢀlongꢀasꢀtheꢀV
ꢀ
OUT
OUT
UVLOꢀconditionꢀremains.ꢀNoteꢀthatꢀitꢀisꢀnotꢀpossibleꢀtoꢀ
sequenceꢀanyꢀofꢀtheꢀsuppliesꢀupꢀwhileꢀtheꢀV ꢀUVLOꢀ
OUT
conditionꢀ exists.ꢀ LDO1ꢀ willꢀ beꢀ re-enabledꢀ whenꢀ theꢀ
UponꢀenteringꢀtheꢀPDNꢀstateꢀBuck3ꢀisꢀdisabledꢀandꢀtheꢀ
V
ꢀUVLOꢀconditionꢀisꢀremoved.ꢀTheꢀotherꢀsuppliesꢀ
OUT
2
I Cꢀregistersꢀareꢀcleared.ꢀHoldingꢀONꢀLOWꢀthroughꢀtheꢀ willꢀremainꢀdisabledꢀuntilꢀaꢀvalidꢀpower-upꢀpushbuttonꢀ
1ꢀsecondꢀpower-downꢀperiodꢀwillꢀnotꢀcauseꢀaꢀpower-upꢀ eventꢀtakesꢀplace.
eventꢀatꢀendꢀofꢀtheꢀ1ꢀsecondꢀperiod.ꢀTheꢀONꢀinputꢀmustꢀbeꢀ
broughtꢀHIGHꢀfollowingꢀtheꢀpower-downꢀeventꢀandꢀthenꢀ
goꢀLOWꢀagainꢀtoꢀestablishꢀaꢀvalidꢀpower-upꢀevent.ꢀ
V
UVLO
OUT
V
UVLO
1 SEC
OUT
1 SEC
ON (PB)
ON (PB)
LDO1
PBSTAT
PWR_ON
BUCK1
BUCK2
LDO2
50ms
PBSTAT
PWR_ON
BUCK1
BUCK2
LDO2
µC/µP CONTROL
50ms
PGOOD
STATE
PGOOD
STATE
PON
PDN
POFF
36773 F15
36773 F16
PON
PDN
POFF
Figure 15. Power-Down via Pushbutton
Figure 16. VOUT UVLO Power-Down
36773f
ꢂꢇ
LTC3677-3
operaTion
Hard Reset Timing
Power-Up Sequencing
HardꢀresetꢀprovidesꢀaꢀwayꢀtoꢀresetꢀtheꢀμC/μPꢀinꢀcaseꢀofꢀaꢀ Figureꢀ18ꢀshowsꢀtheꢀactualꢀpower-upꢀsequencingꢀofꢀtheꢀ
softwareꢀlockup.ꢀToꢀinitiateꢀaꢀhardꢀreset,ꢀtheꢀpushbuttonꢀisꢀ LTC3677-3.ꢀBuck1,ꢀBuck2ꢀandꢀLDO2ꢀareꢀallꢀinitiallyꢀdisabledꢀ
pressedꢀ(ONꢀLOW)ꢀandꢀheldꢀforꢀgreaterꢀthanꢀ14ꢀseconds.ꢀ (0V).ꢀOnceꢀtheꢀpushbuttonꢀhasꢀbeenꢀappliedꢀ(ONꢀLOW)ꢀ
OnceꢀtheꢀhardꢀresetꢀtimeꢀisꢀexceededꢀtheꢀPGOODꢀinputꢀ forꢀ50msꢀPBSTATꢀgoesꢀLOWꢀandꢀLDO2ꢀisꢀenabled.ꢀOnceꢀ
willꢀgoꢀLOWꢀforꢀ1.8msꢀwhichꢀresetsꢀtheꢀμC/μP.ꢀOperationꢀ enabled,ꢀLDO2ꢀslewsꢀupꢀandꢀentersꢀregulation.ꢀTheꢀactualꢀ
ofꢀtheꢀenabledꢀsuppliesꢀisꢀnotꢀeffectedꢀbyꢀtheꢀhardꢀresetꢀ slewꢀrateꢀisꢀcontrolledꢀbyꢀtheꢀsoft-startꢀfunctionꢀofꢀLDO2ꢀ
event.ꢀAllꢀenabledꢀsuppliesꢀshouldꢀremainꢀinꢀregulationꢀ whichꢀrampsꢀtheꢀLDOꢀreferenceꢀupꢀoverꢀaꢀ200µsꢀperiodꢀ
andꢀ operatingꢀ correctlyꢀ assumingꢀ specifiedꢀ operatingꢀ typically.ꢀAfterꢀaꢀ14msꢀdelayꢀfromꢀLDO2ꢀbeingꢀenabled,ꢀ
conditionsꢀareꢀmetꢀ(i.e.,ꢀnoꢀshortedꢀsupplies,ꢀetc).ꢀ
Buck1ꢀisꢀenabledꢀandꢀslewsꢀupꢀintoꢀregulation.ꢀWhenꢀBuck1ꢀ
isꢀwithinꢀaboutꢀ8%ꢀofꢀfinalꢀregulation,ꢀBuck2ꢀisꢀenabledꢀ
andꢀslewsꢀupꢀintoꢀregulation.ꢀTheꢀbucksꢀalsoꢀhaveꢀaꢀsoft-
startꢀfunctionꢀtoꢀlimitꢀinrushꢀcurrentꢀatꢀstart-up.ꢀ230msꢀ
afterꢀBuck2ꢀisꢀwithinꢀ8%ꢀofꢀfinalꢀregulation,ꢀtheꢀPGOODꢀ
outputꢀwillꢀgoꢀhighꢀimpedanceꢀ(notꢀshownꢀinꢀFigureꢀ18).ꢀ
TheꢀregulatorsꢀinꢀFigureꢀ18ꢀareꢀslewingꢀupꢀwithꢀnominalꢀ
outputꢀcapacitorsꢀandꢀnoꢀload.ꢀAddingꢀaꢀloadꢀorꢀincreasingꢀ
outputꢀcapacitanceꢀonꢀanyꢀofꢀtheꢀoutputsꢀwillꢀreduceꢀtheꢀ
slewꢀrateꢀandꢀlengthenꢀtheꢀtimeꢀitꢀtakesꢀtheꢀregulatorꢀtoꢀ
getꢀintoꢀregulation.ꢀ
ThereꢀareꢀonlyꢀtwoꢀmethodsꢀtoꢀpowerꢀdownꢀtheꢀLTC3677-3ꢀ
supplies:ꢀ1)ꢀPWR_ONꢀgoesꢀLOW;ꢀꢀ2)ꢀV ꢀdropsꢀbelowꢀtheꢀ
OUT
V
OUT
ꢀUVLOꢀthreshold.ꢀIfꢀtheꢀμC/μPꢀcontrolsꢀshutdownꢀbyꢀ
bringingꢀPWR_ONꢀLOW,ꢀitꢀisꢀpossibleꢀthatꢀtheꢀapplicationꢀ
canꢀhangꢀwithꢀallꢀsuppliesꢀenabledꢀifꢀtheꢀμC/μPꢀfailsꢀtoꢀ
resetꢀcorrectlyꢀonꢀhardꢀreset.ꢀInꢀthisꢀcaseꢀtheꢀbatteryꢀwillꢀ
continueꢀtoꢀbeꢀdrainedꢀuntilꢀV ꢀdropsꢀbelowꢀtheꢀV
ꢀ
OUT
OUT
UVLOꢀthreshold,ꢀorꢀtheꢀuserꢀintervenesꢀtoꢀshutꢀdownꢀtheꢀ
applicationꢀmanually.ꢀTheꢀapplicationꢀcanꢀbeꢀshutꢀdownꢀ
manuallyꢀbyꢀremovingꢀtheꢀbatteryꢀandꢀanyꢀexternalꢀsupplies,ꢀ
orꢀbyꢀprovidingꢀaꢀsuicideꢀbuttonꢀthatꢀwillꢀbringꢀPWR_ONꢀ
LOWꢀwhenꢀpressed.
V
UVLO
OUT
1
>14 SEC
PBSTAT
0
LDO2
1V/DIV
0V
BUCK1
1V/DIV
0V
ON (PB)
50ms
PBSTAT
PWR_ON
BUCK1
BUCK2
2V/DIV
BUCK2
LDO1
0V
36773 F18
2ms/DIV
14 SEC
1.8ms
36773 F17
PGOOD
STATE PON
Figure 18. Power-Up Sequencing
Figure 17. Hard Reset Timing
36773f
ꢂꢈ
LTC3677-3
operaTion
LAYOUT AND THERMAL CONSIDERATIONS
whereꢀLDOxꢀisꢀtheꢀprogrammedꢀoutputꢀvoltage,ꢀVI
ꢀ
NLDOx
ꢀisꢀtheꢀLDOꢀoutputꢀ
isꢀtheꢀLDOꢀsupplyꢀvoltageꢀandꢀI
LDOx
Printed Circuit Board Power Dissipation
loadꢀcurrent.ꢀNoteꢀthatꢀifꢀtheꢀLDOꢀsupplyꢀisꢀconnectedꢀtoꢀ
oneꢀofꢀtheꢀbuckꢀoutput,ꢀthenꢀitsꢀsupplyꢀcurrentꢀmustꢀbeꢀ
addedꢀtoꢀtheꢀbuckꢀregulatorꢀloadꢀcurrentꢀforꢀcalculatingꢀ
theꢀbuckꢀpowerꢀloss.
Inꢀorderꢀtoꢀbeꢀableꢀtoꢀdeliverꢀmaximumꢀchargeꢀcurrentꢀ
underꢀallꢀconditions,ꢀitꢀisꢀcriticalꢀthatꢀtheꢀexposedꢀgroundꢀ
padꢀonꢀtheꢀbacksideꢀofꢀtheꢀLTC3677-3ꢀpackageꢀbeꢀsol-
deredꢀtoꢀaꢀgroundꢀplaneꢀonꢀtheꢀboard.ꢀCorrectlyꢀsolderedꢀ
Thusꢀtheꢀpowerꢀdissipatedꢀbyꢀallꢀregulatorsꢀis:
2
toꢀ2500mm ꢀgroundꢀplaneꢀonꢀaꢀdouble-sidedꢀ1ozꢀcopperꢀ
ꢀ P ꢀ=ꢀP
DREGS
+ꢀP
DSW1ꢀ
+ꢀP
DSW2ꢀ
ꢀ+ꢀP
DSW3
ꢀ+ꢀP
DLDO1
ꢀ
DLDO2
boardꢀtheꢀLTC3677-3ꢀhasꢀaꢀthermalꢀresistanceꢀ(θ )ꢀofꢀap-
JA
proximatelyꢀ45°C/W.ꢀFailureꢀtoꢀmakeꢀgoodꢀthermalꢀcontactꢀ
betweenꢀtheꢀexposedꢀpadꢀonꢀtheꢀbacksideꢀofꢀtheꢀpackageꢀ
andꢀaꢀadequatelyꢀsizedꢀgroundꢀplaneꢀwillꢀresultꢀinꢀthermalꢀ
resistancesꢀfarꢀgreaterꢀthanꢀ45°C/W.
Itꢀisꢀnotꢀnecessaryꢀtoꢀperformꢀanyꢀworst-caseꢀpowerꢀdissi-
pationꢀscenariosꢀbecauseꢀtheꢀLTC3677-3ꢀwillꢀautomaticallyꢀ
reduceꢀtheꢀchargeꢀcurrentꢀtoꢀmaintainꢀtheꢀdieꢀtemperatureꢀ
atꢀapproximatelyꢀ110°C.ꢀHowever,ꢀtheꢀapproximateꢀambi-
entꢀtemperatureꢀatꢀwhichꢀtheꢀthermalꢀfeedbackꢀbeginsꢀtoꢀ
protectꢀtheꢀICꢀis:
TheꢀconditionsꢀthatꢀcauseꢀtheꢀLTC3677-3ꢀtoꢀreduceꢀchargeꢀ
currentꢀdueꢀtoꢀtheꢀthermalꢀprotectionꢀfeedbackꢀcanꢀbeꢀap-
proximatedꢀbyꢀconsideringꢀtheꢀpowerꢀdissipatedꢀinꢀtheꢀpart.ꢀ
ForꢀhighꢀchargeꢀcurrentsꢀwithꢀaꢀwallꢀadapterꢀappliedꢀtoꢀV ,ꢀ
theꢀLTC3677-3ꢀpowerꢀdissipationꢀisꢀapproximately:ꢀ
ꢀ T ꢀ=ꢀ110°Cꢀ–ꢀP ꢀ•ꢀθ
JA
A
D
OUTꢀ
Example:ꢀConsiderꢀtheꢀLTC3677-3ꢀoperatingꢀfromꢀaꢀwallꢀ
adapterꢀwithꢀ5Vꢀ(V )ꢀprovidingꢀ1Aꢀ(I )ꢀtoꢀchargeꢀaꢀ
OUT
BAT
ꢀ P ꢀ=ꢀ(V ꢀ–ꢀBAT)ꢀ•ꢀI ꢀ+ꢀP
Li-Ionꢀbatteryꢀatꢀ3.3Vꢀ(BAT).ꢀAlsoꢀassumeꢀP
soꢀtheꢀtotalꢀpowerꢀdissipationꢀis:
ꢀ=ꢀ0.3W,ꢀ
D
OUT
BAT
DREGS
DREGS
whereꢀP ꢀisꢀtheꢀtotalꢀpowerꢀdissipated,ꢀV ꢀisꢀtheꢀsupplyꢀ
D
OUT
BAT
voltage,ꢀBATꢀisꢀtheꢀbatteryꢀvoltageꢀandꢀI ꢀisꢀtheꢀbatteryꢀ
ꢀ P ꢀ=ꢀ(5Vꢀ–ꢀ3.3V)ꢀ•ꢀ1Aꢀ+ꢀ0.3Wꢀ=ꢀ2W
D
chargeꢀcurrent.ꢀP
ꢀisꢀtheꢀsumꢀofꢀpowerꢀdissipatedꢀon-
DREGS
TheꢀambientꢀtemperatureꢀaboveꢀwhichꢀtheꢀLTC3677-3ꢀbe-
ginsꢀtoꢀreduceꢀtheꢀ1Aꢀchargeꢀcurrent,ꢀisꢀapproximately
chipꢀbyꢀtheꢀstep-downꢀswitching,ꢀandꢀLDOꢀregulators.ꢀ
Theꢀpowerꢀdissipatedꢀbyꢀaꢀstep-downꢀswitchingꢀregulatorꢀ
canꢀbeꢀestimatedꢀasꢀfollows:ꢀ
ꢀ T ꢀ=ꢀ110°Cꢀ–ꢀ2Wꢀ•ꢀ45°C/Wꢀ=ꢀ20°C
A
TheꢀLTC3677-3ꢀcanꢀbeꢀusedꢀaboveꢀ20°C,ꢀbutꢀtheꢀchargeꢀ
currentꢀwillꢀbeꢀreducedꢀbelowꢀ1A.ꢀTheꢀchargeꢀcurrentꢀatꢀaꢀ
givenꢀambientꢀtemperatureꢀcanꢀbeꢀapproximatedꢀby:
100 –Eff
P
= OUTx •I
(
•
)
D(SWx)
OUTx
100
ꢀ
whereꢀ OUTxꢀ isꢀ theꢀ programmedꢀ outputꢀ voltage,ꢀ I
ꢀ
110°C – TA
OUTx
P =
= V
–BAT •IBAT +P
(
)
D
OUT
D(REGS)
isꢀtheꢀloadꢀcurrentꢀandꢀEffꢀisꢀtheꢀ%ꢀefficiencyꢀwhichꢀcanꢀ
beꢀmeasuredꢀorꢀlookedꢀupꢀonꢀanꢀefficiencyꢀtableꢀforꢀtheꢀ
programmedꢀoutputꢀvoltage.
θJA
ꢀ
Thus:
110°C – T
(
)
A
TheꢀpowerꢀdissipatedꢀonꢀchipꢀbyꢀaꢀLDOꢀregulatorꢀcanꢀbeꢀ
estimatedꢀasꢀfollows:ꢀ
θJA – P
D(REGS)
ꢀ
IBAT
=
VOUT – BAT
ꢀ P
ꢀ=ꢀ(V
ꢀ–ꢀLDOx)ꢀ•ꢀI
ꢀ
DLDOx
INLDOx
LDOx
ꢀ
36773f
ꢃ0
LTC3677-3
operaTion
Considerꢀ theꢀ previousꢀ exampleꢀ withꢀ anꢀ ambientꢀ tem-
peratureꢀofꢀ55°C.ꢀTheꢀchargeꢀcurrentꢀwillꢀbeꢀreducedꢀtoꢀ
approximately:
ConnectꢀV
ꢀandꢀV ꢀtoꢀV ꢀthroughꢀaꢀshortꢀlowꢀ
IN12 IN3 OUT
impedanceꢀtrace.ꢀ
3.ꢀTheꢀswitchingꢀpowerꢀtracesꢀconnectingꢀSW1,ꢀSW2,ꢀ
andꢀSW3ꢀtoꢀtheirꢀrespectiveꢀinductorsꢀshouldꢀbeꢀmini-
mizedꢀtoꢀreduceꢀradiatedꢀEMIꢀandꢀparasiticꢀcoupling.ꢀ
Dueꢀtoꢀtheꢀlargeꢀvoltageꢀswingꢀofꢀtheꢀswitchingꢀnodes,ꢀ
sensitiveꢀnodesꢀsuchꢀasꢀtheꢀfeedbackꢀnodesꢀ(FBxꢀ
andꢀLDOx_FB)ꢀshouldꢀbeꢀkeptꢀfarꢀawayꢀorꢀshieldedꢀ
fromꢀtheꢀswitchingꢀnodesꢀorꢀpoorꢀperformanceꢀcouldꢀ
result.
110°C – 55°C
– 0.3W
45°C/W
IBAT
IBAT
=
=
5V – 3.3V
1.22 – 0.3W
= 542mA
1.7V
ꢀ
Printed Circuit Board Layout
4.ꢀConnectionsꢀbetweenꢀtheꢀstep-downꢀswitchingꢀregu-
latorꢀinductorsꢀandꢀtheirꢀrespectiveꢀoutputꢀcapacitorsꢀ
shouldꢀbeꢀkeptꢀasꢀshortꢀasꢀpossible.ꢀTheꢀGNDꢀsideꢀofꢀ
theꢀoutputꢀcapacitorsꢀshouldꢀconnectꢀdirectlyꢀtoꢀtheꢀ
thermalꢀgroundꢀplaneꢀofꢀtheꢀpart.
Whenꢀlayingꢀoutꢀtheꢀprintedꢀcircuitꢀboard,ꢀtheꢀfollowingꢀ
listꢀshouldꢀbeꢀfollowedꢀtoꢀensureꢀproperꢀoperationꢀofꢀtheꢀ
LTC3677-3:
1.ꢀTheꢀ exposedꢀ padꢀ ofꢀ theꢀ packageꢀ (Pinꢀ 45)ꢀ shouldꢀ
connectꢀdirectlyꢀtoꢀaꢀlargeꢀgroundꢀplaneꢀtoꢀminimizeꢀ
thermalꢀandꢀelectricalꢀimpedance.ꢀ
5.ꢀKeepꢀtheꢀbuckꢀfeedbackꢀpinꢀtracesꢀ(FB1,ꢀFB2,ꢀandꢀFB3)ꢀ
asꢀshortꢀasꢀpossible.ꢀMinimizeꢀanyꢀparasiticꢀcapacitanceꢀ
betweenꢀtheꢀfeedbackꢀtracesꢀandꢀanyꢀswitchingꢀnodeꢀ
(i.e.,ꢀSW1,ꢀSW2,ꢀSW3,ꢀandꢀlogicꢀsignals).ꢀIfꢀnecessaryꢀ
shieldꢀtheꢀfeedbackꢀnodesꢀwithꢀaꢀGNDꢀtrace.
2.ꢀTheꢀstep-downꢀswitchingꢀregulatorꢀinputꢀsupplyꢀpinsꢀ
(V
ꢀandꢀV )ꢀandꢀtheirꢀrespectiveꢀdecouplingꢀca-
IN12
IN3
pacitorsꢀshouldꢀbeꢀkeptꢀasꢀshortꢀasꢀpossible.ꢀTheꢀGNDꢀ
sideꢀofꢀtheseꢀcapacitorsꢀshouldꢀconnectꢀdirectlyꢀtoꢀtheꢀ
groundꢀplaneꢀofꢀtheꢀpart.ꢀTheseꢀcapacitorsꢀprovideꢀ
theꢀACꢀcurrentꢀtoꢀtheꢀinternalꢀpowerꢀMOSFETsꢀandꢀ
theirꢀdrivers.ꢀIt’sꢀimportantꢀtoꢀminimizingꢀinductanceꢀ
fromꢀtheseꢀcapacitorsꢀtoꢀtheꢀpinsꢀofꢀtheꢀLTC3677-3.ꢀ
6.ꢀConnectionsꢀbetweenꢀtheꢀLTC3677-3ꢀpowerꢀpathꢀpinsꢀ
(V ꢀandꢀV )ꢀandꢀtheirꢀrespectiveꢀdecouplingꢀca-
BUS
OUT
pacitorsꢀshouldꢀbeꢀkeptꢀasꢀshortꢀasꢀpossible.ꢀTheꢀGNDꢀ
sideꢀofꢀtheseꢀcapacitorsꢀshouldꢀconnectꢀdirectlyꢀtoꢀtheꢀ
groundꢀplaneꢀofꢀtheꢀpart.
36773f
ꢃꢀ
LTC3677-3
Typical applicaTion
5V WALL
ADAPTER
Si2333DS
4
41
WALL ACPR
V
OUT
13
8
30
27
39
SYSTEM LOAD
20µF
OVGATE
V
V
INLDO2
INLDO1
10µF
2.2µF
2.2µF
OVSENSE
V
OUT
40
32
6
USB
V
BUS
V
IN12
1k
10µF
2k
LTC3677-3
V
IN3
44
37
CHRG
36
43
Si2333DS
(OPT)
PROG
IDGATE
38
2.1k
BAT
BAT
+
100k
CLPROG
34
35
Li-Ion
NTCBIAS
NTC
10
11
12
100k
NTC
DV
CC
SDA
SCL
DV
CC
SDA
SCL
499k 499k 499k
µC/µP
42
16
14
3, 9, 18 ,19, 20, 22
EXTPWR
PBSTAT
EXTPWR
PBSTAT
NC
PWR_ON
PWR_ON
KILL
4.7µH
33
17
1
V
OUT1
EN3
EN3
SW1
FB1
1.8V
I
I
I
I
LIM0
LIM1
LIM0
LIM1
500mA
10pF
806k
10µF
2
649k
26
RST
PUSHBUTTON
15
ON
4.7µH
31
V
V
3.3V
500mA
LDO1
3.3V
150mA
OUT2
28
LDO1
SW2
1µF
1µF
1.02M
348k
10pF
10pF
1.02M
232k
10µF
10µF
324k
464k
324k
464k
23
29
25
LDO1_FB
LDO2
FB2
3.3µH
5
V
1.2V
800mA
V
OUT3
LDO2
SW3
1.4V
150mA
7
24
LDO2_FB
FB3
21
PGOOD
GND
45
100k
36773 TA02
36773f
ꢃꢁ
LTC3677-3
package DescripTion
UFF Package
Variation: UFFMA
44-Lead Plastic QFN (4mm × 7mm)
(ReferenceꢀLTCꢀDWGꢀ#ꢀ05-08-1762ꢀRevꢀØ)
1.48 0.05
0.70 0.05
0.98 0.05
1.70 0.05
2.56 0.05
4.50 0.05
3.10 0.05
2.40 REF
2.02 0.05
2.76 0.05
2.64 0.05
PACKAGE
OUTLINE
0.20 0.05
5.60 REF
0.40 BSC
6.10 0.05
7.50 0.05
RECOMMENDED SOLDER PAD LAYOUT
PIN 1 NOTCH
R = 0.30 TYP
OR 0.35 s 45o
CHAMFER
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 p0.05
2.40 REF
4.00 p0.10
43
44
0.00 – 0.05
0.40 p0.10
1
2
PIN 1
TOP MARK
(SEE NOTE 6)
2.64
0.10
2.56
0.10
7.00 p0.10
5.60 REF
R = 0.10
TYP
1.70
0.10
2.76
0.10
0.74 0.10
R = 0.10 TYP
0.74 0.10
(UFF44MA) QFN REF Ø 1107
R = 0.10 TYP
0.200 REF
0.20 p0.05
0.40 BSC
0.98 0.10
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
36773f
InformationꢀfurnishedꢀbyꢀLinearꢀTechnologyꢀCorporationꢀisꢀbelievedꢀtoꢀbeꢀaccurateꢀandꢀreliable.ꢀ
However,ꢀnoꢀresponsibilityꢀisꢀassumedꢀforꢀitsꢀuse.ꢀLinearꢀTechnologyꢀCorporationꢀmakesꢀnoꢀrepresenta-
tionꢀthatꢀtheꢀinterconnectionꢀofꢀitsꢀcircuitsꢀasꢀdescribedꢀhereinꢀwillꢀnotꢀinfringeꢀonꢀexistingꢀpatentꢀrights.
ꢃꢂ
LTC3677-3
Typical applicaTion
Si2333DS
Si2306BDS
5V WALL
ADAPTER
D3
5.6V
Si2333DS
4
41
R1
WALL ACPR
500k
V
OUT
SYSTEM LOAD
20µF
13
8
30
39
OVGATE
V
INLDO1
6.2k
10µF
2.2µF
2.2µF
OVSENSE
OPTIONAL OVERVOLTAGE/
REVERSE VOLTAGE PROTECTION
V
OUT
40
32
6
USB
V
BUS
V
IN12
1k
LTC3677-3
10µF
V
IN3
44
37
2k
CHRG
36
43
Si2333DS
(OPT)
PROG
IDGATE
38
2.1k
BAT
BAT
+
100k
CLPROG
34
35
Li-Ion
NTCBIAS
NTC
10
11
12
100k
NTC
DV
CC
DV
CC
SDA
SCL
SDA
SCL
499k 499k 499k
µC/µP
42
16
14
3, 9, 18 ,19, 20, 22
EXTPWR
PBSTAT
EXTPWR
PBSTAT
NC
PWR_ON
PWR_ON
KILL
4.7µH
33
17
1
V
OUT1
EN3
EN3
SW1
FB1
3.3V
I
I
I
I
LIM0
LIM1
LIM0
LIM1
500mA
10pF
1.02M
10µF
2
324k
26
30
RST
PUSHBUTTON
15
V
ON
INLDO2
4.7µH
31
V
V
1.8V
500mA
LDO1
2.5V
150mA
OUT2
28
LDO1
SW2
1µF
1µF
1.00M
115k
10pF
10pF
806k
402k
10µF
10µF
470k
464k
649k
649k
23
29
25
LDO1_FB
LDO2
FB2
3.3µH
5
V
1.3V
800mA
V
OUT3
LDO2
SW3
1.0V
150mA
7
24
LDO2_FB
FB3
21
GND PGOOD
45
100k
36773 TA03
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LTC3556
HighꢀEfficiencyꢀUSBꢀPowerꢀManagerꢀPlusꢀDualꢀ
BuckꢀPlusꢀBuck-BoostꢀDC/DCꢀPMIC
Twoꢀ400mAꢀSynchronousꢀBuckꢀRegulators,ꢀOneꢀ1AꢀBuck-BoostꢀRegulator,ꢀ4mmꢀ×ꢀ
5mmꢀQFN28ꢀPackage.
LTC3557/
LTC3557-1
USBꢀPowerꢀManagerꢀwithꢀLi-Ion/Polymerꢀ
ChargerꢀandꢀTripleꢀSynchronousꢀBuckꢀConverter
LinearꢀPowerꢀManagerꢀandꢀThreeꢀBuckꢀRegulators,ꢀ4mmꢀ×ꢀ4mmꢀQFN28ꢀPackage,ꢀ
LTC3557-1ꢀVersionꢀHasꢀ4.1VꢀFloatꢀVoltage.
LTC3577/
LTC3577-1
HighlyꢀIntegratedꢀProtable/NavigationꢀPMIC
LinearꢀPowerꢀManagerꢀandꢀThreeꢀBuckꢀRegulators,ꢀ10-LEDꢀBoostꢀRegulator,ꢀ2×ꢀ150mAꢀ
LDOs,ꢀ4mmꢀ×ꢀ7mmꢀQFN44ꢀPackage,ꢀLTC3577-1ꢀVersionꢀHasꢀ4.1VꢀFloatꢀVoltage.ꢀ
36773f
LT 0310 • PRINTED IN USA
Linear Technology Corporation
1630ꢀ McCarthyꢀ Blvd.,ꢀ Milpitas,ꢀ CAꢀ 95035-7417
ꢀ
ꢃꢃ
●
●ꢀ
LINEAR TECHNOLOGY CORPORATION 2010
(408)ꢀ432-1900ꢀ ꢀFAX:ꢀ(408)ꢀ434-0507ꢀ www.linear.com
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