LTC3701EGN#PBF [Linear]
LTC3701 - 2-Phase, Low Input Voltage, Dual Step-Down DC/DC Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LTC3701EGN#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3701 - 2-Phase, Low Input Voltage, Dual Step-Down DC/DC Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总20页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3701
2-Phase, Low Input Voltage,
Dual Step-Down DC/DC Controller
U
FEATURES
DESCRIPTIO
The LTC®3701 is a 2-phase dual constant frequency cur-
rentmodestep-downDC/DCcontrollerprovidingexcellent
load and line regulation. Power loss and noise due to ESR
of the input capacitor are minimized by operating the two
controller output stages out-of-phase.
■
Out-of-Phase Controllers Reduce Required
Input Capacitance
■
True PLL for Frequency Locking or Frequency
Adjustment
■
Operating Frequency Range: 300kHz to 750kHz
■
Wide VIN Range: 2.5V to 10V
The LTC3701 provides a 0.8V ±2% voltage reference and
consumes only 460µA of quiescent current. To further
maximize the life of a battery source, the external
P-channel MOSFET is turned on continuously in dropout
(100% duty cycle).
■
Constant Frequency Current Mode Architecture
■
Low Dropout: 100% Duty Cycle
■
Power Good Output Voltage Monitor
■
Internal Soft-Start Circuitry
Selectable Burst Mode®/Pulse Skipping Operation
at Light Loads
■
Switching frequency is internally set at 550kHz, allowing
the use of small inductors and capacitors. For noise sen-
sitive applications, the LTC3701 can be externally syn-
chronized using its phase-locked loop. The frequency can
also be externally set from 300kHz to 750kHz by applying
avoltagetothePLLLPFpin.BurstModeoperationisinhib-
ited during synchronization or when the EXTCLK/MODE
pin is pulled low to reduce noise and RF interference.
■
■
■
■
Output Overvoltage Protection
Low Quiescent Current: 460µA
0.8V ±2% Voltage Reference
Small 16-Lead Narrow SSOP Package
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APPLICATIO S
■
One or Two Lithium-Ion Powered Applications
Notebook and Handheld Computers
Personal Digital Assistants
Portable Instruments
Distributed DC Power Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LTC3701 contains independent internal soft-start
circuitry for each controller. Other features include a
power good output voltage monitor and output overvolt-
age and short-circuit protection.
■
■
■
■
The LTC3701 is available in a small footprint 16-lead nar-
row SSOP package.
Burst Mode is a registered trademark of Linear Technology Corporation.
U
TYPICAL APPLICATIO
V
IN
2.5V TO 9.8V
Efficiency vs Load Current
100
169k
V
= 3.3V
1
3
2
4
6
5
7
8
16
15
14
13
12
11
10
9
V
= 4.2V
IN
–
+
IN
SENSE1
SENSE1
V
OUT1
L1
0.03Ω
0.03Ω
90
80
2.5V
220pF
78.7k
V
FB1
V
4.7µH
IN
10k
10k
2A
10µF
M1
M2
+
I
/RUN1
PGATE1
PGND
D1
TH
SGND
/RUN2
47µF
47µF
LTC3701
V
IN
= 6V
V
= 8.4V
IN
I
PGATE2
PGOOD
70
60
TH
D2
80.6k
100k
V
220pF
FB2
+
L2
4.7µH
V
1.8V
2A
OUT2
PLLLPF EXTCLK/MODE
–
+
SENSE2
SENSE2
50
40
V
= 2.5V
OUT
3701 F01a
D1, D2: IR10BQ015 L1, L2: LQN6C-4R7 M1, M2: FDC638P
1
10
100
1000
10000
LOAD CURRENT (mA)
3701 F01b
Figure 1. High Efficiency 2-Phase 550kHz Dual Step-Down Converter
3701fa
1
LTC3701
W W
U W
U W
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ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
ORDER PART
NUMBER
Input Supply Voltage (VIN)........................ –0.3V to 10V
SENSE1–, SENSE2–, PGATE1, PGATE2,
–
+
SENSE1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SENSE1
PLLLPF, SENSE1+, SENSE2+,
I
TH
/RUN1
V
IN
LTC3701EGN
V
PGATE1
PGND
FB1
EXTCLK/MODE Voltages .............. –0.3V to (VIN + 0.3V)
VFB1, VFB2, ITH/RUN1,
ITH/RUN2 Voltages .................................. –0.3V to 2.4V
PGOOD Voltage ........................................ –0.3V to 10V
PGATE1, PGATE2 Peak Output Current (<10µs)....... 1A
Operating Ambient Temperature Range
(Note 2) ...................................................–40°C to 85°C
Storage Ambient Temperature Range ... –65°C to 150°C
Junction Temperature (Note 3)............................ 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
SGND
V
PGATE2
PGOOD
FB2
I
TH
/RUN2
GN PART
MARKING
PLLLPF
–
EXTCLK/MODE
+
SENSE2
SENSE2
3701
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 140°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 4.2V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
Input DC Supply Current
Normal Operation
Sleep Mode
Shutdown
UVLO
(Note 4)
2.5V < V < 9.8V
2.5V < V < 9.8V
2.5V < V < 9.8V, I /RUN1 = I /RUN2 = 0V
460
305
9
780
470
28
µA
µA
µA
µA
IN
IN
IN TH TH
V
IN
< UVLO Threshold
18
30
Undervoltage Lockout Threshold
V
IN
V
IN
Falling
Rising
●
1.55
1.70
2.00
2.12
2.50
2.55
V
V
Shutdown Threshold at I /RUN1, 2
0.2
0.35
0.5
0.5
V
TH
Start-Up Current Source on I /RUN1, 2
V /RUN1, 2 = 0V
ITH
0.25
0.85
µA
TH
Regulated Feedback Voltage
0°C to 70°C (Note 5), I /RUN = 1.3V
–40°C to 85°C (Note 5)
●
●
0.784
0.774
0.8
0.8
0.816
0.826
V
V
TH
Output Voltage Line Regulation
Output Voltage Load Regulation
2.5V < V < 9.8V (Note 5)
0.05
0.20
mV/V
IN
I
I
/RUN = 0.9V (Note 5)
TH
/RUN = 1.6V
TH
0.2
–0.2
0.8
–0.8
%
%
V
Input Current
(Note 5)
10
0.88
20
50
nA
V
FB1, 2
Output Overvoltage Protect Threshold
Output Overvoltage Protect Hysteresis
Gate Drive 1, 2 Rise Time
Measured at V
0.835
95
0.930
FB
mV
ns
C = 3000pF
L
40
Gate Drive 1, 2 Fall Time
C = 3000pF
L
40
ns
+
–
Maximum Current Sense Voltage (SENSE – SENSE )
(Note 6)
120
145
mV
Soft-Start
Current Sense Voltage Step
Time to Maximum Sense Voltage
30
2048
mV
Cycles
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2
LTC3701
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 4.2V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator and Phase-Locked Loop
Oscillator Frequency
V
V
V
= 1.2V or Floating
= 0V
≥ 2.4V
500
230
690
550
280
775
600
320
890
kHz
kHz
kHz
PLLLPF
PLLLPF
PLLLPF
Phase Detector Output Current
Sinking
Sourcing
f
f
< f
> f
–5
5
µA
µA
EXTCLK/MODE
EXTCLK/MODE
OSC
OSC
PGOOD Output
PGOOD Voltage Low
PGOOD Trip Level
I
= 500µA
70
150
mV
PGOOD
V
with Respect to Set Output Voltage
Ramping Positive
Ramping Negative
FB
V
V
–15
2.5
–8
8
–2.5
15
%
%
FB
FB
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 2: The LTC3701E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: The LTC3701 is tested in a feedback loop that servos I
to a
TH/RUN
specified voltage and measures the resultant V voltage.
FB
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as given in Figure 2.
Note 3: TJ is calculated from the ambient temperature T and power
A
dissipation P according to the following formula:
D
T = T + (P • θ °C/W)
J
A
D
JA
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Threshold
vs Temperature
Oscillator Frequency
vs Temperature
Reference Voltage vs Temperature
1000
900
800
700
600
500
400
300
200
100
0
0.810
0.805
0.50
0.48
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
0.28
0.26
0.24
0.22
0.20
V = 4.2V
IN
V
IN
= 4.2V
V
= 4.2V
IN
PLLLPF = 2.4V
0.800
PLLLPF = FLOAT
0.795
0.790
0.785
0.780
PLLLPF = 0V
0.775
–60
20
TEMPERATURE (°C)
60 80
–20
0
20 40
100
20
TEMPERATURE (°C)
–40 –20
0
40
100
–60 –40
60 80
–60 –40 –20
0
40 60 80 100
TEMPERATURE (°C)
3701 G03
3701 G01
3701 G02
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LTC3701
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Undervoltage Lockout Trip
Voltage (Falling) vs Temperature
Undervoltage Lockout Trip
Voltage (Rising) vs Temperature
Maximum Current Sense
Threshold vs Temperature
125
120
115
110
105
100
2.20
2.18
2.16
2.14
2.12
2.10
2.08
2.06
2.04
2.02
2.00
2.15
2.10
2.05
2.00
1.95
1.90
1.85
40 60
TEMPERATURE (°C)
20
TEMPERATURE (°C)
–60 –40 –20
0
20
80 100
–60 –40 –20
0
40 60 80 100
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
3701 G04
3701 G06
3701 G05
Input and Shutdown Currents vs
Input Voltage
Efficiency vs Load Current (Pulse
Skipping Mode)
100
90
80
70
60
50
40
600
500
400
300
200
100
0
FIGURE 1 CIRCUIT
EXTCLK/MODE = GND
V
IN
= 3.3V
PULSE SKIPPING MODE OPERATION
(EXTCLK/MODE = 0V)
V
OUT
= 2.5V
V
IN
= 8.4V
BURST MODE OPERATION
(EXTCLK/MODE = V
)
IN
V
IN
= 6V
FIGURE 1 CIRCUIT
LOAD CURRENT = 0A
V
IN
= 4.2V
100
SHUTDOWN
(I /RUN = 0V)
TH
1,2
1
10
100O
1OOOO
2
3
4
5
6
7
8
9
10 11
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
3701 G08
3701 G07
PGOOD RON vs Input Voltage
2-Phase Operation
500
450
400
350
300
250
200
150
100
50
I
= 500µA
PGOOD
SW1
5V/DIV
SW2
5V/DIV
INPUT
CURRENT
1A/DIV
FIGURE 1 CIRCUIT
500ns/DIV
0
4
0
1
2
3
5
6
7
8
9
10
INPUT VOLTAGE (V)
3701 G09
3701fa
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LTC3701
U
U
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PI FU CTIO S
SENSE1–, SENSE2– (Pins 1, 8): The (–) Inputs to the
Differential Current Comparators.
EXTCLK/MODE (Pin 10): External Clock Input. Applying a
clock to this pin causes the internal oscillator to phase-
lock to the external clock (nominal lock frequency range
between 300kHz and 750kHz). This also disables Burst
Mode operation but allows pulse-skipping at low load
currents.
ITH/RUN1, ITH/RUN2 (Pins 2, 6): These pins each serve
two functions. Each pin serves as the error amplifier
compensation point as well as the run control input for the
respectivecontroller. Forcingonepinbelow0.35Vcauses
the functions associated with that controller to be shut
down. Forcing both ITH/RUN pins below 0.35V causes the
device to be shut down. Nominal operating voltage range
on these pins is from 0.7V to 1.9V.
Forcing this pin high enables Burst Mode operation.
Forcing this pin low enables pulse-skipping mode. In
these cases, the frequency of the internal oscillator is set
by the voltage on the PLLLPF pin. If the PLLLPF voltage is
not set externally, the frequency internally defaults to
550kHz.
V
FB1, VFB2 (Pins 3, 5): Each receives the remotely sensed
feedback voltage for each controller from an external
resistive divider across the output.
PGOOD(Pin 11): Power Good Output Voltage Monitor
Open-Drain Logic Output. This pin is pulled to ground
whenthevoltageoneitherfeedbackpin(VFB1, VFB2)isnot
within ±8% of its nominal set point. PGOOD is pulled low
when channel 1 or both channels are shut down. When
channel 2 is shut down and channel 1 enabled, the
PGOOD output indicates the state of VFB1 only.
SGND (Pin 4): Signal Ground.
PLLLPF (Pin 7): Serves as the lowpass filter point for the
PLL and as the voltage control input to the internal
oscillator.Normally,aseriesRCisconnectedbetweenthis
pin and ground when synchronizing to an external clock.
Nominal voltage range is from 0V to 2.4V. Frequency can
be set by forcing this pin with a voltage. Tying this pin to
GND selects 300kHz. Tying to VIN or a voltage ≥ 2.4V
selects 750kHz. Floating this pin selects 550kHz opera-
tion.
PGATE2, PGATE1 (Pins 12, 14): Gate Drivers for the
External P-Channel MOSFETs. These pins swing from 0 to
SENSE+ (PVIN).
PGND (Pin 13): Ground Pin for Gate Drivers.
SENSE2+ (PVIN2), SENSE1+ (PVIN1) (Pins 9, 16): The (+)
InputstotheDifferentialCurrentComparators. Thesepins
also power the gate drivers.
VIN (Pin 15): Chip Signal Power Supply Input. This pin
powers the entire chip except for the gate drivers.
3701fa
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LTC3701
U
U
W
FU CTIO AL DIAGRA
R
SENSE1
L1
M1
V
OUT
V
IN
C
IN
C
OUT
D1
+
–
SENSE1
SENSE1
15
V
IN
16
1
SLOPE1
PV
IN1
–
+
SWITCHING
LOGIC AND
BLANKING
CIRCUIT
CLK1
S
PGATE1
PGND
I
Q
14
13
CMP
VOLTAGE
REFERENCE
R
V
REF
0.8V
+
V
IN
OV1
OVP
SCP
UV
UNDERVOLTAGE
LOCKOUT
+
–
0.880V
0.3V
–
UVSD
SLEEP1
0.15V
SHDN1
SHDN2
+
–
0.3V
SC1
BURSTDIS
BURSTDIS
BURST DEFEAT
CLOCK DETECT
EXTCLK/MODE
R2
R1
10
7
V
FB1
PHASE
DETECTOR
0.5µA
3
2
+
–
–
+
EAMP
10k
PLLLPF
V
REF
0.8V
CLK1
R
C
SLOPE1
SLOPE2
VOLTAGE
CONTROLLED
OSCILLATOR
V
I /RUN1
TH
IN
SLOPE
COMP
C
C
CLK2
R
C
0.35V
+
–
C
C
V
IN
SHDN1
I
TH
PGOOD1
CLAMP
PGOOD
SGND
CLK1
SOFT-START
11
4
100Ω
SHDN1
0.74V
+
–
OV1
PGOOD2
SHDN2
PGOOD1
DUPLICATE FOR SECOND CHANNEL
3701 BD
3701fa
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LTC3701
U
OPERATIO
Main Control Loop
(Refer to Functional Diagram)
VIN or to a voltage of at least 2V. To disable Burst Mode
operation and enable PWM pulse skipping mode, connect
the EXTCLK/MODE pin to ground. In this mode, the
efficiency is lower at light loads. However, pulse skipping
mode has the advantages of lower output ripple and less
interference to audio circuitry.
The LTC3701 uses a constant frequency, current mode
architecture with the two controller channels operating
180 degrees out of phase. During normal operation, each
external P-channel power MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the current comparator (ICMP) resets the latch. The When a controller is in Burst Mode operation, the peak
peak inductor current at which ICMP resets the RS latch is current of the inductor is set as if VITH/RUN = 1V, even
controlled by the voltage on the ITH/RUN pin, which is the though the voltage at the ITH/RUN pin is at a lower value.
output of each error amplifier, EAMP. The VFB pin receives If the inductor’s average current is greater than the load
the voltage feedback signal, which is compared to the requirement, the voltage at the ITH/RUN pin will drop.
internal reference voltage by the EAMP. When the load When the ITH/RUN voltage goes below 0.85V, the sleep
current increases, it causes a slight decrease in VFB signal goes high, turning off the external MOSFET. The
relativetothe0.8Vreference,whichinturn,causestheITH/ sleep signal goes low when the ITH/RUN voltage goes
RUN voltage to increase until the average inductor current above0.925Vandthatcontrollerchannelresumesnormal
matches the new load current.
operation. The next oscillator cycle will turn the external
MOSFET on and the switching cycle repeats.
Each main control loop is shut down by pulling the
respective ITH/RUN pin low. When both ITH/RUN1 and ITH/
RUN2 are low, all LTC3701 controller functions are shut
down. Releasing ITH/RUN allows an internal 0.5µA current
source to charge up the external compensation network.
When the ITH/RUN pin reaches 0.35V, the main control
loop is enabled with the ITH/RUN voltage then pulled up to
its zero current level of approximately 0.7V. After the loop
is enabled, an internal soft-start begins. During this soft-
start time of 2048 clock cycles, the ITH/RUN voltage is
clamped such that the maximum peak current sense
Frequency Synchronization
A phase-locked loop (PLL) is available on the LTC3701 to
allow the internal oscillator to be synchronized to an
external clock source connected to the EXTCLK/MODE
pin. The output of the phase detector at the PLLLPF pin
operates over a 0V to 2.4V range corresponding to ap-
proximately 300kHz to 750kHz. When locked, the PLL
aligns the turn-on of the external MOSFET of controller
channel 1 to the rising edge of the synchronizing signal.
The turn-on of the external MOSFET of controller channel
2 is 180 degrees out of phase with the rising edge of the
external clock source.
+
–
voltage (VSENSE – VSENSE ) is held to approximately 0%,
25%, 50%and75%, respectively, ofitsmaximumvalueof
120mV for four equally timed intervals. After soft-start is
completed, full current operation is allowed. As the exter-
nal compensation network continues to charge, the corre-
spondingoutputcurrenttriplevelfollows,allowingnormal
operation.
When the LTC3701 is clocked by an external source, Burst
Mode operation is disabled and the LTC3701 operates in
PWM pulse skipping mode. In this mode, when the output
load is very low, the current comparator ICMP may remain
tripped for several cycles and force the external MOSFET
to stay off for the same number of cycles. Increasing the
output load slightly allows constant frequency PWM op-
eration to resume. This mode exhibits low output ripple as
well as low audio noise and reduced RF interference while
providing reasonable low current efficiency.
Comparator OVP guards against transient output voltage
overshoots greater than 10% by turning off the external
P-channel power MOSFET and keeping it off until the fault
is removed.
Burst Mode Operation
The LTC3701 can be enabled to enter Burst Mode opera-
tionatlowload currentsby tying theEXTCLK/MODE pin to
3701fa
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LTC3701
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OPERATIO
(Refer to Functional Diagram)
Dropout Operation
Slope Compensation and Peak Inductor Current
When the input supply voltage decreases towards the
output voltage, the rate of change of the inductor current
during the ON cycle decreases. This reduction means that
the external P-channel MOSFET will remain on for more
than one oscillator cycle if the inductor current has not
ramped up to the threshold set by EAMP on the ITH/RUN
pin. Further reduction in input supply voltage will eventu-
ally cause the P-channel MOSFET to be turned on 100%,
i.e., DC. The output voltage will then be determined by the
input voltage minus the voltage drop across the MOSFET,
the sense resistor and the inductor.
The inductor’s peak current is determined by:
V
ITH/RUN – 0.7V
10 •RSENSE
IPK
=
when the LTC3701 is operating below 20% duty cycle.
However, once the duty cycle exceeds 20%, slope
compensation begins and effectively reduces the peak
inductor current. The amount of reduction is given by the
curve in Figure 2.
110
100
90
80
70
60
50
40
30
20
10
0
Undervoltage Lockout
TopreventoperationoftheP-channelMOSFETbelowsafe
input voltage levels, an undervoltage lockout is incorpo-
rated into the LTC3701. When the input supply voltage
drops below 2V, the P-channel MOSFET and all circuitry
are turned off except the undervoltage block, which draws
only several microamperes.
0
10 20 30 40 50 60 70 80 90 100
Short-Circuit Protection
DUTY CYCLE (%)
3701 F02
When an output is shorted to ground (VFB < 0.3V), the
switching frequency of that channel is reduced to 1/5 of
the normal operating frequency. The other controller
channel is unaffected and maintains normal operation.
This lower frequency allows the inductor current to safely
discharge,therebypreventingcurrentrunaway.Theswitch-
ing frequency will return to its normal value when the
feedback voltage rises above 0.3V. During the first 64
cycles(nonzero-currentcycles)ofsoft-start,however,the
controller operates at its full frequency.
Figure 2. Maximum Peak Current vs Duty Cycle
Power Good (PGOOD) Pin
A window comparator monitors both output voltages and
the open-drain PGOOD output is pulled low when the
divided down output voltages are not within ±8% of the
reference voltage of 0.8V. PGOOD is pulled low when
channel 1 or both channels are shut down. When chan-
nel 2 is shut down and channel 1 enabled, the PGOOD
output indicates the state of channel 1 only.
Output Overvoltage Protection
2-Phase Operation
As a further protection, the overvoltage comparator in the
LTC3701 will turn the external MOSFET off when the
feedback voltage has risen 10% above the reference
voltage of 0.8V. This comparator has a typical hysteresis
of 20mV.
The LTC3701 dual switching controller offers the consid-
erable benefits of using 2-phase operation. Circuit ben-
efits include lower input filtering requirements, reduced
electromagnetic interference (EMI) and increased effi-
ciency associated with 2-phase operation.
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LTC3701
U
OPERATIO
(Refer to Functional Diagram)
Why the need for 2-phase operation? Until recently, con- both channels switching. A single phase dual regulator
stant frequency dual switching regulators operated both system with both sides switching would exhibit twice the
channels in phase (i.e., single phase operation). This single side numbers. In this example, 2-phase operation
means that both topside MOSFETs are turned on at the reduced the RMS input current from 1.79ARMS to
same time, causing current pulses of up to twice the 0.91ARMS. While this is an impressive reduction in itself,
2
amplitude of those from a single regulator to be drawn remember that power losses are proportional to IRMS
,
from the input capacitor. These large amplitude pulses meaning that actual power wasted is reduced by a factor
increase the total RMS current flowing into the input of 3.86. The reduced input ripple current also means that
capacitor, requiring the use of more expensive input less power is lost in the input power path, which could
capacitors, and increasing both EMI and losses in the include batteries, switches, trace/connector resistances,
input capacitor and input power supply.
andprotectioncircuitry. Improvementsinbothconducted
and radiated EMI also directly accrue as a result of the
reduced RMS input current and voltage.
With 2-phase operation, the two channels of the LTC3701
are operated 180 degrees out of phase. This effectively
interleaves the current pulses coming from the switches, Of course, the improvement afforded by 2-phase opera-
greatly reducing the overlap time where they add tion is a function of the dual switching regulator’s relative
together. The result is a significant reduction in the total duty cycles, which in turn are dependent upon the input
RMS input current, which in turn allows for use of less voltage VIN. Figure 4 shows how the RMS input current
expensiveinputcapacitors,reducesshieldingrequirements varies for 1-phase and 2-phase operation for 2.5V and
for EMI and improves real world operating efficiency.
1.8V regulators over a wide input voltage range.
Figure 3 shows example waveforms for a single switching It can be readily seen that the advantages of 2-phase
regulator channel versus a 2-phase LTC3701 system with operation are not limited to a narrow operating range, but
in fact extend over a wide region. A good rule of thumb for
mostapplicationsisthat2-phaseoperationwillreducethe
input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
Single Phase
Dual Controller
2-Phase
Dual Controller
SW1 (V)
SW2 (V)
2.0
1.8
SINGLE PHASE
1.6
DUAL CONTROLER
1.4
I
2-PHASE
1.2
1.0
0.8
0.6
0.4
0.2
0
L1
DUAL CONTROLER
I
L2
V
V
= 2.5V/2A
= 1.8V/2A
OUT1
OUT2
2
6
8
9
3
4
5
7
10
I
IN
INPUT VOLTAGE (V)
3701 F04
3701 F03
Figure 4. RMS Input Current Comparison
Figure 3. Example Waveforms for a Single Switching
Regulator Channel vs 2-Phase LTC3701 System with
Both Channels Switching
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smaller inductor for the same amount of inductor ripple
current. However, this is at the expense of efficiency due
to an increase in MOSFET gate charge and switching
losses.
The basic LTC3701 application circuit is shown in Fig-
ure 1. External component selection is driven by the load
requirementandbeginswiththeselectionofLandRSENSE
.
Next, the power MOSFET M1 and the output diode D1 are
selected. Finally CIN (C1) and COUT (C2) are chosen.
The inductance value also has a direct effect on ripple
current. The ripple current, IRIPPLE, decreases with higher
inductance or frequency. The inductor’s peak-to-peak
ripple current is:
RSENSE Selection for Output Current
RSENSE is chosen based on the required output current.
Since the current comparator monitors the voltage devel-
oped across RSENSE, the threshold of the comparator
determines the inductor’s peak current. The output cur-
rent that the LTC3701 can provide is given by:
V – VOUT
V
OUT + VD
IN
IRIPPLE
=
f •L
V + VD
IN
where f is the operating frequency and VD is the forward
voltage drop of the external Schottky diode. Accepting
larger values of IRIPPLE allows the use of low inductances,
but results in higher output voltage ripple and greater core
losses. A reasonable starting point for setting ripple cur-
rent is IRIPPLE = 0.4(IOUT(MAX)). The maximum IRIPPLE
occurs at the maximum input voltage.
0.095 IRIPPLE
IOUT
=
–
RSENSE
2
where IRIPPLE is the inductor peak-to-peak ripple current
(see Inductor Value Calculation).
A reasonable starting point for setting ripple current is
IRIPPLE = (0.4)(IOUT). Rearranging the above equation
yields:
With Burst Mode operation selected on the LTC3701, the
ripple current is normally set such that the inductor
current is continuous during the burst periods. Therefore,
the peak-to-peak ripple current must not exceed:
1
RSENSE
=
for Duty Cycle < 20%
12.7 •IOUT
IRIPPLE ≤ (0.03)/RSENSE
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of RSENSE to provide the required
amount of current. Using Figure 2, the value of RSENSE is:
This implies a minimum inductance of:
V – VOUT
VOUT + VD
V + VD
IN
IN
LMIN
=
0.03
f
RSENSE
SF
RSENSE
=
12.7 IOUT 100
Use V = V
(
)(
)(
)
(
)
IN
IN(MAX)
A smaller value than LMIN could be used in the circuit,
however, the inductor current will not be continuous
during burst periods.
For noise sensitive applications, a 1nF capacitor placed
between the SENSE+ and SENSE– pins very close to the
chip is suggested.
Inductor Core Selection
Inductor Value Calculation
Once the value of L is known, the type of inductor must be
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ® cores. Actual core loss is independent of core
The inductor selection will depend on the operating fre-
quency of the LTC3701. The internal nominal frequency is
550kHz, but can be externally synchronized or set from
approximately 300kHz to 750kHz.
The operating frequency and inductor selection are inter-
related in that higher frequencies permit the use of a
Kool Mµ is a registered trademark of Magnetics, Inc.
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U
where PP is the allowable power dissipation and δp is the
temperature dependency of RDS(ON) . (1 + δp) is generally
given for a MOSFET in the form of a normalized RDS(ON) vs
temperature curve, but δp = 0.005/°C can be used as an
approximation for low voltage MOSFETs.
sizeforafixedinductorvalue, butisverydependentonthe
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will in-
crease. Ferrite designs have very low core losses and are
preferred at high switching frequencies, so design goals
canconcentrateoncopperlossandpreventingsaturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
In applications where the maximum duty cycle is less than
100%andtheLTC3701isincontinuousmode,theRDS(ON)
is governed by:
PP
RDS(ON)
2
DC I
1+ δp
(
)
(
)
OUT
where DC is the maximum operating duty cycle for that
channel of the LTC3701.
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when several layers of wire can be used, while
inductors wound on bobbins are generally easier to sur-
face mount. However, new designs for surface mount that
do not increase the height significantly are available from
Coiltronics, Coilcraft, Dale and Sumida.
Output Diode Selection
The catch diode carries load current during the switch off-
time. The average diode current is therefore dependent on
the P-channel MOSFET duty cycle. At high input voltages,
the diode conducts most of the time. As VIN approaches
VOUT, the diode conducts for only a small fraction of the
time. The most stressful condition for the diode is when
the output is short-circuited. Under this condition, the
diode must safely handle IPEAK at close to 100% duty
cycle. Therefore, it is important to adequately specify the
diode peak current and average power dissipation so as
not to exceed the diode’s ratings.
Power MOSFET Selection
An external P-channel MOSFET must be selected for use
with each channel of the LTC3701. The main selection
criteria for the power MOSFET are the threshold voltage
V
GS(TH), “on” resistance RDS(ON), reverse transfer capaci-
Under normal load conditions, the average current con-
ducted by the diode is:
tance CRSS and the total gate charge.
Since the LTC3701 is designed for operation down to low
inputvoltages,asublogiclevelthresholdMOSFET(RDS(ON)
guaranteed at VGS = 2.5V) is required for applications that
workclosetothisvoltage.WhentheseMOSFETsareused,
makesurethattheinputsupplytotheLTC3701islessthan
the absolute maximum MOSFET VGS rating, typically 8V.
V – VOUT
V + VD
IN
IN
ID =
IOUT
The allowable forward voltage drop in the diode is calcu-
lated from the maximum short-circuit current as:
The required minimum RDS(ON) of the MOSFET is gov-
erned by its allowable power dissipation. For applications
that may operate the LTC3701 in dropout, i.e., 100% duty
cycle, the required RDS(ON) is given by:
PD
VF ≈
IPEAK
where PD is the allowable power dissipation and will be
determined by efficiency and/or thermal requirements.
PP
ASchottkydiodeisagoodchoiceforlowforwarddropand
fast switching time. Remember to keep lead length short
and observe proper grounding (see Board Layout Check-
RDS(ON)DC=100%
=
2
I
(
1+ δp
(
)
)
OUT(MAX)
list) to avoid ringing and increased dissipation.
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CIN and COUT Selection
currentpulsesrequiredthroughtheinputcapacitor’sESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Also, the input protection fuse re-
sistance,batteryresistance,andPCboardtraceresistance
losses are also reduced due to the reduced peak currents
in a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source imped-
ance of the power supply/battery is included in the effi-
ciency testing. The sources of the P-channel MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may pro-
duce undesirable voltage and current resonances at VIN.
The selection of CIN is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The control-
ler with the highest (VOUT)(IOUT) product needs to be used
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output cur-
rent drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3701, is also
suggested. A 10Ω resistor placed between CIN (C1) and
the VIN pin provides further isolation between the two
channels.
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (VOUT + VD)/
(VIN + VD). To prevent large voltage transients, a low ESR
capacitor sized for the maximum RMS current of one
channel must be used. The maximum RMS capacitor
current is given by:
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
CIN Required IRMS
IMAX
V + VD
IN
≈
1/2
]
V
OUT + VD V – V
(
[
)(
)
IN OUT
1
∆VOUT ≈ IRIPPLE ESR +
8fCOUT
This formula has a maximum at VIN = 2VOUT + VD, where
IRMS = IOUT/2. This simple worst-case condition is com-
monlyusedfordesignbecauseevensignificantdeviations
do not offer much relief. Note that capacitor manufactur-
ers’ ripple current ratings are often based on only 2000
hours of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design.DuetothehighoperatingfrequencyoftheLTC3701,
ceramic capacitors can also be used for CIN. Always
consult the manufacturer if there is any question.
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
Low Supply Operation
AlthoughtheLTC3701canfunctiondowntoapproximately
2V,themaximumallowableoutputcurrentisreducedwhen
VIN decreases below 3V. Figure 5 shows the amount of
change as the supply is reduced down to 2V. Also shown
is the effect of VIN on VREF as VIN goes below 2.3V.
The benefit of the LTC3701 2-phase operation can be cal-
culated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
Setting Output Voltage
The LTC3701 output voltages are each set by an external
feedback resistive divider carefully placed across the
output capacitor (see Figure 6). The resultant feedback
signal is compared with an internal 0.8V reference by the
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U
error amplifier. The regulated output voltage is deter-
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
frequency is shown in Figure 7 and specified in the
electrical characteristics table. Note that the LTC3701 can
only be synchronized to an external clock whose fre-
quency is within the frequency range of the LTC3701’s
internal oscillator, which is specified in the electrical
characteristics table. A simplified block diagram of the
PLL is shown in Figure 8.
mined by:
R2
VOUT = 0.8V • 1+
R1
Formostapplications, an80kresistorissuggestedforR1.
To prevent stray pickup, a 100pF capacitor is suggested
across R1 close to the LTC3701.
105
V
REF
100
If the external frequency (VEXTCLK/MODE) is greater than
the internal oscillator frequency fOSC, current is sourced
continuously, pulling up the PLLLPF pin. When the exter-
nal frequency is less than fOSC, current is sunk continu-
ously, pulling down the PLLLPF pin. If the external and
internal frequencies are the same but exhibit a phase dif-
ference, the current sources turn on for an amount of time
corresponding to the phase difference. The voltage on the
PLLLPF pin is adjusted until the phase and frequency of
the external oscillators are identical. At the stable operat-
ing point, the phase comparator output is high impedance
and the filter capacitor CLP holds the voltage.
95
90
MAXIMUM
OUTPUT CURRENT
85
80
75
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
3701 F05
Figure 5. Line Regulation of VREF and Maximum Output Current
V
OUT
The loop filter components CLP and RLP smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components RLP and CLP determine how fast the loop
acquires lock. Typically, RLP = 10k and CLP is 2200pF to
0.01µF. When not synchronized to an external clock, the
R2
1/2 LTC3701
V
FB
100pF
R1
3701 F06
Figure 6. Setting Output Voltage
800
750
700
650
600
550
500
450
400
350
300
250
Phase-Locked Loop and Frequency Synchronization
The LTC3701 has a phase-locked loop comprised of an
internal voltage-controlled oscillator and phase detector.
This allows the turn-on of the external P-channel MOSFET
of controller 1 to be locked to the rising edge of an external
frequency source. The turn-on of controller 2’s external
P-channelMOSFETisthus180degreesoutofphasetothe
external clock. The nominal frequency range of the volt-
age-controlled oscillator is 280kHz to 775kHz. The phase
detectorisanedgesensitivedigitaltypethatprovideszero
degrees phase shift between the external and internal
oscillators. This type of phase detector does not exhibit
false lock to harmonics of the external oscillator.
0
0.4
0.8
1.2
1.6
2.0
2.4
PLLLPF PIN VOLTAGE (V)
3701 F07
Figure 7. Relationship Between Oscillator Frequency
and Voltage at PLLLPF Pin
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internal oscillator frequency may be set by applying a DC
voltage to the PLLLPF pin. 550kHz operation can be
selected by floating the PLLLPF pin. The PLLLPF pin may
be connected to voltages as high as VIN.
typically much larger than the DC supply current. In
continuous mode, IGATECHG = f • QP.
3) I2R losses are calculated from the DC resistances of the
MOSFET, inductor and sense resistor. In continuous
mode, the average output current flows through L but
is “chopped” between the P-channel MOSFET in series
withRSENSE andtheoutputdiode.TheMOSFETRDS(ON)
plus RSENSE multiplied by duty cycle can be summed
with the resistance of L to obtain I2R losses.
2.4V
R
LP
C
LP
PLLLPF
10k
EXTCLK/
MODE
DIGITAL
PHASE/
FREQUENCY
DETECTOR
EXTERNAL
OSCILLATOR
4) Theoutputdiodeisamajorsourceofpowerlossathigh
currents and is worse at high input voltages. The diode
loss is calculated by multiplying the forward voltage
times the load current times the diode duty cycle.
OSCILLATOR
5) Transition losses apply to the external MOSFET and
increase with higher operating frequencies and input
voltages. Transition losses can be estimated from:
3701 F08
Figure 8. Phase-Locked Loop Block Diagram
Transition Loss = 2 (VIN)2IO(MAX) RSS
(f)
C
Efficiency Considerations
Other losses, including CIN and COUT ESR dissipative
lossesandinductorcorelosses,generallyaccountforless
than 2% total additional loss.
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
oftenusefultoanalyzeindividuallossestodeterminewhat
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Foldback Current Limiting
As described in the Output Diode Selection, the worst-
case diode dissipation occurs with a short-circuited out-
putwhenthediodeconductsthecurrentlimitvaluealmost
continuously. To prevent excessive heating in the diode,
foldback current limiting can be added to reduce the
current in proportion to the severity of the fault.
Efficiency = 100% – (L1 + L2 + L3 + …)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3701 circuits: 1) LTC3701 DC bias current,
2) MOSFET gate charge current, 3) I2R losses, 4) voltage
drop of the output diode and 5) transition losses.
Foldback current limiting is implemented by adding di-
odes DFB1 and DFB2 between the output and the ITH/RUN
pin as shown in Figure 9. In a hard short (VOUT = 0V), the
current will be reduced to approximately 50% of the
maximum output current.
1) The VIN (pin) current is the DC supply current, given in
the electrical characteristics, that excludes MOSFET
driver currents. VIN current results in a small loss that
increases with VIN.
V
OUT
1/2 LTC3701
R2
R1
D
D
+
FB1
I
V
FB
TH/RUN
FB2
2) MOSFETgatechargecurrentresultsfromswitchingthe
gate capacitance of the power MOSFET. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from PVIN to ground. The
resulting dQ/dt is a current out of PVIN, which is
3701 F09
Figure 9. Foldback Current Limiting
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with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(CLOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD)(ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or dis-
chargeCOUT, whichgeneratesafeedbackerrorsignal. The
regulator loop then returns VOUT to its steady-state value.
Duringthisrecoverytime,VOUT canbemonitoredforover-
shoot or ringing. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest amount of
time that the LTC3701 is capable of turning the top
MOSFET on and then off. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. The minimum on-time for the LTC3701 is
about 250ns. Low duty cycle and high frequency applica-
tions may approach this minimum on-time limit and care
should be taken to ensure that:
The ITH series RC-CC filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The ITH exter-
nal components shown in the Figure 1 circuit will provide
an adequate starting point for most applications. The
values can be modified slightly (from 0.2 to 5 times their
suggestedvalues)tooptimizetransientresponseoncethe
final PC layout is done and the particular output capacitor
type and value have been determined. The output capaci-
tors need to be decided upon because the various types
and values determine the loop feedback factor gain and
phase. Anoutputcurrentpulseof20%to100%offullload
current having a rise time of 1µs to 10µs will produce
outputvoltageandITH pinwaveformsthatwillgiveasense
of the overall loop stability. The gain of the loop will be
increased by increasing RC, and the bandwidth of the loop
will be increased by decreasing CC. The output voltage
settling behavior is related to the stability of the closed-
loopsystemandwilldemonstratetheactualoverallsupply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
VOUT
tON(MIN)
<
f •V
IN
Ifthedutycyclefallsbelowwhatcanbeaccommodatedby
the minimum on-time, the LTC3701 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3701. These items are illustrated graphically in the
layout diagram of Figure 10. Figure 11 illustrates the
current waveforms present in the various branches of the
2-phase regulators. Check the following in your layout:
1) Are the sense resistors and P-channel MOSFETs for the
two channels located within 1cm of each other with a
common connection at CIN? Do not attempt to split the
input decoupling for the two channels as it can cause a
large resonant loop.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
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2) Are the signal and power grounds kept separate? The
LTC3701 signal ground consists of the feedback resistor
divider, the ITH/RUN compensation network, and Pin 4.
The power ground consists of the (–) terminal of CIN, the
(–) terminals of COUT1,2, the anodes of the Schottky
diodes, and Pin 13 of the LTC3701. The power ground
traces should be kept short, direct, and wide. Connect the
anodeoftheSchottkydiodesdirectlytotheinputcapacitor
ground.
From Figure 2, SF = 57%.
SF
0.57
RSENSE
=
=
= 0.03Ω
12.7 •IOUT •100 12.7 •1.5
In the application, a 0.03Ω resistor is used. The PLLLPF
pin will be left floating, so the LTC3701 will operate at its
default frequency of 550kHz. For continuous operation in
Burst Mode, the required minimum inductor value is:
3) Do the VFB pins connect directly to the feedback
resistors?PutthefeedbackresistorsclosetotheVFB pins.
The traces connecting the top feedback resistors to the
correspondingoutputcapacitorshouldtobeKelvintraces.
4) Are the SENSE– and SENSE+ leads routed together with
minimumPCtracespacing? The(optional)filtercapacitor
between SENSE+ and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the sense resistor.
4.2V – 2.5V
0.03V
2.5V + 0.3V
4.2V + 0.3V
LMIN
=
= 2.00µH
550kHz
0.03Ω
For the selection of the external MOSFET, the RDS(ON)
mustbeguaranteedat2.5VsincetheLTC3701hastowork
down to 2.7V. Let’s assume that the MOSFET dissipation
is to be limited to PP = 250mW and its thermal resistance
is 50°C/W. Hence, the junction temperature at TA = 25°C
will be 37.5°C and δp = 0.005 • (37.5 – 25) = 0.0625. The
required RDS(ON) is then given by:
5) Keep the switching nodes (SW1, SW2) and top gate
nodes (PGATE1, PGATE2) away from small-signal nodes,
especially the opposite channel’s voltage and current
sensing feedback pins. All of these nodes have large and
fast moving signals and therefore should be keep on the
“output side” of the LTC3701 and occupy minimum PC
trace area.
P
P
RDS(ON)
≈
= 0.11Ω
2
DC •IOUT 1+ δp
(
)
The P-channel MOSFET requirement can be met by an
Si3443DV.
The requirement for the Schottky diode is the most strin-
gent when VOUT = 0V, i.e., short circuit. With a 0.03Ω
RSENSE resistor, the short-circuit current through the
Schottky is 0.1/0.03 = 3.3A. An MBRS340T3 Schottky
diode is chosen. With 3.3A flowing through, the diode is
rated with a forward voltage of 0.4V. Therefore, the worst-
case power dissipated by the diode is 1.32W. The addition
of DFB1 and DFB2 (Figure 6) will reduce the diode dissipa-
tion to approximately 0.66W
Design Example
As a design example for one channel, assume VIN will be
operating from a maximum of 4.2V down to a minimum of
2.7V.Loadcurrentrequirementisamaximumof1.5A,but
most of the time it will be in a standby mode requiring only
2mA. Efficiency at both low and high load currents is
important. Burst Mode operation at light loads is desired.
Output voltage is 2.5V.
The input capacitor requires an RMS current rating of at
least 0.75A at temperature, and COUT will require an ESR
of 0.1Ω for optimum efficiency.
VOUT + VD
Maximum Duty Cycle =
= 93%
VIN(MIN) + VD
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U
+
–
C
OUT1
V
OUT1
L1
R
SENSE1
M1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–
+
SENSE1
/RUN1
SENSE1
D1
I
TH
V
IN
V
PGATE1
PGND
FB1
LTC3701
SGND
V
IN
+
C
V
FB2
PGATE2
PGOOD
IN
I
TH
/RUN2
D2
PLLLPF EXTCLK/MODE
–
+
SENSE2
SENSE2
M2
R
SENSE2
L2
–
+
V
OUT2
C
OUT2
BOLD LINES INDICATE
HIGH CURRENT PATHS
3701 F10
Figure 10. LTC3701 Layout Diagram
SW1
L1
R
SENSE1
V
OUT1
+
D1
C
OUT1
R
L1
V
IN
R
IN
+
C
IN
SW2
L2
R
SENSE2
V
OUT2
+
D2
C
OUT2
R
L2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
3701 F11
Figure 11. Branch Current Waveforms
3701fa
17
LTC3701
TYPICAL APPLICATIO S
U
2-Phase, Synchronizable Dual Output Step-Down DC/DC Converter
V
IN
2.7V to 9.8V
R7
169k
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
M1
–
+
V
2.5V
2A
OUT1
SENSE1
/RUN1
SENSE1
V
R1
L1
R6
78.7k
R10
10k
C6 220pF
C4 220pF
I
TH
IN
0.03Ω
4.7µH
+
C1
C2
10µF
V
FB1
PGATE1
D1
47µF
LTC3701
SGND
PGND
PGATE2
PGOOD
GND
V
I
FB2
100k
D2
R5
10k
C5
R8
80k
/RUN2
V
IN
TH
+
47µF
L2
4.7µH
PLLLPF EXTCLK/MODE
R9
100k
–
+
V
1.8V
2A
10k
10nF
OUT2
SENSE2
SENSE2
M2
R2
0.03Ω
3701 TA02
C1, C5: SANYO 6TPA47M
C2: TAIYO YUDEN LMK325BJ106K-T
D1, D2: IR10BQ015
L1, L2: MURATA LQN6C-4R7
M1, M2: Si3443DV
R1, R2: DALE 0.25W
2-Phase, 550kHz Single Output Step-Down DC/DC Converter
V
Optional Output Sequencing Circuit
IN
2.5V TO 9.8V
R7
169k
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
M1
V
IN
–
+
V
2.5V
4A
OUT
SENSE1
/RUN1
SENSE1
V
R1
L1
R6
78.7k
I
TH
IN
0.03Ω
4.7µH
0.01µF
+
C2
10µF
C1
V
PGATE1
D1
15k
FB1
47µF
3
5
LTC3701
SGND
PGND
PGATE2
PGOOD
+
1N4148
LT1004-1
1
1.2V
FB2
V
FB2
LT1797
D2
R5
10k
4
C4
220pF
I
TH
/RUN2
V
OUT1
–
2
L2
4.7µH
R2
0.03Ω
PLLLPF EXTCLK/MODE
3701 TA05
–
+
SENSE2
SENSE2
3701 TA03
M2
C1: SANYO 6TPA47M
C2: TAIYO YUDEN LMK325BJ106K-T M1, M2: Si3443DV
D1, D2: IR10BQ015 R1, R2: DALE 0.25W
L1, L2: MURATA LQN6C-4R7
Single Cell Li-Ion to 3.3V (Zeta Converter) and 1.8V (Buck Converter)
V
IN
2.7V to 4.2V
R7
C3 10µF
L1B
V
249k
OUT1
1
3
2
4
6
5
7
8
16
15
14
13
12
11
10
9
M1
–
+
SENSE1
SENSE1
V
3.3V
1A
•
R1
R6
78.7k
•
R10
47k
C6 470pF
C4 220pF
V
+
FB1
IN
0.025Ω
C2
L1A
D1
GND
C5
C1
I
/RUN1
PGATE1
22µF
TH
SGND
/RUN2
LTC3701
PGND
PGATE2
PGOOD
I
TH
100k
D2
R5
10k
R8
80.6k
V
V
IN
FB2
+
47µF
L2
4.7µH
PLLLPF EXTCLK/MODE
R9
100k
–
+
V
10k
10nF
OUT2
1.8V
2A
SENSE2
SENSE2
M2
R2
0.03Ω
3701 TA06
C1, C5: SANYO 6TPA47M
L1A, L1B: COILTRONICS CTX5-2
L2: MURATA LQN6C-4R7
M1, M2: Si3443DV
C2: TAIYO YUDEN JMK325BJ226MM
C3: TAIYO YUDEN JMK316BJ106ML
D1, D2: IR10BQ015
R1, R2: DALE 0.25W
3701fa
18
LTC3701
U
TYPICAL APPLICATIO S
2-Phase, Synchronizable Dual Output Step-Down DC/DC Converter with 4A Output Currents
1nF
V
IN
2.7V to 9.8V
R7
R1
169k
0.012Ω
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
M1
–
+
V
2.5V
4A
C2
10µF
OUT1
SENSE1
/RUN1
SENSE1
V
L1
R6
78.7k
R10
10k
10Ω
1µF
C6 220pF
C4 220pF
I
TH
IN
1.5µH
+
C1
V
FB1
PGATE1
D1
47µF
GND
LTC3701
SGND
PGND
PGATE2
PGOOD
V
I
FB2
100k
D2
R5
10k
C5
+
47µF
R8
80k
/RUN2
V
IN
TH
L2
1.5µH
PLLLPF EXTCLK/MODE
R9
100k
–
+
V
1.8V
4A
10k
10nF
OUT2
SENSE2
SENSE2
M2
R2
0.015Ω
1nF
D1, D2: IR30BQ015
3701 TA02
C1, C5: SANYO 6TPA47M
C2: TAIYO YUDEN LMK325BJ106K-T
M1, M2: Si9803DY
R1, R2: DALE 0.25W
L1, L2: COILCRAFT DO3316P-152
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN16 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3701fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
19
LTC3701
U
TYPICAL APPLICATIO
Dual Input Voltage Single Output, 2-Phase, 550kHz, Step-Down DC/DC Converter
V
IN1
2.5V TO 9.8V
R7
V
≥ V
IN1
IN2
169k
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
M1
–
+
V
2.5V
2A
SENSE1
/RUN1
SENSE1
OUT
R1
L1
I
TH
V
IN
0.03Ω
4.7µH
+
R8
10k
R6
78.7k
C2
C1
47µF
C5
220pF
D1
V
FB1
PGATE1
PGND
10µF
LTC3701
SGND
V
FB2
PGATE2
PGOOD
D2
I
TH
/RUN2
C3
10µF
L2
4.7µH
R2
0.03Ω
PLLLPF EXTCLK/MODE
–
+
SENSE2
SENSE2
M2
V
IN2
2.5V TO 9.8V
3701 TA04
C1: SANYO 6TPA47M
C2, C3: TAIYO YUDEN LMK325BJ106K-T
D1, D2: IR10BQ015
L1, L2: MURATA LQN6C-4R7
M1, M2: Si3443DV
R1, R2: DALE 0.25W
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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LTC1628/
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IN
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Q
OUT
IN
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I
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SD
Constant Frequency Current Mode Step-Down
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Up to 4A, SOT-23 Package, 550kHz
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IN
LTC1773
LTC1778
Synchronous Step-Down Controller
2.65V ≤ V ≤ 8.5V, I
Up to 4A, 10-Lead MSOP
OUT
IN
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Synchronous Step-Down Controller
Current Mode Operation Without Sense Resistor,
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SENSE
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LTC1872
LTC1929
Constant Frequency Current Mode Step-Up Controller
2.5V ≤ V ≤ 9.8V, SOT-23 Package, 550kHz
IN
Constant Frequency Current Mode 2-Phase
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IN
LTC3411
LTC3412
LTC3700
1.25A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.8V, I = 60µA,
Q
OUT
IN
OUT
OUT
I
= <1µA, MS Package
2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60µA,
Q
OUT
IN
I
= <1µA, TSSOP-16E Package
SD
Constant Frequency Step-Down Controller with LDO Regulator
2.65≤ V ≤ 9.8V, 550kHz, 10-Lead SSOP
IN
LTC3728/LTC3728L Dual, 550kHz, 2-Phase Synchronous Step-Down
Switching Regulator
Constant Frequency, V to 36V, 5V and 3.3V LDOs,
IN
5mm × 5mm QFN or 28-Lead SSOP
PolyPhase and No R
are trademarks of Linear Technology Corporation.
SENSE
3701fa
LT/TP 0403 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
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