LTC3703 [Linear]
100V Synchronous Switching Regulator Controller; 100V同步开关稳压控制器
| 型号： | LTC3703 |
| 厂家： | 
Linear |
| 描述： | 100V Synchronous Switching Regulator Controller |
| 文件： | 总32页 (文件大小：492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3703
100V Synchronous
Switching Regulator
Controller
U
FEATURES
DESCRIPTIO
The LTC®3703 is a synchronous step-down switching
regulator controller that can directly step-down voltages
from up to 100V, making it ideal for telecom and automo-
tive applications. The LTC3703 drives external N-channel
MOSFETs using a constant frequency (up to 600kHz),
voltage mode architecture. The external component count
has been minimized, providing a compact overall solution
footprint.
■
High Voltage Operation: Up to 100V
■
Large 1
Ω Gate Drivers
■
■
■
■
■
No Current Sense Resistor Required
Step-Up or Step-Down DC/DC Converter
Dual N-Channel MOSFET Synchronous Drive
Excellent Transient Response and DC Line Regulation
Programmable Constant Frequency: 100kHz to
600kHz
■
■
■
■
■
■
■
■
±1% Reference Accuracy
A precise internal reference provides 1% DC accuracy. A
high bandwidth error amplifier and patented line feed
forward compensation provide very fast line and load
transient response. Strong 1Ω gate drivers allow the
LTC3703 to drive multiple MOSFETs for higher current
applications. The operating frequency is user program-
mable from 100kHz to 600kHz and can also be synchro-
nized to an external clock for noise-sensitive applications.
Current limit is programmable with an external resistor
and utilizes the voltage drop across the synchronous
MOSFET to eliminate the need for a current sense resistor.
Soft- start is provided by an external capacitor. Pulling the
soft-start pin low shuts down the LTC3703, reducing
supply current to 50µA.
Synchronizable up to 600kHz
Selectable Pulse Skip Mode Operation
Low Shutdown Current: 50µA Typ
Programmable Current Limit
Undervoltage Lockout
Programmable Soft-Start
16-Pin Narrow SUSOP and 28-Pin SSOP Packages
APPLICATIO S
■
48V Telecom and Base Station Power Supplies
Networking Equipment, Servers
Automotive and Industrial Control
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
V
CC
9.3V TO 15V
+
V
22µF
25V
IN
Efficiency vs Load Current
15V TO 100V
BAS21
MODE/SYNC
V
IN
100
+
22µF
30k
×2
FSET
LTC3703
COMP
FB
BOOST
TG
V
IN
= 25V
Si7456DP
22k
95
90
85
80
V
= 50V
IN
0.1µF
3300pF
15pF
15k
8µH
V
IN
= 75V
SW
V
12V
5A
OUT
8.06k
1%
I
V
MAX
CC
10Ω
+
220µF
25V
×2
INV
DRV
CC
Si7456DP
MBR1100
0.1µF
RUN/SS
GND
BG
10µF
330Ω
113k
1%
BGRTN
0
1
2
3
4
5
1µF
1500pF
LOAD (A)
3703 F01b
3703 F01
Figure 1. High Efficiency High Voltage Step-Down Converter
3703f
1
LTC3703
W W U W
ABSOLUTE AXI U RATI GS (Note 1)
Supply Voltages
MODE/SYNC, INV Voltages....................... –0.3V to 15V
fSET, FB, IMAX Voltages ............................... –0.3V to 3V
Peak Output Current <10µs BG,TG ............................ 5A
Operating Temperature Range (Note 2) .. –40°C to 85°C
Junction Temperature (Notes 3, 7) ....................... 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
VCC, DRVCC .......................................... –0.3V to 15V
(DRVCC – BGRTN), (BOOST – SW) ...... –0.3V to 15V
BOOST................................................ –0.3V to 115V
BGRTN ...................................................... –5V to 0V
VIN Voltage ............................................. –0.3V to 100V
SW Voltage ................................................ –1V to 100V
Run/SS Voltage .......................................... –0.3V to 5V
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
TOP VIEW
NUMBER
V
1
2
28 BOOST
27 TG
IN
TOP VIEW
NC
LTC3703EGN
LTC3703EG
NC
NC
3
26 SW
25 NC
24 NC
23 NC
22 NC
MODE/SYNC
1
2
3
4
5
6
7
8
16
V
IN
4
f
15 B00ST
SET
NC
5
COMP
FB
14
13
12
11
10
9
TG
MODE/SYNC
6
SW
f
7
SET
I
V
CC
MAX
COMP
FB
8
21
V
CC
9
20 DRV
19 BG
18 NC
17 NC
16 NC
INV
RUN/SS
GND
DRV
BG
CC
CC
GN PART
MARKING
I
10
11
12
13
14
MAX
INV
NC
BGRTN
3703
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
RUN/SS
GND
15 BGRTN
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
BGRTN = 0V, RUN/SS = IMAX = open, RSET = 25k, unless otherwise specified.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = VBOOST = VIN = 10V, VMODE/SYNC = VINV = VSW
=
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
15
UNITS
V
V
, DRV
CC
IN
V
V
V
, DRV Supply Voltage
●
●
●
9.3
V
V
CC
CC
IN
CC
Pin Voltage
100
2.5
I
I
I
Supply Current
V = 0V
FB
RUN/SS = 0V
1.7
50
mA
µA
CC
CC
DRV Supply Current
(Note 5)
RUN/SS = 0V
0
0
5
5
µA
µA
DRVCC
BOOST
CC
BOOST Supply Current
(Note 5)
RUN/SS = 0V
●
360
0
500
5
µA
µA
3703f
2
LTC3703
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = VBOOST = VIN = 10V, VMODE/SYNC = VINV = VSW
BGRTN = 0V, RUN/SS = IMAX = open, RSET = 25k, unless otherwise specified.
=
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
V
Feedback Voltage
(Note 4)
0.792
0.788
0.800
0.808
0.812
V
V
FB
●
●
●
∆V
∆V
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
MODE/SYNC Threshold
MODE/SYNC Hysteresis
MODE/SYNC Current
9V < V < 15V (Note 4)
0.007
0.01
0.8
20
0.05
0.1
%/V
%
FB, LINE
CC
1V < V
< 2V (Note 4)
FB, LOAD
COMP
VMODE/SYNC
∆VMODE/SYNC
IMODE/SYNC
MODE/SYNC Rising
0.75
1
0.87
V
mV
µA
V
0 ≤ V ≤ 15V
0
1
2
1
MODE/SYNC
V
Invert Threshold
1.5
0
INV
INV
VIN
I
I
Invert Current
0 ≤ V ≤ 15V
µA
INV
V
Sense Input Current
V
= 100V
IN
100
0
140
1
µA
µA
IN
RUN/SS = 0V, V = 10V
IN
I
I
Source Current
V = 0V
IMAX
10.5
–25
0.7
2.5
9
12
10
0.9
4
13.5
55
µA
mV
V
MAX
MAX
V
V
V
Offset Voltage
|V | – V
at I
= 0µA
RUN/SS
OS, IMAX
RUN/SS
IMAX
SW
IMAX
Shutdown Threshold
1.2
5.5
25
I
RUN/SS Source Current
Maximum RUN/SS Sink Current
Undervoltage Lockout
RUN/SS = 0V
|V | – V
µA
µA
RUN/SS
> 100mV
IMAX
17
SW
V
V
V
Rising
●
●
8.0
5.7
8.7
6.2
9.3
6.8
V
V
UV
CC
CC
Falling
= 25kΩ
Oscillator
f
f
t
Oscillator Frequency
R
270
100
300
330
600
kHz
kHz
ns
OSC
SET
External Sync Frequency Range
Minimum On-Time
SYNC
ON, MIN
200
93
DC
Maximum Duty Cycle
f < 200kHz
89
1.5
1.5
96
%
MAX
Driver
I
BG Driver Peak Source Current
2
1
2
1
A
Ω
A
BG, PEAK
R
BG Driver Pull-Down R
(Note 8)
(Note 8)
(Note 4)
1.5
1.5
BG, SINK
TG, PEAK
DS, ON
I
TG Driver Peak Source Current
TG Driver Pull-Down R
R
Ω
TG, SINK
DS, ON
Feedback Amplifier
A
Op Amp DC Open Loop Gain
74
85
25
0
dB
MHz
µA
VOL
f
I
I
Op Amp Unity Gain Crossover Frequency (Note 6)
U
FB Input Current
0 ≤ V ≤ 3V
1
FB
FB
COMP Sink/Source Current
±5
±10
mA
COMP
Note 1: Absolute Maximum Ratings are those values beyond which the life of Note 5: The dynamic input supply current is higher due to the power
a device may be impaired.
MOSFET gate charging being delivered at the switching frequency
(Q • f ).
Note 6: Guaranteed by design. Not subject to test.
Note 7: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 2: The LTC3703E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
G
OSC
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
LTC3703: T = T + (P • 100 °C/W) G Package
J
A
D
Note 8: R
guaranteed by correlation to wafer level measurement.
Note 4: The LTC3703 is tested in a feedback loop that servos V to the
DS(ON)
FB
reference voltage with the COMP pin forced to a voltage between 1V and 2V.
3703f
3
LTC3703
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C (unless otherwise noted).
Load Transient Response
Efficiency vs Input Voltage
Efficiency vs Load Current
100
95
90
85
80
75
70
100
95
90
85
80
75
70
I
= 5A
OUT
V
OUT
V
= 15V
50mV/DIV
IN
V
= 45V
IN
I
= 0.5A
OUT
V
= 75V
I
IN
OUT
2A/DIV
V
OUT
= 12V
V
OUT
= 5V
50µs/DIV
V
V
= 50V
IN
OUT
f = 300kHz
PULSE SKIP DISABLED
f = 250kHz
PULSE SKIP ENABLED
= 12V
1A TO 5A LOAD STEP
3703 G03
0
40
INPUT VOLTAGE (V)
60 70
10 20 30
50
80
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD CURRENT (A)
3703 G01
3703 G02
VCC Shut-Down Current vs VCC
Voltage
VCC Current vs VCC Voltage
VCC Current vs Temperature
100
90
80
70
60
50
40
30
20
10
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4
COMP = 1.5V
COMP = 1.5V
3
2
1
0
V
FB
= 0V
V
FB
= 0V
20 40
TEMPERATURE (°C)
80
–60 –40 –20
0
100
8
10
VOLTAGE (V)
14
16
60
6
8
12
VOLTAGE (V)
14
6
12
10
V
CC
16
V
CC
3703 G05
3703 G04
3703 G06
Normalized Frequency vs
Temperature
V
CC Shut-Down Current vs
Reference Voltage vs
Temperature
Temperature
0.803
0.802
0.801
0.800
0.799
0.798
70
65
60
55
50
45
40
35
30
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
20 40
TEMPERATURE (°C)
80
20 40
TEMPERATURE (°C)
80
–60 –40 –20
0
20 40 60 80 100
–60 –40 –20
0
100
–60 –40 –20
0
100
60
60
TEMPERATURE (°C)
3703 G08
3703 G07
3703 G09
3703f
4
LTC3703
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Driver Peak Source Current vs
Temperature
Driver Peak Source Current vs
Supply Voltage
Driver Pull-Down RDS(ON) vs
Temperature
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 10V
V
= 10V
CC
CC
5
6
7
8
9
10 11 12 13 14 15
–60 –40 –20
0
20 40 60 80 100
–60 –40 –20
0
20 40 60 80 100
DRV /BOOST VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
CC
3703 G10
3703 G12
3703 G11
RUN/SS Pull-Up Current vs
Temperature
Driver Pull-Down RDS(ON) vs
Supply Voltage
Rise/Fall Time vs Gate
Capacitance
70
60
50
40
30
20
10
0
1.1
6
5
4
3
2
1
0
DRVCC, BOOST = 10V
1.0
0.9
RISE
0.8
FALL
0.7
0.6
0
2000
4000
6000
8000
10000
6
7
8
9
10 11 12 13 14 15
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
GATE CAPACITANCE (pF)
DRV /BOOST VOLTAGE (V)
CC
3703 G14
3703 G13
1573 G06
RUN/SS Pull-Up Current vs
VCC Voltage
RUN/SS Sink Current vs
SW Voltage
Max % DC vs RUN/SS Voltage
6
5
4
3
2
1
0
25
20
15
10
5
100
90
80
70
60
50
40
30
20
10
0
I
= 0.3V
MAX
0
–5
–10
–10
6
8
10
12
14
16
0
0.1
0.2 0.3
0.4
|SW| VOLTAGE (V)
0.5
0.6 0.7
0.5
1.0
1.5
2.0
2.5
3.0
V
VOLTAGE (V)
RUN VOLTAGE (V)
CC
3703 G16
3703 G17
3703 G18
3703f
5
LTC3703
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Max % DC vs Frequency and
Temperature
IMAX Current vs Temperature
% Duty Cycle vs COMP Voltage
100
80
60
40
20
0
13
12
11
100
95
90
85
80
75
70
V
= 10V
IN
–45°C
V
= 75V
IN
25°C
90°C
V
= 50V
IN
V
= 25V
IN
0.5
1.00 1.25 1.50
COMP (V)
1.75 2.00
0
100 200 300 400 500 600 700
FREQUENCY (kHz)
0.75
–60 –40 –20
0
20 40 60 80 100
TEMPERATURE (°C)
3703 G20
3703 G21
3703 G19
Shutdown Threshold vs
Temperature
tON(MIN) vs Temperature
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
160
140
120
100
80
60
40
20
0
–60 –40 –20
0
20 40 60 80 100
–60 –40 –20
0
20 40 60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
3703 G22
3703 G23
3703f
6
LTC3703
U
U
U
PI FU CTIO S
(GN16)
MODE/SYNC (Pin 1): Pulse Skip Mode Enable/Sync Pin.
This multifunction pin provides Pulse Skip Mode enable/
disable control and an external clock input for synchroni-
zation of the internal oscillator. Pulling this pin below 0.8V
or to an external logic-level synchronization signal dis-
ables Pulse Skip Mode operation and forces continuous
operation. Pulling the pin above 0.8V enables Pulse Skip
Mode operation. This pin can also be connected to a
feedback resistor divider from a secondary winding on the
inductor to regulate a second output voltage.
GND (Pin 8): Ground Pin.
BGRTN (Pin 9): Bottom Gate Return. This pin connects to
the source of the pull-down MOSFET in the BG driver and
is normally connected to ground. Connecting a negative
supply to this pin allows the synchronous MOSFET’s gate
to be pulled below ground to help prevent false turn-on
during high dV/dt transitions on the SW node. See the
Applications Information section for more details.
BG(Pin10):BottomGateDrive. TheBGpindrivesthegate
of the bottom N-channel synchronous switch MOSFET.
This pin swings from BGRTN to DRVCC.
fSET (Pin 2): Frequency Set. A resistor connected to this
pin sets the free running frequency of the internal oscilla-
tor. See applications section for resistor value selection
details.
DRVCC (Pin 11): Driver Power Supply Pin. DRVCC pro-
vides power to the BG output driver. This pin should be
connected to a voltage high enough to fully turn on the
external MOSFETs, normally 10V to 15V for standard
thresholdMOSFETs.DRVCC shouldbebypassedtoBGRTN
with a 10µF, low ESR (X5R or better) ceramic capacitor.
COMP (Pin 3): Loop Compensation. This pin is connected
directly to the output of the internal error amplifier. An RC
network is used at the COMP pin to compensate the
feedback loop for optimal transient response.
V
CC (Pin 12) :Main Supply Pin. All internal circuits except
FB (Pin 4): Feedback Input. Connect FB through a resistor
divider network to VOUT to set the output voltage. Also
connect the loop compensation network from COMP to
FB.
the output drivers are powered from this pin. VCC should
beconnectedtoalownoisepowersupplyvoltagebetween
9V and 15V and should be bypassed to GND (pin 8) with
atleasta0.1µFcapacitorincloseproximitytotheLTC3703.
IMAX (Pin 5): Current Limit Set. The IMAX pin sets the
current limit comparator threshold. If the voltage drop
across the bottom MOSFET exceeds the magnitude of the
voltage at IMAX, the controller goes into current limit. The
IMAX pin has an internal 12µA current source, allowing the
current threshold to be set with a single external resistor
to ground. See the Current Limit Programming section for
SW (Pin 13): Switch Node Connection to Inductor and
Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground to
VIN.
TG (Pin 14): Top Gate Drive. The TG pin drives the gate of
the top N-channel synchronous switch MOSFET. The TG
driver draws power from the BOOST pin and returns to the
SW pin, providing true floating drive to the top MOSFET.
more information on choosing RIMAX
.
INV(Pin6):Top/BottomGateInvert.Pullingthispinabove
2V sets the controller to operate in step-up (boost) mode
with the TG output driving the synchronous MOSFET and
the BG output driving the main switch. Below 1V, the
controller will operate in step-down (buck) mode.
BOOST (Pin 15): Top Gate Driver Supply. The BOOST pin
supplies power to the floating TG driver. The BOOST pin
should be bypassed to SW with a low ESR (X5R or better)
0.1µF ceramic capacitor. An additional fast recovery
Schottky diode from DRVCC to BOOST will create a com-
plete floating charge-pumped supply at BOOST.
RUN/SS (Pin 7): Run/Soft-Start. Pulling RUN/SS below
0.9V will shut down the LTC3703, turn off both of the
external MOSFET switches and reduce the quiescent sup-
ply current to 50µA. A capacitor from RUN/SS to ground
will control the turn-on time and rate of rise of the output
voltage at power-up. An internal 4µA current source pull-
up at the RUN/SS pin sets the turn-on time at approxi-
mately 750ms/µF.
VIN (Pin 16): Input Voltage Sense Pin. This pin is con-
nectedtothehighvoltageinputoftheregulatorandisused
by the internal feedforward compensation circuitry to
improve line regulation. This is not a supply pin.
3703f
7
LTC3703
U
U
W
FU CTIO AL DIAGRA
RSET
FSET
2
OVERCURRENT
12µA
4µA
I
MAX
–
+
5
R
MAX
50mV
–
+
±
RUN/SS
–
+
5
1
±
INV
CHIP
SD
C
SS
1V
3.2V
UVSD OTSD
V
CC
EXT SYNC
+
SYNC
DETECT
OSC
MODE/SYNC
COMP
–
D
B
BOOST
TG
V
IN
REVERSE
CURRENT
FORCED CONTINUOUS
INV
15
14
13
C
B
M1
3
4
SW
–
DRIVE
LOGIC
PWM
+
+
–
0.8V
% DC
LIMIT
+
FB
DRV
CC
÷
FB
11
10
BG
V
IN
16
M2
R1
R2
MIN
MAX
–
–
+
+
BGRTN
9
6
INV
0.84V
0.76V
V
CC
(<15V)
12
L1
OVER
TEMP
V
OUT
GND
8
BANDGAP
V
CC
UVLO
C
OUT
OT SD
0.8V
REFERENCE
INTERNAL
3.2V V
UV SD
CC
GN16
V
CC
C
VCC
3703 FD
U
OPERATIO
(Refer to Functional Diagram)
The LTC3703 is a constant frequency, voltage mode
controller for DC/DC step-down converters. It is designed
to be used in a synchronous switching architecture with
two external N-channel MOSFETs. Its high operating volt-
agecapabilityallowsittodirectlystepdowninputvoltages
up to 100V without the need for a step-down transformer.
For circuit operation, please refer to the Functional Dia-
gram of the IC and Figure 1. The LTC3703 uses voltage
mode control in which the duty ratio is controlled directly
by the error amplifier output and thus requires no current
sense resistor. The VFB pin receives the output voltage
feedbackandiscomparedtotheinternal0.8Vreferenceby
the error amplifier, which outputs an error signal at the
COMP pin. When the load current increases, it causes a
drop in the feedback voltage relative to the reference. The
COMPvoltagethenrises,increasingthedutyratiountilthe
3703f
8
LTC3703
U
OPERATIO
(Refer to Functional Diagram)
output feedback voltage again matches the reference
voltage. In normal operation, the top MOSFET is turned on
when the RS latch is set by the on-chip oscillator and is
turned off when the PWM comparator trips and resets the
latch. The PWM comparator trips at the proper duty ratio
bycomparingtheerroramplifieroutput(afterbeing“com-
pensated”bythelinefeedforwardmultiplier)toasawtooth
waveform generated by the oscillator. When the top
MOSFET is turned off, the bottom MOSFET is turned on
untilthenextcyclebeginsor, ifPulseSkipModeoperation
is enabled, until the inductor current reverses as deter-
mined by the reverse current comparator. MAX and MIN
comparators ensure that the output never exceed ±5% of
nominal value by monitoring VFB and forcing the output
back into regulation quickly by either keeping the top
MOSFET off or forcing maximum duty cycle. The opera-
tion of its other features—fast transient response, out-
standing line regulation, strong gate drivers, short-circuit
protection, and shutdown/soft-start—are described be-
low.
V
OUT
50mV/DIV
V
IN
20V/DIV
I
L
2A/DIV
3703 F02
V
LOAD
25V TO 60V V STEP
= 12V
= 1A
20µs/DIV
OUT
I
IN
Figure 2. Line Transient Performance
Strong Gate Drivers
The LTC3703 contains very low impedance drivers ca-
pable of supplying amps of current to slew large MOSFET
gates quickly. This minimizes transition losses and allows
paralleling MOSFETs for higher current applications. A
100V floating high side driver drives the top side MOSFET
and a low side driver drives the bottom side MOSFET (see
Figure 3). They can be powered from either a separate DC
supply or a voltage derived from the input or output
voltage (see MOSFET Driver Supplies section). The bot-
tom side driver is supplied directly from the DRVCC pin.
The top MOSFET drivers are biased from floating boot-
strap capacitor CB, which normally is recharged during
eachoffcyclethroughanexternaldiodefromDRVCC when
the top MOSFET turns off. In Pulse Skip Mode operation,
where it is possible that the bottom MOSFET will be off for
anextendedperiodoftime, aninternalcounterguarantees
that the bottom MOSFET is turned on at least once every
10 cycles for 10% of the period to refresh the bootstrap
capacitor. An undervoltage lockout keeps the LTC3703
shut down unless this voltage is above 9V.
Fast Transient Response
The LTC3703 uses a fast 25MHz op amp as an error
amplifier. This allows the compensation network to be
optimized for better load transient response. The high
bandwidth of the amplifier, along with high switching
frequencies and low value inductors, allow very high loop
crossover frequencies. The 800mV internal reference al-
lows regulated output voltages as low as 800mV without
external level shifting amplifiers.
Line Feedforward Compensation
TheLTC3703achievesoutstandinglinetransientresponse
using a patented feedforward correction scheme. With
this circuit the duty cycle is adjusted instantaneously to
changes in input voltage, thereby avoiding unacceptable
overshoot or undershoot. It has the added advantage of
making the DC loop gain independent of input voltage.
Figure 2 shows how large transient steps at the input have
little effect on the output voltage.
The bottom driver has an additional feature that helps
minimize the possibility of external MOSFET shoot-thru.
When the top MOSFET turns on, the switch node dV/dt
pulls up the bottom MOSFET’s internal gate through the
Millercapacitance, evenwhenthebottomdriverisholding
the gate terminal at ground. If the gate is pulled up high
enough, shoot-thru between the top side and bottom side
3703f
9
LTC3703
U
OPERATIO
(Refer to Functional Diagram)
cycle control set to 0%. As CSS continues to charge, the
duty cycle is gradually increased, allowing the output
voltagetorise.Thissoft-startschemesmoothlyrampsthe
output voltage to its regulated value, with no overshoot.
The RUN/SS voltage will continue ramping until it reaches
an internal 4V clamp. Then the MIN feedback comparator
is enabled and the LTC3703 is in full operation. When the
RUN/SS is low, the supply current is reduced to 50µA.
MOSFETs can occur. To prevent this from occuring, the
bottom driver return is brought out as a separate pin
(BGRTN) so that a negative supply can be used to reduce
theeffectoftheMillerpull-up.Forexample,ifa–2Vsupply
is used on BGRTN, the switch node dV/dt could pull the
gateup2VbeforetheVGS ofthebottomMOSFEThasmore
than 0V across it.
V
DRV
IN
CC
D
+
B
DRV
CC
LTC3703
BOOST
TG
C
IN
V
OUT
C
B
MT
0V
SW
NORMAL OPERATION
SHUTDOWN START-UP
L
CURRENT
LIMIT
V
OUT
MIN COMPARATOR ENABLED
4V
3V
BG
+
MB
OUTPUT VOLTAGE
IN REGULATION
C
OUT
BGRTN
0V TO –5V
RUN/SS SOFT-STARTS
OUTPUT VOLTAGE AND
INDUCTOR CURRENT
V
RUN/SS
3703 F03
1.4V
1V
Figure 3. Floating TG Driver Supply and Negative BG Return
MINIMUM
DUTY CYCLE
0V
LTC3703
POWER
Constant Frequency
3703 F04
ENABLE DOWN MODE
The internal oscillator can be programmed with an exter-
nalresistorconnectedfromfSET togroundtorun between
100kHz and 600kHz, thereby optimizing component size,
efficiency, and noise for the specific application. The
internal oscillator can also be synchronized to an external
clock applied to the MODE/SYNC pin and can lock to a
frequency in the 100kHz to 600kHz range. When locked to
an external clock, Pulse Skip Mode operation is automati-
callydisabled. Constantfrequencyoperationbringswithit
anumberofbenefits:Inductorandcapacitorvaluescanbe
chosenforapreciseoperatingfrequencyandthefeedback
loop can be similarly tightly specified. Noise generated by
the circuit will always be at known frequencies.
Subharmonic oscillation and slope compensation, com-
mon headaches with constant frequency current mode
switchers, are absent in voltage mode designs like the
LTC3703.
Figure 4. Soft-Start Operation in Start Up and Current Limit
Current Limit
TheLTC3703includesanonboardcurrentlimitcircuitthat
limitsthemaximumoutputcurrenttoauser-programmed
level. It works by sensing the voltage drop across the
bottom MOSFET and comparing that voltage to a user-
programmed voltage at the IMAX pin. Since the bottom
MOSFET looks like a low value resistor during its on-time,
the voltage drop across it is proportional to the current
flowinginit. Inabuckconverter, theaveragecurrentinthe
inductor is equal to the output current. This current also
flows through the bottom MOSFET during its on-time.
Thus by watching the drain-to-source voltage when the
bottom MOSFET is on, the LTC3703 can monitor the
output current. The LTC3703 senses this voltage and
inverts it to allow it to compare the sensed voltage (which
becomes more negative as peak current increases) with a
positive voltage at the IMAX pin. The IMAX pin includes a
12µA pull-up, enabling the user to set the voltage at IMAX
with a single resistor (RIMAX) to ground. See the Current
Shutdown/Soft-Start
The main control loop is shut down by pulling RUN/SS pin
low. Releasing RUN/SS allows an internal 4µA current
source to charge the soft-start capacitor CSS. When CSS
reaches 1V, the main control loop is enabled with the duty
Limit Programming section for RIMAX selection.
3703f
10
LTC3703
U
OPERATIO
For maximum protection, the LTC3703 current limit con-
sists of a steady-state limit circuit and an instantaneous
limit circuit. The steady-state limit circuit is a gm amplifier
that pulls a current from the RUN/SS pin proportional to
the difference between the SW and IMAX voltages. This
current begins to discharge the capacitor at RUN/SS,
reducing the duty cycle and controlling the output voltage
until the current regulates at the limit. Depending on the
size of the capacitor, it may take many cycles to discharge
the RUN/SS voltage enough to properly regulate the
output current. This is where the instantaneous limit
circuit comes into play. The instantaneous limit circuit is
a cycle-by-cycle comparator which monitors the bottom
MOSFET’s drain voltage and keeps the top MOSFET from
turning on whenever the drain voltage is 50mV above the
programmed max drain voltage. Thus the cycle-by-cycle
comparator will keep the inductor current under control
until the gm amplifier gains control.
cycles to maintain regulation. The frequency drops but
thisfurtherimprovesefficiencybyminimizinggatecharge
losses. Inforcedcontinuousmode, thebottomMOSFETis
always on when the top MOSFET is off, allowing the
inductor current to reverse at low currents. This mode is
lessefficientduetoresistivelosses, buthastheadvantage
of better transient response at low currents, constant
frequency operation, and the ability to maintain regulation
whensinkingcurrent. SeeFigure5foracomparisonofthe
effect on efficiency at light loads for each mode. The
MODE/SYNCthresholdis0.8V±7.5%,allowingtheMODE/
SYNC to act as a feedback pin for regulating a second
winding. If the feedback voltage drops below 0.8V, the
LTC3703 reverts to continuous operation to maintain
regulation in the secondary supply.
100
V
= 25V
= 75V
90
80
70
60
50
40
30
20
10
0
IN
V
IN
Pulse Skip Mode
V
= 25V
IN
V
The LTC3703 can operate in one of two modes selectable
with the MODE/SYNC pin—Pulse Skip Mode or forced
continuous mode. Pulse Skip Mode is selected when
increased efficiency at light loads is desired. In this mode,
the bottom MOSFET is turned off when inductor current
reverses to minimize the efficiency loss due to reverse
current flow. As the load is decreased (see Figure 6), the
duty cycle is reduced to maintain regulation until its
minimum on-time (~200ns) is reached. When the load
decreases below this point, the LTC3703 begins to skip
= 75V
IN
FORCED CONTINUOUS
PULSE SKIP MODE
10
100
1000
10000
LOAD (mA)
3703 F05
Figure 5. Efficiency in Pulse Skip/Forced Continuous Modes
PULSE SKIP MODE
FORCED CONTINUOUS
DECREASING
LOAD
CURRENT
3703 F06
Figure 6. Comparison of Inductor Current Waveforms for Pulse Skip Mode and Forced Continuous Operation
3703f
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LTC3703
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OPERATIO
Buck or Boost Mode Operation
The LTC3703 has the capability of operating both as a
step-down(buck)andstep-up(boost)controller. Inboost
mode, output voltages as high as 80V can be tightly
regulated. With the INV pin grounded, the LTC3703 oper-
ates in buck mode with TG driving the main (top side)
switch and BG driving the synchronous (bottom side)
switch. If the INV pin is pulled above 2V, the LTC3703
operates in boost mode with BG driving the main (bottom
side) switch and TG driving the synchronous (top side)
switch. Internalcircuitoperationisverysimilarregardless
of the operating mode with the following exceptions: In
boost mode, Pulse Skip Mode operation is always dis-
abled regardless of the level of the MODE/SYNC pin and
the line feedforward compensation is also disabled. The
overcurrentcircuitrycontinuestomonitortheloadcurrent
by looking at the drain voltage of the main (bottom side)
MOSFET. In boost mode, however, the peak MOSFET
current does not equal the load current but instead
ID = ILOAD/(1 – D). This factor needs to be taken into
account when programming the IMAX voltage.
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The basic LTC3703 application circuit is shown in
Figure 1. External component selection is determined by
theinputvoltageandloadrequirementsasexplainedinthe
following sections. After the operating frequency is se-
lected, RSET andLcanbechosen. Theoperatingfrequency
and the inductor are chosen for a desired amount of ripple
current and also to optimize efficiency and component
size. Next, the power MOSFETs and D1 are selected based
on voltage, load and efficiency requirements. CIN is se-
lected for its ability to handle the large RMS currents in the
converter and COUT is chosen with low enough ESR to
meet the output voltage ripple and transient specifica-
tions. Finally, the loop compensation components are
chosen to meet the desired transient specifications.
noise-sensitive communications systems, it is often de-
sirable to keep the switching noise out of a sensitive
frequency band.
The LTC3703 uses a constant frequency architecture that
can be programmed over a 100kHz to 600kHz range with
a single resistor from the fSET pin to ground, as shown in
Figure 1. The nominal voltage on the fSET pin is 1.2V, and
the current that flows from this pin is used to charge and
discharge an internal oscillator capacitor. The value of
RSET for a given operating frequency can be chosen from
Figure 7 or from the following equation:
7100
RSET (kΩ) =
f(kHz)– 25
Operating Frequency
1000
The choice of operating frequency and inductor value is a
trade off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses and gate charge losses. How-
ever, lower frequency operation requires more induc-
tance for a given amount of ripple current, resulting in a
larger inductor size and higher cost. If the ripple current
is allowed to increase, larger output capacitors may be
required to maintain the same output ripple. For convert-
ers with high step-down VIN to VOUT ratios, another
consideration is the minimum on-time of the LTC3703
(see the Minimum On-time Considerations section). A
final consideration for operating frequency is that in
100
10
1
200
400
600
800
1000
0
FREQUENCY (kHz)
3703 F07
Figure 7. Timing Resistor (RSET) Value
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U
The oscillator can also be synchronized to an external
clock applied to the MODE/SYNC pin with a frequency in
the range of 100kHz to 600kHz (refer to the MODE/SYNC
Pin section for more details). In this synchronized mode,
Pulse Skip Mode operation is disabled. The clock high
level must exceed 2V for at least 25ns. As shown in
Figure 8, the top MOSFET turn-on will follow the rising
edgeoftheexternalclockbyaconstantdelayequaltoone-
tenth of the cycle period.
ripple current occurs at the highest VIN. To guarantee that
ripple current does not exceed a specified maximum, the
inductor in buck mode should be chosen according to:
VOUT
f ∆IL(MAX)
VOUT
V
IN(MAX)
L ≥
1–
The inductor also has an affect on low current operation
when Pulse Skip Mode operation is enabled. The fre-
quency begins to decrease when the output current drops
below the average inductor current at which the LTC3703
is operating at its tON(MIN) in discontinuous mode (see
Figure 6). Lower inductance increases the peak inductor
current that occurs in each minimum on-time pulse and
thus increases the output current at which the frequency
starts decreasing.
2V TO 10V
MODE/
SYNC
t
= 25ns
MIN
0.8T
T
T = 1/f
O
TG
D = 40%
0.1T
Power MOSFET Selection
The LTC3703 requires at least two external N-channel
power MOSFETs, one for the top (main) switch and one or
more for the bottom (synchronous) switch. The number,
type and “on” resistance of all MOSFETs selected take into
account the voltage step-down ratio as well as the actual
position (main or synchronous) in which the MOSFET will
be used. A much smaller and much lower input capaci-
tance MOSFET should be used for the top MOSFET in
applications that have an output voltage that is less than
I
L
3703 F08
Figure 8. MODE/SYNC Clock Input and Switching
Waveforms for Synchronous Operation
Inductor
The inductor in a typical LTC3703 circuit is chosen for a
specific ripple current and saturation current. Given an
input voltage range and an output voltage, the inductor
value and operating frequency directly determine the
ripple current. The inductor ripple current in the buck
mode is:
1/3oftheinputvoltage. InapplicationswhereVIN >>VOUT
,
the top MOSFETs’ “on” resistance is normally less impor-
tant for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufac-
turers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
inputcapacitanceforthemainswitchapplicationinswitch-
ing regulators.
VOUT
(f)(L)
VOUT
V
IN
∆IL =
1–
Selection criteria for the power MOSFETs include the “on”
resistance RDS(ON), input capacitance, breakdown voltage
and maximum output current.
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus highest efficiency operation is obtained at low
frequency with small ripple current. To achieve this how-
ever, requires a large inductor.
The most important parameter in high voltage applica-
tions is breakdown voltage BVDSS. Both the top and
bottom MOSFETs will see full input voltage plus any
additional ringing on the switch node across its drain-to-
source during its off-time and must be chosen with the
3703f
A reasonable starting point is to choose a ripple current
between 20% and 40% of IO(MAX). Note that the largest
13
LTC3703
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APPLICATIO S I FOR ATIO
VOUT
V
IN
appropriate breakdown specification. Since many high
voltage MOSFETs have higher threshold voltages (typi-
cally, VGS(MIN) ≥ 6V), the LTC3703 is designed to be used
with a 9V to 15V gate drive supply (DRVCC pin).
MainSwitchDutyCycle =
V – VOUT
IN
SynchronousSwitchDutyCycle =
V
IN
For maximum efficiency, on-resistance RDS(ON) and input
capacitanceshouldbeminimized. LowRDS(ON) minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 9).
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
2
IMAX
1– DMAX
P
MAIN = DMAX
(1+ δ)RDR(ON) +
1
2
IMAX
2
V
IN
VOUT
(RDR)(CMILLER)•
1– DMAX
MILLER EFFECT
V
V
GS
1
1
+
(f)
a
b
V
CC – VTH(IL) VTH(IL)
+
–
V
DS
+
Q
IN
V
GS
1
–
C
= (Q – Q )/V
B A DS
MILLER
P
SYNC
=
(IMAX)2(1+ δ)RDS(0N)
3703 F09
1– DMAX
Figure 9. Gate Charge Characteristic
where δ is the temperature dependency of RDS(ON), RDR is
the effective top driver resistance (approximately 2Ω at
VGS = VMILLER), VIN is the drain potential and the change
indrainpotentialintheparticularapplication. VTH(IL) isthe
data sheet specified typical gate threshold voltage speci-
fied in the power MOSFET data sheet at the specified drain
current. CMILLER is the calculated capacitance using the
gate charge curve from the MOSFET data sheet and the
technique described above.
BothMOSFETshaveI2RlosseswhilethetopsideN-channel
equationincludesanadditionaltermfortransitionlosses,
which peak at the highest input voltage. For VIN < 25V, the
high current efficiency generally improves with larger
MOSFETs, while for VIN > 25V, the transition losses
rapidly increase to the point that the use of a higher
RDS(ON)devicewithlowerCMILLERactuallyprovideshigher
efficiency. The synchronous MOSFET losses are greatest
athighinputvoltagewhenthetopswitchdutyfactorislow
or during a short circuit when the synchronous switch is
on close to 100% of the period.
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initialslopeistheeffectofthegate-to-sourceandthegate-
to-drain capacitance. The flat portion of the curve is the
resultoftheMillermultiplicationeffectofthedrain-to-gate
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
drain-to-gate accumulation capacitance and the gate-to-
source capacitance. The Miller charge (the increase in
coulombsonthehorizontalaxisfromatobwhilethecurve
is flat) is specified for a given VDS drain voltage, but can be
adjusted for different VDS voltages by multiplying by the
ratio of the application VDS to the curve specified VDS
values. A way to estimate the CMILLER term is to take the
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated VDS voltage
specified. CMILLER is the most important selection criteria
fordeterminingthetransitionlossterminthetopMOSFET
but is not directly specified on MOSFET data sheets. CRSS
and COS are specified sometimes but definitions of these
parameters are not included.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, and
typically varies from 0.005/°C to 0.01/°C depending on
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
the particular MOSFET used.
3703f
14
LTC3703
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U
MultipleMOSFETscanbeusedinparalleltolowerRDS(ON) Because tantalum and OS-CON capacitors are not avail-
and meet the current and thermal requirements if desired. able in voltages above 30V, for regulators with input
The LTC3703 contains large low impedance drivers ca- supplies above 30V, choice of input capacitor type is
pable of driving large gate capacitances without signifi- limited to ceramics or aluminum electrolytics. Ceramic
cantly slowing transition times. In fact, when driving capacitors have the advantage of very low ESR and can
MOSFETs with very low gate charge, it is sometimes handle high RMS current, however ceramics with high
helpful to slow down the drivers by adding small gate voltage ratings (>50V) are not available with more than a
resistors (5Ω or less) to reduce noise and EMI caused by few microfarads of capacitance. Furthermore, ceramics
the fast transitions.
have high voltage coefficients which means that the ca-
pacitance values decrease even more when used at the
rated voltage. X5R and X7R type ceramics are recom-
mended for their lower voltage and temperature coeffi-
cients. Another consideration when using ceramics is
their high Q which if not properly damped, may result in
excessive voltage stress on the power MOSFETs. Alumi-
num electrolytics have much higher bulk capacitance,
however, they have higher ESR and lower RMS current
ratings.
Schottky Diode Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on and storing charge during the
dead time and requiring a reverse recovery period that
could cost as much as 1% to 2% in efficiency. A 1A
Schottky diode is generally a good size for 3A to 5A
regulators. Larger diodes result in additional losses due to
theirlargerjunctioncapacitance.Thediodecanbeomitted
if the efficiency loss can be tolerated.
A good approach is to use a combination of aluminum
electrolytics for bulk capacitance and ceramics for low
ESR and RMS current. If the RMS current cannot be
handled by the aluminum capacitors alone, when used
together, the percentage of RMS current that will be
suppliedbythealuminumcapacitorisreducedtoapproxi-
mately:
Input Capacitor Selection
In continuous mode, the drain current of the top MOSFET
is approximately a square wave of duty cycle VOUT/VIN
which must be supplied by the input capacitor. To prevent
large input transients, a low ESR input capacitor sized for
the maximum RMS current is given by:
1
%IRMS,ALUM
≈
•100%
2
1+ (8fCRESR
)
1/2
where RESR is the ESR of the aluminum capacitor and C is
theoverallcapacitanceoftheceramiccapacitors.Usingan
aluminum electrolytic with a ceramic also helps damp the
high Q of the ceramic, minimizing ringing.
VOUT
V
IN
V
IN
VOUT
ICIN(RMS) IO(MAX)
– 1
This formula has a maximum at VIN = 2VOUT, where IRMS
= IO(MAX)/2. This simple worst-case condition is com-
monlyusedfordesignbecauseevensignificantdeviations
donotoffermuchrelief.Notethattheripplecurrentratings
from capacitor manufacturers are often based on only
2000hoursoflife.Thismakesitadvisabletofurtherderate
the capacitor or to choose a capacitor rated at a higher
temperaturethanrequired.Severalcapacitorsmayalsobe
placedinparalleltomeetsizeorheightrequirementsinthe
design.
Output Capacitor Selection
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple. The output ripple
(∆VOUT) is approximately equal to:
1
∆VOUT ≤ ∆IL ESR +
8fCOUT
3703f
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LTC3703
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APPLICATIO S I FOR ATIO
Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. ESR also has a signifi-
cant effect on the load transient response. Fast load
transitions at the output will appear as voltage across the
ESR of COUT until the feedback loop in the LTC3703 can
change the inductor current to match the new load current
value. Typically, once the ESR requirement is satisfied the
capacitance is adequate for filtering and has the required
RMS current rating.
sensing. The resultant feedback signal is compared with
the internal precision 800mV voltage reference by the
error amplifier. The internal reference has a guaranteed
tolerance of ±1%. Tolerance of the feedback resistors will
add additional error to the output voltage. 0.1% to 1%
resistors are recommended.
MOSFET Driver Supplies (DRVCC and BOOST)
The LTC3703 drivers are supplied from the DRVCC and
BOOST pins (see Figure 3), which have an absolute
maximum voltage of 15V. If the main supply voltage, VIN,
is higher than 15V a separate supply with a voltage
between 9V and 15V must be used to power the drivers. If
a separate supply is not available, one can easily be
generated from the main supply using one of the circuits
shown in Figure 10. If the output voltage is between 10V
and 15V, the output can be used to directly power the
drivers as shown in Figure 10a. If the output is below 10V,
Figure 10b shows an easy way to boost the supply voltage
to a sufficient level. This boost circuit uses the LT1613 in
a ThinSOTTMpackage and a chip inductor for minimal extra
area (<0.2 in2). Two other possible schemes are an extra
winding on the inductor (Figure 10c) or a capacitive
charge pump (Figure 10d). All the circuits shown in
Figure 10 require a start-up circuit (Q1, D1 and R1) to
providedriverpoweratinitialstart-uporfollowingashort-
circuit. The resistor R1 must be sized so that it supplies
sufficientbasecurrentandzenerbiascurrentatthelowest
expected value of VIN. When using an existing supply, the
supply must be capable of supplying the required gate
driver current which can be estimated from:
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance
throughhole capacitors. The OS-CON (organic semicon-
ductor dielectric) capacitor available from Sanyo has the
lowest product of ESR and size of any aluminum electro-
lytic at a somewhat higher price. An additional ceramic
capacitor in parallel with OS-CON capacitors is recom-
mended to reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, spe-
cial polymer and aluminum electrolytic capacitors are
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Several excellent surge-tested choices
are the AVX TPS and TPSV or the KEMET T510 series.
Aluminumelectrolyticcapacitorshavesignificantlyhigher
ESR,butcanbeusedincost-drivenapplicationsproviding
that consideration is given to ripple current ratings and
long term reliability. Other capacitor types include
Panasonic SP and Sanyo POSCAPs.
IDRVCC = (f)(QG(TOP) + QG(BOTTOM)
)
This equation for IDRVCC is also useful for properly sizing
the circuit components shown in Figure 10.
Output Voltage
An external bootstrap capacitor, CB, connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFETs. Capacitor CB is charged through external
diode, DB, from the DRVCC supply when SW is low. When
the top side MOSFET is turned on, the driver places the CB
voltage across the gate-source of the top MOSFET. The
switch node voltage, SW, rises to VIN and the BOOST pin
follows. With the topside MOSFET on, the boost voltage
The LTC3703 output voltage is set by a resistor divider
according to the following formula:
R1
VOUT = 0.8V 1+
R2
The external resistor divider is connected to the output as
shownintheFunctionalDiagram, allowingremotevoltage
3703f
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D2
ZHCS400
L2
10µH
V
V
IN
IN
+
C10
1µF
16V
C9
4.7µF
6.3V
1µF
R17
1M
V
SW
IN
1%
+
LT1613
C
V
IN
SHDN
FB
12V
+
R17
110k
1%
C
GND
IN
V
IN
IN
LTC3703
12V
LTC3703
TG
SW
BG
TG
SW
BG
V
OUT
10V TO
15V
V
<10V
OUT
L1
L1
V
V
CC
CC
+
+
C
C
DRV
CC
OUT
DRV
OUT
CC
BGRTN
BGRTN
3703 F10a
3703 F10b
Figure 10a. VCC Generated from 10V < VOUT < 15V
Figure 10b. VCC Generated from VOUT < 10V
V
(<40V)
IN
V
IN
+
1µF
+
C
IN
OPTIONAL V
+
CC
CONNECTION
10V < V < 15V
C
IN
SEC
12V
BAT85
12V
BAT85
V
IN
V
IN
V
SEC
+
+
LTC3703
0.22µF
VN2222LL
LTC3703
BAT85
1µF
N
1
V
TG1
SW
CC
TG
SW
BG
T1
V
OUT
V
OUT
DRV
FCB
L1
CC
V
CC
R1
R2
+
C
BG1
OUT
C
DRV
OUT
CC
GND
BGRTN
BGRTN
3703 F10c
3703 F10d
Figure 10c. Secondary Output Loop and VCC Connection
Figure 10d. Capacitive Charge Pump for VCC (VIN < 40V)
is above the input supply: VBOOST = VIN + VDRVCC. The
value of the boost capacitor CB needs to be 100 times that
of the total input capacitance of the top side MOSFET(s).
The reverse breakdown of the external diode, DB, must be
greater than VIN(MAX). Another important consideration
for the external diode is the reverse recovery and reverse
leakage, either of which may cause excessive reverse
current to flow at full reverse voltage. If the reverse
current times reverse voltage exceeds the maximum
allowable power dissipation, the diode may be damaged.
For best results, use an ultrafast recovery silicon diode
such as the BAS21.
An internal undervoltage lockout (UVLO) monitors the
voltage on DRVCC to ensure that the LTC3703 has suffi-
cient gate drive voltage. If the DRVCC voltage falls below
theUVLOthreshold,theLTC3703shutsdownandthegate
drive outputs remain low.
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Bottom MOSFET Source Supply (BGRTN)
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Thebottomgatedriver,BG,switchesfromDRVCCtoBGRTN
where BGRTN can be a voltage between ground and –5V.
Why not just keep it simple and always connect BGRTN to
ground? In high voltage switching converters, the switch
node dV/dt can be many volts/ns, which will pull up on the
gateofthebottomMOSFETthroughitsMillercapacitance.
If this Miller current, times the internal gate resistance of
theMOSFETplusthedriverresistance,exceedsthethresh-
old of the FET, shoot-through will occur. By using a nega-
tive supply on BGRTN, the BG can be pulled below ground
when turning the bottom MOSFET off. This provides a few
extra volts of margin before the gate reaches the turn-on
threshold of the MOSFET. Be aware that the maximum
voltage difference between DRVCC and BGRTN is 15V. If,
for example, VBGRTN = –2V, the maximum voltage on
DRVCC pin is now 13V instead of 15V.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
resistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable assumption is that the minimum RDS(ON) lies
the same amount below the typical value as the maximum
liesaboveit.ConsulttheMOSFETmanufacturerforfurther
guidelines.
For best results, use a VPROG voltage between 100mV and
500mV. Values outside of this range may give less accu-
rate current limit. The current limit can also be disabled by
floating the IMAX pin.
FEEDBACK LOOP/COMPENSATION
Feedback Loop Types
Current Limit Programming
Programming current limit on the LTC3703 is straight
forward. The IMAX pin sets the current limit by setting the
maximum allowable voltage drop across the bottom
MOSFET. The voltage across the MOSFET is set by its on-
resistance and the current flowing in the inductor, which
is the same as the output current. The LTC3703 current
limitcircuitinvertsthenegativevoltageacrosstheMOSFET
before comparing it to the voltage at IMAX, allowing the
current limit to be set with a positive voltage.
In a typical LTC3703 circuit, the feedback loop consists of
the modulator, the external inductor, the output capacitor
andthefeedbackamplifierwithitscompensationnetwork.
All of these components affect loop behavior and must be
accounted for in the loop compensation. The modulator
consistsoftheinternalPWMgenerator,theoutputMOSFET
drivers and the external MOSFETs themselves. From a
feedback loop point of view, it looks like a linear voltage
transferfunctionfromCOMPtoSWandhasagainroughly
equal to the input voltage. It has fairly benign AC behavior
at typical loop compensation frequencies with significant
phase shift appearing at half the switching frequency.
To set the current limit, calculate the expected voltage
drop across the bottom MOSFET at the maximum desired
current and maximum junction temperature:
VPROG = (ILIMIT)(RDS(ON))(1 + δ
where
)
Theexternalinductor/outputcapacitorcombinationmakes
a more significant contribution to loop behavior. These
componentscauseasecondorderLCrolloffattheoutput,
with the attendant 180° phase shift. This rolloff is what
filters the PWM waveform, resulting in the desired DC
output voltage, but the phase shift complicates the loop
compensation if the gain is still higher than unity at the
pole frequency. Eventually (usually well above the LC pole
frequency), the reactance of the output capacitor will
approach its ESR and the rolloff due to the capacitor
will stop, leaving 6dB/octave and 90° of phase shift
δ
is explained in the MOSFET Selection section.
VPROG is then programmed at the IMAX pin using the
internal 12µA pull-up and an external resistor:
RIMAX = VPROG/12µA
The current limit value should be checked to ensure that
ILIMIT(MIN) >IOUT(MAX).Theminimumvalueofcurrentlimit
generally occurs with the largest VIN at the highest ambi-
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
(Figure 11).
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U
C2
C1
IN
R2
–
–6dB/OCT
GAIN
R1
FB
GAIN
A
V
–6dB/OCT
–12dB/OCT
0
FREQ
–90
R
OUT
0
FREQ
–90
B
PHASE
V
REF
+
–180
–270
–360
–180
–270
–360
–6dB/OCT
PHASE
3703 F11
3703 F13
Figure 13. Type 2 Schematic and Transfer Function
Figure 11. Transfer Function of Buck Modulator
total phase shift due to the LC. The additional phase
compensation in the feedback amplifier allows the 0dB
point to be at or above the LC pole frequency, improving
loop bandwidth substantially over a simple Type 1 loop. It
has limited ability to compensate for LC combinations
where low capacitor ESR keeps the phase shift near 180°
for an extended frequency range. LTC3703 circuits using
conventional switching grade electrolytic output capaci-
tors can often get acceptable phase margin with Type 2
compensation.
So far, the AC response of the loop is pretty well out of the
user’scontrol.Themodulatorisafundamentalpieceofthe
LTC3703 design and the external L and C are usually
chosen based on the regulation and load current require-
ments without considering the AC loop response. The
feedback amplifier, on the other hand, gives us a handle
with which to adjust the AC response. The goal is to have
180° phase shift at DC (so the loop regulates) and some-
thing less than 360° phase shift at the point that the loop
gain falls to 0dB. The simplest strategy is to set up the
feedback amplifier as an inverting integrator, with the 0dB
frequency lower than the LC pole (Figure 12). This “Type
1” configuration is stable but transient response is less
than exceptional if the LC pole is at a low frequency.
“Type 3” loops (Figure 14) use two poles and two zeros to
obtain a 180° phase boost in the middle of the frequency
band. A properly designed Type 3 circuit can maintain
acceptable loop stability even when low output capacitor
ESR causes the LC section to approach 180° phase shift
well above the initial LC roll-off. As with a Type 2 circuit,
the loop should cross through 0dB in the middle of the
phase bump to maximize phase margin. Many LTC3703
circuitsusinglowESRtantalumorOS-CONoutputcapaci-
torsneedType3compensationtoobtainacceptablephase
margin with a high bandwidth feedback loop.
C1
IN
GAIN
R1
FB
–
–6dB/OCT
R
OUT
0
FREQ
–90
B
V
+
REF
–180
–270
–360
PHASE
IN
C2
3703 F12
C1
C3
R3
R2
Figure 12. Type 1 Schematic and Transfer Function
R1
–6dB/OCT
GAIN
FB
–
+6dB/OCT
–6dB/OCT
Figure 13 shows an improved “Type 2” circuit that uses an
additional pole-zero pair to temporarily remove 90° of
phase shift. This allows the loop to remain stable with 90°
more phase shift in the LC section, provided the loop
reaches 0dB gain near the center of the phase “bump.”
Type 2 loops work well in systems where the ESR zero in
the LC roll-off happens close to the LC pole, limiting the
R
OUT
0
FREQ
–90
B
V
+
REF
–180
–270
–360
PHASE
3703 F14
Figure 14. Type 3 Schematic and Transfer Function
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*3703 modulator gain/phase
*2003 Linear Technology
*this file written to run with PSpice 8.0
*may require modifications for other
SPICE simulators
Feedback Component Selection
Selecting the R and C values for a typical Type 2 or Type 3
loop is a nontrivial task. The applications shown in this
data sheet show typical values, optimized for the power
components shown. They should give acceptable perfor-
mance with similar power components, but can be way off
if even one major power component is changed signifi-
cantly. Applications that require optimized transient re-
sponse will require recalculation of the compensation
values specifically for the circuit in question. The underly-
ing mathematics are complex, but the component values
can be calculated in a straightforward manner if we know
the gain and phase of the modulator at the crossover
frequency.
*MOSFETs
rfet mod sw 0.02
;MOSFET rdson
*inductor
lext sw out1 10u
rl out1 out 0.015
;inductor value
;inductor series R
*output cap
cout out out2 540u
resr out2 0 0.01
;capacitor value
;capacitor ESR
Modulator gain and phase can be measured directly from
a breadboard or can be simulated if the appropriate
parasitic values are known. Measurement will give more
accurateresults,butsimulationcanoftengetcloseenough
to give a working system. To measure the modulator gain
and phase directly, wire up a breadboard with an LTC3703
and the actual MOSFETs, inductor and input and output
capacitors that the final design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close to
the LTC3703, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
amplifier as a simple Type 1 loop, with a 10k resistor from
VOUT to FB and a 0.1µF feedback capacitor from COMP to
FB. Choose the bias resistor (RB) as required to set the
desired output voltage. Disconnect RB from ground and
connect it to a signal generator or to the source output of
a network analyzer to inject a test signal into the loop.
Measure the gain and phase from the COMP pin to the
output node at the positive terminal of the output capaci-
tor. Make sure the analyzer’s input is AC coupled so that
the DC voltages present at both the COMP and VOUT nodes
don’t corrupt the measurements or damage the analyzer.
*3703 internals
emod mod 0 value = {57*v(comp)}
;3703multiplier
vstim comp 0 0 ac 1 ;ac stimulus
.ac dec 100 1k 1meg
.probe
.end
With the gain/phase plot in hand, a loop crossover fre-
quency can be chosen. Usually the curves look something
like Figure 11. Choose the crossover frequency in the
rising or flat parts of the phase curve, beyond the external
LC poles. Frequencies between 10kHz and 50kHz usually
work well. Note the gain (GAIN, in dB) and phase (PHASE,
in degrees) at this point. The desired feedback amplifier
gain will be -GAIN to make the loop gain at 0dB at this
frequency.Nowcalculatetheneededphaseboost,assum-
ing 60° as a target phase margin:
BOOST = –(PHASE + 30°)
If the required BOOST is less than 60°, a Type 2 loop can
be used successfully, saving two external components.
BOOST values greater than 60° usually require Type 3
loops for satisfactory performance.
If breadboard measurement is not practical, a SPICE
simulation can be used to generate approximate gain/
phase curves. Plug the expected capacitor, inductor and
MOSFET values into the following SPICE deck and gener-
ate an AC plot of V(VOUT )/V(COMP) in dB and phase of
VOUT in degrees. Refer to your SPICE manual for details of
how to generate this plot.
Finally, choose a convenient resistor value for R1 (10k is
usuallyagoodvalue). Nowcalculatetheremainingvalues:
(K is a constant used in the calculations)
f = chosen crossover frequency
G = 10(GAIN/20) (this converts GAIN in dB to G in
absolute gain)
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U
section. An example of a boost converter circuit is shown
intheTypicalApplicationssection.TooperatetheLTC3703
in boost mode, the INV pin should be tied to the VCC
voltage (or a voltage above 2V). Note that in boost mode,
pulse-skip operation and the line feedforward compensa-
tion are disabled.
TYPE 2 Loop:
BOOST
K = tan
+ 45°
2
1
C2 =
2π • f •G •K •R1
C1= C2 K2 −1
For a boost converter, the duty cycle of the main switch is:
(
)
VOUT – V
IN
D =
K
VOUT
R2 =
RB =
2π • f •C1
For high VOUT to VIN ratios, the maximum VOUT is limited
by the LTC3703’s maximum duty cycle which is typically
93%. The maximum output voltage is therefore:
VREF(R1)
VOUT − VREF
V
IN(MIN)
VOUT(MAX)
=
14V
IN(MIN)
TYPE 3 Loop:
BOOST
1– DMAX
K = tan2
+ 45°
Boost Converter: Inductor Selection
4
In a boost converter, the average inductor current equals
the average input current. Thus, the maximum average
inductor current can be calculated from:
1
C2 =
2π • f •G •R1
IO(MAX)
1− DMAX
C1= C2 K −1
VO
V
IN(MIN)
(
)
IL(MAX)
=
= IO(MAX) •
K
R2 =
R3 =
C3 =
Similartoabuckconverter, choosetheripplecurrenttobe
20% to 40% of IL(MAX). The ripple current amplitude then
determines the inductor value as follows:
2π • f •C1
R1
K − 1
V
1
IN(MIN)
L =
•DMAX
∆IL • f
2πf K • R3
VREF(R1)
The minimum required saturation current for the inductor
RB =
is:
VOUT − VREF
IL(SAT) > IL(MAX) + ∆IL/2
Boost Converter Design
Boost Converter: Power MOSFET Selection
For information about choosing power MOSFETs for a
boostconverter, seethePowerMOSFETSelectionsection
for the buck converter, since MOSFET selection is similar.
However,notethatthepowerdissipationequationsforthe
MOSFETsatmaximumoutputcurrentinaboostconverter
are:
The following sections discuss the use of the LTC3703 as
a step-up (boost) converter. In boost mode, the LTC3703
can step-up output voltages as high as 80V. These sec-
tions discuss only the design steps specific to a boost
converter. For the design steps common to both a buck
and a boost, see the applicable section in the buck mode
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2
discussion in Input Capacitor section for the buck con-
verter). With this combination, the ripple voltage can be
improved significantly. The low ESR ceremic capacitor
will minimize the ESR step, while the electrolytic will
supply the required bulk capacitance.
IMAX
1– DMAX
P
MAIN = DMAX
1+ δ RDS(ON)
+
(
)
2
1
2
IMAX
VOUT
RDR CMILLER
•
(
)(
)
1– DMAX
Boost Converter: Input Capacitor Selection
1
1
+
f
( )
Theinputcapacitorofaboostconverterislesscriticalthan
the output capacitor, due to the fact that the inductor is in
series with the input and the input current waveform is
continuous. The input voltage source impedance deter-
mines the size of the input capacitor, which is typically in
the range of 10µF to 100µF. A low ESR capacitor is
recommended though not as critical as for the output
capacitor.
VCC – VTH(IL) VTH(IL)
2
) (
1
P
SYNC
= –
IMAX 1+ δ RDS(ON)
(
)
1– DMAX
Boost Converter: Output Capacitor Selection
In boost mode, the output capacitor requirements are
moredemandingduetothefactthatthecurrentwaveform
ispulsedinsteadofcontinuousasinabuckconverter. The
choice of component(s) is driven by the acceptable ripple
voltage which is affected by the ESR, ESL and bulk
capacitance as shown in Figure 15. The total output ripple
voltage is:
The RMS input capacitor ripple current for a boost con-
verter is:
V
IN(MIN)
IRMS(CIN) = 0.3 •
•DMAX
L• f
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to the
input of the converter and solid tantalum capacitors can
fail catastrophically under these conditions. Be sure to
specify surge-tested capacitors!
1
ESR
∆VOUT = IO(MAX)
+
f •COUT 1– DMAX
where the first term is due to the bulk capacitance and
second term due to the ESR.
∆V
COUT
Boost Converter: Current Limit Programming
V
OUT
(AC)
The LTC3703 provides current limiting in boost mode by
monitoring the VDS of the main switch during its on-time
and comparing it to the voltage at IMAX. To set the current
limit, calculate the expected voltage drop across the
MOSFET at the maximum desired inductor current and
maximum junction temperature. The maximum inductor
current is a function of both duty cycle and maximum load
current,sothelimitmustbesetforthemaximumexpected
duty cycle (minimum VIN) in order to ensure that the
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
∆V
ESR
Figure 15. Output Voltage Ripple
Waveform for a Boost Converter
The choice of output capacitor is driven also by the RMS
ripple current requirement. The RMS ripple current is:
VO – V
IN(MIN)
IRMS(COUT) ≈ IO(MAX)
•
current limit does not kick in at loads < IO(MAX)
:
V
IN(MIN)
At lower output voltages (less than 30V), it may be
possible to satisfy both the output ripple voltage and RMS
ripplecurrentrequirementswithoneormorecapacitorsof
a single capacitor type. However, at output voltages above
30V where capacitors with both low ESR and high bulk
capacitance are hard to find, the best approach is to use a
combination of aluminum and ceramic capacitors (see
IO(MAX)
1– DMAX
VOUT
VPROG
=
=
RDS(ON)(1+ δ)
IO(MAX) •RDS(ON)(1+ δ)
V
IN(MIN)
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Once VPROG is determined, RIMAX is chosen as follows:
Since significant phase shift begins at frequencies above
the dominant LC pole, choose a crossover frequency no
greater than about half this pole frequency. The gain of the
compensation network should equal –GAIN at this fre-
quency so that the overall loop gain is 0dB here. The
compensation component to achieve this, using a Type 1
amplifier (see Figure 12), is:
RIMAX = VPROG/12µA
Note that in a boost mode architecture, it is only possible
to provide protection for “soft” shorts where VOUT > VIN.
For hard shorts, the inductor current is limited only by the
input supply capability. Refer to Current Limit Program-
ming for buck mode for further considerations for current
limit programming.
G = 10–GAIN/20
C1 = 1/(2π • f • G • R1)
Boost Converter: Feedback Loop/Compensation
Run/Soft-Start Function
Compensating a voltage mode boost converter is unfortu-
nately more difficult than for a buck converter. This is due The RUN/SS pin is a multipurpose pin that provide a soft-
to an additional right-half plane (RHP) zero that is present start function and a means to shut down the LTC3703.
in the boost converter but not in a buck. The additional Soft-start reduces the input supply’s surge current by
phase lag resulting from the RHP zero is difficult if not gradually increasing the duty cycle and can also be used
impossible to compensate even with a Type 3 loop, so the for power supply sequencing.
best approach is usually to roll off the loop gain at a lower
Pulling RUN/SS below 1V puts the LTC3703 into a low
frequency than what could be achievable in buck con-
quiescent current shutdown (IQ 50µA). This pin can be
verter.
drivendirectlyfromlogicasshowninFigure17. Releasing
A typical gain/phase plot of a voltage-mode boost con- the RUN/SS pin allows an internal 4µA current source to
verter is shown in Figure 16. The modulator gain and charge up the soft-start capacitor CSS. When the voltage
phase can be measured as described for a buck converter on RUN/SS reaches 1V, the LTC3703 begins operating at
or can be estimated as follows:
its minimum on-time. As the RUN/SS voltage increases
from 1V to 3V, the duty cycle is allowed to increase from
0% to 100%. The duty cycle control minimizes input
supply inrush current and elimates output voltage over-
shootatstart-upandensurescurrentlimitprotectioneven
withahardshort.TheRUN/SSvoltageisinternallyclamped
at 4V.
GAIN (COMP-to-VOUT DC gain) = 20Log(VOUT2/VIN)
V
VOUT
1
IN
Dominant Pole: fP =
•
2π LC
GAIN
(dB)
PHASE
(DEG)
GAIN
RUN/SS
2V/DIV
A
V
0
–12dB/OCT
V
OUT
0
5V/DIV
–90
I
PHASE
L
2A/DIV
–180
3703 F17
V
= 50V
2ms/DIV
IN
I
= 2A
LOAD
C
= 0.01µF
SS
3703 F16
Figure 17. LTC3703 Startup Operation
Figure 16. Transfer Function of Boost Modulator
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IfRUN/SSstartsat0V,thedelaybeforestartingisapproxi-
mately:
output remains heavy. To avoid this, the auxiliary output
voltage can be divided down with a conventional feedback
resistor string with the divided auxiliary output voltage fed
back to the MODE/SYNC pin. The MODE/SYNC threshold
is trimmed to 800mV with 20mV of hysteresis, allowing
precise control of the auxiliary voltage and is set as
follows:
1V
4µA
tDELAY,START
=
CSS = (0.25s /µF)CSS
plus an additional delay, before the output will reach its
regulated value, of:
3V – 1V
4µA
R1
VSEC(MIN) ≈ 0.8V 1+
R2
tDELAY,REG
≥
CSS = (0.5s /µF)CSS
The start delay can be reduced by using diode D1 in
where R1 and R2 are shown in Figure 10c.
Figure 18.
3.3V
If the LTC3703 is operating in Pulse Skip Mode and the
auxiliaryoutputvoltagedropsbelowVSEC(MIN),theMODE/
SYNC pin will trip and the LTC3703 will resume continu-
ous operation regardless of the load on the main output.
Thus, the MODE/SYNC pin removes the requirement that
power must be drawn from the inductor primary in order
to extract power from the auxiliary winding. With the loop
in continuous mode (MODE/SYNC < 0.8V), the auxiliary
outputs may nominally be loaded without regard to the
primary output load.
OR 5V
RUN/SS
RUN/SS
D1
C
SS
C
SS
3703 F18
Figure 18. RUN/SS Pin Interfacing
MODE/SYNC Pin (Operating Mode and Secondary
Winding Control)
TheMODE/SYNCpinisadualfunctionpinthatcanbeused
for enabling or disabling Pulse Skip Mode operation and
also as an external clock input for synchronizing the
internal oscillator (see next section). Pulse Skip Mode is
enabled when the MODE/SYNC pin is above 0.8V and is
disabled, i.e. forced continuous, when the pin is below
0.8V.
The following table summarizes the possible states avail-
able on the MODE/SYNC pin:
Table 1.
MODE/SYNC Pin
Condition
DC Voltage: 0V to 0.75V
Forced Continuous
Current Reversal Enabled
In addition to providing a logic input to force continuous
operation and external synchronization, the MODE/SYNC
pin provides a means to regulate a flyback winding output
as shown in Figure 10c. The auxiliary output is taken from
a second winding on the core of the inductor, converting
it to a transformer. The auxiliary output voltage is set by
the main output voltage and the turns ratio of the extra
winding to the primary winding as follows:
DC Voltage: ≥ 0.87V
Pulse Skip Mode Operation
No Current Reversal
Feedback Resistors
Regulating a Secondary Winding
Ext. Clock: 0V to ≥ 2V
Forced Continuous
No Current Reversal
MODE/SYNC Pin (External Synchronization)
The internal LTC3703 oscillator can be synchronized to an
external oscillator by applying and clocking the MODE/
SYNC pin with a signal above 2VP-P. The internal oscillator
lockstotheexternalclockafterthesecondclocktransition
is received. When external synchronization is detected,
LTC3703 will operate in forced continuous mode. If an
external clock transition is not detected for three succes-
sive periods, the internal oscillator will revert to the
V
SEC ≈ (N + 1)VOUT
Since the secondary winding only draws current when the
synchronous switch is on, load regulation at the auxiliary
output will be relatively good as long as the main output is
running in continuous mode. As the load on the primary
output drops and the LTC3703 switches to Pulse Skip
Mode operation, the auxiliary output may not be able to
maintain regulation, especially if the load on the auxiliary
frequency programmed by the RSET resistor. The internal
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oscillatorcansynchronizetofrequenciesbetween100kHz
and 600kHz, independent of the frequency programmed
by the RSET resistor. However, it is recommended that an
RSET resistor be chosen such that the frequency pro-
grammed by the RSET resistor is close to the expected
frequency of the external clock. In this way, the best
converter operation (ripple, component stress, etc) is
achieved if the external clock signal is lost.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power (x100%). Per-
cent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power. It is often useful to analyze the individual
losses to determine what is limiting the efficiency and
what change would produce the most improvement. Al-
though all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3703 circuits: 1) LTC3703 VCC current, 2)
MOSFET gate current, 3) I2R losses, 4) Topside MOSFET
transition losses.
Minimum On-Time Considerations (Buck Mode)
Minimum on-time tON(MIN) is the smallest amount of time
that the LTC3703 is capable of turning the top MOSFET on
andoffagain.Itisdeterminedbyinternaltimingdelaysand
the amount of gate charge required to turn on the top
MOSFET. Low duty cycle applications may approach this
minimumon-timelimitandcareshouldbetakentoensure
1. VCC Supply current. The VCC current is the DC supply
current given in the Electrical Characteristics table which
powers the internal control circuitry of the LTC3703. Total
supplycurrentistypicallyabout2.5mAandusuallyresults
in a small (<1%) loss which is proportional to VCC.
that:
VOUT
V • f
IN
tON
=
> tON(MIN)
where tON(MIN) is typically 200ns.
Ifthedutycyclefallsbelowwhatcanbeaccommodatedby
the minimum on-time, the LTC3703 will begin to skip
cycles. The output will be regulated, but the ripple current
and ripple voltage will increase. If lower frequency opera-
tion is acceptable, the on-time can be increased above
tON(MIN) for the same step-down ratio.
2. DRVCC current is MOSFET driver current. This current
results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched on and
then off, a packet of gate charge QG moves from DRVCC to
ground. The resulting dQ/dt is a current out of the DRVCC
supply.Incontinuousmode,IDRVCC =f(QG(TOP)+QG(BOT)),
where QG(TOP) and QG(BOT) are the gate charges of the top
and bottom MOSFETs.
Pin Clearance/Creepage Considerations
TheLTC3703isavailableintwopackages(GN16andG28)
both with identical functionality. The GN16 package gives
the smallest size solution, however the 0.013” (minimum)
space between pins may not provide sufficient PC board
trace clearance between high and low voltage pins in
higher voltage applications. Where clearance is an issue,
the G28 package should be used. The G28 package has 4
unconnected pins between the all adjacent high voltage
and low voltage pins, providing 5(0.0106”) = 0.053”
clearance which will be sufficient for most applications up
to 100V. For more information, refer to the printed circuit
board design standards described in IPC-2221
(www.ipc.org).
3. I2R losses are predicted from the DC resistances of
MOSFETs, the inductor and input and output capacitor
ESR. In continuous mode, the average output current
flows through L but is “chopped” between the topside
MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same RDS(ON), then the
resistanceofoneMOSFETcansimplybesummedwiththe
DCR resistance of L to obtain I2R losses. For example, if
each RDS(ON) = 25mΩ and RL = 25mΩ, then total resis-
tance is 50mΩ. This results in losses ranging from 1% to
5% as the output current increases from 1A to 5A for a 5V
output.
4. Transition losses apply only to the topside MOSFET in
buckmodeandtheybecomesignificantwhenoperatingat
3703f
25
LTC3703
U
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APPLICATIO S I FOR ATIO
higher input voltages (typically 20V or greater). Transition
lossescanbeestimatedfromthesecondtermofthePMAIN
equation found in the Power MOSFET Selection section.
Most loads care only about the maximum deviation from
ideal, whichoccurssomewhereinthefirsttwocyclesafter
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirelycontrolledbytheESRofthecapacitorandamounts
to most of the total voltage drop. To minimize this drop,
choose a low ESR capacitor and/or parallel multiple ca-
pacitors at the output. The capacitance value accounts for
the rest of the voltage drop until the inductor current rises.
With most output capacitors, several devices paralleled to
get the ESR down will have so much capacitance that this
drop term is negligible. Ceramic capacitors are an excep-
tion; a small ceramic capacitor can have suitably low ESR
with relatively small values of capacitance, making this
second drop term more significant.
The transition losses can become very significant at the
high end of the LTC3703 operating voltage range. To
improve efficiency, one may consider lowering the fre-
quency and/or using MOSFETs with lower CRSS at the
expense of higher RDS(ON)
.
Other losses including CIN and COUT ESR dissipative
losses, Schottkyconductionlossesduringdead-time, and
inductor core losses generally account for less than 2%
total additional loss.
Transient Response
Due to the high gain error amplifier and line feedforward
compensation of the LTC3703, the output accuracy due to
DC variations in input voltage and output load current will
be almost negligible. For the few cycles following a load
transient, however, the output deviation may be larger
while the feedback loop is responding. Consider a typical
48V input to 5V output application circuit, subjected to a
1A to 5A load transient. Initially, the loop is in regulation
and the DC current in the output capacitor is zero. Sud-
denly, an extra 4A (= 5A-1A) flows out of the output
capacitor while the inductor is still supplying only 1A. This
sudden change will generate a (4A) • (RESR) voltage step
at the output; with a typical 0.015Ω output capacitor ESR,
this is a 60mV step at the output.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on tran-
sient recovery time, the time it takes the LTC3703 to
recover after the output voltage has dropped due to a load
step. Optimizing loop compensation entails maintaining
the highest possible loop bandwidth while ensuring loop
stability. The feedback component selection section de-
scribes in detail the techniques used to design an opti-
mizedType3feedbackloop,appropriateformostLTC3703
systems.
Measurement Techniques
The feedback loop will respond and will move at the band-
width allowed by the external compensation network
towards a new duty cycle. If the unity gain crossover fre-
quencyissetto50kHz, theCOMPpinwillgetto60%ofthe
way to 90% duty cycle in 3µs. Now the inductor is seeing
43V across itself for a large portion of the cycle and its
current will increase from 1A at a rate set by di/dt = V/L. If
theinductorvalueis10µH, thepeakdi/dtwillbe43V/10µH
or 4.3A/µs. Sometime in the next few micro-seconds after
the switch cycle begins, the inductor current will have
risen to the 5A level of the load current and the output
voltage will stop dropping. At this point, the inductor cur-
rent will rise somewhat above the level of the output cur-
rent to replenish the charge lost from the output capacitor
during the load transient. With a properly compensated
loop, the entire recovery time will be inside of 10µs.
Measuring transient response presents a challenge in two
respects: obtaining an accurate measurement and gener-
ating a suitable transient to test the circuit. Output mea-
surements should be taken with a scope probe directly
across the output capacitor. Proper high frequency prob-
ing techniques should be used. In particular, don’t use the
6" ground lead that comes with the probe! Use an adapter
that fits on the tip of the probe and has a short ground clip
toensurethatinductanceinthegroundpathdoesn’tcause
a bigger spike than the transient signal being measured.
Conveniently, the typical probe tip ground clip is spaced
just right to span the leads of a typical output capacitor.
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test and switch it on and off while
3703f
26
LTC3703
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APPLICATIO S I FOR ATIO
watching the output. If this isn’t convenient, a current step
generator is needed. This generator needs to be able to
turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC3703 and the transient generator
must be minimized.
With 10µH inductor, ripple current will vary from 3.2A to
4A (32% to 40%) over the input supply range.
Next, verify that the minimum on-time is not violated. The
minimum on-time occurs at maximum VIN:
VOUT
12
tON(MIN)
=
=
= 667ns
Figure 19 shows an example of a simple transient genera-
tor. Be sure to use a noninductive resistor as the load
element—many power resistors use an inductive spiral
pattern and are not suitable for use here. A simple solution
is to take ten 1/4W film resistors and wire them in parallel
togetthedesiredvalue.Thisgivesanoninductiveresistive
load which can dissipate 2.5W continuously or 50W if
pulsed with a 5% duty cycle, enough for most LTC3703
circuits. SoldertheMOSFETandtheresistor(s)ascloseto
the output of the LTC3703 circuit as possible and set up
thesignalgeneratortopulseata100Hzratewitha5%duty
cycle.ThispulsestheLTC3703with500µstransients10ms
apart, adequate for viewing the entire transient recovery
time for both positive and negative transitions while keep-
ing the load resistor cool.
V
IN(MIN)(f) 72(250kHz)
which is above the LTC3703’s 200ns minimum on-time.
Next, choose the top and bottom MOSFET switch. Since
the drain of each MOSFET will see the full supply voltage
72V(max) plus any ringing, choose a 100V MOSFET to
provide a margin of safety. Si7456DP has a 100V BVDSS
,
RDS(ON) = 25mΩ(max), δ = 0.009/°C, CMILLER = (19nC –
10nC)/50V = 180pF, VGS(MILLER) = 4.7V, θJA = 20°C/W.
Thepowerdissipationcanbeestimatedatmaximuminput
voltage, assuming a junction temperature of 100°C (30°C
above an ambient of 70°C):
12
72
PMAIN
=
(10)2 1+ 0.009(100 – 25) (0.025)
[
]
10
2
1
1
+ (72)2
(2)(180pF)•
+
(250k)
LTC3703
10 – 4.7 4.7
V
OUT
R
LOAD
= 0.70W + 0.94W = 1.64W
IRFZ44 OR
EQUIVALENT
PULSE
GENERATOR
And double check the assumed TJ in the MOSFET:
50Ω
0V TO 10V
100Hz, 5%
DUTY CYCLE
TJ = 70°C + (1.64W)(20°C/W) = 103°C
3703 F19
Since the synchronous MOSFET will be conducting over
twice as long each period (almost 100% of the period in
short circuit) as the top MOSFET, use two Si7456DP
MOSFETs on the bottom:
LOCATE CLOSE TO THE OUTPUT
Figure 19. Transient Load Generator
Design Example
As a design example, take a supply with the following
72 − 12
P
SYNC
=
(10)2 1+ 0.009(100 – 25) •
[
]
specifications: VIN = 36V to 72V (48V nominal), VOUT
=
72
0.025
2
12V ±5%, IOUT(MAX) = 10A, f=250kHz. First, calculate RSET
to give the 250kHz operating frequency:
= 1.74W
RSET = 7100/(250-25) = 31.6k
TJ = 70°C + (1.74W)(20°C/W) = 105°C
Next, choose the inductor value for about 40% ripple
current at maximum VIN:
Next, set the current limit resistor. Since IMAX = 10A, the
limit should be set such that the minimum current limit is
>10A.MinimumcurrentlimitoccursatmaximumRDS(ON)
12V
12
72
.
L =
1–
= 10µH
(250kHz)(0.4)(10A)
3703f
27
LTC3703
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APPLICATIO S I FOR ATIO
Using the above calculation for bottom MOSFET TJ, the
2. The high di/dt loop formed by the top N-channel
MOSFET, the bottom MOSFET and the CIN capacitor
should have short leads and PC trace lengths to minimize
high frequency noise and voltage stress from inductive
ringing.
max RDS(ON) = (25mΩ/2) [1 + 0.009 (105-25)] = 21.5mΩ
Therefore,IMAX pinvoltageshouldbesetto(10A)(0.0215)
= 0.215V. The RSET resistor can now be chosen to be
0.215V/12µA = 18kΩ.
3. Connect the drain of the top side MOSFET directly to the
(+) plate of CIN, and connect the source of the bottom side
MOSFET directly to the (–) terminal of CIN. This capacitor
provides the AC current to the MOSFETs.
CIN is chosen for an RMS current rating of about 5A (IMAX
/
2) at 85°C. For the output capacitor, two low ESR OSCON
capacitors (18mΩ each) are used to minimize output
voltage changes due to inductor current ripple and load
steps. The ripple voltage will be:
4. Place the ceramic CDRVCC decoupling capacitor imme-
diately next to the IC, between DRVCC and BGRTN. This
capacitor carries the MOSFET drivers’ current peaks.
Likewise the CB capacitor should also be next to the IC
between BOOST and SW.
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR) = (4A)(0.018Ω/2)
= 36mV
However, a 0A to 10A load step will cause an output
voltage change of up to:
5. Place the small-signal components away from high
frequency switching nodes (BOOST, SW, TG, and BG). In
the layout shown in Figure 20, all the small signal compo-
nents have been placed on one side of the IC and all of the
power components have been placed on the other. This
also helps keep the signal ground and power ground
isolated.
∆VOUT(STEP) = ∆ILOAD(ESR) = (10A)(0.009Ω)
= 90mV
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3703. These items are also illustrated graphically in
thelayoutdiagramofFigure18.ForlayoutofaBoostMode
Converter, layout is similar with VIN and VOUT swapped.
Check the following in your layout:
6. A separate decoupling capacitor for the supply, VCC, is
useful with an RC filter between the DRVCC supply and VCC
pin to filter any noise injected by the drivers. Connect this
capacitor close to the IC, between the VCC and GND pins
and keep the ground side of the VCC capacitor (signal
ground) isolated from the ground side of the DRVCC
capacitor (power ground).
1. Keepthesignalandpowergroundsseparate. Thesignal
ground consists of the LTC3703 GND pin, the ground
return of CVCC, and the (–) terminal of VOUT. The power
ground consists of the Schottky diode anode, the source
of the bottom side MOSFET, and the (–) terminal of the
input capacitor and DRVCC capacitor. Connect the signal
and power grounds together at the (–) terminal of the
output capacitor. Also, try to connect the (–) terminal of
the output capacitor as close as possible to the (–)
terminals of the input and DRVCC capacitor and away from
the Schottky loop described in (2).
7. For optimum load regulation and true remote sensing,
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC3703 in order to
keep the high impedance FB node short.
3703f
28
LTC3703
U
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APPLICATIO S I FOR ATIO
8. Forapplicationswithmultipleswitchingpowerconvert-
ersconnectedtothesameinputsupply,makesurethatthe
input filter capacitor for the LTC3703 is not shared with
other converters. AC input current from another converter
couldcausesubstantialinputvoltageripple,andthiscould
interfere with the operation of the LTC3703. A few inches
of PC trace or wire (L 100nH) between CIN of the
LTC3703 and the actual source VIN should be sufficient to
prevent input noise interference problems.
V
CC
V
IN
D
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE/SYNC
V
IN
R
SET
M1
FSET
LTC3703
COMP
BOOST
TG
+
R
C1
C
IN
C
B
C
C2
C
C1
FB
SW
L1
R
MAX
+
I
V
R2
MAX
CC
R
F
+
INV
DRV
CC
V
OUT
C
OUT
C
SS
D1
C
RUN/SS
GND
BG
DRVCC
M2
X5R
R
C2
BGRTN
–
R1
C
VCC
C
C3
X5R
3703 F18
Figure 20. LTC3703 Buck Converter Suggested Layout
3703f
29
LTC3703
U
TYPICAL APPLICATIO S
36V-72V Input Voltage to 5V/10A Step-Down Converter with Pulse Skip Mode Enabled
V
CC
9.3V TO 15V
+
V
22µF
25V
IN
D
B
36V TO 72V
BAS21
1
2
3
4
5
6
7
8
16
15
14
13
12
MODE/SYNC
V
IN
C
IN
R
SET
+
22µF
100V
×2
25k
FSET
LTC3703
COMP
BOOST
TG
R
C1
M1
Si7456DP
120k
C
B
C
C
C1
C2
100pF
0.1µF
L1
4.7µH
8pF
FB
SW
V
OUT
R
20k
5V
MAX
10A
I
V
CC
C
MAX
OUT
+
220µF
25V
×2
11
10
9
R
F
R2
8.06k
1%
INV
DRV
CC
10Ω
M2
Si7456DP
C
SS
0.1µF
RUN/SS
GND
BG
D1
MBR1100
C
DRVCC
10µF
R
C2
R1
42k
1%
3.2k
C
BGRTN
C
C3
VCC
1µF
260pF
3703 TA01
Single Input Supply 12V/5A Output Step-Down Converter
100Ω
*
10k
V
IN
FZT600
15V TO 80V
12V
+
22µF
25V
D
B
BAS21
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE/SYNC
V
IN
C
IN
+
22µF
100V
×2
CMDSH-3
R
25k
20k
SET
FSET
BOOST
TG
R
C1
M1
Si7456DP
LTC3703
22k
COMP
FB
C
B
C
15pF
C
C1
C2
0.1µF
L1
15µH
3300pF
SW
V
OUT
R
12V
5A
MAX
I
V
CC
C
MAX
OUT
+
220µF
25V
×2
R
F
R2
8.06k
1%
INV
DRV
CC
10Ω
M2
Si7456DP
C
SS
0.1µF
RUN/SS
GND
BG
D1
MBR1100
C
DRVCC
10µF
R
C2
330Ω
R1
113k
1%
BGRTN
C
C
C3
VCC
1µF
1500pF
3703 TA02
*OPTIONAL ZENER PROVIDES UNDERVOLTAGE LOCKOUT ON INPUT SUPPLY, V
UVLO
10 + V
Z
3703f
30
LTC3703
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
NOTE:
1. CONTROLLING DIMENSION: INCHES
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN16 (SSOP) 0502
3. DRAWING NOT TO SCALE
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
5
7
8
1
2
3
4
6
9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
5.00 – 5.60**
(.197 – .221)
2.0
(.079)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
0.55 – 0.95
(.0035 – .010)
(.022 – .037)
0.05
0.22 – 0.38
(.009 – .015)
(.002)
G28 SSOP 0802
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3. DRAWING NOT TO SCALE
3703f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
31
LTC3703
U
TYPICAL APPLICATIO
5V to 12V/5A Synchronous Boost Converter
V
CC
9.3V TO 15V
+
D
22µF
25V
B
V
12V
5A
OUT
CMDSH-3
1
16
C
+
OUT
MODE/SYNC
V
IN
220µF
16V
×2
R
25k
SET
2
3
4
5
6
7
8
15
14
13
12
11
10
9
FSET
BOOST
TG
M1
LTC3703
Si7348DP
MBRS140T3
COMP
FB
C
B
C
C1
0.1µF
L1
3.3µH
0.1µF
SW
V
IN
R
13k
MAX
3V TO 11V
I
V
MAX
CC
CC
+
C
IN
100µF
R
F
R1
113k
1%
R2
8.06k
1%
INV
DRV
16V
10Ω
M2
Si7366DP
C
SS
0.1µF
RUN/SS
GND
BG
C
DRVCC
10µF
BGRTN
C
VCC
3703 TA03
1µF
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3703f
LT/TP 1203 1K • PRINTED IN USA
32 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2003
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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