LTC3707IGN-SYNC#TRPBF

LTC3707

High Efﬁciency, 2-Phase

Synchronous Step-Down

Switching Regulator

DESCRIPTION

FEATURES

The LTC^®3707 is a high performance dual step-down

switching regulator controller that drives N-channel

synchronouspowerMOSFETstages.Aconstantfrequency

current mode architecture allows adjustment of the

frequency up to 300kHz. Power loss and noise due to the

ESR of the input capacitors are minimized by operating

the two controller output stages out of phase.

■

180° Phased Dual Controllers Reduce Required

Input Capacitance and Power Supply Induced Noise

OPTI-LOOP^®Compensation Minimizes C

■

OUT

■

1.5% Output Voltage Accuracy over Temperature

■

Dual N-Channel MOSFET Synchronous Drive

■

Power Good Output Voltage Monitor

■

DC Programmed Fixed Frequency 150kHz to 300kHz

■

Wide V Range: 4.5V to 28V Operation

IN

OPTI-LOOPcompensationallowsthetransientresponseto

be optimized over a wide range of output capacitance and

ESR values. The precision 0.8V reference and power good

outputindicatorarecompatiblewithfuturemicroprocessor

generations, and a wide 3.5V to 30V input supply range

encompasses all battery chemistries.

■

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Soft-Start Current Ramping

Foldback Output Current Limiting

Latched Short-Circuit Shutdown with Defeat Option

Output Overvoltage Protection

Remote Output Voltage Sense

A RUN/SS pin for each controller provides both soft-start

and optional timed, short-circuit shutdown. Current

foldback limits MOSFET dissipation during short-circuit

conditions when overcurrent latchoff is disabled. Output

overvoltage protection circuitry latches on the bottom

Low Shutdown I : 20μA

Q

5V and 3.3V Standby Regulators

Selectable Constant Frequency, Burst Mode^®

Operation or PWM Operation

■

Small 28-Lead Narrow SSOP Package

MOSFET until V

returns to normal. The FCB mode

OUT

APPLICATIONS

pin can select among Burst Mode operation, constant

frequency mode and continuous inductor current mode

or regulate a secondary winding.

■

Notebook and Palmtop Computers, PDAs

■

Battery Chargers

■

Portable Instruments

L, LT, LTC, LTM, Burst Mode, and OPTI-LOOP are registered trademarks of Linear Technology

Corporation. All other trademarks are the property of their respective owners. Protected by U.S.

Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6304066, 6580258.

■

Battery-Operated Digital Devices

■

DC Power Distribution Systems

V

IN

5.2V TO 28V

C

22μF

50V

TYPICAL APPLICATION

IN

+

1μF

4.7μF

D3

CERAMIC

D4

V

INTV

IN

CC

CERAMIC

M1

M2

M3

M4

TG1

TG2

L1

6.3μH

L2

6.3μH

C

, 0.1μF

C

, 0.1μF

B2

B1

BOOST1

SW1

BOOST2

SW2

LTC3707

BG1

BG2

D1

D2

SGND

SENSE1

PGND

+

SENSE2

R

SENSE1

SENSE2

0.01Ω

1000pF

0.01Ω

–

SENSE1

SENSE2

V

3.3V

5A

OUT1

5V

5A

OUT2

V

OSENSE2

OSENSE1

R2

105k

1%

R4

63.4k

1%

I

TH1

TH2

C

C2

C

C1

220pF

C

56μF

6V

OUT1

OUT

RUN/SS1

RUN/SS2

+

R1

20k

1%

R3

20k

1%

220pF

R

C2

47μF

6V

R

C1

C

SS2

0.1μF

SS1

0.1μF

15k

SP

M1, M2, M3, M4: FDS6680A

3707 F01

Figure 1. High Efﬁciency Dual 5V/3.3V Step-Down Converter

3707fb

1

LTC3707

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

Input Supply Voltage (V ).........................30V to –0.3V

IN

1

2

PGOOD

TG1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS1

Top Side Driver Voltages

+

SENSE1

(BOOST1, BOOST2) ................................... 36V to –0.3V

Switch Voltage (SW1, SW2) ......................... 30V to –5V

–

3

SW1

SENSE1

4

BOOST1

V

OSENSE1

INTV EXTV , RUN/SS1, RUN/SS2, (BOOST1-SW1),

CC,

CC

5

V

FREQSET

STBYMD

FCB

IN

(BOOST2-SW2), PGOOD.............................. 7V to –0.3V

6

BG1

+

–

+

–

SENSE1 , SENSE2 , SENSE1 ,

7

EXTV

CC

SENSE2 Voltages .........................(1.1)INTV to –0.3V

8

INTV

CC

I

TH1

FREQSET, STBYMD, FCB Voltage ......... INTV to –0.3V

9

PGND

BG2

SGND

I

, V

Voltages ... 2.7V to –0.3V

10

11

12

13

14

3.3V

OUT

TH1, TH2 OSENSE1 OSENSE2

BOOST2

SW2

I

Peak Output Current <10μs (TG1, TG2, BG1, BG2).....3A

TH2

V

INTV Peak Output Current ................................. 40mA

OSENSE2

–

CC

TG2

SENSE2

Operating Temperature Range (Note 2).... –40°C to 85°C

Junction Temperature (Note 3) ............................. 125°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

+

RUN/SS2

GN PACKAGE

28-LEAD PLASTIC SSOP

= 125°C, θ = 95°C/W

T

JMAX

JA

ORDER INFORMATION

LEAD FREE FINISH

LTC3707EGN#PBF

LTC3707IGN#PBF

LEAD BASED FINISH

LTC3707EGN

TAPE AND REEL

PART MARKING

3707EGN

PACKAGE DESCRIPTION

28-Lead Plastic SSOP

PACKAGE DESCRIPTION

28-Lead Plastic SSOP

TEMPERATURE RANGE

–40°C to 85°C

LTC3707EGN#TRPBF

LTC3707IGN#TRPBF

TAPE AND REEL

3707IGN

–40°C to 85°C

PART MARKING

3707EGN

TEMPERATURE RANGE

–40°C to 85°C

LTC3707EGN#TR

LTC3707IGN#TR

LTC3707IGN

3707IGN

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

The l denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 15V, V_{RUN/SS1, 2}= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

l

V

Regulated Feedback Voltage

Feedback Current

(Note 4); I

Voltage = 1.2V

TH1, 2

0.788

0.800 0.812

V

nA

OSENSE1, 2

I

(Note 4)

–5

–50

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

= 3.6V to 30V (Note 4)

0.002

0.02

%/V

REFLNREG

IN

(Note 4)

Measured in Servo Loop; ΔI Voltage = 1.2V to 0.7V

Measured in Servo Loop; ΔI Voltage = 1.2V to 2.0V

LOADREG

l

0.1

–0.1

0.5

–0.5

%

TH

g

Transconductance Ampliﬁer g

I = 1.2V; Sink/Source 5μA; (Note 4)

TH1, 2

1.3

mmho

m1,2

m

3707fb

2

LTC3707

The l denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 15V, V_{RUN/SS1, 2}= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

= 1.2V; (Note 4)

MIN

TYP

MAX UNITS

g

Transconductance Ampliﬁer GBW

I

3

MHz

mGBW1, 2

TH1, 2

I

Q

Input DC Supply Current

Normal Mode

Standby

(Note 5)

EXTV Tied to V

= 5V

350

125

20

μA

CC

OUT1

= 0V, V

V

> 2V

RUN/SS1, 2

RUN.SS1, 2

STBYMD

Shutdown

= Open

35

l

V

Forced Continuous Threshold

Forced Continuous Pin Current

0.76

0.800

–0.18

4.3

0.84

–0.1

4.8

V

FCB

I

V

= 0.85V

–0.30

μA

V

FCB

V

Burst Inhibit (Constant Frequency)

Threshold

Measured at FCB pin

BINHIBIT

l

UVLO

Undervoltage Lockout

Feedback Overvoltage Lockout

Sense Pins Total Source Current

Master Shutdown Threshold

Keep-Alive Power On-Threshold

Maximum Duty Factor

V

Ramping Down

3.5

0.86

–60

0.6

4

V

IN

V

OVL

Measured at V

0.84

–90

0.4

0.88

OSENSE1, 2

I

(Each Channel); V

–

– = V

+

+ = 0V

μA

V

SENSE

SENSE1 , 2

V

Ramping Down

STBYMD MS

STBYMD

KA

Ramping Up, RUN

= 0V

1.5

2

V

STBYMD

SS1, 2

DF

In Dropout

98

0.5

1.0

99.4

1.2

%

μA

V

MAX

I

Soft-Start Charge Current

V

= 1.9V

RUN/SS1, 2

V

ON RUN/SS Pin ON Threshold

V Rising

RUN/SS1, RUN/SS2,

1.5

2.0

RUN/SS1, 2

V

LT RUN/SS Pin Latchoff Arming

Threshold

V

Rising from 3V

4.1

4.75

V

RUN/SS1, RUN/SS2,

I

RUN/SS Discharge Current

Soft Short Condition V

= 0.5V;

0.5

2

4

5

μA

SCL1, 2

OSENSE1, 2

V

= 4.5V

RUN/SS1, 2

OSENSE1, 2

Shutdown Latch Disable Current

= 0.5V

1.6

SDLHO

V

Maximum Current Sense Threshold

= 0.7V, V

– – = 5V

OSENSE1 , 2

65

62

75

85

88

mV

SENSE(MAX)

l

TG Transition Time:

Rise Time

Fall Time

(Note 6)

TG1, 2 t

C

= 3300pF

60

110

ns

r

f

LOAD

= 3300pF

BG Transition Time:

Rise Time

Fall Time

(Note 6)

LOAD

BG1, 2 t

C

= 3300pF

50

110

100

ns

r

f

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

1D

C

= 3300pF Each Driver

80

ns

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

2D

= 3300pF Each Driver

80

ns

LOAD

t

Minimum On-Time

Tested with a Square Wave (Note 7)

180

ON(MIN)

INTV Linear Regulator

CC

V

Internal V Voltage

6V < V < 30V, V = 4V

EXTCC

4.8

4.5

5.0

0.2

100

4.7

0.2

5.2

2.0

200

V

%

INTVCC

CC

IN

INT

INTV Load Regulation

I

CC

I

CC

I

CC

= 0 to 20mA, V

= 4V

EXTVCC

LDO

CC

EXT

EXTV Voltage Drop

= 20mA, V

= 5V

EXTVCC

mV

V

CC

l

EXTV Switchover Voltage

= 20mA, EXTV Ramping Positive

CC

EXTVCC

LDOHYS

CC

EXTV Hysteresis

V

CC

Oscillator

f

Oscillator Frequency

Lowest Frequency

V

= Open (Note 8)

= 0V

190

120

220

140

250

160

kHz

OSC

FREQSET

f

LOW

FREQSET

3707fb

3

LTC3707

The l denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 15V, V_{RUN/SS1, 2}= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

310

–2

MAX UNITS

f

Highest Frequency

FREQSET Input Current

V

= 2.4V

= 0V

280

360

–1

kHz

μA

HIGH

FREQSET

I

V

FREQSET

3.3V Linear Regulator

l

V

3.3V Regulator Output Voltage

3.3V Regulator Load Regulation

3.3V Regulator Line Regulation

No Load

= 0 to 10mA

3.20

3.35

0.5

3.45

2

V

%

3.3OUT

3.3IL

I

3.3

6V < V < 30V

0.05

0.2

3.3VL

IN

PGOOD Output

V

PGOOD Voltage Low

I

= 2mA

= 5V

0.1

0.3

1

V

PGL

PGOOD

I

PGOOD Leakage Current

PGOOD Trip Level, Either Controller

V

μA

PGOOD

V

Respect to Set Output Voltage

PG

OSENSE

V

Ramping Negative

Ramping Positive

–6

6

–7.5

7.5

–9.5

9.5

%

OSENSE

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: The LTC3707 is tested in a feedback loop that servos V

to a

ITH1, 2

speciﬁed voltage and measures the resultant V

OSENSE1, 2.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 2: The LTC3707E is guaranteed to meet performance speciﬁcations

from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC3707I is guaranteed to meet

performance speciﬁcations over the full –40°C to 85°C operating

temperature range.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: The IC minimum on-time is tested under an ideal condition

without external power FETs. It can be different when the IC is working in

an actual circuit. See Minimum On-Time Considerations in the Application

Information section.

Note 3: T is calculated from the ambient temperature T and power

J

A

Note 8: V

pin internally tied to a 1.19V reference through a

FREQSET

dissipation P according to the following formula:

D

large resistance.

LTC3707EGN = T = T + (P • 85°C/W)

J

A

D

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁciency vs Output Current

(Figure 13)

Efﬁciency vs Input Voltage

Efﬁciency vs Output Current

and Mode (Figure 13)

(Figure 13)

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

100

Burst Mode

OPERATION

V

= 15V

OUT

IN

V

= 7V

IN

= 5V

90

80

70

60

V

= 10V

IN

FORCED

CONTINUOUS

MODE (PWM)

V

= 15V

IN

V

IN

= 20V

CONSTANT

FREQUENCY

(BURST DISABLE)

V

= 5V

= 3A

OUT

V

= 15V

IN

OUT

I

= 5V

50

0.01

0.1

1

5

15

25

30

0.001

0.1

1

10

0.001

0.01

OUTPUT CURRENT (A)

INPUT VOLTAGE (V)

3707 G02

3707 G03

3707 G01

3707fb

4

LTC3707

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current vs Input Voltage

and Mode (Figure 13)

INTV_CCand EXTV_CCSwitch

Voltage vs Temperature

EXTV_CCVoltage Drop

1000

800

600

400

200

0

200

150

100

50

5.05

5.00

4.95

4.90

4.85

4.80

4.75

4.70

INTV VOLTAGE

CC

BOTH

CONTROLLERS ON

EXTV SWITCHOVER THRESHOLD

CC

STANDBY

SHUTDOWN

10

0

15

20

25

0

10

20

30

40

–50 –25

0

25

50

TEMPERATURE (°C)

75

100 125

0

5

30

INPUT VOLTAGE (V)

CURRENT (mA)

3707 G05

3707 G06

3707 G04

Maximum Current Sense

Threshold vs Percent of Nominal

Output Voltage (Foldback)

Maximum Current Sense

Threshold vs Duty Factor

Internal 5V LDO Line Reg

75

50

25

0

5.1

5.0

80

70

60

50

40

30

20

10

0

I

= 1mA

LOAD

4.9

4.8

4.7

4.6

4.5

4.4

20

INPUT VOLTAGE (V)

30

0

20

40

60

80

100

50

0

5

10

15

25

0

25

75

100

DUTY FACTOR (%)

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

3707 G08

3707 G07

3707 G09

Maximum Current Sense

Threshold vs V_RUN/SS(Soft-Start)

Maximum Current Sense Threshold

vs Sense Common Mode Voltage

Current Sense Threshold

vs I_THVoltage

80

76

72

68

64

60

80

60

40

20

90

80

V

= 1.6V

SENSE(CM)

70

60

50

40

30

20

10

0

–10

–20

–30

0

1

2

3

4

5

6

0

1

2

3

4

5

0

0.5

1

1.5

(V)

2

2.5

V

(V)

COMMON MODE VOLTAGE (V)

RUN/SS

V

ITH

3707 G10

3707 G11

3707 G12

3707fb

5

LTC3707

TYPICAL PERFORMANCE CHARACTERISTICS

Load Regulation

V_ITHVS V_RUN/SS

SENSE Pins Total Source Current

2.5

2.0

1.5

1.0

0.0

–0.1

–0.2

–0.3

–0.4

100

50

V

= 0.7V

FCB = 0V

= 15V

OSENSE

V

IN

FIGURE 1

0

–50

–100

0.5

0

2

3

4

5

6

0

1

2

3

4

5

1

2

4

0

6

V

(V)

LOAD CURRENT (A)

RUN/SS

V

COMMON MODE VOLTAGE (V)

SENSE

3707 G14

3707 G13

3707 G15

Maximum Current Sense

Threshold vs Temperature

Dropout Voltage vs Output Current

(Figure 13)

RUN/SS Current vs Temperature

80

78

76

74

72

70

4

3

2

1

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

V

= 5V

OUT

R

= 0.015Ω

SENSE

R

= 0.010Ω

SENSE

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

OUTPUT CURRENT (A)

–50 –25

0

25

50

75 100 125

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

3707 G18

3707 G17

3707 G25

Soft-Start Up (Figure 13)

Load Step (Figure 13)

V

OUT

200mV/DIV

V

OUT

200mV/DIV

5V/DIV

V

RUN/SS

5V/DIV

I

OUT

2A/DIV

OUT

2A/DIV

I

OUT

2A/DIV

3707 G20

3707 G21

3707 G19

20μs/DIV

V

= 15V

= 5V

V

= 15V

= 5V

OUT

5ms/DIV

V

= 15V

= 5V

IN

OUT

IN

OUT

LOAD STEP = 0A TO 3A

Burst Mode OPERATION

LOAD STEP = 0A TO 3A

CONTINUOUS OPERATION

3707fb

6

LTC3707

TYPICAL PERFORMANCE CHARACTERISTICS

Constant Frequency (Burst Inhibit)

Operation (Figure 13)

Input Source/Capacitor

Instantaneous Current (Figure 13)

Burst Mode Operation (Figure 13)

I

IN

V

OUT

2A/DIV

V

OUT

20mV/DIV

V

IN

200mV/DIV

V

SW1

10V/DIV

I

V

I

OUT

SW2

OUT

0.5A/DIV

10V/DIV

0.5A/DIV

3707 G24

3707 G23

3707 G22

2μs/DIV

10μs/DIV

1μs/DIV

V

I

= 15V

= 5V

V

I

= 15V

= 5V

V

I

= 15V

= 5V

OUT5 OUT3.3

IN

OUT

FCB

IN

OUT

FCB

IN

OUT

= 5V

= OPEN

= 20mA

= I

= 2A

= 20mA

OUT

Oscillator Frequency

vs Temperature

Current Sense Pin Input Current

vs Temperature

EXTV_CCSwitch Resistance

vs Temperature

10

8

350

300

35

33

31

29

27

25

V

= 5V

V

= 5V

OUT

FREQSET

250

200

150

100

50

V

= OPEN

= 0V

FREQSET

V

6

FREQSET

4

2

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

75

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

3707 G28

3707 G27

3707 G26

Undervoltage Lockout

vs Temperature

Shutdown Latch Thresholds

vs Temperature

3.50

3.45

3.40

3.35

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

LATCH ARMING

LATCHOFF

THRESHOLD

3.30

3.25

3.20

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

3707 G29

3707 G30

3707fb

7

LTC3707

PIN FUNCTIONS

RUN/SS1,RUN/SS2(Pins1,15):Combinationofsoft-start,

run control inputs and short-circuit detection timers. A

capacitor to ground at each of these pins sets the ramp

time to full output current. Forcing either of these pins

back below 1.0V causes the IC to shut down the circuitry

requiredforthatparticularcontroller. Latchoffovercurrent

protection is also invoked via this pin as described in the

Applications Information section.

3.3V

(Pin 10): Output of a linear regulator capable

OUT

of supplying 10mA DC with peak currents as high as

50mA.

PGND (Pin 20): Driver Power Ground. Connects to the

sources of bottom (synchronous) N-channel MOSFETs,

anodes of the Schottky rectiﬁers and the (–) terminal(s)

of C .

IN

INTV (Pin 21): Output of the Internal 5V Linear Low

CC

+

SENSE1 , SENSE2 (Pins 2, 14): The (+) Input to the

Differential Current Comparators. The I pin voltage and

Dropout Regulator and the EXTV Switch. The driver and

CC

TH

controlcircuitsarepoweredfromthisvoltagesource.Must

–

+

controlledoffsetsbetweentheSENSE andSENSE pinsin

conjunction with R

be decoupled to power ground with a minimum of 4.7μF

set the current trip threshold.

SENSE

tantalum or other low ESR capacitor. The INTV regulator

CC

–

SENSE1 , SENSE2 (Pins 3, 13): The (–) Input to the

standby function is determined by the STBYMD pin.

Differential Current Comparators.

EXTV (Pin22):ExternalPowerInputtoanInternalSwitch

CC

V

, V

(Pins 4, 12): Receives the remotely-

Connected to INTV . This switch closes and supplies V

OSENSE1 OSENSE2

sensedfeedbackvoltageforeachcontrollerfromanexternal

CC CC

power,bypassingtheinternallowdropoutregulator,when-

resistive divider across the output.

ever EXTV is higher than 4.7V. See EXTV connection

CC

in Applications section. Do not exceed 7V on this pin.

FREQSET(Pin5):FrequencyControlInputtotheOscillator.

This pin can be left open, tied to ground, tied to INTV

or driven by an external voltage source. This pin can also

be used with an external phase detector to build a true

phase-locked loop.

BG1, BG2 (Pins 23, 19): High Current Gate Drives for Bot-

CC

tom (Synchronous) N-Channel MOSFETs. Voltage swing

at these pins is from ground to INTV .

CC

V (Pin 24): Main Supply Pin. A bypass capacitor should

IN

STBYMD (Pin 6): Control pin that determines which cir-

cuitry remains active when the controllers are shut down

and/orprovidesacommoncontrolpointtoshutdownboth

controllers. See the Operation section for details.

be tied between this pin and the signal ground pin.

BOOST1, BOOST2 (Pins 25, 18): Bootstrapped Supplies

to the Top Side Floating Drivers. Capacitors are connected

betweentheboostandswitchpinsandSchottkydiodesare

tied between the boost and INTV pins. Voltage swing at

the boost pins is from INTV to (V + INTV ).

FCB(Pin7):ForcedContinuousControl Input. Thisinput

actsonbothcontrollersandisnormallyusedtoregulatea

secondary winding. Pulling this pin below 0.8V will force

continuous synchronous operation on both controllers.

Do not leave this pin ﬂoating.

CC

IN

CC

SW1, SW2 (Pins 26, 17): Switch Node Connections to

Inductors. Voltage swing at these pins is from a Schottky

diode (external) voltage drop below ground to V .

IN

I

(Pins8,11):ErrorAmpliﬁerOutputandSwitching

TH1, TH2

TG1, TG2 (Pins 27, 16): High Current Gate Drives for

RegulatorCompensationPoint.Eachassociatedchannels’

current comparator trip point increases with this control

voltage.

Top N-Channel MOSFETs. These are the outputs of ﬂoat-

ing drivers with a voltage swing equal to INTV – 0.5V

CC

superimposed on the switch node voltage SW.

SGND (Pin 9): Small Signal Ground common to both

controllers, must be routed separately from high current

grounds to the common (–) terminals of the C

capacitors.

PGOOD (Pin 28): Open-Drain Logic Output. PGOOD is

pulled to ground when the voltage on either V

is not within 7.5% of its set point.

OSENSE

OUT

3707fb

8

LTC3707

FUNCTIONAL DIAGRAM

INTV

V

IN

CC

D

C

DUPLICATE FOR SECOND

CONTROLLER CHANNEL

B

1.19V

1M

BOOST

TG

FREQSET

PGOOD

B

DROP

OUT

DET

+

CLK1

CLK2

TOP

BOT

C

IN

D

1

OSCILLATOR

BOT

FCB

SW

TOP ON

S

R

Q

SWITCH

LOGIC

INTV

CC

–

+

0.86V

BG

V

OUT

FB

PGND

–

+

B

+

–

0.55V

V

OUT

0.74V

BINH

SHDN

R

SENSE

V

SEC

3V

–

+

4.5V

0.8V

0.18μA

FCB

INTV

CC

I1

I2

R6

+

–

+

–

+ +

–

+

–

+

–

SENSE

FCB

D

SEC

C

SEC

30k

R5

3mV

0.86V

4(V

–

)

FB

3.3V

OUT

+

–

V

REF

SLOPE

COMP

45k

2.4V

V

OSENSE

R2

V

FB

V

IN

–

+

EA

0.80V

0.86V

R1

+

–

4.8V

OV

5V

LDO

REG

+

–

EXTV

CC

C

I

TH

1.2μA

INTV

CC

5V

SHDN

RST

+

RUN

SOFT-

START

R

C

C2

INTERNAL

SUPPLY

SGND

6V

4(V

FB

)

RUN/SS

STBYMD

C

SS

3707 FD/F02

Figure 2

3707fb

9

LTC3707

OPERATION

Main Control Loop

(Refer to Functional Diagram)

secondary winding by temporarily forcing continuous

PWM operation on both controllers and 2) a logic input

to select between two modes of low current operation.

When the FCB pin voltage is below 0.800V, the controller

forces continuous PWM current mode operation. In

this mode, the top and bottom MOSFETs are alternately

turned on to maintain the output voltage independent

of direction of inductor current. When the FCB pin is

The LTC3707 uses a constant frequency, current mode

step-down architecture with the two controller channels

operating 180 degrees out of phase. During normal

operation, each top MOSFET is turned on when the clock

for that channel sets the RS latch, and turned off when

the main current comparator, I , resets the RS latch.

1

The peak inductor current at which I resets the RS

1

below V

– 2V but greater than 0.80V, the controller

INTVCC

latch is controlled by the voltage on the I pin, which

TH

enters Burst Mode operation. Burst Mode operation sets

a minimum output current level before inhibiting the top

switch and turns off the synchronous MOSFET(s) when

the inductor current goes negative. This combination of

is the output of each error ampliﬁer EA. The V

OSENSE

receives the voltage feedback signal, which is compared

to the internal reference voltage by the EA. When the load

current increases, it causes a slight decrease in V

OSENSE

requirementswill, atlowcurrents, forcetheI pinbelow

TH

relative to the 0.8V reference, which in turn causes the

avoltagethresholdthatwilltemporarilyinhibitturn-onof

bothoutputMOSFETsuntiltheoutputvoltagedrops.There

is 60mV of hysteresis in the burst comparator B tied to

I

voltage to increase until the average inductor current

TH

matches the new load current. After the top MOSFET has

turnedoff, thebottomMOSFETisturnedonuntileitherthe

inductor current starts to reverse, as indicated by current

theI pin.Thishysteresisproducesoutputsignalstothe

TH

MOSFETs that turn them on for several cycles, followed

by a variable “sleep” interval depending upon the load

current. The resultant output voltage ripple is held to a

very small value by having the hysteretic comparator

after the error ampliﬁer gain block.

comparator I , or the beginning of the next cycle.

2

ThetopMOSFETdriversarebiasedfromﬂoatingbootstrap

capacitor C , which normally is recharged during each off

B

cycle through an external diode when the top MOSFET

turns off. As V decreases to a voltage close to V

,

IN

OUT

the loop may enter dropout and attempt to turn on the

top MOSFET continuously. The dropout detector detects

this and forces the top MOSFET off for about 500ns every

Constant Frequency Operation

When the FCB pin is tied to INTV , Burst Mode operation

CC

is disabled and the forced minimum output current

requirementisremoved.Thisprovidesconstantfrequency,

discontinuous (preventing reverse inductor current)

current operation over the widest possible output current

range.Thisconstantfrequencyoperationisnotasefﬁcient

as Burst Mode operation, but does provide a lower noise,

constantfrequencyoperatingmodedowntoapproximately

1% of designed maximum output current. Voltage should

not be applied to the FCB pin prior to the application of

tenth cycle to allow C to recharge.

B

The main control loop is shut down by pulling the RUN/

SS pin low. Releasing RUN/SS allows an internal 1.2μA

current source to charge soft-start capacitor C . When

SS

C

TH

reaches1.5V, themaincontrolloopisenabledwiththe

SS

I

voltageclampedatapproximately30%ofitsmaximum

value. As C continues to charge, the I pin voltage is

SS

TH

graduallyreleasedallowingnormal,full-currentoperation.

When both RUN/SS1 and RUN/SS2 are low, all LTC3707

controller functions are shut down, and the STBYMD pin

determines if the standby 5V and 3.3V regulators are

kept alive.

voltage to the V pin.

IN

Continuous Current (PWM) Operation

Tying the FCB pin to ground will force continuous current

operation. This is the least efﬁcient operating mode,

but may be desirable in certain applications. The output

can source or sink current in this mode. When sinking

current while in forced continuous operation, current will

Low Current Operation

The FCB pin is a multifunction pin providing two

functions: 1) an analog input to provide regulation for a

3707fb

10

LTC3707

OPERATION

be forced back into the main power supply potentially

boosting the input supply to dangerous voltage levels—

BEWARE!

(Refer to Functional Diagram)

Output Overvoltage Protection

An overvoltage comparator, 0V, guards against transient

overshoots (>7.5%) as well as other more serious condi-

tions that may overvoltage the output. In this case, the top

MOSFET is turned off and the bottom MOSFET is turned

on until the overvoltage condition is cleared.

Frequency Setting

The FREQSET pin provides frequency adjustment of the

internal oscillator from approximately 140kHz to 310kHz.

This input is nominally biased through an internal resistor

to the 1.19V reference, setting the oscillator frequency to

approximately 220kHz. This pin can be driven from an ex-

ternal AC or DC signal source to control the instantaneous

frequency of the oscillator. Voltage should not be applied

to the FREQSET pin prior to the application of voltage to

Power Good (PGOOD) Pin

The PGOOD pin is connected to an open drain of an in-

ternal MOSFET. The MOSFET turns on and pulls the pin

low when both the outputs are not within 7.5% of their

nominal output levels as determined by their resistive

feedback dividers. When both outputs meet the 7.5%

requirement, the MOSFET is turned off within 10μs and

the pin is allowed to be pulled up by an external resistor

to a source of up to 7V.

the V pin.

IN

INTV /EXTV Power

CC

Power for the top and bottom MOSFET drivers and most

otherinternalcircuitryisderivedfromtheINTV pin.When

Foldback Current, Short-Circuit Detection

and Short-Circuit Latchoff

CC

the EXTV pin is left open, an internal 5V low dropout

CC

linear regulator supplies INTV power. If EXTV is taken

CC

TheRUN/SScapacitorsareusedinitiallytolimittheinrush

current of each switching regulator. After the controller

has been started and been given adequate time to charge

up the output capacitors and provide full load current, the

RUN/SScapacitorisusedinashort-circuittime-outcircuit.

If the output voltage falls to less than 70% of its nominal

output voltage, the RUN/SS capacitor begins discharging

on the assumption that the output is in an overcurrent

and/or short-circuit condition. If the condition lasts for

a long enough period as determined by the size of the

RUN/SS capacitor, the controllers will be shut down until

the RUN/SS pin(s) voltage(s) are recycled. This built-in

latchoff can be overridden by providing a >5μA pull-up at

a compliance of 4.2V to the RUN/SS pin(s). This current

shortens the soft start period but also prevents net dis-

charge of the RUN/SS capacitor(s) during an overcurrent

and/or short-circuit condition. Foldback current limiting

is also activated when the output voltage falls below

70% of its nominal level whether or not the short-circuit

latchoff circuit is enabled. Even if a short is present and

the short-circuit latchoff is not enabled, a safe, low output

current is provided due to internal current foldback and

actual power dissipated is low due to the efﬁcient nature

of the current mode switching regulator.

above 4.7V, the 5V regulator is turned off and an internal

switch is turned on connecting EXTV to INTV . This

CC

allowstheINTV powertobederivedfromahighefﬁciency

CC

external source such as the output of the regulator itself

or a secondary winding, as described in the Applications

Information.

Standby Mode Pin

The STBYMD pin is a three-state input that controls com-

mon circuitry within the IC as follows: When the STBYMD

pinisheldatground,bothcontrollerRUN/SSpinsarepulled

to ground providing a single control pin to shut down both

controllers. When the pin is left open, the internal RUN/SS

currents are enabled to charge the RUN/SS capacitor(s),

allowing the turn-on of either controller and activating

necessary common internal biasing. When the STBYMD

pin is taken above 2V, both internal linear regulators are

turned on independent of the state on the RUN/SS pins

of the two switching regulator controllers, providing an

outputpowersourcefor“wake-up”circuitry.Decouplethe

pin with a small capacitor (0.01μF) to ground if the pin is

not connected to a DC potential.

3707fb

11

LTC3707

OPERATION

THEORY AND BENEFITS OF 2-PHASE OPERATION

(Refer to Functional Diagram)

input current, which in turn allows less expensive input

capacitors to be used, reduces shielding requirements for

EMI and improves real world operating efﬁciency.

The LTC1628 and the LTC3707 are the ﬁrst dual high

efﬁciency DC/DC controllers to bring the considerable

beneﬁts of 2-phase operation to portable applications.

Notebook computers, PDAs, handheld terminals and au-

tomotive electronics will all beneﬁt from the lower input

ﬁlteringrequirement,reducedelectromagneticinterference

(EMI) and increased efﬁciency associated with 2-phase

operation.

Figure 3 compares the input waveforms for a representa-

tive single-phase dual switching regulator to the LTC3707

2-phasedualswitchingregulator.Anactualmeasurementof

theRMSinputcurrentundertheseconditionsshowsthat2-

phaseoperationdroppedtheinputcurrentfrom2.53A

RMS

to1.55A

.Whilethisisanimpressivereductioninitself,

RMS

2

rememberthatthepowerlossesareproportionaltoI

,

RMS

Whytheneedfor2-phaseoperation?UpuntiltheLTC1628

wasintroduced,constant-frequencydualswitchingregula-

tors operated both channels in phase (i.e., single-phase

operation). This means that both switches turned on at

the same time, causing current pulses of up to twice the

amplitude of those for one regulator to be drawn from the

input capacitor and battery. These large amplitude current

pulses increased the total RMS current ﬂowing from the

input capacitor, requiring the use of more expensive input

capacitorsandincreasingbothEMIandlossesintheinput

capacitor and battery.

meaning that the actual power wasted is reduced by a fac-

tor of 2.66. The reduced input ripple voltage also means

less power is lost in the input power path, which could

include batteries, switches, trace/connector resistances

and protection circuitry. Improvements in both conducted

and radiated EMI also directly accrue as a result of the

reduced RMS input current and voltage.

Of course, the improvement afforded by 2-phase opera-

tion is a function of the dual switching regulator’s relative

duty cycles which, in turn, are dependent upon the input

voltage V (Duty Cycle = V /V ). Figure 4 shows how

IN

OUT IN

With 2-phase operation, the two channels of the dual-

switchingregulatorareoperated180degreesoutofphase.

Thiseffectivelyinterleavesthecurrentpulsesdrawnbythe

switches,greatlyreducingtheoverlaptimewheretheyadd

together. The result is a signiﬁcant reduction in total RMS

theRMSinputcurrentvariesforsingle-phaseand2-phase

operation for 3.3V and 5V regulators over a wide input

voltage range.

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

3707 F03a

3707 F03b

I

= 2.53A

I

= 1.55A

RMS

IN(MEAS)

RMS

IN(MEAS)

(a)

(b)

Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual

Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple

with the LTC1628 2-Phase Regulator Allows Less Expensive Input Capacitors, Reduces

Shielding Requirements for EMI and Improves Efﬁciency

3707fb

12

LTC3707

OPERATION

(Refer to Functional Diagram)

Itcanreadilybeseenthattheadvantagesof2-phaseopera-

tion are not just limited to a narrow operating range, but

in fact extend over a wide region. A good rule of thumb

for most applications is that 2-phase operation will reduce

theinputcapacitorrequirementtothatforjustonechannel

operating at maximum current and 50% duty cycle.

TheLTC1628andtheLTC3707areproofthatthesehurdles

have been surmounted. The new device offers unique ad-

vantagesfortheever-expandingnumberofhighefﬁciency

power supplies required in portable electronics.

3.0

SINGLE PHASE

A ﬁnal question: If 2-phase operation offers such an

advantage over single-phase operation for dual switching

regulators, why hasn’t it been done before? The answer

is that, while simple in concept, it is hard to implement.

Constant-frequency current mode switching regulators

require an oscillator derived “slope compensation”

signal to allow stable operation of each regulator at over

50% duty cycle. This signal is relatively easy to derive in

single-phase dual switching regulators, but required the

development of a new and proprietary technique to allow

2-phase operation. In addition, isolation between the two

channels becomes more critical with 2-phase operation

becauseswitchtransitionsinonechannelcouldpotentially

disrupt the operation of the other channel.

DUAL CONTROLLER

2.5

2.0

1.5

1.0

0.5

0

2-PHASE

DUAL CONTROLLER

V

= 5V/3A

O1

O2

= 3.3V/3A

0

10

20

30

40

INPUT VOLTAGE (V)

3707 F04

Figure 4. RMS Input Current Comparison

APPLICATIONS INFORMATION

Figure 1 on the ﬁrst page is a basic LTC3707 application

circuit. External component selection is driven by the

50mV

=

R_SENSE

I_MAX

loadrequirement,andbeginswiththeselectionofR

SENSE

and the inductor value. Next, the power MOSFETs and

BecauseofpossiblePCBnoiseinthecurrentsensingloop,

the AC current sensing ripple of ΔV = ΔI • R

also needs to be checked in the design to get good

signal-to-noise ratio. In general, for a reasonable good

PCB layout, a 15mV ΔV

as a conservative number to start with.

D1 are selected. Finally, C and C are selected. The

IN

OUT

SENSE

circuit shown in Figure 1 can be conﬁgured for operation

up to an input voltage of 28V (limited by the external

MOSFETs).

voltage is recommended

SENSE

R

SENSE

Selection For Output Current

When using the controller in very low dropout conditions,

the maximum output current level will be reduced due to

the internal compensation required to meet stability cri-

terion for buck regulators operating at greater than 50%

duty factor. A curve is provided to estimate this reducton

in peak output current level depending upon the operating

duty factor.

R

ischosenbasedontherequiredoutputcurrent.The

SENSE

LTC3707 current comparator has a maximum threshold

of 75mV/R

and an input common mode range of

SENSE

SGND to 1.1(INTV ). The current comparator threshold

CC

sets the peak of the inductor current, yielding a maximum

average output current I

half the peak-to-peak ripple current, ΔI .

equal to the peak value less

MAX

L

AllowingamarginforvariationsintheLTC3707andexternal

component values yields:

3707fb

13

LTC3707

APPLICATIONS INFORMATION

Selection of Operating Frequency

Accepting larger values of ΔI allows the use of low

L

inductances, but results in higher output voltage ripple

The LTC3707 uses a constant frequency architecture with

thefrequencydeterminedbyaninternaloscillatorcapacitor.

This internal capacitor is charged by a ﬁxed current plus

an additional current that is proportional to the voltage

applied to the FREQSET pin.

and greater core losses. A reasonable starting point for

setting ripple current is ΔI = 30% • I

or higher for

OUT(MAX)

good load transient response and sufﬁcient ripple current

signal in the current loop. Remember, the maximum ΔI

occurs at the maximum input voltage.

L

A graph for the voltage applied to the FREQSET pin vs

frequency is given in Figure 5. As the operating frequency

isincreasedthegatechargelosseswillbehigher, reducing

efﬁciency (see Efﬁciency Considerations). The maximum

switching frequency is approximately 310kHz.

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

25% of the current limit determined by R

. Lower

SENSE

inductor values (higher ΔI ) will cause this to occur at

L

2.5

2.0

1.5

1.0

0.5

0

lower load currents, which can cause a dip in efﬁciency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. High efﬁciency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcing the use of more expensive ferrite, molypermalloy,

orKoolMμ^®cores. Actualcorelossisindependentofcore

size for a ﬁxed inductor value, but it is very dependent

on inductance selected. As inductance increases, core

losses go down. Unfortunately, increased inductance

requires more turns of wire and therefore copper losses

will increase.

120

170

220

270

320

OPERATING FREQUENCY (kHz)

3707 F05

Figure 5. FREQSET Pin Voltage vs Frequency

Inductor Value Calculation

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efﬁciency. A higher

frequency generally results in lower efﬁciency because

of MOSFET gate charge losses. In addition to this basic

trade-off, the effect of inductor value on ripple current and

low current operation must also be considered.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

The inductor value has a direct effect on ripple current.

Molypermalloy (from Magnetics, Inc.) is a very good, low

loss core material for toroids, but it is more expensive

than ferrite. A reasonable compromise from the same

manufacturer is Kool Mμ. Toroids are very space efﬁcient,

especiallywhenyoucanuseseverallayersofwire.Because

they generally lack a bobbin, mounting is more difﬁcult.

The inductor ripple current ΔI decreases with higher

L

inductance or frequency and increases with higher V :

IN

⎛

⎞

V_OUT

V_IN

1

ΔI_L=

V_OUT1–

⎜

⎝

⎟

(f)(L)

⎠

3707fb

14

LTC3707

APPLICATIONS INFORMATION

However, designs for surface mount are available that do

not increase the height signiﬁcantly.

which are highest at high input voltages. For V < 20V

IN

the high current efﬁciency generally improves with larger

MOSFETs, while for V > 20V the transition losses rapidly

IN

Power MOSFET and D1 Selection

increasetothepointthattheuseofahigherR

device

DS(ON)

with lower C

actually provides higher efﬁciency. The

RSS

Two external power MOSFETs must be selected for each

controller with the LTC3707: One N-channel MOSFET for

the top (main) switch, and one N-channel MOSFET for the

bottom (synchronous) switch.

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

The peak-to-peak drive levels are set by the INTV

CC

The term (1+δ) is generally given for a MOSFET in the

voltage. This voltage is typically 5V during start-up

form of a normalized R

vs Temperature curve, but

DS(ON)

(see EXTV Pin Connection). Consequently, logic-level

CC

δ = 0.005/°C can be used as an approximation for low

threshold MOSFETs must be used in most applications.

The only exception is if low input voltage is expected

voltageMOSFETs.C isusuallyspeciﬁedintheMOSFET

RSS

characteristics. The constant k = 1.7 can be used to esti-

mate the contributions of the two terms in the main switch

dissipation equation.

(V < 5V); then, sub-logic level threshold MOSFETs

IN

GS(TH)

(V

< 3V) should be used. Pay close attention to the

speciﬁcation for the MOSFETs as well; most of the

BV

DSS

logic level MOSFETs are limited to 30V or less.

The Schottky diode D1 shown in Figure 1 conducts dur-

ing the dead-time between the conduction of the two

power MOSFETs. This prevents the body diode of the

bottom MOSFET from turning on, storing charge during

the dead-time and requiring a reverse recovery period

SelectioncriteriaforthepowerMOSFETsincludethe“ON”

resistanceR

,reversetransfercapacitanceC ,input

DS(ON)

RSS

voltage and maximum output current. When the LTC3707

is operating in continuous mode the duty cycles for the

top and bottom MOSFETs are given by:

that could cost as much as 3% in efﬁciency at high V .

IN

A 1A to 3A Schottky is generally a good compromise for

both regions of operation due to the relatively small aver-

age current. Larger diodes result in additional transition

losses due to their larger junction capacitance. Schottky

diodes should be placed in parallel with the synchronous

MOSFETs when operating in pulse-skip mode or in Burst

Mode operation.

V_OUT

Main Switch Duty Cycle =

V_IN

V_IN– V_OUT

Synchronous SwitchDuty Cycle=

V_IN

The MOSFET power dissipations at maximum output

current are given by:

C and C

Selection

IN

OUT

V_OUT

V_IN

2

The selection of C is simpliﬁed by the multiphase ar-

P_MAIN

=

I

1+δ R

+

IN

(

)

(

2

)

MAX

DS(ON)

chitecture and its impact on the worst-case RMS current

drawnthroughtheinputnetwork(battery/fuse/capacitor).

It can be shown that the worst case RMS current occurs

when only one controller is operating. The controller with

k V

I

C

f

( )

(

_IN) ( _MAX

)

(

)

RSS

V – V_OUT

2

IN

P_SYNC

=

I

1+δ R

DS(ON)

the highest (V )(I ) product needs to be used in the

(

)

(

)

OUT OUT

MAX

V_IN

formula below to determine the maximum RMS current

requirement. Increasing the output current, drawn from

theotherout-of-phasecontroller,willactuallydecreasethe

input RMS ripple current from this maximum value (see

Figure 4). The out-of-phase technique typically reduces

the input capacitor’s RMS ripple current by a factor of

where δ is the temperature dependency of R

is a constant inversely related to the gate drive current.

and k

DS(ON)

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

3707fb

15

LTC3707

APPLICATIONS INFORMATION

30% to 70% when compared to a single phase power

supply solution.

ripple current ratings are often based on only 2000 hours

of life. This makes it advisable to further derate the capaci-

tor, or to choose a capacitor rated at a higher temperature

than required. Several capacitors may also be paralleled

to meet size or height requirements in the design. Always

consult the manufacturer if there is any question.

The type of input capacitor, value and ESR rating have

efﬁciency effects that need to be considered in the selec-

tion process. The capacitance value chosen should be

sufﬁcient to store adequate charge to keep high peak

battery currents down. 20μF to 40μF is usually sufﬁcient

for a 25W output supply operating at 200kHz. The ESR of

the capacitor is important for capacitor power dissipation

as well as overall battery efﬁciency. All of the power (RMS

ripple current • ESR) not only heats up the capacitor but

wastes power from the battery.

ThebeneﬁtoftheLTC3707multiphasecanbecalculatedby

using the equation above for the higher power controller

and then calculating the loss that would have resulted if

both controller channels switch on at the same time. The

total RMS power lost is lower when both controllers are

operatingduetotheinterleavingofcurrentpulsesthrough

the input capacitor’s ESR. This is why the input capacitor’s

requirementcalculatedabovefortheworst-casecontroller

is adequate for the dual controller design. Remember that

inputprotectionfuseresistance,batteryresistanceandPC

board trace resistance losses are also reduced due to the

reducedpeak currents in a multiphasesystem. Theoverall

beneﬁt of a multiphase design will only be fully realized

when the source impedance of the power supply/battery

is included in the efﬁciency testing. The drains of the

two top MOSFETS should be placed within 1cm of each

Medium voltage (20V to 35V) ceramic, tantalum, OS-CON

and switcher-rated electrolytic capacitors can be used

as input capacitors, but each has drawbacks: ceramic

voltage coefﬁcients are very high and may have audible

piezoelectric effects; tantalums need to be surge-rated;

OS-CONs suffer from higher inductance, larger case size

and limited surface-mount applicability; electrolytics’

higher ESR and dryout possibility require several to be

used. Multiphase systems allow the lowest amount of

capacitance overall. As little as one 22μF or two to three

10μF ceramic capacitors are an ideal choice in a 20W to

50W power supply due to their extremely low ESR. Even

though the capacitance at 20V is substantially below their

rating at zero-bias, very low ESR loss makes ceramics

an ideal candidate for highest efﬁciency battery operated

systems. Also consider parallel ceramic and high quality

electrolytic capacitors as an effective means of achieving

ESR and bulk capacitance goals.

other and share a common C (s). Separating the drains

IN

and C may produce undesirable voltage and current

IN

resonances at V .

IN

The selection of C

is driven by the required effective

OUT

series resistance (ESR). Typically once the ESR require-

ment is satisﬁed the capacitance is adequate for ﬁltering.

The output ripple (ΔV ) is determined by:

OUT

⎛

⎞

1

ΔV_OUT≈ ΔI_LESR+

Incontinuousmode,thesourcecurrentofthetopN-channel

⎜

⎝

⎟

8fC_OUT

⎠

MOSFETisasquarewaveofdutycycleV /V .Toprevent

OUT IN

largevoltagetransients,alowESRinputcapacitorsizedfor

the maximum RMS current of one channel must be used.

The maximum RMS capacitor current is given by:

1/2

Wheref=operatingfrequency, C

=outputcapacitance,

OUT

and ΔI = ripple current in the inductor. The output ripple is

L

highestatmaximuminputvoltagesinceΔI increaseswith

L

inputvoltage.WithΔI =0.3I

theoutputripplewill

IN

⎡

⎤

V_OUTV − V

L

OUT(MAX)

(

)

IN

OUT

⎣

⎦

C_INRequiredI_RMS≈I_MAX

typically be less than 50mV at max V assuming:

V_IN

C

OUT

Recommended ESR < 2 R

SENSE

This formula has a maximum at V = 2V , where

IN

OUT

and C

> 1/(8fR

)

SENSE

OUT

I

= I /2. This simple worst case condition is com-

RMS

OUT

TheﬁrstconditionrelatestotheripplecurrentintotheESR

oftheoutputcapacitancewhilethesecondtermguarantees

monlyusedfordesignbecauseevensigniﬁcantdeviations

donotoffermuchrelief.Notethatcapacitormanufacturer’s

3707fb

16

LTC3707

APPLICATIONS INFORMATION

thattheoutputcapacitancedoesnotsigniﬁcantlydischarge

duringtheoperatingfrequencyperiodduetoripplecurrent.

The choice of using smaller output capacitance increases

the ripple voltage due to the discharging term but can be

compensated for by using capacitors of very low ESR to

INTV Regulator

CC

An internal P-channel low dropout regulator produces 5V

at the INTV_CCpin from the V_INsupply pin. INTV_CCpow-

ers the drivers and internal circuitry within the LTC3707.

The INTV_CCpin regulator can supply a peak current of

40mA and must be bypassed to ground with a minimum

of 4.7ꢀF tantalum, 10μF special polymer, or low ESR type

electrolytic capacitor. A 1μF ceramic capacitor placed di-

rectly adjacent to the INTV_CCand PGND IC pins is highly

recommended. Good bypassing is necessary to supply

the high transient currents required by the MOSFET gate

drivers and to prevent interaction between channels.

maintain the ripple voltage at or below 50mV. The I pin

TH

OPTI-LOOP compensation components can be optimized

to provide stable, high performance transient response

regardless of the output capacitors selected.

Manufacturers such as Nichicon, United Chemicon and

Sanyo can be considered for high performance through-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo has the lowest (ESR)(size)

product of any aluminum electrolytic at a somewhat

higher price. An additional ceramic capacitor in parallel

with OS-CON capacitors is recommended to reduce the

inductance effects.

Higher input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3707 to be

exceeded.Thesystemsupplycurrentisnormallydominated

by the gate charge current. Additional external loading of

In surface mount applications multiple capacitors may

need to be used in parallel to meet the ESR, RMS current

handling and load step requirements of the application.

Aluminum electrolytic, dry tantalum and special polymer

capacitorsareavailableinsurfacemountpackages.Special

polymer surface mount capacitors offer very low ESR but

have lower storage capacity per unit volume than other

capacitortypes.Thesecapacitorsofferaverycost-effective

output capacitor solution and are an ideal choice when

combined with a controller having high loop bandwidth.

Tantalum capacitors offer the highest capacitance density

and are often used as output capacitors for switching

regulators having controlled soft-start. Several excellent

surge-tested choices are the AVX TPS, AVX TPSV or

the KEMET T510 series of surface mount tantalums,

available in case heights ranging from 2mm to 4mm.

Aluminumelectrolyticcapacitorscanbeusedincost-driven

applications providing that consideration is given to ripple

current ratings, temperature and long term reliability. A

typical application will require several to many aluminum

electrolytic capacitors in parallel. A combination of the

abovementionedcapacitorswilloftenresultinmaximizing

performance and minimizing overall cost. Other capacitor

types include Nichicon PL series, NEC Neocap, Pansonic

SP and Sprague 595D series. Consult manufacturers for

other speciﬁc recommendations.

the INTV and 3.3V linear regulators also needs to be

CC

taken into account for the power dissipation calculations.

The total INTV current can be supplied by either the 5V

CC

internal linear regulator or by the EXTV input pin. When

CC

the voltage applied to the EXTV pin is less than 4.7V, all

CC

of the INTV current is supplied by the internal 5V linear

CC

regulator. Power dissipation for the IC in this case is high-

est: (V )(I

), and overall efﬁciency is lowered. The

IN INTVCC

gate charge current is dependent on operating frequency

as discussed in the Efﬁciency Considerations section.

The junction temperature can be estimated by using the

equations given in Note 2 of the Electrical Characteristics.

For example, the LTC3707 V current is limited to less

IN

than 24mA from a 24V supply when not using the EXTV

CC

pin as follows:

T = 70°C + (24mA)(24V)(95°C/W) = 125°C

J

Use of the EXTV input pin reduces the junction tem-

CC

perature to:

T = 70°C + (24mA)(5V)(95°C/W) = 81°C

J

Dissipationshouldbecalculatedtoalsoincludeanyadded

current drawn from the internal 3.3V linear regulator.

To prevent maximum junction temperature from being

exceeded, the input supply current must be checked

operating in continuous mode at maximum V .

IN

3707fb

17

LTC3707

APPLICATIONS INFORMATION

EXTV Connection

The following list summarizes the four possible connec-

tions for EXTV

CC

CC:

The LTC3707 contains an internal P-channel MOSFET

switch connected between the EXTV and INTV pins.

1. EXTV LeftOpen(orGrounded).ThiswillcauseINTV

CC CC

tobepoweredfromtheinternal5Vregulatorresultinginan

efﬁciency penalty of up to 10% at high input voltages.

CC

When the voltage applied to EXTV rises above 4.7V,

CC

the internal regulator is turned off and the switch closes,

connecting the EXTV pin to the INTV pin thereby sup-

CC

2. EXTV Connected directly to V . This is the normal

CC

OUT

plying internal power. The switch remains closed as long

connection for a 5V regulator and provides the highest

as the voltage applied to EXTV remains above 4.5V. This

CC

efﬁciency.

allows the MOSFET driver and control power to be derived

3. EXTV Connected to an External supply. If an external

from the output during normal operation (4.7V < V

<

CC

OUT

supply is available in the 5V to 7V range, it may be used to

7V) and from the internal regulator when the output is

out of regulation (start-up, short-circuit). If more current

powerEXTV providing itis compatible withthe MOSFET

CC

gate drive requirements.

is required through the EXTV switch than is speciﬁed,

CC

an external Schottky diode can be added between the

4. EXTV ConnectedtoanOutput-DerivedBoostNetwork.

CC

EXTV and INTV pins. Do not apply greater than 7V to

CC

For 3.3V and other low voltage regulators, efﬁciency gains

the EXTV pin and ensure that EXTV < V .

CC

IN

can still be realized by connecting EXTV to an output-

CC

derivedvoltagethathasbeenboostedtogreaterthan4.7V.

This can be done with either the inductive boost winding

as shown in Figure 6a or the capacitive charge pump

shown in Figure 6b. The charge pump has the advantage

of simple magnetics.

Signiﬁcant efﬁciency gains can be realized by powering

INTV from the output, since the V current resulting

CC

IN

from the driver and control currents will be scaled by a

factor of (Duty Cycle)/(Efﬁciency). For 5V regulators this

supply means connecting the EXTV pin directly to V

.

OUT

CC

However, for 3.3V and other lower voltage regulators,

additional circuitry is required to derive INTV power

CC

from the output.

+

V

IN

1μF

OPTIONAL EXTV

CONNECTION

CC

+

5V < V

< 7V

SEC

C

IN

0.22μF

BAT85

V

SEC

V

IN

+

N-CH

LTC3707

1μF

V

VN2222LL

TG1

SW

TG1

SW

R

SENSE

V

OUT

T1

1:N

L1

EXTV

CC

R6

R5

+

C

FCB

BG1

OUT

BG1

OUT

N-CH

SGND

PGND

3707 F06a

3707 F06b

Figure 6a. Secondary Output Loop & EXTV_CCConnection

Figure 6b. Capacitive Charge Pump for EXTV_CC

3707fb

18

LTC3707

APPLICATIONS INFORMATION

Topside MOSFET Driver Supply (C , D )

the V resistive divider to compensate for the current

OUT

B

comparator’s negative input bias current. The maximum

current ﬂowing out of each pair of SENSE pins is:

External bootstrap capacitors C connected to the BOOST

B

pinssupplythegatedrivevoltagesforthetopsideMOSFETs.

+

–

Capacitor C in the functional diagram is charged though

I

+ I

= (2.4V – V )/24k

B

SENSE

SENSE OUT

external diode D from INTV when the SW pin is low.

B

CC

Since V

is servoed to the 0.8V reference voltage,

OSENSE

When one of the topside MOSFETs is to be turned on,

we can choose R1 in Figure 2 to have a maximum value

to absorb this current.

the driver places the C voltage across the gate-source

B

of the desired MOSFET. This enhances the MOSFET and

turns on the topside switch. The switch node voltage, SW,

⎛

⎞

0.8V

R1_(MAX)= 24k

⎜

⎟

rises to V and the BOOST pin follows. With the topside

IN

2.4V – V

⎝

⎠

OUT

MOSFET on, the boost voltage is above the input supply:

V

= V + V

. The value of the boost capacitor

BOOST

IN

INTVCC

for V

< 2.4V

OUT

C needstobe100timesthatofthetotalinputcapacitance

B

Regulating an output voltage of 1.8V, the maximum value

of R1 should be 32K. Note that for an output voltage above

2.4V, R1 has no maximum value necessary to absorb the

of the topside MOSFET(s). The reverse breakdown of the

external Schottky diode must be greater than V

.

IN(MAX)

When adjusting the gate drive level, the ﬁnal arbiter is the

total input current for the regulator. If a change is made

and the input current decreases, then the efﬁciency has

improved. If there is no change in input current, then there

is no change in efﬁciency.

sensecurrents;however,R1isstillboundedbytheV

feedback current.

OSENSE

Soft-Start/Run Function

The RUN/SS1 and RUN/SS2 pins are multipurpose pins

thatprovideasoft-startfunctionandameanstoshutdown

the LTC3707. Soft-start reduces the input power source’s

surge currents by gradually increasing the controller’s

Output Voltage

The LTC3707 output voltages are each set by an external

feedbackresistivedividercarefullyplacedacrosstheoutput

capacitor. The resultant feedback signal is compared with

theinternalprecision0.800Vvoltagereferencebytheerror

ampliﬁer. The output voltage is given by the equation:

current limit (proportional to V ). This pin can also be

ITH

used for power supply sequencing.

An internal 1.2μA current source charges up the C ca-

SS

R2

R1

⎛

⎝

⎞

pacitor WhenthevoltageonRUN/SS1(RUN/SS2)reaches

.

V_OUT= 0.8V 1+

⎜

⎟

⎠

1.5V,theparticularcontrollerispermittedtostartoperating.

As the voltage on RUN/SS increases from 1.5V to 3.0V,

the internal current limit is increased from 25mV/R_SENSE

to 75mV/R_SENSE. The output current limit ramps up slowly,

taking an additional 1.25s/μF to reach full current. The

output current thus ramps up slowly, reducing the start-

ing surge current required from the input power supply.

If RUN/SS has been pulled all the way to ground there is

a delay before starting of approximately:

+

–

SENSE /SENSE Pins

The common mode input range of the current comparator

sense pins is from 0V to (1.1)INTV . Continuous linear

CC

operation is guaranteed throughout this range allowing

output voltage setting from 0.8V to 7.7V, depending upon

the voltage applied to EXTV . A differential NPN input

CC

stageisbiasedwithinternalresistorsfromaninternal2.4V

source as shown in the Functional Diagram. This requires

that current either be sourced or sunk from the SENSE

pinsdependingontheoutputvoltage. Iftheoutputvoltage

is below 2.4V current will ﬂow out of both SENSE pins to

the main output. The output can be easily preloaded by

1.5V

1.2µA

t_DELAY

=

C = 1.25s /µF C

SS SS

(

)

3V −1.5V

1.2µA

t_IRAMP

C = 1.25s /µF C

SS SS

(

)

3707fb

19

LTC3707

APPLICATIONS INFORMATION

By pulling both RUN/SS pins below 1V and/or pulling

the STBYMD pin below 0.2V, the LTC3707 is put into

low current shutdown (I_Q= 20μA). The RUN/SS pins

can be driven directly from logic as shown in Figure 7.

Diode D1 in Figure 7 reduces the start delay but allows

C_SSto ramp up slowly providing the soft-start function.

Each RUN/SS pin has an internal 6V zener clamp (See

Functional Diagram).

in Figure 7. This resistance shortens the soft-start period

andpreventsthedischargeoftheRUN/SScapacitorduring

an over current condition. Tying this pull-up resistor to

V_INas in Figure 7a, defeats overcurrent latchoff. Diode-

connecting this pull-up resistor to INTV_CC, as in Figure

7b, eliminates any extra supply current during controller

shutdown while eliminating the INTV_CCloading from

preventing controller start-up.

V

INTV

IN

CC

Why should you defeat overcurrent latchoff? During the

prototyping stage of a design, there may be a problem

with noise pickup or poor layout causing the protection

circuit to latch off. Defeating this feature will easily allow

troubleshooting of the circuit and PC layout. The internal

short-circuit and foldback current limiting still remains

active, thereby protecting the power supply system from

failure. After the design is complete, a decision can be

made whether to enable the latchoff feature.

3.3V OR 5V

RUN/SS

*

R

*

SS

D1

RUN/SS

C

SS

C

SS

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

3707 F07

(a)

(b)

Figure 7. RUN/SS Pin Interfacing

The value of the soft-start capacitor C may need to be

SS

Fault Conditions: Overcurrent Latchoff

scaled with output voltage, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

The RUN/SS pins also provide the ability to latch off the

controller(s) when an overcurrent condition is detected.

The RUN/SS capacitor, C , is used initially to turn on

SS

–4

C

SS

> (C

)(V ) (10 ) (R

)

SENSE

OUT

and limit the inrush current. After the controller has been

started and been given adequate time to charge up the

outputcapacitorandprovidefullloadcurrent, theRUN/SS

capacitor is used for a short-circuit timer. If the regulator’s

output voltage falls to less than 70% of its nominal value

The minimum recommended soft-start capacitor of

= 0.1μF will be sufﬁcient for most applications.

C

SS

Fault Conditions: Current Limit and Current Foldback

after C reaches 4.2V, C begins discharging on the as-

SS

The LTC3707 current comparator has a maximum sense

voltage of 75mV resulting in a maximum MOSFET cur-

sumption that the output is in an overcurrent condition. If

theconditionlastsforalongenoughperiodasdetermined

rent of 75mV/R

. The maximum value of current

SENSE

by the size of the C and the speciﬁed discharge current,

SS

limit generally occurs with the largest V at the highest

IN

the controller will be shut down until the RUN/SS pin volt-

age is recycled. If the overload occurs during start-up, the

time can be approximated by:

ambient temperature, conditions that cause the highest

power dissipation in the top MOSFET.

The LTC3707 includes current foldback to help further

limit load current when the output is shorted to ground.

The foldback circuit is active even when the overload

shutdown latch described above is overridden. If the

output falls below 70% of its nominal output level, then

themaximumsensevoltageisprogressivelyloweredfrom

75mV to 25mV. Under short-circuit conditions with very

low duty cycles, the LTC3707 will begin cycle skipping in

order to limit the short-circuit current. In this situation

the bottom MOSFET will be dissipating most of the power

3707fb

t

≈ [C (4.1 – 1.5 + 4.1 – 3.5)]/(1.2μA)

LO1

SS

6

= 2.7 • 10 (C )

SS

If the overload occurs after start-up the voltage on C will

begin discharging from the zener clamp voltage:

SS

6

t

≈ [C (6 – 3.5)]/(1.2μA) = 2.1 • 10 (C )

LO2

SS

This built-in overcurrent latchoff can be overridden by

providing a pull-up resistor to the RUN/SS pin as shown

20

LTC3707

APPLICATIONS INFORMATION

but less than in normal operation. The short-circuit ripple

current is determined by the minimum on-time t_ON(MIN)

of the LTC3707 (less than 200ns), the input voltage and

inductor value:

for turning on each controller independently. If the pin is

provided with a current of >3μA at a voltage greater than

2V, both internal linear regulators (INTV and 3.3V) will

CC

be on even when both controllers are shut down. In this

mode, the onboard 3.3V and 5V linear regulators can

provide power to keep-alive functions such as a keyboard

controller. This pin can also be used as a latching “on”

and/or latching “off” power switch if so designed.

ΔI

= t (V /L)

ON(MIN) IN

L(SC)

The resulting short-circuit current is:

25mV

R_SENSE

1

2

I_SC=

+ ΔI_L(SC)

Frequency of Operation

The LTC3707 has an internal voltage controlled oscillator.

The frequency of this oscillator can be varied over a 2 to 1

range. The pin is internally self-biased at 1.19V, resulting

in a free-running frequency of approximately 220kHz. The

FREQSET pin can be grounded to lower this frequency to

Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

muchhigherthannominallevels.Thecrowbarcauseshuge

currents to ﬂow, that blow the fuse to protect against a

shorted top MOSFET if the short occurs while the control-

ler is operating.

approximately 140kHz or tied to the INTV pin to yield

CC

approximately 310kHz. The FREQSET pin may be driven

with a voltage from 0 to INTV to ﬁx or modulate the

CC

oscillator frequency as shown in Figure 5.

A comparator monitors the output for overvoltage con-

ditions. The comparator (0V) detects overvoltage faults

greaterthan7.5%abovethenominaloutputvoltage.When

this condition is sensed, the top MOSFET is turned off and

the bottom MOSFET is turned on until the overvoltage

condition is cleared. The output of this comparator is

only latched by the overvoltage condition itself and will

thereforeallowaswitchingregulatorsystemhavingapoor

PC layout to function while the design is being debugged.

The bottom MOSFET remains on continuously for as long

Minimum On-Time Considerations

Minimum on-time t

is the smallest time duration

ON(MIN)

that the LTC3707 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that

V_OUT

V_IN(f)

as the 0V condition persists; if V

returns to a safe level,

t_ON(MIN)

<

OUT

normal operation automatically resumes. A shorted top

MOSFET will result in a high current condition which will

openthesystemfuse.Theswitchingregulatorwillregulate

properly with a leaky top MOSFET by altering the duty

cycle to accommodate the leakage.

If the duty cycle falls below what can be accommodated

by the minimum on-time, the LTC3707 will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The Standby Mode (STBYMD) Pin Function

The typical tested minimum on-time of the LTC3707 is

180ns under an ideal condition without switching noise.

However, the minimum on-time can be affected by PCB

switching noise in the voltage and current loops. With

reasonably good PCB layout, minimum 30% inductor

current ripple and about 15mV sensing ripple voltage,

300ns minimum on-time is a conservative number to

start with.

TheStandbyMode(STBYMD)pinprovidesseveralchoices

for start-up and standby operational modes. If the pin is

pulled to ground, the RUN/SS pins for both controllers

are internally pulled to ground, preventing start-up and

thereby providing a single control pin for turning off both

controllersatonce. Ifthepinisleftopenordecoupledwith

a capacitor to ground, the RUN/SS pins are each internally

provided with a starting current enabling external control

3707fb

21

LTC3707

APPLICATIONS INFORMATION

FCB Pin Operation

internal current source pulling the pin high. Include this

current when choosing resistor values R5 and R6.

The FCB pin can be used to regulate a secondary winding

or as a logic level input. Continuous operation is forced

when the FCB pin drops below 0.8V. During continuous

mode, current ﬂows continuously in the transformer pri-

mary. The secondary winding(s) draw current only when

the bottom, synchronous switch is on. When primary

The following table summarizes the possible states avail-

able on the FCB pin:

Table 1

FCB Pin

Condition

Forced Continuous (Current Reversal

Allowed—Burst Inhibited)

0V to 0.75V

load currents are low and/or the V /V

ratio is low,

IN OUT

the synchronous switch may not be on for a sufﬁcient

amountoftimetotransferpowerfromtheoutputcapacitor

to the secondary load. Forced continuous operation will

support secondary windings providing there is sufﬁcient

synchronous switch duty factor. Thus, the FCB input pin

removes the requirement that power must be drawn from

the inductor primary in order to extract power from the

auxiliary windings. With the loop in continuous mode, the

auxiliary outputs may nominally be loaded without regard

to the primary output load.

0.85V < V < V

– 2V

INTVCC

Minimum Peak Current Induces

Burst Mode Operation

FCB

No Current Reversal Allowed

Feedback Resistors

Regulating a Secondary Winding

= V

Burst Mode Operation Disabled

Constant Frequency Mode Enabled

No Current Reversal Allowed

No Minimum Peak Current

INTVCC

Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak

output voltage excursions under worst-case transient

loading conditions. The open-loop DC gain of the control

loop is reduced depending upon the maximum load step

speciﬁcations. Voltage positioning can easily be added to

ThesecondaryoutputvoltageV isnormallysetasshown

SEC

in Figure 6a by the turns ratio N of the transformer:

V

≅ (N + 1) V

OUT

SEC

However, if the controller goes into Burst Mode operation

andhaltsswitchingduetoalightprimaryloadcurrent,then

the LTC3707 by loading the I pin with a resistive divider

TH

having a Thevenin equivalent voltage source equal to the

midpoint operating voltage of the error ampliﬁer, or 1.2V

(see Figure 8).

V

will droop. An external resistive divider from V to

SEC

the FCB pin sets a minimum voltage V

:

SEC(MIN)

The resistive load reduces the DC loop gain while main-

taining the linear control range of the error ampliﬁer.

The maximum output voltage deviation can theoretically

be reduced to half or alternatively the amount of output

capacitance can be reduced for a particular application.

A complete explanation is included in Design Solutions

10. (See www.linear.com)

R6

R5

⎛

⎝

⎞

V_SEC(MIN)≈0.8V 1+

⎜

⎟

⎠

If V

drops below this level, the FCB voltage forces

temporary continuous switching operation until V

again above its minimum.

SEC

is

SEC

In order to prevent erratic operation if no external connec-

tions are made to the FCB pin, the FCB pin has a 0.18μA

INTV

CC

R

T2

T1

I

TH

LTC3707

R

C

3707 F08

Figure 8. Active Voltage Positioning Applied to the LTC3707

3707fb

22

LTC3707

APPLICATIONS INFORMATION

Efﬁciency Considerations

2

3. I R losses are predicted from the DC resistances of

the fuse (if used), MOSFET, inductor, current sense resis-

tor, and input and output capacitor ESR. In continuous

mode the average output current ﬂows through L and

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

R

, but is “chopped” between the topside MOSFET

SENSE

and the synchronous MOSFET. If the two MOSFETs have

approximately the same R

, then the resistance of

DS(ON)

one MOSFET can simply be summed with the resistances

2

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

of L, R

each R

ESR

and ESR to obtain I R losses. For example, if

SENSE

= 30mΩ, R = 50mΩ, R

= 40mΩ (sum of both input and output capacitance

= 10mΩ and

DS(ON)

L

SENSE

where L1, L2, etc. are the individual losses as a percent-

age of input power.

R

losses), then the total resistance is 130mΩ. This results

in losses ranging from 3% to 13% as the output current

increases from 1A to 5A for a 5V output, or a 4% to 20%

loss for a 3.3V output. Efﬁciency varies as the inverse

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most

of the losses in LTC3707 circuits: 1) LTC3707 V cur-

IN

rent (including loading on the 3.3V internal regulator),

square of V

for the same external components and

OUT

2

2) INTV regulator current, 3) I R losses, 4) Topside

CC

output power level. The combined effects of increasingly

lower output voltages and higher currents required by

high performance digital systems is not doubling but

quadrupling the importance of loss terms in the switching

regulator system!

MOSFET transition losses.

1. The V current has two components: the ﬁrst is the DC

IN

supply current given in the Electrical Characteristics table,

which excludes MOSFET driver and control currents; the

second is the current drawn from the 3.3V linear regulator

4. Transition losses apply only to the topside MOSFET(s),

and become signiﬁcant only when operating at high input

voltages (typically 15V or greater). Transition losses can

be estimated from:

output. V current typically results in a small (<0.1%)

IN

loss.

2. INTV current is the sum of the MOSFET driver and

CC

2

control currents. The MOSFET driver current results from

switching the gate capacitance of the power MOSFETs.

Each time a MOSFET gate is switched from low to high

Transition Loss = (1.7) V

I

C

f

IN O(MAX) RSS

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efﬁciency degradation in portable systems. It is

very important to include these “system” level losses

during the design phase. The internal battery and fuse

resistance losses can be minimized by making sure that

to low again, a packet of charge dQ moves from INTV

to ground. The resulting dQ/dt is a current out of INTV

that is typically much larger than the control circuit cur-

CC

rent. In continuous mode, I

=f(Q +Q ), where Q

GATECHG

T B T

and Q are the gate charges of the topside and bottom

B

C has adequate charge storage and very low ESR at the

IN

side MOSFETs.

switching frequency. A 25W supply will typically require

a minimum of 20μF to 40μF of capacitance having a

maximum of 20mΩ to 50mΩ of ESR. The LTC3707 2-

phase architecture typically halves this input capacitance

requirement over competing solutions. Other losses

including Schottky conduction losses during dead-time

and inductor core losses generally account for less than

2% total additional loss.

Supplying INTV power through the EXTV switch input

CC

from an output-derived source will scale the V current

IN

required for the driver and control circuits by a factor of

(Duty Cycle)/(Efﬁciency). For example, in a 20V to 5V ap-

plication,10mAofINTV currentresultsinapproximately

CC

2.5mA of V current. This reduces the mid-current loss

IN

from10%ormore(ifthedriverwaspowereddirectlyfrom

V ) to only a few percent.

IN

3707fb

23

LTC3707

APPLICATIONS INFORMATION

Checking Transient Response

of full-load current having a rise time of 1μs to 10μs will

produce output voltage and I pin waveforms that will

TH

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

give a sense of the overall loop stability without break-

ing the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

load current. When a load step occurs, V

shifts by

OUT

an amount equal to ΔI

(ESR), where ESR is the ef-

LOAD

fective series resistance of C . ΔI

also begins to

OUT

LOAD

charge or discharge C

generating the feedback error

OUT

signal that forces the regulator to adapt to the current

change and return V

this recovery time V

to its steady-state value. During

can be monitored for excessive

OUT

is why it is better to look at the I pin signal which is in

TH

the feedback loop and is the ﬁltered and compensated

overshoot or ringing, which would indicate a stability

problem. OPTI-LOOP compensation allows the transient

response to be optimized over a wide range of output

control loop response. The gain of the loop will be in-

creased by increasing R and the bandwidth of the loop

C

will be increased by decreasing C . If R is increased by

C

capacitance and ESR values. The availability of the I pin

TH

the same factor that C is decreased, the zero frequency

C

not only allows optimization of control loop behavior but

also provides a DC coupled and AC ﬁltered closed loop

response test point. The DC step, rise time and settling

at this test point truly reﬂects the closed loop response.

Assuming a predominantly second order system, phase

margin and/or damping factor can be estimated using the

percentage of overshoot seen at this pin. The bandwidth

can also be estimated by examining the rise time at the

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

pin. The I external components shown in the Figure 1

TH

circuit will provide an adequate starting point for most

with C , causing a rapid drop in V . No regulator can

OUT OUT

applications.

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

The I series R -C ﬁlter sets the dominant pole-zero

TH

C

loop compensation. The values can be modiﬁed slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the ﬁnal PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

C

LOAD

to C

is greater than1:50, the switch rise time

OUT

should be controlled so that the load rise time is limited

to approximately 25 • C . Thus a 10μF capacitor would

LOAD

require a 250μs rise time, limiting the charging current

to about 200mA.

3707fb

24

LTC3707

APPLICATIONS INFORMATION

Automotive Considerations: Plugging into the

Cigarette Lighter

just what it says, while double-battery is a consequence of

tow-truck operators ﬁnding that a 24V jump start cranks

cold engines faster than 12V.

As battery-powered devices go mobile, there is a natural

interest in plugging into the cigarette lighter in order to

conserve or even recharge battery packs during opera-

tion. But before you connect, be advised: you are plug-

ging into the supply from hell. The main power line in an

automobile is the source of a number of nasty potential

transients, including load-dump, reverse-battery, and

double-battery.

The network shown in Figure 9 is the most straight for-

ward approach to protect a DC/DC converter from the

ravages of an automotive power line. The series diode

prevents current from ﬂowing during reverse-battery,

while the transient suppressor clamps the input voltage

during load-dump. Note that the transient suppressor

should not conduct during double-battery operation, but

must still clamp the input voltage below breakdown of the

converter. Although the LTC3707 has a maximum input

voltage of 30V, most applications will be limited to 28V

by the MOSFET BVDSS.

Load-dump is the result of a loose battery cable. When the

cable breaks connection, the ﬁeld collapse in the alterna-

tor can cause a positive spike as high as 60V which takes

several hundred milliseconds to decay. Reverse-battery is

50A I RATING

PK

V

IN

12V

LTC3707

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

1.5KA24A

3707 F09

Figure 9. Automotive Application Protection

3707fb

25

LTC3707

APPLICATIONS INFORMATION

Design Example

Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields

an output voltage of 1.816V.

As a design example for one channel, assume V

=

IN

= 5A,

12V(nominal), V = 22V(max), V

= 2V, I

The power dissipation on the top side MOSFET can be

easily estimated. Choosing a Siliconix Si4412DY results

IN

OUT

MAX

and f = 300kHz.

in; R

= 0.042Ω, C

= 100pF. At maximum input

DS(ON)

RSS

Theinductancevalueischosenﬁrstbasedona30%ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage. Tie the FREQSET

voltage with T(estimated) = 50°C:

2V

22V

2

pin to the INTV pin for 300kHz operation. The minimum

CC

P_MAIN

=

(

5

1+(0.005)(50°C–25°C)

( )

[

]

inductance for 30% ripple current is:

2

⎛

⎞

V_OUT

(f)(L)

V_OUT

V_IN

0.042Ω +1.7 22V 5A 100pF 300kHz

= 230mW

)

(

) ( )(

)(

)

ΔI_L=

1–

⎜

⎟

⎝

⎠

Ashort-circuittogroundwillresultinafoldedbackcurrent

of:

A 4.7μH inductor will produce 25% ripple current and a

3.3μH will result in 36%. The peak inductor current will be

the maximum DC value plus one half the ripple current, or

5.92A, for the 3.3μH value. Increasing the ripple current

will also help ensure that the minimum on-time of 200ns

is not violated. The minimum on-time occurs at maximum

25mV 1⎛ 200ns(22V)⎞

I_SC=

+

= 3.2A

⎜

⎟

⎝

⎠

0.01Ω 2

3.3µH

with a typical value of R

and δ = (0.005/°C)(20) =

DS(ON)

0.1. TheresultingpowerdissipatedinthebottomMOSFET

V :

IN

is:

V_OUT

V_IN(MAX)f 22V(300kHz)

2V

22V – 2V

22V

= 430mW

t_ON(MIN)

=

= 303ns

2

P_SYNC

=

3.2A 1.1 0.042Ω

(

) ( )(

)

The R

resistor value can be calculated by using the

SENSE

maximum current sense voltage speciﬁcation with some

accommodation for tolerances:

which is less than under full-load conditions.

C is chosen for an RMS current rating of at least 3A at

IN

60mV

5.92A

temperature assuming only this channel is on. C

is

OUT

R_SENSE

≤

≈0.01Ω

chosen with an ESR of 0.02Ω for low output ripple. The

output ripple in continuous mode will be highest at the

maximum input voltage. The output voltage ripple due to

ESR is approximately:

Since the output voltage is below 2.4V the output resistive

divider will need to be sized to not only set the output

voltage but also to absorb the SENSE pins speciﬁed input

current.

V

= R

Δ

= 0.02Ω(1.67A) = 33mV

ORIPPLE

ESR( IL) P–P

⎛

⎞

0.8V

R1_(MAX)= 24k

= 24K

⎜

⎟

2.4V – V

⎝

⎠

OUT

0.8V

2.4V –1.8V

⎛

⎞

= 32k

⎜

⎝

⎟

⎠

3707fb

26

LTC3707

APPLICATIONS INFORMATION

PC Board Layout Checklist

ofC

mustreturntothecombinedC (–)terminals.

INTVCC OUT

The path formed by the top N-channel MOSFET, Schottky

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3707. These items are also illustrated graphically in

the layout diagram of Figure 10. The Figure 11 illustrates

the current waveforms present in the various branches

of the 2-phase synchronous regulators operating in the

continuous mode. Check the following in your layout:

diode and the C capacitor should have short leads and

IN

PCtracelengths.Theoutputcapacitor(–)terminalsshould

be connected as close as possible to the (–) terminals

of the input capacitor by placing the capacitors next to

each other and away from the Schottky loop described

above.

3. DotheLTC3707V

to the (+) terminals of C ? The resistive divider must

be connected between the (+) terminal of C

ground and a small V

be as close as possible to the LTC3707 SGND pin. The R2

and R4 connections should not be along the high current

input feeds from the input capacitor(s).

pinsresistivedividersconnect

OSENSE

1. Are the top N-channel MOSFETs M1 and M3 located

within 1cm of each other with a common drain connection

OUT

and signal

OUT

at C ? Do not attempt to split the input decoupling for

IN

decoupling capacitor should

OSENSE

the two channels as it can cause a large resonant loop.

2. Are the signal and power grounds kept separate? The

combinedLTC3707signalgroundpinandthegroundreturn

R

PU

V

PULL-UP

(<7V)

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PGOOD

RUN/SS1

PGOOD

TG1

L1

R

SENSE

D1

+

V

SENSE1

OUT1

3

–

SENSE1

SW1

R2

M1

M2

C

B1

4

V

BOOST1

OSENSE1

R1

5

FREQSET

STBYMD

FCB

V

IN

6

C

OUT1

BG1

R

IN

7

C

IN

INTV

EXTV

CC

C

VIN

GND

LTC3707

8

I

INTV

TH1

V

IN

C

INTVCC

9

SGND

PGND

BG2

OUT2

D2

10

11

12

13

14

3.3V

OUT

I

BOOST2

SW2

TH2

C

B2

M3

M4

L2

V

OSENSE2

–

R

R3

R4

SENSE

V

SENSE2

TG2

OUT2

+

RUN/SS2

3707 F10

Figure 10. LTC3707 Recommended Printed Circuit Layout Diagram

3707fb

27

LTC3707

APPLICATIONS INFORMATION

SW1

D1

L1

R

SENSE1

V

OUT1

+

C

R

L1

OUT1

V

IN

R

IN

+

C

IN

SW2

L2

R

SENSE2

V

OUT2

+

D2

C

R

L2

OUT2

BOLD LINES INDICATE

HIGH, SWITCHING

CURRENT LINES.

KEEP LINES TO A

MINIMUM LENGTH.

3707 F11

Figure 11. Branch Current Waveforms

–

+

4. AretheSENSE andSENSE leadsroutedtogetherwith

minimum PC trace spacing? The ﬁlter capacitor between

from sensitive small-signal nodes, especially from the

opposites channel’s voltage and current sensing feedback

pins. All of these nodes have very large and fast moving

signals and therefore should be kept on the “output side”

of the LTC3707 and occupy minimum PC trace area.

+

–

SENSE and SENSE should be as close as possible to

the IC. Ensure accurate current sensing with Kelvin con-

nections at the SENSE resistor.

5. Is the INTV decoupling capacitor connected close to

7. Use a modiﬁed “star ground” technique: a low imped-

ance,largecopperareacentralgroundingpointonthesame

sideofthePCboardastheinputandoutputcapacitorswith

CC

the IC, between the INTV and the power ground pins?

CC

This capacitor carries the MOSFET drivers current peaks.

An additional 1μF ceramic capacitor placed immediately

tie-ins for the bottom of the INTV decoupling capacitor,

CC

next to the INTV and PGND pins can help improve noise

the bottom of the voltage feedback resistive divider and

the SGND pin of the IC.

CC

performance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2), and boost nodes (BOOST1, BOOST2) away

3707fb

28

LTC3707

APPLICATIONS INFORMATION

PC Board Layout Debugging

Reduce V from its nominal level to verify operation

IN

of the regulator in dropout. Check the operation of the

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

totheinternaloscillatorandprobetheactualoutputvoltage

as well. Check for proper performance over the operating

voltage and current range expected in the application. The

frequencyofoperationshouldbemaintainedovertheinput

voltage range down to dropout and until the output load

dropsbelowthelowcurrentoperationthreshold—typically

10% to 20% of the maximum designed current level in

Burst Mode operation.

undervoltage lockout circuit by further lowering V while

IN

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawell-designed,lownoisePCBimplementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required. Only after each

controller is checked for their individual performance

should both controllers be turned on at the same time.

A particularly difﬁcult region of operation is when one

controller channel is nearing its current comparator trip

pointwhentheotherchannelisturningonitstopMOSFET.

This occurs around 50% duty cycle on either channel due

to the phasing of the internal clocks and may cause minor

duty cycle jitter.

for inductive coupling between C , Schottky and the top

IN

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

SGND pin of the IC.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

when the current sensing leads are hooked up backwards.

The output voltage under this improper hookup will still

be maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

Short-circuit testing can be performed to verify proper

overcurrentlatchoff,or5μAcanbeprovidedtotheRUN/SS

pin(s) by resistors from V to prevent the short-circuit

IN

latchoff from occurring.

3707fb

29

LTC3707

TYPICAL APPLICATION

59k

1M

100k

MBRS1100T3

T1, 1:1.8

+

V

PULL-UP

(<7V)

33μF

25V

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

10μH

PGOOD

RUN/SS1

PGOOD

TG1

0.015Ω

D1

V

0.1μF

OUT1

2

+

5V

SENSE1

3A; 4A PEAK

180pF

1000pF

3

4

8

–

SENSE1

SW1

105k, 1%

5

M1

M2

0.1μF

LT1121

ON/OFF

MBRM

V

BOOST1

OSENSE1

3

2

1

140T3

20k

1%

220k

V

12V

120mA

5

OUT3

INTV

FREQSET

STBYMD

FCB

V

CC

IN

6

150μF, 6.3V

PANASONIC SP

BG1

+

33pF

1μF

25V

10Ω

22μF

50V

100k

0.01μF

7

CMDSH-3TR

EXTV

INTV

CC

0.1μF

GND

LTC3707

8

I

TH1

1μF

10V

15k

4.7μF

1000pF

9

180μF, 4V

PANASONIC SP

SGND

PGND

BG2

V

33pF

IN

CMDSH-3TR

7V TO

28V

10

11

12

13

14

3.3V

OUT

D2

MBRM

140T3

I

BOOST2

SW2

TH2

15k

0.1μF

M3

M4

1000pF

V

OSENSE2

–

20k

1%

V

OUT2

3.3V

5A; 6A PEAK

SENSE2

TG2

63.4k

1%

0.01Ω

1000pF

L1

6.3μH

+

SENSE2

RUN/SS2

180pF

0.1μF

1628 F12

V

: 7V TO 28V

IN

: 5V, 3A/3.3V, 6A/12V, 120mA

OUT

SWITCHING FREQUENCY = 300kHz

MI, M2, M3, M4: NDS8410A

L1: SUMIDA CEP123-6R3MC

T1: 10mH 1:1.8 — DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID

Figure 12. LTC3707 High Efﬁciency Low Noise 5V/3A, 3.3V/5A, 12/120mA Regulator

3707fb

30

LTC3707

PACKAGE DESCRIPTION

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.386 – .393*

(9.804 – 9.982)

.045 ±.005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 ±.0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 ± .004

(0.38 ± 0.10)

.0532 – .0688

(1.35 – 1.75)

× 45°

.004 – .0098

(0.102 – 0.249)

.0075 – .0098

(0.19 – 0.25)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

3707fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

31

LTC3707

TYPICAL APPLICATION

V

PULL-UP

(<7V)

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

L1

RUN/SS1

PGOOD

TG1

PGOOD

8μH

0.015Ω

V

0.1μF

OUT1

+

SENSE1

5V

3A; 4A PEAK

27pF

1000pF

105k

1%

3

–

SENSE1

SW1

M1A

M1B

0.1μF

4

V

BOOST1

OSENSE1

20k

1%

5

INTV

FREQSET

STBYMD

FCB

V

CC

IN

6

47μF 6.3V

BG1

33pF

10Ω

22μF

50V

0.01μF

7

CMDSH-3TR

EXTV

INTV

CC

0.1μF

LTC3707

GND

8

I

TH1

1μF

10V

15k

4.7μF

220pF

9

SGND

PGND

BG2

56μF, 4V

V

33pF

IN

CMDSH-3TR

5.2V TO

28V

10

11

12

13

14

3.3V

OUT

I

BOOST2

SW2

TH2

15k

0.1μF

M2A

M2B

220pF

V

OSENSE2

–

20k

1%

V

OUT2

3.3V

SENSE2

TG2

63.4k

1%

0.015Ω

3A; 4A PEAK

1000pF

L2

8μH

+

27pF

SENSE2

RUN/SS2

0.1μF

: 5.2V TO 28V

3707 F13

V

SWITCHING FREQUENCY = 300kHz

MI, M2: FDS6982S

L1, L2: 8mH SUMIDA CEP1238R0MC

OUTPUT CAPACITORS: PANASONIC SP SERIES

IN

: 5V, 4A/3.3V, 4A

OUT

Figure 13. LTC3707 5V/4A, 3.3V/4A Regulator

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IN

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IN

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IN

Adaptive Power, No RSENSE and PolyPhase are trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.

3707fb

LT 0508 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3707IGN-SYNC#TRPBF
厂家：	Linear
描述：	LTC3707-SYNC - High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C 稳压器开关
文件：	总32页 (文件大小：392K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3707IGN-SYNC#TRPBF [Linear]

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