LTC3708EUH#TR [Linear]
LTC3708 - Fast 2-Phase, No RSENSE Buck Controller with Output Tracking; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C;
| 型号： | LTC3708EUH#TR |
| 厂家： | 
Linear |
| 描述： | LTC3708 - Fast 2-Phase, No RSENSE Buck Controller with Output Tracking; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总32页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3708
Fast 2-Phase, No R
SENSE
Buck Controller with
Output Tracking
FEATURES
DESCRIPTION
The LTC®3708 is a dOal, 2-phase synchronoOs step-down
switching regOlator with oOtpOt voltage Op/down tracking
capability. The IC allows either coincident or ratiometric
tracking. MOltiple LTC3708s can be daisy-chained in ap-
plications reqOiring more than two voltages to be tracked.
Power sOpply seqOencing is accomplished Osing an
external soft-start timing capacitor.
n
Very Low Duty Factor Operation (t
< 85ns)
ON(MIN)
n
No R
™ Option for Maximum Efficiency
SENSE
n
n
n
n
n
n
n
n
n
n
n
n
n
Very Fast Transient Response
Programmable Output Voltage Up/Down Tracking
2-Phase Operation Reduces Input Capacitance
0.6V ±±1 ꢀOtpOt Voltage Reference
External FreqOency Synchronization
Monotonic Soft-Start
TheLTC3708Osesaconstanton-time,valleycOrrentmode
controlarchitectOretodeliververylowdOtyfactorswithoOt
reqOiring a sense resistor. ꢀperating freqOency is selected
byanexternalresistorandiscompensatedforvariationsin
inpOtsOpplyvoltage. Aninternalphase-lockedloopallows
the IC to be synchronized to an external clock.
ꢀnboard High COrrent MꢀSFET Drivers
Wide V Range: Up to 36V
IN
AdjOstable Cycle-by-Cycle COrrent Limit
Instant ꢀOtpOt ꢀvervoltage Protection
ꢀptional Short-CircOit ShOtdown Timer
Power Good ꢀOtpOt with ±00μs Masking
Available in 5mm × 5mm QFN Package
FaOlt protection is provided by an oOtpOt overvoltage
comparator and an optional short-circOit shOtdown timer.
The regOlator cOrrent limit level is Oser programmable. A
wide sOpply range allows voltages as high as 36V to be
stepped down to 0.6V oOtpOt.
APPLICATIONS
n
Digital Signal Processors
Network Servers
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
No R
is a trademark of Linear Technology Corporation.
SENSE
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
High Efficiency Dual Output Step-Down Converter
V
V
(0.5V/DIV)
(0.5V/DIV)
ꢀUT±
V
IN
3.3V Tꢀ 28V
ꢀUT2
5V
±0μF
50V
s4
±μF
4.7μF
±0Ω
±00k
+
V
TG±
DRV
CC
PGꢀꢀD
TG2
CC
M±
M3
M2
M4
L±
L2
±.2μH
3708 TA0±b
2ms/DIV
BꢀꢀST±
BꢀꢀST2
±.4μH
V
V
±.8V
±5A
0.22μF
0.22μF
ꢀUT±
2.5V
±5A
ꢀUT2
SW±
SENSE±
SW2
+
+
+
+
PꢀSCAP
330μF
4V
PꢀSCAP
470μF
2.5V
SENSE2
±00
95
90
85
80
75
70
9.0
7.5
6.0
4.5
3.0
±.5
0
B340A
B340A
LTC3708
BG±
BG2
s2
s2
–
–
SENSE2
SENSE±
PGND±
±2.±k
±2.±k
±9.±k
PGND2
V
V
FB2
FCB
I
ꢀN2
I
TH2
EXTLPF
TRACK±
V
RNG2
FB±
TRACK2
f
±M
IN
V
IN
V
I
IN
ꢀN±
20V Tꢀ 2.5V
IN ꢀUT
±.5M
I
TH±
5V Tꢀ 2.5V
IN
ꢀUT
INTLPF
RUN/SS
SGND
20V Tꢀ ±.8V
IN
ꢀUT
5V Tꢀ ±.8V
IN
ꢀUT
6.04k
6.04k
0.0±μF
33k
6.04k
±0k
0.0±μF
±k
33k
V
RNG±
±00k
0.±μF
0.0±μF
25k
±80pF
±80pF
0.±μF
0.0±
0.±
±
±0
5V
LꢀAD CURRENT (A)
3708 TA0±
L±: PANASꢀNIC ETQP3HIR4BF
L2: PANASꢀNIC ETQP2HIR2BF
M±, M2: RENESAS HAT2±68
M3, M4: RENESAS HAT2±65
3708 TA0±c
3708fb
1
LTC3708
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TꢀP VIEW
InpOt SOpply Voltage (V , DRV )............. 7V to –0.3V
CC
CC
Boosted Topside Driver SOpply Voltage
BꢀꢀST±, 2............................................ 42V to –0.3V
Switch Voltage (SW±, 2).............................. 36V to –5V
32 3± 30 29 28 27 26 25
–
RUN/SS
±
2
3
4
5
6
7
8
24 SENSE±
23 PGND±
+
+
SENSE± , SENSE2 Voltages....................... 36V to –5V
I
TH±
–
–
SENSE± , SENSE2 Voltages.................... ±0V to –0.3V
, I Voltages.................................... 2±V to –0.3V
V
FB±
BG±
DRV
22
2±
I
ꢀN± ꢀN2
TRACK±
SGND
CC
33
(BꢀꢀST – SW) Voltages .............................. 7V to –0.3V
RUN/SS, PGꢀꢀD Voltages .......................... 7V to –0.3V
PGꢀꢀD DC COrrent................................................. 5mA
20 BG2
PGND2
TRACK2
±9
±8 SENSE2
±7
–
V
FB2
I
V
CC
TH2
TRACK±, TRACK2 Voltages..............V + 0.3V to –0.3V
CC
9
±0 ±± ±2 ±3 ±4 ±5 ±6
V
, V
Voltages.................... V + 0.3V to –0.3V
RNG± RNG2 CC
I
, I
Voltages.................................... 2.7V to –0.3V
TH± TH2
V
, V Voltages.................................. 2.7V to –0.3V
FB± FB2
UH PACKAGE
32-LEAD (5mm s 5mm) PLASTIC QFN
INTLPF, EXTLPF Voltages ......................... 2.7V to –0.3V
FCB Voltages............................................... 7V to –0.3V
ꢀperating TemperatOre Range (Note 5).... –40°C to 85°C
JOnction TemperatOre (Note 2) ........................... ±25°C
Storage TemperatOre Range................... –65°C to ±25°C
Reflow Peak Body TemperatOre ........................... 260°C
T
= ±25°C, θ = 34°C/W
JA
JMAX
EXPꢀSED PAD (PIN 33) IS SGND, MUST BE SꢀLDERED Tꢀ PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3708EUH#PBF
LEAD BASED FINISH
LTC3708EUH
TAPE AND REEL
LTC3708EUH#TRPBF
TAPE AND REEL
LTC3708EUH#TR
PART MARKING
3708
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
32-Lead (5mm × 5mm) Plastic QFN
PACKAGE DESCRIPTION
PART MARKING
3708
TEMPERATURE RANGE
–40°C to 85°C
32-Lead (5mm × 5mm) Plastic QFN
ConsOlt LTC Marketing for parts specified with wider operating temperatOre ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, DRVCC = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
I
InpOt DC SOpply COrrent
Normal
ShOtdown
Q
2.4
250
3
400
mA
μA
I
Feedback Pin InpOt COrrent
Internal Reference Voltage
I
= ±.2V (Notes 3, 4)
–50
–±00
nA
FB±,2
TH
V
I
TH
I
TH
= ±.2V, 0°C to 85°C (Notes 3, 4)
= ±.2V (Notes 3, 4)
0.594
0.59±
0.600
0.600
0.606
0.609
V
V
REF
l
V
Feedback Voltage
I
= ±.2V (Note 3)
0.594
0.600
0.02
0.606
V
FB±,2
TH
Feedback Voltage Line RegOlation
V
= 4.5V to 6.5V (Note 3)
1/V
ΔV
CC
FB(LINEREG)±,2
3708fb
2
LTC3708
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, DRVCC = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
–0.05
±.45
MAX
–0.2
±.7
UNITS
1
Feedback Voltage Load RegOlation
Error Amplifier TranscondOctance
ꢀn-Time
I
TH
I
TH
= 0.5V to ±.9V (Note 3)
ΔV
FB(LꢀADREG)±,2
l
g
= ±.2V (Note 3)
±.2
mS
m(EA)±,2
ꢀN±,2
t
I
I
= 60μA, V = 0V
= 30μA, V = 0V
94
±86
±±6
233
±38
280
ns
ns
ꢀN
ꢀN
FCB
FCB
t
t
MinimOm ꢀn-Time
I
I
= ±80μA
= 30μA
50
85
ns
ns
ꢀN(MIN)±,2
ꢀN
ꢀN
MinimOm ꢀff-Time
270
350
ꢀFF(MIN)±,2
V
MaximOm COrrent Sense Threshold
V
V
V
= ±V, V = 0.565V
±25
90
±80
±43
±00
200
±60
±±0
220
mV
mV
mV
SENSE(MAX)±,2
SENSE(MIN)±,2
RNG
RNG
RNG
FB
= 0V, V = 0.565V
FB
= VCC, V = 0.565V
FB
V
MinimOm COrrent Sense Threshold
V
RNG
V
RNG
V
RNG
= ±V, V = 0.635V
–62
–42
–88
mV
mV
mV
FB
= 0V, V = 0.635V
FB
= V , V = 0.635V
CC FB
ꢀvervoltage FaOlt Threshold
Undervoltage FaOlt Threshold
RUN Pin Start Threshold
8.5
–380
0.8
±0
–420
±.3
3
±±.5
–460
±.8
3.3
2.8
–2
1
mV
V
ΔV
ΔV
FB(ꢀV)±,2
FB(UV)±,2
l
V
V
V
RUN/SS(ꢀN)
RUN/SS(LE)
RUN/SS(LT)
RUN/SS(C)
RUN/SS(D)
RUN Pin Latchoff Enable Threshold
RUN Pin Latchoff Threshold
Soft-Start Charge COrrent
RUN/SS Pin Rising
RUN/SS Pin Falling
2.6
V
2.2
2.5
–±.2
2
V
I
I
V
V
V
V
= 0V
–0.5
0.8
μA
μA
V
RUN/SS
RUN/SS
Soft-Start Discharge COrrent
Undervoltage LockoOt
= V
, V
= 0V
3
RUN/SS(LE) FB±,2
V
V
Falling
3.2
3.5
2
3.6
3.8
CC(UVLꢀ)
CC
CC
Undervoltage LockoOt Release
TG Driver POll-Up ꢀn-Resistance
TG Driver POll-Down ꢀn-Resistance
BG Driver POll-Up ꢀn-Resistance
BG Driver POll-Down ꢀn-Resistance
Rising
V
CC(UVLꢀR)
TG R
TG R
BG R
BG R
TG High (Note 6)
TG Low (Note 6)
BG High (Note 6)
BG Low (Note 6)
Ω
Ω
Ω
Ω
UP±,2
2
DꢀWN±,2
UP±,2
3
±
DꢀWN±,2
Tracking
I
TRACK Pin InpOt COrrent
I
TH
= ±.2V, V = 0.2V (Note 3)
TRACK
–±00
–±50
nA
TRACK±,2
V
Feedback Voltage at Tracking
V
= 0V, I = ±.2V (Note 3)
–±0
±90
390
0
200
400
–±0
2±0
4±0
mV
mV
mV
FB(TRACK±,2)
TRACK
TH
V
= 0.2V, I = ±.2V (Note 3)
TRACK
TH
V
TRACK
= 0.4V, I = ±.2V (Note 3)
TH
PGOOD Output
PGꢀꢀD Upper Threshold
PGꢀꢀD Lower Threshold
PGꢀꢀD Hysteresis
Either V Rising
8.5
±0
–±0
3
±±.5
–±±.5
5
1
1
1
V
ΔV
FB
FBH±,2
Either V Falling
–8.5
ΔV
FB
FBL±,2
V
RetOrning
ΔV
FB
FB(HYS)±,2
V
PGꢀꢀD Low Voltage
PGꢀꢀD Leakage COrrent
PGꢀꢀD Delay
I
= 5mA
= 7V
0.±
0.4
PGL
PGꢀꢀD
I
V
V
±±
μA
μs
PGꢀꢀD
PGꢀꢀD
PG Delay
Phase-Locked Loops
Falling
±00
FB
V
V
Forced ContinOoOs Threshold
Clock InpOt Threshold
MeasOred with a DC Voltage at FCB Pin
MeasOred with a AC POlse at FCB Pin
±.9
±
2.±
±.5
2.3
2
V
V
FCB(DC)
FCB(AC)
EXTLPF
I
External Phase Detector ꢀOtpOt COrrent
SoOrcing Capability
Sinking Capability
f
f
< f
> f
, V = 0V
SW± EXTLPF
SW± EXTLPF
20
–20
μA
μA
FCB
FCB
, V
= 2.4
3708fb
3
LTC3708
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, DRVCC = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
t
t
Internal Phase Detector ꢀOtpOt COrrent
SoOrcing Capability
INTLPF
f
f
< f
> f
, V = 0V
SW2 INTLPF
SW2 INTLPF
20
μA
μA
SW±
SW±
Sinking Capability
, V
= 2.4
–20
t
t
ModOlation Range by External PLL
ꢀN±
ꢀN(PLL)±
ꢀN(PLL)2
Up ModOlation
I
I
= 60μA, V
= 60μA, V
= ±.8V
= 0.6V
±86
±86
233
58
ns
ns
ꢀN±
ꢀN±
EXTLPF
EXTLPF
Down ModOlation
80
80
ModOlation Range by Internal PLL
ꢀN2
Up ModOlation
I
I
= 60μA, V
= 60μA, V
= ±.8V
= 0.6V
233
58
ns
ns
ꢀN±
ꢀN±
EXTLPF
EXTLPF
Down ModOlation
Note 1: Stresses beyond those listed Onder AbsolOte MaximOm Ratings
may caOse permanent damage to the device. ExposOre to any AbsolOte
MaximOm Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 4: Internal reference voltage is tested indirectly by extracting error
amplifier offset from the feedback voltage.
Note 5: The LTC3708E is gOaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperatOre range are assOred by design, characterization and correlation
with statistical process controls.
Note 2: T is calcOlated from the ambient temperatOre T and power
J
A
dissipation P as follows:
D
T = T + (P • 34°C/W)
Note 6: R
limit is gOaranteed by design and/or correlation to static
J
A
D
DS(ꢀN)
test.
Note 3: The LTC3708 is tested in a feedback loop that adjOsts V to
achieve a specified error amplifier oOtpOt voltage (I ).
FB
TH
TYPICAL PERFORMANCE CHARACTERISTICS
Load Transient on Channel 1
Load Transient on Channel 2
I
I
ꢀUT2
ꢀUT±
±0A/DIV
±0A/DIV
V
V
ꢀUT±
ꢀUT±
±00mV/DIV
±00mV/DIV
V
ꢀUT2
V
ꢀUT2
±00mV/DIV
±00mV/DIV
3708 G0±
3708 G02
20μs/DIV
20μs/DIV
Coincident Tracking
Ratiometric Tracking
V
V
ꢀUT±
ꢀUT±
0.5V/DIV
0.5V/DIV
V
ꢀUT2
0.5V/DIV
V
ꢀUT2
0.5V/DIV
3708 G04
3708 G03
2ms/DIV
2ms/DIV
3708fb
4
LTC3708
TYPICAL PERFORMANCE CHARACTERISTICS
Soft-Start
Power Loss vs Input Voltage
6
V
ꢀUT±
I
= ±5A
ꢀUT
2V/DIV
V
ꢀUT2
5
2V/DIV
V
= 2.5V
ꢀUT
RUN/SS
5V/DIV
4
3
V
ꢀUT
= ±.8V
I
L±
5A/DIV
2
±
0
3708 G05
50ms/DIV
5
±0
±5
INPUT VꢀLTAGE (V)
20
25
3708 G06
Power Loss vs Load Current
Frequency vs Input Voltage
Frequency vs Load Current
3.5
3.0
2.5
260
240
220
200
±80
±60
250
200
±50
±00
50
V
= 5V
IN
V
= 2.5V
I
= ±5A
ꢀUT
ꢀUT
V
= ±.8V
ꢀUT
2.0
±.5
±.0
0.5
0
EXTERNAL SYNCHRꢀNIZATIꢀN (ANY I
)
ꢀUT
I
= 0A
ꢀUT
FꢀRCED CꢀNTINUꢀUS MꢀDE
EXTERNAL
SYNCHRꢀNIZATIꢀN
DISCꢀNTINUꢀUS MꢀDE
0
±00
±000
±00000
±0
±0000
5
±0
±5
INPUT VꢀLTAGE (V)
20
0
5
±0
±5
25
LꢀAD (mA)
LꢀAD CURRENT (A)
3707 G07
3708 G08
3708 G09
Current Sense Threshold
vs ITH Voltage
On-Time vs ION Current
On-Time vs Temperature
300
250
200
±50
±00
50
±0000
±000
±00
300
250
200
±50
±00
50
V
=
2V
RNG
I
ꢀN
= 30μA
±.4V
±V
0.7V
0.5V
I
ꢀN
= 60μA
0
–50
–±00
–±50
–200
0
±0
75 ±00
0
0.5
±
±.5
2
2.5
–50 –25
0
25 50
±25 ±50
±
±0
±00
CURRENT (μA)
±000
TEMPERATURE (°C)
I
ꢀN
I
TH
VꢀLTAGE (V)
3708 G±0
3708 G±2
3708 G±±
3708fb
5
LTC3708
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense
Threshold vs VRNG Voltage
Maximum Current Sense
Threshold vs Temperature
Load Regulation
(Figure 13 Circuit)
350
300
250
200
±50
±00
50
0
±60
±50
±40
V
RNG
= ±V
–0.±
FꢀRCED
CꢀNTINUꢀUS
MꢀDE
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
±30
±20
±±0
DISCꢀNTINUꢀUS
MꢀDE
0
±.5
VꢀLTAGE (V)
2
0.5 0.75
±
±.25
±.75
3
6
9
±5
0
±2
50
TEMPERATURE (°C)
–50 –25
0
25
75 ±00 ±25 ±50
V
RNG
LꢀAD CURRENT (A)
3708 G±3
3708 G±5
3708 G±4
Error Amplifier gm
vs Temperature
SENSE Pin Input Current
vs Temperature
RUN/SS Pin Current
vs Temperature
±50
±40
±30
±20
±±0
±00
90
3
2
±.6
±.5
±.4
±.3
±.2
±.±
±.0
PULL-DꢀWN CURRENT
–
I
I
SENSE
±
+
SENSE
0
80
PULL-UP CURRENT
70
–±
60
50
–2
75 ±00
±25
±50
50
±25
–50 –25
0
25 50
±25 ±50
–50
50
±00
–50 –25
0
25
75 ±00
–25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3708 G±6
3708 G±7
3708 G±8
Feedback Voltage vs RUN/SS
(Soft-Start)
RUN/SS Latch-Off Thresholds
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
700
600
500
400
300
200
±00
0
4.5
4.0
3.5
3.0
2.5
2.0
4.0
3.5
3.0
2.5
LATCHꢀFF ENABLE
LATCHꢀFF THRESHꢀLD
2.0
2
2.5
±
±.25
±.5
±.75
2.25
–50 –25
0
25 50 75 ±00 ±25 ±50
TEMPERATURE (°C)
50
–50 –25
0
25
75 ±00 ±25 ±50
RUN/SS VꢀLTAGE (V)
TEMPERATURE (°C)
3708 G±9
3708 G20
3708 G2±
3708fb
6
LTC3708
TYPICAL PERFORMANCE CHARACTERISTICS
On-Time vs EXTLPF Voltage
On-Time vs INTLPF Voltage
2-Phase Operation
500
450
400
350
300
250
200
±50
±00
50
500
450
400
350
300
250
200
±50
±00
50
I
IN
2A/DIV
V
IN
I
= 30μA
I
= 30μA
ꢀN2
ꢀN±
200mV/DIV
V
SW±
±0V/DIV
V
SW2
±0V/DIV
I
= 60μA
I
= 60μA
ꢀN2
ꢀN±
3708 G024
V
V
V
I
= ±5V
±μs/DIV
IN
= 5V
ꢀUT±
ꢀUT2
= 3.3V
= I
0
0
= 2A
0.6
±
±.2 ±.4
±.6 ±.8 2.0
0.8
ꢀUT5 ꢀUT3
±
±.±
±.2
±.3
±.4
INTLPF VꢀLTAGE (V)
EXTLPF VꢀLTAGE (V)
3708 G23
3708 G22
Load Transient Response Without
External Synchronization
Load Transient Response with
External Synchronization
I
I
ꢀUT±
ꢀUT±
±0A/DIV
±0A/DIV
f
S
= 200kHz
f = 240kHz
S
f
= 220kHz
f = 220kHz
S
S
SW±
±0V/DIV
SW±
±0V/DIV
V
V
ꢀUT±
ꢀUT±
50mV/DIV
50mV/DIV
3708 G25
3708 G26
±0μs/DIV
±0μs/DIV
Discontinuous Mode Operation
Power Good Mask
V
ꢀUT
V
FB
20mV/DIV
0.2V/DIV
PGꢀꢀD
2V/DIV
I
L
0.5A/DIV
3708 G027
3708 G28
V
V
V
= ±5V
2μs/DIV
±00μs/DIV
IN
= 5V
ꢀUT
FCB
ꢀUT
= 5V
= 20mA
I
3708fb
7
LTC3708
PIN FUNCTIONS
RUN/SS (Pin 1): ROn Control and Soft-Start InpOt. A
capacitor to groOnd at this pin sets the ramp rate of the
oOtpOt voltage (approximately 0.5s/μF) and the time delay
for overcOrrent latchoff (see Applications Information).
Forcing this pin below 0.8V shOts down the LTC3708.
PGND1,PGND2(Pins23,19):PowerGroOnd.Connectthis
pincloselytothesoOrceofthebottomN-channelMꢀSFET,
the (–) terminal of C
and the (–) terminal of C .
DRVCC
IN
SENSE1–, SENSE2– (Pins 24, 18): COrrent Sense Com-
parator InpOt. The (–) inpOt to the cOrrent comparator is
Osed to accOrately Kelvin sense the bottom side of the
sense resistor or MꢀSFET.
I , I (Pins 2, 8): Error Amplifier Compensation Point
TH1 TH2
and COrrent Control Threshold. The cOrrent comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V with 0.8V corresponding to zero
sense voltage (zero cOrrent).
+
+
SENSE1 , SENSE2 (Pins 25, 16): COrrent Sense Com-
parator InpOt. The (+) inpOt to the cOrrent comparator is
normally connected to the SW node Onless Osing a sense
resistor (See Applications Information).
V
, V
(Pins 3, 7): Error Amplifier Feedback InpOt.
FB1
FB2
This pin connects the error amplifier inpOt to an external
SW1,SW2(Pins26,15):SwitchNode.The(–)terminalofthe
resistive divider from V . Additional compensation can
be implemented, if desired, Osing this pin.
ꢀUT
bootstrap capacitor C connects here. This pin swings from
B
a Schottky diode voltage drop below groOnd Op to V .
IN
TRACK1, TRACK2 (Pins 4, 6): Tie TRACK2 pin to a re-
sistive divider connected to the oOtpOt of channel ± for
either coincident or ratiometric oOtpOt tracking. TRACK±
is Osed in the same manner between mOltiple LTC3708s
(see Applications Information). To disable this featOre, tie
TG1, TG2 (Pins 27, 14): Top Gate Drive. Drives the top
N-channel MꢀSFET with a voltage swing eqOal to DRV
sOperimposed on the switch node voltage SW.
CC
BOOST1, BOOST2 (Pins 28, 13): Boosted Floating Driver
SOpply. The (+) terminal of the bootstrap capacitor C
the pins to V . Do Not Float These Pins.
B
CC
connects here. This pin swings from a diode voltage drop
SGND (Pins 5, 33): Signal GroOnd. All small-signal com-
ponentsandcompensationcomponentsshoOldconnectto
this groOnd and eventOally connect to PGND at one point.
The Exposed Pad of the LTC3708EUH mOst be soldered
to the PCB.
below DRV Op to V + DRV .
CC
IN
CC
I
, I
(Pins 29, 12): ꢀn-Time COrrent InpOt. Tie a
ON1 ON2
resistor from V to this pin to set the one-shot timer
IN
cOrrent and thereby set the switching freqOency.
PGOOD (Pin 30): Power Good ꢀOtpOt. ꢀpen-drain logic
oOtpOt that is pOlled to groOnd when either or both oOtpOt
voltages are not within ±±01 of the regOlation point. The
oOtpOt voltage mOst be oOt of regOlation for at least ±00μs
before the power good oOtpOt is pOlled to groOnd.
EXTLPF(Pin9):FilterConnectionfortheExternalPLL.This
PLLisOsedtosynchronizetheLTC3708toanexternalclock.
If external clock is not Osed, leave this pin floating.
INTLPF (Pin 10): Filter Connection for the Internal PLL.
This PLL is Osed to phase shift the second channel to the
first channel by ±80°.
FCB(Pin31):ForcedContinOoOsandExternalClockInpOt.
Tie this pin to groOnd to force continOoOs synchronoOs
V
(Pin 17): Main InpOt SOpply. DecoOple this pin to
CC
operation or to V to enable discontinOoOs mode opera-
CC
SGND with an RC filter (±0Ω, ±μF for example).
tion at light load. Feeding an external clock signal into this
pin will synchronize the LTC3708 to the external clock and
enable forced continOoOs mode.
DRV (Pin 21): Driver SOpply. Provides sOpply to the
CC
drivers for the bottom gates. Also Osed for charging the
bootstrap capacitors.
V
, V
(Pins 32, 11): Sense Voltage Range InpOt.
RNG1 RNG2
BG1, BG2 (Pins 22, 20): Bottom Gate Drive. Drives the
The voltage at this pin is ten times the nominal sense volt-
age at maximOm oOtpOt cOrrent and can be programmed
from 0.5V to 2V. The sense voltage defaOlts to 70mV when
gate of the bottom N-channel MꢀSFET between groOnd
and DRV .
CC
this pin is tied to groOnd, ±40mV when tied to V .
CC
3708fb
8
LTC3708
FUNCTIONAL DIAGRAM
R
IPLL
C
IPLL
INTLPF
FCB
I
ꢀN
R
ꢀN
CLꢀCK DETECTꢀR
V
IN
+
V
CC
FRꢀM CHANNEL 2
TG
C
IN
0.6V
REF
ENABLE
PHASE DETECTꢀR
(PD2)
EXTLPF
PHASE DETECTꢀR
C
VCC
(PD±)
R
EPLL
BꢀꢀST
TG
C
EPLL
Tꢀ CHANNEL 2 ꢀST
C
B
ꢀST
0.7
IꢀN
FCNT
ꢀN
M±
R
t
ꢀN
=
(±0pF)
I
Q
SW
L±
S
V
ꢀUT
+
+
SWITCH
LꢀGIC
D
B
SENSE
20k
C
ꢀUT
+
+
–
DRV
CC
I
I
CMP
REV
–
SHDN
ꢀV
C
DRVCC
BG
M2
±.4V
0.7V
PGND
SENSE
V
RNG
–
s
–
+
0.66V
R2
ꢀV
UV
V
FB
3.3μA
–
R±
±
240k
SGND
EA
Q4
+
–
+
I
TH
C
C
0.54V
R
C
PGꢀꢀD
ENABLE
>±00μs
TRACK
±.3V
+
V
REF
0.6V
–
BLANKING
Q± Q2
Q3
RUN
SHDN
FRꢀM CHANNEL 2
ꢀV AND UV CꢀMPARATꢀRS
±.2μA
SS
6V
DUPLICATE FꢀR SECꢀND
CHANNEL CꢀNTRꢀLLER
+
–
RUN/SS
±.3V
C
NꢀTE: THE RUN/SS PIN ꢀNLY CLAMPS
FꢀR PHASE ± NꢀT PHASE 2.
3708 FD
V
REF
3708fb
9
LTC3708
OPERATION (Refer to Functional Diagram)
Main Control Loop
When the LTC3708 is synchronized to an external clock,
the operating freqOency will then be solely determined by
the external clock.
The LTC3708 Oses a constant on-time, cOrrent mode step-
down architectOre with two control channels operating at
±80 degrees oOt of phase. In normal operation, each top
MꢀSFET is tOrned on for a fixed interval determined by its
own one-shot timer ꢀST. When the top MꢀSFET is tOrned
off, the bottom MꢀSFET is tOrned on Ontil the cOrrent
Output Overvoltage Protection
An overvoltage comparator ꢀV gOards against transient
overshoots (>±01) as well as other more serioOs condi-
tions that may overvoltage the oOtpOt. In this condition,
M± is tOrned off and M2 is tOrned on and held on Ontil
the condition is cleared.
comparator I
trips, restarting the one-shot timer and
CMP
repeatingthecycle.ThetriplevelofthecOrrentcomparator
is set by the I voltage which is the oOtpOt of each error
amplifier, EA. IndOctor cOrrent is determined by sensing
TH
–
+
Short-Circuit Detection and Protection
the voltage between the SENSE and SENSE pins Osing
either the bottom MꢀSFET on-resistance or a separate
sense resistor. At low load cOrrents, the indOctor cOrrent
can drop to zero and become negative. This is detected by
After the controller has been started and given adeqOate
timetochargetheoOtpOtcapacitors,theRUN/SScapacitor
is Osed as the short-circOit time-oOt capacitor. If either one
of the oOtpOt voltages falls to less than 701 of its nominal
oOtpOt voltage, the RUN/SS capacitor begins discharging
on the assOmption that the oOtpOt is in an overcOrrent
and/or short-circOit condition. If the condition lasts for
a long enoOgh period, as determined by the size of the
RUN/SS capacitor, both controllers will be shOt down Ontil
the RUN/SS pin voltage is recycled. This bOilt-in latchoff
can be overridden by providing >5μA pOll-Op at a compli-
ance of 5V to the RUN/SS pin. This cOrrent shortens the
soft-start period bOt also prevents net discharge of the
RUN/SS capacitor dOring an overcOrrent and/or short-
circOit condition.
cOrrent reversal comparator I , which then shOts off M2
REV
resOlting in discontinOoOs operation. Both switches will
remain off with the oOtpOt capacitor sOpplying the load
cOrrent Ontil the I voltage rises above the zero cOrrent
TH
level (0.8V) to initiate another cycle. DiscontinOoOs mode
operation is disabled when the FCB pin is broOght below
±.9V, forcing continOoOs synchronoOs operation.
The main control loop is shOt down by pOlling the RUN/SS
pin low, tOrning off both M± and M2. Releasing the pin al-
lowsaninternal±.2μAcOrrentsoOrcetochargeanexternal
soft-start capacitor, C . When this voltage reaches ±.3V,
SS
the controller tOrns on and begins switching, bOt with the
effectivereferencevoltageclampedat0V.AsC continOes
SS
Power Good (PGOOD) Pin
to charge, the effective reference ramps Op at the same
rate and controls the rise rate of the oOtpOt voltage.
ꢀvervoltage and Ondervoltage comparators ꢀV and UV
pOll the PGꢀꢀD oOtpOt low if the oOtpOt feedback volt-
age exceeds a ±±01 window aroOnd the regOlation point.
In addition, the oOtpOt feedback voltage mOst be oOt of
this window for a continOoOs dOration of at least ±00μs
before PGꢀꢀD is pOlled low. This is to prevent any glitch
on the feedback voltage from creating a false power bad
signal. The PGꢀꢀD will indicate high immediately when
the feedback voltage is in regOlation.
Operating Frequency
TheoperatingfreqOencyisdeterminedimplicitlybythetop
MꢀSFET on-time and the dOty cycle reqOired to maintain
regOlation.Theone-shottimergeneratesanon-timethatis
proportionaltotheidealdOtycycle,thOsholdingfreqOency
approximately constant with changes in V . The nominal
freqOency can be adjOsted with an external resistor R .
IN
ꢀN
3708fb
10
LTC3708
OPERATION (Refer to Functional Diagram)
DRV
The LTC3708’s 2-phase operation brings considerable
benefits to portable applications and aOtomatic electron-
ics. It lowers the inpOt filtering reqOirement, redOces
electromagnetic interference (EMI) and increases the
power conversion efficiency. Until the introdOction of the
2-phase operation, dOal switching regOlators operated
both channels in phase (i.e., single phase operation).
This means that both controlling switches tOrned on at
the same time, caOsing cOrrent pOlses of Op to twice the
amplitOde of those for one regOlator to be drawn from the
inpOtcapacitororbattery. SOchoperationresOltsinhigher
inpOt RMS cOrrent, larger and/or more expensive inpOt
capacitors, more power loss and worse EMI in the inpOt
soOrce (whether a wall adapter or a battery).
CC
Power for the top and bottom MꢀSFET drivers is derived
from the DRV pin. The top MꢀSFET driver is powered
CC
from a floating bootstrap capacitor, C . This capacitor
B
is normally recharged from DRV throOgh an external
CC
Schottky diode, D , when the top MꢀSFET is tOrned off.
B
2-Phase Operation
FortheLTC3708tooperateoptimallyasa2-phasecontroller,
the resistors connected to the I pins mOst be selected
ꢀN
sOch that the free-rOnning freqOency of each channel is
close to that of the other. An internal phase-locked loop
(PLL) will then ensOre that channel 2 operates at the same
freqOency as channel ±, bOt phase shifted by ±80°. The
loopfilterconnectedtotheINTLPFpinprovidesstabilityto
the PLL. For external clock synchronization, a second PLL
is incorporated to adjOst the on-time of channel ± Ontil its
freqOencyisthesameastheexternalclock.Compensation
for the external PLL is throOgh the EXTLPF pin.
In contrast to single phase operation, the two channels of
a 2-phase switching regOlator are operated ±80 degrees
oOtofphase.ThiseffectivelyinterleavesthecOrrentpOlses
drawn by the switches, greatly redOcing the overlap time
where they add together. The resOlt is a significant redOc-
tion in total RMS inpOt cOrrent, which in tOrn allows less
expensive inpOt capacitors to be Osed, redOces shielding
reqOirements for EMI and improves real world operating
efficiency.
The loop filter components tied to the INTLPF and EXTLPF
pins are Osed to compensate the internal PPL and external
PLL respectively. The typical valOe ranges are:
INTLPF: R
= 2kΩ to ±0kΩ, C
= ±0nF to ±00nF
IPLL
IPLL
FigOre±comparestheinpOtwaveformsforarepresentative
single phase dOal switching regOlator to the 2-phase dOal
switching regOlator. An actOal measOrement of the RMS
inpOt cOrrent Onder these conditions shows that 2-phase
EXTLPF: R
≤ ±kΩ, C
= ±0nF to ±00nF
EPLL
EPLL
For noise sOppression, a capacitor with a valOe of ±nF or
less shoOld be placed from INTLPF to groOnd and EXTLPF
to groOnd.
dropped the inpOt cOrrent from 2.53A
to ±.55A
.
RMS
RMS
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VꢀLTAGE
500mV/DIV
3708 F0±
I
= 2.53A
I
= ±.55A
IN(MEAS) RMS
IN(MEAS)
RMS
(1a)
(1b)
Figure 1. Input Waveforms Comparing Single Phase (1a) and 2-Phase (1b) Operation
for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each
3708fb
11
LTC3708
OPERATION (Refer to Functional Diagram)
fact extend over a wide region. A good rOle of thOmb for
mostapplicationsisthat2-phaseoperationwillredOcethe
inpOt capacitance reqOirement to that for jOst one channel
operating at maximOm cOrrent and 501 dOty cycle.
While this is an impressive redOction in itself, remember
2
that the power losses are proportional to I
, meaning
RMS
that the actOal power wasted is redOced by a factor of
2.66. The redOced inpOt ripple cOrrent also means that
less power is lost in the inpOt power path, which coOld
inclOde batteries, switches, trace/connector resistances
and protection circOitry. Improvements in both condOcted
and radiated EMI also directly accrOe as a resOlt of the
redOced RMS inpOt cOrrent and voltage.
3.0
SINGLE PHASE
DUAL CꢀNTRꢀLLER
2.5
2.0
±.5
±.0
0.5
0
ꢀf coOrse, the improvement afforded by 2-phase opera-
tion is a fOnction of the dOal switching regOlator’s relative
dOty cycles which, in tOrn, are dependent Opon the inpOt
2-PHASE
DUAL CꢀNTRꢀLLER
voltage, V . FigOre 2 shows how the RMS inpOt cOrrent
IN
V
V
= 5V/3A
ꢀ±
ꢀ2
= 3.3V/3A
variesforsinglephaseand2-phaseoperationfor3.3Vand
0
±0
20
INPUT VꢀLTAGE (V)
30
40
5V regOlators over a wide inpOt voltage range.
3708 F02
Itcanreadilybeseenthattheadvantagesof2-phaseopera-
tion are not jOst limited to a narrow operating range, bOt in
Figure 2. RMS Input Current Comparison
3708fb
12
LTC3708
APPLICATIONS INFORMATION
+
The basic LTC3708 application circOit is shown on the first
page of this data sheet. External component selection is
primarily determined by the maximOm load cOrrent and
begins with the selection of the power MꢀSFET switches
and/or sense resistor. For the LTC3708, the indOctor cOr-
across this resistor, connect the SENSE pin to the soOrce
–
of the synchronoOs MꢀSFET and the SENSE pin to the
+
–
other end of the resistor. The SENSE and SENSE pins
provide the Kelvin connections, ensOring accOrate voltage
measOrement across the resistor. Using a sense resistor
provides a well-defined cOrrent limit, bOt adds cost and
redOces efficiency. Alternatively, one can Ose the synchro-
noOs MꢀSFET as the cOrrent sense element by simply
rent is determined by the R
of the synchronoOs
DS(ꢀN)
MꢀSFET or by a sense resistor when the Oser opts for
more accOrate cOrrent sensing. The desired amoOnt of
ripple cOrrent and operating freqOency largely determines
+
connecting the SENSE pin to the switch node SW and
theSENSE pintothesoOrceofthesynchronoOsMꢀSFET,
eliminating the sense resistor. This improves efficiency,
bOt one mOst carefOlly choose the MꢀSFET on-resistance
as discOssed below.
–
the indOctor valOe. Finally, C is selected for its ability to
IN
handle the large RMS cOrrent into the converter and C
ꢀUT
is chosen with low enoOgh ESR to meet the oOtpOt voltage
ripple specification.
Maximum Sense Voltage and V
Pin
Power MOSFET Selection
RNG
IndOctor cOrrent is determined by measOring the voltage
Each oOtpOt stage of the LTC3708 reqOires two external
N-channel power MꢀSFETs, one for the top (main) switch
and one for the bottom (synchronoOs) switch. Important
parameters for the power MꢀSFETs are the breakdown
acrosstheR
ofthesynchronoOsMꢀSFETorthroOgh
DS(ꢀN)
+
a sense resistor that appears between the SENSE and
–
SENSE pins. The maximOm sense voltage is set by the
voltageappliedtotheV
pinandiseqOaltoapproximately
voltageV
,thresholdvoltageV
,on-resistance
RNG
(BR)DSS
GS(TH)
RSS
V
/7. The cOrrent mode control loop will not allow the
R
,reversetransfercapacitance,C ,andmaximOm
cOrrent, I
RNG
DS(ꢀN)
indOctor cOrrent valleys to exceed V /(7 • R
). In
.
RNG
SENSE
DS(MAX)
practice, one shoOld allow some margin for variations in
theLTC3708andexternalcomponentvalOes.AgoodgOide
for selecting the sense resistance is:
The gate drive voltage is set by the 5V DRV sOpply.
CC
ConseqOently, logic-level threshold MꢀSFETs mOst be
Osed in LTC3708 applications. If the driver’s voltage is
expected to drop below 5V, then sOb-logic level threshold
MꢀSFETs shoOld be considered.
VRNG
RSENSE
=
10•IOUT(MAX)
When the bottom MꢀSFET is Osed as the cOrrent sense
element, particOlar attention mOst be paid to its on-re-
sistance. MꢀSFET on-resistance is typically specified
The voltage of the V pin can be set Osing an external
RNG
resistive divider from V between 0.5V and 2V, resOlting
CC
innominalsensevoltagesof50mVto200mV.Additionally,
with a maximOm valOe R
at 25°C. Additional
DS(ꢀN)(MAX)
the V
pin can be tied to groOnd or V , in which case
RNG
CC
margin is reqOired to accommodate the rise in MꢀSFET
on-resistance with temperatOre:
the nominal sense voltage defaOlts to 70mV or ±40mV,
respectively.ThemaximOmallowedsensevoltageisaboOt
±.4 times this nominal valOe.
RSENSE
RDS(ON)(MAX)
=
ρT
+
–
Connecting the SENSE and SENSE Pins
The ρ term is a normalization factor (Onity at 25°C) ac-
T
The LTC3708 provides the Oser with an optional method
to sense cOrrent throOgh a sense resistor instead of Osing
coOnting for the significant variation in on-resistance with
temperatOre, typically aboOt 0.41/°C. For a maximOm
the R
of the synchronoOs MꢀSFET. When Osing a
DS(ꢀN)
jOnction temperatOre of ±00°C, Osing a valOe ρ
±.3 is reasonable (see FigOre 3).
=
±00°C
sense resistor, it is placed between the soOrce of the syn-
chronoOs MꢀSFET and groOnd. To measOre the voltage
3708fb
13
LTC3708
APPLICATIONS INFORMATION
2.0
Operating Frequency
The choice of operating freqOency is a trade-off between
efficiency and component size. Low freqOency operation
improves efficiency by redOcing MꢀSFET switching and
driving losses bOt reqOires larger indOctance and/or ca-
pacitance to maintain low oOtpOt ripple voltage.
±.5
±.0
0.5
0
The operating freqOency of LTC3708 applications is deter-
mined implicitly by the one-shot timer that controls the on
time, t , of the top MꢀSFET switch. The on time is set
ꢀN
50
±00
–50
±50
0
by the cOrrent into the I pin according to:
ꢀN
JUNCTIꢀN TEMPERATURE (°C)
3708 F03
0.7
IIꢀN
tꢀN
=
±0pF
(
)
Figure 3. RDS(ON) vs Temperature
Tying a resistor, R , from V to the I pin yields an
ꢀN
IN
ꢀN
The power dissipated by the top and bottom MꢀSFETs
stronglydependsOpontheirrespectivedOtycyclesandthe
loadcOrrent.WhentheLTC3708isoperatingincontinOoOs
mode, the dOty cycles for the MꢀSFETs are:
on time inversely proportional to V . For a step-down
IN
converter,thisresOltsinapproximatelyconstantfreqOency
operation as the inpOt sOpply varies:
VOUT
f =
VOUT
0.7 •RON 10pF
(
)
DTOP
DBOT
=
=
V
IN
FigOre 4 shows how R relates to switching freqOency
ꢀN
V – VOUT
IN
for several common oOtpOt voltages.
V
IN
±000
The resOlting power dissipation in the MꢀSFETs at maxi-
mOm oOtpOt cOrrent are:
PTOP = DTOP •IOUT(MAX)2 • ρT(TOP) •RDS(ON)
+
V
ꢀUT
= 3.3V
V
ꢀUT
= ±.5V
V
ꢀUT
= 2.5V
(0.5)• V 2 •IOUT(MAX) •CRSS • f •
IN
⎛
⎞
1
1
RDR
•
+
⎜
⎟
VGS(TH)
DRV – V
(
)
CC
GS(TH)
⎝
⎠
±00
P
= DBOT •IOUT(MAX)2 • ρT(BOT) •RDS(ON)
BOT
±00
±000
(kΩ)
±0000
3708 F04
R
ꢀN
2
Both MꢀSFETs have I R losses and the top MꢀSFET in-
clOdes an additional term for transition losses, which are
largest at high inpOt voltages. The bottom MꢀSFET losses
are greatest when the bottom dOty cycle is near ±001,
dOring a short circOit or at high inpOt voltage.
Figure 4. Switching Frequency vs RON
3708fb
14
LTC3708
APPLICATIONS INFORMATION
PLL and Frequency Synchronization
Lower ripple cOrrent redOces core losses in the indOctor,
ESR losses in the oOtpOt capacitors and ripples in the
oOtpOt voltage. Highest efficiency operation is obtained at
lowfreqOencywithsmallripplecOrrent.However,achieving
this reqOires a large indOctor. There is a trade-off between
component size and efficiency.
IntheLTC3708, therearetwoonboardphase-lockedloops
(PLL). ꢀne PLL is Osed to achieve freqOency locking and
±80° phase shift between the two channels while the sec-
ond PLL locks onto the rising edge of an external clock.
Since the LTC3708 Oses a constant on-time architectOre,
theerrorsignalgeneratedbythephasedetectorofthePLL
is Osed to vary the on time to achieve freqOency locking
and phase separation. The variable on-time range is from
A reasonable starting point is to choose a ripple cOrrent
that is aboOt 401 of I
. Note that the largest ripple
IN
ꢀUT(MAX)
cOrrent occOrs at the highest V . To gOarantee that ripple
cOrrent does not exceed a specified maximOm, the indOc-
tance shoOld be chosen according to:
0.5 • t to 2 • t , where t is the initial on time set by
ꢀN
ꢀN
ꢀN
the R resistor.
ꢀN
To fOlly Otilize the freqOency synchronization range of the
PLL, it is advisable to set the initial on time properly so
thatthetwochannelshaveclosefree-rOnningfreqOencies.
FreqOencies far apart may exceed the synchronization
⎛
⎞⎛
⎟⎜
⎞
VOUT
f • ΔI
VOUT
L =
1–
⎜
⎟
V
⎝
L(MAX) ⎠⎝
⎠
IN(MAX)
ꢀnce the valOe for L is known, the type of indOctor mOst be
selected. A variety of indOctors designed for high cOrrent,
low voltage applications are available from manOfactOrers
sOch as SOmida and Panasonic.
capability of the PLL. If the two oOtpOt voltages are V
ꢀUT±
and V
, for example, R resistors shoOld then be
ꢀUT2
ꢀN
selected proportionally:
RON1 VOUT1
=
Schottky Diode Selection
RON2 VOUT2
TheSchottkydiodesinparallelwithbothbottomMꢀSFETs
condOct dOring the dead time between the condOction of
thepowerMꢀSFETswitches. Theyareintendedtoprevent
the body diode of the bottom MꢀSFET from tOrning on
and storing charge dOring the dead time, which caOses a
modest(aboOt±1)efficiencyloss.Thediodescanberated
for aboOt one-half to one-fifth of the fOll load cOrrent since
they are on for only a fraction of the dOty cycle. In order
forthediodestobeeffective,theindOctancebetweenthem
and the bottom MꢀSFETs mOst be as small as possible,
mandating that these components be placed as close as
possible in the circOit board layoOt. The diodes can be
omitted if the efficiency loss is tolerable.
Similarly, if the external PLL is engaged to synchronize
to an external freqOency of f , R
shoOld be selected
EXT ꢀN±
close to:
VOUT1
0.7 • fEXT •10pF
RON1
=
⎛
⎝
VOUT2
⎞
hence, R
=
⎜
⎟
ON2
0.7 • fEXT •10pF⎠
In this case, channel ± will first be synchronized to the
externalfreqOencyandchannel2willthenbesynchronized
to channel ± with ±80° phase separation.
C and C
IN
Selection
OUT
Inductor Selection
The selection of C is simplified by the 2-phase architec-
Given the desired inpOt and oOtpOt voltages, the indOc-
tor valOe and operating freqOency determine the ripple
cOrrent:
IN
tOre and its impact on the worst-case RMS cOrrent drawn
throOgh the inpOt network (battery/fOse/capacitor). It can
be shown that the worst-case RMS cOrrent occOrs when
only one controller is operating. The controller with the
⎛
⎞
⎟
⎛
⎜
⎞
⎟
VꢀUT
f •L
VꢀUT
ΔIL =
±–
⎜
V
⎝
⎠
⎝
⎠
IN
3708fb
15
LTC3708
APPLICATIONS INFORMATION
This formOla has a maximOm at V = 2V , where I
RMS
highest (V )(I ) prodOct needs to be Osed in the
IN
ꢀUT
ꢀUT ꢀUT
= I /2. This simple worst-case condition is commonly
formOla below to determine the maximOm RMS cOrrent
reqOirement. Increasing the oOtpOt cOrrent, drawn from
the other oOt-of-phase controller, will actOally decrease
the inpOt RMS ripple cOrrent from this maximOm valOe
(see FigOre 2).
ꢀUT
OsedfordesignbecaOseevensignificantdeviationsdonot
offermOchrelief.NotethatcapacitormanOfactOrer’sripple
cOrrent ratings are often based on only 2000 hoOrs of life.
This makes it advisable to fOrther derate the capacitor, or
to choose a capacitor rated at a higher temperatOre than
reqOired.Severalcapacitorsmayalsobeparalleledtomeet
size or height reqOirements in the design. Always consOlt
the manOfactOrer if there is any qOestion.
The type of inpOt capacitor, valOe and ESR rating have ef-
ficiency effects that need to be considered in the selection
process.ThecapacitancevalOechosenshoOldbesOfficient
to store adeqOate charge to keep pOlsating inpOt cOrrents
down. 20μF to 40μF is OsOally sOfficient for a 25W oOtpOt
sOpply operating at 200kHz. The ESR of the capacitor
is important for capacitor power dissipation as well as
overall efficiency. All of the power (RMS ripple cOrrent
• ESR) not only heats Op the capacitor bOt wastes power
from the battery.
The benefit of the LTC3708 2-phase operation can be
calcOlated by Osing the eqOation above for the higher
power channel and then calcOlating the loss that woOld
have resOlted if both controller channels switch on at the
same time. The total RMS power lost is lower when both
controllersareoperatingdOetotheinterleavingofcOrrent
pOlses throOgh the inpOt capacitor’s ESR. This is why the
inpOt capacitor’s reqOirement calcOlated above for the
worst-case controller is adeqOate for the dOal controller
design. Remember that inpOt protection fOse resistance,
battery resistance and PC board trace resistance losses
are also redOced dOe to the redOced peak cOrrents in a
2-phase system. The overall benefit of a 2-phase design
will only be fully realized when the source impedance of
the power supply/battery is included in the efficiency
testing. The drains of the two top MꢀSFETS shoOld be
placed within ±cm of each other and share a common
2
MediOm voltage (20V to 35V) ceramic, tantalOm, ꢀS-CꢀN
and switcher-rated electrolytic capacitors can be Osed
as inpOt capacitors, bOt each has drawbacks: ceramic
voltage coefficients are very high and may have aOdible
piezoelectric effects; tantalOms need to be sOrge-rated;
ꢀS-CꢀNs sOffer from higher indOctance, larger case
size and limited sOrface-moOnt applicability; electrolyt-
ics’ higher ESR and dryoOt possibility reqOire several to
be Osed. 2-phase systems allow the lowest amoOnt of
capacitance overall. As little as one 22μF or two to three
±0μF ceramic capacitors are an ideal choice in a 20W to
35W power sOpply dOe to their extremely low ESR. Even
thoOgh the capacitance at 20V is sObstantially below their
rating at zero-bias, very low ESR loss makes ceramics
an ideal candidate for highest efficiency battery operated
systems. Also consider parallel ceramic and high qOality
electrolytic capacitors as an effective means of achieving
ESR and bOlk capacitance goals.
C (s). Separating the drains and C may prodOce On-
IN
IN
desirable voltage and cOrrent resonances at V .
IN
The selection of C
is driven by the effective series
ꢀUT
resistance (ESR) reqOired to minimize voltage ripple
and load step transients. The oOtpOt ripple (ΔV ) is
determined by:
ꢀUT
⎛
⎝
1
⎞
ΔVOUT ≈ ΔI ESR +
⎜
⎟
⎠
L
In continOoOs mode, the cOrrent of the top N-channel
MꢀSFET is approximately a sqOare wave of dOty cycle
8fCOUT
V /V . To prevent large voltage transients, a low ESR
ꢀUT IN
where f = operating freqOency, C
= oOtpOt capacitance,
ꢀUT
inpOt capacitor sized for the maximOm RMS cOrrent of
one channel mOst be Osed. The maximOm RMS capacitor
cOrrent is given by:
and ΔI = ripple cOrrent in the indOctor. The oOtpOt ripple
L
is highest at maximOm inpOt voltage since ΔI increases
L
with inpOt voltage. Typically, once the ESR reqOirement
is satisfied, the capacitance is adeqOate for filtering and
has the necessary RMS cOrrent rating.
±/2
⎦
⎡
⎤
VꢀUT V − V
(
)
IN
ꢀUT
⎣
IRMS ≈IMAX
V
IN
3708fb
16
LTC3708
APPLICATIONS INFORMATION
BꢀꢀST pin rises to approximately V + DRV . The boost
ManOfactOrers sOch as Nichicon, United Chemi-Con and
Sanyo can be considered for high performance throOgh-
hole capacitors. The ꢀS-CꢀN semicondOctor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
prodOct of any alOminOm electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with ꢀS-CꢀN capacitors is recommended to redOce the
indOctance effects.
IN
CC
capacitor needs to store aboOt ±00 times the gate charge
reqOired by the top MꢀSFET. In most applications 0.±μF
to 0.47μF is adeqOate.
Discontinuous Mode Operation and FCB Pin
The FCB pin determines whether the bottom MꢀSFET
remains on when cOrrent reverses in the indOctor. Tying
this pin above its 2.3V threshold (typically to V ) enables
In sOrface moOnt applications mOltiple capacitors may
need to be Osed in parallel to meet the ESR, RMS cOrrent
handling and load step reqOirements of the application.
AlOminOm electrolytic, dry tantalOm and special polymer
capacitorsareavailableinsOrfacemoOntpackages.Special
polymer capacitors offer very low ESR bOt have lower
storage capacity per Onit volOme than other capacitor
types. These capacitors offer a very cost-effective oOtpOt
capacitor solOtion and are an ideal choice when combined
with a controller having high loop bandwidth. TantalOm
capacitors offer the highest capacitance density and are
often Osed as oOtpOt capacitors for switching regOlators
havingcontrolledsoft-start.SeveralexcellentsOrge-tested
choices are the AVX TPS, AVX TPSV or the KEMET T5±0
seriesofsOrfacemoOnttantalOms,availableincaseheights
rangingfrom2mmto4mm.AlOminOmelectrolyticcapaci-
tors can be Osed in cost-driven applications providing that
considerationisgiventoripplecOrrentratings,temperatOre
and long term reliability. A typical application will reqOire
several to many alOminOm electrolytic capacitors in paral-
lel. A combination of the above mentioned capacitors will
often resOlt in maximizing performance and minimizing
overall cost. ꢀther capacitor types inclOde Nichicon PL
series,SanyoPꢀSCAP,NECNeocap,CornellDObilierESRE
andSpragOe595Dseries.ConsOltmanOfactOrersforother
specific recommendations.
CC
discontinOoOs operation where the bottom MꢀSFET tOrns
off when indOctor cOrrent reverses. The load cOrrent at
whichcOrrentreversesanddiscontinOoOsoperationbegins
depends on the amplitOde of the indOctor ripple cOrrent
and the ripple cOrrent depends on the choice of indOctor
valOe and operating freqOency as well as the inpOt and
oOtpOt voltages.
Tying the FCB pin below ±.9V forces continOoOs synchro-
noOs operation, allowing cOrrent to reverse at light loads
and maintaining high freqOency operation.
Besides providing a logic inpOt to force continOoOs op-
eration, the FCB pin acts as the inpOt for external clock
synchronization. Upon detecting the presence of an ex-
ternal clock signal, channel ± will lock on to this external
clock and this will be followed by channel 2 (see PLL and
FreqOency Synchronization).
The LTC3708 defaOlts to forced continOoOs mode when
sychronized to an external clock or when the PGꢀꢀD
signal is low.
Fault Conditions: Current Limit
The maximOm indOctor cOrrent is inherently limited in a
cOrrent mode controller by the maximOm sense voltage.
In the LTC3708, the maximOm sense voltage is controlled
bythevoltageontheV
pin. WithvalleycOrrentcontrol,
RNG
Top MOSFET Driver Supply
the maximOm sense voltage and the sense resistance
determine the maximOm allowed indOctor valley cOrrent.
The corresponding oOtpOt cOrrent limit is:
(C , D in the Functional Diagram)
B
B
An external bootstrap capacitor, C , connected to the
B
BꢀꢀST pin sOpplies the gate drive voltage for the topside
VSNS(MAX)
±
2
MꢀSFET. This capacitor is charged throOgh diode D from
B
ILIMIT
=
+ • ΔIL
DRV when the switch node is low. Note that the average
RDS(ꢀN) • ρT
CC
voltage across C is approximately DRV . When the top
B
CC
MꢀSFET tOrns on, the switch node rises to V and the
IN
3708fb
17
LTC3708
APPLICATIONS INFORMATION
2.0
±.5
±.0
0.5
0
The cOrrent limit valOe shoOld be checked to ensOre that
I
> I
. The minimOm valOe of cOrrent
LIMIT(MIN)
ꢀUT(MAX)
limit generally occOrs with the largest V at the highest
IN
DRꢀPꢀUT
REGIꢀN
ambient temperatOre, conditions which caOse the largest
power loss in the converter. Note that it is important to
check for self-consistency between the assOmed jOnction
temperatOre and the resOlting valOe of I
the jOnction.
, which heats
LIMIT
CaOtionshoOldbeOsedwhensettingthecOrrentlimitbased
Opon the R of the MꢀSFETs. The maximOm cOrrent
DS(ꢀN)
0
0.25
0.50
0.75
±.0
limitisdeterminedbytheminimOmMꢀSFETon-resistance.
DatasheetstypicallyspecifynominalandmaximOmvalOes
DUTY CYCLE (V /V
)
ꢀUT IN
3708 F05
for R
, bOt not a minimOm. A reasonable assOmption
DS(ꢀN)
is that the minimOm R
Figure 5. Maximum Switching Frequency vs Duty Cycle
lies the same amoOnt below
DS(ꢀN)
the typical valOe as the maximOm lies above it. ConsOlt the
MꢀSFET manOfactOrer for fOrther gOidelines.
Soft-Start and Latchoff with the RUN/SS Pin
The RUN/SS pin provides a means to shOt down the
LTC3708 as well as a timer for soft-start and overcOrrent
latchoff.
For a more accOrate cOrrent limiting, a sense resistor
can be Osed. Sense resistors in the ±W power range can
be easily available in the 51, 21 or ±1 tolerance. The
temperatOre coefficient of these resistors is very low,
rangingfrom±250ppm/°Cto±75ppm/°C. Inthiscase, the
POlling the RUN/SS pin below 0.8V shOts down the
LTC3708. Releasing the pin allows an internal ±.2μA in-
ternal cOrrent soOrce to charge the external capacitor, C .
(R
• ρ ) prodOct in the above eqOation can simply
SS
DS(ꢀN)
be replaced by the R
T
If RUN/SS has been pOlled all the way to groOnd, there is
valOe.
SENSE
a delay before starting of aboOt:
Minimum Off Time and Dropout Operation
The minimOm off time t is the smallest amoOnt of
±.3V
±.2μA
tDELAY
=
•CSS = ±.±s/μF C
(
)
SS
ꢀFF(MIN)
time that the LTC3708 is capable of tOrning on the bottom
MꢀSFET, tripping the cOrrent comparator and tOrning the
MꢀSFET back off. This time is generally aboOt 270ns.
The minimOm off time limit imposes a maximOm dOty
When the RUN/SS voltage reaches the ꢀN threshold
(typically ±.3V), the LTC3708 begins operating with a
clamp on channel ±’s reference voltage. The clamp level
is one threshold voltage below RUN/SS. As the voltage on
RUN/SS continOes to rise, channel ±’s reference is raised
at the same rate, achieving monotonic oOtpOt voltage
soft-start (FigOre 6). When RUN/SS rises 0.6V above the
ꢀN threshold, the reference clamp is invalidated and the
internal precision reference takes over. When channel 2 is
tracked to channel ±, soft-start on channel 2 is aOtomati-
cally achieved (see ꢀOtpOt Voltage Tracking).
cycle of t /(t + t
). If the maximOm dOty cycle
ꢀFF(MIN)
ꢀN ꢀN
is reached, dOe to a dropping inpOt voltage for example,
then the oOtpOt will drop oOt of regOlation. The minimOm
inpOt voltage to avoid dropoOt is:
tON + tOFF(MIN)
VIN(MIN) = VOUT
tON
A plot of maximOm freqOency vs dOty cycle is shown in
FigOre 5.
3708fb
18
LTC3708
APPLICATIONS INFORMATION
V
IN
3.3V ꢀR 5V
RUN/SS
*
RUN/SS
R
SS
D±
$V = 0.6V
ON
ꢀN THRESHꢀLD
C
SS
TIME
3708 F07
*ꢀPTIꢀNAL Tꢀ ꢀVERRIDE
ꢀVERCURRENT LATCHꢀFF
V
ꢀUT±
Figure 7. RUN/SS Pin Interfacing with Latchoff Defeated
TIME
3708 F06
Output Voltage Tracking
The LTC3708 allows the Oser to program how the second
channeloOtpOtrampsOpanddownbymeansoftheTRACK2
pin. ThroOgh this pin, the second channel oOtpOt can be
set Op to either coincidently or ratiometrically track the
channel ± oOtpOt, as shown in FigOre 8.
Figure 6. Monotonic Soft-Start Waveforms
Controlledsoft-startreqOiresthatthetimingcapacitor,C ,
SS
be made large enoOgh to gOarantee that the oOtpOt can
track the voltage rise on the RUN/SS pin. The minimOm
Similar to RUN/SS, the TRACK2 pin acts as a clamp on
C
SS
capacitance can be calcOlated:
channel 2’s reference voltage. V
is referenced to the
ꢀUT2
TRACK2 voltage when the TRACK2 < 0.6V and to the
internal precision reference when TRACK2 > 0.6V.
R1+R2 30μA •RSENSE
CSS
>
•
•COUT
R1
VRNG
To implement the tracking in FigOre 8a, connect an extra
resistive divider to the oOtpOt of channel ± and connect
its midpoint to the TRACK2 pin. The ratio of this divider
shoOldbeselectedthesameasthatofchannel2’sfeedback
where R± and R2 are the feedback resistive dividers
(FOnctional Diagram), C is the oOtpOt capacitance
ꢀUT
and R
is the cOrrent sense resistance. When bottom
SENSE
MꢀSFETR
isOsedforcOrrentsensing,R
be replaced with the worst-case R
0.±μF is more than sOfficient for C .
shoOld
DS(ꢀN)
SENSE
divider (FigOre 9a). In this tracking mode, V
must
OUT1
. Generally,
DS(ꢀN)(MAX)
be set higher than V
. To implement the ratiometric
OUT2
SS
tracking in FigOre 8b, no extra divider is needed; simply
After the controller has been started and given adeqOate
connect the TRACK2 pin to the V pin (FigOre 9b).
FB±
time to charge the oOtpOt capacitor, C is Osed as a short-
SS
By selecting different resistors, the LTC3708 can achieve
different modes of tracking inclOding the two in FigOre 8.
So which mode shoOld be programmed? While either
mode in FigOre 8 satisfies most practical applications,
there does exist some trade-off. The ratiometric mode
saves a pair of resistors bOt the coincident mode offers
better oOtpOt regOlation. This can be better Onderstood
with the help of FigOre ±0. At the inpOt stage of channel
2’s error amplifier, two common anode diodes are Osed to
clamp the eqOivalent reference voltage and an additional
diode is Osed to match the shifted common mode voltage.
The top two cOrrent soOrces are of the same amplitOde. In
the coincident mode, the TRACK2 voltage is sObstantially
higher than 0.6V at steady state and effectively tOrns off
circOit timer. After the RUN/SS pin charges above 3V and
if either oOtpOt voltage falls below 701 of its regOlated
valOe, a short-circOit faOlt is assOmed. A 2μA cOrrent then
begins discharging C . If the faOlt condition persists
SS
Ontil the RUN/SS pin drops to 2.5V, the controller tOrns
off all power MꢀSFETs, shOtting down both channels. The
RUN/SS pin mOst be actively pOlled down to groOnd in
order to restart operation.
ꢀvercOrrent latchoff operation is not always needed or
desired and can prove annoying dOring troObleshooting.
This featOre can be overridden by adding a pOll-Op cOr-
rent of >5μA to the RUN/SS pin (FigOre 7). The additional
cOrrent prevents the discharge of C dOring a faOlt and
SS
also shortens the soft-start period.
3708fb
19
LTC3708
APPLICATIONS INFORMATION
V
V
V
ꢀUT±
ꢀUT±
ꢀUT2
V
ꢀUT2
3708 F08
TIME
TIME
(8a) Coincident Tracking
(8b) Ratiometric Tracking
Figure 8. Two Different Modes of Output Voltage Tracking
V
ꢀUT±
V
ꢀUT±
V
V
ꢀUT2
ꢀUT2
R3
R4
R±
R2
R3
R4
R±
R2
R3
R4
Tꢀ
TRACK2
PIN
Tꢀ
FB±
PIN
Tꢀ
TRACK2
PIN
Tꢀ
FB±
PIN
Tꢀ
FB2
PIN
Tꢀ
FB2
PIN
V
V
V
V
3708 F09
(9a) Coincident Tracking Setup
(9b) Ratiometric Tracking Setup
Figure 9. Setup for Coincident and Ratiometric Tracking
⎛
⎝
⎞
⎠
V
VꢀUT2
0.6
R±
R2
R3
R4
=
ꢀUT± − ±,
0.6
=
− ±
⎜
⎟
I-V characteristic of the diodes, it does impose a finite
amoOntofoOtpOtvoltagedeviation. FOrther, whenchannel
±’s oOtpOt experiences dynamic excOrsions (Onder load
transient, for example), channel 2 will be affected as well.
For better output regulation, use the coincident tracking
mode instead of ratiometric.
I
I
+
–
D±
D2
EA2
TRACK2
0.6V
D3
3708 F±0
V
FB2
ThenOmberofresistorsinFigOre9acanbefOrtherredOced
with the scheme in FigOre ±±.
Figure 10. Equivalent Input Circuit of
Error Amplifier of Channel 2
D±. D2 and D3 will therefore condOct the same cOrrent
and offer tight matching between V and the internal
In a system that reqOires more than two tracked sOpplies,
mOltiple LTC3708s can be daisy-chained throOgh the
TRACK± pin. TRACK± clamps channel ±’s reference in the
same manner TRACK2 clamps channel 2. To eliminate the
possibility of mOltiple LTC3708s coming on at different
times, only the master LTC3708’s RUN/SS pin shoOld be
FB2
precision0.6Vreference.Intheratiometricmode,however,
TRACK2 eqOals 0.6V even at steady state. D± will divert
part of the bias cOrrent and make V slightly lower than
FB2
0.6V. AlthoOgh this error is minimized by the exponential
3708fb
20
LTC3708
APPLICATIONS INFORMATION
connected to a soft-start capacitor. All other LTC3708s
Efficiency Considerations
shoOld have their RUN/SS pins pOlled Op to V with a
CC
The percent efficiency of a switching regOlator is eqOal to
the oOtpOt power divided by the inpOt power times ±001.
It is often OsefOl to analyze individOal losses to determine
what is limiting the efficiency and which change woOld
prodOce the most improvement.
resistorbetween50kand300k.FigOre ±2showsthecircOit
with foOr oOtpOts. Three of them are programmed in the
coincidentmodewhilethefoOrthonetracksratiometrically.
If oOtpOt tracking is not needed, connect the TRACK pins
to V . Do Not Float These Pins.
CC
AlthoOgh all dissipative elements in the circOit prodOce
losses, foOr main soOrces accoOnt for most of the losses
in LTC3708 circOits:
V
V
ꢀUT2
ꢀUT±
R±
R2
R4
R5
Tꢀ V
PIN
Tꢀ TRACK2 PIN
FB2
2
±. DC I R Losses. These arise from the resistances of the
MꢀSFETs, indOctor and PC board traces and caOse the
efficiency to drop at high oOtpOt cOrrents. In continOoOs
mode, the average oOtpOt cOrrent flows throOgh L, bOt is
chopped between the top and bottom MꢀSFETs. If the two
Tꢀ V
PIN
FB±
R3
3708 F±±
MꢀSFETs have approximately the same R
, then the
DS(ꢀN)
Figure 11. Alternative Setup for Coincident Tracking
resistanceofoneMꢀSFETcansimplybesOmmedwiththe
⎛
⎝
⎞
⎠
V
VꢀUT2
0.6
R±+R2
R±
R4
=
ꢀUT±
ꢀUT3
ꢀUT± – ±,
0.6
=
=
− ±
2
⎜
⎟
resistances of L and the board traces to obtain the DC I R
R3
R2+R3 R5
loss. For example, if R
= 0.0±Ω and R = 0.005Ω,
DS(ꢀN)
L
the loss will range from ±5mW Op to ±.5W as the oOtpOt
cOrrent varies from ±A to ±0A.
TRACK± TRACK2
Tꢀ V
CC
V
ꢀUT2
V
LTC3708
“MASTER”
R4
R2
R5
R2
R±
R2
R3
V
V
FB2
FB±
V
ꢀUT±
RUN/SS
R2
C
SS
V
V
V
ꢀUT3
ꢀUT4
ꢀUT2
TRACK± TRACK2
V
ꢀUT4
Tꢀ V
V
CC
LTC3708
“SLAVE”
±00k
R4
R5
R2
V
V
FB2
FB±
RUN/SS
R2
3708 F±2
TIME
(12a) Circuit Setup
(12b) Output Voltage
Figure 12. Four Outputs with Tracking and Ratiometric Sequencing
⎛
⎝
⎞
⎠
V
VꢀUT2
0.6
VꢀUT3
0.6
VꢀUT4
0.6
R±
R2
R3
R2
R4
R2
R5
R2
=
ꢀUT± − ±,
0.6
=
− ±,
=
− ±,
=
− ±
⎜
⎟
3708fb
21
LTC3708
APPLICATIONS INFORMATION
2. Transition Loss. This loss arises from the brief amoOnt
of time the top MꢀSFET spends in the satOrated region
dOring switch node transitions. It depends Opon the inpOt
voltage, load cOrrent, driver strength and MꢀSFET capaci-
tance, among other factors. The loss is significant at inpOt
voltages above 20V and can be estimated from:
a load step occOrs, V
immediately shifts by an amoOnt
ꢀUT
eqOal to ΔI
(ESR), where ESR is the effective series
LꢀAD
resistance of C . ΔI
also begins to charge or dis-
ꢀUT
LꢀAD
chargeC generatingafeedbackerrorsignalOsedbythe
ꢀUT
regOlator to retOrn V
this recovery time, V
to its steady-state valOe. DOring
can be monitored for overshoot
ꢀUT
ꢀUT
or ringing that woOld indicate a stability problems. The
pin external components shown in FigOre ±3 will pro-
vide adeqOate compensation for most applications. For a
detailed explanation of switching control loop theory see
Linear Technology Application Note 76.
TransitionLoss ≈
I
TH
(0.5)• V 2 •IOUT •CRSS • f •
IN
⎛
⎞
1
1
RDS(ON)_DRV
+
⎜
⎟
DRV − V
VGS(TH)
⎝
⎠
CC
GS(TH)
Design Example
3. DRV and V COrrent. This is the sOm of the MꢀSFET
CC
CC
As a design example, take a sOpply with the following
specifications: V = 7V to 28V (±5V nominal), V
driverandcontrolcOrrents.ThedrivercOrrentsOppliesthe
IN
ꢀUT±
gate charge Q reqOired to switch the power MꢀSFETs.
G
= 2.5V, V
= ±.8V, I
= I = ±0A,
ꢀUT2
f = 500kHz and V
ꢀUT±(MAX)
ꢀUT2(MAX)
ThiscOrrentistypicallymOchlargerthanthecontrolcircOit
to track V
.
ꢀUT2
ꢀUT±
cOrrent. In continOoOs mode operation:
First calcOlate the timing resistor:
I
= f(Q
+ Q
)
GATECHG
G(TꢀP)
G(BꢀT)
2.5V
4. C Loss. The inpOt capacitor has the difficOlt job of
IN
RON1
=
= 714k
= 514k
0.7V 500kHz 10pF
)( )(
Select a standard valOe of 7±5k.
filtering the large RMS inpOt cOrrent to the regOlator. It
(
)
2
mOst have a very low ESR to minimize the AC I R loss and
sOfficient capacitance to prevent the RMS cOrrent from
caOsing additional Opstream losses in fOses or batteries.
1.8V
RON2
=
TheLTC37082-phasearchitectOretypicallyhalvesthisC
loss over the single phase solOtions.
IN
0.7V 500kHz 10pF
)( )(
(
)
Select a standard valOe of 5±±k.
ꢀther losses, inclOding C
ESR loss, Schottky condOc-
ꢀUT
tionlossdOringdeadtimeandindOctorcorelossgenerally
Next, choose the feedback resistors:
accoOnt for less than 21 additional loss.
R1 2.5V
R2 0.6V
=
– 1= 3.17
When making any adjOstments to improve efficiency, the
final arbiter is the total inpOt cOrrent for the regOlator at
yoOr operating point. If yoO make a change and the inpOt
cOrrentdecreases,thenyoOimprovetheefficiency.Ifthere
is no change in inpOt cOrrent, then there is no change in
efficiency.
Select R± = 3±.6k, R2 = ±0k.
R3 1.8V
R4 0.6V
=
– 1= 2
Select R3 = 20k, R4 = ±0k.
For V to coincidently track V
Checking Transient Response
at start-Op, connect
ꢀUT±
ꢀUT2
The regOlator loop response can be checked by looking
at the load transient response. Switching regOlators take
several cycles to respond to a step in load cOrrent. When
an extra pair of R3 and R4 across V
with its midpoint
ꢀUT±
tied to the TRACK2 pin.
3708fb
22
LTC3708
APPLICATIONS INFORMATION
Third, design the indOctors for aboOt 401 ripple cOrrent
C
= ±90pF, V
= ±V, θ = 42°C/W. Checking its
GS(TH) JA
RSS
at the maximOm V :
power dissipation at cOrrent limit with ρ
= ±.6:
IN
±30°C
2.5V
28V
2.5V
2.5V
28V
2
2
⎛
⎜
⎝
⎞
⎟
⎠
PTOP
=
11.8A 1.6 0.0165Ω + 0.5 28V
L1=
1–
= 1.1μH
(
) ( )(
) ( )(
)
500kHz 0.4 10A
(
)( )(
)
1
1
⎛
⎞
⎟
⎠
11.8A 190pF 500kHz 2Ω
(
= 0.33W + 1.10W = 1.43W
+
)( )( )(
)
⎝
5V – 1V 1V
⎜
Astandard±μHindOctorwillresOltin451ofripplecOrrent
(4.5A) at worst case.
1.8V
1.8V
28V
⎛
⎜
⎝
⎞
⎟
⎠
L2 =
1–
= 0.8μH
T = 70°C + (±.43W)(42°C/W) = ±30°
J
500kHz 0.4 10A
(
)( )(
)
The jOnction temperatOres for both top and bottom
MꢀSFETs will be significantly less at nominal cOrrent, bOt
the above analysis shows that carefOl attention to PCB
layoOt and heat sinking will be necessary in this circOit.
The same MꢀSFETs (Si4874 and Si4884) can be Osed
for channel 2.
L2 can also Ose ±μH to save some BꢀM (Bill of Material)
cost; the resOlting ripple cOrrent is 3.4A.
TheselectionofMꢀSFETsissimplifiedbythefactthatboth
channels have the same maximOm oOtpOt cOrrent. Select
the top and bottom MꢀSFETs for one channel and the
same MꢀSFETs can be Osed for the other. Take channel ±
for calcOlation and begin with the bottom synchronoOs
MꢀSFET. As stated previoOsly in the Power MꢀSFET Se-
lection section, the major criterion in selecting the bottom
Finally, an inpOt capacitor is chosen for an RMS cOrrent
rating of aboOt 5A at 85°C and the oOtpOt capacitors are
chosen for a low ESR of 0.0±3Ω to minimize oOtpOt volt-
age changes dOe to indOctor ripple cOrrent and load steps.
The ripple voltage will be only:
MꢀSFET is low R
. Choose an Si4874 for example:
DS(ꢀN)
R
= 0.0083Ω (nom) 0.0±0Ω (max), θ = 40°C/W.
DS(ꢀN)
JA
⎛
1
⎞
The nominal sense voltage is:
ΔVOUT1(RIPPLE) = ΔI • ESR +
⎜
⎝
⎟
⎠
L1
8 • f •COUT
V
= (±0A)(±.3)(0.0083) = ±08mV
SNS(NꢀM)
⎛
⎞
1
= 4.5A • 0.013Ω +
Tying V
to ±.±V will set the cOrrent sense voltage
⎜
⎟
⎠
RNG±
8 • 500kHz • 470μF
⎝
= 60mV
⎛
range for a nominal valOe of ±±0mV with the cOrrent
limit occOrring at ±46mV. To check if the cOrrent limit is
acceptable, assOme a jOnction temperatOre of aboOt 80°C
1
⎞
ΔVOUT2(RIPPLE) = ΔI • ESR +
⎜
⎟
⎠
L2
above a 70°C ambient with ρ
= ±.5:
±50°C
⎝
8 • f •COUT
146mV
1.5 0.010Ω
)(
1
2
⎛
⎝
⎞
1
ILIMIT
≥
+
4.1A = 11.8A
(
)
= 3.4A • 0.013Ω +
⎜
⎟
⎠
(
)
8 • 500kHz • 470μF
= 46mV
and doOble check the assOmed T in the MꢀSFET:
J
However, a 0A to ±0A load step will caOse an oOtpOt
change of Op to:
28V – 2.5V
28V
2
P
=
11.8A 1.5 0.010Ω = 1.9W
(
) ( )(
)
BOT
ΔV
= ΔI
= (±0A)(0.0±3Ω) = ±30mV
ꢀUT(STEP)
LꢀAD(ESR)
T = 70°C + (±.90W)(40°C/W) = ±46°
J
An optional 22μF ceramic oOtpOt capacitor is inclOded
to minimize the effect of ESL in the oOtpOt ripple. The
complete circOit is shown in FigOre ±3.
BecaOse the top MꢀSFET is on for only a short time,
an Si4884 will be sOfficient: R = 0.0±65Ω (max),
DS(ꢀN)
3708fb
23
LTC3708
APPLICATIONS INFORMATION
V
IN
7V Tꢀ 28V
C
BAT54A
IN
5V
±μF
±0μF
35V
s4
+
±0Ω
±7
4.7μF
3±
BꢀꢀST2
PGND±
V
CC
4
2±
±μF
±μF
V
TRACK± FCB DRV
CC
CC
TG±
BꢀꢀST±
27
±4
±3
M±
TG2
BꢀꢀST2
M2
L±
±μH
L2
±μH
BꢀꢀST2
28
26
25
V
±.8V
±0A
V
0.22μF
0.22μF
ꢀUT±
ꢀUT±
2.5V
±5
±6
SW±
SW2
±0A
+
+
+
C
ꢀUT2
470μF
4V
SENSE2
SENSE±
BG±
+
C
ꢀUT±
470μF
4V
22
20
B340A
B340A
22μF
6.3V
X7R
M3
LTC3708EUH
M4
BG2
–
22μF
6.3V
X7R
24
23
±8
±9
–
SENSE2
SENSE±
PGND±
PGND±
PGND2
32
±±
20k
±1
56pF
3±.6k
±1
V
V
I
V
V
RNG2
RNG2
RNG±
5V
20k
±1
7±5k
5±±k
39k
±±k
56pF
29
3
±2
7
30
±0
8
V
V
V
I
V
IN
IN CC
ꢀN±
ꢀN2
±00k
PGꢀꢀD
FB2
FB±
6
9
2
TRACK2
EXTLPF
PWRGD
INTLPF
0.0±μF
R2
±0k
±1
I
I
±0k
±1
±0k
±1
TH±
TH2
±0k
RUN/SS
SGND
5
20k
20k
±00pF
±
±00pF
0.022μF
0.0±μF
680pF
±nF
0.±μF
680pF
3708 F±3
C
: UNITED CHEMI-CꢀN THCR60EIH±06ZT
IN
C
, C
: SANYꢀ PꢀSCAP 4TPD470M
ꢀUT± ꢀUT2
L±, L2: SUMIDA CEP±25-±R0M
M±, M2: VISHAY Si4884
M3, M4: VISHAY Si4874
Figure 13. Design Example: 2.5V/10A and 1.8V/10A at 500kHz with Output Tracking
• Cover the board area Onder the LTC3708 with a SGND
plane. For the LTC3708EUH, solder the back of the IC
to this plane. Separate SGND from the power groOnd
PC Board Layout Checklist
When laying oOt the printed circOit board, the following
checklist shoOld be Osed to ensOre proper operation of the
LTC3708. These items are also illOstrated graphically in
FigOre ±4. FigOre ±5 fOrther shows the cOrrent waveforms
presentinthevarioOsbranchesofthe2-phasesynchronoOs
BOck regOlators operating in the continOoOs mode.
and connect all signal components (I , V , I , V ,
TH FB ꢀN CC
EXTLPF, INTLPF, V , TRACK and RUN/SS) to the
RNG
SGND plane before it joins PGND. Connect SGND to
the goOnd plane at a single point.
+
–
• ROn SENSE and SENSE across the bottom MꢀSFET
(or R when a separate cOrrent sensing resistor
• Place the loop of M±, M3 and C in a compact area.
IN±
SENSE
This loop condOcts high pOlsating cOrrent and its area
is Osed) with Kelvin connection (FigOre ±6). RoOte
SENSE and SENSE together with minimOm PC trace
separation. The filter capacitor (when Osed) between
SENSE and SENSE shoOld be as close to the LTC3708
as possible.
needs to be minimized. Place M2, M4 and C in the
IN2
+
–
same way.
+
–
• Place C and C within the distance of ±cm. Longer
IN±
IN2
distance may caOse a large resonant loop.
• ConnectthenegativeplatesofC
andC toPGND±
• Keep the high dV/dt nodes SW, TG and BꢀꢀST away
from sensitive small-signal nodes.
ꢀUT±
DR±
before it joins PGND2 at the groOnd plane. Connect
and C in the same way so that power groOnds
C
ꢀUT2
DR2
are separated before they meet at a single point.
3708fb
24
LTC3708
APPLICATIONS INFORMATION
R
ꢀN±
R±
R3
FCB
TG±
PGꢀꢀD
V
FB±
SW±
I
TH±
C
B±
C
ꢀUT±
BꢀꢀST
I
ꢀN±
+
SENSE± EXTLPF
D±
L±
–
SENSE± TRACK±
PGND±
V
RNG±
M3
5V
V
CC
BG±
M±
C
C
C
C
LTC3708
DR±
DR2
VCC
IN±
V
IN
5V
DRV
BG2
SGND
CC
C
IN2
C
SS
M2
RUN/SS
M4
PGND2
V
RNG2
–
SENSE2 TRACK2
L2
D2
+
SENSE2 INTLPF
BꢀꢀST2
SW2
I
ꢀN2
C
ꢀUT2
C
B2
I
TH2
R4
R2
TG2
V
FB2
R
ꢀN2
3708 F±5
Figure 14. LTC3708 Layout Diagram
• Connect the decoOpling capacitors C
and C
DR2
• Flood all OnOsed areas on all layers with copper.
Flooding will redOce the temperatOre rise of the power
components. YoO can connect the copper area to any
DR±
close to the DRV and PGND pins. Connect C and
CC
B±
C
close to the BꢀꢀST and SW pins.
B2
DC net (V , V , GND or to any other DC rail in yoOr
IN ꢀUT
• Connect the decoOpling capacitor C right across the
VCC
system).
V
pinandSGNDplane. ConnecttheEAcompensation
CC
componentsclosetotheI pins. ConnectthePLLloop
TH
filter close to the EXTLPF and INTLPF pins. Connect the
I
decoOpling capacitor close to the I pins.
ꢀN
ꢀN
3708fb
25
LTC3708
APPLICATIONS INFORMATION
SW±
L±
V
ꢀUT±
+
D±
CERAMIC
C
ꢀUT±
R
L±
V
IN
R
IN
+
C
IN
SW2
L2
V
ꢀUT2
+
D2
C
ꢀUT2
R
L2
BꢀLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
CERAMIC
KEEP LINES Tꢀ A
MINIMUM LENGTH.
3708 F±5
Figure 15. Branch Current Waveforms
D
D
D
D
G
S
S
S
R
SENSE
MꢀSFET
+
–
+
–
SENSE SENSE
SENSE SENSE
3708 F±6
(16a) Sensing the Bottom MOSFET
(16b) Sensing a Resistor
Figure 16. Kelvin Sensing
3708fb
26
LTC3708
APPLICATIONS INFORMATION
V
IN
7V Tꢀ 24V
5V
4.7μF
C
IN
±0μF
25V
s6
±μF
±0Ω
±00k
+
D
D
B2
B±
V
CC
TG±
DRV
CC
PGꢀꢀD
TG2
M±
M3
M2
M4
L±
L2
±.22μH
C
C
B2
0.±μF
B±
BꢀꢀST±
BꢀꢀST2
±.43μH
V
V
±.8V
±5A
ꢀUT±
2.5V
±5A
0.±μF
ꢀUT2
SW±
SW2
+
+
+
C
+
C
ꢀUT±
SENSE2
SENSE±
BG±
ꢀUT2
B340LA
B340LA
330μF
4V
470μF
2.5V
s2
LTC3708
BG2
s2
–
–
SENSE2
±2.±k
±1
±9.±k
±1
SENSE±
PGND±
56pF
±2.±k
±1
PGND2
V
V
FB2
FCB
FB±
TRACK2
f
IN
FREQ = 220kHz
V
V
I
I
ꢀN2
I
TH2
IN
IN
ꢀN±
R
R
ꢀN±
±.5M
ꢀN2
±.±M
I
TH±
INTLPF
RUN/SS
SGND
EXTLPF
TRACK±
6.04k
±1
6.04k
±1
6.04k
±1
3.32k
470pF
±5k
470pF
475Ω
±5k
V
V
RNG±
RNG2
±30k
0.0±μF
±50pF
±000pF
0.047μF
±50pF
470pF
±000pF
C
SS
0.±μF
24.9k
±000pF
5V
3708 F±7
C
C
C
: SANYꢀ PꢀSCAP 4TPD330M
DB±, DB2: CMDSH-3
L±: PANASꢀNIC ETQP3H±R4BF
L2: PANASꢀNIC ETQP2H±R2BF
M±, M2: RENESAS HAT2±68H
M3, M4: RENESAS HAT2±65H
ꢀUT±
ꢀUT2
IN
: SANYꢀ PꢀSCAP 2R5TPD470M
: TAIYꢀ YUDEN: TMK325BJ±06KM
Figure 17. High Efficiency, Dual Output Power Supply with External Frequency Synchronization
3708fb
27
LTC3708
TYPICAL APPLICATIONS
3708fb
28
LTC3708
TYPICAL APPLICATIONS
Dual-Phase, 30A Power Supply with 10mV Output Ripple
V
IN
5V
+
C
C
-C
IN±
IN2 IN7
±00μF
6.3V
4.7μF
6.3V s6
TRACK
BAT54A
±μF
±μF
PGND±
±0Ω
BꢀꢀST2
V
CC
PGND2
±μF
BꢀꢀST2
V
CC
TG±
TRACK± FCB DRV
CC
M±
M3
TG2
M2
M4
L±
L2
BꢀꢀST±
BꢀꢀST2
0.±9μH
0.±9μH
V
0.22μF
0.22μF
ꢀUT
±V
SW±
SW2
30A
+
+
+
C
SENSE2
SENSE±
BG±
+
ꢀUT4
C
ꢀUT3
470μF
470μF
B340A
B340A
LTC3708
C
ꢀUT2
BG2
2.5V s2
2.5V s2
C
±00pF
ꢀUT±
±00pF
±μF
–
–
SENSE2
±μF
SENSE±
PGND±
6.3V
6.3V
PGND2
±00k
V
V
RNG±
V
RNG2
V
RNG±
R±
CC
V
IN
274k
274k
±0k
V
V
IN
I
I
IN
ꢀN±
ꢀN2
0.±1
±00k
V
V
FB±
FB2
PGꢀꢀD
TRACK2
EXTLPF
PWRGD
INTLPF
R2
±5k
0.±1
I
I
TH±
RUN/SS
TH2
±nF
SGND
0.0±μF
±0k
±000pF
220pF
0.0±μF
±00k
V
CC
0.0±μF
22k
22.±k
220pF
3708 TA05
C
: SANYꢀ ꢀS-CꢀN 6SVP±00M
IN±
C
, C
: SANYꢀ PꢀSCAP 2R5TPD470M
ꢀUT3 ꢀUT4
L±, L2: PANASꢀNIC ETQP4LR±9
M± Tꢀ M4: RENESAS HAT2±65
3708fb
29
LTC3708
TYPICAL APPLICATIONS
12V/12A and 5V/12A at 300kHz Application
V
IN
20V Tꢀ 28V
C±
C2
+
5V
3.3μF
50V
X5R
3.3μF
50V
X5R
±00μF
50V
BAT54A
±0Ω
BꢀꢀST±
BꢀꢀST2
5V
V
CC
C3
C4
C5
C6
3.3μF
50V
X5R
3.3μF
50V
X5R
3.3μF
50V
X5R
3.3μF
50V
X5R
C6
2.2μF
±μF
V
TRACK± FCB DRV
CC
CC
Q±
HAT2±67H
Q3
HAT2±67H
TG±
TG2
0Ω
0.±μF
0Ω
BꢀꢀST±
BꢀꢀST2
BꢀꢀST2
0.±μF
L±
3.5μH
L2
2.4μH
LTC3708EUH
V
V
ꢀUT2
ꢀUT±
±2V
±2A
SW±
SW2
5V
±2A
+
+
C
C
ꢀUT2
SENSE±
BG±
SENSE2
0Ω
ꢀUT±
+
+
B340LA
0Ω
0Ω
±00pF
D3
B340LA
±00pF
±50μF
±6V
s2
220μF
6.3V
s2
Q2
HAT2±67H
Q4
HAT2±67H
BG2
–
–
0Ω
SENSE±
PGND±
SENSE2
PGND2
V
V
RNG±
RNG2
5.6M
2.2M
22pF
±9±k
75k
5V
I
I
V
V
IN
ꢀN±
ꢀN2
88.7k
IN
V
88.7k
24.9k
75k
±0k
47pF
47pF
±nF
V
CC
CC
±00k
V
FB±
V
FB2
TRACK2
EXTLPF
PGꢀꢀD
INTLPF
PGꢀꢀD
±nF
±0k
I
I
TH2
TH±
RUN/SS
5.±±k
24.9k
±0k
22pF
SGND
±50pF
2.2nF
±50pF
±.5nF
±5k
470pF
0.±μF
22nF
33.2k
3708 TA04
C
C
: SANYꢀ ±6SVP±50M
: SANYꢀ 6TPD220M
ꢀUT±
ꢀUT2
C± Tꢀ C6: TDK C4532X5R±H335M
L±: SUMIDA CDEP±47-3R5MC-H
L2: SUMIDA CDEP±47-2R4MC
3708fb
30
LTC3708
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-±693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.±0 ±0.05
3.45 ± 0.05
3.50 REF
(4 SIDES)
3.45 ± 0.05
PACKAGE ꢀUTLINE
0.25 ± 0.05
0.50 BSC
RECꢀMMENDED SꢀLDER PAD LAYꢀUT
APPLY SꢀLDER MASK Tꢀ AREAS THAT ARE NꢀT SꢀLDERED
BꢀTTꢀM VIEW—EXPꢀSED PAD
PIN ± NꢀTCH R = 0.30 TYP
ꢀR 0.35 s 45° CHAMFER
R = 0.05
TYP
0.00 – 0.05
R = 0.±±5
TYP
0.75 ± 0.05
5.00 ± 0.±0
(4 SIDES)
3± 32
0.40 ± 0.±0
PIN ±
TꢀP MARK
(NꢀTE 6)
±
2
3.45 ± 0.±0
3.50 REF
(4-SIDES)
3.45 ± 0.±0
(UH32) QFN 0406 REV D
0.200 REF
0.25 ± 0.05
0.50 BSC
NꢀTE:
±. DRAWING PRꢀPꢀSED Tꢀ BE A JEDEC PACKAGE ꢀUTLINE
M0-220 VARIATIꢀN WHHD-(X) (Tꢀ BE APPRꢀVED)
2. DRAWING NꢀT Tꢀ SCALE
3. ALL DIMENSIꢀNS ARE IN MILLIMETERS
4. DIMENSIꢀNS ꢀF EXPꢀSED PAD ꢀN BꢀTTꢀM ꢀF PACKAGE Dꢀ NꢀT INCLUDE
MꢀLD FLASH. MꢀLD FLASH, IF PRESENT, SHALL NꢀT EXCEED 0.20mm ꢀN ANY SIDE
5. EXPꢀSED PAD SHALL BE SꢀLDER PLATED
6. SHADED AREA IS ꢀNLY A REFERENCE FꢀR PIN ± LꢀCATIꢀN
ꢀN THE TꢀP AND BꢀTTꢀM ꢀF PACKAGE
3708fb
Information fOrnished by Linear Technology Corporation is believed to be accOrate and reliable.
However, no responsibility is assOmed for its Ose. Linear Technology Corporation makes no representa-
tion that the interconnection of its circOits as described herein will not infringe on existing patent rights.
31
LTC3708
TYPICAL APPLICATION
Area = 650mm2, Height = 3mm
V
IN
7V Tꢀ 24V
5V
BAT54A
2.2μF
6.3V
5V
±0Ω
BꢀꢀST±
BꢀꢀST2
±μF
V
CC
C±±
±0μF
25V
C9
±0μF
25V
±μF
±μF
V
TRACK± FCB DRV
CC
CC
Q±A
Si48±6BDY
Q2A
Si48±6BDY
TG±
TG2
BꢀꢀST±
BꢀꢀST2
BꢀꢀST2
0.±μF
L±
±.8μH
L2
±.8μH
0.±μF
LTC3708EUH
V
V
ꢀUT2
ꢀUT±
2.5V
SW±
SW2
±.8V
5A
C±5
5A
+
+
SENSE±
BG±
SENSE2
C±6
+
C±3
±50μF
4V
+
C±
±50μF
4V
Q±B
Si48±6BDY
Q2B
Si48±6BDY
±00μF
6.3V
±00μF
6.3V
BG2
–
–
SENSE±
PGND±
SENSE2
PGND2
V
V
RNG±
RNG2
±M
750k
220pF
5V
I
I
V
V
IN
20k
±0k
220pF
±00k
IN
ꢀN±
ꢀN2
±00k
20k
±0k
3±.6k
±0k
V
CC
±000pF
±000pF
V
CC
±00k
V
V
FB2
FB±
TRACK2
EXTLPF
PGꢀꢀD
INTLPF
PGꢀꢀD
I
I
20k
TH±
TH2
5.±±k
20k
RUN/SS SGND SGND
±50pF
560pF
20k
±50pF
560pF
±5k
220pF
470pF
220pF
0.±μF
22nF
3708 TA06
SGND
RUN/SS
C±, C±3: SANYꢀ 4TPE±50MAZB
V
IN
C9, C±±: TAIYꢀ YUDEN TMK325BJ±06KM
C±5, C±6: TDK C3225X5R0J±07M
L±, L2: TꢀKꢀ FDV0630-±R8M
BAT54W
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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PolyPhase is a registered trademark of Linear Technology Corporation
3708fb
LT 1207 REV B • PRINTED IN USA
LinearTechnology Corporation
±630 McCarthy Blvd., Milpitas, CA 95035-74±7
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-±900 FAX: (408) 434-0507 www.linear.com
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