LTC3709EG_技术文档

LTC3709

TM

SENSE

Fast 2-Phase, No R

,

Synchronous DC/DC Controller

with Tracking/Sequencing

U

FEATURES

DESCRIPTIO

PolyPhase^TMValley Current Mode Controller

TheLTC^®3709isasingleoutput,dualphase,synchronous

step-down switching regulator. The controller uses a

constant on-time, valley current control architecture to

deliver very low duty cycles without requiring a sense

resistor. Operating frequency is selected by an external

resistor and is compensated for variations in input supply

voltage.Aninternalphase-lockedloopallowstheLTC3709

to be synchronized to an external clock.

■

Synchronizable to an External Clock with PLL

■

Coincident or Ratiometric Tracking

■

Sense Resistor Optional

■

2% to 90% Duty Cycle at 200kHz

■

t_ON(MIN)< 100ns

■

True Remote Sensing Differential Amplifier

■

High Efficiency at Both Light and Heavy Loads

■

Power Good Output Voltage Monitor

0.6V ±1% Reference

Adjustable Current Limit

A TRACK pin is provided for tracking or sequencing the

output voltage among several LTC3709 chips or an

LTC3709 and other DC/DC regulators. Soft-start is ac-

■

Programmable Soft-Start and Operating Frequency

Output Overvoltage Protection

Optional Short-Circuit Shutdown Timer

^{32-Lead (5mm ×}U^{5mm) QFN Package}

complished using an external timing capacitor.

■

Faultprotectionisprovidedbyanoutputovervoltagecom-

parator and an optional short-circuit shutdown timer. The

current limit level is user programmable. A wide supply

rangeallowsvoltagesashighas31Vtostepdownto0.6V.

, LTC and LT are registered trademarks of Linear Technology Corporation.

No RSENSE and PolyPhase are trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5481178, 6476589, 6144194, 5847554, 6177678,

6304066, 6580258, 6674274, 6462525, 6593724.

APPLICATIO S

■

Notebook Computers

Power Supply for DSP, ASIC, Graphic Processors

■

U

TYPICAL APPLICATIO

High Efficiency Dual Phase 1.5V/30A Step-Down Converter

1µF

PGND1

1µF

5V

PGND2

4.7µF

324k

10Ω

V

IN

4.5V TO 28V

10µF

35V

×3

1µF

V

DRV

I

47.5k

10k

CC

CC ON

TG1

Efficiency and Power Loss

HAT2168H

HAT2165H

TRACK

RNG

FCB

V

100

95

90

85

80

75

70

65

60

55

50

10

9

8

7

6

5

4

3

2

1

0

0.22µF

V

= 12V

IN

BOOST1

SW1

SENSE1

1.22µH

100k

+

0.1µF

PGOOD

EFFICIENCY

RUN/SS

BG1

–

EXTLPF

INTLPF

SENSE1

3.32k

PGND1

100nF

680pF

LTC3709

I

TH

V

IN

20k

HAT2168H

HAT2165H

SGND

TG2

BOOST2

SW2

POWER LOSS

0.22µF

10k

1.22µH

V

1.5V

30A

OUT

V

FB

+

DIFFOUT

SENSE2

15k

0.01

0.1

1

10

100

BG2

–

LOAD CURRENT (A)

330µF

2.5V

×4

+

V

OS

SENSE2

PGND2

+

3709 TA01b

OS

3709 TA01a

3709f

1

LTC3709

W W

U W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TOP VIEW

Input Supply Voltage (V_CC, DRV_CC) ............ 7V to –0.3V

Boosted Topside Driver Supply Voltage

(BOOST1, BOOST2) .................................. 37V to –0.3V

Switch Voltage (SW1, 2) ............................. 31V to –1V

SENSE1⁺, SENSE2⁺Voltages....................... 31V to –1V

SENSE1^–, SENSE2^–Voltages.................... 10V to –0.3V

32 31 30 29 28 27 26 25

–

RUN/SS

1

2

3

4

5

6

7

8

24 SENSE1

23 PGND1

I

TH

V

FB

BG1

DRV

22

21

I

_ONVoltage ............................................... 31V to –0.3V

TRACK

SGND

CC

33

(BOOST – SW) Voltages ..............................7V to –0.3V

RUN/SS, PGOOD Voltages.......................... 7V to –0.3V

TRACK Voltage ............................................7V to –0.3V

V_RNGVoltage ................................. V_CC+ 0.3V to –0.3V

20 BG2

PGND2

SGND

–

19

18 SENSE2

17

–

V

OS

DIFFOUT

V

CC

9

10 11 12 13 14 15 16

I_THVoltage............................................... 2.7V to –0.3V

V_FBVoltage .............................................. 2.7V to –0.3V

INTLPF, EXTLPF Voltages ........................ 2.7V to –0.3V

V_OS⁺, V_OS^–Voltages ................................... 7V to –0.3V

FCB Voltage ................................................ 7V to –0.3V

Operating Temperature Range ................ –40°C to 85°C

Junction Temperature (Note 2)............................ 125°C

Storage Temperature Range ................ –65°C to 125°C

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

EXPOSED PAD IS SGND (PIN 33)

MUST BE SOLDERED TO PCB

T_JMAX= 125°C, θ_JA= 34°C/ W

ORDER PART NUMBER

LTC3709EUH

UH PART MARKING

3709

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= DRV_CC= 5V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

I

Input DC Supply Current

Normal

Shutdown

Q

2.4

25

3

65

mA

µA

I

FB Pin Input Current

I

= 1.2V (Note 3)

–35

0.600

0.02

–60

nA

V

FB

TH

V

Feedback Voltage

= 1.2V (Note 3)

●

0.594

1.3

0.606

FB

∆V

Feedback Voltage Line Regulation

Feedback Voltage Load Regulation

Error Amplifier Transconductance

On-Time

V

= 4V to 6.5V (Note 3)

= 0.5V to 2V (Note 3)

= 1.2V (Note 3)

%/V

%

FB(LINEREG)

FB(LOADREG)

IN

TH

I

–0.12

1.45

–0.2

1.6

g

mS

m(EA)

t

V

= 20V, I = 180µA

90

180

116

233

140

280

ns

ON

IN

ON

= 20V, I = 90µA

ON

t

Minimum On-Time

Minimum Off-Time

V

= 20V, I = 540µA

45

100

350

ns

ON(MIN)

OFF(MIN)

IN

ON

= 20V, I = 90µA

250

ON

3709f

2

LTC3709

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= DRV_CC= 5V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Maximum Current Sense Threshold

V

= 1V

= 0V

124

86

177

144

101

202

166

119

234

mV

SENSE(MAX)

RNG

= V

CC

V

Minimum Current Sense Threshold

V

= 1V

= 0V

–60

–40

–80

mV

SENSE(MIN)

RNG

= V

CC

∆V

Overvoltage Fault Threshold

Undervoltage Fault Threshold

RUN Pin Start Threshold

8.5

–8.5

0.8

10

–10

1.4

3

12.5

–12.5

2

%

V

FB(OV)

FB(UV)

V

●

RUN/SS(ON)

RUN/SS(LE)

RUN/SS(LT)

RUN/SS(C)

RUN/SS(D)

RUN Pin Latchoff Enable Threshold

RUN Pin Latchoff Threshold

Soft-Start Charge Current

RUN/SS Pin Rising

RUN/SS Pin Falling

V

2.3

–1.2

2

V

I

–0.5

0.8

–3

4

µA

V

Soft-Start Discharge Current

Undervoltage Lockout

UVLO

Measured at V Pin

3.9

2

4.2

CC

TG R

BG R

TG Driver Pull-Up On-Resistance

TG Driver Pull-Down On-Resistance

BG Driver Pull-Up On-Resistance

BG Driver Pull-Down On-Resistance

TG High

TG Low

BG High

BG Low

Ω

UP

1.5

3

DOWN

UP

1.5

DOWN

Tracking

I

TRACK Pin Input Current

I

= 1.2V, V = 0.2V (Note 3)

TRACK

–100

–150

nA

TRACK

TH

V

Feedback Voltage at Tracking

V

= 0.1V, I = 1.2V (Note 3)

90

290

490

100

300

500

110

310

510

mV

FB(TRACK)

TRACK

TH

= 0.3V, I = 1.2V (Note 3)

TH

= 0.5V, I = 1.2V (Note 3)

TH

PGOOD Output

∆V

PGOOD Upper Threshold

PGOOD Lower Threshold

PGOOD Delay

V

Rising

8.5

–8.5

100

10

12.5

%

µs

%

µA

V

FBH

FBL

FB

Falling

–10

–12.5

FB

PG Delay

∆V

Falling

FB

PGOOD Hysteresis

Returning

3.5

0.2

FB(HYS)

FB

I

PGOOD Leakage Current

PGOOD Low Voltage

= 7V

±1

PGOOD

V

I

= 5mA

0.4

PGL

Phase-Lock Loop

I

Internal PLL Sourcing Current

Internal PLL Sinking Current

External PLL Sourcing Current

External PLL Sinking Current

Forced Continuous Threshold

Clock Input Threshold

20

–20

20

µA

V

INTPLL_SOURCE

INTPLL_SINK

EXTPLL_SOURCE

EXTPLL_SINK

–20

2.1

1.5

V

Measured with a DC Voltage at FCB Pin

Measured with a AC Pulse at FCB Pin

1.9

1

2.3

2

FCB(DC)

FCB(AC)

V

t

Modulation Range by External PLL

ON1

ON(PLL)1

Up Modulation

I

= 180µA, V

= 1.8V

= 0.6V

186

233

58

ns

ON1

EXTPLL

Down Modulation

80

t

Modulation Range by Internal PLL

ON2

Up Modulation

Down Modulation

ON(PLL)2

I

= 180µA, V

= 1.8V

= 0.6V

233

58

ns

ON2

INTPLL

3709f

3

LTC3709

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= DRV_CC= 5V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Differential Amplifier

A

V

Differential Gain

0.995

1.000

0.5

1.005

7

V/V

mV

V

+

–

Input Offset Voltage

IN = IN = 1.2V, I

= 1mA,

OS

OUT

Input Referred; Gain = 1

CM

Common Mode Input Voltage Range

Common Mode Rejection Ratio

I

= 1mA

0

5

V

OUT

+

–

CMRR

0V < IN = IN < 5V, I

Input Referred

= 1mA,

45

70

dB

OUT

I

Output Current

10

40

2

mA

MHz

V/µs

V

CL

GBP

SR

Gain Bandwidth Product

Slew Rate

I

= 1mA

OUT

R = 2k

5

L

V

Maximum High Output Voltage

Input Resistance

I

= 1mA

V

– 1.2 V – 0.8

O(MAX)

OUT

CC

+

R

Measured at IN Pin

80

kΩ

IN

Note 4: The LTC3709E is guaranteed to meet performance specifications

from 0°C to 70°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: T is calculated from the ambient temperature T and power

J

A

dissipation P as follows:

D

Note 5: R

test.

limit is guaranteed by design and/or correlation to static

DS(ON)

LTC3709EUH: T = T + (P • 34°C/W)

Note 3: The LTC3709 is tested in a feedback loop that adjusts V to

J

A

D

FB

achieve a specified error amplifier output voltage (I ).

TH

3709f

4

LTC3709

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Start-Up

Continuous Current Mode (CCM)

Discontinuous Current Mode (DCM)

V

RUN/SS

5V/DIV

V

OUT

1V/DIV

SW1

5V/DIV

SW1

5V/DIV

I

L1

10A/DIV

SW2

1V/DIV

SW2

5V/DIV

I

L2

10A/DIV

3709 G01

3709 G02

3709 G03

1ms/DIV

2µs/DIV

10µs/DIV

Transient Response (CCM)

Transient Response (DCM)

Efficiency vs Load Current

100

95

90

85

80

75

70

65

60

55

50

V

= 12V

IN

OUT

I

LOAD

3A-18A

= 1.5V

3A-18A

f = 220kHz

V

OUT

50mV/DIV

V

SW1

20V/DIV

SW1

20V/DIV

V

SW2

20V/DIV

3709 G04

3709 G05

20µs/DIV

10

100

1000

10000

100000

LOAD (mA)

3709 G06

Power Loss vs Load Current

Efficiency vs V_IN

Quiescent Current at V_CC= 5V

3.0

2.8

2.6

2.4

2.2

2.0

10

1

100

95

90

85

80

V

= 12V

V

I

= 1.5V

= 10A

IN

OUT

LOAD

f = 220kHz

= 1.5V

f = 220kHz

0.1

0.01

0.001

10

100

1000

10000

100000

–40

–20

0

20

40

60

80

4

8

12

16

(V)

20

24

LOAD CURRENT (mA)

TEMPERATURE (°C)

V

IN

3709 G07

3709 G09

3709 G08

3709f

5

LTC3709

TYPICAL PERFOR A CE CHARACTERISTICS

U W

Shutdown Current at V_CC= 5V

Error Amplifier g_m

EA Load Regulation

45

40

35

30

25

20

15

1.6

1.5

1.4

1.3

1.2

0.4

0.3

0.2

0.1

0

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

3709 G10

3709 G11

3709 G12

V_FBPin Input Current

RUN/SS Threshold

Armed Threshold

–20

–25

–30

–35

–40

–45

–50

1.8

1.6

1.4

1.2

1.0

0.8

4.0

3.5

3.0

2.5

2.0

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

3709 G13

3709 G14

3709 G15

Current Sense Threshold

vs I_THVoltage

UVLO Threshold

On-Time vs I_ONCurrent

4.5

4.3

4.1

3.9

3.7

3.5

300

250

200

150

100

50

10000

1000

100

V

= 2V

RNG

V

= V

RNG

CC

V

= 1V

RNG

V

= 0V

RNG

V

= 0.5V

RNG

1.8

0

–50

–100

–150

10

1.2

VOLTAGE (V)

0

0.6

2.4

–40

–20

0

20

40

60

80

10

100

1000

I

CURRENT (µA)

I

TH

TEMPERATURE (°C)

ON

3709 G17

3709 G18

3709 G16

3709f

6

LTC3709

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Maximum Current Sense

Threshold Voltage vs V_RNG

Minimum Current Sense

Threshold Voltage vs V_RNG

350

0

300

–20

250

200

150

100

50

–40

–60

–80

–100

–120

–140

0

0.5

0.8

1.1

V

1.4

(V)

2.0

0.8

1.1

V

1.4

(V)

2.0

1.7

0.5

1.7

RNG

3709 G19

3709 G20

U

PI FU CTIO S

RUN/SS (Pin 1): Run Control and Soft-Start Input. A ca-

pacitor to ground at this pin sets the ramp rate of the out-

put voltage (approximately 0.5s/µF) and the time delay for

overcurrentlatch-off(seeApplicationsInformation).Forc-

ing this pin below 1.4V shuts down the device.

SGND (Pins 5, 6, 33): Signal Ground. All small-signal

components such as C_SSand compensation components

should connect to this ground and eventually connect to

PGND at one point. The Exposed Pad of the QFN package

must be soldered to PCB ground.

I_TH(Pin 2): Error Amplifier Compensation Point. The

current comparator threshold increases with this control

voltage. The voltage ranges from 0V to 2.4V with 0.8V

corresponding to zero sense voltage (zero current).

V_OS^–(Pin 7): The (–) Input to the Differential Amplifer.

DIFFOUT (Pin 8): The Output of the Differential Amplifier.

V_OS⁺(Pin 9): The (+) Input to the Differential Amplifier.

EXTLPF (Pin 10): Filter Connection for the PLL. This PLL

V_FB(Pin 3): Error Amplifier Feedback Input. This pin

connects to the error amplifier input. It can be used to

attach additional compensation components if desired.

isusedtosynchronizetheLTC3709withanexternalclock.

INTLPF (Pin 11): Filter Connection for the PLL. This PLL

isusetophaseshiftthesecondchanneltothefirstchannel

by 180°.

TRACK (Pin 4): Tie the TRACK pin to a resistive divider

connected to the output of another LTC3709 for either

coincident or ratiometric output tracking (see Applica-

tions Information). To disable this feature, tie the pin to

V_CC. Do Not Float this pin.

NC (Pin 12): No Connect.

3709f

7

LTC3709

U

PI FU CTIO S

V_CC(Pin 17): Main Input Supply. Decouple this pin to

BOOST1, BOOST2 (Pins 28, 13): Boosted Floating Driver

Supply. The (+) terminal of the bootstrap capacitor C_B

connects here. This pin swings from a diode voltage drop

below DRV_CCup to V_IN+ DRV_CC.

SGND with an RC filter (1Ω, 0.1µF).

DRV_CC(Pin 21): Driver Supply. Provides supply to the

driver for the bottom gate. Also used for charging the

bootstrap capacitor.

PGOOD (Pin 29): Power Good Output. Open-drain logic

output that is pulled to ground when output voltage is not

within ±10% of the regulation point. The output voltage

must be out of regulation for at least 100µs before the

power good output is pulled to ground.

BG1, BG2 (Pins 22, 20): Bottom Gate Drive. Drives the

gate of the bottom N-channel MOSFET between ground

and DRV_CC.

PGND1,PGND2(Pins23,19):PowerGround.Connectthis

pincloselytothesourceofthebottomN-channelMOSFET,

the (–) terminal of C_DRVCCand the (–) terminal of C_IN.

SENSE1^–, SENSE2^–(Pins 24, 18): Current Sense Com-

parator Input. The (–) input to the current comparator is

used to accurately Kelvin sense the bottom side of the

sense resistor or MOSFET.

SENSE1⁺, SENSE2⁺(Pins 25, 16): Current Sense Com-

parator Input. The (+) input to the current comparator is

normally connected to the SW node unless using a sense

resistor (see Applications Information).

I

_ON(Pin 30): On-Time Current Input. Tie a resistor from

V_INtothispintosettheone-shottimercurrentandthereby

set the switching frequency.

FCB (Pin 31): Forced Continuous and External Clock

Input. Tie this pin to ground to force continuous synchro-

nous operation or to V_CCto enable discontinuous mode

operation at light load. Feeding an external clock signal

into this pin will synchronize the LTC3709 to the external

clock and enable forced continuous mode.

V_RNG(Pin 32): Sense Voltage Range Input. The voltage at

thispinistentimesthenominalsensevoltageatmaximum

output current and can be programmed from 0.5V to 2V.

The sense voltage defaults to 70mV when this pin is tied

to ground, 140mV when tied to V_CC.

SW1, SW2 (Pins 26, 15): Switch Node. The (–) terminal

of the bootstrap capacitor C_Bconnects here. This pin

swings from a Schottky diode voltage drop below ground

up to V_IN.

TG1, TG2 (Pins 27, 14): Top Gate Drive. Drives the top

N-channel MOSFET with a voltage swing equal to DRV_CC

superimposed on the switch node voltage SW.

3709f

8

LTC3709

U

W

FU CTIO AL DIAGRA

I

ON

INTLPF

R

ON

V

IN

+

FCB

C

IN

CLOCK DETECTOR

V

CC

0.6V

REF

FROM CHANNEL 2

TG

+

C

VCC

EXTLPF

PLL2

PLL1

BOOST

TO CHANNEL 2 OST

C

TG

B

OST

0.7

ION

FCNT

ON

M1

R

S

t

=

(30pF)

ON

I

Q

SW

L1

V

+

OUT

D

SWITCH

LOGIC

B

SENSE

20k

+

–

+

5V

C

OUT

DRV

CC

I

CMP

REV

–

SHDN

OV

C

DRVCC

BG

DUPLICATE FOR

M2

SECOND CHANNEL

PGND

SENSE

1.4V

–

SHDN TO

V

RNG

CHANNEL 2

SWITCH LOGIC

×

0.7V

–

3.3µA

0.66V

R2

OV

UV

V

FB

+

–

+

R1

1

240k

SGND

EA

Q4

–

+

I

TH

PGOOD

C

0.54V

R

C

100µs

BLANKING

SHED

40k

+

RUN

SHDN

V

OS

DISABLE

40k

I

+

–

THB

DIFFOUT

1.2µA

–

TRACK

6V

OS

40k

Q1 Q2

0.6V Q3

REF

+

–

1.4V

V

RUN/SS

1.4V

C

SS

+

–

3709 FD

3709f

9

LTC3709

U

(Refer to Functional Diagram)

OPERATIO

MAIN CONTROL LOOP

holdingthefrequencyapproximatelyconstantwithchanges

in V_IN. The nominal frequency can be adjusted with an

external resistor R_ON.

The LTC3709 is a constant on-time, current mode step-

down controller with two channels operating 180 degrees

out of phase. In normal operation, each top MOSFET is

turned on for a fixed interval determined by its own one-

shot timer OST. When the top MOSFET is turned off, the

bottom MOSFET is turned on until the current comparator

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient

overshoots (>10%) as well as other more serious condi-

tions that may overvoltage the output. In this condition,

the top MOSFET is turned off and the bottom MOSFET is

turned on and held on until the condition is cleared.

I_CMPtrips, restarting the one-shot timer and repeating the

cycle. The trip level of the current comparator is set by the

I_THvoltage, which is the output of error amplifier EA.

Inductor current is determined by sensing the voltage

between the SENSE^–and SENSE⁺pins using either the

bottom MOSFET on-resistance or a separate sense resis-

tor. At light load, the inductor current can drop to zero and

become negative. This is detected by current reversal

comparatorI_REV,whichthenshutsoffthebottomMOSFET,

resulting in discontinuous operation. Both switches will

remain off with the output capacitor supplying the load

current until the I_THvoltage rises above the zero current

level (0.8V) to initiate another cycle. Discontinuous mode

operation is disabled when the FCB pin is tied to ground,

forcing continuous synchronous operation.

Power Good (PGOOD) Pin

Overvoltage and undervoltage comparators OV and UV

pull the PGOOD output low if the output feedback voltage

exits a ±10% window around the regulation point. In

addition, the output feedback voltage must be out of this

window for a continuous duration of at least 100µs before

the PGOOD is pulled low. This is to prevent any glitch on

the feedback voltage from creating a false power bad

signal.ThePGOODwillindicateagoodpowerimmediately

when the feedback voltage is in regulation.

Short-Circuit Detection and Protection

The main control loop is shut down by pulling the RUN/SS

pinlow,turningoffbothtopMOSFETandbottomMOSFET.

Releasing the pin allows an internal 1.2µA current source

to charge an external soft-start capacitor C_SS. When this

voltage reaches 1.4V, the LTC3709 turns on and begins

operating with a clamp on the noninverting input of the

error amplifier. This input is also the reference input of the

error amplifier. As the voltage on RUN/SS continues to

rise, the voltage on the reference input also rises at the

same rate, effectively controlling output voltage slew rate.

After the controller has been started and been given

adequatetimetochargetheoutputcapacitor,theRUN/SS

capacitor is used in a short-circuit time-out circuit. If the

output voltage falls to less than 67% of its nominal output

voltage, the RUN/SS capacitor begins discharging on the

assumption that the output is in an overcurrent and/or

short-circuit condition. If the condition lasts for a long

enough period, as determined by the size of the RUN/SS

capacitor, the controller will be shut down until the

RUN/SS pin voltage is recycled. This built-in latch off can

be overridden by providing a >5µA pull-up at a compli-

ance of 5V to the RUN/SS pin. This current shortens the

soft-start period but also prevents net discharge of the

RUN/SS capacitor during an overcurrent and/or short-

circuit condition.

Operating Frequency

The operating frequency is determined implicitly by the

top MOSFET on time and the duty cycle required to

maintain regulation. The one-shot timer generates an on-

time that is proportional to the ideal duty cycle, thus

3709f

10

LTC3709

U

(Refer to Functional Diagram)

OPERATIO

DRV_CC

Dual Phase Operation

An internal phase-lock loop (PLL1) ensures that channel

2 operates exactly at the same frequency as channel 1 and

is also phase shifted by 180°, enabling the LTC3709 to

operateoptimallyasadualphasecontroller. Theloopfilter

connected to the INTLPF pin provides stability to the PLL.

For external clock synchronization, a second PLL (PLL2)

is incorporated into the LTC3709. PLL2 will adjust the on-

time of channel 1 until its frequency is the same as the

external clock. When locked, the PLL2 aligns the turn on

of the top MOSFET of channel 1 to the rising edge of the

external clock. Compensation for PLL2 is through the

EXTLPF pin.

Power for the top and bottom MOSFET drivers and most

of the internal controller circuitry is derived from the

DRV_CCpin. The top MOSFET driver is powered from a

floating bootstrap capacitor C_B. This capacitor is normally

recharged from DRV_CCthrough an external Schottky di-

ode D_Bwhen the top MOSFET is turned off.

Differential Amplifier

This amplifier provides true differential output voltage

sensing. Sensing both V_OUT⁺and V_OUT^–benefits regula-

tion in high current applications and/or applications hav-

ing electrical interconnection losses. This sensing also

isolates the physical power ground from the physical

signal ground, preventing the possibility of troublesome

“ground loops” on the PC layout and preventing voltage

errors caused by board-to-board interconnects.

Second Channel Shutdown During Light Loads

When FCB is tied to V_CC, discontinuous mode is selected.

In this mode, no reverse current is allowed. The second

channel is off when I_THis less than 0.8V for better

efficiency. When FCB is tied to ground, forced continuous

mode is selected, both channels are on and reversed

current is allowed.

3709f

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LTC3709

APPLICATIO S I FOR ATIO

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The basic LTC3709 application circuit is shown on the this resistor, connect the SENSE⁺pin to the source end of

first page of this data sheet. External component selec- the resistor and the SENSE^–pin to the other end of the

tion is primarily determined by the maximum load cur- resistor. The SENSE⁺and SENSE^–pin connections pro-

rent and begins with the selection of the power MOSFET vide the Kelvin connections, ensuring accurate voltage

switches and/or sense resistor. The inductor current is measurement across the resistor. Using a sense resistor

determined by the R_DS(ON)of the synchronous MOSFET provides a well-defined current limit, but adds cost and

while the user has the option to use a sense resistor for reduces efficiency. Alternatively, one can use the synchro-

a more accurate current limiting. The desired amount of nous MOSFET as the current sense element by simply

ripple current and operating frequency largely deter- connecting the SENSE⁺pin to the switch node SW and the

mines the inductor value. Finally, C_INis selected for its SENSE^–pin to the source of the synchronous MOSFET,

ability to handle the large RMS current into the converter eliminating the sense resistor. This improves efficiency,

and C_OUTis chosen with low enough ESR to meet the but one must carefully choose the MOSFET on-resistance

output voltage ripple specification.

as discussed in the Power MOSFET Selection section.

Maximum Sense Voltage and V_RNGPin

Power MOSFET Selection

Inductor current is determined by measuring the voltage The LTC3709 requires four external N-channel power

acrosstheR_DS(ON)ofthesynchronousMOSFETorthrough MOSFETs, two for the top (main) switches and two for the

a sense resistance that appears between the SENSE^–and bottom (synchronous) switches. Important parameters

theSENSE⁺pins.Themaximumsensevoltageissetbythe for the power MOSFETs are the breakdown voltage

voltage applied to the V_RNGpin and is equal to approxi- V_(BR)DSS,thresholdvoltageV_(GS)TH,on-resistanceR_DS(ON)

,

mately V_RNG/7.5. The current mode control loop will not reverse transfer capacitance C_RSSand maximum current

allow the inductor current valleys to exceed V_RNG/(7.5 • I_DS(MAX)

R_SENSE). In practice, one should allow some margin for

.

The gate drive voltage is set by the 5V DRV_CCsupply.

Consequently, logic-level threshold MOSFETs must be

used in LTC3709 applications. If the driver’s voltage is

expected to drop below 5V, then sub-logic level threshold

MOSFETs should be used.

variationsintheLTC3709andexternalcomponentvalues.

A good guide for selecting the sense resistance for each

channel is:

2 • V_RNG

10 •I_OUT(MAX)

R_SENSE

=

When the bottom MOSFETs are used as the current sense

elements, particular attention must be paid to their on-

resistance. MOSFET on-resistance is typically specified

with a maximum value R_DS(ON)(MAX)at 25°C. In this case

additional margin is required to accommodate the rise in

MOSFET on-resistance with temperature:

The voltage of the V_RNGpin can be set using an external

resistive divider from V_CCbetween 0.5V and 2V resulting

in nominal sense voltages of 50mV to 200mV. Addition-

ally, the V_RNGpin can be tied to ground or V_CC, in which

case the nominal sense voltage defaults to 70mV or

140mV, respectively. The maximum allowed sense volt-

age is about 1.3 times this nominal value.

R_SENSE

R_DS(ON)(MAX)

=

ρ_T

Connecting the SENSE⁺and SENSE^–Pins

The ρ_Tterm is a normalization factor (unity at 25°C)

accounting for the significant variation in on-resistance

with temperature, typically about 0.4%/°C. Junction-to-

case temperature is about 20°C in most applications. For

a maximum junction temperature of 100°C, using a value

ρ_100°C= 1.3 is reasonable (Figure 1).

TheLTC3709providestheuserwithanoptionalmethodto

sensecurrentthroughasenseresistorinsteadofusingthe

R_DS(ON)ofthesynchronousMOSFET. Whenusingasense

resistor, it is placed between the source of the synchro-

nous MOSFET and ground. To measure the voltage across

3709f

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U

bottom MOSFET losses are the greatest when the bottom

duty cycle is near 100%, during a short circuit or at high

input voltage. A much smaller and much lower input

capacitance MOSFET should be used for the top MOSFET

in applications that have an output voltage that is less than

2.0

1.5

1.0

0.5

0

1/3oftheinputvoltage. InapplicationswhereV_IN>>V_OUT

,

the top MOSFETs’ “on” resistance is normally less impor-

tant for overall efficiency than its input capacitance at

operating frequencies above 300kHz. MOSFET manufac-

turers have designed special purpose devices that provide

reasonably low “on” resistance with significantly reduced

inputcapacitanceforthemainswitchapplicationinswitch-

ing regulators.

50

100

–50

150

0

JUNCTION TEMPERATURE (°C)

3709 F01

Figure 1. R_DS(ON)vs Temperature

Operating Frequency

The power dissipated by the top and bottom MOSFETs

strongly depends upon their respective duty cycles and

the load current. When the LTC3709 is operating in

continuous mode, the duty cycles for the MOSFETs are:

The choice of operating frequency is a tradeoff between

efficiency and component size. Low frequency operation

improvesefficiencybyreducingMOSFETswitchinglosses

butrequireslargerinductanceand/orcapacitancetomain-

tain low output ripple voltage.

V_OUT

D_TOP

D_BOT

=

TheoperatingfrequencyofLTC3709applicationsisdeter-

mined implicitly by the one-shot timer that controls the on

time, t_ON, of the top MOSFET switch. The on-time is set by

the current into the I_ONpin according to:

V

IN

V – V_OUT

IN

V

IN

The maximum power dissipation in the MOSFETs per

channel is:

0.7

I_ION

t_ON

=

30pF

(

)

2

Tying a resistor from V_INto the I_ONpin yields an on-time

inversely proportional to V_IN. For a down converter, this

results in approximately constant frequency operation as

the input supply varies:

I

⎛

⎞

OUT(MAX)

P

_TOP= D_TOP

•

• ρ_T(TOP)•R_DS(ON)(MAX)+

⎜

⎟

2

⎝

⎠

I

⎛

⎜

⎝

⎞

⎠

2

OUT

2

(0.5)• V

•

•C_RSS• f •

⎟

IN

V_OUT

f =

⎛

⎞

⎟

⎠

1

0.7 •R_ON30pF

(

)

R_{DS(ON)_DRV}

+

⎜

⎝

V_GS(TH)

DRV – V

(

)

CC

GS(TH)

PLL and Frequency Synchronization

2

I

⎛

⎞

OUT(MAX)

In the LTC3709, there are two on-chip phase-lock loops

(PLLs). One of the PLLs is used to achieve frequency

locking and phase separation between the two channels

while the second PLL is for locking onto an external clock.

Since the LTC3709 is a constant on-time architecture, the

error signal generated by the phase detector of the PLL is

P_BOT= D_BOT

•

• ρ_T(BOT)•R_DS(ON)(MAX)

⎜

⎟

2

⎝

⎠

BothtopandbottomMOSFETshaveI²Rlossesandthetop

MOSFET includes an additional term for transition losses,

which are the largest at maximum input voltages. The

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APPLICATIO S I FOR ATIO

used to vary the on-time to achieve frequency locking and

180° phase separation.

ripple current does not exceed a specified maximum, the

inductance should be chosen according to:

The synchronization is set up in a “daisy chain” manner

whereby channel 2’s on-time will be varied with respect to

channel 1. If an external clock is present, then channel 1’s

on-time will be varied and channel 2 will follow suit. Both

PLLs are set up with the same capture range and the fre-

quencyrangethattheLTC3709canbeexternallysynchro-

nized to is between 2 • f_Cand 0.5 • f_C, where f_Cis the initial

frequency setting of the two channels. It is advisable to set

initialfrequencyasclosetoexternalfrequencyaspossible.

⎛

⎞⎛

⎞

V_OUT

f • ∆I

V_OUT

L =

1–

⎜

⎟⎜

⎟

V

⎝

⎠⎝

⎠

L(MAX)

IN(MAX)

Once the value for L is known, the inductors must be

selected (based on the RMS saturation current ratings). A

variety of inductors designed for high current, low voltage

applications are available from manufacturers such as

Sumida, Toko and Panasonic.

AlimitationofbothPLLsiswhentheon-timeisclosetothe

minimum (100ns). In this situation, the PLL will not be

able to synchronize up in frequency.

Schottky Diode Selection

The Schottky diodes conduct during the dead time be-

tween the conduction of the power MOSFET switches. It is

intended to prevent the body diode of the bottom MOSFET

from turning on and storing charge during the dead time,

which causes a modest (about 1%) efficiency loss. The

diode can be rated for about one-half to one-fifth of the full

load current since it is on for only a fraction of the duty

cycle. In order for the diode to be effective, the inductance

between the diode and the bottom MOSFET must be as

small as possible, mandating that these components be

placed adjacently. The diode can be omitted if the effi-

ciency loss is tolerable.

Toensureproperoperationoftheinternalphase-lockloop

when no external clock is applied to the FCB pin, the

INTLPF pin may need to be pulled down while the output

voltage is ramping up. One way to do this is to connect the

anode of a silicon diode to the INTLPF pin and its cathode

to the PGOOD pin and connect a pull-up resistor between

the PGOOD pin and V_CC. Refer to Figure 9 for an example.

Inductor Selection

Given the desired input and output voltages, the inductor

valueandoperatingfrequencydeterminetheripplecurrent:

C_INand C_OUTSelection

V

⎛

⎞

V_OUT

V

IN

⎞

⎛

⎜

⎝

OUT

In continuous mode, the current of each top N-channel

MOSFET is a square wave of duty cycle V_OUT/V_IN. A low

ESR input capacitor sized for the maximum RMS current

must be used. The details of a close form equation can be

found in Application Note 77. Figure 2 shows the input

capacitor ripple current for a 2-phase configuration with

theoutputvoltagefixedandinputvoltagevaried. Theinput

ripple current is normalized against the DC output current.

Thegraphcanbeusedinplaceoftediouscalculations.The

minimum input ripple current can be achieved when the

input voltage is twice the output voltage.

∆I =

L

1–

⎟

⎜

⎟

⎠

f •L ⎝

⎠

Lower ripple current reduces core losses in the inductor,

ESR losses in the output capacitors and output voltage

ripple. Highest efficiency operation is obtained at low

frequency with small ripple current. However, achieving

this requires a large inductor. There is a tradeoff between

component size, efficiency and operating frequency.

A reasonable starting point is to choose a ripple current

that is about 40% of I_OUT(MAX)/2. Note that the largest

ripple current occurs at the highest V_IN. To guarantee that

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In the Figure 2 graph, the local maximum input RMS

The selection of C_OUTis primarily determined by the ESR

requiredtominimizevoltagerippleandloadsteptransients.

The output ripple ∆V_OUTis approximately bounded by:

capacitor currents are reached when:

V_OUT2k – 1

=

where k = 1, 2

⎛

1

⎞

V

4

IN

∆V_OUT≤ ∆I ESR +

⎜

⎟

L

⎝

8fC_OUT

⎠

These worst-case conditions are commonly used for

design because even significant deviations do not offer

muchrelief.Notethatripplecurrentratingsfromcapacitor

manufacturers are often based on only 2000 hours of life

which makes it advisable to derate the capacitor. Several

capacitors may also be paralleled to meet size or height

requirements in the design. Always consult the capacitor

manufacturer if there is any question.

Since ∆I_Lincreases with input voltage, the output ripple is

highestatmaximuminputvoltage.Typically,oncetheESR

requirement is satisfied, the capacitance is adequate for

filtering and has the necessary RMS current rating.

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic and

ceramic capacitors are all available in surface mount

packages. Special polymer capacitors offer very low ESR

but have lower capacitance density than other types.

Tantalum capacitors have the highest capacitance density

but it is important to only use types that have been surge

tested for use in switching power supplies. Aluminum

electrolytic capacitors have significantly higher ESR, but

can be used in cost-sensitive applications providing that

consideration is given to ripple current ratings and long-

term reliability. Ceramic capacitors have excellent low

ESRcharacteristicsbutcanhaveahighvoltagecoefficient

and audible piezoelectric effects. High performance

through-hole capacitors may also be used, but an addi-

tional ceramic capacitor in parallel is recommended to

reduce the effect of their lead inductance.

It is important to note that the efficiency loss is propor-

tional to the input RMS current squared and therefore a

2-stage implementation results in 75% less power loss

when compared to a single phase design. Battery/input

protection fuse resistance (if used), PC board trace and

connector resistance losses are also reduced by the re-

ductionoftheinputripplecurrentina2-phasesystem.The

requiredamountofinputcapacitanceisfurtherreducedby

the factor 2 due to the effective increase in the frequency

of the current pulses.

0.6

0.5

0.4

1-PHASE

2-PHASE

0.3

Top MOSFET Driver Supply (C_B, D_B)

0.2

0.1

AnexternalbootstrapcapacitorC_BconnectedtotheBOOST

pinsuppliesthegatedrivevoltageforthetopsideMOSFET.

This capacitor is charged through diode D_Bfrom DRV_CC

when the switch node is low. Note that the average voltage

acrossC_BisapproximatelyDRV_CC. WhenthetopMOSFET

turns on, the switch node rises to V_INand the BOOST pin

rises to approximately V_IN+ DRV_CC. The boost capacitor

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

3709 F02

Figure 2. RMS Input Current Comparison

3709f

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needstostoreabout100timesthegatechargerequiredby

the top MOSFET. In most applications 0.1µF to 0.47µF is

adequate.

generally occurs with the largest V_INat the highest ambi-

enttemperature,conditionswhichcausethelargestpower

loss in the converter. Note that it is important to check for

self-consistency between the assumed junction tempera-

ture and the resulting value of I_LIMIT, which heats the

junction.

Discontinuous Mode Operation and FCB Pin

The FCB pin determines whether the bottom MOSFET

remains on when current reverses in the inductor. Tying

this pin to V_CCenables discontinuous operation where the

bottomMOSFETturnsoffwheninductorcurrentreverses.

The load current at which inductor current reverses and

discontinuousoperationbeginsdependsontheamplitude

of the inductor ripple current. The ripple current depends

onthechoiceofinductorvalueandoperatingfrequencyas

well as the input and output voltages.

Cautionshouldbeusedwhensettingthecurrentlimitbased

upon the R_DS(ON)of the MOSFETs. The maximum current

limitisdeterminedbytheminimumMOSFETon-resistance.

Datasheetstypicallyspecifynominalandmaximumvalues

for R_DS(ON), but not a minimum. A reasonable assumption

is that the minimum R_DS(ON)lies the same amount below

the typical value as the maximum lies above it. Consult the

MOSFET manufacturer for further guidelines.

Tying the FCB pin to ground forces continuous synchro-

nous operation, allowing current to reverse at light loads

and maintaining high frequency operation.

For a more accurate current limiting, a sense resistor can

be used. Sense resistors in the 1W power range are easily

available with 5%, 2% or 1% tolerance. The temperature

coefficient of these resistors are very low, ranging from

±250ppm/°C to ±75ppm/°C. In this case, the denomina-

tor in the above equation can simply be replaced by the

Besides providing a logic input to force continuous opera-

tion, the FCB pin acts as the input for external clock syn-

chronization. Upon detecting a TTL level clock and the fre-

quency is higher than the minimum allowable, channel 1

will lock on to this external clock. This will be followed by

channel 2 (see PLL and Frequency Synchronization). The

LTC3709 will be forced to operate in forced continuous

mode in this situation.

R_SENSEvalue.

Minimum Off-Time and Dropout Operation

The minimum off-time t_OFF(MIN)is the smallest amount of

time that the LTC3709 is capable of turning on the bottom

MOSFET, tripping the current comparator and turning the

MOSFET back off. This time is generally about 250ns. The

minimum off-time limit imposes a maximum duty cycle of

t_ON/(t_ON+t_OFF(MIN)).Ifthemaximumdutycycleisreached,

due to a dropping input voltage for example, then the

output will drop out of regulation in order to maintain the

duty cycle at its limit. The minimum input voltage to avoid

dropout is:

Fault Conditions: Current Limit

The maximum inductor current is inherently limited in a

currentmodecontrollerbythemaximumsensevoltage.In

the LTC3709, the maximum sense voltage is controlled by

the voltage on the V_RNGpin. With valley current control,

the maximum sense voltage and the sense resistance

determine the maximum allowed inductor valley current.

The corresponding output current limit is:

1

V_IN(MIN)= V_OUT

1– t_OFF(MIN)•f

⎛

⎞

V_SNS(MAX)

1

2

I_LIMIT

=

+ • ∆I_L• 2

⎟

⎜

A plot of maximum duty cycle vs frequency is shown in

Figure 3.

R_DS(ON)• ρ_T

⎝

⎠

The current limit value should be checked to ensure that

I_LIMIT(MIN)>I_OUT(MAX).Theminimumvalueofcurrentlimit

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U

2.0

1.5

1.0

0.5

0

RUN/SS

∆V = 0.6V

DROPOUT

REGION

ON THRESHOLD

TIME

V

OUT1

TIME

3709 F04

0

0.25

0.50

0.75

1.0

DUTY CYCLE (V /V

)

OUT IN

3709 F03

Figure 4. Monotonic Soft-Start Waveforms

Figure 3. Maximum Switching Frequency vs Duty Cycle

Soft-Start and Latchoff with the RUN/SS Pin

if the output voltage falls below 67% of its regulated value,

then a short-circuit fault is assumed. A 2µA current then

beginsdischargingC_SS. Ifthefaultconditionpersistsuntil

the RUN/SS pin drops to 2.5V, then the controller turns off

both power MOSFETs, shutting down the converter per-

manently. The RUN/SS pin must be actively pulled down

to ground in order to restart operation.

The RUN/SS pin provides a means to shut down the

LTC3709 as well as a timer for soft-start and overcurrent

latchoff.

Pulling the RUN/SS pin below 1.4V puts the LTC3709 into

a low quiescent current shutdown (I_Q< 30µA). Releasing

the pin allows an internal 1.2µA internal current source to

charge the external capacitor C_SS. If RUN/SS has been

pulledallthewaytoground, thereisadelaybeforestarting

of about:

The overcurrent protection timer requires that the soft-

start timing capacitor C_SSbe made large enough to guar-

antee that the output is in regulation by the time C_SShas

reachedthe3Vthreshold.Ingeneral,thiswilldependupon

the size of the output capacitance, output voltage and load

currentcharacteristic.Aminimumsoft-startcapacitorcan

be estimated from:

1.4V

1.2µA

t_DELAY

=

•C_SS= 1.2s/µF C

SS

(

)

When the RUN/SS voltage reaches the ON threshold

(typically 1.4V), the LTC3709 begins operating with a

clamponEA’sreferencevoltage.TheclamplevelisoneON

thresholdvoltagebelowRUN/SS.AsthevoltageonRUN/SS

continues to rise, EA’s reference is raised at the same rate,

achieving monotonic output voltage soft-start (Figure 4).

When RUN/SS rises 0.6V above the ON threshold, the

reference clamp is invalidated and the internal precision

reference takes over.

C_SS> C_OUTV_OUTR_SENSE(10^–4[F/V_S])

Overcurrent latchoff operation is not always needed or

desired and can prove annoying during troubleshooting.

The feature can be overridden by adding a pull-up current

of >5µA to the RUN/SS pin. The additional current pre-

vents the discharge of C_SSduring a fault and also shortens

the soft-start period. Using a resistor to V_INas shown in

Figure 5 is simple, but slightly increases shutdown cur-

rent. Any pull-up network must be able to pull RUN/SS

above the 3V threshold that arms the latchoff circuit and

overcome the 2µA maximum discharge current.

After the controller has been started and given adequate

timetochargetheoutputcapacitor, C_SSisusedasashort-

circuit timer. After the RUN/SS pin charges above 3V, and

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APPLICATIO S I FOR ATIO

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V

CC

tobethesameasthedivideracrosssupply2’soutput. The

TRACK pin of supply 2 is connected to this extra resistor

divider. For the ratiometric tracking, simply connect the

TRACK pin of supply 2 to the V_FBpin of supply 1. Figure 7

shows this implementation. Note that in the coincident

tracking, output voltage of supply 1 has to be set higher

than output voltage of supply 2.

R

*

SS

V

IN

RUN/SS

3.3V OR 5V

RUN/SS

*

D2*

R

SS

D1

2N7002

C

SS

C

SS

3709 F05

*OPTIONAL TO OVERRIDE

OVERCURRENT LATCHOFF

Note that since the shutdown trip point varies from part to

part, the “slave” part’s RUN/SS pin will need to be con-

nected to V_CC. This eliminates the possibility that different

LTC3709s may shut down at different times.

(5a)

(5b)

Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated

If output sequencing is not needed, connect the TRACK

pins to V_CC. Do Not Float these pins.

Output Voltage Tracking

The feedback voltage, V_FB, will follow the TRACK pin

voltage when the TRACK pin voltage is less than the

reference voltage, V_REF(0.6V). When the TRACK pin

voltage is greater than V_REF, the feedback voltage will

servo to V_REF. When selecting components for the TRACK

pin, ensurethefinalsteady-statevoltageontheTRACKpin

is greater than V_REFat the end of the tracking interval.

SUPPLY 1

SUPPLY 2

LTC3709

V

OUT2

OUT1

R5

R6

R1

R2

R3

V

FB

V

TRACK

FB

R4

3709 F07

R3 R5

=

The LTC3709 allows the user to set up start-up sequenc-

ing among different supplies in either coincident tracking

orratiometrictrackingasshowninFigure6. Toimplement

the coincident tracking, connect an extra resistor divider

to the output of supply 1. This resistor divider is selected

V

COINCIDENTLY TRACKS V

OUT1

OUT2

R4 R6

R3 R1 RATIOMETRIC POWER UP

=

R4 R2 BETWEEN V

AND V

OUT1

OUT2

Figure 7. Setup for Coincident and Ratiometric Tracking

V

OUT1

OUT2

OUT1

OUT2

3709 F06

TIME

(6a) Coincident Tracking

(6b) Ratiometric Tracking

Figure 6. Two Different Forms of Output Voltage Sequencing

3709f

18

LTC3709

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APPLICATIO S I FOR ATIO

U

Efficiency Considerations

causing additional upstream losses in fuses or batteries.

Other losses, including C_OUTESR loss, Schottky conduc-

tionlossduringdeadtimeandinductorcorelossgenerally

account for less than 2% additional loss.

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement.

When making any adjustments to improve efficiency, the

final arbiter is the total input current for the regulator at

your operating point. If you make a change and the input

current decreases, then you improved the efficiency. If

thereisnochangeininputcurrent, thenthereisnochange

in efficiency.

Although all dissipative elements in the circuit produce

losses, four main sources account for most of the losses

in LTC3709 circuits:

1. DC I²R losses. These arise from the resistances of the

MOSFETs, inductor and PC board traces and cause the

efficiency to drop at high output currents. In continuous

mode the average output current flows through L, but is

chopped between the top and bottom MOSFETs. If the two

MOSFETs have approximately the same R_DS(ON), then the

resistanceofoneMOSFETcansimplybesummedwiththe

resistances of L and the board traces to obtain the DC I²R

loss.Forexample,ifR_DS(ON)=0.01ΩandR_L=0.005Ω,the

loss will range from 0.1% up to 10% as the output current

varies from 1A to 10A for a 1.5V output.

Checking Transient Response

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, V_OUTimmediately shifts by an amount

equal to ∆I_LOAD(ESR), where ESR is the effective series

resistance of C_OUT. ∆I_LOADalso begins to charge or

dischargeC_OUTgeneratingafeedbackerrorsignalusedby

the regulator to return V_OUTto its steady-state value.

During this recovery time, V_OUTcan be monitored for

overshoot or ringing that would indicate a stability prob-

lems. The I_THpin external components shown in Figure 9

will provide adequate compensation for most applica-

tions. For a detailed explanation of switching control loop

theory see Application Note 76.

2. Transition loss. This loss arises from the brief amount

of time the top MOSFET spends in the saturated region

during switch node transitions. It depends upon the input

voltage, load current, driver strength and MOSFET capaci-

tance, among other factors. The loss is significant at input

voltages above 20V and can be estimated from:

Design Example

TransitionLoss ≈ (0.5)• V ²•I_OUT•C_RSS• f •

As a design example, take a supply with the following

specifications: V_IN= 7V to 28V (15V nominal), V_OUT

2.5V, I_OUT(MAX)= 20A, f = 250kHz. First, calculate the

timing resistor:

IN

=

⎛

⎞

1

R_{DS(ON)_DRV}

+

⎜

⎟

DRV − V

V_GS(TH)

⎝

⎠

CC

GS(TH)

3. Gate driver supply current. The driver current supplies

thegatechargeQ_GrequiredtoswitchthepowerMOSFETs.

This current is typically much larger than the control

circuit current. In continuous mode operation:

2.5V

R_ON

=

= 476k

0.7V 250kHz 30pF

)( )(

(

)

and choose the inductor for about 40% ripple current at

the maximum V_IN. Maximum output current for each

channel is 10A:

I_GATECHG= f (Q_g(TOP)+ Q_g(BOT)

)

4. C_INloss. The input capacitor has the difficult job of

filtering the large RMS input current to the regulator. It

must have a very low ESR to minimize the AC I²R loss and

sufficient capacitance to prevent the RMS current from

2.5V

250kHz 0.4 10A

2.5V

28V

⎛

⎜

⎝

⎞

⎟

⎠

L =

1−

= 2.3µH

(

)( )(

)

3709f

19

LTC3709

W U U

U

APPLICATIO S I FOR ATIO

Selecting a standard value of 1.8µH results in a maximum

ripple current of:

inductor ripple current and load steps. The ripple voltage

will be only:

∆V_OUT(RIPPLE)= ∆I_L(MAX)(ESR)

= (5.1A) (0.013Ω) = 66mV

2.5V

250kHz 1.8µH

2.5V

28V

⎛

⎜

⎝

⎞

⎟

⎠

∆I_L=

1–

= 5.1A

(

)(

)

However, a 0A to 10A load step will cause an output

change of up to:

Next, choose the synchronous MOSFET switch. Choosing

a Si4874 (R_DS(ON)= 0.0083Ω (NOM) 0.010Ω (MAX),

∆V_OUT(STEP)=∆I_LOAD(ESR)=(10A)(0.013Ω)=130mV

q

_JA= 40°C/W) yields a nominal sense voltage of:

An optional 22µF ceramic output capacitor is included to

minimize the effect of ESL in the output ripple. The

complete circuit is shown in Figure 9.

V_SNS(NOM)= (10A)(1.3)(0.0083Ω) = 108mV

TyingV_RNGto1.1V willsetthecurrentsensevoltagerange

for a nominal value of 110mV with current limit occurring

at 146mV. To check if the current limit is acceptable,

assume a junction temperature of about 80°C above a

70°C ambient with ρ_150°C= 1.5:

PC Board Layout Checklist

When laying out a PC board follow one of the two sug-

gested approaches. The simple PC board layout requires

a dedicated ground plane layer. Also, for higher currents,

it is recommended to use a multilayer board to help with

heat sinking power components.

⎛

⎞

146mV

1

2

I_LIMIT

≥

+

5.1A • 2 = 24A

(

)

⎜

⎟

1.5 0.010Ω

(

)(

)

⎝

⎠

• The ground plane layer should not have any traces and

it should be as close as possible to the layer with power

MOSFETs.

and double check the assumed T_Jin the MOSFET:

2

28 V –2.5V 24A

⎛

⎞

⎟

⎠

P_BOT

=

1.5 0.010Ω = 1.97W

)(

(

)

⎜

• Place C_IN, C_OUT, MOSFETs, D1, D2 and inductors all in

one compact area. It may help to have some compo-

nents on the bottom side of the board.

⎝

28 V

2

T_J= 70°C + (1.97W)(40°C/W) = 149°C

Because the top MOSFET is on for such a short time, an

Si4884 R_DS(ON)(MAX)= 0.0165Ω, C_RSS= 100pF, θ_JA

40°C/W will be sufficient. Checking its power dissipation

at current limit with ρ_100°C= 1.4:

• Use an immediate via to connect the components to

ground plane including SGND and PGND of LTC3709.

Use several larger vias for power components.

=

• Use a compact plane for switch node (SW) to keep EMI

down.

2

2.5V 24A

⎛

⎞

⎟

⎠

• Use planes for V_INand V_OUTto maintain good voltage

filtering and to keep power losses low.

P_TOP

=

1.4 0.0165Ω +

)(

(

)

⎜

⎝

28V

2

1.7 28V 12A 100pF 250kHz

)( ) ( )( )(

(

)

• Flood all unused areas on all layers with copper. Flood-

ing with copper will reduce the temperature rise of

powercomponent.Youcanconnectthecopperareasto

any DC net (V_IN, V_OUT, GND or to any other DC rail in

your system).

= 0.30W + 0.40W = 0.7W

T_J= 70°C + (0.7W)(40°C/W) = 98°C

The junction temperatures will be significantly less at

nominal current, but this analysis shows that careful

attention to heat sinking will be necessary in this circuit.

When laying out a printed circuit board, without a ground

plane, use the following checklist to ensure proper opera-

tion of the controller. These items are also illustrated in

Figure 9.

C_INis chosen for an RMS current rating of about 10A

at 85°C. The output capacitors are chosen for a low ESR

of 0.013Ω to minimize output voltage changes due to

3709f

20

LTC3709

W U U

APPLICATIO S I FOR ATIO

U

• Segregate the signal and power grounds. All small

signal components should return to the SGND pin at

one point, which is then tied to a “clean” point in the

power ground such as the “–” node of C_IN.

• Keep the high dV/dt SW, BOOST and TG nodes away

from sensitive small-signal nodes.

• Connect the DRV_CCdecoupling capacitor C_VCCclosely

to the DRV_CCand PGND pins.

• Minimize impedance between input ground and output

ground.

• Connect the top driver boost capacitor C_Bclosely to the

BOOST and SW pins.

• Connect PGND1 to the source of M2 or R_S1(QFN)

directly. This also applies to channel 2.

• Connect the V_INpin decoupling capacitor C_Fclosely to

the V_CCand PGND pins.

• Place M2 as close to the controller as possible, keeping

the PGND1, BG1 and SW1 traces short. The same for

the other channel. SW2 trace should connect to the

drain of M2 directly.

• Are the SENSE^–and SENSE⁺leads routed together with

minimum PC trace spacing? The filter capacitor be-

tweenSENSE^–andSENSE⁺(C_SENSE)shouldbeasclose

as possible to the IC. Ensure accurate current sensing

with Kelvin connections at the sense resistor as shown

in Figure 8.

• Connect the input capacitor(s) C_INclose to the power

MOSFETs: (+) node to drain of M1, (–) node to source

of M2. This capacitor carries the MOSFET AC current.

D

G

S

R

SENSE

MOSFET

+

–

+

–

SENSE SENSE

3709 F08

(8a) Sensing the Bottom MOSFET

(8b) Sensing a Resistor

Figure 8. Kelvin Sensing

3709f

21

LTC3709

W U U

U

APPLICATIO S I FOR ATIO

MMSD4148

(OPTIONAL)

10nF

C

0.1µF

SS

10k

1

2

3

4

5

6

7

8

9

32

31

30

29

28

27

26

25

24

RUN/SS

V

RNG

FCB

R 20k

C

470pF

C

35.7k

f

I

IN

TH

100pF

R

476k

ON

V

IN

7V TO 28V

V

I

ON

FB

R

100k

PGOOD

DRV

5V

CC

TRACK

SGND

PGOOD

BOOST1

TG1

D1

B340A

PGOOD

TRACK

100pF

D

CMDSH-3

B1

C

0.22µF

B1

SGND

–

M1

M2

L1

1.8µH

V

SW1

+

OS

R

10k

R

31.6k

F1

F2

DIFFOUT SENSE1

+

100pF

–

V

SENSE1

OS

100nF

475Ω

C

OUT

LTC3709EUH

180µF

4V ×4

C

10µF

1nF

IN

35V ×3

10

11

12

13

14

15

16

23

22

21

20

19

18

17

V

2.5V

20A

EXTLPF

INTLPF

NC

PGND1

BG1

OUT

100nF

1µF

3.32k

470pF

DRV

CC

BOOST2

TG2

BG2

C

B2

0.22µF

PGND2

–

SW2

SENSE2

L2

1.8µH

10Ω

1µF

+

SENSE2

V

CC

M3

M4

D

100pF

B2

CMDSH-3

D2

B340A

3709 F09

L1, L2: PANASONIC ETQP6FIR8BFA

: PANASONIC EEFUEOG181R

C

OUT

M1, M3: SILICONIX Si4884DY

M2, M4: SILICONIX Si4874DY

Figure 9. 2-Phase 2.5V/20A Supply at 250kHz with Tracking and External Synch

3709f

22

LTC3709

U

PACKAGE DESCRIPTIO

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693)

0.70 ±0.05

5.50 ±0.05

4.10 ±0.05

3.45 ±0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 ± 0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

BOTTOM VIEW—EXPOSED PAD

0.23 TYP

(4 SIDES)

R = 0.115

TYP

0.75 ± 0.05

5.00 ± 0.10

(4 SIDES)

31 32

0.00 – 0.05

0.40 ± 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.45 ± 0.10

(4-SIDES)

(UH) QFN 0603

0.200 REF

0.25 ± 0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3709f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

23

LTC3709

U

TYPICAL APPLICATIO

Low Output Ripple, 2-Phase 12V/30A Supply

C

0.1µF

SS

1

2

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

10k

21.5k

RUN/SS

V

RNG

FCB

10nF

2.86M

R

C

20k

5V

C

1nF

C

I

TH

R

ON

3

V

IN

24V

V

I

ON

FB

220pF

R

100k

D

PGOOD

4

D1

B340A

DRV

5V

CC

TRACK

SGND

PGOOD

BOOST1

TG1

CMDSH-3

5

B1

L1

C

0.22µF

6

B1

4.7µH

TOKO

FDA1254

M2

M1

LTC3709

7

–

V

SW1

+

OS

R

10k

R

190k

F1

F2

8

DIFFOUT SENSE1

+

C

OUT

100pF

9

–

150µF

V

SENSE1

OS

16V ×3

10

11

12

13

14

15

16

EXTLPF

INTLPF

NC

PGND1

BG1

100nF

V

OUT

3.32k

1µF

C

10µF

IN

35V ×3

470pF

DRV

CC

BOOST2

TG2

BG2

C

B2

1µF

0.22µF

PGND2

L2

4.7µH

–

SW2

SENSE2

10Ω

1µF

+

SENSE2

100pF

V

CC

D

B2

CMDSH-3

M3

M4

D2

B340A

M1-M4: RENESAS HAT2167

: OS-CON 16SVP150M

C

OUT

3709 TA02

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PART NUMBER

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COMMENTS

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LTC3413

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PolyPhase is a registered trademark of Linear Technology Corporation.

3709f

LT/TP 1104 1K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3709EG
厂家：	Linear
描述：	LTC3709 - Fast 2-Phase, No RSENSE Synchronous DC/DC Controller with Tracking/Sequencing; Package: SSOP; Pins: 24; Temperature Range: -40°C to 85°C 控制器
文件：	总24页 (文件大小：280K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3709EG [Linear]

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