LTC3714EG#TRPBF [Linear]
LTC3714 - Intel Compatible, Wide Operating Range, Step-Down Controller with Internal Op Amp; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C;
| 型号： | LTC3714EG#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3714 - Intel Compatible, Wide Operating Range, Step-Down Controller with Internal Op Amp; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C 运算放大器 控制器 |
| 文件： | 总28页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3714
Intel Compatible,
Wide Operating Range, Step-Down Controller
with Internal Op Amp
U
DESCRIPTIO
FEATURES
The LTC®3714 is a synchronous step-down switching
regulator controller for CPU power. An output voltage
between 0.6V and 1.75V is selected by a 5-bit code (Intel
mobile VID specification). The controller uses a constant
on-time, valley current control architecture to deliver very
low duty cycles without requiring a sense resistor. Oper-
ating frequency is selected by an external resistor and is
■
True Current Mode with Ultrafast Transient
Response
■
Stable with Ceramic COUT
■
tON(MIN) < 100ns for Operation from High Input
Ranges
■
Supports Active Voltage Positioning
■
No Sense Resistor Required
■
5-Bit VID Programmable Output Voltage: 0.6V to 1.75V
compensated for variations in VIN and VOUT.
■
Dual N-Channel MOSFET Synchronous Drive
Discontinuous mode operation provides high efficiency
operation at light loads. A forced continuous control pin
reduces noise and RF interference and can assist second-
ary winding regulation by disabling discontinuous mode
when the main output is lightly loaded. Internal op amp
allows programmable offsets to the output voltage during
power saving modes.
■
Programmable Output Offsets
■
Power Good Output Voltage Monitor
■
Wide VIN Range: 4V to 36V
■
±1% 0.6V Reference
■
Adjustable Frequency
■
Programmable Soft-Start
■
Output Overvoltage Protection
■
■
■
■
Fault protection is provided by internal foldback current
limiting, an output overvoltage comparator and optional
short-circuitshutdowntimer.Soft-startcapabilityforsup-
ply sequencing is accomplished using an external timing
capacitor. The regulator current limit level is user pro-
grammable. Wide supply range allows operation from 4V
to 36V at the input.
Optional Short-Circuit Shutdown Timer
Forced Continuous Control Pin
Logic Controlled Micropower Shutdown: IQ ≤ 30µA
Available in 0.20U9" Wide 28-Lead SSOP Package
APPLICATIO S
Power Supply for Mobile Pentium® Processors and
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
Transmeta Processors
Notebook and Portable Computers
■
U
TYPICAL APPLICATIO
LTC3714
R
ON
Transient Response of 8A to 23A Output Load Step
PGOOD
I
ON
INTV
C
CC
V
IN
V
IN
SS
0.1µF
5V TO 24V
10µF
35V
×4
M1
RUN/SS
TG
1.395V
IRF7811
L1
×2
0.68µH
V
I
TH
SW
OUT
C , 0.22µF
B
0.6V TO 1.75V
23A
R
C
C
C
C
BOOST
OUT
+
V
D
B
CMDSH-3
270µF
2V
OUT
SGND
(1.35V)
INTV
CC
×4
50mV/DIV
M2
D1*
UPS840
BG
VID4
VID3
VID2
VID1
VID0
IRF7811
×3
1.213V
23A
SENSE
5-BIT
VID
+
C
VCC
4.7µF
0.003Ω*
I
PGND
LOAD
10A/DIV
3714 F01
V
OSENSE
8A
*OPTIONAL
20µs/DIV
3714 TA03
Figure 1. High Efficiency Step-Down Converter
3714f
1
LTC3714
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
ORDER PART
NUMBER
Input Supply Voltage (VIN), ION..................36V to –0.3V
Boosted Topside Driver Supply Voltage
(BOOST) ................................................... 42V to –0.3V
SW, SENSE Voltages ................................... 36V to –5V
EXTVCC, (BOOST – SW), RUN/SS, VID0-VID4,
PGOOD, FCB Voltages ............................... 7V to –0.3V
VON, VRNG Voltages ................(INTVCC + 0.3V) to –0.3V
ITH, VFB, VOSENSE Voltages....................... 2.7V to –0.3V
TG, BG, INTVCC, EXTVCC Peak Currents.................... 2A
TG, BG, INTVCC, EXTVCC RMS Currents .............. 50mA
OPVIN, OP+, OP– ....................................................... 0V to 18V
Operating Ambient Temperature Range
LTC3714EG (Note 2) .......................... –40°C to 85°C
Junction Temperature (Note 3)............................ 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
1
2
INTV
28
27
26
25
24
23
BG
PGND
SENSE
SW
CC
V
IN
LTC3714EG
3
EXTV
VID4
VID3
V
CC
4
5
TG
6
BOOST
VID0
OSENSE
7
22 VFB
8
I
ON
21
20
19
18
17
16
15
VID1
9
FCB
VID2
10
11
12
13
14
SGND
OPOUT
RUN/SS
V
ON
+
OP
PGOOD
–
OP
V
RNG
OPV
IN
I
TH
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
I
Input DC Supply Current
Normal
Shutdown Supply Current
Q
900
15
2000
30
µA
µA
V
Feedback Reference Voltage
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
Error Amplifier Transconductance
Forced Continuous Threshold
Forced Continuous Current
On-Time
I
= 1.2V (Note 4)
TH
●
0.594
0.600
0.002
–0.05
1.7
0.606
V
%/V
%
FB
∆V
∆V
V
= 4V to 30V (Note 4), I = 1.2V
FB(LINEREG)
IN
TH
TH
TH
I
I
= 0.5V to 1.9V (Note 4)
= 1.2V (Note 4)
●
●
●
–0.3
2
FB(LOADREG)
g
1.4
ms
V
m(EA)
V
0.57
0.6
0.63
–2
FCB
I
t
t
t
V
= 0.6V
FCB
–1
µA
ns
FCB
I
I
I
= 60µA, V = 1.5V
200
250
50
300
100
400
ON
ON
ON
ON
ON
Minimum On-Time
= 180µA, V = 0V
ns
ON(MIN)
OFF(MIN)
ON
Minimum Off-Time
= 60µA, V = 1.5V
250
ns
ON
V
Maximum Current Sense Threshold
V
V
V
= 1V, V = 0.56V
●
●
●
113
79
158
133
93
186
153
107
214
mV
mV
mV
SENSE(MAX)
RNG
RNG
RNG
FB
= 0V, V = 0.56V
FB
= INTV , V = 0.56V
CC FB
V
Minimum Current Sense Threshold
V
V
V
= 1V, V = 0.64V
–67
–33
–93
mV
mV
mV
SENSE(MIN)
RNG
RNG
RNG
FB
= 0V, V = 0.64V
FB
= INTV , V = 0.64V
CC FB
∆V
∆V
Output Overvoltage Fault Threshold
Output Undervoltage Fault Threshold
RUN Pin Start Threshold
7.5
340
0.8
10
400
1.5
12.5
460
2
%
FB(OV)
mV
FB(UV)
V
●
V
RUN/SS(ON)
3714f
2
LTC3714
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
4
MAX
4.5
4.2
–3
3
UNITS
V
V
V
RUN Pin Latchoff Enable Threshold
RUN Pin Latchoff Threshold
Soft-Start Charge Current
Soft-Start Discharge Current
Undervoltage Lockout Threshold
Undervoltage Lockout Threshold
TG Driver Pull-Up On Resistance
TG Driver Pull-Down On Resistance
BG Driver Pull-Up On Resistance
BG Driver Pull-Down On Resistance
TG Rise Time
RUN/SS Pin Rising
RUN/SS Pin Falling
RUN/SS(LE)
RUN/SS(LT)
RUN/SS(C)
RUN/SS(D)
3.5
–1.2
1.8
3.4
3.5
2
V
I
I
–0.5
0.8
µA
µA
V
V
V
V
V
Falling
Rising
●
●
3.9
4
IN(UVLO)
IN
IN
V
IN(UVLOR)
TG R
TG R
BG R
BG R
TG High
TG Low
BG High
BG Low
3
Ω
UP
2
3
Ω
DOWN
UP
3
4
Ω
1
2
Ω
DOWN
TG t
TG t
C
C
C
C
= 3300pF
= 3300pF
= 3300pF
= 3300pF
20
20
20
20
ns
ns
ns
ns
r
f
LOAD
LOAD
LOAD
LOAD
TG Fall Time
BG t
BG t
BG Rise Time
r
BG Fall Time
f
Internal V Regulator
CC
V
Internal V Voltage
6V < V < 30V, V = 4V
EXTVCC
●
●
4.7
4.5
5
5.3
V
%
INTVCC
CC
IN
∆V
Internal V Load Regulation
I
I
I
= 0mA to 20mA, V = 4V
EXTVCC
–0.1
4.7
±2
LDO(LOADREG)
CC
CC
CC
CC
V
EXTV Switchover Voltage
= 20mA, V
= 20mA, V
Rising
= 5V
V
EXTVCC
CC
EXTVCC
EXTVCC
∆V
∆V
EXTV Switch Drop Voltage
150
200
300
mV
mV
EXTVCC
CC
EXTV Switchover Hysteresis
EXTVCC(HYS)
CC
PGOOD Output
∆V
∆V
∆V
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysteresis
V
V
V
Rising
7.5
10
–10
1
12.5
–12.5
2.5
%
%
%
V
FBH
FB
Falling
–7.5
FBL
FB
Returning
FB(HYS)
FB
V
PGOOD Low Voltage
I
= 1mA
0.15
0.4
PGL
PGOOD
VID DAC
V
VID0-VID4 Logic Threshold Voltage
VID0-VID4 Pull-Up Current
VID0-VID4 Pull-Up Voltage
VID0-VID4 Leakage Current
0.4
1.2
–2.5
4.5
0.01
10
2
V
µA
V
VID(T)
I
V
V
V
to V
= 0V
VID(PULLUP)
VID0
VID0
VID0
VID4
VID4
VID4
V
to V
to V
Open
VID(PULLUP)
I
= 5V, V
= 0V
1
µA
KΩ
%
VID(LEAK)
RUN/SS
R
Resistance from V
to V
FB
6
14
VID
OSENSE
∆V
DAC Output Accuracy
V
Programmed from
–0.45
0
0.25
OSENSE
OSENSE
0.6V to 1.75V (Note 5)
VIN = 5V unless otherwise noted.
Internal Op Amp
V
Input Offset Voltage
Input Offset Current
Input Bias Current
400
4
1000
10
µV
nA
nA
OS
I
I
OS
45
80
B
CMRR
Common Mode Rejection Ratio
V
V
= 0V to (V – 1V)
= 0V to 18V
100
80
dB
dB
CM
CM
CC
3714f
3
LTC3714
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
OPV = 3V to 12.5V, OP
MIN
TYP
100
MAX
UNITS
dB
PSRR
Power Supply Rejection Ratio
Large-Signal Voltage Gain
Output Voltage Swing LOW
Output Voltage Swing HIGH
Short-Circuit Current
= V = 1V
OUT O
IN
A
V
V
OPV = 5V, OP
= 500mV to 4.5V, R = 10k
1500
165
V/mV
mV
VOL
OL
IN
OUT
L
OPV = 5V, I
= 5mA
SINK
●
●
500
IN
OPV = 5V, I
= 5mA
4.5
4.87
V
OH
IN
SOURCE
I
Short to GND
30
40
mA
mA
SC
Short to OPV
IN
I
Supply Current
170
300
µA
S
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: The LTC3714 is tested in a feedback loop that adjusts V to
FB
achieve a specified error amplifier output voltage (I ).
TH
Note 2: The LTC3714E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: The LTC3714 VID DAC is tested in a feedback loop that adjusts
to achieve a specified feedback voltage (V = 0.6V) for each DAC
VID code.
V
OSENSE
FB
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P as follows:
D
LTC3714EG: T = T + (P • 130°C/W)
J
A
D
3714f
4
LTC3714
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Transient Response
(Discontinuous Mode)
Transient Response
Start-Up
RUN/SS
2V/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
VOUT
500mV/DIV
IL
IL
IL
5A/DIV
5A/DIV
5A/DIV
20µs/DIV
3714 G01
20µs/DIV
3714 G02
50ms/DIV
3714 G19
LOAD STEP 0A TO 10A
LOAD STEP 1A TO 10A
VIN = 15V
V
IN = 15V
V
IN = 15V
VOUT = 1.25V
VOUT = 1.5V
VOUT = 1.5V
FCB = INTVCC
FIGURE 1 CIRCUIT
RLOAD = 0.125Ω
FCB = 0V
FIGURE 1 CIRCUIT
Efficiency vs Load Current
Efficiency vs Input Voltage
Frequency vs Input Voltage
100
90
80
70
60
300
280
260
240
220
200
95
90
85
80
75
70
FCB = 0V
FIGURE 1 CIRCUIT
V
= 8.5V
IN
I
= 10A
= 0A
OUT
I
= 10A
OUT
V
= 15V
IN
I
I
= 1A
OUT
V
= 24V
I
IN
OUT
= 23A
OUT
V
= 1.35V
FREQUENCY = 300kHz
FIGURE 1 CIRCUIT
OUT
0
5
10
15
20
25
30
5
10
15
INPUT VOLTAGE (V)
20
25
0
3
6
9
12 15 18 21
INPUT VOLTAGE (V)
LOAD CURRENT (A)
3714 G04
3714 G05
3714 G03
Current Sense Threshold
vs ITH Voltage
Load Regulation
ITH Voltage vs Load Current
300
200
100
0
0
–0.1
–0.2
–0.3
–0.4
2.5
2.0
1.5
1.0
0.5
0
2V
V
RNG
=
NO AVP
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
1.4V
1V
0.7V
0.5V
CONTINUOUS
MODE
DISCONTINUOUS
MODE
–100
–200
0
1.0
1.5
2.0
2.5
3.0
0.5
0
2
4
6
8
10
0
5
10
LOAD CURRENT (A)
15
I
VOLTAGE (V)
TH
LOAD CURRENT (A)
3714 G08
3714 G06
3714 G07
3714f
5
LTC3714
U W
TYPICAL PERFOR A CE CHARACTERISTICS
On-Time vs ION Current
On-Time vs VON Voltage
On-Time vs Temperature
10k
1k
300
250
200
150
1000
800
600
400
200
0
V
= 0V
VON
I
= 30µA
ION
I
= 30µA
VON
ION
V
= 0V
100
10
100
50
0
1
10
100
1
2
3
–50 –25
0
25
50
TEMPERATURE (°C)
75
100 125
0
I
CURRENT (µA)
ON
V
VOLTAGE (V)
ON
3714 G20
3714 G21
3714 G22
Maximum Current Sense
Threshold vs Temperature
Maximum Current Sense
Threshold vs VRNG Voltage
Maximum Current Sense
Threshold vs RUN/SS Voltage
150
125
150
140
130
120
110
100
300
250
200
150
100
50
V
RNG
= 1V
V
RNG
= 1V
100
75
50
25
0
0
1.5
2
2.5
3
3.5
–50 –25
0
25
50
75 100 125
0.5
1.0
1.25
1.5
1.75
2.0
0.75
RUN/SS VOLTAGE (V)
TEMPERATURE (°C)
V
VOLTAGE (V)
RNG
3714 G23
3714 G11
3714 G10
Feedback Reference Voltage
vs Temperature
Error Amplifier gm vs Temperature
2.0
1.8
1.6
1.4
1.2
1.0
0.62
0.61
0.60
0.59
0.58
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
3714 G12
3714 G13
3714f
6
LTC3714
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input and Shutdown Currents
vs Input Voltage
EXTVCC Switch Resistance
vs Temperature
INTVCC Load Regulation
10
8
0
–0.1
–0.2
–0.3
–0.4
–0.5
1200
1000
800
60
50
40
30
20
10
0
EXTV OPEN
CC
6
SHUTDOWN
600
4
400
200
0
2
EXTV = 5V
CC
0
0
10
20
30
40
50
–50 –25
0
25
50
75 100 125
20
INPUT VOLTAGE (V)
30
35
0
5
10
15
25
TEMPERATURE (°C)
INTV LOAD CURRENT (mA)
CC
3714 G25
3714 G14
3714 G24
RUN/SS Pin Current
vs Temperature
FCB Pin Current vs Temperature
3
2
0
–0.25
–0.50
–0.75
PULL-DOWN CURRENT
1
0
–1.00
–1.25
–1.50
PULL-UP CURRENT
–1
–2
–50 –25
0
25
50
75 100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
TEMPERATURE (°C)
3714 G16
3714 G15
RUN/SS Latchoff Thresholds
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
5.0
4.5
4.0
3.5
4.0
3.5
3.0
2.5
LATCHOFF ENABLE
LATCHOFF THRESHOLD
3.0
2.0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (C)
3714 G17
3714 G18
3714f
7
LTC3714
U
U
U
PI FU CTIO S
BG (Pin 1): Bottom Gate Drive. Drives the gate of the
mum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The sense voltage defaults
to 70mV when this pin is tied to ground, 140mV when tied
to INTVCC.
bottom N-channel MOSFET between ground and INTVCC.
PGND (Pin 2): Power Ground. Connect this pin closely to
the bottom of the sense resistor or if no sense resistor is
used, to the source of the bottom N-channel MOSFET, the
(–) terminal of CVCC and the (–) terminal of CIN.
I
TH (Pin 14): Current Control Threshold and Error Ampli-
fier Compensation Point. The current comparator thresh-
old increases with this control voltage. The voltage ranges
from 0V to 2.4V with 0.8V corresponding to zero sense
voltage (zero current).
SENSE (Pin 3): Current Sense Comparator Input. The (+)
input to the current comparator is normally connected to
the SW node unless using a sense resistor (see Applica-
tions Information).
OPVIN (Pin 15): Internal Op Amp Supply. Connect to
INTVCC or a separate supply greater than 5V.
OP– (Pin 16): Negative Input of the Internal Op Amp.
OP+ (Pin 17): Positive Input of the Internal Op Amp.
OPOUT (Pin 18): Output of the Internal Op Amp.
SW(Pin4):SwitchNode.The(–)terminalofthebootstrap
capacitor CB connects here. This pin swings from a diode
voltage drop below ground up to VIN.
TG (Pin 5): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superim-
posed on the switch node voltage SW.
SGND (Pin 19): Signal Ground. All small-signal compo-
nents and compensation components should connect to
this ground, which in turn connects to PGND at one point.
BOOST (Pin 6): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
VIN + INTVCC.
FCB (Pin 20): Forced Continous Input. Tie this pin to
ground to force continuous synchronous operation at low
load, to INTVCC to enable discontinuous mode operation
atlowloadortoaresistivedividerfromasecondaryoutput
when using a secondary winding.
VID0-VID4 (Pins 7, 8, 9, 24, 25): VID Digital Inputs. The
voltageidentification(VID)codesetstheinternalfeedback
resistordividerratiofordifferentoutputvoltagesasshown
in Table 1. If unconnected, the pins are pulled high by
internal 2.5µA current sources.
ION (Pin 21): On-Time Current Input. Tie a resistor from
VIN tothispintosettheone-shottimercurrentandthereby
set the switching frequency.
RUN/SS (Pin 10): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.
VFB (Pin 22): Error Amplifier Feedback Input. This pin
connectstoboththeerroramplifierinputandtotheoutput
of the internal resistive divider. It can be used to attach
additional compensation components if desired.
VOSENSE (Pin 23): Output Voltage Sense. The output
voltage connects here to the input of the internal resistive
feedback divider.
VON (Pin11):On-TimeVoltageInput. Voltagetrippointfor
the on-time comparator. Tying this pin to the output
voltage makes the on-time proportional to VOUT. The
comparatorinputdefaultsto0.7Vwhenthepinisgrounded,
2.4V when the pin is tied to INTVCC.
EXTVCC (Pin 26): External VCC Input. When EXTVCC ex-
ceeds 4.7V, an internal switch connects this pin to INTVCC
and shuts down the internal regulator so that controller
andgatedrivepowerisdrawnfromEXTVCC.Donotexceed
7V at this pin and ensure that EXTVCC < VIN.
PGOOD (Pin 12): Power Good Output. Open drain logic
output that is pulled to ground when the output voltage is
not within ±10% of the regulation point.
VIN (Pin 27): Main Input Supply. Decouple this pin to
SGND with an RC filter (1Ω, 0.1µF).
VRNG (Pin 13): Sense Voltage Range Input. The voltage at
this pin is ten times the nominal sense voltage at maxi-
3714f
8
LTC3714
U
U
U
PI FU CTIO S
INTVCC (Pin 28): Internal 5V Regulator Output. The driver
and control circuits are powered from this voltage. De-
couple this pin to power ground with a minimum of 4.7µF
tantalum or other low ESR capacitor.
U
U
W
FU CTIO AL DIAGRA
R
ON
V
IN
27
V
11
V
21
I
ON
20 FCB
26 EXTV
CC
IN
ON
4.7V
+
C
IN
1µA
+
–
0.7V
2.4V
0.6V
REF
0.6V
1
5V
REG
+
–
F
OST
BOOST
6
TG
5
V
=
VON
ION
t
ON
(10pF)
R
S
C
B
I
Q
FCNT
M1
SW
4
ON
20k
+
–
+
–
L1
SENSE
3
SWITCH
LOGIC
I
I
REV
CMP
V
OUT
INTV
28
CC
SHDN
OV
+
C
VCC
1.4V
BG
1
C
OUT
M2
V
RNG
PGND
2
13
X
(0.5 TO 2)
PGOOD
12
0.7V
3.3µA
V
OSENSE
23
1
R2
10k
0.54V
240k
+
–
1V
Q2 Q4
5× (ALL VID PINS)
UV
OV
INTV
Q6
CC
2.5µA
VID0
7
8
Q3 Q1
+
–
Q5
VID1
VID2
VID3
VID4
+
–
VID
9
0.66V
0.8V
DAC
RUN
SHDN
SS
24
–
+
1.2µA
EA
×5.3
6V
25
–
+
0.6V
R1
C
C
SS
C1
I
TH
RUN/SS
V
SGND
19
14
10
22
0.6V
FB
0.4V
R
C
3714 FD
OPV
IN
15
+
OP
OP
17
16
+
OPOUT
18
OP AMP
–
–
SGND
19
3714f
9
LTC3714
U
OPERATIO
Main Control Loop
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an on-
time that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN and VOUT. The nominal frequency can be adjusted
with an external resistor RON.
TheLTC3714isaconstanton-time, currentmodecontrol-
ler for DC/DC step-down converters. In normal operation,
the top MOSFET is turned on for a fixed interval deter-
mined by a one-shot timer OST. When the top MOSFET is
turned off, the bottom MOSFET is turned on until the
current comparator ICMP trips, restarting the one-shot
timer and initiating the next cycle. Inductor current is
determined by sensing the voltage between the PGND and
SENSE pins using either the bottom MOSFET on-resis-
tance or a separate sense resistor. The voltage on the ITH
pin sets the comparator threshold corresponding to in-
ductor valley current. The error amplifier EA adjusts this
voltage by comparing the feedback signal VFB from the
output voltage with an internal 0.6V reference. The feed-
back voltage is derived from the output voltage by a
resistive divider DAC that is set by the VID code pins VID0-
VID4. If the load current increases, it causes a drop in the
feedback voltage relative to the reference. The ITH voltage
thenrisesuntiltheaverageinductorcurrentagainmatches
the load current.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exitsa±10%windowaroundtheregulationpoint.Further-
more, inanovervoltagecondition, M1isturnedoffandM2
is turned on and held on until the overvoltage condition
clears.
Foldback current limiting is provided if the output is
shorted to ground. As VFB drops, the buffered current
threshold voltage ITHB is pulled down by clamp Q3 to a 1V
level set by Q2 and Q6. This reduces the inductor valley
current level to one sixth of its maximum value as VFB
approaches ground.
Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Releasing
the pin allows an internal 1.2µA current source to charge
up an external soft-start capacitor CSS. When this voltage
reaches 1.5V, the controller turns on and begins switch-
ing, but with the ITH voltage clamped at approximately
0.6V below the RUN/SS voltage. As CSS continues to
charge, the soft-start current limit is removed.
At low load currents, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator IREV which then shuts off M2, resulting in
discontinuous operation. Both switches will remain off
with the output capacitor supplying the load current until
the ITH voltage rises above the zero current level (0.8V) to
initiate another cycle. Continuous synchronous operation
can be forced in the LTC3714 by bringing the FCB pin
below 0.6V. The benefit of forced continuous operation is
lower output voltage ripple, faster transient response to
currentloadstepsandamuchquieterfrequencyspectrum
so that it won’t interfere with any neighboring noise
sensitive components.
3714f
10
LTC3714
U
OPERATIO
Internal Op Amp
INTVCC/EXTVCC Power
The internal op amp allows the user to program accurate
offsets to the output voltage during power saving modes.
By connecting the OP+ pin to the output, the OPOUT pin to
the VOSENSE pin and an external resistor R1 between the
OP–and OPOUT pins, the op amp is hooked up as a unity-
gain feedback amplifier. Resistors R2 and R3, together
with series switches, can then be placed on the OP– pin to
allow negative offsets to be switched onto the output
voltage (see Figures 2a and 2b). The accuracy of the offset
will depend on the matching of the external resistors R1 to
R2 and R3.*
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is re-
chargedfromINTVCC throughanexternalSchottkydiode
DB when the top MOSFET is turned off. When the EXTVCC
pin is grounded, an internal 5V low dropout regulator
supplies the INTVCC power from VIN. If EXTVCC rises
above 4.7V, the internal regulator is turned off, and an
internal switch connects EXTVCC to INTVCC. This allows
ahighefficiencysourceconnectedtoEXTVCC, suchasan
external 5V supply or a secondary output from the
converter, to provide the INTVCC power. Voltages up to
7V can be applied to EXTVCC for additional gate drive. If
the input voltage is low and INTVCC drops below 3.5V,
undervoltage lockout circuitry prevents the power
switches from turning on.
For applications that require less accurate output offsets,
or none at all, the user can use the internal op amp for true
differential remote sensing of the output voltage by con-
necting OPOUT to VOSENSE and using OP+ and OP– for
differential sensing across the output capacitor as shown
in Figure 2c.
*An alternate configuration, shown in Figure 2b, can be used to program
offsets as well. Either configuration can be used, depending upon the logic
of control signals. If offsets are not required, the op amp can be used to
remotely sense the output voltage, proving true differential sense.
V
OUT
V
OUT
OPV
15
IN
R1
+
OP
OPV
15
IN
+
OP
17
+
–
VID DAC
17
+
–
V
R2
OPOUT
18
OSENSE
23
18
23
VID DAC
–
OP
BATTERY
MODE
OFFSET
16
V
FB
–
OP
16
V
FB
22
R1
22
R2
R1
R2
R3
R3
3714 F02b
SLEEP
MODE
OFFSET
BATTERY
MODE
OFFSET
3714 F02b
SLEEP
MODE
OFFSET
Figure 2a
Figure 2b
OPV
15
IN
+
OP
R
R
+
–
17
+
–
V
OPOUT
18
V
OUT
OUT
OSENSE
23
–
OP
16
R
3714 F02c
V
R
Figure 2c
3714f
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LTC3714
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APPLICATIO S I FOR ATIO
The basic LTC3714 application circuit is shown in
Figure 1. External component selection is primarily de-
termined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches. The LTC3714 can use either a sense resistor or
theon-resistanceofthesynchronouspowerMOSFETfor
determining the inductor current. The desired amount of
ripple current and operating frequency largely deter-
mines the inductor value. Finally, CIN is selected for its
ability to handle the large RMS current into the converter
and COUT is chosen with low enough ESR to meet the
output voltage ripple and transient specification.
MOSFET as the current sense element by simply connect-
ingtheSENSEpintotheswitchnodeSWatthedrainofthe
bottom MOSFET. This improves efficiency, but one must
carefully choose the MOSFET on-resistance as discussed
below.
Power MOSFET Selection
The LTC3714 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V(BR)DSS
threshold voltage V(GS)TH, on-resistance RDS(ON), reverse
transfercapacitanceCRSS andmaximumcurrentIDS(MAX)
,
.
Maximum Sense Voltage and VRNG Pin
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3714 applications. If the input voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered.
Inductor current is determined by measuring the voltage
across a sense resistance that appears between the PGND
and SENSE pins. The maximum sense voltage is set by the
voltage applied to the VRNG pin and is equal to approxi-
mately (0.133)VRNG. The current mode control loop will
not allow the inductor current valleys to exceed
(0.133)VRNG/RSENSE. In practice, one should allow some
margin for variations in the LTC3714 and external compo-
nent values and a good guide for selecting the sense
resistance is:
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-
resistance. MOSFET on-resistance is typically specified
with a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
VRNG
10 •IOUT(MAX)
RSENSE
=
RSENSE
RDS(ON)(MAX)
=
ρT
An external resistive divider from INTVCC can be used to
set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC
in which case the nominal sense voltage defaults to 70mV
or 140mV, respectively. The maximum allowed sense
voltage is about 1.33 times this nominal value.
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 3. Junction-to-case temperature is about 30°C in
most applications. For a maximum ambient temperature
of 70°C, using a value ρ100°C = 1.3 is reasonable.
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
the load current. When the LTC3714 is operating in
continuous mode, the duty cycles for the MOSFETs are:
Connecting the SENSE Pin
TheLTC3714canbeusedwithorwithoutasenseresistor.
When using a sense resistor, it is placed between the
source of the bottom MOSFET M2 and ground. Connect
theSENSEpintothesourceofthebottomMOSFETsothat
the resistor appears between the SENSE and PGND pins.
Using a sense resistor provides a well defined current
limit, but adds cost and reduces efficiency. Alternatively,
one can eliminate the sense resistor and use the bottom
VOUT
DTOP
DBOT
=
=
V
IN
V – VOUT
IN
V
IN
3714f
12
LTC3714
W U U
APPLICATIO S I FOR ATIO
U
2.0
1.5
1.0
0.5
0
Tying a resistor RON from VIN to the ION pin yields an on-
time inversely proportional to VIN. For a step-down con-
verter, this results in approximately constant frequency
operation as the input supply varies:
VOUT
VVONRON(10pF)
f =
Toholdfrequencyconstantduringoutputvoltagechanges,
tie the VON pin to VOUT. The VON pin has internal clamps
that limit its input to the one-shot timer. If the pin is tied
below 0.7V, the input to the one-shot is clamped at 0.7V.
Similarly, if the pin is tied above 2.4V, the input is clamped
at 2.4V.
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
3714 F02
Figure 3. RDS(ON) vs Temperature
Because the voltage at the ION pin is about 0.7V, the
currentintothispinisnotexactlyinverselyproportionalto
VIN, especially in applications with lower input voltages.
To correct for this error, an additional resistor RON2
connected from the ION pin to the 5V INTVCC supply will
further help to stabilize the frequency.
The resulting power dissipation in the MOSFETs at maxi-
mum output current are:
PTOP = DTOP OUT(MAX)
I
2 ρT(TOP) RDS(ON)(MAX)
+ k VIN IOUT(MAX) CRSS
2
f
PBOT = DBOT OUT(MAX)
2 ρT(BOT) RDS(ON)(MAX)
I
Both MOSFETs have I2R losses and the top MOSFET
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottomMOSFETlossesaregreatestwhenthebottomduty
cycle is near 100%, during a short-circuit or at high input
voltage.
5V
0.7V
RON2
=
RON
Changes in the load current magnitude will also cause
frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
loadcurrentincreases.Bylengtheningtheon-timeslightly
as current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
from the ITH pin to the VON pin and VOUT. The values
required will depend on the parasitic resistances in the
specific application. A good starting point is to feed about
25% of the voltage change at the ITH pin to the VON pin as
shown in Figure 4a. Place capacitance on the VON pin to
filter out the ITH variations at the switching frequency. The
resistor load on ITH reduces the DC gain of the error amp
and degrades load regulation, which can be avoided by
using the PNP emitter follower of Figure 4b.
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improvesefficiencybyreducingMOSFETswitchinglosses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
TheoperatingfrequencyofLTC3714applicationsisdeter-
mined implicitly by the one-shot timer that controls the
on-time tON of the top MOSFET switch. The on-time is set
by the current into the ION pin and the voltage at the VON
pin according to:
V
tON
=
VON (10pF)
I
ION
3714f
13
LTC3714
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APPLICATIO S I FOR ATIO
R
R
VON1
3k
VON1
30k
V
V
ON
V
OUT
V
OUT
ON
C
R
VON
C
VON2
VON
R
0.01µF
VON2
100k
10k
10k
0.01µF
LTC3714
TH
LTC3714
TH
INTV
CC
R
R
C
C
Q1
2N5087
I
I
C
C
C
C
3714 F04a
3714 F04b
(4a)
(4b)
Figure 4. Correcting Frequency Shift with Load Current Changes
Inductor Selection
Schottky Diode D1 Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
ofthebottomMOSFETfromturningonandstoringcharge
during the dead time, causing a modest (about 1%)
efficiency loss. The diode can be rated for about one half
to one fifth of the full load current since it is on for only a
fraction of the duty cycle. In order for the diode to be
effective,theinductancebetweenitandthebottomMOSFET
must be as small as possible, mandating that these
components be placed adjacently. The diode can be omit-
ted if the efficiency loss is tolerable.
VOUT
fL
VOUT
V
IN
∆IL =
1−
Lower ripple current reduces cores losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
CIN and COUT Selection
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
VOUT
V
IN
V
IN
VOUT
IRMS IOUT(MAX)
– 1
VOUT
f∆IL(MAX)
VOUT
V
IN(MAX)
L =
1−
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX)/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
basedononly2000hoursoflifewhichmakesitadvisable
to derate the capacitor.
Once the value for L is known, the type of inductor must be
selected. A variety of inductors designed for high current,
low voltage applications are available from manufacturers
such as Sumida and Panasonic.
3714f
14
LTC3714
W U U
APPLICATIO S I FOR ATIO
U
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step
transients. The output ripple ∆VOUT is approximately
bounded by:
to store about 100 times the gate charge required by the
top MOSFET. In most applications 0.1µF to 0.47µF is
adequate.
Discontinuous Mode Operation and FCB Pin
1
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.6V threshold (typically to INTVCC)
enables discontinuous operation where the bottom
MOSFET turns off when inductor current reverses. The
load current at which current reverses and discontinuous
operation begins, depends on the amplitude of the induc-
tor ripple current. The ripple current depends on the
choice of inductor value and operating frequency as well
as the input and output voltages.
∆VOUT ≤ ∆IL ESR +
8fCOUT
Since ∆IL increases with input voltage, the output ripple is
highestatmaximuminputvoltage.Typically,oncetheESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, POSCAP aluminum elec-
trolytic and ceramic capacitors are all available in surface
mount packages. Special polymer capacitors offer very
low ESR but have lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
density but it is important to only use types that have been
surge tested for use in switching power supplies. Alumi-
num electrolytic capacitors have significantly higher ESR,
but can be used in cost-sensitive applications providing
that consideration is given to ripple current ratings and
long term reliability. Ceramic capacitors have excellent
low ESR characteristics but can have a high voltage
coefficient and audible piezoelectric effects. The high Q of
ceramic capacitors with trace inductance can also lead to
significant ringing. When used as input capacitors, care
must be taken to ensure that ringing from inrush currents
and switching does not pose an overvoltage hazard to the
powerswitchesandcontroller. Highperformancethrough-
hole capacitors may also be used, but an additional
ceramic capacitor in parallel is recommended to reduce
the effect of their lead inductance.
TyingtheFCBpinbelowthe0.6Vthresholdforcescontinu-
ous synchronous operation, allowing current to reverse at
light loads.
In addition to providing a logic input to force continuous
operation, the FCB pin provides a means to maintain a
flyback winding output when the primary is operating in
discontinuous mode. The secondary output VSEC is nor-
mally set as shown in Figure 5 by the turns ratio N of the
transformer. However, if the controller goes into discon-
tinuous mode and halts switching due to a light primary
load current, then VSEC will droop. An external resistor
divider from VSEC to the FCB pin sets a minimum voltage
VSEC(MIN) below which continuous operation is forced
until VSEC has risen above its minimum.
R4
VSEC(MIN) = 0.6V 1+
R3
V
IN
+
C
IN
V
IN
1N4148
Top MOSFET Driver Supply (CB, DB)
V
V
TG
SEC
OUT
•
OPTIONAL
EXTV
+
LTC3714
EXTV
C
AnexternalbootstrapcapacitorCBconnectedtotheBOOST
pinsuppliesthegatedrivevoltageforthetopsideMOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
SEC
CC
SW
1µF
CC
CONNECTION
5V < V < 7V
R4
R3
•
SEC
T1
1:N
+
SENSE
C
OUT
FCB
BG
SGND
PGND
3714 F05
Figure 5. Secondary Output Loop and EXTVCC Connection
3714f
15
LTC3714
W U U
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APPLICATIO S I FOR ATIO
Fault Conditions: Current Limit and Foldback
To further limit current in the event of a short circuit to
ground, the LTC3714 includes foldback current limiting. If
the output falls by more than 50%, then the maximum
sense voltage is progressively lowered to about one sixth
of its full value.
The maximum inductor current is inherently limited in a
currentmodecontrollerbythemaximumsensevoltage.In
the LTC3714, the maximum sense voltage is controlled by
the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
Minimum Off-Time and Dropout Operation
The minimum off-time tOFF(MIN) is the smallest amount of
time that the LTC3714 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 250ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON +tOFF(MIN)).Ifthemaximumdutycycleisreached,
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:
VSNS(MAX)
*RDS(ON)ρT
1
+ ∆IL
ILIMIT
=
2
The current limit value should be checked to ensure that
ILIMIT(MIN) >IOUT(MAX).Theminimumvalueofcurrentlimit
generallyoccurswiththelowestVIN atthehighestambient
temperature. Note that it is important to check for self-
consistency between the assumed junction temperature
and the resulting value of ILIMIT which heats the MOSFET
switches.
t
ON + tOFF(MIN)
V
= VOUT
IN(MIN)
tON
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
resistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable assumption is that the minimum RDS(ON) lies
the same amount below the typical value as the maximum
liesaboveit.ConsulttheMOSFETmanufacturerforfurther
guidelines.
Output Voltage Programming
The output voltage is digitally set to levels between 0.6V
and 1.75V using the voltage identification (VID) inputs
VID0-VID4. An internal 5-bit DAC configured as a preci-
sion resistive voltage divider sets the output voltage in
increments according to Table 1. The VID codes are
compatiblewithIntelMobilePentium® IIIprocessorspeci-
fications. Each VID input is pulled up by an internal 2.5µA
current source from the INTVCC supply and includes a
series diode to prevent damage from VID inputs that
exceed the supply.
*Use RSENSE value here if a sense resistor is connected between SENSE and PGND.
3714f
16
LTC3714
W U U
APPLICATIO S I FOR ATIO
INTVCC Regulator
U
Table 1. VID Output Voltage Programming
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V
(V)
OUT
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3714. The INTVCC pin can supply up to
50mA RMS and must be bypassed to ground with a
minimum of 4.7µF tantalum or other low ESR capacitor.
Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate drivers. Applica-
tions using large MOSFETs with a high input voltage and
high frequency of operation may cause the LTC3714 to
exceed its maximum junction temperature rating or RMS
current rating. Most of the supply current drives the
MOSFET gates unless an external EXTVCC source is used.
1.75V
1.70V
1.65V
1.60V
1.55V
1.50V
1.45V
1.40V
1.35V
1.30V
1.25V
1.20V
1.15V
1.10V
1.05V
1.00V
In continuous mode operation, this current is IGATECHG
=
f(Qg(TOP) + Qg(BOT)). The junction temperature can be
estimated from the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC3714EG is
limited to less than 14mA from a 30V supply:
TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C
0.975V
0.950V
0.925V
0.900V
0.875V
0.850V
0.825V
0.800V
0.775V
0.750V
0.725V
0.700V
0.675V
0.650V
0.625V
0.600V
Forlargercurrents, considerusinganexternalsupplywith
the EXTVCC pin.
3714f
17
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APPLICATIO S I FOR ATIO
EXTVCC Connection
3. EXTVCC connected to an output derived boost network.
The low voltage output can be boosted using a charge
pump or flyback winding to greater than 4.7V. The system
will start-up using the internal linear regulator until the
boosted output supply is available.
The EXTVCC pin can be used to provide MOSFET gate drive
and control power from the output or another external
source during normal operation. Whenever the EXTVCC
pin is above 4.7V the internal 5V regulator is shut off and
an internal 50mA P-channel switch connects the EXTVCC
pintoINTVCC.INTVCC powerissuppliedfromEXTVCC until
this pin drops below 4.5V. Do not apply more than 7V to
the EXTVCC pin and ensure that EXTVCC ≤ VIN. The follow-
ing list summarizes the possible connections for EXTVCC:
External Gate Drive Buffers
The LTC3714 drivers are adequate for driving up to about
60nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
frequencies requiring greater RMS currents will benefit
fromusingexternalgatedrivebufferssuchastheLTC1693.
Alternately, the external buffer circuit shown in Figure 6
can be used. Note that the bipolar devices reduce the
signal swing at the MOSFET gate, and benefit from in-
creased EXTVCC voltage of about 6V.
1. EXTVCC grounded. INTVCC is always powered from the
internal 5V regulator.
2. EXTVCC connected to an external supply. A high effi-
ciency supply compatible with the MOSFET gate drive
requirements (typically 5V) can improve overall
efficiency.
BOOST
INTV
CC
Q1
Q3
FMMT619
FMMT619
10Ω
10Ω
GATE
OF M1
GATE
OF M2
TG
BG
Q2
FMMT720
Q4
FMMT720
SW
PGND
3714 F06
Figure 6. Optional External Gate Driver
3714f
18
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Soft-Start and Latchoff with the RUN/SS Pin
troller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.
The RUN/SS pin provides a means to shut down the
LTC3714 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 1.5V puts the
LTC3714 into a low quiescent current shutdown (IQ ≤
30µA). Releasing the pin allows an internal 1.2µA internal
current source to charge up the external timing capacitor
CSS.IfRUN/SShasbeenpulledallthewaytoground,there
is a delay before starting of about:
The overcurrent protection timer requires that the soft-
start timing capacitor CSS be made large enough to guar-
antee that the output is in regulation by the time CSS has
reachedthe4Vthreshold.Ingeneral,thiswilldependupon
the size of the output capacitance, output voltage and load
currentcharacteristic.Aminimumsoft-startcapacitorcan
be estimated from:
1.5V
1.2µA
C
SS > COUT VOUT RSENSE (10–4 [F/Vs])
tDELAY
=
C
SS = 1.3s/µF CSS
(
)
Generally 0.1µF is more than sufficient.
When the voltage on RUN/SS reaches 1.5V, the LTC3714
begins operating with a clamp on ITH of approximately
0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH
is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF, during which the load current is folded
backuntiltheoutputreaches50%ofitsfinalvalue. Thepin
can be driven from logic as shown in Figure 7. Diode D1
reduces the start delay while allowing CSS to charge up
slowly for the soft-start function.
Overcurrent latchoff operation is not always needed or
desired. Load current is already limited during a short-
circuit by the current foldback circuitry and latchoff
operation can prove annoying during troubleshooting.
The feature can be overridden by adding a pull-up current
of >5µA to the RUN/SS pin. The additional current pre-
ventsthedischargeofCSS duringafaultandalsoshortens
the soft-start period. Using a resistor to VIN as shown in
Figure 7a is simple, but slightly increases shutdown
current. Connecting a resistor to INTVCC as shown in
Figure 7b eliminates the additional shutdown current, but
requires a diode to isolate CSS. Any pull-up network must
be able to pull RUN/SS above the 4.5V maximum thresh-
old that arms the latchoff circuit and overcome the 4µA
maximum discharge current.
After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.7µA cur-
rent then begins discharging CSS. If the fault condition
persists until the RUN/SS pin drops to 3.5V, then the con-
INTV
CC
R *
SS
V
IN
RUN/SS
3.3V OR 5V
RUN/SS
*
D2*
R
SS
D1
C
SS
C
SS
3714 F07
*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
(7a)
(7b)
Figure 7. RUN/SS Pin Interfacing with Latchoff Defeated
3714f
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LTC3714
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APPLICATIO S I FOR ATIO
Efficiency Considerations
When making any adjustments to improve efficiency, the
final arbiter is the total input current for the regulator at
your operating point. If you make a change and the input
current decreases, then you improved the efficiency. If
thereisnochangeininputcurrent, thenthereisnochange
in efficiency.
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3714 circuits:
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD (ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
dischargeCOUT generatingafeedbackerrorsignalusedby
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The ITH pin external components shown in Figure 8
will provide adequate compensation for most applica-
tions. For a detailed explanation of switching control loop
theory see Linear Technology Application Note 76.
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then the
resistanceofoneMOSFETcansimplybesummedwiththe
resistances of L and the board traces to obtain the DC I2R
loss.Forexample,ifRDS(ON) =0.01ΩandRL =0.005Ω,the
loss will range from 15mW up to 1.5W as the output
current varies from 1A to 10A for a 1.5V output.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capaci-
tance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
Design Example
As a design example, take a supply with the following
specifications: VIN = 7V to 24V (15V nominal),
VOUT = 1.15V ±100mV, IOUT(MAX) = 15A, f = 300kHz. First,
2
Transition Loss (1.7A–1) VIN IOUT CRSS
f
calculate the timing resistor with VON = VOUT
:
3. INTVCC current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by supply-
ing INTVCC current through the EXTVCC pin from a high
efficiency source, such as an output derived boost net-
work or alternate supply if available.
1
RON
=
= 330k
300kHz 10pF
(
)(
)
and choose the inductor for about 40% ripple current at
the maximum VIN:
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
1.15V
1.15V
24V
L =
1−
= 0.6µH
300kHz 0.4 15A
(
)( )(
)
Choosing a standard value of 0.68µH results in a maxi-
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
mum ripple current of:
1.15V
1.15V
24V
∆IL =
1–
= 5.4A
300kHz 0.68µH
(
)(
)
3714f
20
LTC3714
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APPLICATIO S I FOR ATIO
U
Next, choose the synchronous MOSFET switch. Because
of the narrow duty cycle and large current, a single SO-8
MOSFET will have difficulty dissipating the power lost in
the switch. Choosing two IRF7811s (RDS(ON) = 0.013Ω,
186mV
1
2
ILIMIT
≥
+
5.4A = 20A
(
)
0.5 1.6 0.013Ω
(
)( )(
)
and double check the assumed TJ in the MOSFET:
C
RSS = 60pF) yields a nominal sense voltage of:
2
VSNS(NOM) = (15A)(0.5)(1.3)(0.013Ω) = 127mV
24V – 1.15V 20A
PBOT
=
1.6 0.013Ω = 1.98W
)(
(
)
24V
2
Tying VRNG to INTVCC will set the current sense voltage
range for a nominal value of 140mV with current limit
occurring at 186mV. To check if the current limit is
acceptable,assumeajunctiontemperatureofabout100°C
above a 50°C ambient with ρ150°C = 1.6:
TJ = 50°C + (1.98W)(50°C/W) = 149°C
9
10
11
12
13
14
19
21
22
20
23
24
15
16
8
C
VID2
VID1
VID0
BOOST
TG
SS
0.1µF
7
RUN/SS
D
B
CMDSH-3
6
V
IN
V
ON
7V TO 24V
C
R
C
IN
PG
B
22µF
25V
×3
100k
0.33µF
5
M1
L1
PGOOD
IRF7811
0.68µH
V
OUT
1.15V
15A
4
C
C1
2.2nF
V
I
SW
RNG
C
R
OUT
C
270µF
2V
M2
IRF7811
×2
20k
3
SENSE
TH
D1
UPS840
C
×5
C2
LTC3714
SGND
100pF
2
PGND
BG
C
0.01µF
ION
1
I
ON
C
VCC
4.7µF
28
27
26
25
18
17
V
INTV
CC
FB
R
1Ω
F
C
100pF
FB
FCB
V
IN
C
F
0.1µF
V
EXTV
5V
OSENSE
CC
R
ON
VID3
VID4
330k
OPV
OPOUT
IN
–
+
OP
OP
3714 F08
C
C
: UNITED CHEMICON THCR70EIH226ZT
IN
: PANASONIC EEFUE0D271
OUT
L1: SUMIDA CEP125-4712-T007
Figure 8. CPU Core Voltage Regulator 1.15V/15A at 300kHz without Active Voltage Positioning
3714f
21
LTC3714
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APPLICATIO S I FOR ATIO
Because the top MOSFET is on for such a short time, a
single IRF7811 will be sufficient. Checking its power
dissipation at current limit with ρ80°C = 1.2:
1
3
∆VOUT(STEP) = 15A
0.025Ω = 125mV
(
)
(
)
By positioning the output voltage 60mV above the regula-
tionpointatnoload,itwilldrop65mVbelowtheregulation
point after the load step. However, when the load disap-
pears or the output is stepped from 15A to 0A, the 65mV
isrecovered. Thisway, atotalof65mVchangeisobserved
on VOUT in all conditions, whereas a total of ±75mV or
150mV is seen on VOUT without voltage positioning.
1.15V
24V
2
PTOP
=
20A 1.2 0.013Ω +
(
) ( )(
)
2
1.7 24V 20A 60pF 300kHz
)( ) ( )( )(
= 0.299W + 0.353W = 0.652W
(
)
TJ = 50°C + (0.652W)(50°C/W) = 82.6°C
Implementingactivevoltagepositioningrequiressettinga
precise gain between the sensed current and the output
voltage. Because of the variability of MOSFET on-resis-
tance, it is prudent to use a sense resistor with active
voltage positioning. In order to minimize power lost in this
resistor, a low value of 0.003Ω is chosen. The nominal
sense voltage will now be:
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
CIN is chosen for an RMS current rating of about 6A at
temperature. The output capacitors are chosen for a low
ESR of 0.005Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
VSNS(NOM) = (0.003Ω)(15A) = 45mV
To maintain a reasonable current limit, the voltage on the
VRNG pin is reduced to 0.5V by connecting it between
INTVCC andGND,correspondingtoa50mVnominalsense
voltage.
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR) = (5.4A) (0.005Ω)
= 27mV
However, a 0A to 15A load step will cause an output
change of up to:
Next, the gain of the LTC3714 error amplifier must be
determined. ThechangeinITH voltageforacorresponding
change in the output current is:
∆VOUT(STEP) =∆ILOAD (ESR)=(15A)(0.005Ω)=±75mV
The complete circuit is shown in Figure 8.
12V
VRNG
Active Voltage Positioning
∆ITH
=
RSENSE ∆IOUT
Active voltage positioning (also termed load “deregula-
tion” or droop) describes a technique where the output
voltage varies with load in a controlled manner. It is useful
in applications where rapid load steps are the main cause
of error in the output voltage. By positioning the output
voltage at or above the regulation point at zero load, and
below the regulation point at full load, one can use more
of the error budget for the load step. This allows one to
reduce the number of output capacitors by relaxing the
ESR requirement.
= 24 0.003Ω 15A = 1.08V
( )( )(
)
The corresponding change in the output voltage is deter-
mined by the gain of the error amplifier and feedback
divider. The LTC3714 error amplifier has a
transconductance gm that is constant over both tempera-
ture and a wide ±40mV input range. Thus, by connecting
aloadresistanceRVP totheITH pin, theerroramplifiergain
can be precisely set for accurate voltage positioning.
In the design example, Figure 8, five 0.025Ω capacitors
are required in parallel to keep the output voltage within
tolerance. Using active voltage positioning, the same
specification can be met with only threecapacitors. In this
case, the load step will cause an output voltage change of:
0.6V
VOUT
∆ITH = gmRVP
∆VOUT
3714f
22
LTC3714
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APPLICATIO S I FOR ATIO
U
Solving for this resistance value:
nominal value of the ITH pin voltage when the error
amplifier input is zero. To set the beginning of the load line
at the regulation point, the ITH pin voltage must be set to
correspond to zero output current. The relation between
voltage and the output current is:
V
OUT ∆ITH
RVP
=
=
(0.6V)gm ∆VOUT
(1.15V)(1.08V)
(0.6V)(1.7mS)(60mV)
= 20.3k
12V
VRNG
1
2
ITH(NOM)
=
=
RSENSE OUT
I
– ∆IL + 0.75V
The gain setting resistance RVP is implemented with two
resistors, RVP1 connected from ITH to ground and RVP2
connectedfromITH toINTVCC. Theparallelcombinationof
these resistors must equal RVP and their ratio determines
12V
0.5V
1
2
0.003Ω 0A – 5.4A + 0.75V
(
)
= 0.55V
9
10
11
12
13
8
7
6
5
4
C
VID2
VID1
VID0
BOOST
TG
SS
0.1µF
RUN/SS
D
B
CMDSH-3
V
IN
V
ON
7V TO 24V
C
R
R
R
PG
100k
C
IN
RNG1
10k
RNG2
B
10µF
25V
×3
90.1k
0.33µF
M1
IRF7811
L1
0.68µH
PGOOD
V
OUT
1.15V/15A
V
SW
RNG
M2
IRF7811
×2
D1
UPS840
C
C
OUT
C1
LTC3714
R
C
R
VP2
270µF
2V
2.2nF
20k
185k
14
19
21
22
20
23
24
15
16
3
I
SENSE
PGND
BG
×3
TH
R
C
VP1
C1
23k
100pF
R
SENSE
2
SGND
0.003Ω
C
0.01µF
ION
1
I
ON
C
VCC
C
100pF
FB
4.7µF
28
27
26
25
18
17
V
INTV
FB
CC
R
F
1Ω
FCB
V
V
IN
C
F
0.1µF
EXTV
5V
OSENSE
CC
R
ON
VID3
OPV
VID4
330k
OPOUT
INTV
0.1µF
IN
CC
–
+
OP
OP
3714 F08
C
C
: UNITED CHEMICON THCR70EIH226ZT
IN
: PANASONIC EEFUE0D271
OUT
L1: SUMIDA CEP125-4712-T007
Figure 9. CPU Core Voltage Regulator with Active Voltage Positioning 1.15V/15A at 300kHz
3714f
23
LTC3714
W U U
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APPLICATIO S I FOR ATIO
Solving for the required values of the resistors:
The modified circuit is shown in Figure 9. Refer to Linear
Technology Design Solutions 10 for additional informa-
tion about output voltage positioning.
5V
5V
RVP1
=
RVP
=
20.3k
5V – ITH(NOM)
5V – 0.55V
PC Board Layout Checklist
= 23k
5V
ITH(NOM)
When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the controller.
5V
0.55V
RVP2
=
RVP
=
20.3k = 185k
C
VCC
LTC3714
+
M1
1
2
28
27
26
25
24
23
22
21
20
M2
D1
BG
INTV
EXTV
CC
V
C
IN
–
–
IN
C
F
PGND
V
IN
R
R
F
3
SENSE
SW
CC
V
C
OUT
OUT
D
B
+
4
ON
VID4
VID3
5
TG
C
B
6
BOOST
VID0
VID1
VID2
RUN/SS
V
OSENSE
7
V
FB
C
ION
C
FB
8
I
ON
9
FCB
C
SS
10
11
12
13
14
SGND 19
18
V
OPOUT
ON
17
16
15
+
PGOOD
OP
–
V
OP
RNG
C
C1
R
C
I
TH
OPV
IN
C
C2
3714 F10
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 10. LTC3714 Layout Diagram
3714f
24
LTC3714
W U U
APPLICATIO S I FOR ATIO
U
These items are also illustrated in Figures 10 and 11.
• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
onepointwhichisthentiedtothePGNDpinclosetothe
source of M2.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and PGND pins.
• Connect the top driver boost capacitor CB closely to the
BOOST and SW pins.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SENSE traces short.
• Connect the VIN pin decoupling capacitor CF closely to
the VIN and PGND pins.
•
Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current.
• VID0-VID4 interface circuitry must return to SGND.
V
IN
C
IN
C
IN
C
IN
C
IN
TO PGND
(PIN 2)
PGND
R
SENSE
SW
M1
M1
M2
SENSE
TO SENSE
(PIN 3)
D1
M2
M2
PGND
L1
C
OUT
C
OUT
C
C
OUT OUT
V
OUT
3714 F11
Figure 11. General Layout of External Power Components
3714f
25
LTC3714
U
TYPICAL APPLICATIO
Performance Data for Intel Compatible Mobile Microprocessor Power Supply with Active Voltage Positioning
Line Transient Reponse from VIN = 9V to 17V Load Transient Reponse for IOUT = 8A to 23A
VIN
1.395V
5V/DIV
VOUT
(1.35V)
50mV/DIV
1.213V
VOUT
50mV/DIV
AC COUPLED
23A
ILOAD
10A/DIV
8A
50µs/DIV
3714 TA02
20µs/DIV
3714 TA03
Efficiency
95
V
= 1.35V
OUT
90
85
80
75
70
V
= 8.5V
IN
V
= 15V
IN
V
= 24V
IN
0
3
6
9
12 15 18 21
LOAD CURRENT (A)
3714 TA04
3714f
26
LTC3714
U
TYPICAL APPLICATIO
Transmeta CrusoeTM Microprocessor Power Supply with Active Voltage Positioning
200k
VID2
3.3V
INTV
CC
VRON
VID1 VID0
3.3V
U1
LTC3714EG
VID1
BAT54
1M
200k
200k
9
10
11
12
13
8
V
IN
VID2
1µF
0.1µF
7
RUN/SS
VID0
BOOST
TG
1k
V
0.01µF
CMDSH-3
1k
6
V
V
ON
IN
2k
100Ω
OUT
5V TO 24V
C
IN
3.2k
5
10µF
35V
×2
IRF7811
L1
POWER GOOD
PGOOD
0.22µF
V
OUT
4
20k
220pF
820pF
13k 1%
0.6V To 1.75V
8A
V
RNG
SW
10k
1.8µH
3
SENSE
+
C
1µF
6.3V
OUT
LTC3714EG
270µF
2V
80.6k 1%
14
19
20
21
22
23
24
18
15
2
I
TH
PGND
BG
×2
1
IRF7811
SGND
FCB
MBRS340
4.7µF
BAT54
0.1µF
10k
28
INTV
CC
1Ω
0.005Ω
1000pF
100pF
V
IN
I
ON
330k
200k
0.1µF
V
IN
27
25
26
17
16
V
V
V
FB
IN
VID4
OSENSE
VID3
3.3V
VID4
200k
5V
3.3V
VID3
EXTV
CC
DPSLP
BAT54C
START
+
OPOUT
OP
R22
100k
–
OPV
IN
OP
0.01µF
75k
1%
V
OUT
100k
1%
453k
1%
START
DPSLP
3714 TA01
U
PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
10.07 – 10.33*
(.397 – .407)
28 27 26 25 24 23 22 21 20 19 18
5.20 – 5.38**
(.205 – .212)
1.73 – 1.99
(.068 – .078)
16 15
17
0° – 8°
7.65 – 7.90
(.301 – .311)
.65
(.0256)
BSC
.13 – .22
.55 – .95
(.005 – .009)
(.022 – .037)
.05 – .21
(.002 – .008)
.25 – .38
(.010 – .015)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
5
7
8
1
2
3
4
6
9 10 11 12 13 14
G28 SSOP 0501
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
Crusoe is a trademark of Transmeta Corporation.
3714f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC3714
U
TYPICAL APPLICATIO
Intel Compatible Mobile Microprocessor Power Supply with Active Voltage Positioning
INTV
3.3V
V
RON
CC
200k
3.3V
2k
200k
200k
9
8
VID2
VID1
VID0
BOOST
TG
0.1µF
100Ω
1µF
1k
10
11
12
13
7
RUN/SS
7V ≤ V ≤ 24V
IN
POWER GOOD
6
V
C
IN
ON
3.2k
0.22µF
10µF
35V
×4
5
IRF7811
×2
L1
0.68µH
10k
PGOOD
V
OUT
0.6V TO 1.75V
23A
4
V
SW
RNG
CMDSH-3
C
3
OUT
IRF7811
+
SENSE
270µF
MBRS
340T3
×3
220pF
100pF
2V
×4
LTC3714
20k
14
19
21
22
20
23
24
18
15
2
200k
1%
I
PGND
R
TH
SENSE
0.003Ω
INTV
CC
1
220pF
SGND
BG
10nF
28
I
INTV
CC
ON
20.5k
1%
+
4.7µF
10V
V
FB
1Ω
27
25
26
17
16
1k
FCB
V
IN
0.1µF
200k
V
VID4
3.3V
OSENSE
200k
3.3V
VID3
EXTV
5V
CC
+
OPOUT
OP
806k
1%
10k
1%
–
INTV
CC
OPV
IN
OP
0.1µF
GMUXSEL
330k
10k
1%
INTV
CC
806k
1%
277k
1%
10k
100Ω
DPSLP#
DPRSLPVR
3714 TA01
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
GN-16 Package, 0.8V Reference, Burst Mode Operation
GN-24 Package, 5-Bit VID, 0.8V , Burst Mode Operation,
LTC1778
Low Duty Cycle, No R
TM Step-Down Controller
SENSE
LTC3711
5-Bit Adjustable, Low Duty Cycle, No R
,
SENSE
REF
Step-Down Controller
0.925V ≤ V
≤ 2V
OUT
LTC3716
LTC3778
Dual Phase, High Efficiency Step-Down Controller
Wide V , No R Step-Down Controller
2-Phase, 5-Bit VID (0.6V to 1.75V), Narrow 36-Pin SSOP, 3.5V ≤ V ≤ 36V
IN
4V ≤ V ≤ 36V, True Current Mode Control, 1A ≤ I ≤ 20A
OUT
IN
SENSE
IN
No R
is a trademark of Linear Technology Corporation.
SENSE
3714f
LT/TP 0602 2K • PRINTED IN USA
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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