LTC3722-1_15_技术文档

LTC3722-1/LTC3722-2

Synchronous Dual Mode

Phase Modulated

Full Bridge Controllers

DESCRIPTION

The LTC^®3722-1/LTC3722-2 phase-shift PWM controllers

provide all of the control and protection functions neces-

sary to implement a high efﬁciency, zero voltage switched

(ZVS), full bridge power converter. Adaptive ZVS circuitry

delays the turn-on signals for each MOSFET independent

of internal and external component tolerances. Manual

delay set mode enables secondary side control operation

or direct control of switch turn-on delays.

FEATURES

n

Adaptive or Manual Delay Control for Zero Voltage

Switching Operation

n

Adjustable Synchronous Rectiﬁcation Timing for

Highest Efﬁciency

Adjustable Maximum ZVS Delay

n

Adjustable System Undervoltage Lockout Hysteresis

n

Programmable Leading Edge Blanking

n

Very Low Start-Up and Quiescent Currents

n

Current Mode (LTC3722-1) or Voltage Mode

The LTC3722-1/LTC3722-2 feature adjustable synchron-

ousrectiﬁertimingforoptimalefﬁciency.AUVLOprogram

input provides accurate system turn-on and turn-off

voltages. The LTC3722-1 features peak current mode

control with programmable slope compensation and

leading edge blanking, while the LTC3722-2 employs

voltage mode control.

(LTC3722-2) Operation

Programmable Slope Compensation

n

V

UVLO and 25mA Shunt Regulator

CC

n

50mA Output Drivers

Soft-Start, Cycle-by-Cycle Current Limiting and

Hiccup Mode Short-Circuit Protection

5V, 15mA Low Dropout Regulator

24-Pin Surface Mount GN Package

n

TheLTC3722-1/LTC3722-2featureextremelylowoperating

and start-up currents. Both devices include a full range of

protection features and are available in the 24-pin surface

mount GN package.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

DirectSense is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

APPLICATIONS

n

Telecommunications, Infrastructure Power Systems

n

Distributed Power Architectures

n

Server Power Supplies

TYPICAL APPLICATION

V

IN

36V TO

72V

C

R1

IN

12V_OUT, 240W Converter Efﬁciency

U2

U1

95

MA

MC

36V

IN

T1

90

85

80

75

L1

L2

LTC3722

V

OUT

12V

48V

IN

72V

IN

C

OUT

MB

MD

T2

RCS

ME

0

2

4

6

8

10 12 14 16 18 20

CURRENT (A)

U3

C1

MF

372212 TA01b

U1, U2: LTC4440 GATE DRIVER

U3: LTC3901 GATE DRIVER

372212 TA01a

372212fb

1

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

V

to GND (Low Impedance Source)........ –0.3V to 10V

CC

V

Output Current................................. Self Regulated

REF

(Chip Self Regulates at 10.3V)

Outputs (A, B, C, D, E, F) Current....................... 100mA

Operating Junction Temperature Range

UVLO to GND..............................................–0.3V to V

All Other Pins to GND

CC

(Note 6).................................................. –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

(Low Impedance Source).......................... –0.3V to 5.5V

(Current Fed)...................................................25mA

V

CC

PIN CONFIGURATION

LTC3722-1

LTC3722-2

TOP VIEW

SYNC

DPRG

CS

1

2

3

4

5

6

7

8

9

24

SYNC

RAMP

CS

1

2

3

4

5

6

7

8

9

24

23

22

21

20

19

18

17

16

15

14

13

C

T

23 GND

GND

22 PGND

21 OUTA

20 OUTB

19 OUTC

PGND

OUTA

OUTB

OUTC

COMP

RLEB

FB

COMP

DPRG

FB

SS

18

SS

V

CC

NC

17 OUTD

16 OUTE

15 OUTF

NC

OUTD

OUTE

OUTF

PDLY

SBUS 10

ADLY 11

UVLO 12

SBUS 10

ADLY 11

UVLO 12

14

V

REF

13 SPRG

SPRG

GN PACKAGE

24-LEAD NARROW PLASTIC SSOP

GN PACKAGE

24-LEAD NARROW PLASTIC SSOP

T

JMAX

= 125°C, θ = 100°C/W

T = 125°C, θ = 100°C/W

JMAX JA

JA

ORDER INFORMATION

LEAD FREE FINISH

LTC3722EGN-1#PBF

LTC3722EGN-2#PBF

LTC3722IGN-1#PBF

LTC3722IGN-2#PBF

LTC3722HGN-1#PBF

TAPE AND REEL

PART MARKING

LTC3722EGN-1

LTC3722EGN-2

LTC3722IGN-1

LTC3722IGN-2

LTC3722HGN-1

PACKAGE DESCRIPTION

24-Lead Plastic SSOP

TEMPERATURE RANGE

–40°C to 85°C

LTC3722EGN-1#TRPBF

LTC3722EGN-2#TRPBF

LTC3722IGN-1#TRPBF

LTC3722IGN-2#TRPBF

LTC3722HGN-1#TRPBF

–40°C to 85°C

–40°C to 150°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

372212fb

2

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the speciﬁed operating

junction temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 9.5V, C_T= 270pF, R_DPRG= 60.4k, R_SPRG= 100k, unless

otherwise noted (Note 6).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input Supply

V

Under Voltage Lockout

UVLO Hysteresis

Measured on V

10.25

4.2

10.5

V

CCUV

CCHY

CCST

CC

3.8

I

Start-Up Current

V

= V

– 0.3V

UVLO

CC

l

LTC3722E-1/LTC3722I-1/LTC3722E-2/LTC3722I-2

LTC3722H-1

145

230

250

µA

I

Operating Current

No Load on Outputs

Current into V = 10mA

5

8

mA

V

CCRN

V

Shunt Regulator Voltage

Shunt Resistance

10.3

1.1

5.0

10

10.8

3.5

SHUNT

CC

R

Current into V = 10mA to 17mA

Ω

SHUNT

CC

SUVLO

System UVLO Threshold

System UVLO Hysteresis Current

Measured on UVLO Pin, 10mA into V

Current Flows Out of UVLO Pin

4.8

8.5

5.2

V

CC

SHYST

11.5

µA

Delay Blocks

DTHR

l

Delay Pin Threshold

ADLY and PDLY

SBUS = 1.5V

SBUS = 2.25V

1.4

2.1

1.5

2.25

1.6

2.4

V

DHYS

Delay Hysteresis Current

ADLY and PDLY

SBUS = 1.5V, ADLY/PDLY = 1.7V

1.3

mA

DTMO

DFXT

DFTM

Delay Timeout

R

= 60.4K

100

4

ns

V

DPRG

Fixed Delay Threshold

Fixed Delay Time

Measured on SBUS

SBUS = V , ADLY, PDLY = 1V

70

ns

REF

Phase Modulator

I

CS

CS Discharge Current

CS = 1V, COMP = 0V, C = 4V,

50

mA

T

LTC3722-1 Only

I

Slope Compensation Current

Measured on CS, C = 1V

30

68

µA

SLP

T

C = 2.25V

T

l

DC

Maximum Phase Shift

Minimum Phase Shift

COMP = 4.5V

COMP = 0V

95

98.5

0

%

MAX

0.5

MIN

Oscillator

OSCI

Initial Accuracy

Total Variation

T = 25°C, C = 270pF

225

215

250

2.2

275

285

kHz

V

A

T

l

OSCT

V

CC

= 6.5V to 9.5V

OSCV

C Ramp Amplitude

T

Measured on C

T

OSYT

SYNC Threshold

Measured on SYNC

1.6

1.9

2.2

V

OSYW

Minimum SYNC Pulse Width

SYNC Frequency Range

Measured at Outputs (Note 2)

100

1000

ns

OSYR

kHz

Error Ampliﬁer

V

FB Input Voltage

FB Input Range

Open-Loop Gain

Input Bias Current

Output High

COMP = 2.5V (Note 4)

Measured on FB (Note 5)

COMP = 1V to 3V (Note 4)

COMP = 2.5V (Note 4)

Load on COMP = –100µA

Load on COMP = 100µA

COMP = 2.5V

1.172

–0.3

70

1.204

1.236

2.5

V

FB

FBI

A

VOL

90

5

dB

nA

V

IIB

20

V

4.7

4.92

0.18

800

5

OH

Output Low

0.4

V

OL

I

Output Source Current

Output Sink Current

400

2

µA

mA

SOURCE

SINK

COMP = 2.5V

372212fb

3

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the speciﬁed operating

junction temperature range, otherwise speciﬁcations are at T_A= 25°C. V_CC= 9.5V, C_T= 270pF, R_DPRG= 60.4k, R_SPRG= 100k, unless

otherwise noted (Note 6).

SYMBOL PARAMETER

Reference

CONDITIONS

MIN

TYP

MAX

UNITS

V

Initial Accuracy

Load Regulation

Line Regulation

Total Variation

T = 25°C, Measured on V

REF

4.925

5.00

2

5.075

15

V

mV

V

REF

A

REFLD

REFLN

REFTV

REFSC

Outputs

Load on V = 100µA to 5mA

REF

V

= 6.5V to 9.5V

0.9

10

CC

l

Line, Load

4.900

18

5.000

30

5.100

45

Short-Circuit Current

V

REF

Shorted to GND

mA

OUTH(x) Output High Voltage

OUTL(x) Output Low Voltage

I

= –50mA

7.9

8.4

0.6

22

12

5

V

OUT(x)

= 50mA

1

R

Pull-Up Resistance

Pull-Down Resistance

Rise Time

= –50mA to –10mA

= 50pF (Note 8)

= 100k

30

20

15

Ω

ns

HI(x)

LO(x)

t

C

r(x)

f(x)

OUT(x)

Fall Time

5

SDEL

SYNC Driver Turn-0ff Delay

R

180

SPRG

Current Limit and Shutdown

CLPP

Pulse by Pulse Current Limit Threshold Measured on CS

LTC3722E-1/LTC3722I-1/LTC3722E-2/LTC3722I-2

270

300

330

340

mV

LTC3722H-1

CLSD

CLDEL

SSI

Shutdown Current Limit Threshold

Current Limit Delay to Output

Soft-Start Current

Measured on CS

0.55

0.65

80

0.73

V

ns

µA

V

100mV Overdrive on CS (Notes 3, 7)

SS = 2.5V

7

12

17

0.1

3.5

SSR

FLT

Soft-Start Reset Threshold

Fault Reset Threshold

Measured on SS

0.7

4.5

0.4

3.9

Measured on SS

V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

characterization and correlation with statistical process controls. The

LTC3722I-1/LTC3722I-2 are guaranteed over the –40°C to 85°C operating

junction temperature range and the LTC3722H-1 is guaranteed over the

–40°C to 150°C operating junction temperature range.

Note 2: Sync amplitude = 5V , pulse width = 50ns. Verify output (A-F)

frequency = one-half sync frequency.

High junction temperatures degrade operating lifetimes; operating lifetime

is derated for junction temperatures greater than 125°C. Note that the

maximum ambient temperature consistent with these speciﬁcations is

determined by speciﬁc operating conditions in conjunction with board

layout, the rated package thermal impedance and other environmental

factors.

P-P

Note 3: Includes leading edge blanking delay, R = 20k.

LEB

Note 4: FB is driven by a servo-loop ampliﬁer to control V

for these

COMP

tests.

Note 5: Set FB to –0.3V, 2.5V and insure that COMP does not phase invert.

Note 6: The LTC3722 is tested under pulsed load condition such that

Note 7: Guaranteed by design, not tested in production.

Note 8: Rise time is measured from the 10% to 90% points of the rising

edge of the driver output signal. Fall time is measured from the 90% to

10% points of the falling edge of the driver output signal.

T ≈ T . The LTC3722E-1/LTC3722E-2 are guaranteed to meet performance

J

A

speciﬁcations from 0°C to 85°C. Speciﬁcations over the –40°C to

85°C operating junction temperature range are assured by design,

372212fb

4

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

TYPICAL PERFORMANCE CHARACTERISTICS

Oscillator Frequency

vs Temperature

260

Start-Up I_CCvs V_CC

V_CCvs I_SHUNT

200

150

100

50

10.50

10.25

10.00

9.75

T

= 25°C

T

= 25°C

C = 270pF

T

A

250

240

230

0

9.50

0

2

4

6

8

10

0

10

20

30

40

50

–50 –30 –10 10 30 50 70 90 110 130 150

TEMPERATURE (°C)

V

(V)

I

(mA)

CC

SHUNT

372212 G01

372212 G02

372212 G03

Leading Edge Blanking Time

vs R_LEB

V_REFvs I_REF

V_REFvs Temperature

350

300

250

200

150

100

50

5.05

5.00

4.95

4.90

4.85

4.80

5.01

T

= 25°C

A

T

= 25°C

A

5.00

4.99

T

= 85°C

A

4.98

4.97

4.96

T

= –40°C

A

0

20

(mA)

5

10 15

25 30 35 40

0

10 20 30 40 50

70

90 100

80

–50 –30 –10 10 30 50 70 90 110 130 150

60

(k)

I

R

TEMPERATURE (°C)

REF

LEB

372212 G04

372212 G05

372212 G06

Delay Hysteresis Current

vs Temperature

Error Ampliﬁer Gain/Phase

Start-Up I_CCvs Temperature

1.302

1.300

1.298

1.296

1.294

1.292

1.290

1.288

1.286

1.284

1.282

1.280

190

180

170

160

150

140

130

120

110

T

= 25°C

SBUS = 1.5V

A

100

80

60

40

20

0

–180

–270

–360

100

10

100

1k

10k 100k

1M

10M

–60

0

30

60

90 120 150

–30

–60 –30

0

30

150

60

90 120

FREQUENCY (Hz)

TEMPERATURE (°C)

372212 G07

372212 G09

372212 G08

372212fb

5

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

TYPICAL PERFORMANCE CHARACTERISTICS

Delay Pin Threshold

vs Temperature

Slope Current vs Temperature

V_CCShunt Voltage vs Temperature

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

1.4

90

80

70

60

50

40

30

20

10

10.5

10.4

I

= 10mA

CC

SBUS = 2.25V

C

= 2.25V

T

10.3

10.2

10.1

10.0

9.9

C

= 1V

T

SBUS = 1.5V

9.8

0

60

TEMPERATURE (°C)

120 150

–60

0

30

60

90 120

–60 –30

0

30

90

–30

150

–60 –30

0

30

150

60

90 120

TEMPERATURE (°C)

372212 G11

372212 G12

372212 G10

ZVS Delay in Fixed Mode,

SBUS = 5V

FB Input Voltage vs Temperature

Delay Timeout vs R_DPRG

1.210

300

250

200

150

100

50

300

250

200

150

100

50

T

= 25°C

T

= 25°C

A

1.209

1.208

SBUS = 2.25V

ADLY = PDLY = 2.25V

ADLY = PDLY = 1.5V

SBUS = 1.5V

1.207

1.206

1.205

1.204

1.203

SBUS = 1.125V

ADLY = PDLY = 1.125V

1.202

0

–30

0

60

90 120 150

–60

30

10

110

160

210

260

310

10

110

160

210

260

310

60

TEMPERATURE (°C)

R

DPRG

(kΩ)

R

DPRG

(kΩ)

372212 G14

372212 G15

372212 G13

Synchronous Driver Turn-Off

Delay in Fixed Mode

Synchronous Driver Turn-Off Delay in

Adaptive Mode, SBUS = 1.5V

350

300

250

T

= 25°C

T

= 25°C

A

260

220

180

140

100

60

B HI-F LOW

A HI-E LOW

200

150

100

50

0

20

60

110

(kΩ)

210

10

160

10

70

110 130 150 170 190

(kΩ)

30 50

90

R

SPRG

R

SPRG

372212 G17

372212 G16

372212fb

6

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

PIN FUNCTIONS ^{(LTC3722-1/LTC3722-2)}

SYNC (Pin 1/Pin 1): Synchronization Input/Output for the

Oscillator. The input threshold for SYNC is approximately

1.9V, making it compatible with both CMOS and TTL logic.

Terminate SYNC with a 5.1k resistor to GND.

SBUS (Pin 10/Pin 10): Line Voltage Sense Input. SBUS is

connected to the main DC voltage feed by a resistive volt-

age divider when using adaptive ZVS control. The voltage

divider is designed to produce 1.5V on SBUS at nominal

V . If SBUS is tied to V , the LTC3722-1/LTC3722-2 is

IN

REF

DPRG (Pin 2/Pin 5): Programming Input for Default Zero

conﬁgured for ﬁxed mode ZVS control.

Voltage Transition (ZVS) Delay. Connect a resistor from

DPRGtoV tosetthemaximumturnondelayforoutputs

ADLY(Pin11/Pin11):ActiveLegDelayCircuitInput.ADLY

is connected through a voltage divider to the right leg of

the bridge in adaptive ZVS mode. In ﬁxed ZVS mode, a

voltage between 0V and 2.5V on ADLY, programs a ﬁxed

ZVS delay time for the active leg transition.

REF

A, B, C, D. The nominal voltage on DPRG is 2V.

RAMP (NA/Pin 2): Input to Phase Modulator Comparator

for LTC3722-2 only. The voltage on RAMP is internally

level shifted by 650mV.

UVLO (Pin 12/Pin 12): Input to Program System Turn-

On and Turn-Off Voltages. The nominal threshold of the

UVLO comparator is 5V. UVLO is connected to the main

DC system feed through a resistor divider. When the

UVLO threshold is exceeded, the LTC3722-1/LTC3722-2

commences a soft-start cycle and a 10µA (nominal) cur-

rent is fed out of UVLO to program the desired amount of

system hysteresis. The hysteresis level can be adjusted

by changing the resistance of the divider.

CS (Pin 3/Pin 3): Input to Phase Modulator for the

LTC3722-1. Input to pulse-by-pulse and overload current

limitcomparators,outputofslopecompensationcircuitry.

The pulse by pulse comparator has a nominal 300mV

threshold, while the overload comparator has a nominal

650mV threshold.

COMP (Pin 4/Pin 4): Error Ampliﬁer Output, Inverting

Input to Phase Modulator.

R

(Pin 5/NA): Timing Resistor for Leading Edge Blank-

SPRG (Pin 13/Pin 13): A resistor is connected between

SPRGandGNDtosettheturn-offdelayforthesynchronous

rectiﬁer driver outputs (OUTE and OUTF). The nominal

voltage on SPRG is 2V.

LEB

ing. Use a 10k to 100k resistor to program from 40ns to

310ns of leading edge blanking of the current sense signal

on CS for the LTC3722-1. A 1% tolerance resistor is

recommended. The LTC3722-2 has a ﬁxed blanking time

of approximately 80ns.

V

(Pin 14/Pin 14): Output of the 5V Reference. V

REF

is capable of supplying up to 18mA to external circuitry.

REF

FB (Pin 6/Pin 6): Error Ampliﬁer Inverting Input. This is

the voltage feedback input for the LTC3722. The nominal

regulation voltage at FB is 1.204V.

V

should be decoupled to GND with a 1µF ceramic

capacitor.

OUTF (Pin 15/Pin 15): 50mA Driver for Synchronous

Rectiﬁer Associated with OUTB and OUTC.

SS(Pin7/Pin7):Soft-Start/RestartDelayCircuitryTiming

Capacitor.AcapacitorfromSStoGNDprovidesacontrolled

ramp of the current command (LTC3722-1), or duty cycle

(LTC3722-2).DuringoverloadconditionsSSisdischarged

to ground initiating a soft-start cycle.

OUTE (Pin 16/Pin 16): 50mA Driver for Synchronous

Rectiﬁer Associated with OUTA and OUTD.

OUTD (Pin 17/Pin 17): 50mA Driver for Low Side of the

Full Bridge Active Leg.

NC (Pin 8/Pin 8): No Connection. Tie this pin to GND.

V

(Pin 18/Pin 18): Supply Voltage Input to the

CC

PDLY (Pin 9/Pin 9): Passive Leg Delay Circuit Input. PDLY

is connected through a voltage divider to the left leg of

the bridge in adaptive ZVS mode. In ﬁxed ZVS mode, a

voltage between 0V and 2.5V on PDLY, programs a ﬁxed

ZVS delay time for the passive leg transition.

LTC3722-1/LTC3722-2 and 10.25V Shunt Regulator.

The chip is enabled after V has risen high enough to

CC

allow the V shunt regulator to conduct current and the

CC

UVLO comparator threshold is exceeded. Once the V

CC

shunt regulator has turned on, V can drop to as low as

CC

6V (typ) and maintain operation.

372212fb

7

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

PIN FUNCTIONS ^{(LTC3722-1/LTC3722-2)}

OUTC (Pin 19/Pin 19): 50mA Driver for High Side of the

Full Bridge Active Leg.

GND (Pin 23/Pin 23): All circuits other than the output

drivers in the LTC3722 are referenced to GND. Use of a

ground plane is recommended but not absolutely neces-

sary.

OUTB (Pin 20/Pin 20): 50mA Driver for Low Side of the

Full Bridge Passive Leg.

C (Pin 24/Pin 24): Timing Capacitor for the Oscillator.

T

OUTA (Pin 21/Pin 21): 50mA Driver for High Side of the

Full Bridge Passive Leg.

Use a 5% or better low ESR ceramic capacitor for best

results.

PGND (Pin 22/Pin 22): Power Ground for the LTC3722.

The output drivers of the LTC3722 are referenced to

PGND. Connect the ceramic V bypass capacitor di-

CC

rectly to PGND.

BLOCK DIAGRAM

LTC3722-1 Current Mode SYNC Phase-Shift PWM

V

UVLO

12

V

C

T

SYNC

1

SPRG DPRG

13

SBUS

10

CC

REF

18

14

24

2

PDLY

9

V

UVLO

5V

CC

REF AND LDO

1.2V

OSC

10.25V = ON

6V = OFF

REF GOOD

OUTA

21

SYSTEM

FB

6

–

+

–

PASSIVE

DELAY

UVLO

Q

1 = ENABLE

0 = DISABLE

OUTB

20

T

QB

1.2V

5V

V

CC

GOOD

ERROR

AMPLIFIER

R1

50k

COMP

4

–

+

OUTE

16

SYNC

RECTIFIER

DRIVE

+

–

OUTF

15

LOGIC

PHASE

MODULATOR

R2

650mV

14.9k

M1

QB

R

S

OUTC

19

20Ω

V

REF

Q

R

S

QB

ACTIVE

DELAY

12µA

SS

7

OUTD

17

SHUTDOWN

CURRENT

LIMIT

ADLY

11

+

–

FAULT

LOGIC

650mV

PGND

22

M2

SLOPE

COMPENSATION

C /R

T

CS

3

BLANK

+

–

5

23

PULSE BY PULSE

CURRENT LIMIT

300mV

R

LEB

GND

372212 BD01

372212fb

8

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

BLOCK DIAGRAM

LTC3722-2 Voltage Mode SYNC Phase-Shift PWM

V

UVLO

12

V

C

T

SYNC

1

SPRG DPRG

13

SBUS

10

CC

REF

18

14

24

5

PDLY

9

V

UVLO

5V

CC

REF AND LDO

1.2V

OSC

10.25V = ON

6V = OFF

REF GOOD

OUTA

21

SYSTEM

ERROR

AMPLIFIER

FB

6

–

+

–

PASSIVE

DELAY

UVLO

Q

1 = ENABLE

0 = DISABLE

OUTB

20

T

QB

+

1.2V

5V

V

CC

GOOD

R1

50k

COMP

4

–

+

OUTE

16

SYNC

RECTIFIER

DRIVE

2

OUTF

15

LOGIC

+

–

PHASE

MODULATOR

RAMP

650mV

QB

R

S

OUTC

19

V

REF

QB

Q

R

S

ACTIVE

DELAY

12µA

SS

7

OUTD

17

SHUTDOWN

CURRENT

LIMIT

ADLY

11

+

–

FAULT

LOGIC

650mV

PGND

22

M2

372212 BD02

CS

3

BLANK

300mV

+

–

23

PULSE BY PULSE

CURRENT LIMIT

GND

372212fb

9

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

TIMING DIAGRAM

PASSIVE LEG

DELAY

ACTIVE LEG

DELAY

OUTA

OUTB

OUTC

OUTD

COMP

RAMP

COMP

OUTE

SYNC TURN OFF

DELAY (PROGRAMMABLE)

SYNC TURN OFF

DELAY (PROGRAMMABLE)

OUTF

NOTE: SHADED AREAS CORRESPOND TO POWER DELIVERY PULSES.

372212 TD01

OPERATION

Phase-Shift Full Bridge PWM

generallyundesirableparasiticelementspresentwithinthe

power stage. The parasitic elements are utilized to drive

near lossless switching transitions for all of the external

power MOSFETs.

Conventionalfullbridgeswitchingpowersupplytopologies

are often employed for high power, isolated DC/DC and

off-line converters. Although they require two additional

switchingelements,substantiallygreaterpowerandhigher

efﬁciency can be attained for a given transformer size

comparedtothemorecommonsingle-endedforwardand

ﬂybackconverters.Theseimprovementsarerealizedsince

the full bridge converter delivers power during both parts

of the switching cycle, reducing transformer core loss

and lowering voltage and current stresses. The full bridge

converter also provides inherent automatic transformer

ﬂux reset and balancing due to its bidirectional drive

conﬁguration. As a result, the maximum duty cycle range

is extended, further improving efﬁciency. Soft-switching

variations on the full bridge topology have been proposed

to improve and extend its performance and application.

These zero voltage switching (ZVS) techniques exploit the

LTC3722-1/LTC3722-2 phase-shift PWM controllers pro-

vide enhanced performance and simplify the design task

required for a ZVS phase-shifted full bridge converter.

The primary attributes of the LTC3722-1/LTC3722-2 as

compared to currently available solutions include:

1. Truly adaptive and accurate (DirectSense^TMtechnology)

ZVS with programmable timeout.

Beneﬁt: higher efﬁciency, higher duty cycle capability,

eliminates external trim.

2. Fixed ZVS capability.

Beneﬁt: enables secondary-side control and simpliﬁes

external circuit.

372212fb

10

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

3 Internally generated drive signals with programmable

turn-off for current doubler synchronous rectiﬁers.

elements are detailed in this data sheet. The secondary

voltage of the transformer is the primary voltage divided

by the transformer turns ratio. Similar to a buck converter,

the secondary square wave is applied to an output ﬁlter

inductor and capacitor to produce a well regulated DC

output voltage.

Beneﬁt: eliminates external glue logic, drivers, optimal

timing for highest efﬁciency.

4. Programmable (single resistor) leading edge blanking.

Beneﬁt: prevents spurious operation, reduces external

ﬁltering required on CS.

Switching Transitions

The phase-shifted full bridge can be described by four

primary operating states. The key to understanding how

ZVS occurs is revealed by examining the states in detail.

Each full cycle of the transformer has two distinct periods

in which power is delivered to the output, and two “free-

wheeling” periods. The two sides of the external bridge

havefundamentallydifferentoperatingcharacteristicsthat

become important when designing for ZVS over a wide

load current range. The left bridge leg is referred to as the

passive leg, while the right leg is referred to as the active

leg. The following descriptions provide insight as to why

these differences exist.

5. Programmable (single resistor) slope compensation.

Beneﬁt: eliminates external glue circuitry.

6. Optimized current mode control architecture.

Beneﬁt: eliminates glue circuitry, less overshoot at

start-up, faster recovery from system faults.

7. Programmable system undervoltage lockout and hys-

teresis.

Beneﬁt: provides an accurate turn-on voltage for power

supply and reduces external circuitry.

Asaresult,theLTC3722-1/LTC3722-2makestheZVStopol-

ogy feasible for a wider variety of applications, including

those at lower power levels.

State 1 (Power Pulse 1)

As shown in Figure 1, State 1 begins with MA, MD and MF

“ON” and MB, MC and ME “OFF.” During the simultane-

ous conduction of MA and MD, the full input voltage is

applied across the transformer primary winding and fol-

The LTC3722-1/LTC3722-2 control four external power

switches in a full bridge arrangement. The load on the

bridge is the primary winding of a power transformer. The

diagonal switches in the bridge connect the primary wind-

ing between the input voltage and ground every oscillator

cycle. The pair of switches that conduct are alternated by

an internal ﬂip-ﬂop in the LTC3722-1/LTC3722-2. Thus,

the voltage applied to the primary is reversed in polarity

on every switching cycle and each output drive signal is

one-half the frequency of the oscillator. The on-time of

each driver signal is slightly less than 50%. The on-time

overlap of the diagonal switch pairs is controlled by the

LTC3722-1/LTC3722-2 phase modulation circuitry (refer

to the Block and Timing Diagrams). This overlap sets the

approximate duty cycle of the converter. The LTC3722-1/

LTC3722-2 driver output signals (OUTA to OUTF) are

optimized for interface with an external gate driver IC or

buffer. External power MOSFETs A and C require high side

driver circuitry, while B and D are ground referenced and E

and F are ground referenced but on the secondary-side of

the isolation barrier. Methods for providing drive to these

lowing the dot convention, V /N is applied to the left side

IN

of LO1 allowing current to increase in LO1. The primary

current during this period is approximately equal to the

output inductor current (LO1) divided by the transformer

turns ratio plus the transformer magnetizing current

(V • t )/(L

• 2). MD turns off and ME turns on at

IN ON

the end of State 1.

MAG

State 2 (Active Transition and Freewheel Interval)

MDturnsoffwhenthephasemodulatorcomparatortransi-

tions. At this instant, the voltage on the MD/MC junction

begins to rise towards the applied input voltage (V ).

IN

The transformer’s magnetizing current and the reﬂected

output inductor current propels this action. The slew rate

is limited by MOSFET MC and MD’s outputcapacitance

(C ), snubbing capacitance and the transformer inter-

OSS

winding capacitance. The voltage transition on the active

leg from the ground reference point to V will always

IN

372212fb

11

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

State 1

POWER PULSE 1

V

OUT

V

IN

L01

L02

MA

MB

MC

MD

LOAD

N:1

+

MF

ME

I

≈ I /N + (V • T )/L

P

L01

IN

ON

MAG

PRIMARY AND

SECONDARY SHORTED

State 2

State 3

State 4

ACTIVE

TRANSITION

FREEWHEEL

INTERVAL

V

OUT

MA

MB

MC

MD

MA

MB

MC

MD

LOAD

MF

ME

PASSIVE

TRANSITION

MA

MB

MC

MD

POWER PULSE 2

V

OUT

MA

MB

MC

LOAD

MD

+

MF

ME

372212 F01

372212fb

12

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

occur, independent of load current as long as energy in

the transformer’s magnetizing and leakage inductance is

greater than the capacitive energy. That is, 1/2 • (LM + LI)

When the voltage on the passive leg nears GND, MOSFET

MB is commanded “ON” by the ZVS circuitry. Current

continues to increase in the leakage and external series

inductance which is opposite in polarity to the reﬂected

output inductor current. When this current is equal in

magnitude to the reﬂected output current, the primary

currentreversesdirection,theoppositesecondarywinding

becomes forward biased and a new power pulse is initi-

ated. The time required for the current reversal reduces

the effective maximum duty cycle and must be considered

when computing the power transformer turns ratio. If

ZVS is required over the entire range of loads, a small

commutating inductor is added in series with the primary

to aid with the passive leg transition, since the leakage

inductance alone is usually not sufﬁcient and predictable

enough to guarantee ZVS over the full load range.

• IM2 > 1/2 • 2 • COSS • V 2 — the worst case occurs

IN

when the load current is zero. This condition is usually

easytomeet. Themagnetizingcurrentisvirtuallyconstant

duringthistransitionbecausethemagnetizinginductance

has positive voltage applied across it throughout the low

to high transition. Since the leg is actively driven by this

current source, it is called the active or linear transition.

When the voltage on the active leg has risen to V ,

IN

MOSFET MC is switched on by the ZVS circuitry. The

primary current now ﬂows through the two high side

MOSFETs (MA and MC). The transformer’s secondary

windings are electrically shorted at this time since both

ME and MF are “ON”. As long as positive current ﬂows

in LO1 and LO2, the transformer primary (magnetizing)

inductance is also shorted through normal transformer

action. MA and MF turn off at the end of State 2.

State 4 (Power Pulse 2)

During power pulse 2, current builds up in the primary

winding in the opposite direction as power pulse 1. The

primary current consists of reﬂected output inductor cur-

rentandcurrentduetotheprimarymagnetizinginductance.

At the end of State 4, MOSFET MC turns off and an active

transition, essentially similar to State 2 but opposite in

direction (high to low), takes place.

State 3 (Passive Transition)

MA turns off when the oscillator timing period ends, i.e.,

the clock pulse toggles the internal ﬂip-ﬂop. At the instant

MA turns off, the voltage on the MA/MB junction begins to

decaytowardsthelowersupply(GND).Theenergyavailable

to drive this transition is limited to the primary leakage

inductance and added commutating inductance which

Zero Voltage Switching (ZVS)

have (I

+ I /2N) ﬂowing through them initially. The

MAG

OUT

Alosslessswitchingtransitionrequiresthattherespective

full bridge MOSFETs be switched to the “ON” state at the

exactinstanttheirdrain-to-sourcevoltageiszero.Delaying

theturn-onresultsinlowerefﬁciencyduetocirculatingcur-

rent ﬂowing in the body diode of the primary side MOSFET

rather than its low resistance channel. Premature turn-on

produceshardswitchingoftheMOSFETs,increasingnoise

and power dissipation.

magnetizing and output inductors do not contribute any

energy because they are effectively shorted as mentioned

previously,signiﬁcantlyreducingtheavailableenergy.This

is the major difference between the active and passive

transitions. If the energy stored in the leakage and com-

mutating inductance is greater than the capacitive energy,

the transition will be completed successfully. During the

transition, an increasing reverse voltage is applied to the

leakageandcommutatinginductances,helpingtheoverall

primary current to decay. The inductive energy is thus

resonantly transferred to the capacitive elements, hence,

the term passive or resonant transition. Assuming there

is sufﬁcient inductive energy to propel the bridge leg to

GND, the time required will be approximately equal to:

LTC3722-1/LTC3722-2 Adaptive Delay Circuitry

TheLTC3722-1/LTC3722-2monitorsboththeinputsupply

and instantaneous bridge leg voltages, and commands

a switching transition when the expected zero voltage

condition is reached. DirectSense technology provides

optimal turn-on delay timing, regardless of input voltage,

output load, or component tolerances. The DirectSense

π

LC

2

technique requires only a simple voltage divider sense

372212fb

13

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

network to implement. If there is not enough energy to

fully commutate the bridge leg to a ZVS condition, the

LTC3722-1/LTC3722-2 automatically overrides the Di-

rectSense circuitry and forces a transition. The override

or default delay time is programmed with a resistor from

delays exist between the time at which the LTC3722-1/

LTC3722-2 controller output transitions, to the time at

which the power MOSFET switches on due to MOSFET

turn-on delay and external driver circuit delay. Ideally, we

want the power MOSFET to switch at the instant there

is zero volts across it. By setting a threshold voltage for

ADLY and PDLY corresponding to several volts across the

MOSFET, the LTC3722-1/LTC3722-2 can anticipate a zero

voltage VDS and signal the external driver and switch to

turn-on. The amount of anticipation can be tailored for

anyapplicationbymodifyingtheupperdividerresistor(s).

The LTC3722-1/LTC3722-2 DirectSense circuitry sources

a trimmed current out of PDLY and ADLY (proportional

to SBUS) after a low to high level transition occurs. This

provides hysteresis and noise immunity for the PDLY and

ADLYcircuitry,andsetsthehightolowthresholdonADLYor

PDLY to nearly the same level as the low to high threshold,

thereby making the upper and lower MOSFET VDS switch

DPRG to V

.

REF

Adaptive Mode

The LTC3722-1/LTC3722-2 are conﬁgured for adaptive

delay sensing with three pins, ADLY, PDLY and SBUS.

ADLY and PDLY sense the active and passive delay legs

respectively via a voltage divider network, as shown in

Figure 2.

V

IN

A

C

D

R2

R1

ADLY

SBUS

PDLY

R5

R6

points virtually identical, independent of V .

IN

B

Example: V = 48V nominal (36V to 72V)

IN

R3

1k

R4

1k

1. Set up SBUS: 1.5V is desired on SBUS with V = 48V.

IN

R

CS

Set divider current to 100µA.

1.5V

372212 F02

R1=

R2 =

= 15k

100µA

Figure 2. Adaptive Mode

48V − 1.5V

= 465k

The threshold voltage on PDLY and ADLY for both the ris-

ing and falling transitions is set by the voltage on SBUS.

A buffered version of this voltage is used as the threshold

100µA

An optional small capacitor (0.001µF) can be added

across R1 to decouple noise from this input.

level for the internal DirectSense circuitry. At nominal V ,

IN

the voltage on SBUS is set to 1.5V by an external voltage

2. Set up ADLY and PDLY: 7V of anticipation is desired

in this circuit to account for the delays of the external

MOSFET driver and gate drive components.

divider between V and GND, making this voltage directly

IN

proportionaltoV .TheLTC3722-1/LTC3722-2DirectSense

circuitry uses this characteristic to zero voltage switch

all of the external power MOSFETs, independent of input

voltage.

R3, R4 = 1k, sets a nominal 1.5mA in the divider chain

at the threshold.

ADLY and PDLY are connected through voltage dividers to

the active and passive bridge legs respectively. The lower

resistor in the divider is set to 1k. The upper resistor in

the divider is selected for the desired positive transition

trip threshold.

(48V − 7V − 1.5V)

1.5mA

use (2) equal 13k segments.

R5,R6 =

= 26.3k,

To set up the ADLY and PDLY resistors, ﬁrst determine at

whatdraintosourcevoltagetoturn-ontheMOSFETs.Finite

372212fb

14

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

Fixed Delay Mode

Powering the LTC3722-1/LTC3722-2

TheLTC3722-1/LTC3722-2providestheﬂexibilitythrough The LTC3722-1/LTC3722-2 utilize an integrated V shunt

CC

the SBUS pin to disable the DirectSense delay circuitry regulator to serve the dual purposes of limiting the volt-

and enable ﬁxed ZVS delays. The level of ﬁxed ZVS delay age applied to V as well as signaling that the chip’s bias

CC

is proportional to the voltage programmed through the voltage is sufﬁcient to begin switching operation (under-

voltage divider on the PDLY and ADLY pins (see Figure 3 voltage lockout). With its typical 10.2V turn-on voltage

for more detail).

and 4.2V UVLO hysteresis, the LTC3722-1/LTC3722-2

is tolerant of loosely regulated input sources such as an

V

REF

auxiliary transformer winding. The V shunt is capable

CC

R1

R2

R3

SBUS

PDLY

of sinking up to 25mA of externally applied current. The

UVLO turn-on and turn-off thresholds are derived from

an internally trimmed reference making them extremely

accurate. In addition, the LTC3722-1/LTC3722-2 exhibits

very low (145µA typ) start-up current that allows the use

of 1/8W to 1/4W trickle charge start-up resistors.

ADLY

372212 F03

Figure 3. Setup for Fixed ZVS Delays

The trickle charge resistor should be selected as follows:

10.7V

Programming Adaptive Delay Time-Out

R_START(MAX)= V

−

IN(MIN)

250µA

TheLTC3722-1/LTC3722-2controllersincludeafeatureto

program the maximum time delay before a bridge switch

turn on command is summoned. This function will come

into play if there is not enough energy to commutate a

bridge leg to the opposite supply rail, therefore bypass-

ing the adaptive delay circuitry. The time delay can be

set with an external resistor connected between DPRG

Adding a small safety margin and choosing standard

values yields:

APPLICATION

DC/DC

V

RANGE

R

START

IN

36V TO 72V

100k

430k

1.4M

Off-Line

85V to 270V

RMS

PFC Preregulator

390V

and V

(see Figure 4). The nominal regulated voltage

DC

REF

on DPRG is 2V. The external resistor programs a current

which ﬂows into DPRG. The delay can be adjusted from

approximately 35ns to 300ns, depending on the resistor

value. If DPRG is left open, the delay time is approximately

400ns. The amount of delay can also be modulated based

onanexternalcurrentsourcethatfeedscurrentintoDPRG.

Care must be taken to limit the current fed into DPRG to

350µA or less.

V

should be bypassed with a 0.1µF to 1µF multilayer

CC

ceramic capacitor to decouple the fast transient currents

demanded by the output drivers and a bulk tantalum or

electrolytic capacitor to hold up the V supply before

CC

the bootstrap winding, or an auxiliary regulator circuit

takes over.

t_DELAY

C_HOLDUP= (I_CC+ I_DRIVE) •

3.8V

V

REF

(minimum UVLO hysteresis)

R

DPRG

+

–

+

V

–

TURN-ON

OUTPUT

2V

SBUS

372212 F04

Figure 4. Delay Timeout Circuitry

372212fb

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For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

Regulated bias supplies as low as 7V can be utilized to

providebiastotheLTC3722-1/LTC3722-2. Figure5shows

various bias supply conﬁgurations.

to UVLO is present and greater than 5V prior to the V

CC

UVLO circuitry activation, then the internal UVLO logic

will prevent output switching until the following three

conditions are met: (1) V UVLO is enabled, (2) V is

CC

REF

V

IN

V

< V

UVLO

12V ±10%

1.5k

BIAS

in regulation and (3) UVLO pin is greater than 5V.

1N5226

3V

1N914

R

START

0.1µF

UVLO can also be used to enable and disable the power

converter. An open drain transistor connected to UVLO,

as shown in Figure 6, provides this capability.

+

0.1µF

C

HOLD

V

CC

372212 F05

Off-Line Bias Supply Generation

Figure 5. Bias Conﬁgurations

If a regulated bias supply is not available to provide V

CC

voltage to the LTC3722-1/LTC3722-2 and supporting

circuitry, one must be generated. Since the power require-

ment is small, approximately 1W, and the regulation is not

critical, a simple open-loop method is usually the easiest

and lowest cost approach. One method that works well

is to add a winding to the main power transformer, and

post regulate the resultant square wave with an L-C ﬁlter

(see Figure 7a). The advantage of this approach is that it

maintains decent regulation as the supply voltage varies,

and it does not require full safety isolation from the input

windingofthetransformer.Somemanufacturersincludea

primarywindingforthispurposeintheirstandardproduct

offerings as well. A different approach is to add a winding

to the outputinductorand peak detectand ﬁlter the square

wave signal (see Figure 7b). The polarity of this winding

Programming Undervoltage Lockout

TheLTC3722-1/LTC3722-2providesundervoltagelockout

(UVLO) control for the input DC voltage feed to the power

converter in addition to the V UVLO function described

CC

in the preceding section. Input DC feed UVLO is provided

with the UVLO pin. A comparator on UVLO compares a

divided down input DC feed voltage to the 5V precision

reference. When the 5V level is exceeded on UVLO, the

SS pin is released and output switching commences. At

the same time a 10µA current is enabled which ﬂows out

of UVLO into the voltage divider connected to UVLO. The

amount of DC feed hysteresis provided by this current is:

10µA • R , see Figure 6. The system UVLO threshold is:

TOP

5V • [(R

+ R

)/R ]. If the voltage applied

BOTTOM BOTTOM

R

TOP

UVLO

ON OFF

R

BOTTOM

372212 F06

Figure 6. System UVLO Setup

V

IN

V

CC

V

OUT

IN

R

L

START

OUT

2k

+

R

ISO BARRIER

START

+

15V*

0.1µF

C

HOLD

0.1µF

C

HOLD

372212 F07a

*OPTIONAL

V

372212 F07b

CC

Figure 7a. Auxiliary Winding Bias Supply

Figure 7b. Output Inductor Bias Supply

372212fb

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For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

is designed so that the positive voltage square wave is

produced while the output inductor is freewheeling. An

advantage of this technique over the previous is that it

does not require a separate ﬁlter inductor and since the

voltageisderivedfromthewellregulatedoutputvoltage, it

is also well controlled. One disadvantage is that this wind-

ing will require the same safety isolation that is required

for the main transformer. Another disadvantage is that a

LTC3722-1/LTC3722-2 can be set up to either synchronize

other PWM chips or be synchronized by another chip or

externalclocksource.The1.8VSYNCthresholdallowsthe

LTC3722-1/LTC3722-2 to be synchronized directly from

all standard 3V and 5V logic families.

Design Procedure:

1. Choose C for the desired oscillator frequency. The

T

much larger V ﬁlter capacitor is needed, since it does

CC

switching frequency selected must be consistent with

thepowermagneticsandoutputpowerlevel.Ingeneral,

increasing the switching frequency will decrease the

maximum achievable output power, due to limitations

of maximum duty cycle imposed by transformer core

reset and ZVS. Remember that the tranformer fre-

quency is one-half that of the oscillator.

not generate a voltage as the output is ﬁrst starting up,

or during short-circuit conditions.

Programming the LTC3722-1/LTC3722-2 Oscillator

ThehighaccuracyLTC3722-1/LTC3722-2oscillatorcircuit

provides ﬂexibility to program the switching frequency,

slope compensation, and synchronization with minimal

externalcomponents.TheLTC3722-1/LTC3722-2oscillator

circuitry produces a 2.2V peak-to-peak amplitude ramp

1

C_T=

(13.4k • f_OSC

)

waveform on C and a narrow pulse on SYNC that can be

T

Example: Desired f

= 330kHz

OSC

used to synchronize other PWM chips. Typical maximum

duty cycles of 98.5% are obtained at 300kHz and 96% at

1MHz. A compensating slope current is derived from the

oscillator ramp waveform and sourced out of CS.

C = 1/(13.4k • f ) = 226pF, choose closest standard

T

OSC

value of 220pF. A 5% or better tolerance multilayer NPO

or X7R ceramic capacitor is recommended for best

performance.

The desired amount of slope compensation is selected

2.TheLTC3722-1/LTC3722-2caneithersynchronizeother

PWMs, or be synchronized to an external frequency

source or PWM chip (see Figure 8 for details).

with single external resistor. A capacitor to GND on C

T

programstheswitchingfrequency.TheC rampdischarge

T

current is internally set to a high value (>10mA). The dedi-

cated SYNC I/O pin easily achieves synchronization. The

C

OF SLAVE(S) IS

T

LTC3722

1.25 C OF MASTER.

T

1k

C

SYNC

5.1k

T

AMPLITUDE > 1.8V

100ns < PW < 0.4/ƒ

LTC3722

C

T

C

T

SYNC

LTC3722

EXTERNAL

FREQUENCY

SOURCE

1k

C

SYNC

5.1k

T

LTC3722

SLAVES

5.1k

C

T

SYNC

C

T

MASTER

•

C

T

5.1k

372212 F08b

UP TO

5 SLAVES

372212 F08a

Figure 8a. SYNC Output (Master Mode)

Figure 8b. SYNC Input from an External Source

372212fb

17

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

3. Slope compensation is required for most peak current

mode controllers in order to prevent subharmonic

oscillation of the current control loop. In general, if the

system duty cycle exceeds 50% in a ﬁxed frequency,

continuous current mode converter, an unstable con-

dition exists within the current control loop. Any

perturbation in the current signal is ampliﬁed by the

PWM modulator resulting in an unstable condition.

Some common manifestations of this include alternate

pulse nonuniformity and pulse width jitter. Fortunately,

this can be addressed by adding a corrective slope to

the current sense signal or by subtracting the same

slope from the current command signal (error am-

pliﬁer output). In theory, the current doubler output

conﬁguration does not require slope compensation

since the output inductor duty cycles only approach

50%. However, transient conditions can momentarily

cause higher duty cycles and therefore, the possibility

for unstable operation.

Transformer turns ratio (N) =

DC_MAX

V

•

= 5

IN(MIN)

(2 • V_OUT

)

R

= 0.05Ω

CS

f_SW= 300kHz, i.e., transformer f =

f_SW

2

= 150kHz

R_CS

R_SLOPE= V_O•

(2 • L • f_SW• 74µA • N)

0.05

= 3.3V •

2 • 2.2µH • 300k • 74µA • 5

R

= 338Ω, choose the next higher standard value

SLOPE

to account for tolerances in I

, R , N and L.

SLOPE CS

The exact amount of required slope compensation is

easily programmed by the LTC3722-1/LTC3722-2 with

the addition of a single external resistor (see Figure 9).

The LTC3722-1/LTC3722-2 generates a current that

LTC3722

BRIDGE

V(C )

T

CURRENT

I =

R

SLOPE

C

T

33k

CS

ADDED

SLOPE

R

CS

33k

is proportional to the instantaneous voltage on C ,

T

(33µA/V(C )). Thus, at the peak of C , this current is

T

CURRENT SENSE

WAVEFORM

approximately 74µA and is output from the CS pin. A

resistorconnectedbetweenCSandtheexternalcurrent

sense resistor sums in the required amount of slope

compensation. The value of this resistor is dependent

372212 F09

Figure 9. Slope Compensation Circuitry

onseveralfactorsincludingminimumV ,V

,switch-

IN OUT

ing frequency, current sense resistor value and output

inductor value. An illustrative example with the design

equation for current doubler secondary follows.

Example:

V = 36V to 72V

IN

V

= 3.3V

= 40A

OUT

I

L = 2.2µH

372212fb

18

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

Current Sensing and Overcurrent Protection

ever, with high input voltage, very low R

MOSFETs

DS(ON)

and a shorted output, or with saturating magnetics, the

overcurrent comparator provides a means of protecting

the power converter.

Current sensing provides feedback for the current mode

control loop and protection from overload conditions. The

LTC3722-1/LTC3722-2 are compatible with either resis-

tive sensing or current transformer methods. Internally

connected to the LTC3722-1/LTC3722-2 CS pin are two

comparators that provide pulse-by-pulse and overcurrent

shutdown functions respectively (see Figure 10).

Leading Edge Blanking

TheLTC3722-1/LTC3722-2providesprogrammableleading

edge blanking to prevent nuisance tripping of the current

sense circuitry. Leading edge blanking relieves the ﬁlter-

ing requirements for the CS pin, greatly improving the

response to real overcurrent conditions. It also allows

the use of a ground referenced current sense resistor

or transformer(s), further simplifying the design. With a

The pulse-by-pulse comparator has a 300mV nominal

threshold. If the 300mV threshold is exceeded, the PWM

cycle is terminated. The overcurrent comparator is set

approximately 2x higher than the pulse-by-pulse level.

If the current signal exceeds this level, the PWM cycle is

terminated, the soft-start capacitor is quickly discharged

andasoft-startcycleisinitiated.Iftheovercurrentcondition

persists, the LTC3722-1/LTC3722-2 halts PWM operation

and waits for the soft-start capacitor to charge up to ap-

proximately 4V before a retry is allowed. The soft-start

capacitor is charged by an internal 12µA current source.

If the fault condition has not cleared when soft-start

reaches 4V, the soft-start pin is again discharged and a

new cycle is initiated. This is referred to as hiccup mode

operation. In normal operation and under most abnormal

conditions, the pulse-by-pulse comparator is fast enough

to prevent hiccup mode operation. In severe cases, how-

single 10k to 100k resistor from R

to GND, blanking

LEB

times of approximately 40ns to 320ns are programmed. If

not required, connecting R to V can disable leading

LEB

REF

edge blanking. Keep in mind that the use of leading edge

blanking will set a minimum linear control range for the

phase modulation circuitry.

Resistive Sensing

A resistor connected between input common and the

sources of MB and MD is the simplest method of current

sensing for the full bridge converter. This is the preferred

method for low to moderate power levels. The sense

resistor should be chosen such that the maximum rated

H = SHUTDOWN

PWM

OUTPUTS

UVLO

ENABLE

LATCH

PULSE BY PULSE

CURRENT LIMIT

PWM

LOGIC

Q

φ

MOD

Q

BLANK

S

R

Q

+

–

S

CS

300mV

OVERLOAD

CURRENT LIMIT

R

CS

+

–

12µA

4.1V

S

R

Q

–

+

650mV

SS

UVLO

ENABLE

+

–

0.4V

C

SS

Q

372212 F10

Figure 10. Current Sense/Fault Circuitry Detail

372212fb

19

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

output current for the converter can be delivered at the

The advantage of the high side location is a greater im-

munity to leading edge noise spikes, since gate charge

current and reﬂected rectiﬁer recovery current are largely

eliminated. Figure 11 illustrates a typical current sense

lowestexpectedV .Usethefollowingformulatocalculate

IN

the optimal value for R . I equation valid for current

CS

P

doubler secondary.

transformer based sensing scheme. R in this case is

S

LTC3722-1:

calculated the same as in the resistive case, only its value

is increased by the sense transformer turns ratio. At high

duty cycles, it may become difﬁcult or impossible to re-

set the current transformer. This is because the required

transformer reset voltage increases as the available time

forresetdecreasestoequalizethe(volt•seconds)applied.

Theinterwindingcapacitanceandsecondaryinductanceof

the current sense transformer form a resonant circuit that

limits the dV/dT on the secondary of the CS transformer.

This, inturn, limitsthemaximumachievabledutycyclefor

the CS transformer. Attempts to operate beyond this limit

will cause the transformer core to “walk” and eventually

saturate, opening up the current feedback loop.

300mV – (82.5µA • R

)

SLOPE

R

=

CS

I (PEAK)

P

I

V

• D

O(MAX)

IN(MAX)

MIN

I (PEAK) =

+

P

2 • N • EFF

L

• f

• 2

CLK

MAG

V (1– D

)

MIN

O

L

• f

• N

CLK

OUT

N_P

N_S

where: N = Transformer turnsratio =

Common methods to address this limitation include:

LTC3722-2:

1. Reducing the maximum duty cycle by lowering the

power transformer turns ratio.

300mV

I_P(PEAK)

R_CS

=

2. Reducing the switching frequency of the converter.

3. Employ external active reset circuitry.

Current Transformer Sensing

Acurrentsensetransformercanbeusedinlieuofresistive

sensing with the LTC3722-1/LTC3722-2. Current sense

transformers are available in many styles from several

manufacturers. A typical sense transformer for this ap-

plication will use a 1:50 turns ratio (N), so that the sense

resistor value is N times larger, and the secondary current

Ntimessmallerthanintheresistivesensecase.Therefore,

the sense resistor power loss is about N times less with

thetransformermethod, neglectingthetransformerscore

and copper losses. The disadvantages of this approach

include, higher cost and complexity, lower accuracy,

core reset/maximum duty cycle limitations and lower

speed. Nevertheless, for very high power applications,

this method is preferred. The sense transformer primary

is placed in the same location as the ground referenced

sense resistor, or between the upper MOSFET drains in

4. Using two CS transformers summed together.

5. Choose a CS transformer optimized for high frequency

applications.

MD

SOURCE

MB

SOURCE

R

SLOPE

N:1

RAMP

CS

CURRENT

TRANSFORMER

R

S

OPTIONAL

FILTERING

372212 F11

Figure 11. Current Transformer Sense Circuitry

the (MA, MC) and V .

IN

372212fb

20

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

Phase Modulator (LTC3722-1)

the current sense resistor is connected between GND and

the two bottom bridge transistors, a voltage proportional

The LTC3722-1 phase modulation control circuitry is

comprised of the phase modulation comparator and

logic, the error ampliﬁer, and the soft-start ampliﬁer (see

Figure 12). Together, these elements develop the required

phase overlap (duty cycle) required to keep the output

voltage in regulation. In isolated applications, the sensed

output voltage error signal is fed back to COMP across the

input to output isolation boundary by an optical coupler

and shunt reference/error ampliﬁer (LT^®1431) combina-

tion. The FB pin is connected to GND, forcing COMP high.

The collector of the optoisolator is connected to COMP

directly. The voltage COMP is internally attenuated by the

LTC3722-1. The attenuated COMP voltage provides one

input to the phase modulation comparator. This is the

current command. The other input to the phase modula-

tion comparator is the RAMP voltage, level shifted by

approximately 650mV. This is the current loop feedback.

During every switching cycle, alternate diagonal switches

(MA-MDorMB-MC)conductandcausecurrentinanoutput

inductor to increase. This current is seen on the primary

of the power transformer divided by the turns ratio. Since

to the output inductor current will be seen across R

.

SENSE

The high side of R

is also connected to CS, usually

SENSE

through a small resistor (R

). When the voltage on

SLOPE

CS exceeds either (COMP/4.3) –650mV, or 300mV, the

overlap conduction period will terminate. During normal

operation, the attenuated COMP voltage will determine

the CS trip point. During start-up, or slewing conditions

following a large load step, the 300mV CS threshold will

terminate the cycle, as COMP will be driven high, such

that the attenuated version exceeds the 300mV threshold.

In extreme conditions, the 650mV threshold on CS will be

exceeded, invoking a soft-start/restart cycle.

Selecting the Power Stage Components

Perhaps the most critical part of the overall design of the

converter is selecting the power MOSFETs, transformer,

inductors and ﬁlter capacitors. Tremendous gains in ef-

ﬁciency, transient performance and overall operation can

beobtainedaslongasafewsimpleguidelinesarefollowed

with the phase-shifted full bridge topology.

TOGGLE

F/F

A

B

ERROR

AMPLIFIER

Q

CLK

FB

–

+

PHASE

MODULATION

COMPARATOR

Q

1.2V

V

PHASE

MODULATION

LOGIC

50k

COMP

–

+

C

D

S

Q

REF

+

–

R

CLK

12µA

650mV

SOFT-START

AMPLIFIER

FROM

CURRENT

LIMIT

SS

+

–

IDEAL

COMPARATOR

14.9k

R

LEB

CS

BLANKING

Q

S

R

372212 F12

CLK

Figure 12. Phase Modulation Circuitry (LTC3722-1)

372212fb

21

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

Power Transformer

where:

Switching frequency, core material characteristics, series

resistance and input/output voltages all play an important

role in transformer selection. Close attention also needs

to be paid to leakage and magnetizing inductances as

they play an important role in how well the converter will

achieve ZVS. Planar magnetics are very well suited to

these applications because of their excellent control of

these parameters.

D = minimum duty cycle

f

= oscillator frequency

SW

L = output inductance

O

ESR = output capacitor series resistance

Theamountofbulkcapacitancerequiredisusuallysystem

dependent,buthassomerelationshiptooutputinductance

value, switching frequency, load power and dynamic load

characteristics. Polymer electrolytic capacitors are the

preferred choice for their combination of low ESR, small

size and high reliability. For less demanding applications,

or those not constrained by size, aluminum electrolytic

capacitors are commonly applied. Most DC/DC convert-

ers in the 100kHz to 300kHz range use 20µF to 25µF of

bulk capacitance per watt of output power. Converters

switching at higher frequencies can usually use less bulk

capacitance.Insystemswheredynamicresponseiscritical,

additional high frequency capacitors, such as ceramics,

can substantially reduce voltage transients.

Turns Ratio

The required turns ratio for a current doubler secondary

is given below. Depending on the magnetics selected, this

value may need to be reduced slightly.

Turns ratio formula:

V

_IN(MIN)•D_MAX

N =

2 • V_OUT

where:

V

= Minimum V for operation

IN(MIN)

IN

Power MOSFETs

D

MAX

= Maximum duty cycle of controller (DC

)

MAX

The full bridge power MOSFETs should be selected for

Output Capacitors

their R

and BV

ratings. Select the lowest BV

DS(ON)

DSS DSS

rated MOSFET available for a given input voltage range

leaving at least a 20% voltage margin. Conduction losses

Outputcapacitorselectionhasadramaticimpactonripple

voltage, dynamic response to transients and stability.

Capacitor ESR along with output inductor ripple current

will determine the peak-to-peak voltage ripple on the out-

put. The current doubler conﬁguration is advantageous

because it has inherent ripple current reduction. The dual

outputinductorsdelivercurrenttotheoutputcapacitor180

degrees out-of-phase, in effect, partially canceling each

other’s ripple current. This reduction is maximized at high

duty cycle and decreases as the duty cycle reduces. This

meansthatacurrentdoublerconverterrequireslessoutput

capacitance for the same performance as a conventional

converter. By determining the minimum duty cycle for the

are directly proportional to R

. Since the full bridge

DS(ON)

has two MOSFETs in the power path most of the time,

conduction losses are approximately equal to:

I_O

2 • R_DS(ON)•I², where I =

2N

Switching losses in the MOSFETs are dominated by the

power required to charge their gates, and turn-on and

turn-off losses. At higher power levels, gate charge power

is seldom a signiﬁcant contributor to efﬁciency loss. ZVS

operation virtually eliminates turn-on losses. Turn-off

lossesarereducedbytheuseofanexternaldraintosource

snubber capacitor and/or a very low resistance turn-off

driver. If synchronous rectiﬁer MOSFETs are used on the

secondary, the same general guidelines apply. Keep in

converter, worse-case V

following formula:

ripple can be derived by the

OUT

V_O•ESR

V_ORIPPLE= I_RIPPLE•ESR =

(1–D)(1– 2D)

L_O• 2 • f_SW

mind, however, that the BV

rating needed for these can

DSS

be greater than V

/N, depending on how well the

IN(MAX)

372212fb

22

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

secondary is snubbed. Without snubbing, the secondary

voltage can ring to levels far beyond what is expected due

totheresonanttankcircuitformedbetweenthesecondary

margin and transient response. Additional modiﬁcations

will sometimes be required in order to deal with parasitic

elements within the converter that can alter the feedback

response. The compensation network will vary depending

ontheloadcurrentrangeandthetypeofoutputcapacitors

used. In isolated applications, the compensation network

is generally located on the secondary side of the power

supply, around the error ampliﬁer of the opto-coupler

driver, usually an LT1431 or equivalent. In nonisolated

systems, the compensation network is located around

the LTC3722-1/LTC3722-2’s error ampliﬁer.

leakage inductance and the C

(output capacitance) of

OSS

the synchronous rectiﬁer MOSFETs.

Switching Frequency Selection

Unless constrained by other system requirements, the

power converter’s switching frequency is usually set as

highaspossiblewhilestayingwithinthedesiredefﬁciency

target. The beneﬁts of higher switching frequencies are

many including smaller size, weight and reduced bulk

capacitance. In the full bridge phase-shift converter, these

principlesaregenerallythesamewiththeaddedcomplica-

tion of maintaining zero voltage transitions, and therefore,

higher efﬁciency. ZVS is achieved in a ﬁnite time during

the switching cycle. During the ZVS time, power is not

delivered to the output; the act of ZVS reduces the maxi-

mum available duty cycle. This reduction is proportional

to maximum output power since the parasitic capacitive

element (MOSFETs) that increase ZVS time get larger as

powerlevelsincrease. Thisimpliesaninverserelationship

between output power level and switching frequency.

Table 1 displays recommended maximum switching

frequency vs power level for a 30V/75V in to 3.3V/5V out

converter. Higher switching frequencies can be used if the

input voltage range is limited, the output voltage is lower

and/or lower efﬁciency can be tolerated.

In current mode control, the dominant system pole is

determined by the load resistance (V /I ) and the output

O

capacitor 1/(2π • R • C ). The output capacitors ESR

O

1/(2π • ESR • C ) introduces a zero. Excellent DC line and

O

load regulation can be obtained if there is high loop gain

at DC. This requires an integrator type of compensator

around the error ampliﬁer. A procedure is provided for

deriving the required compensation components. More

complex types of compensation networks can be used to

obtain higher bandwidth if necessary.

Step 1. Calculate location of minimum and maximum

output pole:

1

F_P1(MIN)

F_P1(MAX)

=

(2π •R_O(MAX)•C_O)

1

=

(2π •R_O(MIN)•C_O)

Table 1. Switching Frequency vs Power Level

Step 2. Calculate ESR zero location:

<50W

<100W

<200W

<500W

<1kW

600kHz

450kHz

300kHz

200kHz

150kHz

100kHz

1

F_Z1=

(2π •R_ESR•C_O)

Step 3. Calculate the feedback divider gain:

R_B

(R_B+ R_T)

V_REF

V_OUT

<2kW

or

Closing the Feedback Loop

If polymer electrolytic output capacitorsare used, the ESR

zero can be employed in the overall loop compensation

and optimum bandwidth can be achieved. If aluminum

electrolytics are used, the loop will need to be rolled off

prior to the ESR zero frequency, making the loop response

slower. A linearized SPICE macromodel of the control

372212fb

Closing the feedback loop with the full bridge converter

involves identifying where the power stage and other

systempoles/zeroesarelocatedandthendesigningacom-

pensation network around the converters error ampliﬁer

toshapethefrequencyresponsetoinsureadequatephase

23

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

loop is very helpful tool to quickly evaluate the frequency

response of various compensation networks.

improve transient response, particularly overshoot, and

improve ZVS ability at light loads.

Polymer Electrolytic (see Figure 13) 1/(2πC R ) sets a

C I

Programming the Synchronous Rectiﬁer Turn-Off Delay

low frequency pole. 1/(2πC R ) sets the low frequency

C F

TheLTC3722-1/LTC3722-2controllersincludeafeatureto

program the turn-off edge of the secondary side synchro-

nous rectiﬁer MOSFETs relative to the beginning of a new

primary side power delivery pulse. This feature provides

optimized timing for the synchronous MOSFETs which

improves efﬁciency. At higher load currents it becomes

more advantageous to delay the turn-off of the synchro-

nous rectiﬁers until the transformer core has been reset

to begin the new power pulse. This allows for secondary

freewheeling current to ﬂow through the synchronous

MOSFET channel instead of its body diode.

zero. The zero frequency should coincide with the worst-

case lowest output pole frequency. The pole frequency

and mid frequency gain (R /R ) should be set such so

F

I

that the loop crosses over zero dB with a –1 slope at a

frequency lower than (f /8). Use a bode plot to graphi-

SW

cally display the frequency response. An optional higher

frequency pole set by CP2 and R is used to attenuate

f

switching frequency noise.

Aluminum Electrolytic (see Figure 13) the goal of this

compensator will be to cross over the output minimum

pole frequency. Set a low frequency pole with C and R

C

IN

The turn-off delay is programmed with a resistor from

SPRG to GND (see Figure 14). The nominal regulated

voltage on SPRG is 2V. The external resistor programs a

currentwhichﬂowsoutofSPRG.Thedelaycanbeadjusted

from approximately 20ns to 200ns, with resistor values of

10k to 200k. Do not leave SPRG ﬂoating. The amount of

delay can also be modulated based on an external current

source that sinks current out of SPRG. Care must be taken

to limit the current out of SPRG to 350µA or less.

at a frequency that will cross over the loop at the output

pole minimum F, place the zero formed by C and R at

C

f

the output pole F.

V

OUT

COMP

OPTO

C

P2

V

OUT

OPTIONAL

C

R

f

R

C

I

O

REF

COLL

R

L

–

+

SPRG

2.5V

ESR

R

D

LT1431 OR EQUIVALENT

PRECISION ERROR

+

V

–

TURN-OFF

AMP AND REFERENCE

372212 F13

R

SPRG

SYNC OUT

2V

–

Figure 13. Compensation for Polymer Electrolytic

372212 F14

Figure 14. Synchronous Delay Circuitry

Synchronous Rectiﬁcation

The LTC3722-1/LTC3722-2 produces the precise timing

signalsnecessarytocontrolcurrentdoublersecondaryside

synchronous MOSFETs on OUTE and OUTF. Synchronous

rectiﬁers are used in place of Schottky or Silicon diodes

on the secondary side of the power supply. As MOSFET

Current Doubler

Thecurrentdoublersecondaryemploystwooutputinduc-

tors that equally share the output load current. The trans-

former secondary is not center-tapped. This conﬁguration

provides 2x higher output current capability compared to

similarly sized single output inductor modules, hence the

name. Each output inductor is twice the inductance value

as the equivalent single inductor conﬁguration and the

transformer turns ratio is one-half that of a single inductor

R

levels continue to drop, signiﬁcant efﬁciency im-

DS(ON)

provementscanberealizedwithsynchronousrectiﬁcation,

provided that the MOSFET switch timing is optimized. An

additional beneﬁt realized with synchronous rectiﬁers is

bipolar output current capability. These characteristics

372212fb

24

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

OPERATION

the traces from the gate driver chip or buffer to the gate

and source leads are short and direct. Drive requirements

arefurthereasedsincealloftheswitchesturnonwithzero

VDS, eliminating the Miller effect. Low turn-off resistance

is critical, however, in order to prevent excessive turn-off

losses resulting from the same Miller effects that were not

an issue for turn-on. The LTC3722-1/LTC3722-2 does not

require the propagation delays of the high and low side

drive circuits to be precisely matched as the DirectSense

ZVScircuitrywilladaptaccordingly.Asaresult,LTC3722-1/

LTC3722-2 can drive a simple NPN-PNP buffer or a gate

driver chip like the LTC1693-1 to provide the low side gate

drive. Providing drive to the high side presents additional

challenges since the MOSFET gate must be driven above

theinputsupply. Asimplecircuit(Figure17)usingasingle

LTC1693-1, an inexpensive signal transformer and a few

discrete components provides both high side gate drives

(A and C) reliably.

secondary. The drive to the inductors is 180 degrees out-

of-phasewhichprovidespartialripplecurrentcancellation

intheoutputcapacitor(s).Reducedcapacitorripplecurrent

lowersoutputvoltagerippleandenhancesthecapacitors’s

reliability. The amount of ripple cancellation is related to

duty cycle (see Figure 15). Although the current doubler

requires an additional inductor, the inductor core volume

2

is proportional to LI , thus the size penalty is small. The

transformerconstructionissimpliﬁedwithoutacenter-tap

windingandtheturnsratioisreducedbyone-halfcompared

to a conventional full wave rectiﬁer conﬁguration.

Synchronous rectiﬁcation of the current doubler second-

ary requires two ground referenced N-channel MOSFETs.

The timing of the LTC3722-1/LTC3722-2 drive signals is

shown in the Timing Diagram.

Full Bridge Gate Drive

The full bridge converter requires high current MOSFET

gate driver circuitry for two ground referenced switches

and two high side referred switches. Providing drive to the

ground referenced switches is not too difﬁcult as long as

The LTC4440 high side driver can also be applied. The

LTC4440eliminatesthesignaltransformerandispreferred

for applications where V is less than 80V (max).

IN

1

LTC1693-1

OUT1

LTC3722

NOTE: INDUCTOR(S) DUTY CYCLE

IN1

IS LIMITED TO 50% WITH CURRENT

2:1:1

DOUBLER PHASE SHIFT CONTROL.

NORMALIZED

OUTPUT RIPPLE

CURRENT

ATTENUATION

OUTE

OUTF

GND1

GND2

IN2

OUT2

0

0.25

0.5

372212 F16

DUTY CYCLE

3722212 F15

Figure 15. Ripple Current Cancellation vs Duty Cycle

Figure 16. Isolated Drive Circuitry

V

IN

REGULATED

BIAS

2µF

CER

LTC3722

0.1µF

V

CC

POWER

MOSFET

0.1µF

OUT

1/2

IN

OUTA

OR

BAT

54

2k

OUTC

LTC1693-1

GND

SIGNAL

TRANSFORMER

BRIDGE

LEG

372212 F17

Figure 17. High Side Gate Driver Circuitry

372212fb

25

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

PACKAGE DESCRIPTION

GN Package

24-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641 Rev B)

.337 – .344*

(8.560 – 8.738)

.033

(0.838)

REF

24 23 22 21 20 19 18 17 16 15 1413

.045 .005

.150 – .165

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

.254 MIN

1

2

3

4

5

6

7

8

9 10 11 12

.0165 .0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

.015 .004

(0.38 0.10)

.0532 – .0688

(1.35 – 1.75)

× 45°

.004 – .0098

(0.102 – 0.249)

.0075 – .0098

(0.19 – 0.25)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN24 REV B 0212

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

372212fb

26

For more information www.linear.com/LTC3722

LTC3722-1/LTC3722-2

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

1 to 28

A

03/10 I-grade parts added. Reﬂected throughout the data sheet.

02/13 H-grade part added. Reﬂected throughout the data sheet.

B

1 to 28

372212fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC3722

27

LTC3722-1/LTC3722-2

TYPICAL APPLICATION

LTC3722/LTC4440 420W, 36V-72V Input to 12V/35A Isolated Full Bridge Supply

V

IN

L1, 1.3µH

51Ω, 2W

+V

IN

1µF

100V

×4

1µF

100V

36V TO

72V

D5

0.47µF

100V

–V

IN

12V

D2

D3

T1

5:5(105µH):1:1

13k

D4

D1

D6

1/2W

3

+V

OUT

4

11

10

51Ω

2W

0.47µF

100V

820pF

200V

V

CC

LTC4440EMS8E

CC

LTC4440EMS8E

1

6

7

6

7

•

BOOST

IN

BOOST

C

15Ω

1.5W

1

Si7852DP

×2

2

•

8

7

A

IN

TG

Si7852DP

GND GND TS

V

×2

HIGH

0.22µF

0.47µF

100V

4

2

8

4

2

8

0.22µF

L2

150nH

L3

4

2

11

10

V

HIGH

0.85µH

–V

OUT

12V

+V

•

OUT

+

C1, C2

8

7

B

D

Q1

Q2

180µF

16V

×2

Si7852DP

×2

12V

35A

•

×2

Si7852DP

×4

Q3

Q4

×4

0.47µF, 100V = TDK C3216X7R2A474M

1µF, 100V = TDK C4532X7R2A105M

C1, C2: SANYO 16SP180M

C3: AVX TPSE686M020R0150

C4: MuRata DE2E3KH222MB3B

D1, D4, D5, D6: MURS120T3

D2, D3, D7, D8: BAS21

D9: MMBZ5226B

1µF

–V

T2

5:5(105µH):1:1

L4

1mH

OUT

+V

100Ω

6

12V

1.10k

OUT

D9

3.3V

I

+

D7

D8

C3

68µF

20V

SNS

0.02Ω

1.5W

0.02Ω

1.5W

4.02k

1k

•

1

D10: MMBZ5240B

4.64k

1/4W

4.64k

1/4W

MMBT3904

D11: BAT54

2.15k

D12: MMBZ5231B

L1: SUMIDA CDEP105-1R3MC-50

L2: PULSE PA0651

6

+

5

2

3

11

+

12

14 15 16

MF MF2

30.1k

100Ω

–

T3

1(1.5mH):0.5

L3: PA1294.910

CSE

ME ME2 CSF

CSF

V

CC

1

L4: COILCRAFT DO1608C-105

Q1, Q2: ZETEX FMMT619

Q3, Q4: ZETEX FMMT718

T1, T2: PULSE PA0526

T3: PULSE PA0785

SYCN

LTC3901EGN

PV

CC

1

4

D10

10V

0.1µF

GND PGND GND2 PGND2 TIMER

8

100Ω

220pF

1µF

8

5

4

10

13

7

1µF

330pF

220pF

20k

22Ω

V

12V

IN

470Ω

1/4W

+V

OUT

4.99k

I

–V

OUT

SNS

5V

REF

20k

1/4W

A

B

C

D

17

200k

330Ω

11

9

21

20

19

15

16

9.53k

10k

22nF

2.7k

MOC207

10

1

ADLY PDLY

OUTA OUTB OUTC OUTD OUTF

OUTE

750Ω

SBUS

7

6

150Ω

3

18

12

182k

V

CS

LTC3722-1

0.047µF

CC

3

2

4

UVLO

V

DPRG NC SYNC CT SPRG R

FB GND PGND

SS

+

COMP

4

REF

LEB

5

R

V

COMP

LT1431

TOP

5V

REF

5

2

30.1k

14

2

8

1

24 13

10k

6

23 22

7

8

1

220pF

COLL

REF

5.1k

180pF

150k

330pF

2.2nF

MMBT3904

D12

5.1V

GNDF GNDS R

MID

7

2.49k

100k

220pF

C4

2.2nF

250V

6

5

33k

D11

1M

1µF

0.47µF

8.25k

68nF

–V

OUT

372212 TA02

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

High Efﬁciency with On-Chip MOSFET Drivers

Non-Synchronous Push-Pull and Full-Bridge Controller Minimizes External Components, On-Chip MOSFET Drivers

LTC3723-1/LTC3723-2 Synchronous Push-Pull and Full-Bridge Controllers

LTC3721-1

LTC3765/LTC3766

LT1952/LT1952-1

LTC3901

Isolated Synchronous Forward Controller Chip Set

Isolated Synchronous Forward Controllers

Ideal for 24V or 48V Input Applications

Secondary-Side Synchronous Driver for Full-Bridge and Programmable Timeout, Reverse Inductor Current Sense

Push-Pull Converters

LTC4440

High Voltage High Side MOSFET Driver

100V, 2.4A Pull-Up, 1.6Ω Pull-Down, SOT-23 and MSOP-8 Packages

372212fb

LT 0213 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

For more information www.linear.com/LTC3722

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3722

●

 LINEAR TECHNOLOGY CORPORATION 2009


型号：	LTC3722-1_15
厂家：	Linear
描述：	Synchronous Dual Mode Phase Modulated Full Bridge Controllers
文件：	总28页 (文件大小：347K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3722-1_15 [Linear]

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