LTC3722-1 [Linear]
Synchronous Dual Mode Phase Modulated Full Bridge Controllers; 同步双模式相调制的全桥式控制器
| 型号： | LTC3722-1 |
| 厂家： | 
Linear |
| 描述： | Synchronous Dual Mode Phase Modulated Full Bridge Controllers |
| 文件： | 总28页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Final Electrical Specifications
LTC3722-1/LTC3722-2
Synchronous Dual Mode
Phase Modulated
Full Bridge Controllers
February 2003
U
DESCRIPTIO
FEATURES
TheLTC®3722-1/LTC3722-2phaseshiftPWMcontrollers
provide all of the control and protection functions neces-
sary to implement a high efficiency, zero voltage switched
(ZVS), full bridge power converter. Adaptive ZVS circuitry
delays the turn-on signals for each MOSFET independent
of internal and external component tolerances. Manual
delay set mode enables secondary side control operation
or direct control of switch turn-on delays.
■
Adaptive or Manual Delay Control for Zero Voltage
Switching Operation
■
Adjustable Synchronous Rectification Timing for
Highest Efficiency
Adjustable Maximum ZVS Delay
■
■
Adjustable System Undervoltage Lockout and
Hysteresis
■
Programmable Leading Edge Blanking
■
Very Low Start-Up and Quiescent Currents
The LTC3722-1/LTC3722-2 feature adjustable synchro-
nous rectifier timing for optimal efficiency. A UVLO pro-
gram input provides accurate system turn-on and turn-off
voltages. The LTC3722-1 features peak current mode
controlwithprogrammableslopecompensationandlead-
ing edge blanking, while the LTC3722-2 employs voltage
mode control with voltage feedforward capability.
■
Current Mode (LTC3722-1) or Voltage Mode
(LTC3722-2) Operation
■
Programmable Slope Compensation
■
VCC UVLO and 25mA Shunt Regulator
■
50mA Output Drivers
■
Soft-Start, Cycle-by-Cycle Current Limiting and
Hiccup Mode Short-Circuit Protection
■
The LTC3722-1/LTC3722-2 feature extremely low operat-
ingandstart-upcurrents. Bothdevicesincludeafullrange
of protection features and are available in the 24-pin
surface mount (GN) package.
5V, 15mA Low DUropout Regulator
APPLICATIO S
■
Telecommunications, Infrastructure Power Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Distributed Power Architectures
Server Power Supplies
■
U
TYPICAL APPLICATIO
V
IN
36V TO 72V
C
IN
R1
12VOUT, 240W Converter Efficiency
95
36V
IN
MA
MC
MD
T1
LTC3722
90
85
80
75
L1
L2
48V
V
IN
OUT
12V
72V
IN
C
OUT
MB
1/2
U1
1/2
U1
U2
ME
RCS
T2
C1
MF
0
2
4
6
8
10 12 14 16 18 20
CURRENT (A)
3722 • TA01A
U1, U2: LTC1693-1 DUAL GATE DRIVER
3722 TA01b
372212i
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
1
LTC3722-1/LTC3722-2
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
VREF Output Current ................................ Self Regulated
Outputs (A,B,C,D,E,F) Current .......................... ±100mA
Operating Temperature Range (Note 6)
LTC3722E........................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
VCC to GND (Low Impedance Source) ......... –0.3 to 10V
(Chip Self Regulates at 10.3V)
UVLO to GND................................................–0.3 to VCC
All Other Pins to GND
(Low Impedance Source) ....................... –0.3 to 5.5V
VCC (Current Fed) ................................................. 25mA
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
ORDER PART
TOP VIEW
TOP VIEW
NUMBER
NUMBER
SYNC
DPRG
CS
1
2
3
4
5
6
7
8
9
24
C
T
SYNC
RAMP
CS
1
2
3
4
5
6
7
8
9
24
C
T
23 GND
23 GND
LTC3722EGN-1
LTC3722EGN-2
22 PGND
21 OUTA
20 OUTB
19 OUTC
22 PGND
21 OUTA
20 OUTB
19 OUTC
COMP
RLEB
FB
COMP
DPRG
FB
SS
18
V
CC
SS
18
V
CC
NC
17 OUTD
16 OUTE
15 OUTF
NC
17 OUTD
16 OUTE
15 OUTF
PDLY
PDLY
SBUS 10
ADLY 11
UVLO 12
SBUS 10
ADLY 11
UVLO 12
14
V
REF
14
V
REF
13 SPRG
13 SPRG
GN PACKAGE
GN PACKAGE
24-LEAD NARROW PLASTIC SSOP
24-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
TJMAX = 125°C, θJA = 100°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
372212i
2
LTC3722-1/LTC3722-2
ELECTRICAL CHARACTERISTICS
unless otherwise noted.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V, CT = 270pF, RDPRG = 60.4k, RSPRG = 100k, TA = tMIN to tMAX
,
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply
V
V
V
V
Under Voltage Lockout
UVLO Hysteresis
Measured on V
Measured on V
10.25
4.2
145
5
10.5
V
V
CCUV
CCHY
CCST
CCRN
CC
CC
CC
CC
3.8
I
I
Start-Up Current
V
= V
– 0.3V
UVLO
●
230
8
µA
mA
V
CC
Operating Current
No Load on Outputs
Current into V = 10mA
V
Shunt Regulator Voltage
Shunt Resistance
10.3
1.1
5.0
10
10.8
3.5
5.2
11.5
SHUNT
CC
R
Current into V = 10mA to 17mA
Ω
SHUNT
CC
SUVLO
System UVLO Threshold
System UVLO Hysteresis Current
Measured on UVLO Pin, 7mA into V
4.8
8.5
V
CC
SHYST
Current Flows Out of UVLO Pin, 7mA into V
µA
CC
Delay Blocks
DTHR
Delay Pin Threshold
ADLY and PDLY
SBUS = 1.5V
SBUS = 2.25V
●
●
1.4
2.1
1.5
2.25
1.6
2.4
V
V
DHYS
Delay Hysteresis Current
ADLY and PDLY
SBUS = 1.5V, ADLY/PDLY = 1.7V
1.3
mA
DTMO
Delay Timeout
R
= 60.4K
100
4
ns
V
DPRG
DFXT
Fixed Delay Threshold
Fixed Delay Time
Measured on SBUS
DFTM
ADLY,PDLY = 1V, SBUS = V
70
ns
REF
Phase Modulator
I
Ramp Discharge Current
RAMP = 1V, COMP = 0V, C = 4V,
LTC3722-1 Only
50
mA
RMP
T
I
Slope Compensation Current
Measured on CS, C = 1V
30
68
µA
µA
SLP
T
C = 2.25V
T
DC
DC
Maximum Phase Shift
Minimum Phase Shift
COMP = 4.5V
COMP = 0V
●
●
95
98.5
0
%
%
MAX
0.5
MIN
Oscillator
OSCI
Initial Accuracy
Total Variation
T = 25°C, C = 270pF
225
215
250
250
2.2
275
285
kHz
kHz
V
A
T
OSCT
V
= 6.5V to 9.5V
●
CC
OSCV
OSYT
C Ramp Amplitude
T
Measured on C
T
SYNC Threshold
Measured on SYNC
1.6
1.9
2.2
V
OSYW
OSYR
Minimum SYNC Pulse Width
SYNC Frequency Range
Measured at Outputs (Note 2)
Measured at Outputs (Note 2)
100
1000
ns
kHz
372212i
3
LTC3722-1/LTC3722-2
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V, TA = tMIN to tMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Error Amplifier
V
FB Input Voltage
FB Input Range
Open-Loop Gain
Input Bias Current
Output High
COMP = 2.5V (Note 4)
Measured on FB (Note 5)
COMP = 1V to 3V (Note 4)
COMP = 2.5V (Note 4)
Load on COMP = –100µA
Load on COMP = 100µA
COMP = 2.5V
1.172
–0.3
70
1.204
1.236
2.5
V
V
FB
FBI
A
90
5
dB
nA
V
VOL
IIB
20
V
V
4.7
4.92
0.18
800
5
OH
Output Low
0.4
V
OL
I
I
Output Source Current
Output Sink Current
400
2
µA
mA
SOURCE
SINK
COMP = 2.5V
Reference
V
Initial Accuracy
Load Regulation
Line Regulation
Total Variation
T = 25°C, Measured on V
REF
4.925
5.00
2
5.075
15
V
mV
mV
V
REF
A
REFLD
REFLN
REFTV
Load on V
= 100µA to 5mA
REF
V
= 6.5V to 9.5V
0.9
10
CC
Line, Load
●
4.900
18
5.000
30
5.100
45
REFSC
Outputs
OUTH(x)
OUTL(x)
Short-Circuit Current
V
Shorted to GND
mA
REF
Output High Voltage
Output Low Voltage
Pull-Up Resistance
Pull-Down Resistance
Rise Time
I
I
I
I
= –50mA
= 50mA
7.9
8.4
0.6
22
12
5
V
V
OUT(x)
OUT(x)
OUT(x)
OUT(x)
1
R
R
= –50mA to –10mA
= –50mA to –10mA
= 50pF
30
20
15
15
Ω
Ω
ns
ns
ns
HI(x)
LO(x)
r(x)
t
t
C
C
OUT(x)
OUT(x)
Fall Time
= 50pF
5
f(x)
SDEL
SYNC Driver Turn-0ff Delay
R
SPRG
= 100k
180
Current Limit and Shutdown
CLPP
CLSD
CLDEL
SSI
Pulse by Pulse Current Limit Threshold Measured on CS
240
270
0.65
80
300
mV
V
Shutdown Current Limit Threshold
Current Limit Delay to Output
Soft-Start Current
Measured on CS
0.55
0.73
100mV Overdrive on CS (Notes 3, 7)
SS = 2.5V
ns
µA
V
7
12
17
0.1
3.5
SSR
Soft-Start Reset Threshold
Fault Reset Threshold
Measured on SS
0.7
4.5
0.4
3.9
FLT
Measured on SS
V
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 5: Set FB to –0.3V, 2.5V and insure that COMP does not phase
invert.
Note 2: Sync amplitude = 5V , pulse width = 50ns. Verify output (A-F)
frequency = 1/2 sync frequency.
Note 6: The LTC3722E-1/LTC3722E-2 are guaranteed to meet
P-P
performance specifications from 0°C to 85°C. Specifications over the
–40°C to 85°C operating temperature range are assured by design,
characterization and correlation with statistical process controls.
Note 3: Includes leading edge blanking delay, R = 20k.
LEB
Note 4: FB is driven by a servo-loop amplifier to control V
for these
COMP
Note 7: Guaranteed by design, not tested in production.
tests.
372212i
4
LTC3722-1/LTC3722-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency vs
Temperature
Start-Up ICC vs VCC
VCC vs ISHUNT
200
150
100
50
10.50
10.25
10.00
9.75
260
T
= 25°C
T
A
= 25°C
A
C
T
= 270pF
250
240
230
220
0
9.50
0
2
4
6
8
10
0
10
20
30
40
50
–60 –40 –20
0
20 40 60 80 100
V
(V)
I
(mA)
TEMPERATURE (°C)
CC
SHUNT
3722 • G01
3722 • G02
3722 • G03
Leading Edge Blanking Time
vs RLEB
VREF vs IREF
350
300
250
200
150
100
50
5.05
5.00
4.95
4.90
4.85
4.80
T
A
= 25°C
T
= 25°C
J
T
= 85°C
J
T
= –40°C
J
0
20
(mA)
5
10 15
25 30 35 40
0
0
10 20 30 40 50
70
90 100
80
60
R
LEB
(kΩ)
I
REF
3722 • G05
3722 • G04
VREF vs Temperature
Error Amplifier Gain/Phase
5.01
5.00
4.99
4.98
4.97
T
= 25°C
A
100
80
60
40
20
0
–180
–270
–360
–60 –40 –20
0
20 40 60 80 100
10
100
1k
10k
100k 1M
10M
FREQUENCY (Hz)
TEMPERATURE (°C)
3722 • G07
3722 • G06
372212i
5
LTC3722-1/LTC3722-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Delay Hysteresis Current vs
Temperature
Start-Up ICC vs Temperature
Slope Current vs Temperature
90
80
70
60
50
40
30
20
10
0
1.278
1.276
1.274
1.272
1.270
1.268
1.266
1.264
1.262
1.260
1.258
1.256
160
150
140
130
120
110
100
90
SBUS = 1.5V
C
= 2.25V
T
C
= 1V
–25
T
80
70
–55
–55
5
35
65
95
125
–55
–25
5
35
65
95
125
–25
5
35
65
95
125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3722 • G10
3722 • G09
3722 • G08
VCC Shunt Voltage vs
Temperature
Delay Pin Threshold vs
Temperature
FB Input Voltage vs Temperature
10.5
10.4
10.3
10.2
10.1
10.0
9.9
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.202
1.201
1.200
1.199
1.198
1.197
1.196
1.195
1.194
I
= 10mA
CC
SBUS = 2.25V
SBUS = 1.5V
9.8
–55
–25
5
35
65
95
125
–55
–25
5
35
65
95
125
–55
–25
5
35
65
95
125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3722 • G12
3722 • G13
3722 • G11
U
U
U
PI FU CTIO S (LTC3722-1/LTC3722-2)
SYNC (Pin 1/Pin 1): Synchronization Input/Output for the
Oscillator. The input threshold for SYNC is approximately
1.5V, makingitcompatiblewithbothCMOSandTTLlogic.
Terminate SYNC with a 5.1k resistor to GND.
CS (Pin 3/Pin 3): Input to phase modulator for the
LTC3722-1. Input to Pulse by Pulse and Overload Current
Limit Comparators, Output of Slope Compensation Cir-
cuitry. The pulse by pulse comparator has a nominal
300mV threshold, while the overload comparator has a
nominal 600mV threshold.
DPRG (Pin 2/Pin 5): Programming Input for Default Zero
Voltage Transition (ZVS) Delay. Connect a resistor from
DPRG to VREF to set the maximum turn on delay for
outputs A, B, C, D. The delay is approximately equal to
(1.66e-12 x RDPRG). The nominal voltage on DPRG is 2V.
COMP (Pin 4/Pin 4): Error Amplifier Output, Inverting
Input to Phase Modulator.
RLEB (Pin 5/NA): Timing Resistor for Leading Edge Blank-
RAMP (NA/Pin 2): Input to Phase Modulator Comparator
for LTC3722-2 only. The voltage on RAMP is internally
level shifted by 650mV.
ing. Use a 10k to 100k resistor to program from 40ns to
310ns of leading edge blanking of the current sense signal
on CS for the LTC3722-1. A ±1% tolerance resistor is
372212i
6
LTC3722-1/LTC3722-2
U
U
U
PI FU CTIO S (LTC3722-1/LTC3722-2)
recommended. The LTC3722-2 has a fixed blanking time
of approximately 80ns.
nous rectifier driver outputs (OUTE and OUTF). The nomi-
nal voltage on SPRG is 2V.
FB(Pin6/Pin6):ErrorAmplifierInvertingInput.Thisisthe
voltage feedback input for the LTC3722. The nominal
regulation voltage at FB is 1.204V.
VREF (Pin 14/Pin 14): Output of the 5V Reference. VREF is
capableofsupplyingupto19mAtoexternalcircuitry.VREF
shouldbedecoupledtoGNDwitha1µFceramiccapacitor.
SS(Pin7/Pin7):Soft-Start/RestartDelayCircuitryTiming
Capacitor. A capacitor from SS to GND provides a con-
trolled ramp of the current command (LTC3722-1), or
duty cycle (LTC3722-2). During overload conditions SS is
discharged to ground initiating a soft-start cycle.
OUTF (Pin 15/Pin 15): 50mA Driver for Synchronous
Rectifier Associated with OUTB and OUTC.
OUTE (Pin 16/Pin 16): 50mA Driver for Synchronous
Rectifier Associated with OUTA and OUTD.
OUTD(Pin17/Pin17):50mAdriverforLowSideoftheFull
Bridge Active Leg.
NC (Pin 8/Pin 8): No Connection. Tie this pin to GND.
PDLY(Pin9/Pin9):PassiveLegDelayCircuitInput. PDLY
is connected through a voltage divider to the left leg of the
bridge in adaptive ZVS mode. In fixed ZVS mode, a voltage
between 0V and 2.5V on PDLY, programs a fixed ZVS
delay time for the passive leg transition.
VCC (Pin 18/Pin 18): Supply Voltage Input to the
LTC3722-1/LTC3722-2 and 10.25V Shunt Regulator. The
chipisenabledafterVCC hasrisenhighenoughtoallowthe
VCC shunt regulator to conduct current and the UVLO
comparator threshold is exceeded. Once the VCC shunt
regulator has turned on, VCC can drop to as low as 6V and
maintain operation.
SBUS (Pin 10/Pin 10): Line Voltage Sense Input. SBUS is
connected to the main DC voltage feed by a resistive
voltage divider when using adaptive ZVS control. The
voltage divider is designed to produce 1.5V on SBUS at
nominal VIN. If SBUS is tied to VREF, the LTC3722-1/
LTC3722-2 is configured for fixed mode ZVS control.
OUTC (Pin 19/Pin 19): 50mA Driver for High Side of the
Full Bridge Active Leg.
OUTB (Pin 20/Pin 20): 50mA Driver for Low Side of the
Full Bridge Passive Leg.
ADLY (Pin 11/Pin 11): Active Leg Delay Circuit Input.
ADLY is connected through a voltage divider to the right
legofthebridgeinadaptiveZVSmode. InfixedZVSmode,
a voltage between 0V and 2.5V on ADLY, programs a fixed
ZVS delay time for the active leg transition.
OUTA (Pin 21/Pin 21): 50mA Driver for High Side of the
Full Bridge Passive Leg.
PGND (Pin 22/Pin 22): Power Ground for the LTC3722.
The output drivers of the LTC3722 are referenced to
PGND. Connect the ceramic VCC bypass capacitor directly
to PGND.
UVLO (Pin 12/Pin 12): Input to Program System Turn-On
andTurn-OffVoltages.ThenominalthresholdoftheUVLO
comparator is 5V. UVLO is connected to the main DC
system feed through a resistor divider. When the UVLO
threshold is exceeded, the LTC3722-1/LTC3722-2 com-
mences a soft start cycle and a 10µA (nominal) current is
fed out of UVLO to program the desired amount of system
hysteresis. The hysteresis level can be adjusted by chang-
ing the resistance of the divider.
GND (Pin 23/Pin 23): All circuits other than the output
drivers in the LTC3722 are referenced to GND. Use of a
ground plane is recommended but not absolutely neces-
sary.
CT (Pin 24/Pin 24): Timing Capacitor for the Oscillator.
Use a ±5% or better low ESR ceramic capacitor for best
results.
SPRG (Pin 13/Pin 13): A Resistor is connected between
SPRG and GND to set the turn-off delay for the synchro-
372212i
7
LTC3722-1/LTC3722-2
W
BLOCK DIAGRA S
LTC3722-1 Current Mode SYNC Phase Shift PWM
V
UVLO
12
V
C
T
SYNC
1
SPRG DPRG
13
SBUS
10
CC
REF
18
14
24
2
PDLY
9
V
UVLO
5V
CC
REF AND LDO
1.2V
OSC
10.25V = ON
6V = OFF
REF GOOD
OUTA
21
SYSTEM
FB
6
–
+
+
–
PASSIVE
DELAY
UVLO
Q
1 = ENABLE
0 = DISABLE
OUTB
20
T
QB
1.2V
5V
V
CC
GOOD
ERROR
AMPLIFIER
R1
50k
COMP
4
–
+
OUTE
16
SYNC
RECTIFIER
DRIVE
+
–
OUTF
15
LOGIC
PHASE
MODULATOR
R2
650mV
14.9k
QB
M1
R
S
OUTC
19
V
REF
Q
R
S
QB
ACTIVE
DELAY
12µA
SS
7
OUTD
17
SHUTDOWN
CURRENT
LIMIT
ADLY
11
+
–
FAULT
LOGIC
650mV
PGND
22
M2
SLOPE
COMPENSATION
C /R
T
CS
3
BLANK
270mV
+
–
5
23
PULSE BY PULSE
CURRENT LIMIT
R
LEB
GND
3722 • BD01
372212i
8
LTC3722-1/LTC3722-2
W
BLOCK DIAGRA S
LTC3722-2 Voltage Mode SYNC Phase Shift PWM
V
UVLO
12
V
C
T
SYNC
1
SPRG DPRG
13
SBUS
10
CC
REF
18
14
24
5
PDLY
9
V
UVLO
5V
CC
REF AND LDO
1.2V
OSC
10.25V = ON
6V = OFF
REF GOOD
OUTA
21
SYSTEM
ERROR
AMPLIFIER
FB
6
–
+
–
PASSIVE
DELAY
UVLO
Q
1 = ENABLE
0 = DISABLE
OUTB
20
T
QB
+
1.2V
5V
V
CC
GOOD
R1
50k
COMP
4
–
+
OUTE
16
SYNC
RECTIFIER
DRIVE
+
–
2
OUTF
15
LOGIC
PHASE
MODULATOR
RAMP
650mV
QB
R
S
OUTC
19
V
REF
QB
Q
R
S
ACTIVE
DELAY
12µA
SS
7
OUTD
17
SHUTDOWN
CURRENT
LIMIT
ADLY
11
+
–
FAULT
LOGIC
650mV
PGND
22
M2
3722 • BD02
CS
3
BLANK
270mV
+
–
23
PULSE BY PULSE
CURRENT LIMIT
GND
372212i
9
LTC3722-1/LTC3722-2
W U
W
TI I G DIAGRA
PASSIVE LEG
DELAY
ACTIVE LEG
DELAY
OUTA
OUTB
OUTC
OUTD
COMP
RAMP
COMP
COMP
OUTE
SYNC TURN OFF
DELAY (PROGRAMMABLE)
SYNC TURN OFF
DELAY (PROGRAMMABLE)
OUTF
NOTE: SHADED AREAS CORRESPOND TO POWER DELIVERY PULSES.
3722 TD
U
OPERATIO
ploit the generally undesirable parasitic elements present
within the power stage. The parasitic elements are utilized
to drive near lossless switching transitions for all of the
external power MOSFETs.
Phase Shift Full-Bridge PWM
Conventional full-bridge switching power supply topolo-
gies are often employed for high power, isolated DC/DC
and off-line converters. Although they require two addi-
tionalswitchingelements,substantiallygreaterpowerand
higher efficiency can be attained for a given transformer
sizecomparedtothemorecommonsingle-endedforward
and flyback converters. These improvements are realized
since the full-bridge converter delivers power during both
parts of the switching cycle, reducing transformer core
loss and lowering voltage and current stresses. The full-
bridge converter also provides inherent automatic trans-
former flux reset and balancing due to its bidirectional
drive configuration. As a result, the maximum duty cycle
rangeisextended,furtherimprovingefficiency.Softswitch-
ing variations on the full-bridge topology have been pro-
posedtoimproveandextenditsperformanceandapplica-
tion. These zero voltage switching (ZVS) techniques ex-
LTC3722-1/LTC3722-2 phase shift PWM controllers pro-
vide enhanced performance and simplify the design task
required for a ZVS phase shifted full-bridge converter. The
primary attributes of the LTC3722-1/LTC3722-2 as com-
pared to currently available solutions include:
1) Truly adaptive and accurate (DirectSense technology)
ZVS with programmable timeout.
Benefit: higher efficiency, higher duty cycle capability,
eliminates external trim.
2) Fixed ZVS capability.
Benefit: enables secondary side control and simplifies
external circuit.
372212i
10
LTC3722-1/LTC3722-2
U
OPERATIO
3) Internally generated drive signals with programmable
turn-off for current doubler synchronous rectifiers.
isolation barrier. Methods for providing drive to these
elements are detailed in this data sheet. The secondary
voltage of the transformer is the primary voltage divided
bythetransformerturnsratio. Similartoabuckconverter,
the secondary square wave is applied to an output filter
inductor and capacitor to produce a well regulated DC
output voltage.
Benefit: eliminates external glue logic, drivers, optimal
timing for highest efficiency.
4) Programmable (single resistor) leading edge blanking.
Benefit: prevents spurious operation, reduces external
filtering required on CS.
Switching Transitions
5) Programmable (single resistor) slope compensation.
Benefit: eliminates external glue circuitry.
The phase shifted full-bridge can be described by four
primary operating states. The key to understanding how
ZVS occurs is revealed by examining the states in detail.
Each full cycle of the transformer has two distinct periods
in which power is delivered to the output, and two “free-
wheeling” periods. The two sides of the external bridge
havefundamentallydifferentoperatingcharacteristicsthat
become important when designing for ZVS over a wide
load current range. The left bridge leg is referred to as the
“passive” leg, while the right leg is referred to as the
“active” leg. The following descriptions provide insight as
to why these differences exist.
6) Optimized current mode control architecture.
Benefit: eliminates glue circuitry, less overshoot at start-
up, faster recovery from system faults.
7) Programmable system undervoltage lockout and hys-
teresis.
Benefit: provides an accurate turn-on voltage for power
supply and reduces external circuitry.
As a result, the LTC3722-1/LTC3722-2 makes the ZVS
topology feasible for a wider variety of applications, in-
cluding those at lower power levels.
State 1 (Power Pulse 1)
Referring to Figure 1, State 1 begins with MA, MD and MF
“ON”andMB, MCandME“OFF.”Duringthesimultaneous
conduction of MA and MD, the full input voltage is applied
across the transformer primary winding and following the
dot convention, VIN/N is applied to the left side of LO1
allowing current to increase in LO1. The primary current
during this period is approximately equal to the output
inductor current (LO1) divided by the transformer turns
ratio plus the transformer magnetizing current (VIN • tON/
LMAG). MD turns off and ME turns on at the end of State 1.
The LTC3722-1/LTC3722-2 control four external power
switches in a full-bridge arrangement. The load on the
bridge is the primary winding of a power transformer. The
diagonal switches in the bridge connect the primary wind-
ing between the input voltage and ground every oscillator
cycle. The pair of switches that conduct are alternated by
an internal flip-flop in the LTC3722-1/LTC3722-2. Thus,
thevoltageappliedtotheprimaryisreversedinpolarityon
every switching cycle and each output drive signal is 1/2
the frequency of the oscillator. The on-time of each driver
signal is slightly less that 50%. The on-time overlap of the
diagonal switch pairs is controlled by the LTC3722-1/
LTC3722-2 phase modulation circuitry. (Refer to Block
and Timing Diagrams) This overlap sets the approximate
duty cycle of the converter. The LTC3722-1/LTC3722-2
driver output signals (OUTA to OUTF) are optimized for
interface with an external gate driver IC or buffer. External
power MOSFETs A and C require high side driver circuitry,
while B and D are ground referenced and E and F are
ground referenced but on the secondary side of the
State 2 (Active Transition and Freewheel Interval)
MD turns off when the phase modulator comparator
transitions. At this instant, the voltage on the MD/MC
junction begins to rise towards the applied input voltage
(VIN). The transformer’s magnetizing current and the
reflected output inductor current propels this action. The
slew rate is limited by MOSFET MC and MD’s output
capacitance (COSS), snubbing capacitance and the trans-
former interwinding capacitance. The voltage transition
372212i
11
LTC3722-1/LTC3722-2
U
OPERATIO
ontheactivelegfromthegroundreferencepointtoVIN will
always occur, independent of load current as long as
energy in the transformer’s magnetizing and leakage in-
ductance is greater than the capacitive energy. That is,
1/2 • (LM + LI) • IM2 > 1/2 • 2 • COSS • VIN2 — the worst case
occurs when the load current is zero. This condition is
usually easy to meet. The magnetizing current is virtually
constant during this transition because the magnetizing
inductance has positive voltage applied across it through-
out the low to high transition. Since the leg is actively
driven by this “current source,” it is called the active or
linear transition. When the voltage on the active leg has
risen to VIN, MOSFET MC is switched on by the ZVS
circuitry. The primary current now flows through the two
high side MOSFETs (MA and MC). The transformer’s
secondary windings are electrically shorted at this time
since both ME and MF are “ON”. As long as positive
current flows in LO1 and LO2, the transformer primary
(magnetizing) inductance is also shorted through normal
transformer action. MA and MF turn off at the end of
State 2.
resonantly transferred to the capacitive elements, hence,
the term passive or resonant transition. Assuming there is
sufficient inductive energy to propel the bridge leg to
GND, the time required will be approximately equal to
π • √LC/2. When the voltage on the passive leg nears GND,
MOSFET MB is commanded “ON” by the ZVS circuitry.
Current continues to increase in the leakage and external
series inductance which is opposite in polarity to the
reflected output inductor current. When this current is
equal in magnitude to the reflected output current, the
primary current reverses direction, the opposite second-
ary winding becomes forward biased and a new power
pulseisinitiated. Thetimerequiredforthecurrentreversal
reduces the effective maximum duty cycle and must be
considered when computing the power transformer turns
ratio. If ZVS is required over the entire range of loads, a
small commutating inductor is added in series with the
primary to aid with the passive leg transition, since the
leakage inductance alone is usually not sufficient and
predictable enough to guarantee ZVS over the full load
range.
State 3 (Passive Transition)
State 4 (Power Pulse 2)
MA turns off when the oscillator timing period ends, i.e.,
the clock pulse toggles the internal flip-flop. At the instant
MA turns off, the voltage on the MA/MB junction begins to
decay towards the lower supply (GND). The energy avail-
abletodrivethistransitionislimitedtotheprimaryleakage
inductance and added commutating inductance which
have (IMAG + IOUT/2N) flowing through them initially. The
magnetizing and output inductors don’t contribute any
energy because they are effectively shorted as mentioned
previously, significantly reducing the available energy.
Thisisthemajordifferencebetweentheactiveandpassive
transitions. If the energy stored in the leakage and com-
mutating inductance is greater than the capacitive energy,
the transition will be completed successfully. During the
transition, an increasing reverse voltage is applied to the
leakageandcommutatinginductances,helpingtheoverall
primary current to decay. The inductive energy is thus
During power pulse 2, current builds up in the primary
winding in the opposite direction as power pulse 1. The
primary current consists of reflected output inductor
current and current due to the primary magnetizing induc-
tance. At the end of State 4, MOSFET MC turns off and an
active transition, essentially similar to State 2, but oppo-
site in direction (high to low) takes place.
Zero Voltage Switching (ZVS)
Alosslessswitchingtransitionrequiresthattherespective
full-bridge MOSFETs be switched to the “ON” state at the
exact instant their drain to source voltage is zero. Delaying
the turn-on results in lower efficiency due to circulating
current flowing in the body diode of the primary side
MOSFETratherthanitslowresistancechannel.Premature
turn-on produces hard switching of the MOSFETs, in-
creasing noise and power dissipation.
372212i
12
LTC3722-1/LTC3722-2
U
OPERATIO
State 1.
POWER PULSE 1
V
OUT
V
IN
L01
L02
MA
MC
MD
LOAD
N:1
MB
+
MF
ME
I
P
≈ I /N + (V • T )/L
L01
IN
OVL MAG
PRIMARY AND
SECONDARY SHORTED
State 2.
ACTIVE
TRANSITION
FREEWHEEL
INTERVAL
V
OUT
MA
MB
MC
MD
MA
MB
MC
MD
LOAD
MF
ME
State 3.
PASSIVE
TRANSITION
MA
MB
MC
MD
State 4.
POWER PULSE 2
V
OUT
MA
MB
MC
LOAD
MD
+
MF
ME
3722 F01
Figure 1. ZVS Operation
372212i
13
LTC3722-1/LTC3722-2
U
OPERATIO
ADLYandPDLYareconnectedthroughvoltagedividersto
the active and passive bridge legs respectively. The lower
resistor in the divider is set to 1k. The upper resistor in the
divider is selected for the desired positive transition trip
threshold.
LTC3722-1/LTC3722-2 Adaptive Delay Circuitry
The LTC3722-1/LTC3722-2 monitors both the input sup-
plyandinstantaneousbridgelegvoltages, andcommands
a switching transition when the expected zero voltage
condition is reached. DirectSense technology provides
optimal turn-on delay timing, regardless of input voltage,
output load, or component tolerances. The DirectSense
technique requires only a simple voltage divider sense
network to implement. If there is not enough energy to
fully commutate the bridge leg to a ZVS condition, the
LTC3722-1/LTC3722-2 automatically overrides the
DirectSense circuitry and forces a transition. The override
or default delay time is programmed with a resistor from
To set up the ADLY and PDLY resistors, first determine at
what drain to source voltage to turn-on the MOSFETs.
FinitedelaysexistbetweenthetimeatwhichtheLTC3722-
1/LTC3722-2 controller output transitions, to the time at
which the power MOSFET switches on due to MOSFET
turn on delay and external driver circuit delay. Ideally, we
want the power MOSFET to switch at the instant there is
zero volts across it. By setting a threshold voltage for
ADLY and PDLY corresponding to several volts across the
MOSFET, the LTC3722-1/LTC3722-2 can “anticipate” a
zero voltage VDS and signal the external driver and switch
to turn-on. The amount of anticipation can be tailored for
anyapplicationbymodifyingtheupperdividerresistor(s).
TheLTC3722-1/LTC3722-2 DirectSensecircuitrysources
a trimmed current out of PDLY and ADLY after a low to
high level transition occurs. This provides hysteresis and
noise immunity for the PDLY and ADLY circuitry, and sets
the high to low threshold on ADLY or PDLY to nearly the
same level as the low to high threshold, thereby making
the upper and lower MOSFET VDS switch points virtually
identical, independent of VIN.
DPRG to VREF
.
Adaptive Mode
The LTC3722-1/LTC3722-2 are configured for adaptive
delay sensing with three pins, ADLY, PDLY and SBUS.
ADLY and PDLY sense the active and passive delay legs
respectively via a voltage divider network as shown in
Figure 2.
V
IN
A
B
C
D
R2
ADLY
SBUS
PDLY
R5
R6
Example: VIN = 48V nominal (36V to 72V)
R1
1k
R3
1k
R4
1k
1. Set up SBUS: 1.5V is desired on SBUS with VIN = 48V.
R
CS
Set divider current to 100µA.
1922 F02
R1 = 1.5V/100µA = 15k.
Figure 2. Adaptive Mode
R2 = (48V – 1.5V)/100µA = 465k.
An optional small capacitor (0.001µF) can be added
The threshold voltage on PDLY and ADLY for both the
rising and falling transitions is set by the voltage on SBUS.
A buffered version of this voltage is used as the threshold
level for the internal DirectSense circuitry. At nominal VIN,
the voltage on SBUS is set to 1.5V by an external voltage
divider between VIN and GND, making this voltage directly
proportional to VIN. The LTC3722-1/LTC3722-2
DirectSense circuitry uses this characteristic to zero
voltage switch all of the external power MOSFETs, inde-
pendent of input voltage.
across R1 to decouple noise from this input.
2. Set up ADLY and PDLY: 7V of “anticipation” is desired
in this circuit to account for the delays of the external
MOSFET driver and gate drive components.
R3, R4 = 1k, sets a nominal 1.5mA in the divider
chain at the threshold.
R5, R6 = (48V – 7V – 1.5V)/1.5mA = 26.3k,
use (2) equal 13k segments.
372212i
14
LTC3722-1/LTC3722-2
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OPERATIO
Powering the LTC3722-1/LTC3722-2
Fixed Delay Mode
TheLTC3722-1/LTC3722-2utilizeanintegratedVCC shunt
regulatortoservethedualpurposesoflimitingthevoltage
applied to VCC as well as signaling that the chip’s bias
voltage is sufficient to begin switching operation (under
voltage lockout). With its typical 10.2V turn-on voltage
and 4.2V UVLO hysteresis, the LTC3722-1/LTC3722-2 is
tolerant of loosely regulated input sources such as an
auxiliary transformer winding. The VCC shunt is capable of
sinking up to 25mA of externally applied current. The
UVLO turn-on and turn-off thresholds are derived from an
internally trimmed reference making them extremely ac-
curate. In addition, the LTC3722-1/LTC3722-2 exhibits
very low (145µA typ) start-up current that allows the use
of 1/8W to 1/4W trickle charge start-up resistors.
TheLTC3722-1/LTC3722-2providestheflexibilitythrough
theSBUSpintodisabletheDirectSensedelaycircuitryand
enable fixed ZVS delays. The level of fixed ZVS delay is
proportional to the voltage programmed through the volt-
age divider on the PDLY and ADLY pins. See Figure 3 for
more detail.
V
REF
R1
R2
SBUS
PDLY
ADLY
R3
3722 F03
The trickle charge resistor should be selected as follows:
Figure 3. Setup for Fixed ZVS Delays
RSTART(MAX) = VIN(MIN) – 10.7V/250µA
Programming Adaptive Delay Time-Out
Adding a small safety margin and choosing standard
values yields:
The LTC3722-1/LTC3722-2 controllers include a feature
to program the maximum time delay before a bridge
switch turn on command is summoned. This function will
come into play if there is not enough energy to commutate
a bridge leg to the opposite supply rail, therefore bypass-
ing the adaptive delay circuitry. The time delay can be set
with an external resistor connected between DPRG and
VREF ( see Figure 4). The nominal regulated voltage on
DPRG is 2V. The external resistor programs a current
which flows into DPRG. The delay can be adjusted from
approximately 35ns to 300ns, depending on the resistor
value. If DPRG is left open, the delay time is approximately
400ns. The amount of delay can also be modulated based
on an external current source that feeds current into
DPRG. Care must be taken to limit the current fed into
DPRG to 350µA or less.
APPLICATION
DC/DC
V
RANGE
R
START
IN
36V to 72V
85V to 270V
100k
430k
1.4M
Off-Line
RMS
PFC Preregulator
390V
DC
VCC should be bypassed with a 0.1µF to 1µF multilayer
ceramic capacitor to decouple the fast transient currents
demanded by the output drivers and a bulk tantalum or
electrolytic capacitor to hold up the VCC supply before the
bootstrap winding, or an auxiliary regulator circuit takes
over.
CHOLDUP = (ICC + IDRIVE) • tDELAY/3.8V
(minimum UVLO hysteresis)
Regulated bias supplies as low as 7V can be utilized to
provide bias to the LTC3722-1/LTC3722-2. Refer to
Figure 5 for various bias supply configurations.
V
REF
V
R
DPRG
IN
DPRG
V
< V
UVLO
12V ±10%
1.5k
BIAS
1N5226
3V
1N914
R
START
+
–
+
V
–
TURN-ON
OUTPUT
+
2V
SBUS
0.1µF
0.1µF
C
HOLD
3722 F04
V
CC
V
CC
3722 F04
Figure 4. Delay Timeout Circuitry
Figure 5. Bias Configurations
372212i
15
LTC3722-1/LTC3722-2
U
OPERATIO
Programming Undervoltage Lockout
maintains decent regulation as the supply voltage varies,
and it does not require full safety isolation from the input
winding of the transformer. Some manufacturers include
a primary winding for this purpose in their standard
product offerings as well. A different approach is to add a
winding to the output inductor and peak detect and filter
the square wave signal (see Figure 7b). The polarity of this
winding is designed so that the positive voltage square
wave is produced while the output inductor is freewheel-
ing. An advantage of this technique over the previous is
that it does not require a separate filter inductor and since
the voltage is derived from the well-regulated output
voltage, it is also well controlled. One disadvantage is that
this winding will require the same safety isolation that is
required for the main transformer. Another disadvantage
is that a much larger VCC filter capacitor is needed, since
it does not generate a voltage as the output is first starting
up, or during short-circuit conditions.
The LTC3722-1/LTC3722-2 provides undervoltage lock-
out (UVLO) control for the input DC voltage feed to the
power converter in addition to the VCC UVLO function
described in the preceding section. Input DC feed UVLO is
provided with the UVLO pin. A comparator on UVLO
compares a divided down input DC feed voltage to the 5V
precision reference. When the 5V level is exceeded on
UVLO, the SS pin is released and output switching com-
mences. At the same time a 10µA current is enabled which
flows out of UVLO into the voltage divider connected to
UVLO. The amount of DC feed hysteresis provided by this
current is: 10µA • RTOP, see Figure 6. The system UVLO
threshold is: 5V • {(RTOP + RBOTTOM)/RBOTTOM}. If the
voltage applied to UVLO is present and greater than 5V
prior to the VCC UVLO circuitry activation, then the internal
UVLO logic will prevent output switching until the follow-
ing three conditions are met: (1) VCC UVLO is enabled, (2)
VREF is in regulation and (3) UVLO pin is greater than 5V.
V
IN
V
CC
R
START
UVLO can also be used to enable and disable the power
converter. An open drain transistor connected to UVLO as
shown in Figure 6 provides this capability.
2k
+
15V*
0.1µF
C
HOLD
1922 F05a
*OPTIONAL
R
TOP
Figure 7a. Auxiliary Winding Bias Supply
UVLO
ON OFF
R
BOTTOM
V
IN
V
OUT
L
OUT
R
+
START
ISO BARRIER
3722 F0A
Figure 6. System UVLO Setup
0.1µF
C
HOLD
Off-Line Bias Supply Generation
1922 F05b
V
CC
If a regulated bias supply is not available to provide VCC
voltage to the LTC3722-1/LTC3722-2 and supporting
circuitry, onemustbegenerated. Sincethepowerrequire-
ment is small, approximately 1W, and the regulation is not
critical, a simple open-loop method is usually the easiest
and lowest cost approach. One method that works well is
to add a winding to the main power transformer, and post
regulate the resultant square wave with an L-C filter (see
Figure 7a). The advantage of this approach is that it
Figure 7b. Output Inductor Bias Supply
Programming the LTC3722-1/LTC3722-2 Oscillator
The high accuracy LTC3722-1/LTC3722-2 oscillator cir-
cuit provides flexibility to program the switching fre-
quency, slope compensation, and synchronization with
minimalexternalcomponents.TheLTC3722-1/LTC3722-2
372212i
16
LTC3722-1/LTC3722-2
U
OPERATIO
C
OF SLAVE(S) IS
T
oscillator circuitry produces a 2.2V peak-to-peak ampli-
tude ramp waveform on CT and a narrow pulse on SYNC
that can be used to synchronize other PWM chips. Typical
maximum duty cycles of 98.5% are obtained at 300kHz
and 96% at 1MHz. A compensating slope current is
derived from the oscillator ramp waveform and sourced
out of CS.
LTC3722
1.25 C OF MASTER.
T
1k
5.1k
1k
C
T
SYNC
SYNC
LTC3722
C
T
C
T
SYNC
LTC3722
SLAVES
5.1k
C
T
C
T
MASTER
•
•
•
C
T
5.1k
UP TO
5 SLAVES
3722 F06a
The desired amount of slope compensation is selected
with single external resistor. A capacitor to GND on CT
programs the switching frequency. The CT ramp dis-
charge current is internally set to a high value (>10mA).
The dedicated SYNC I/O pin easily achieves synchroniza-
tion. The LTC3722-1/LTC3722-2 can be set up to either
synchronize other PWM chips or be synchronized by
another chip or external clock source. The 1.8V SYNC
threshold allows the LTC3722-1/LTC3722-2 to be syn-
chronized directly from all standard 3V and 5V logic
families.
Figure 8a. SYNC Output (Master Mode)
AMPLITUDE > 1.8V
100ns < PW < 0.4/ƒ
LTC3722
EXTERNAL
FREQUENCY
SOURCE
1k
C
SYNC
5.1k
T
C
T
3722 F06b
Figure 8b. SYNC Input from an External Source
tion of the current control loop. In general, if the system
duty cycle exceeds 50% in a fixed frequency, continuous
current mode converter, an unstable condition exists
within the current control loop. Any perturbation in the
current signal is amplified by the PWM modulator result-
ing in an unstable condition. Some common manifesta-
tions of this include alternate pulse nonuniformity and
pulse width jitter. Fortunately, this can be addressed by
adding a corrective slope to the current sense signal or by
subtracting the same slope from the current command
signal (error amplifier output). In theory, the current
doubler output configuration does not require slope com-
pensation since the output inductor duty cycles only
approach 50%. However, transient conditions can mo-
mentarily cause higher duty cycles and therefore, the
possibility for unstable operation. The exact amount of
requiredslopecompensationiseasilyprogrammedbythe
LTC3722-1/LTC3722-2 with the addition of a single exter-
nal resistor (see Figure 9). The LTC3722-1/LTC3722-2
generates a current that is proportional to the instanta-
neous voltage on CT, (33µA/V(CT)). Thus, at the peak of CT,
this current is approximately 82.5µA and is output from
the CS pin. A resistor connected between CS and the
externalcurrentsenseresistorsumsintherequiredamount
Design Procedure:
1. Choose CT for the desired oscillator frequency. The
switching frequency selected must be consistent with the
power magnetics and output power level. This is detailed
in the Transformer Design section. In general, increasing
theswitchingfrequencywilldecreasethemaximumachiev-
able output power, due to limitations of maximum duty
cycle imposed by transformer core reset and ZVS. Re-
member that the output frequency is 1/2 that of the
oscillator.
CT = 1/(13.4k • fOSC
)
Example: Desired fOSC = 330kHz
CT = 1/(13.4k • fOSC) = 226pF, choose closest standard
valueof220pF. A5%orbettertolerancemultilayerNPO
or X7R ceramic capacitor is recommended for best
performance.
2.TheLTC3722-1/LTC3722-2caneithersynchronizeother
PWMs,orbesynchronizedtoanexternalfrequencysource
or PWM chip. See Figure 8 for details.
3. Slope compensation is required for most peak current
mode controllers in order to prevent subharmonic oscilla-
372212i
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LTC3722-1/LTC3722-2
U
OPERATIO
ofslopecompensation. Thevalueofthisresistorisdepen-
Current Sensing and Overcurrent Protection
dent on several factors including minimum VIN, VOUT
,
Current sensing provides feedback for the current mode
control loop and protection from overload conditions. The
LTC3722-1/LTC3722-2 are compatible with either resis-
tive sensing or current transformer methods. Internally
connected to the LTC3722-1/LTC3722-2 CS pin are two
comparators that provide pulse-by-pulse and overcurrent
shutdown functions respectively. (See Figure 10)
switching frequency, current sense resistor value and
output inductor value. An illustrative example with the
design equation is provided below.
Example: VIN = 36V to 72V
VOUT = 3.3V
IOUT = 40A
The pulse-by-pulse comparator has a 270mV nominal
threshold. If the 270mV threshold is exceeded, the PWM
cycle is terminated. The overcurrent comparator is set
approximately 2x higher than the pulse-by-pulse level. If
the current signal exceeds this level, the PWM cycle is
terminated, the soft-start capacitor is quickly discharged
and a soft-start cycle is initiated. If the overcurrent condi-
tion persists, the LTC3722-1/LTC3722-2 halts PWM op-
eration and waits for the soft-start capacitor to charge up
to approximately 4V before a retry is allowed. The soft-
start capacitor is charged by an internal 12µA current
source. If the fault condition has not cleared when soft-
start reaches 4V, the soft-start pin is again discharged and
a new cycle is initiated. This is referred to as hiccup mode
operation. In normal operation and under most abnormal
conditions, the pulse-by-pulse comparator is fast enough
to prevent hiccup mode operation. In severe cases, how-
ever, with high input voltage, very low RDS(ON) MOSFETs
and a shorted output, or with saturating magnetics, the
overcurrent comparator provides a means of protecting
the power converter.
L = 2.2µH
Transformer turns ratio (N) = VIN(MIN) • DMAX
VOUT = 3
/
RCS = 0.025Ω
fSW = 300kHz, i.e., transformer f = fSW/2 = 150kHz
RSLOPE = VO • RCS/(2 • L • fT •82.5µA • N) = 3.3V • 0.025/
(2 • 2.2µA • 100k • 82.5µA • 3)
RSLOPE = 505Ω, choose the next higher standard value
to account for tolerances in ISLOPE, RCS, N and L.
LTC3722
BRIDGE
CURRENT
V(C )
33k
T
I =
R
SLOPE
C
T
CS
ADDED
SLOPE
R
CS
33k
CURRENT SENSE
WAVEFORM
3722 F07
Figure 9. Slope Compensation Circuitry
H = SHUTDOWN
PWM
OUTPUTS
UVLO
ENABLE
LATCH
PULSE BY PULSE
CURRENT LIMIT
PWM
LOGIC
Q
φ
MOD
+
Q
S
R
Q
S
CS
–
270mV
OVERLOAD
CURRENT LIMIT
R
CS
+
–
12µA
4.1V
S
R
Q
–
+
650mV
SS
UVLO
ENABLE
+
–
0.4V
C
SS
Q
3722 F08
Figure 10. Current Sense/Fault Circuitry Detail
372212i
18
LTC3722-1/LTC3722-2
U
OPERATIO
Leading Edge Blanking
Current Transformer Sensing
TheLTC3722-1/LTC3722-2providesprogrammablelead-
ing edge blanking to prevent nuisance tripping of the
currentsensecircuitry. Leadingedgeblankingrelievesthe
filteringrequirementsfortheCSpin,greatlyimprovingthe
response to real overcurrent conditions. It also allows the
use of a ground referenced current sense resistor or
transformer(s), further simplifying the design. With a
single 10k to 100k resistor from RLEB to GND, blanking
times of approximately 40ns to 320ns are programmed. If
not required, connecting RLEB to VREF can disable leading
edge blanking. Keep in mind that the use of leading edge
blanking will set a minimum linear control range for the
phase modulation circuitry.
Acurrentsensetransformercanbeusedinlieuofresistive
sensing with the LTC3722-1/LTC3722-2. Current sense
transformers are available in many styles from several
manufacturers. A typical sense transformer for this appli-
cation will use a 1:50 turns ratio (N), so that the sense
resistor value is N times larger, and the secondary current
Ntimessmallerthanintheresistivesensecase.Therefore,
thesenseresistorpowerlossisaboutNtimeslesswiththe
transformer method, neglecting the transformers core
and copper losses. The disadvantages of this approach
include, higher cost and complexity, lower accuracy, core
reset/max duty cycle limitations and lower speed. Never-
theless, for very high power applications, this method is
preferred. The sense transformer primary is placed in the
same location as the ground referenced sense resistor, or
between the upper MOSFET drains in the (MA, MC) and
VIN. The advantage of the high side location is a greater
immunity to leading edge noise spikes, since gate charge
current and reflected rectifier recovery current are largely
eliminated. Figure 11 illustrates a typical current sense
transformer based sensing scheme. RS in this case is
calculated the same as in the resistive case, only its value
is increased by the sense transformer turns ratio. At high
duty cycles, it may become difficult or impossible to reset
the current transformer. This is because the required
transformer reset voltage increases as the available time
forresetdecreasestoequalizethe(volt•seconds)applied.
The interwinding capacitance and secondary inductance
of the current sense transformer form a resonant circuit
that limits the dV/dT on the secondary of the CS trans-
former. This in turn limits the maximum achievable duty
cycle for the CS transformer. Attempts to operate beyond
this limit will cause the transformer core to “walk” and
eventually saturate, opening up the current feedback loop.
Resistive Sensing
A resistor connected between input common and the
sources of MB and MD is the simplest method of current
sensing for the full-bridge converter. This is the preferred
method for low to moderate power levels. The sense
resistor should be chosen such that the maximum rated
output current for the converter can be delivered at the
lowest expected VIN. Use the following formula to calcu-
late the optimal value for RCS.
LTC3722-1:
270mV – (82.5µA •RSLOPE
)
RCS
=
IP(PEAK)
IO(MAX)
V
IN(MAX) •2•DMIN
IP(PEAK) =
+
+
2•N•EFF
LMAG • fCLK
VO(1– DMIN
)
LOUT • fCLK•N
Common methods to address this limitation include:
NP
NS
1. Reducing the maximum duty cycle by lowering the
power transformer turns ratio.
=
where: N = Transformer turns ratio
2. Reducing the switching frequency of the converter.
3. Employ external active reset circuitry.
LTC3722-2:
270mV
RCS
=
IP(PEAK)
372212i
19
LTC3722-1/LTC3722-2
U
OPERATIO
4. Using two CS transformers summed together.
directly. The voltage COMP is internally attenuated by the
LTC3722-1. The attenuated COMP voltage provides one
input to the phase modulation comparator. This is the
current command. The other input to the phase modula-
tion comparator is the RAMP voltage, level shifted by
approximately 650mV. This is the current loop feedback.
During every switching cycle, alternate diagonal switches
(MA-MD or MB-MC) conduct and cause current in an
output inductor to increase. This current is seen on the
primary of the power transformer divided by the turns
ratio. Since the current sense resistor is connected be-
tween GND and the two bottom bridge transistors, a
voltage proportional to the output inductor current will be
seen across RSENSE. The high side of RSENSE is also
connectedtoCS,usuallythroughasmallresistor(RSLOPE).
When the voltage on CS exceeds either (COMP/5.2)
–650mV, or 270mV, the overlap conduction period will
terminate. Duringnormaloperation, theattenuatedCOMP
voltagewilldeterminetheCStrippoint.Duringstart-up,or
slewing conditions following a large load step, the 270mV
CS threshold will terminate the cycle, as COMP will be
driven high, such that the attenuated version exceeds the
270mV threshold. In extreme conditions, the 650mV
threshold on CS will be exceeded, invoking a soft-start/
restart cycle.
5. Choose a CS transformer optimized for high frequency
applications.
MD
SOURCE
MB
SOURCE
R
SLOPE
N:1
RAMP
CS
CURRENT
TRANSFORMER
R
S
OPTIONAL
FILTERING
1922 F10
Figure 11. Current Transformer Sense Circuitry
Phase Modulator (LTC3722-1)
The LTC3722-1 phase modulation control circuitry is
comprisedofthephasemodulationcomparatorandlogic,
the error amplifier, and the soft-start amplifier (see Fig-
ure 12). Together, these elements develop the required
phase overlap (duty cycle) required to keep the output
voltage in regulation. In isolated applications, the sensed
output voltage error signal is fed back to COMP across the
input to output isolation boundary by an optical coupler
and shunt reference/error amplifier (LT®1431) combina-
tion. The FB pin is connected to GND, forcing COMP high.
The collector of the optoisolator is connected to COMP
TOGGLE
F/F
A
B
ERROR
AMPLIFIER
Q
CLK
FB
–
+
PHASE
MODULATION
COMPARATOR
Q
1.2V
V
PHASE
MODULATION
LOGIC
50k
COMP
–
+
C
D
S
Q
REF
+
R
CLK
12µA
650mV
SOFT-START
AMPLIFIER
–
FROM
CURRENT
LIMIT
SS
+
–
COMPARATOR
14.9k
R
LEB
CS
BLANKING
Q
S
R
3722 F11
CLK
Figure 12. Phase Modulation Circuitry (LTC3722-1)
372212i
20
LTC3722-1/LTC3722-2
U
OPERATIO
Selecting the Power Stage Components
maximized at high duty cycle and decreases as the duty
cycle reduces. This means that a current doubler con-
verter requires less output capacitance for the same
performance as a conventional converter. By determining
the minimum duty cycle for the converter, worse-case
Perhaps the most critical part of the overall design of the
converter is selecting the power MOSFETs, transformer,
inductors and filter capacitors. Tremendous gains in effi-
ciency, transient performance and overall operation can
beobtainedaslongasafewsimpleguidelinesarefollowed
with the phase shifted full-bridge topology.
V
OUT ripple can be derived by the formula given below.
VO •ESR
VORIPPLE = IRIPPLE •ESR =
(1– D)(1– 2D)
LO •2• fSW
Power Transformer
where:
D
Switching frequency, core material characteristics, series
resistance and input/output voltages all play an important
roleintransformerselection. Closeattentionalsoneedsto
be paid to leakage and magnetizing inductances as they
play an important role in how well the converter will
achieve ZVS. Planar magnetics are very well suited to
these applications because of their excellent control of
these parameters.
= minimum duty cycle
fSW = oscillator frequency
LO = output inductance
ESR = output capacitor series resistance
Theamountofbulkcapacitancerequiredisusuallysystem
dependent, but has some relationship to output induc-
tancevalue,switchingfrequency,loadpoweranddynamic
load characteristics. Polymer electrolytic capacitors are
the preferred choice for their combination of low ESR,
small size and high reliability. For less demanding applica-
tions, or those not constrained by size, aluminum electro-
lytic capacitors are commonly applied. Most
DC/DCconvertersinthe100kHzto300kHzrangeuse20µF
to 25µF of bulk capacitance per watt of output power.
Converters switching at higher frequencies can usually
use less bulk capacitance. In systems where dynamic
response is critical, additional high frequency capacitors,
such as ceramics, can substantially reduce voltage tran-
sients.
Turns Ratio
The required turns ratio for a current doubler secondary is
given below. Depending on the magnetics selected, this
value may need to be reduced slightly.
Turns ratio formula:
V
IN(MIN) •DMAX
N =
2•VOUT
where:
VIN(MIN) = Minimum VIN for operation
MAX = Maximum duty cycle of controller (DCMAX
D
)
Power MOSFETs
Output Capacitors
The full-bridge power MOSFETs should be selected for
their RDS(ON) and BVDSS ratings. Select the lowest BVDSS
rated MOSFET available for a given input voltage range
leaving at least a 20% voltage margin. Conduction losses
are directly proportional to RDS(ON). Since the full-bridge
has two MOSFETs in the power path most of the time,
conduction losses are approximately equal to:
Outputcapacitorselectionhasadramaticimpactonripple
voltage, dynamic response to transients and stability.
Capacitor ESR along with output inductor ripple current
will determine the peak-to-peak voltage ripple on the
output. The current doubler configuration is advanta-
geous because it has inherent ripple current reduction.
The dual output inductors deliver current to the output
capacitor 180 degrees out of phase, in effect, partially
canceling each other’s ripple current. This reduction is
2 • RDS(ON) • I2, where I = IO/2N
372212i
21
LTC3722-1/LTC3722-2
U
OPERATIO
Table 1.Switching Frequency vs Power Level
Switching losses in the MOSFETs are dominated by the
power required to charge their gates, and turn-on and
turn-off losses. At higher power levels, gate charge power
is seldom a significant contributor to efficiency loss. ZVS
operation virtually eliminates turn-on losses. Turn-off
lossesarereducedbytheuseofanexternaldraintosource
snubber capacitor and/or a very low resistance turn-off
driver. If synchronous rectifier MOSFETs are used on the
secondary, the same general guidelines apply. Keep in
mind, however, thattheBVDSS ratingneededforthesecan
be greater than VIN(MAX)/N, depending on how well the
secondary is snubbed. Without snubbing, the secondary
voltage can ring to levels far beyond what is expected due
totheresonanttankcircuitformedbetweenthesecondary
leakage inductance and the COSS (output capacitance) of
the synchronous rectifier MOSFETs.
<50W
<100W
<200W
<500W
<1kW
600kHz
450kHz
300kHz
200kHz
150kHz
100kHz
<2kW
Closing the Feedback Loop
Closing the feedback loop with the full-bridge converter
involves identifying where the power stage and other
system poles/zeroes are located and then designing a
compensationnetworkaroundtheconverterserrorampli-
fier to shape the frequency response to insure adequate
phase margin and transient response. Additional modifi-
cations will sometimes be required in order to deal with
parasitic elements within the converter that can alter the
feedback response. The compensation network will vary
dependingontheloadcurrentrangeandthetypeofoutput
capacitors used. In isolated applications, the compensa-
tion network is generally located on the secondary side of
the power supply, around the error amplifier of the
optocoupler driver, usually an LT1431 or equivalent. In
nonisolated systems, the compensation network is lo-
catedaroundtheLTC3722-1/LTC3722-2’serroramplifier.
Switching Frequency Selection
Unless constrained by other system requirements, the
power converter’s switching frequency is usually set as
highaspossiblewhilestayingwithinthedesiredefficiency
target. The benefits of higher switching frequencies are
many including smaller size, weight and reduced bulk
capacitance. In the full-bridge phase shift converter, these
principles are generally the same with the added compli-
cation of maintaining zero voltage transitions, and there-
fore, higher efficiency. ZVS is achieved in a finite time
during the switching cycle. During the ZVS time, power is
not delivered to the output; the act of ZVS reduces the
maximum available duty cycle. This reduction is propor-
tional to maximum output power since the parasitic ca-
pacitive element (MOSFETs) that increase ZVS time get
larger as power levels increase. This implies an inverse
relationship between output power level and switching
frequency. Table 1 displays recommended maximum
switching frequency vs power level for a 30V/75V in to
3.3V/5V out converter. Higher switching frequencies can
be used if the input voltage range is limited, the output
voltage is lower and/or lower efficiency can be tolerated.
In current mode control, the dominant system pole is
determined by the load resistance (VO/IO) and the output
capacitor 1/(2π • RO • CO). The output capacitors ESR
1/(2π • ESR • CO) introduces a zero. Excellent DC line and
load regulation can be obtained if there is high loop gain at
DC. This requires an integrator type of compensator
around the error amplifier. A procedure is provided for
deriving the required compensation components. More
complex types of compensation networks can be used to
obtain higher bandwidth if necessary.
Step 1. Calculate location of minimum and maximum
output pole:
372212i
22
LTC3722-1/LTC3722-2
U
OPERATIO
FP1(MIN) = 1/(2π • RO(MAX) • CO)
Polymer Electrolytic (see Figure 13) 1/(2πCCRI) sets a
low frequency pole. 1/(2πCCRF) sets the low frequency
zero. The zero frequency should coincide with the worst-
case lowest output pole frequency. The pole frequency
and mid frequency gain (RF/RI) should be set such so that
the loop crosses over zero dB with a –1 slope at a
frequency lower than (fSW/8). Use a bode plot to graphi-
cally display the frequency response. An optional higher
frequency pole set by CP2 and Rf is used to attenuate
switching frequency noise.
FP1(MAX) = 1/(2π • RO(MIN) • CO)
Step 2. Calculate ESR zero location:
FZ1 = 1/(2π • RESR • CO)
Step 3. Calculate the feedback divider gain:
RB/(RB + RT) or VREF/VOUT
IfPolymerelectrolyticoutputcapacitorsareused, theESR
zero can be employed in the overall loop compensation
and optimum bandwidth can be achieved. If aluminum
electrolytics are used, the loop will need to be rolled off
priortotheESRzerofrequency, makingtheloopresponse
slower.AlinearizedSPICEmacromodelofthecontrolloop
is very helpful tool to quickly evaluate the frequency
response of various compensation networks.
Aluminum Electrolytic (see Figure 13) the goal of this
compensator will be to cross over the output minimum
pole frequency. Set a low frequency pole with CC and RIN
at a frequency that will cross over the loop at the output
pole minimum F, place the zero formed by CC and Rf at the
output pole F.
V
OUT
COMP
OPTO
C
P2
V
OUT
OPTIONAL
C
C
R
f
R
C
I
O
REF
COLL
R
L
–
+
2.5V
ESR
R
D
LT1431 OR EQUIVALENT
PRECISION ERROR
AMP AND REFERENCE
1922 F12
Figure 13. Compensation for Polymer Electrolytic
372212i
23
LTC3722-1/LTC3722-2
U
OPERATIO
Synchronous Rectification
new primary side power delivery pulse. This feature pro-
vides optimized timing for the synchronous MOSFETs
which improves efficiency. At higher load currents it
becomes more advantageous to delay the turn-off of the
synchronousrectifiersuntilthetransformercorehasbeen
reset to begin the new power pulse. This allows for
secondary freewheeling current to flow through the syn-
chronous MOSFET channel instead of its body diode.
The LTC3722-1/LTC3722-2 produces the precise timing
signals necessary to control current doubler secondary
side synchronous MOSFETs on OUTE and OUTF. Syn-
chronousrectifiersareusedinplaceofSchottkyorSilicon
diodes on the secondary side of the power supply. As
MOSFET RDS(ON) levels continue to drop, significant effi-
ciency improvements can be realized with synchronous
rectification, provided that the MOSFET switch timing is
optimized. An additional benefit realized with synchro-
nous rectifiers is bipolar output current capability. These
characteristics improve transient response, particularly
overshoot, and improve ZVS ability at light loads.
The turn-off delay is programmed with a resistor from
SPRG to GND, see Figure 14. The nominal regulated
voltage on SPRG is 2V. The external resistor programs a
current which flows out of SPRG. The delay can be
adjusted from approximately 20ns to 200ns, with resistor
values of 10k to 200k. Do not leave SPRG floating. The
amount of delay can also be modulated based on an
external current source that sinks current out of SPRG.
Care must be taken to limit the current out of SPRG to
350µA or less.
Programming the Synchronous Rectifier Turn-Off
Delay
The LTC3722-1/LTC3722-2 controllers include a feature
to program the turn-off edge of the secondary side syn-
chronous rectifier MOSFETs relative to the beginning of a
SPRG
+
+
V
–
TURN-OFF
R
SPRG
SYNC OUT
2V
–
3722 F0Y
Figure 14. Synchronous Delay Circuitry
372212i
24
LTC3722-1/LTC3722-2
U
OPERATIO
Current Doubler
capacitors’s reliability. The amount of ripple cancellation
is related to duty cycle (see Figure 15). Although the
currentdoublerrequiresanadditionalinductor, theinduc-
torcorevolumeisproportionaltoLI2, thusthesizepenalty
is small. The transformer construction is simplified with-
out a center-tap winding and the turns ratio is reduced by
1/2comparedtoaconventionalfullwaverectifierconfigu-
ration.
Thecurrentdoublersecondaryemploystwooutputinduc-
tors that equally share the output load current. The trans-
formersecondaryisnotcenter-tapped. Thisconfiguration
provides 2x higher output current capability compared to
similarly sized single output inductor modules, hence the
name. Each output inductor is twice the inductance value
as the equivalent single inductor configuration and the
transformer turns ratio is 1/2 that of a single inductor
secondary. The drive to the inductors is 180 degrees out
of phase which provides partial ripple current cancellation
in the output capacitor(s). Reduced capacitor ripple cur-
rent lowers output voltage ripple and enhances the
Synchronous rectification of the current doubler second-
ary requires two ground referenced N-channel MOSFETs.
The timing of the LTC3722-1/LTC3722-2 drive signals is
shown in the Timing Diagram.
1
NOTE: INDUCTOR(S) DUTY CYCLE
IS LIMITED TO 50% WITH CURRENT
DOUBLER PHASE SHIFT CONTROL.
NORMALIZED
OUTPUT RIPPLE
CURRENT
ATTENUATION
0
0
0.25
0.5
DUTY CYCLE
1922 • F13
Figure 15. Ripple Current Cancellation vs Duty Cycle
372212i
25
LTC3722-1/LTC3722-2
U
OPERATIO
Full-Bridge Gate Drive
does not require the propagation delays of the high and
low side drive circuits to be precisely matched as the
DirectSense ZVS circuitry will adapt accordingly. As a
result, LTC3722-1/LTC3722-2 can drive a simple NPN-
PNP buffer or a gate driver chip like the LTC1693-1 to
provide the low side gate drive. Providing drive to the high
side presents additional challenges since the MOSFET
gate must be driven above the input supply. A simple
circuit (Figure 17) using a single LTC1693-1, an inexpen-
sive signal transformer, and a few discrete components
provides both high side gate drives (A and C) reliably.
The full-bridge converter requires high current MOSFET
gate driver circuitry for two ground referenced switches
and two high side referred switches. Providing drive to the
ground referenced switches is not too difficult as long as
thetracesfromthegatedriverchiporbuffertothegateand
source leads are short and direct. Drive requirements are
further eased since all of the switches turn on with zero
VDS, eliminating the “Miller” effect. Low turn-off resis-
tance is critical, however, in order to prevent excessive
turn-off losses resulting from the same Miller effects that
were not an issue for turn on. The LTC3722-1/LTC3722-2
LTC1693-1
LTC3722
OUT1
IN1
1:2
OUTE
OUTF
GND1
GND2
IN2
OUT2
3722 F14
Figure 16. Isolated Drive Circuitry
V
IN
REGULATED
BIAS
2µF
CER
LTC3722
V
CC
0.1µF
POWER
MOSFET
0.1µF
OUT
1/2
IN
OUTA
OR
OUTC
BAT
54
2k
LTC1693-1
GND
SIGNAL
TRANSFORMER
BRIDGE
LEG
3722 F15
Figure 17. High Side Gate Driver Circuitry
372212i
26
LTC3722-1/LTC3722-2
U
PACKAGE DESCRIPTIO
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.033
(0.838)
REF
24 23 22 21 20 19 18 17 16 15 14 13
.045 ±.005
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.254 MIN
.150 – .165
1
2
3
4
5
6
7
8
9 10 11 12
.0165 ±.0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
(0.38 ± 0.10)
.053 – .068
(1.351 – 1.727)
× 45°
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN24 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
372212i
27
LTC3722-1/LTC3722-2
U
TYPICAL APPLICATIO
240W, 36-72 VIN to 12V/20A Isolated Supply
L5
1.3µH
V
IN
PRELIMINARY SCHEMATIC, UNLESS NOTED:
ALL CAPS 25V, ALL RESISTORS 0603 (1/16W) OR 0805 (1/8W)
+V
IN
D3, D4, D12, D14 BAS21
D6, D7, D15, D17 BAT54
L4 COILCRAFT DO1608C-105
V
10V
IN
0.82µF
3× 0.82µF
10V
L5 SUMIDA CDEP105-1R3MC-50
36V TO
72V
100V
100V
D8, D9 ON-SEMI MMBD914LT1 Q1, Q2, Q7,Q9 ZETEX FMMT619
D3
D4
–V
IN
Q3, Q4, Q8, Q11-Q15 Si7456 DP
Q5, Q6, Q10, Q16-Q18 ZETEX FMMT718
T2, T3 PULSE PE-68386
T4 PULSE PB2001
T5 PULSE PA0297
D16, D20 MMBZ5239B
D21, D22 MURS120T3
D22 MMBZ5251B
L1,L3 PULSE PA0295
L2 PULSE PA0573
T2
T3
785µH
1:1
Q2
Q5
Q1
D21
A
C
1µF
0.01µF
1µF
0.01µF
785µH
1:1
75Ω
75Ω
Q3
Q4
D22
T4
1k
0.1µF
1k
0.1µF
7T(75µH): 6T: 6T
Q6
L1
6.7µH
+V
OUT
12
11
10
V
LOW
D6
D7
6
5
+V
OUT
A_LEG
L2
252nH
L3
6.7µH
P_LEG
V
HIGH
1
2
9
8
7
10V
Q7
+
10V
Q9
220µF
16V
12V
20A
1µF
D
B
Q12,
Q13
Q14,
Q15
4
Q8
Q11
Q10
Q16
–V
OUT
ISNS
680Ω 680Ω
–V
10V
OUT
L4
+
D12
0.04Ω
1.5W
0.04Ω 68µF
1.5W
20V
1mH
D8
D9
D14
T5
Q17
Q18
–V
OUT
A_LEG
V
IN
P_LEG
1mH 1:0.5:0.5
5
7
15.4k
15.4k
13.3k
13.3k
13.3k
13.3k
3
OUT1
LTC1693-1
OUT2
51Ω
1/4W
1.5pF
100V
1.5pF
1
D15
D17
4.7k
1nF
100Ω
100V
ADLY
A
3
1
4
6
8
2
1/4W
+V
IN2
IN1
GND2
V
CC2
OUT
15k
15k
6
4
0.1µF
V
CC1
22Ω
D16
9.1V
GND1
220pF
8
1k
1k
SBUS
PDLY
1k
0.1µF
5
–V
OUT
ISNS 5V
10V
REF
+V
OUT
ADLY
11
C
PDLY
9
B
D
17
200Ω
SBUS
21
19
20
15
OUTF
16
OUTE
470Ω
1
750Ω
1/4W
39Ω
10
4
3
8
ADLY
OUTA
OUTC
PDLY
OUTB OUTD
9.53k
SBUS
7
6
1/4W
1k
2
18
12
V
IN
COMP
0.1µF
10k
LTC3722-1
0.1µF
3
4
V
UVLO
IN
V
REF
DPRG
2
NC
8
SYNC
1
CT
24
SPRG
13
R
GND PGND SS
23 22
FB CS
+
LEB
5
MOC207
R
V
COMP
LT1431
COLL
GNDF GNDS R
TOP
180k
5
2
0.022µF
14
7
6
3
100pF
1
5V
REF
REF
5.1k
10k
30k
2.2nF
250V
27k
D20
10V
MID
7
2.49k
100k
33k
330pF
150pF
0.068µF
1µF
1µF
6
5
–V
OUT
RELATED PARTS
PART NUMBER
LT1681/LT3781
LTC1696
DESCRIPTION
COMMENTS
High Efficiency 2-Switch Forward Control
Synchronous Forward Controller
Overvoltage Protection Controller
ThinSOT Package, Gate Drive for SCR Crowbar or External N-Channel MOSFET
8V-48V, Protected from –15V to 60V Transients, Auto Restart
Adaptive ZVS, Primary Side Control
LT1910
Protected High Side MOSFET Driver
Synchronous Phase Shift Controller
LTC1922-1
372212i
LT/TP 0203 1.5K • PRINTED IN USA
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
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