LTC3725IMSE#PBF_技术文档

LTC3725

Single-Switch Forward

Controller and Gate Driver

U

FEATURES

DESCRIPTIO

The LTC^®3725 is a controller for a single-switch forward

converter and includes an on-chip gate driver.

■

High Speed Gate Driver for Forward Converter

■

On-Chip Rectifier and Self-Starting Architecture

Eliminates Need for Separate Gate Drive Bias

Supply

For secondary-side control, combine the LTC3725 with

the LTC3706 PolyPhase^®secondary-side synchronous

forward controller to create a complete forward converter

using a minimum of discrete parts. A proprietary scheme

is used to multiplex gate drive signals across the isolation

barrier through a tiny pulse transformer. The on-chip

rectifierandthesamepulsetransformerprovidegatedrive

bias power.

■

Wide Input Voltage Supply Range: 9V and Up

■

Linear Regulator Controller for Fast Start-Up

■

Precision UVLO with Adjustable Hysteresis

■

Overcurrent Protection

■

Volt-Second Limit Prevents Transformer Core

Saturation

■

Voltage Feedforward for Fast Transient Response

■

Alternatively, the LTC3725 can be used as a standalone

voltagemodecontrollerinaprimary-sidecontrolarchitec-

ture with optoisolator feedback. Voltage feedforward pro-

vides excellent line regulation and transient response.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

PolyPhase is a registered trademark of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Patent Pending

Available in 10-Lead MSOP Package

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APPLICATIO S

■

Isolated 48V Telecommunication Systems

■

Internet Servers and Routers

■

Distributed Power Step-Down Converters

■

Automotive and Heavy Equipment

U

TYPICAL APPLICATIO

36V-72V to 3.3V/30A Isolated Single-Switch Forward Converter

+

T1

V

IN

36V TO 72V

•

L1

0.85µH

•

+

V

3.3V

30A

OUT

1µF

100V

×2

B0540W

100µF

6.3V

×2

+

220µF

HAT2165

×2

HAT2165

×2

1.2Ω

1/4W

Si7450DP

6.3V

2.2nF

200V

0.030Ω

1W

0.0012Ω

1W

–

10µF

V

IN

–

V

OUT

2.2µF

FCX491A

100k

FDC2512

2.74k

0.1µF

1µF

–

+

NDRV GATE

I

FG SW

I

SG V NDRV

IN

V

MODE

CC

S

+

–

+

–

V

FB/IN

PT

CC

T2

365k

•

5.1k

UVLO

LTC3725

LTC3706

FB

1µF

SSFLT

FS/IN

15k

V

GND PGND RUN/SS SLP REGSD FS/SYNC PHASE

I

TH

SLMT PGND GND

162k

604Ω

33nF

3.3k

47nF

33nF

100k

470pF

L1: PULSE PA1294.910

T1: PULSE PA0815

T2: PULSE PA0297

3725 TA01

3725fa

1

LTC3725

W W

U W

U

W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TOP VIEW

Power Supply (V_CC) ...................................–0.3V to 15V

External NMOS Drive (NDRV) ....................–0.3V to 20V

NDRV to V_CC........................................................... –0.3V to 5V

Soft-Start Fault, Feedback,

UVLO

SSFLT

NDRV

1

2

3

4

5

10

9

I

V

S

SLMT

CC

11

8

+

FB/IN

7

6

GATE

PGND

–

FS/IN

MSE PACKAGE

10-LEAD PLASTIC MSOP

Frequency Set, Transformer

Inputs (SSFLT, FB/IN⁺, FS/IN^–) ..................–0.3V to 15V

All Other Pins (V_SLMT, I_S, UVLO) .................–0.3V to 5V

Peak Output Current <1µs (GATE) ............................. 2A

Operating Ambient Temperature Range.. –40°C to 85°C

Operating Junction Temperature (Note 2) ............ 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

T_JMAX= 125°C, θ_JA= 45°C/W, θ_JC= 10°C/W

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

ORDER PART NUMBER

MSE PART MARKING

LTBSV

LTBSW

LTC3725EMSE

LTC3725IMSE

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 12V, GND = PGND = 0V, T = 25°C, unless otherwise noted.

A

CC

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Supply, Linear Regulator and Trickle Charger Shunt Regulator

CC

Operating Voltage Range

Output Voltage

7

12

8

15

V

CCOP

CCLR

NDRV

r(VCC)

NDRVTO

CC

Linear Regulator in Operation

I

t

I

Current into NDRV Pin

Linear Regulator in Operation

0.1

1

mA

µs

Rise Time of V

Linear Regulator Charging (0.5V to 7.5V)

45

0.27

1.4

CC

Linear Regulator Time Out Current Threshold Primary-Side Operation

mA

Supply Current

V

= 1.5V, Linear Regulator in

2.1

2.5

15

UVLO

Operation (Note 3)

I

Maximum Supply Current

V

= 1.5V, Trickle Charger in Operation,

UVLO

1.7

mA

CCM

= 13.2V (Note 3)

CC

V

Maximum Supply Voltage

Trickle Charger Shunt Regulator

14.25

V

CCSR

I

Minimum Current into NDRV/V

Trickle Charger Shunt Regulator, V = 15V

(Note 3)

10

mA

CCSR

CC

Internal Undervoltage

Internal Undervoltage Threshold

V

Rising

Falling

5.3

4.7

V

CCUV

CC

Gate Drive Undervoltage

Gate Drive Undervoltage Threshold

V

Rising (Linear Regulator)

Rising (Trickle Charger)

Falling

●

7.2

13.1

6.8

7.4

13.4

7.0

7.7

14

7.2

V

GDUV

CC

Undervoltage Lockout (UVLO)

V

Undervoltage Lockout Threshold Rising

Undervoltage Lockout Threshold Falling

Rising

Falling

●

1.220

1.205

1.242

1.226

1.280

1.265

V

UVLOR

UVLOF

3725fa

2

LTC3725

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 12V, GND = PGND = 0V, T = 25°C, unless otherwise noted.

A

CC

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

5.6

UNITS

µA

I

Hysteresis Current

V

= 1V

UVLO

●

4.2

4.9

HUVLO

V

Voltage Feedforward Operating Range

Primary-Side Control

V

3.75

V

UVLOOP

UVLOF(MIN)

Gate Driver (GATE)

R

Output Pull-Down Resistance

High Output Voltage

Peak Pull-Up Current

Output Rise Time

I

= 100mA

1.9

11

Ω

V

OS

OH

OUT

V

= –100mA

I

t

1.7

40

A

PU

10% to 90%, C

= 4.7nF

ns

r

f

OUT

Output Fall Time

70

OUT

Rectifier

I

Maximum Rectifier DC Output Current

Oscillator Frequency

25

mA

RECT

Oscillator

f

Primary-Side Control, R

= 100kΩ

= 25kΩ

= 300kΩ

200

700

70

kHz

OSC(P)

FS(P)

∆f

Oscillator Resistor Set Accuracy

Oscillator Frequency

Primary-Side Control

RFS(P)

25k < R

< 300k

±15

%

FSET

f

Secondary-Side Control (During Start-Up),

= 100kΩ

300

kHz

OSC(S)

R

FS(S)

Soft-Start/Fault (SSFLT)

I

Soft-Start Charge Current

Primary-Side Control, V

Secondary-Side Control, V

= 2V

–5.2

–4

µA

SS(C)

SSFLT

= 1.3V,

UVLO

V

= 2V

SSFLT

Secondary-Side Control, V

= 3.75V,

–1.6

µA

UVLO

V

= 2V

SSFLT

V

Linear Regulator Time Out-Threshold

Fault Output High

3.9

6.7

1

V

LRTO

FLTH

V

= 8V

CC

I

Soft-Start Discharge Current

Timing Out After Fault, V

= 2V

SSFLT

µA

SS(D)

Current Sense Input (I )

S

V

Overcurrent Threshold

300

mV

IS(MAX)

Volt Second Limit (V

)

SLMT

V

Volt-Second Limit Threshold

Maximum Volt-Second Limit Resistor Current

1.26

0.25

V

VSL(MAX)

I

mA

VSLMT(MAX)

Optoisolator Bias Current

V

Open Circuit Optoisolator Voltage

Optoisolator Bias Current

Primary-Side Control I = 0V

3.3

V

OPTO

FB

I

Primary-Side Control V = 2.5V

0.5

1.6

mA

FB

Primary-Side Control V = 0V

FB

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: I is the sum of current into NDRV and V .

CC CC

Note 4: The LTC3725EMSE is guaranteed to meet performance

specifications from 0°C to 85°C. Specifications over the –40°C to 85°C

operating temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3725IMSE is

guaranteed and tested over the – 40°C to 85°C operating temperature

range.

Note 2: Operating junction temperature T (in °C) is calculated from the

J

ambient temperature T and the average power dissipation PD (in watts)

A

by the formula: T = T + θ • PD. Refer to the Applications Information

J

A

JA

section for details.

3725fa

3

LTC3725

U W

TYPICAL PERFOR A CE CHARACTERISTICS

UVLO Voltage Threshold vs

Temperature

UVLO Hysteresis Current vs

Temperature

Supply Current vs V

CC

2.0

1.5

1.0

0.5

0

1.245

1.240

1.235

1.230

1.225

1.220

5.05

5.00

4.95

4.90

4.85

4.80

TRICKLE CHARGER

V

UVLOR

LINEAR REGULATOR

V

UVLOF

5

–40 –20

0

20

–40 –20

0

20

0

15

–60

100

–60

100

10

40 60 80

V

(V)

TEMPERATURE (°C)

CC

3725 G01

3725 G02

3725 G03

Shunt Regulator Current I

Oscillator Frequency

vs R

Oscillator Frequency vs

Temperature

CC

vs V

f

CC

OSC

FSET

203

202

201

200

199

198

197

18

15

12

9

800

700

600

500

400

300

200

100

0

PRIMARY-SIDE CONTROL

FS(P)

R

= 100kΩ

SECONDARY-SIDE CONTROL

6

3

PRIMARY-SIDE CONTROL

100 200

(kΩ)

0

–40 –20

0

20

–60

100

14.00

14.25

14.50

(V)

14.75

15.00

40 60 80

0

300

400

TEMPERATURE (°C)

V

R

CC

FSET

3725 G05

3725 G06

3725 G04

Shunt Regulator Current vs

Temperature

Optoisolator Bias V

FB/IN

+ vs

FB/IN

I

+

V

GDUV

vs Temperature

25

14

13

12

11

10

9

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

24

23

22

21

20

19

18

17

16

15

V

RISING (TRICKLE CHARGER)

CC

8

V

RISING (LINEAR REGULATOR)

CC

7

V

FALLING (BOTH)

CC

6

–40 –20

0

20

–40 –20

0

20

–60

100

–60

100

0

0.5

1.0

+ (mA)

1.5

2.0

40 60 80

TEMPERATURE (°C)

–I

FB/IN

3725 G07

3725 G08

3725 G09

3725fa

4

LTC3725

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Gate Drive Pull-Down Resistance

vs Temperature

Gate Drive Peak Pull-Up Current

vs Temperature

2.0

1.9

1.8

1.7

1.6

1.5

2.50

2.25

2.00

1.75

1.50

–40 –20

0

20

–60

100

–40 –20

0

20

40 60 80

–60

100

40 60 80

TEMPERATURE (°C)

3725 G11

3725 G10

Linear Regulator Start-Up

Gate Drive Encoding

Fault Operation

V

IN

GATE

10V/DIV

2V/DIV

GATE

FB/IN

SSFLT

5V/DIV

10V/DIV

NDRV

–

FS/IN

V

CC

3725 G12

3725 G14

3705 G13

25µs/DIV

40ms/DIV

1µs/DIV

3725fa

5

LTC3725

U

PI FU CTIO S

UVLO (Pin 1): Undervoltage Lockout. Connect to a resis-

tive voltage divider to monitor input voltage V_IN. Enables

converter operation for V_UVLO> 1.242V. Hysteresis is a

fixed 16mV hysteresis voltage with a 4.9µA hysteresis

current that combines with the Thevenin resistance of the

divider to set the total UVLO hysteresis voltage. This input

also senses V_INfor voltage feedforward. Finally, this pin

can be used for external run/stop control.

Forprimary-sidecontrolconnectthispintoanoptoisolator

for feedback control of converter output voltage using an

internal optoisolator biasing network.

FS/IN^–(Pin 5): This pin has several functions. Place a

resistor from this pin to GND to set the oscillator fre-

quency. For secondary-side control with the LTC3706,

connect one winding of the pulse transformer for opera-

tion as described for the FB/IN⁺pin above.

SSFLT (Pin 2): Combination Soft-Start and Fault Indica-

tor. A capacitor to GND sets the duty cycle ramp-up rate

during start-up. To indicate a fault, the SSFLT pin is

momentarily pulled up to within 1.3V of V_CC.

PGND (Pin 6): Supply Return for the Bottom Gate Driver

and the On-Chip Bridge Rectifier.

GATE (Pin 7): Gate Drive. Connect to the gate of the

external MOSFET.

NDRV (Pin 3): Drive for the External NMOS Linear Regu-

lator. Connect to the gate of the NMOS and connect a pull

up resistor to the input voltage (V_IN). Optionally, to create

atricklechargeromittheNMOSdeviceandconnectNDRV

to V_CC.

FB/IN⁺(Pin 4): This pin has several functions. One wind-

ing of a pulse transformer is connected to the FB/IN⁺and

FS/IN^–pins. The other pulse transformer winding is con-

nected to the LTC3706. The LTC3725 automatically de-

tects when the LTC3706 applies a pulse-encoded signal to

the FB/IN⁺and FS/IN^–pins and decodes duty cycle infor-

mation for control of the primary-side gate drive (see

Operation below). In secondary-side control, primary-

sidegatedrivebiaspowerisalsoextractedfromtheFB/IN⁺

and FS/IN^–pins using an on-chip full-wave rectifier.

V_CC(Pin 8): Main V_CCPower for All Driver and Control

Circuitry.

V_SLMT(Pin 9): Volt-Second Limit. Form an R-C integrator

by connecting a resistor from V_INto V_SLMTand a capacitor

from V_SLMTto ground. The gate drive is turned off when

the voltage on the V_SLMTpin exceeds 1.26V.

I_S(Pin 10): Input to the Overcurrent Comparator. Connect

to the positive terminal of a current-sense resistor in

series with the source of the ground-referenced bottom

MOSFET.

GND (Pin 11): Signal Ground.

3725fa

6

LTC3725

W

BLOCK DIAGRA

+

8V

NDRV

3

SHUNT REGULATOR

V

CC

–

0.6V

7.4V/7V

LINEAR

REGULATOR

5V

+

–

+

–

+

UVGD

REGULATOR

13.4V/7V

TRICKLE

CHARGE

14.25V

I

CHARGER

NDRV

5.3V/4.7V

+

–

0.27mA

LINE OFF

TIME

UVINT

+

–

V

SOFT-START

FAULT

+

IS

10

2

1

SSFLT

OC

–

300mV

1.242V

1.226V

+

–

UVVIN

UVLO

V

FF

0.66

4.9µA

SW

DET

PWM SECONDARY CONTROL

5V

GND 11

(PAD)

PWM

RECEIVER

DRIVE

LOGIC

+

IN

SW

–

CONDITION

DET

+

–

PWM

PRIMARY

CONTROL

–

PRIMARY

1.26V

9

400mV

SIDE CONTROL

+

N/C

V

SLMT

2V

FREQUENCY

SET

SWITCH

ON

RAMP

V

P-P

0V

V

I

P-P

OSCILLATOR

CLOCK

OPTO

BIAS

OSC

SECONDARY SIDE CONTROL

3.3V

V

CC

+

V

8

7

6

4

5

FB/IN

FS/IN

CC

GATE

RECTIFIER

PGND

–

PGND

3725 BD

3725fa

7

LTC3725

U

OPERATIO

Mode Setting

endofthe“on”time.Althoughthisschemeallowsthetrans-

mission of 0% to 75% duty cycle, it is necessary to estab-

lish a minimum controllable “on” time of approximately

100ns. Thisensuresthat0%dutycyclecanbereliablydis-

tinguished from 75% duty cycle.

The LTC3725 is a controller and gate driver designed

for use in a single-switch forward converter. When used

in conjunction with the LTC3706 PolyPhase secondary-

sidesynchronousforwardcontroller, itformsacomplete

forward converter with secondary-side regulation, gal-

vanic isolation between input and output, and synchro-

nous rectification. In this mode, upon start-up, the FB/

IN⁺andFS/IN^–pinsareeffectivelyshortedbyonewinding

of the pulse transformer. The LTC3725 detects this short

circuit to determine that it is in secondary-side control

mode. Operation in this mode is confirmed when the

LTC3706 begins switching the pulse transformer.

On-Chip Rectifier

Simultaneously with duty-cycle decoding, and through

the same pulse transformer, the wave generated by the

LTC3706 provides primary-side V_CCgate drive bias power

bywayoftheLTC3725’son-chipfull-wavebridgerectifier.

No auxiliary bias supply is necessary and forward con-

verter design and circuitry are considerably simplified.

Alternately, the LTC3725 can be used as a standalone

primary-sidecontroller.Inthiscase,theFB/IN⁺andFS/IN^–

pinsoperateindependently.TheFB/IN⁺pinisconnectedto

thecollectorofanoptoisolatortoprovidefeedbackandthe

FS/IN^–pin is connected to the frequency set resistor.

External Series Pass Linear Regulator

The LTC3725 features an external series pass linear regu-

lator that eliminates the long start-up time associated with

the conventional trickle charger. The drain of an external

NMOS is connected to the input voltage and the source is

connected to V_CC. The gate of the NMOS is connected to

NDRV. To power the gate, an external pull-up resistor is

connected from the input voltage to NDRV. The NMOS

must be a standard 3V threshold type (i.e. not logic level).

An on-chip circuit manages the start up and operation of

the linear regulator. It takes approximately 45µs for the

linear regulator to charge V_CCto its target value of 8V

(unless limited by a slower rise of V_IN). The LTC3725

begins operating the gate drives when V_CCreaches 7.4V.

Often, the thermal rating of the NMOS prevents it from

operating continuously, and the LTC3725 “times out” the

linear regulator to prevent overheating. This is accom-

plished using the capacitor connected to the SSFLT pin as

described subsequently.

Gate Drive Encoding

In secondary-side control with the LTC3706, after a start-

up sequence, the LTC3706 transmits multiplexed PWM

information through a pulse transformer to the FB/IN⁺and

FS/IN^–inputs of the LTC3725. In the LTC3725, the PWM

receiver extracts the duty cycle and uses it to control the

gate driver.

Figure 1 shows that the LTC3706 drives the pulse trans-

former in a complementary fashion, with a duty cycle of

approximately75%.Attheappropriatetimeduringtheposi-

tive half cycle, the LTC3706 applies a short (150ns) zero-

voltage pulse across the pulse transformer, indicating the

DUTY CYCLE = 15%

DUTY CYCLE = 0%

150ns

Trickle Charger Shunt Regulator

+7V

Alternately, a trickle charger can be implemented by

eliminating the external NMOS and connecting NDRV to

V_CCand using the pull-up resistor to charge V_CC. To allow

extra headroom for starting, the LTC3725 detects this

mode and increases the threshold for starting the gate

drives to 13.4V. An internal shunt regulator limits the

voltage on the trickle charger to 15V.

+

–

V

PT1

– V

PT1

–7V

1 CLK PER

3725 F01

Figure 1. Gate Drive Multiplexing Scheme

3725fa

8

LTC3725

U

OPERATIO

Self-Starting Architecture

TheSSFLTpinisalsousedtoindicateafault.TheLTC3725

recognizes faults from four origins: 1) an overcurrent fault

caused by the current sense voltage on the IS pin exceed-

ing the 300mV overcurrent threshold, 2) an input

undervoltage fault caused by the UVLO pin falling below

the 1.226V falling threshold, 3) a gate drive undervoltage

fault caused by the voltage on the V_CCpin falling below the

7V threshold, or 4) loss of the gate drive encoding signal

from the LTC3706.

The LTC3725 is combined with the LTC3706 to form a

complete self-starting DC isolated power supply. When

power is first applied, and when V_CCfor the LTC3725 is

above the appropriate threshold, the LTC3725 begins

open-loop operation using its own internal oscillator.

Power is supplied to the secondary by switching the gate

driver with a gradually increasing duty cycle as controlled

by the rate of rise of the voltage on the SSFLT pin. A peak

detector power supply for the LTC3706 allows it to begin

operation even for small duty cycles. Once adequate

voltage is available for the LTC3706, it provides duty cycle

information and gate drive bias power using the pulse

transformer as shown in Figure 1. The LTC3725 detects

the appearance of this signal and transfers control of the

gatedriverstotheLTC3706.Simultaneously,theLTC3725

also enables the on-chip rectifier and turns off the linear

regulator.

Upon sensing a fault, the LTC3725 immediately turns off

the gate drive and indicates a fault by quickly pulling the

voltage on the SSFLT pin to within 1.3V of the voltage on

the V_CCpin. After indicating the fault, the LTC3725 quickly

ramps down the voltage on the SSFLT pin to approxi-

mately 2.8V. Then, to allow complete discharge of the

secondary-side circuit, the LTC3725 slowly ramps down

thevoltageontheSSFLTpintoabout200mV.TheLTC3725

then attempts a restart.

Alternately, when the LTC3725 is used as a standalone

primary-sidecontroller,thegraduallyincreasingdutycycle

powersupasecondary-sidereferenceandoptoisolatorand

feedback is accomplished when the output of the

optoisolator begins pulling down in the FB/IN⁺pin.

Linear Regulator Timeout

The thermal rating of the linear regulator’s external NMOS

often cannot allow it to indefinitely supply bias current to

the primary-side gate drives. The LTC3725 has a linear

regulator timeout mechanism that also uses the SSFLT

capacitor.

Soft-Start and Fault

These two functions are implemented using the SSFLT

pin. (This pin is also used for linear regulator timeout as

described in the following section.)

Asdescribedinthepriorsection,soft-startisoveroncethe

voltage on the SSFLT pin reaches 2.8V. However, the

SSFLT capacitor continues to charge and the linear regu-

lator is turned off when the voltage on the SSFLT pin

reaches 3.9V. The “Applications Information” section de-

scribes linear regulator timeout in more detail.

Initiating soft-start requires that: 1) the gate drive

undervoltage (UVGD) goes low meaning that adequate

voltage is available on the V_CCpin (7.4V for the linear

regulator or 13.4V for the trickle charger) and 2) the input

undervoltage (UVV_IN) goes low meaning that the voltage

on the UVLO pin has reached the 1.242V rising threshold.

Volt-Second Limit

The volt-second limit ensures that the power transformer

core does not saturate for any combination of duty cycle

and input voltage. The input of an R-C integrator is

connected to V_INand its output is connected to the V_SLMT

pin. While the gate drive is “off,” the LTC3725 grounds the

V_SLMTpin. When the gate drive is turned “on” the V_SLMT

pin is released and the capacitor is allowed to charge in

proportion to V_IN. If the capacitor voltage on the V_SLMTpin

Duringsoft-start, theLTC3725graduallychargesthesoft-

start capacitor to ramp up the converter duty cycle. Soft-

startisoverwhenthevoltageontheSSFLTpinreaches2.8V.

Innormaloperation,atsomepointbeforethis,theLTC3725

makes a transition to controlling duty cycle using closed-

loop regulation of the converter output voltage.

3725fa

9

LTC3725

U

OPERATIO

exceeds 1.26V the gate drive is immediately turned “off.”

Note that this is not considered a fault condition and the

LTC3725 can run indefinitely with the switch duty cycle

beingdeterminedbythevolt-secondlimitcircuit. Theduty

cycle is always limited to 75% to ensure that the power

transformer flux always has time to reset before the start

of the next cycle.

anamplitudeof2V.Toimplementvoltagefeedforward,the

charging current for the soft-start capacitor is reduced in

proportion to the input voltage. As a result, the initial rate

of rise of the converter output voltage is held approxi-

mately constant regardless of the input voltage. At some

point during start-up, the LTC3706 begins to switch the

pulse transformer and take over the soft-start.

In an alternate application, the volt-second limit can be

usedforopen-loopregulationoftheoutputagainstchanges

in V_IN.

For operation with standalone primary-side control and

optoisolator feedback, voltage feedforward is used during

both start-up and normal operation. The duty cycle is

determined by using a 75% duty cycle triangle wave with

an amplitude equal to 66% of the voltage on the UVLO pin

which is, in turn, proportional to V_IN. The charging current

for the soft-start capacitor is a constant 5.2µA. During

soft-start, the duty cycle is determined by comparing the

voltage on the SSFLT pin to the triangle wave. Soft-start is

concluded when the voltage on the SSFLT pin exceeds the

voltage on the FB/IN⁺pin. After the conclusion of soft-

start, the duty cycle is determined by comparison of the

voltage on the FB/IN⁺pin to the triangle wave.

Current Limit

CurrentlimitfortheLTC3725isprincipallyasafetyfeature

to protect the converter and is not part of a control

function. The current that flows in series through the

transformerprimaryandtheswitchissensedbyaresistor

connected between the source of the switch and GND. If

the voltage across this resistor exceeds 300mV, the

LTC3725 initiates a fault.

Voltage Feedforward

Optoisolator Bias

The LTC3725 uses voltage feedforward to properly modu-

late the duty cycle as a function of the input voltage. For

secondary-side control with the LTC3706, voltage

feedforward is used during start-up only. The duty cycle

duringstartupisdeterminedbycomparisonofthevoltage

on the SSFLT pin to a 75% duty cycle triangle wave with

When the LTC3725 is used in standalone primary-side

mode, feedback is provided by an optoisolator connected

to the FB/IN⁺pin. The LTC3725 has a built optoisolator

bias circuit which eliminates the need for external

components.

3725fa

10

LTC3725

U

W

U U

APPLICATIO S I FOR ATIO

UVLO

Note that a trickle charger usually requires a large capaci-

tor to provide holdup for the V_CCpin while the converter

attempts to start. The linear regulator in the LTC3725 can

both charge the capacitor connected to the V_CCpin and

provide primary-side gate-drive bias current. Therefore,

with the linear regulator, the capacitor need only be large

enoughtocopewiththeripplecurrentfromdrivingthegate

of the primary FET and holdup need not be considered.

The UVLO pin is connected to a resistive voltage divider

connected to V_INas shown in Figure 2. The voltage

threshold on the UVLO pin for V_INrising is 1.242V. To

introduce hysteresis, the LTC3725 draws 4.9µA from the

UVLO pin when V_INis rising. The hysteresis is therefore

useradjustableanddependsonthevalueofR1. TheUVLO

threshold for V_INrising is:

The external NMOS for the linear regulator should be a

standard 3V threshold type (i.e. not a logic level thresh-

old). The rate of charge of V_CCfrom 0V to 8V is controlled

by the LTC3725 to be approximately 45µs regardless of

the size of the capacitor connected to the V_CCpin. The

charging current for this capacitor is approximately:

R1+ R2

V

= (1.242V)

+ R1(4.9µA)

IN(UVLO,RISING)

R2

The LTC3725 also has 16mV of voltage hysteresis on the

UVLO pin so that the UVLO threshold for V_INfalling is:

R1+ R2

V

= (1.226V)

IN(UVLO,FALLING)

R2

8V

45µs

I_C=

C

To implement external Run/Stop control, connect a small

NMOS to the UVLO pin as shown in Figure 2. Turning the

NMOSongroundstheUVLOpinandpreventstheLTC3725

from running.

The safe operating area (SOA) for the external NMOS

should be chosen so that capacitor charging does not

damage the NMOS. Excessive values of capacitor are

unnecessary and should be avoided.

V

IN

Start-Up Considerations

R1

R2

When used in a self-starting converter with the LTC3706,

the LTC3725 initially begins the soft-start of the converter

in an open-loop fashion. After bias is obtained on the

secondary side, the LTC3706 assumes control and com-

pletesthesoft-startinterval.Inordertoensurethatcontrol

is properly transferred from the LTC3725 (primary-side)

to the LTC3706 (secondary-side), it is necessary to limit

the rate of rise on the primary-side soft-start ramp so that

the LTC3706 has adequate time to wake up and assume

control before the output voltage gets too high. This

conditionissatisfiedformanyapplicationsifthefollowing

relationship is maintained:

UVLO

RUN/STOP

CONTROL

(OPTIONAL)

LTC3725

GND

3725 F02

Figure 2. Resistive Voltage Divider for

UVLO and Optional Run/Stop Control

Linear Regulator

The linear regulator eliminates the long start-up times

associated with a conventional trickle charger by using an

external NMOS to quickly charge the capacitor connected

to the V_CCpin.

C_SS,SEC≤ C_{SS_PRI}

3725fa

11

LTC3725

W U U

U

APPLICATIO S I FOR ATIO

However, care should be taken to ensure that soft-start

transfer from primary-side to secondary-side is com-

pleted well before the output voltage reaches its target

value.Agooddesigngoalistohavethetransfercompleted

when the output voltage is less than one-half of its target

value. Note that the fastest output voltage rise time during

primary-side soft-start mode occurs with minimum load

current.

LTC3725, the linear regulator times out resulting in a gate

driveundervoltagefault,or2)theprimary-sideovercurrent

circuit is tripped because of current buildup in the output

inductor. In either case, the LTC3725 initiates a shutdown

followed by a soft-start retry.

Linear Regulator Timeout

After start-up, the LTC3725 times out the linear regulator

to prevent overheating of the external NMOS. The timeout

interval is set by further charging the soft-start capacitor

The open-loop start-up frequency on the LTC3725 is set

by placing a resistor R_FS(S)from the FS/IN^–pin to GND.

Although the exact start-up frequency on the primary side

is not critical, it is generally a good practice to set it

approximately equal to the operating frequency on the

secondary side.

C

_SSFLTfromtheend-of-soft-startvoltageofapproximately

2.8V to the timeout threshold of 3.9V. Linear regulator

timeout behaves differently depending on mode.

In primary-side standalone mode, the LTC3725 generally

requires that an auxiliary gate drive bias supply take over

from the linear regulator. (See the subsequent section for

more detail on the auxiliary supply.) During linear regula-

tor timeout, the rate of rise of the soft-start capacitor

voltage depends on the current into the NDRV pin as

controlled by the pull-up resistor R_PULLUP, the value of V_IN

In this mode the start-up frequency of the LTC3725 is

approximately:

34 •10⁹

R_FS(S)+ 10,000

f_PRI

=

and the value of V_NDRV

.

In the event that the LTC3706 fails to start up properly and

assume control of switching, there are several fail-safe

mechanisms to help avoid overvoltage conditions. First,

theLTC3725implementsavolt-secondclampthatmaybe

used to keep the primary-side duty cycle at a level that

does not produce an excessive output voltage. Second,

thetimeoutofthelinearregulator(describedinthefollow-

ing section) means that, unless the LTC3706 starts and

supports the LTC3725 gate drive through the pulse trans-

former and on-chip rectifier, the LTC3725 eventually suf-

fers a gate drive undervoltage fault. Finally, the LTC3706

has an independent overvoltage detection circuit that

crowbars the output of the DC/DC converter using the

synchronous secondary-side MOSFET switch.

V – V_NDRV

R_PULLUP

IN

I_NDRV

=

The value of V_NDRVis V_CC= 8V plus the value of the gate-

to-source voltage (V_NDRV– V_CC) of the external NMOS in

the linear regulator. The gate-to-source voltage depends

on the actual device but is approximately the threshold

voltage of the external NMOS.

For I_NDRV> 0.27mA, the capacitor on the SSFLT pin is

charged in proportion to (I_NDRV– 0.27mA) until the linear

regulator times out. Thus, since V_NDRVis very nearly

constant, the timeout interval for the linear regulator is

inversely proportional to the input voltage and a higher

input voltage produces a shorter timeout.

In the event that a short-circuit is applied to the output of

the converter prior to start-up, the LTC3706 generally

does not receive enough bias voltage to operate. In this

case,theLTC3725detectsaFAULTforoneoftworeasons:

1) since the LTC3706 never sends pulse encoding to the

66C_SSFLT(3.9V – 2.8V)

t_TIMEOUT

=

⎡V − V_NDRV

⎤

IN

– 0.27mA

⎢

⎥

⎦

R_PULLUP

⎣

3725fa

12

LTC3725

W U U

APPLICATIO S I FOR ATIO

U

Since the power dissipation of the linear regulator is

proportional to the input voltage, this strategy of making

the timeout inversely proportional to the input voltage

produces an approximately constant temperature excur-

sion for the external NMOS of the linear regulator regard-

less of the input voltage.

Fault Lockout

The LTC3725 indicates a fault by pulling the SSFLT pin to

within 1V of V_CC. The LTC3725 subsequently attempts a

restart. Optionally, the user can prevent restart and “lock

out” the converter by clamping the voltage on the SSFLT

pin with a 4.3V zener diode. Once the converter has locked

out it can only be restarted by the removal of the input

voltage or by release of the zener diode clamp.

In situations for which the continuous operation of the

linear regulator does not exceed the thermal limitations of

the external NMOS (i.e. converters with low V_INor with

minimal gate drive bias requirements), the auxiliary sup-

ply can be omitted and the linear regulator allowed to

operate continuously. If I_NDRVis less than 0.27mA the

linear regulator never times out and the voltage on the

SSFLT pin stays at approximately 2.8V after start-up is

completed. To accomplish this set:

Pulse Transformer

The pulse transformer that connects the LTC3706 to the

LTC3725 performs the dual functions of gate drive duty

cycleencodingandgatedrivebiassupplyfortheLTC3725

bywayoftheon-chipfull-waverectifier.Thedesignsofthe

LTC3725 and LTC3706 have been coordinated so that the

transformer turn ratio is:

V

_IN(MAX)– V_NDRV

R_PULLUP

>

0.27mA

N_LTC3725= 2N_LTC3706

where V_IN(MAX)is the maximum expected continuous

input voltage. Note that once the linear regulator is turned

off it locks out. Therefore when using this strategy, care

should be taken to ensure that a transient higher than

where N_LTC3725is the number of turns in the winding

connected to the FB/IN⁺and FS/IN^–pins of the LTC3725

and N_LTC3706is the number of turns in the winding

connected to the PT⁺and PT^–pins of the LTC3706. The

winding connected to the LTC3706 must be able to with-

stand volt-seconds equal to:

V

_IN(MAX)does not persist longer than t_TIMEOUT.

In secondary-side operation with the LTC3706, there is

never any need for continuous operation of the linear

regulator since gate drive bias power is provided by the

LTC3706 through the pulse transformer and on-chip

rectifier. The LTC3725 shuts down the linear regulator

once the LTC3706 begins switching the pulse trans-

former. If the LTC3706 fails to start, the LTC3725 quickly

times out the linear regulator once the voltage on the

SSFLT pin reaches 2.8V.

V_CC

2f

(V – s)_MAX

=

whereV_CCisthemaximumsupplyvoltagefortheLTC3706

and f is the operating frequency of the LTC3706.

3725fa

13

LTC3725

W U U

U

APPLICATIO S I FOR ATIO

former from their corresponding LTC3706. To synchro-

nize operation, the SSFLT and V_CCpins of the master are

connected to the corresponding pins of all the slaves. The

master is designated by connection of the frequency set

resistortotheFS/IN^–pinwhilethisresistorisomittedfrom

the slaves. For the slaves the NDRV pin is connected to the

Auxiliary Supply

When used with the LTC3706, the LTC3725 does not

require an auxiliary supply to provide primary-side gate-

drive bias current. After start-up, primary-side gate drive

current is provided by the LTC3706 through a small pulse

transformer and the LTC3725’s on-chip rectifier.

V

_CCpin. See the following section on PolyPhase Applica-

However, when used as a standalone primary-side con-

troller,theLTC3725mayrequireaconventionalgate-drive

bias supply as shown in Figure 3. The bias supply must be

designed to keep the voltage on the V_CCpin between the

absolutemaximumof15Vandthegate-driveundervoltage

lockout of 7V.

tions for more detail.

PolyPhase Applications

Figure4showsthebasicconnectionsforusingtheLTC3725

andLTC3706inPolyPhaseapplications.Oneofthephases

is always identified as the “master,” while all other phases

are “slaves.” For the LTC3725 (primary side), the master

performs the open-loop start-up and supplies the initial

V_CCvoltage for the master and all slaves. The LTC3725

slaves are put into that mode by omitting the resistor on

FS/IN–. The LTC3725 slaves simply stand by and wait for

PWM signals from their respective pulse transformers.

Since the SSFLT pins of master and slave LTC3725s are

interconnected, a FAULT (overcurrent, etc.) on any one of

the phases will perform a shutdown/restart on all phases

together.

The auxiliary supply is connected in parallel with V_CC. The

linear regulator maintains V_CCat 8V. If the auxiliary supply

produces more than 8V, it turns off the external NMOS

beforetheLTC3725cantimeoutthelinearregulator. Ifthe

auxiliarysupplyproduceslessthan8V,thelinearregulator

times out and then the voltage on the V_CCpin declines to

the voltage produced by the auxiliary supply.

Slave Mode Operation

When the LTC3725 is paired with the LTC3706, multiple

pairs can be used to form a PolyPhase converter. In

PolyPhaseoperation,oneLTC3725becomesthe“master”

while the remainder become “slaves.” The master con-

trols start-up in the same manner as for the single-phase

converter, while the slaves do not begin switching until

receivingPWMinformationthroughtheirownpulsetrans-

For the LTC3706, the master performs soft-start and

voltage-loop regulation by driving all slaves to the same

current as the master using the I_THpins. Faults and

shutdowns are communicated via the interconnection of

the RUN/SS pins. The LTC3706 is put into slave mode by

tying the FB pin to V_CC.

V

IN

POWER

TRANSFORMER

PRIMARY

SECONDARY

NDRV

LTC3725

WINDING N

BAS21

WINDING N

P

S

1mH

V

CC

AUXILIARY

WINDING N

2.2µF

BAS21

A

GND

3725 F03

Figure. 3. Auxiliary Supply for Primary-Side Control

3725fa

14

LTC3725

W U U

APPLICATIO S I FOR ATIO

U

+

V

IN

OUT

V

BIAS

V

NDRV V

CC

IN

+

NDRV

FS/SYNC

+

–

UVLO FB/IN

PT

•

V

FB

CC

–

ITH

FS/IN

PT

SS/FLT

RUN/SS

LTC3706

(MASTER)

LTC3725

(MASTER)

–

V

IN

V

NDRV V

CC

IN

RUN/SS FS/SYNC

NDRV

+

–

SS/FLT FB/IN

+

–

FB

ITH

PT

•

V

CC

UVLO FS/IN

PHASE

LTC3725

(SLAVE)

LTC3706

(SLAVE)

3725 F04

Figure 4. Connections for PolyPhase

Standalone Primary-Side Operation

Grounding Considerations

The LTC3725 can be used to implement a standalone

forward converter using optoisolator feedback and a

secondary-sidevoltagereference.AlternatelytheLTC3725

can be used to implement an open-loop forward converter

using the V_SLMTpin to regulate against changes in V_IN. In

either case, the LTC3725 oscillator determines the fre-

quency as found from:

The LT3725 is typically used in high current converter

designs that involve substantial switching transients. Fig-

ure 5 illustrates these currents. The switch driver on the IC

is designed to drive a large capacitance and, as such,

generate significant transient currents. Careful consider-

ation must be made regarding input and local power

supply bypassing to avoid corrupting the ground refer-

ences used by the UVLO and frequency set circuitry.

21•10⁹

R_FS(P)+ 4200

Typically, high current paths and transients from the input

supply and any local drive supplies must be kept isolated

from GND. By virtue of the topologies used in LT3725

applications, the large currents from the primary switch,

as well as the switch drive transients, pass through the

sense resistor to ground. This defines the ground connec-

tion of the sense resistor as the reference point for both

GND and PGND.

f_OSC

=

Note that polyphase operation is not possible in the stand-

alone configuration.

3725fa

15

LTC3725

W U U

U

APPLICATIO S I FOR ATIO

Effective grounding can be achieved by considering the

return current paths from the sense resistor to each

respectivebypasscapacitor.Don’tbetemptedtorunsmall

traces to separate the grounds. A power ground plane is

important as always in high power converters, but care

must be taken to keep high current paths away from the

GND reference. An effective approach is to use a 2-layer

ground plane, reserving an entire layer for GND and an

entire layer for PGND. The UVLO and frequency set

resistors can then be directly connected to the GND plane.

V

IN

V

CC

IN

LTC3725

V

UVLO

CC

–

FS/IN

GATE

GND

PGND

POWER GROUND PLANE

3725 F05

SIGNAL GROUND PLANE

Figure 5. High Current Transient Return Paths

3725fa

16

LTC3725

U

TYPICAL APPLICATIO S

E F F I C I E N C Y ( % )

3725fa

17

LTC3725

U

TYPICAL APPLICATIO S

T1

EFD25

+

V

IN

1

2

3

MURHB860CT

10µF

25V

+

12V

–

V

OUT

10µF

25V

10µF

25V

12

•

100pF

1kV

+

L1

V

27µF

IN

1.5mH

100V

+

•

48V

1.5A

10

9

4

5

6

110Ω

0.5W

27µF

100V

1.5µF

63V

FILM

•

L2

100µH

L3

100µH

Si7370DP

7

–

×2

V

OUT

1nF

100V

–V

S

100Ω

2.4k 2.4k

0.25W 0.25W

0.010Ω

1.5W

1nF

1k

MOC207

10nF

45.3k

1k

10nF

100V

MMBD914

1k

3

7

10

1

2

NDRV GATE

I

S

FB/IN

8

1

2

4

6

+

V

CC

47nF

115k

15k

+

470pF

V

UVLO

LTC3725

LT1431

COLL REF

5

1

8

–

SSFLT

FS/IN

VSLMT PGND GND

11

33nF

2.2nF

250V AC

1µF

9.1V

2.49k

GND-F GND-S

9

6

105k

470pF

6

5

10µF, 25V TDK C3225X7R1E106M (1210)

27µF, 100V SANYO MV-AX

–V

S

1.5µF, 63V FILM WIMA MKS2

2.2nF, 250V AC MURATA GA343QR7GD222KW01L

L1: PULSE PE-53911

L2, L3: TDK SLF12575T-101M1R9

T1: PULSE PA0700 3T(16µH):11:11

Figure 7. 12V to 48V/1.5A Isolated Forward Converter Using Optoisolator

IN

3725fa

18

LTC3725

U

PACKAGE DESCRIPTIO

MSE Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1663)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.06 ± 0.102

(.081 ± .004)

1.83 ± 0.102

(.072 ± .004)

2.794 ± 0.102

(.110 ± .004)

0.889 ± 0.127

(.035 ± .005)

1

5.23

(.206)

MIN

2.083 ± 0.102 3.20 – 3.45

(.082 ± .004) (.126 – .136)

10

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ± .0015)

TYP

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.497 ± 0.076

(.0196 ± .003)

REF

10 9

8

7 6

RECOMMENDED SOLDER PAD LAYOUT

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

1

2

3

4 5

GAUGE PLANE

0.53 ± 0.152

(.021 ± .006)

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.127 ± 0.076

(.005 ± .003)

MSOP (MSE) 0603

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

3725fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC3725

RELATED PARTS

PART NUMBER

LTC1693

DESCRIPTION

COMMENTS

High Speed Single/Dual N-Channel MOSFET Drivers CMOS Compatible Input, V Range: 4.5V to 12V

CC

LTC1698

Secondary Synchronous Rectifier Controller

Use with the LT1681, Optocoupler Driver, Pulse Transformer

Synchronization

LT1950

Single Switch Controller

Used for 20W to 500W Forward Converters

LTC3705

LTC3706

2-Switch Forward Controller and Gate Driver

2-Switch Version of LTC3725

Polyphase Secondary-Side Synchronous

Forward Controller

Fast Transient Response, Self-Starting Architecture, Current Mode Control

LT3710

LTC3726

LT3781

Secondary-Side Synchronous Post Regulator

Secondary-Side Synchronous Forward Controller

For Regulated Auxiliary Output in Isolated DC/DC Converters

Similar to the LTC3706

“Bootstrap” Start Dual Transistor Synchronous

Forward Controller

72V Operation, Synchronous Switch Output

LT3804

Secondary Side Dual Output Controller

with Opto Driver

Regulates Two Secondary Outputs, Optocoupler Feedback Driver

and Second Output Synchronous Driver Controller

LTC3901

Secondary-Side Synchronous Driver for

Push-Pull and Full-Bridge Converter

Similar Function to LTC3900, Used in Full-Bridge and Push-Pull Converter

3725fa

LT 1006 REV A • PRINTED IN USA

20 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3725IMSE#PBF
厂家：	Linear
描述：	LTC3725 - Single-Switch Forward Controller and Gate Driver; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C 栅开关光电二极管
文件：	总20页 (文件大小：249K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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