LTC3728LCGN [Linear]
Dual, 550kHz, 2-Phase Synchronous Regulators; 双通道, 550kHz的, 2相同步稳压器型号: | LTC3728LCGN |
厂家: | Linear |
描述: | Dual, 550kHz, 2-Phase Synchronous Regulators |
文件: | 总32页 (文件大小:661K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3728L/LTC3728LX
Dual, 550kHz, 2-Phase
Synchronous Regulators
U
FEATURES
DESCRIPTIO
The LTC®3728L/LTC3728LX are dual high performance
step-down switching regulator controllers that drive all
N-channel synchronous power MOSFET stages. A con-
stant frequency current mode architecture allows phase-
lockable frequency of up to 550kHz. Power loss and noise
due to the ESR of the input capacitors are minimized by
operating the two controller output stages out of phase.
■
Dual, 180° Phased Controllers Reduce Required
Input Capacitance and Power Supply Induced Noise
OPTI-LOOP® Compensation Minimizes COUT
■
■
±1% Output Voltage Accuracy (LTC3728LC)
Power Good Output Voltage Indicator
■
■
Phase-Lockable Fixed Frequency 250kHz to 550kHz
■
Dual N-Channel MOSFET Synchronous Drive
■
Wide VIN Range: 4.5V to 28V Operation
OPTI-LOOP compensation allows the transient response
tobeoptimizedoverawiderangeofoutputcapacitanceand
ESRvalues. Theprecision0.8Vreferenceandpowergood
output indicator are compatible with future microproces-
sor generations, and a wide 4.5V to 28V (30V maximum)
input supply range encompasses all battery chemistries.
■
Very Low Dropout Operation: 99% Duty Cycle
■
Adjustable Soft-Start Current Ramping
Foldback Output Current Limiting
■
■
Latched Short-Circuit Shutdown with Defeat Option
Output Overvoltage Protection
Low Shutdown IQ: 20µA
5V and 3.3V Standby Regulators
3 Selectable Operating Modes: Constant Frequency,
Burst Mode® Operation and PWM
5mm × 5mm QFN and 28-Lead Narrow SSOP
Packages
■
■
■
■
A RUN/SS pin for each controller provides both soft-start
and optional timed, short-circuit shutdown. Current
foldback limits MOSFET dissipation during short-circuit
conditions when overcurrent latchoff is disabled. Output
overvoltage protection circuitry latches on the bottom
MOSFET until VOUT returns to normal. The FCB mode pin
can select among Burst Mode, constant frequency mode
and continuous inductor current mode or regulate a
secondary winding. The LTC3728L/LTC3728LX include a
power good output pin that indicates when both outputs
are within 7.5% of their designed set point.
■
U
APPLICATIO S
■
Notebook and Palmtop Computers
■
Telecom Systems
■
Portable Instruments
■
Battery-Operated Digital Devices
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.
■
DC Power Distribution Systems
U
TYPICAL APPLICATIO
V
IN
5.2V TO 28V
C
IN
1µF
CERAMIC
+
22µF
4.7µF
D3
50V
D4
V
PGOOD INTV
IN
CC
M2
M1
CERAMIC
TG1
TG2
L1
3.2µH
L2
3.2µH
BOOST1
SW1
BOOST2
SW2
C
, 0.1µF
C
B2
, 0.1µF
B1
LTC3728L/
LTC3728LX
BG1
BG2
f
IN
500kHz
PLLIN
PGND
+
+
SENSE1
SENSE2
R
R
SENSE2
SENSE1
1000pF
1000pF
0.01Ω
0.01Ω
–
–
SENSE1
V
SENSE2
V
V
3.3V
5A
OSENSE1
TH1
OSENSE2
V
OUT2
OUT1
5V
5A
R2
R4
63.4k
1%
I
I
TH2
105k
1%
C
C
C2
C1
220pF
C
47µF
6V
C
56µF
6V
RUN/SS1 SGND RUN/SS2
OUT1
OUT
220pF
R
C2
+
+
R1
20k
1%
R3
20k
1%
R
C1
C
C
SS1
0.1µF
SS2
0.1µF
15k
15k
SP
SP
M1, M2: FDS6982S
3728 F01
Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter
3728lxfa
1
LTC3728L/LTC3728LX
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
ITH1, TH2, VOSENSE1, VOSENSE2 Voltages ...2.7V to –0.3V
I
Input Supply Voltage (VIN)........................ 30V to –0.3V
Top Side Driver Voltages
Peak Output Current <10µs (TG1, TG2, BG1, BG2) .. 3A
INTVCC Peak Output Current ................................ 40mA
Operating Temperature Range (Note 7)
(BOOST1, BOOST2) .................................. 36V to –0.3V
Switch Voltage (SW1, SW2) ........................ 30V to –5V
INTVCC, EXTVCC, RUN/SS1, RUN/SS2, (BOOST1-SW1),
(BOOST2-SW2), PGOOD ............................ 7V to –0.3V
SENSE1+, SENSE2+, SENSE1–,
LTC3728LC/LTC3728LXC....................... 0°C to 85°C
LTC3728LE........................................ –40°C to 85°C
Junction Temperature (Note 2)............................ 125°C
Storage Temperature Range ................ –65°C to 125°C
Reflow Peak Body Temperature (UH Package) .... 260°C
Lead Temperature (Soldering, 10 sec)
SENSE2– Voltages....................... (1.1)INTVCC to –0.3V
PLLIN, PLLFLTR, FCB, Voltage ........... INTVCC to –0.3V
(GN Package) ................................................... 300°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
1
2
28 PGOOD
27 TG1
RUN/SS1
+
32 31 30 29 28 27 26 25
SENSE1
LTC3728LCUH
LTC3728LCGN
LTC3728LEGN
–
V
1
2
3
4
5
6
7
8
24 BOOST1
3
26 SW1
OSENSE1
SENSE
PLLFLTR
PLLIN
FCB
23
22
21
V
IN
4
25 BOOST1
V
LTC3728LEUH
OSENSE1
BG1
5
24
V
IN
PLLFLTR
PLLIN
FCB
LTC3728LXCUH
EXTV
CC
6
23 BG1
22 EXTV
21 INTV
33
I
20 INTV
TH1
SGND
3.3V
CC
7
CC
CC
PGND
19
8
I
TH1
18 BG2
OUT
9
20 PGND
SGND
I
17 BOOST2
TH2
10
11
12
13
14
19 BG2
3.3V
OUT
9
10 11 12 13 14 15 16
UH PART
MARKING
18 BOOST2
17 SW2
I
TH2
V
OSENSE2
–
16 TG2
SENSE2
SENSE2
+
UH PACKAGE
15 RUN/SS2
3728L
3728LE
3728LX
32-LEAD (5mm × 5mm) PLASTIC QFN
GN PACKAGE
TJMAX = 125°C, θJA = 34°C/W
28-LEAD NARROW PLASTIC SSOP
EXPOSED PAD IS SGND (PIN 33),
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 95°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
V
Regulated Feedback Voltage
(Note 3); I
(Note 3); I
Voltage = 1.2V (LTC3728LC)
Voltage = 1.2V (LTC3728LE/LTC3728LX)
●
●
0.792
0.788
0.800
0.800
0.808
0.812
V
V
OSENSE1, 2
TH1, 2
TH1, 2
I
Feedback Current
(Note 3)
–5
–50
0.02
nA
VOSENSE1, 2
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 3.6V to 30V (Note 3)
IN
0.002
%/V
REFLNREG
LOADREG
(Note 3)
Measured in Servo Loop; ∆I Voltage = 1.2V to 0.7V
Measured in Servo Loop; ∆I Voltage = 1.2V to 2.0V
●
●
0.1
–0.1
0.5
–0.5
%
%
TH
TH
g
Transconductance Amplifier g
I = 1.2V; Sink/Source 5uA; (Note 3)
TH1, 2
1.3
mmho
m1, 2
m
3728lxfa
2
LTC3728L/LTC3728LX
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
= 1.2V; (Note 3)
MIN
TYP
MAX
UNITS
g
Transconductance Amplifier GBW
I
3
MHz
mGBW1, 2
TH1, 2
I
Input DC Supply Current
Normal Mode
(Note 4)
IN
RUN/SS1, 2
Q
V
V
= 15V; EXTV Tied to V ; V = 5V
450
20
µA
µA
CC
OUT1 OUT1
Shutdown
= 0V
35
0.84
–0.1
4.8
V
Forced Continuous Threshold
Forced Continuous Pin Current
●
0.76
0.800
–0.18
4.3
V
µA
V
FCB
I
V
= 0.85V
–0.50
FCB
FCB
V
Burst Inhibit (Constant Frequency)
Threshold
Measured at FCB pin
BINHIBIT
UVLO
Undervoltage Lockout
V
Ramping Down
●
●
3.5
0.86
–60
99.4
1.2
1.5
4.1
2
4
V
V
IN
V
Feedback Overvoltage Lockout
Sense Pins Total Source Current
Maximum Duty Factor
Measured at V
0.84
–90
98
0.88
OVL
OSENSE1, 2
I
(Each Channel); V
In Dropout
–
– = V + + = 0V
SENSE1 , 2
µA
%
µA
V
SENSE
SENSE1 , 2
DF
MAX
I
Soft-Start Charge Current
V
V
V
= 1.9V
RUN/SS1, 2
0.5
RUN/SS1, 2
V
V
ON RUN/SS Pin ON Threshold
LT RUN/SS Pin Latchoff Arming Threshold
RUN/SS Discharge Current
V Rising
RUN/SS1, RUN/SS2
1.0
2.0
4.75
4
RUN/SS1, 2
RUN/SS1, 2
SCL1, 2
V
Rising from 3V
V
RUN/SS1, RUN/SS2
I
Soft Short Condition V
V
= 0.5V;
0.5
µA
OSENSE1, 2
= 4.5V
RUN/SS1, 2
I
Shutdown Latch Disable Current
Maximum Current Sense Threshold
V
= 0.5V
1.6
5
µA
SDLHO
OSENSE1, 2
V
V
V
= 0.7V,V
= 0.7V,V
–
SENSE1 , 2
SENSE1 , 2
–
–
= 5V
= 5V
65
62
75
75
85
88
mV
mV
SENSE(MAX)
OSENSE1, 2
OSENSE1, 2
–
●
TG Transition Time:
Rise Time
Fall Time
(Note 5)
TG1, 2 t
TG1, 2 t
C
C
= 3300pF
55
55
100
100
ns
ns
r
f
LOAD
= 3300pF
LOAD
BG Transition Time:
Rise Time
Fall Time
(Note 5)
LOAD
LOAD
BG1, 2 t
BG1, 2 t
C
C
= 3300pF
= 3300pF
45
45
100
90
ns
ns
r
f
TG/BG t
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
1D
C
C
= 3300pF Each Driver
= 3300pF Each Driver
80
ns
LOAD
LOAD
BG/TG t
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
2D
80
ns
ns
t
Minimum On-Time
Tested with a Square Wave (Note 6)
100
ON(MIN)
INTV Linear Regulator
CC
INTVCC
V
V
V
V
V
Internal V Voltage
6V < V < 30V, V = 4V
4.8
4.5
5.0
0.2
100
4.7
0.2
5.2
2.0
V
%
CC
IN
EXTVCC
INT
INTV Load Regulation
I
I
I
= 0 to 20mA, V
= 4V
LDO
LDO
CC
CC
CC
CC
EXTVCC
EXT
EXTV Voltage Drop
= 20mA, V
= 5V
200
mV
V
CC
EXTVCC
EXTV Switchover Voltage
= 20mA, EXTV Ramping Positive
●
EXTVCC
LDOHYS
CC
CC
EXTV Hysteresis
V
CC
Oscillator and Phase-Locked Loop
f
f
f
Nominal Frequency
Lowest Frequency
Highest Frequency
PLLIN Input Resistance
V
V
V
= 1.2V
= 0V
360
230
480
400
260
550
50
440
290
590
kHz
kHz
kHz
kΩ
NOM
LOW
HIGH
PLLFLTR
PLLFLTR
PLLFLTR
≥ 2.4V
R
PLLIN
I
Phase Detector Output Current
Sinking Capability
Sourcing Capability
PLLFLTR
f
f
< f
OSC
> f
OSC
–15
15
µA
µA
PLLIN
PLLIN
3728lxfa
3
LTC3728L/LTC3728LX
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
3.3V Linear Regulator
V
V
V
3.3V Regulator Output Voltage
3.3V Regulator Load Regulation
3.3V Regulator Line Regulation
No Load
●
3.2
3.35
0.5
3.45
2
V
%
%
3.3OUT
3.3IL
I
= 0 to 10mA
3.3
6V < V < 30V
0.05
0.2
3.3VL
IN
PGOOD Output
V
PGOOD Voltage Low
I
= 2mA
= 5V
0.1
0.3
V
PGL
PGOOD
I
PGOOD Leakage Current
PGOOD Trip Level, Either Controller
V
V
±1
µA
PGOOD
PGOOD
V
with Respect to Set Output Voltage
Ramping Negative
Ramping Positive
PG
OSENSE
V
V
–6
6
–7.5
7.5
–9.5
9.5
%
%
OSENSE
OSENSE
Note 1: Absolute Maximum Ratings are those values beyond which the life
delivered at the switching frequency. See Applications Information.
of a device may be impaired.
Note 5: Rise and fall times are measured using 10% and 90% levels. Delay
Note 2: T is calculated from the ambient temperature T and power
times are measured using 50% levels.
J
A
dissipation P according to the following formulas:
D
Note 6: The minimum on-time condition is specified for an inductor
LTC3728LUH/LTC3728LXUH: T = T + (P • 34°C/W)
peak-to-peak ripple current ≥40% of I
considerations in the Applications Information section).
(see minimum on-time
J
A
D
MAX
LTC3728LGN: T = T + (P • 95°C/W)
J
A
D
Note 7: The LTC3728LC/LTC3728LXC are guaranteed to meet
performance specifications from 0°C to 85°C. The LTC3728LE is
guaranteed to meet performance specifications over the –40°C to 85°C
operating temperature range as assured by design, characterization and
correlation with statistical process controls.
Note 3: The IC is tested in a feedback loop that servos V
specified voltage and measures the resultant V
Note 4: Dynamic supply current is higher due to the gate charge being
to a
ITH1, 2
OSENSE1, 2.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Output Current
and Mode (Figure 13)
Efficiency vs Output Current
(Figure 13)
Efficiency vs Input Voltage
(Figure 13)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
100
90
80
70
60
50
Burst Mode
OPERATION
V
= 7V
IN
V
= 10V
IN
FORCED
CONTINUOUS
MODE (PWM)
V
= 15V
IN
V
= 20V
IN
CONSTANT
FREQUENCY
(BURST DISABLE)
V
= 15V
= 5V
V
= 5V
= 3A
IN
OUT
OUT
OUT
V
= 5V
OUT
V
I
f = 250kHz
f = 250kHz
f = 250kHz
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
5
15
25
35
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
3728L G01
3728L G02
3728L G03
3728lxfa
4
LTC3728L/LTC3728LX
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Input Voltage
and Mode (Figure 13)
INTVCC and EXTVCC Switch
Voltage vs Temperature
EXTVCC Voltage Drop
1000
800
600
400
200
0
200
150
100
50
5.05
INTV VOLTAGE
CC
5.00
4.95
4.90
4.85
4.80
4.75
4.70
BOTH
CONTROLLERS ON
EXTV SWITCHOVER THRESHOLD
CC
SHUTDOWN
10
0
0
10
20
30
40
50
TEMPERATURE (°C)
100 125
0
5
15
20
25
30
–50 –25
0
25
75
INPUT VOLTAGE (V)
CURRENT (mA)
3728L G05
3728L G04
3728L G06
Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)
Maximum Current Sense Threshold
vs Duty Factor
Internal 5V LDO Line Regulation
75
50
25
0
5.1
5.0
80
70
60
50
40
30
20
10
0
I
= 1mA
LOAD
4.9
4.8
4.7
4.6
4.5
4.4
0
20
40
60
80
100
50
20
INPUT VOLTAGE (V)
30
0
25
75
100
0
5
10
15
25
DUTY FACTOR (%)
PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
3728L G08
3728L G09
3728L G07
Maximum Current Sense Threshold
vs VRUN/SS (Soft-Start)
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
Current Sense Threshold
vs ITH Voltage
90
80
80
76
72
68
64
60
80
60
40
20
V
= 1.6V
SENSE(CM)
70
60
50
40
30
20
10
0
–10
–20
–30
0
0
1
2
3
4
5
6
0
1
2
3
4
5
0
0.5
1
1.5
(V)
2
2.5
V
(V)
COMMON MODE VOLTAGE (V)
V
ITH
RUN/SS
3728L G10
3728L G11
3728L G12
3728lxfa
5
LTC3728L/LTC3728LX
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Load Regulation
VITH vs VRUN/SS
SENSE Pins Total Source Current
0.0
–0.1
–0.2
–0.3
–0.4
2.5
2.0
1.5
1.0
100
50
V
= 0.7V
FCB = 0V
= 15V
OSENSE
V
IN
FIGURE 13
0
–50
–100
0.5
0
0
2
3
4
5
6
2
4
0
1
2
3
4
5
1
0
6
V
(V)
LOAD CURRENT (A)
V
COMMON MODE VOLTAGE (V)
RUN/SS
SENSE
3728L G14
3728L G13
3728L G15
Maximum Current Sense
Threshold vs Temperature
Dropout Voltage vs Output Current
(Figure 14)
RUN/SS Current vs Temperature
80
78
76
74
72
70
4
3
2
1
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
V
= 5V
OUT
R
= 0.015Ω
SENSE
R
= 0.010Ω
SENSE
0
0
50
75 100 125
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT CURRENT (A)
–50 –25
0
25
–50 –25
0
25
125
50
75 100
TEMPERATURE (°C)
TEMPERATURE (°C)
3728L G18
3728L G17
3728L G25
Soft-Start Up (Figure 13)
Load Step (Figure 13)
Load Step (Figure 13)
VOUT
5V/DIV
VOUT
200mV/DIV
VOUT
200mV/DIV
VRUN/SS
5V/DIV
IL
IL
2A/DIV
2A/DIV
IL
2A/DIV
V
IN = 15V
5ms/DIV
3728L G19
V
IN = 15V
VOUT = 5V
PLLFLTR = 0V
20µs/DIV
3728L G20
VIN = 15V
VOUT = 5V
VPLLFLTR = 0V
20µs/DIV
3728L G21
VOUT = 5V
V
LOAD STEP = 0A TO 3A
Burst Mode OPERATION
LOAD STEP = 0A TO 3A
CONTINUOUS MODE
3728lxfa
6
LTC3728L/LTC3728LX
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Source/Capacitor
Instantaneous Current (Figure 13)
Constant Frequency (Burst Inhibit)
Operation (Figure 13)
Burst Mode Operation (Figure 13)
IIN
VOUT
20mV/DIV
2A/DIV
VOUT
20mV/DIV
VIN
200mV/DIV
VSW1
10V/DIV
VSW2
10V/DIV
IL
IL
0.5A/DIV
0.5A/DIV
V
IN = 15V
1µs/DIV
3728L G22
VIN = 15V
10µs/DIV
3728L G23
VIN = 15V
2µs/DIV
3728L G24
VOUT1 = 5V, VOUT2 = 3.3V
VPLLFLTR = 0V
VOUT = 5V
VOUT = 5V
VPLLFLTR = 0V
VPLLFLTR = 0V
IOUT5 = IOUT3.3 = 2A
V
FCB = OPEN
VFCB = 5V
IOUT = 20mA
IOUT = 20mA
Current Sense Pin Input Current
vs Temperature
EXTVCC Switch Resistance
vs Temperature
Oscillator Frequency
vs Temperature
35
33
31
29
27
25
10
8
700
600
V
OUT
= 5V
V
= 2.4V
PLLFLTR
PLLFLTR
500
400
300
200
100
V
= 1.2V
= 0V
6
4
V
PLLFLTR
2
0
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
50
100 125
–50 –25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3728L G26
3728L G27
3728L G28
Undervoltage Lockout
vs Temperature
Shutdown Latch Thresholds
vs Temperature
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
3.50
3.45
3.40
3.35
LATCH ARMING
LATCHOFF
THRESHOLD
3.30
3.25
3.20
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
125
–50 –25
0
25
75
50
75 100
TEMPERATURE (°C)
3728L G29
3728L G30
3728lxfa
7
LTC3728L/LTC3728LX
U
U
U
PI FU CTIO S
VOSENSE1, VOSENSE2: Error Amplifier Feedback Input. Re-
ceives the remotely-sensed feedback voltage for each
controller from an external resistive divider across the
output.
is also invoked via this pin as described in the Applications
Information section.
TG2, TG1: High Current Gate Drives for Top N-Channel
MOSFETs. These are the outputs of floating drivers with a
voltage swing equal to INTVCC – 0.5V superimposed on
the switch node voltage SW.
PLLFLTR: Filter Connection for Phase-Locked Loop. Al-
ternatively, this pin can be driven with an AC or DC voltage
source to vary the frequency of the internal oscillator.
SW2, SW1: Switch Node Connections to Inductors. Volt-
age swing at these pins is from a Schottky diode (external)
voltage drop below ground to VIN.
PLLIN: External Synchronization Input to Phase Detector.
This pin is internally terminated to SGND with 50kΩ. The
phase-locked loop will force the rising top gate signal of
controller 1 to be synchronized with the rising edge of the
PLLIN signal.
BOOST2,BOOST1:BootstrappedSuppliestotheTopSide
Floating Drivers. Capacitors are connected between the
boost and switch pins and Schottky diodes are tied be-
tween the boost and INTVCC pins. Voltage swing at the
boost pins is from INTVCC to (VIN + INTVCC).
FCB:ForcedContinuousControl Input.Thisinputactson
both controllers and is normally used to regulate a
secondary winding. Pulling this pin below 0.8V will force
continuous synchronous operation.
BG2, BG1:HighCurrentGateDrivesforBottom(Synchro-
nous)N-Channel MOSFETs. Voltageswing at these pinsis
from ground to INTVCC.
ITH1, TH2:Error Amplifier Output and Switching Regulator
I
Compensation Point. Each associated channels’ current
comparator trip point increases with this control voltage.
PGND: Driver Power Ground. Connects to the sources of
bottom (synchronous) N-channel MOSFETs, anodes of the
Schottky rectifiers and the (–) terminal(s) of CIN.
SGND: Small Signal Ground. Common to both con-
trollers, this pin must be routed separately from high
current grounds to the common (–) terminals of the
COUT capacitors.
INTVCC: Output of the Internal 5V Linear Low Dropout
Regulator and the EXTVCC Switch. The driver and control
circuits are powered from this voltage source. Must be
decoupled to power ground with a minimum of 4.7µF tanta-
lum or other low ESR capacitor.
3.3VOUT: Lnear Regulator Output. Capable of supplying
10mA DC with peak currents as high as 50mA.
NC: No Connect.
SENSE2–, SENSE1–: The (–) Input to the Differential
Current Comparators.
SENSE2+, SENSE1+: The (+) Input to the Differential
Current Comparators. The ITH pin voltage and controlled
offsets between the SENSE– and SENSE+ pins in conjunc-
tion with RSENSE set the current trip threshold.
EXTVCC: External Power Input to an Internal Switch Con-
nected to INTVCC. This switch closes and supplies VCC
power,bypassingtheinternallowdropoutregulator,when-
ever EXTVCC is higher than 4.7V. See EXTVCC connection
in Applications section. Do not exceed 7V on this pin.
VIN: Main Supply Pin. A bypass capacitor should be tied
between this pin and the signal ground pin.
PGOOD: Open-Drain Logic Output. PGOOD is pulled to
ground when the voltage on either VOSENSE pin is not
within ±7.5% of its set point.
RUN/SS2, RUN/SS1: Combination of soft-start, run con-
trol inputs and short-circuit detection timers. A capacitor
to ground at each of these pins sets the ramp time to full
output current. Forcing either of these pins back below
1.0V causes the IC to shut down the circuitry required for
that particular controller. Latchoff overcurrent protection
ExposedPad(UHPackageOnly):SignalGround. Mustbe
soldered to the PCB, providing a local ground for the
control components of the IC, and be tied to the PGND pin
under the IC.
3728lxfa
8
LTC3728L/LTC3728LX
U
U
W
FU CTIO AL DIAGRA
PLLIN
INTV
CC
V
IN
F
PHASE DET
IN
D
C
B
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
50k
BOOST
TG
PLLFLTR
B
DROP
OUT
+
CLK1
CLK2
–
TOP
BOT
R
LP
C
IN
D
OSCILLATOR
1
DET
BOT
FCB
C
LP
SW
TOP ON
0.86V
S
Q
Q
+
SWITCH
LOGIC
INTV
CC
R
V
OSENSE1
PGOOD
BG
–
+
0.74V
0.86V
C
OUT
PGND
B
+
+
–
0.55V
–
+
V
OUT
SHDN
R
SENSE
V
OSENSE2
–
+
INTV
CC
0.74V
BINH
I1
I2
INTV
CC
3V
+
–
+
–
+
4.5V
0.8V
–
+ +
–
+
0.18µA
FCB
–
SENSE
SENSE
30k
30k
R6
3mV
0.86V
4(V
–
)
+
–
FB
FCB
R5
SLOPE
COMP
45k
45k
2.4V
3.3V
OUT
V
OSENSE
R2
V
FB
+
–
V
REF
–
EA
+
0.80V
0.86V
R1
OV
V
IN
+
–
V
IN
C
C
+
–
4.8V
I
TH
5V
1.2µA
EXTV
INTV
LDO
REG
CC
SHDN
RST
RUN
SOFT
START
R
C
C
C2
6V
4(V
)
FB
CC
5V
RUN/SS
+
INTERNAL
SUPPLY
SGND (UH PACKAGE PAD)
C
SS
3728 FD/F02
Figure 2
U
OPERATIO
(Refer to Functional Diagram)
Main Control Loop
inductor current at which I1 resets the RS latch is con-
trolled by the voltage on the ITH pin, which is the output of
each error amplifier EA. The VOSENSE pin receives the
voltage feedback signal, which is compared to the internal
reference voltage by the EA. When the load current in-
creases, it causes a slight decrease in VOSENSE relative to
the 0.8V reference, which in turn causes the ITH voltage to
The IC uses a constant frequency, current mode step-
down architecture with the two controller channels oper-
ating 180 degrees out of phase. During normal operation,
each top MOSFET is turned on when the clock for that
channel sets the RS latch, and turned off when the main
current comparator, I1, resets the RS latch. The peak
3728lxfa
9
LTC3728L/LTC3728LX
U
OPERATIO
(Refer to Functional Diagram)
increase until the average inductor current matches the
new load current. AfterthetopMOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
currentstartstoreverse, asindicatedbycurrentcompara-
tor I2, or the beginning of the next cycle.
temporarily inhibit turn-on of both output MOSFETs until
the output voltage drops. There is 60mV of hysteresis in
the burst comparator B tied to the ITH pin. This hysteresis
produces output signals to the MOSFETs that turn them
on for several cycles, followed by a variable “sleep”
interval depending upon the load current. The resultant
output voltage ripple is held to a very small value by
having the hysteretic comparator after the error amplifier
gain block.
The top MOSFET drivers are biased from floating boot-
strap capacitor CB, which normally is recharged during
each off cycle through an external diode when the top
MOSFET turns off. As VIN decreases to a voltage close to
VOUT, the loop may enter dropout and attempt to turn on
the top MOSFET continuously. The dropout detector de-
tects this and forces the top MOSFET off for about 400ns
every tenth cycle to allow CB to recharge.
Frequency Synchronization
The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the PLLIN pin. The
output of the phase detector at the PLLFLTR pin is also the
DC frequency control input of the oscillator that operates
over a 260kHz to 550kHz range corresponding to a DC
voltageinputfrom0Vto2.4V.Whenlocked,thePLLaligns
the turn on of the top MOSFET to the rising edge of the
synchronizingsignal.WhenPLLINisleftopen,thePLLFLTR
pingoeslow,forcingtheoscillatortominimumfrequency.
The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches1.5V,themaincontrolloopisenabledwiththe
ITH voltageclampedatapproximately30%ofitsmaximum
value. As CSS continues to charge, the ITH pin voltage is
gradually released allowing normal, full-current opera-
tion. When both RUN/SS1 and RUN/SS2 are low, all
controller functions are shut down, including the 5V and
3.3V regulators.
Constant Frequency Operation
When the FCB pin is tied to INTVCC, Burst Mode operation
is disabled and the forced minimum output current
requirementisremoved.Thisprovidesconstantfrequency,
discontinuous current (preventing reverse inductor cur-
rent) operation over the widest possible output current
range.Thisconstantfrequencyoperationisnotasefficient
as Burst Mode operation, but does provide a lower noise,
constant frequency operating mode down to approxi-
mately 1% of the designed maximum output current.
Low Current Operation
The FCB pin is a multifunction pin providing two func-
tions:1)toprovideregulationforasecondarywindingby
temporarily forcing continuous PWM operation on
both controllers; and 2) to select between two modes of
lowcurrentoperation. Whenthe FCBpinvoltageis below
0.8V, the controller forces continuous PWM current
mode operation. In this mode, the top and bottom
MOSFETsarealternatelyturnedontomaintaintheoutput
voltage independent of direction of inductor current.
When the FCB pin is below VINTVCC – 2V but greater than
0.8V, the controller enters Burst Mode operation. Burst
Mode operation sets a minimum output current level
beforeinhibitingthetopswitchandturnsoffthesynchro-
nous MOSFET(s) when the inductor current goes nega-
tive. This combination of requirements will, at low cur-
rents, force the ITH pin below a voltage threshold that will
Continuous Current (PWM) Operation
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, current will be
forced back into the main power supply potentially boost-
ing the input supply to dangerous voltage levels—
BEWARE!
3728lxfa
10
LTC3728L/LTC3728LX
U
OPERATIO
(Refer to Functional Diagram)
INTVCC/EXTVCC Power
This built-in latchoff can be overridden by providing a
>5µA pull-up at a compliance of 5V to the RUN/SS pin(s).
This current shortens the soft start period but also pre-
vents net discharge of the RUN/SS capacitor(s) during an
overcurrent and/or short-circuit condition. Foldback cur-
rent limiting is also activated when the output voltage falls
below 70% of its nominal level whether or not the short-
circuit latchoff circuit is enabled. Even if a short is present
and the short-circuit latchoff is not enabled, a safe, low
outputcurrentisprovidedduetointernalcurrentfoldback
and actual power wasted is low due to the efficient nature
of the current mode switching regulator.
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open, an internal 5V low
dropoutlinearregulatorsuppliesINTVCC power.IfEXTVCC
is taken above 4.7V, the 5V regulator is turned off and an
internalswitchisturnedonconnectingEXTVCC toINTVCC.
This allows the INTVCC power to be derived from a high
efficiency external source such as the output of the regu-
lator itself or a secondary winding, as described in the
Applications Information section.
Output Overvoltage Protection
THEORY AND BENEFITS OF 2-PHASE OPERATION
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFETisturnedoffandthebottomMOSFETisturnedon
until the overvoltage condition is cleared.
The LTC1628 and the LTC3728L family of dual high
efficiency DC/DC controllers brings the considerable ben-
efits of 2-phase operation to portable applications for the
first time. Notebook computers, PDAs, handheld termi-
nals and automotive electronics will all benefit from the
lower input filtering requirement, reduced electromag-
netic interference (EMI) and increased efficiency associ-
ated with 2-phase operation.
Power Good (PGOOD) Pin
ThePGOODpinisconnectedtoanopendrainofaninternal
MOSFET.TheMOSFETturnsonandpullsthepinlowwhen
either output is not within ±7.5% of the nominal output
level as determined by the resistive feedback divider.
When both outputs meet the ±7.5% requirement, the
MOSFET is turned off within 10µs and the pin is allowed to
be pulled up by an external resistor to a source of up to 7V.
Why the need for 2-phase operation? Up until the 2-phase
family, constant-frequency dual switching regulators op-
erated both channels in phase (i.e., single-phase opera-
tion). Thismeansthatbothswitchesturnedonatthesame
time, causing current pulses of up to twice the amplitude
of those for one regulator to be drawn from the input
capacitorandbattery.Theselargeamplitudecurrentpulses
increased the total RMS current flowing from the input
capacitor, requiring the use of more expensive input
capacitorsandincreasingbothEMIandlossesintheinput
capacitor and battery.
Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff
TheRUN/SScapacitorsareusedinitiallytolimittheinrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used in a short-circuit time-out
circuit. If the output voltage falls to less than 70% of its
nominal output voltage, the RUN/SS capacitor begins
discharging on the assumption that the output is in an
overcurrent and/or short-circuit condition. If the condi-
tion lasts for a long enough period as determined by the
size of the RUN/SS capacitor, the controller will be shut
down until the RUN/SS pin(s) voltage(s) are recycled.
With 2-phase operation, the two channels of the dual-
switching regulator are operated 180 degrees out of
phase. This effectively interleaves the current pulses
drawn by the switches, greatly reducing the overlap time
where they add together. The result is a significant reduc-
tion in total RMS input current, which in turn allows less
expensive input capacitors to be used, reduces shielding
requirements for EMI and improves real world operating
efficiency.
3728lxfa
11
LTC3728L/LTC3728LX
U
OPERATIO
(Refer to Functional Diagram)
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
IIN(MEAS) = 2.53ARMS
IIN(MEAS) = 1.55ARMS
DC236 F03a
DC236 F03b
(a)
(b)
Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators
Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows
Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency
Figure 3 compares the input waveforms for a representa-
tive single-phase dual switching regulator to the LTC1628
2-phase dual switching regulator. An actual measurement
of the RMS input current under these conditions shows
that 2-phase operation dropped the input current from
2.53ARMS to 1.55ARMS. While this is an impressive reduc-
tion in itself, remember that the power losses are propor-
tional to IRMS2, meaning that the actual power wasted is
reduced by a factor of 2.66. The reduced input ripple
voltage also means less power is lost in the input power
path, which could include batteries, switches, trace/con-
nectorresistancesandprotectioncircuitry.Improvements
inbothconductedandradiatedEMIalsodirectlyaccrueas
a result of the reduced RMS input current and voltage.
regulators, why hasn’t it been done before? The answer is
that, while simple in concept, it is hard to implement.
Constant-frequency current mode switching regulators
require an oscillator derived “slope compensation” signal
to allow stable operation of each regulator at over 50%
duty cycle. This signal is relatively easy to derive in single-
phasedualswitchingregulators,butrequiredthedevelop-
ment of a new and proprietary technique to allow 2-phase
operation. In addition, isolation between the two channels
becomes more critical with 2-phase operation because
switch transitions in one channel could potentially disrupt
the operation of the other channel.
These 2-phase parts are proof that these hurdles have
been surmounted. They offer unique advantages for the
ever-expanding number of high efficiency power supplies
required in portable electronics.
Of course, the improvement afforded by 2-phase opera-
tion is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
voltage VIN (Duty Cycle = VOUT/VIN). Figure 4 shows how
theRMSinputcurrentvariesforsingle-phaseand2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
3.0
SINGLE PHASE
DUAL CONTROLLER
2.5
2.0
1.5
It can readily be seen that the advantages of 2-phase
operation are not just limited to a narrow operating range,
but in fact extend over a wide region. A good rule of thumb
for most applications is that 2-phase operation will reduce
theinputcapacitorrequirementtothatforjustonechannel
operating at maximum current and 50% duty cycle.
2-PHASE
DUAL CONTROLLER
1.0
0.5
V
O1
V
O2
= 5V/3A
= 3.3V/3A
0
0
10
20
INPUT VOLTAGE (V)
30
40
3728 F04
A final question: If 2-phase operation offers such an
advantage over single-phase operation for dual switching
Figure 4. RMS Input Current Comparison
3728lxfa
12
LTC3728L/LTC3728LX
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APPLICATIO S I FOR ATIO
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2.5
2.0
1.5
1.0
0.5
0
Figure1onthefirstpageisabasicLTC3728L/LTC3728LX
applicationcircuit.Externalcomponentselectionisdriven
by the load requirement, and begins with the selection of
R
SENSE andtheinductorvalue.Next,thepowerMOSFETs
and D1 are selected. Finally, CIN and COUT are selected.
The circuit shown in Figure 1 can be configured for
operation up to an input voltage of 28V (limited by the
external MOSFETs).
RSENSE Selection For Output Current
200
300
400
500
600
R
SENSE is chosen based on the required output current.
OPERATING FREQUENCY (kHz)
3728 F05
The current comparator has a maximum threshold of
75mV/RSENSE and an input common mode range of SGND
to1.1(INTVCC).Thecurrentcomparatorthresholdsetsthe
peak of the inductor current, yielding a maximum average
output current IMAX equal to the peak value less half the
peak-to-peak ripple current, ∆IL.
Figure 5. PLLFLTR Pin Voltage vs Frequency
isincreasedthegatechargelosseswillbehigher,reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 550kHz.
Allowing a margin for variations in the IC and external
component values yields:
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
50mV
IMAX
RSENSE
=
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability crite-
rion for buck regulators operating at greater than 50%
duty factor. A curve is provided to estimate this reduction
in peak output current level depending upon the operating
duty factor.
Theinductorvaluehasadirecteffectonripplecurrent.The
inductor ripple current ∆IL decreases with higher induc-
tance or frequency and increases with higher VIN:
Operating Frequency
TheICusesaconstantfrequencyphase-lockablearchitec-
ture with the frequency determined by an internal capaci-
tor. This capacitor is charged by a fixed current plus an
additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to Phase-Locked Loop
and Frequency Synchronization in the Applications Infor-
mation section for additional information.
1
VOUT
V
IN
∆IL =
VOUT 1–
(f)(L)
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL=0.3(IMAX). The maximum ∆IL
occurs at the maximum input voltage.
A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure 5. As the operating frequency
3728lxfa
13
LTC3728L/LTC3728LX
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U
APPLICATIO S I FOR ATIO
The inductor value also has secondary effects. The transi-
tion to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
The peak-to-peak drive levels are set by the INTVCC
voltage. This voltage is typically 5V during start-up (see
EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(VIN < 5V); then, sub-logic level threshold MOSFETs
(VGS(TH) < 3V) should be used. Pay close attention to the
BVDSS specification for the MOSFETs as well; most of the
logic level MOSFETs are limited to 30V or less.
SelectioncriteriaforthepowerMOSFETsincludethe“ON”
resistanceRDS(ON), MillercapacitanceCMILLER, inputvolt-
age and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER isequaltotheincreaseingatechargealong
the horizontal axis while the curve is approximately flat
divided by the specified change in VDS. This result is then
multiplied by the ratio of the application applied VDS to the
Gate charge curve specified VDS. When the IC is operating
in continuous modetheduty cycles forthetopand bottom
MOSFETs are given by:
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite, molyper-
malloy, or Kool Mµ® cores. Actual core loss is indepen-
dent of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance in-
creases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
VOUT
V
IN
Main SwitchDuty Cycle =
V – VOUT
IN
Synchronous SwitchDuty Cycle =
V
IN
The MOSFET power dissipations at maximum output
current are given by:
Molypermalloy (from Magnetics, Inc.) is a very good, low
losscorematerialfortoroids,butitismoreexpensivethan
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be-
cause they generally lack a bobbin, mounting is more
difficult. However, designsforsurfacemountareavailable
that do not increase the height significantly.
2
) (
VOUT
PMAIN
=
(
IMAX 1+ δ RDS(ON)
+
(
)
V
IN
2
)
IMAX
2
V
IN
RDR CMILLER
(
•
)(
)
1
1
+
f
( )
V
INTVCC – VTHMIN VTHMIN
Power MOSFET and D1 Selection
2
) (
V – VOUT
IN
Two external power MOSFETs must be selected for each
controller in the LTC3728L/LTC3728LX: One N-channel
MOSFET for the top (main) switch, and one N-channel
MOSFET for the bottom (synchronous) switch.
P
SYNC
=
IMAX 1+ δ RDS(ON)
(
)
V
IN
Kool Mµ is a registered trademark of Magnetics, Inc.
3728lxfa
14
LTC3728L/LTC3728LX
W U U
APPLICATIO S I FOR ATIO
U
where δ is the temperature dependency of RDS(ON) and
of 30% to 70% when compared to a single phase power
supply solution.
R
DR (approximately 4Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selec-
tion process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 20µF to 40µF is usually sufficient
for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.
BothMOSFETshaveI2RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V the
high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increasetothepointthattheuseofahigherRDS(ON)device
withlowerCMILLER actuallyprovideshigherefficiency.The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
inputcapacitors,buteachhasdrawbacks:ceramicvoltage
coefficients are very high and may have audible piezoelec-
tric effects; tantalums need to be surge-rated; OS-CONs
suffer from higher inductance, larger case size and limited
surface-mount applicability; electrolytics’ higher ESR and
dryout possibility require several to be used. Multiphase
systems allow the lowest amount of capacitance overall.
As little as one 22µF or two to three 10µF ceramic capaci-
tors are an ideal choice in a 20W to 35W power supply due
to their extremely low ESR. Even though the capacitance
at 20V is substantially below their rating at zero-bias, very
low ESR loss makes ceramics an ideal candidate for
highest efficiency battery operated systems. Also con-
sider parallel ceramic and high quality electrolytic capaci-
tors as an effective means of achieving ESR and bulk
capacitance goals.
Theterm(1+δ)isgenerallygivenforaMOSFETintheform
of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead-
time and requiring a reverse recovery period that could
cost as much as 3% in efficiency at high VIN. A 1A to 3A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.
CIN and COUT Selection
Incontinuousmode, thesourcecurrentofthetopN-chan-
nel MOSFET is a square wave of duty cycle VOUT/VIN. To
preventlargevoltagetransients, alowESRinputcapacitor
sized for the maximum RMS current of one channel must
beused. ThemaximumRMScapacitorcurrentisgivenby:
The selection of CIN is simplified by the multiphase archi-
tecture and its impact on the worst-case RMS current
drawnthroughtheinputnetwork(battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
the highest (VOUT)(IOUT) product needs to be used in the
formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease
the input RMS ripple current from this maximum value
(see Figure 4). The out-of-phase technique typically re-
duces the input capacitor’s RMS ripple current by a factor
1/2
]
VOUT V − VOUT
(
IN
)
[
CINRequiredIRMS ≈IMAX
V
IN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst case condition is com-
monlyusedfordesignbecauseevensignificantdeviations
donotoffermuchrelief.Notethatcapacitormanufacturer’s
3728lxfa
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APPLICATIO S I FOR ATIO
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperaturethanrequired.Severalcapacitorsmayalsobe
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.
The first condition relates to the ripple current into the
ESR of the output capacitance while the second term
guarantees that the output capacitance does not signifi-
cantly discharge during the operating frequency period
due to ripple current. The choice of using smaller output
capacitance increases the ripple voltage due to the dis-
charging term but can be compensated for by using
capacitors of very low ESR to maintain the ripple voltage
at or below 50mV. The ITH pin OPTI-LOOP compensation
components can be optimized to provide stable, high
performance transient response regardless of the output
capacitors selected.
ThebenefitoftheLTC3728L/LTC3728LXmultiphaseclock-
ing can be calculated by using the equation above for the
higher power controller and then calculating the loss that
would have resulted if both controller channels switched
on at the same time. The total RMS power lost is lower
whenbothcontrollersareoperatingduetotheinterleaving
of current pulses through the input capacitor’s ESR. This
is why the input capacitor’s requirement calculated above
for the worst-case controller is adequate for the dual
controller design. Remember that input protection fuse
resistance, battery resistance and PC board trace resis-
tance losses are also reduced due to the reduced peak
currents in a multiphase system. The overall benefit of a
multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
intheefficiencytesting.ThedrainsofthetwotopMOSFETS
should be placed within 1cm of each other and share a
common CIN(s). Separating the drains and CIN may pro-
duce undesirable voltage and current resonances at VIN.
Manufacturers such as Nichicon, United Chemi-Con and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
In surface mount applications multiple capacitors may
need to be used in parallel to meet ESR, RMS current
handling and load step requirements. Aluminum electro-
lytic, dry tantalum and special polymer capacitors are
available in surface mount packages. Special polymer
surface mount capacitors offer very low ESR but have
lower storage capacity per unit volume than other capaci-
tor types. These capacitors offer a very cost-effective
output capacitor solution and are an ideal choice when
combined with a controller having high loop bandwidth.
Tantalumcapacitorsofferthehighestcapacitancedensity
and are often used as output capacitors for switching
regulators having controlled soft-start. Several excellent
surge-tested choices are the AVX TPS, AVX TPSV or the
KEMETT510seriesofsurfacemounttantalums, available
in case heights ranging from 2mm to 4mm. Aluminum
electrolytic capacitors can be used in cost-driven applica-
tions providing that consideration is given to ripple cur-
rent ratings, temperature and long term reliability. A
typical application will require several to many aluminum
electrolytic capacitors in parallel. A combination of the
above mentioned capacitors will often result in maximiz-
ing performance and minimizing overall cost. Other ca-
The selection of COUT is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The output ripple (∆VOUT) is determined by:
1
∆VOUT ≈ ∆IL ESR +
8fCOUT
Wheref=operatingfrequency,COUT =outputcapacitance,
and ∆IL= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.3IOUT(MAX) the output
ripple will typically be less than 50mV at the maximum VIN
assuming:
COUT Recommended ESR < 2 RSENSE
and COUT > 1/(8fRSENSE
)
pacitor types include Nichicon PL series, Panasonic SP,
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APPLICATIO S I FOR ATIO
U
NEC Neocap, Cornell Dubilier ESRE and Sprague 595D
series. Consult manufacturers for other specific recom-
mendations.
current drawn from the internal 3.3V linear regulator. To
prevent maximum junction temperature from being
exceeded, the input supply current must be checked
operating in continuous mode at maximum VIN.
INTVCC Regulator
EXTVCC Connection
An internal P-channel low dropout regulator produces 5V
at the INTVCC pin from the VIN supply pin. INTVCC powers
the drivers and internal circuitry within the IC. The INTVCC
pinregulatorcansupplyapeakcurrentof50mAandmust
be bypassed to ground with a minimum of 4.7µF tanta-
lum, 10µF special polymer, or low ESR type electrolytic
capacitor. A 1µF ceramic capacitor placed directly adja-
cent to the INTVCC and PGND IC pins is highly recom-
mended. Good bypassing is necessary to supply the high
transient currents required by the MOSFET gate drivers
and to prevent interaction between channels.
The IC contains an internal P-channel MOSFET switch
connected between the EXTVCC and INTVCC pins. When
the voltage applied to EXTVCC rises above 4.7V, the inter-
nal regulator is turned off and the switch closes, connect-
ing the EXTVCC pin to the INTVCC pin thereby supplying
internal power. The switch remains closed as long as the
voltage applied to EXTVCC remains above 4.5V. This
allows the MOSFET driver and control power to be derived
from the output during normal operation (4.7V < VOUT
<
7V) and from the internal regulator when the output is out
of regulation (start-up, short-circuit). If more
current is required through the EXTVCC switch than is
specified, an external Schottky diode can be added be-
tween the EXTVCC and INTVCC pins. Do not apply greater
than 7V to the EXTVCC pin and ensure that EXTVCC < VIN.
Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the IC to be ex-
ceeded. The system supply current is normally dominated
by the gate charge current. Additional external loading of
the INTVCC and 3.3V linear regulators also needs to be
taken into account for the power dissipation calculations.
The total INTVCC current can be supplied by either the 5V
internal linear regulator or by the EXTVCC input pin. When
the voltage applied to the EXTVCC pin is less than 4.7V, all
of the INTVCC current is supplied by the internal 5V linear
regulator. Power dissipation for the IC in this case is
highest: (VIN)(IINTVCC), and overall efficiency is lowered.
The gate charge current is dependent on operating fre-
quency as discussed in the Efficiency Considerations
section. The junction temperature can be estimated by
using the equations given in Note 2 of the Electrical
Characteristics. For example, the IC VIN current is ther-
mally limited to less than 67mA from a 24V supply when
not using the EXTVCC pin as follows:
Significant efficiency gains can be realized by powering
INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
supply means connecting the EXTVCC pin directly to VOUT
.
However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTVCC power
from the output.
The following list summarizes the four possible connec-
tions for EXTVCC:
1. EXTVCCLeftOpen(orGrounded).ThiswillcauseINTVCC
to be powered from the internal 5V regulator resulting in
an efficiency penalty of up to 10% at high input voltages.
2. EXTVCC Connected directly to VOUT. This is the normal
connection for a 5V regulator and provides the highest
efficiency.
TJ = 70°C + (67mA)(24V)(34°C/W) = 125°C
UseoftheEXTVCC inputpinreducesthejunctiontempera-
ture to:
3. EXTVCC Connected to an External supply. If an external
supply is available in the 5V to 7V range, it may be used to
powerEXTVCC providingitiscompatiblewiththeMOSFET
gate drive requirements.
TJ = 70°C + (67mA)(5V)(34°C/W) = 81°C
The absolute maximum rating for the INTVCC Pin is 40mA.
Dissipationshouldbecalculatedtoalsoincludeanyadded
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APPLICATIO S I FOR ATIO
4. EXTVCC Connected to an Output-Derived Boost Net-
work. For3.3Vandotherlowvoltageregulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than4.7V. This can bedonewitheithertheinductiveboost
winding as shown in Figure 6a or the capacitive charge
pump shown in Figure 6b. The charge pump has the
advantage of simple magnetics.
Output Voltage
The output voltages are each set by an external feedback
resistivedividercarefullyplacedacrosstheoutput capaci-
tor. The resultant feedback signal is compared with the
internal precision 0.800V voltage reference by the error
amplifier. The output voltage is given by the equation:
R2
R1
VOUT = 0.8V 1+
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors CB connected to the BOOST
pinssupplythegatedrivevoltagesforthetopsideMOSFETs.
Capacitor CB in the functional diagram is charged though
external diode DB from INTVCC when the SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the CB voltage across the gate-source of the
desiredMOSFET.ThisenhancestheMOSFETandturnson
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
where R1 and R2 are defined in Figure 2.
SENSE+/SENSE– Pins
The common mode input range of the current comparator
sense pins is from 0V to (1.1)INTVCC. Continuous linear
operation is guaranteed throughout this range allowing
output voltage setting from 0.8V to 7.7V, depending upon
the voltage applied to EXTVCC. A differential NPN input
stage is biased with internal resistors from an internal
2.4V source as shown in the Functional Diagram. This
requires that current either be sourced or sunk from the
SENSE pins depending on the output voltage. If the output
voltage is below 2.4V current will flow out of both SENSE
pinstothemainoutput.Theoutputcanbeeasilypreloaded
bythe VOUT resistive dividerto compensateforthe current
comparator’s negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:
on, the boost voltage is above the input supply: VBOOST
=
VIN + VINTVCC. The value of the boost capacitor CB needs
to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the exter-
nal Schottky diode must be greater than VIN(MAX). When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the
input current decreases, then the efficiency has improved.
If there is no change in input current, then there is no
change in efficiency.
ISENSE+ + ISENSE– = (2.4V – VOUT)/24k
+
V
V
IN
IN
1µF
OPTIONAL EXTV
CONNECTION
CC
+
+
5V < V
< 7V
SEC
C
C
IN
IN
0.22µF
BAT85
BAT85
BAT85
BAT 85
V
V
V
SEC
IN
IN
LTC3728L/
LTC3728LX
LTC3728L/
LTC3728LX
+
+
1µF
VN2222LL
TG1
SW
TG1
SW
R
R
SENSE
SENSE
N-CH
N-CH
N-CH
N-CH
V
OUT
V
OUT
L1
T1
1:N
EXTV
EXTV
CC
CC
R6
R5
+
C
C
FCB
BG1
OUT
BG1
OUT
SGND
PGND
PGND
3728 F06b
3728 F06a
Figure 6b. Capacitive Charge Pump for EXTVCC
Figure 6a. Secondary Output Loop & EXTVCC Connection
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SinceVOSENSE isservoedtothe0.8Vreferencevoltage, we
can choose R1 in Figure 2 to have a maximum value to
absorb this current.
U
V
INTV
IN
CC
R
3.3V OR 5V
RUN/SS
*
R
*
SS
SS
D1
RUN/SS
C
SS
0.8V
2.4V – VOUT
C
SS
R1
= 24k
(MAX)
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
(a)
3728 F07
(b)
for VOUT < 2.4V
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32k. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the
Figure 7. RUN/SS Pin Interfacing
ramp up slowly providing the soft-start function. Each
RUN/SS pin has an internal 6V zener clamp (See Func-
tional Diagram).
V
OSENSE feedback current.
Soft-Start/Run Function
Fault Conditions: Overcurrent Latchoff
The RUN/SS1 and RUN/SS2 pins are multipurpose pins
that provide a soft-start function and a means to shut
down the LTC3728L/LTC3728LX. Soft-start reduces the
input power source’s surge currents by gradually increas-
ing the controller’s current limit (proportional to VITH).
This pin can also be used for power supply sequencing.
The RUN/SS pins also provide the ability to latch off the
controller(s) when an overcurrent condition is detected.
The RUN/SS capacitor, CSS, is used initially to turn on and
limit the inrush current. After the controller has been
started and been given adequate time to charge up the
outputcapacitorandprovidefullloadcurrent, theRUN/SS
capacitorisusedforashort-circuittimer. Iftheregulator’s
output voltage falls to less than 70% of its nominal value
after CSS reaches 4.1V, CSS begins discharging on the
assumption that the output is in an overcurrent condition.
If the condition lasts for a long enough period as deter-
mined by the size of the CSS and the specified discharge
current, the controller will be shut down until the RUN/SS
pin voltage is recycled. If the overload occurs during start-
up, the time can be approximated by:
An internal 1.2µA current source charges up the CSS
capacitor. When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.5V
to 3.0V, the internal current limit is increased from 25mV/
RSENSE to 75mV/RSENSE. The output current limit ramps
up slowly, taking an additional 1.25s/µF to reach full
current. The output current thus ramps up slowly, reduc-
ing the starting surge current required from the input
power supply. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:
tLO1 ≈ [CSS(4.1 – 1.5 + 4.1 – 3.5)]/(1.2µA)
= 2.7 • 106 (CSS)
1.5V
1.2µA
If the overload occurs after start-up the voltage on CSS will
begin discharging from the zener clamp voltage:
tDELAY
=
=
CSS = 1.25s /µF CSS
(
)
t
LO2 ≈ [CSS (6 – 3.5)]/(1.2µA) = 2.1 • 106 (CSS)
3V − 1.5V
1.2µA
t
CSS = 1.25s /µF CSS
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin as shown
in Figure 7. This resistance shortens the soft-start period
and prevents the discharge of the RUN/SS capacitor
during an over current condition. Tying this pull-up resis-
tor to VIN, as in Figure 7a, defeats overcurrent latchoff.
IRAMP
(
)
By pulling both RUN/SS pins below 1V, the IC is put into
low current shutdown (IQ = 20µA). The RUN/SS pins can
be driven directly from logic as shown in Figure 7. Diode
D1 in Figure 7 reduces the start delay but allows CSS to
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Diode-connecting this pull-up resistor to INTVCC, as in
Figure 7b, eliminates any extra supply current during
controller shutdown while eliminating the INTVCC loading
from preventing controller start-up.
∆IL(SC) = tON(MIN) (VIN/L)
The resulting short-circuit current is:
25mV
RSENSE
1
2
ISC
=
– ∆IL(SC)
Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem
with noise pickup or poor layout causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature.
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.
The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
A comparator monitors the output for overvoltage condi-
tions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
off and the bottomMOSFET is turnedon untilthe overvolt-
age condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
thereforeallowaswitchingregulatorsystemhavingapoor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if VOUT returns to a safe level,
normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
open the system fuse. The switching regulator will regu-
late properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.
CSS > (COUT )(VOUT) (10–4) (RSENSE
)
The minimum recommended soft-start capacitor of
CSS = 0.1µF will be sufficient for most applications.
Fault Conditions: Current Limit and Current Foldback
The current comparators have a maximum sense voltage
of 75mV resulting in a maximum MOSFET current of
75mV/RSENSE. The maximum value of current limit gener-
ally occurs with the largest VIN at the highest ambient
temperature, conditions that cause the highest power
dissipation in the top MOSFET.
Each controller includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is overridden. If the
outputfallsbelow70%ofitsnominaloutputlevel,thenthe
maximum sense voltage is progressively lowered from
75mV to 25mV. Under short-circuit conditions with very
low duty cycles, the controller will begin cycle skipping in
order to limit the short-circuit current. In this situation the
bottom MOSFET will be dissipating most of the power but
less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time tON(MIN) of
each controller (typically 100ns), the input voltage and
inductor value:
Phase-Locked Loop and Frequency Synchronization
The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external source. The frequency range of the
voltage controlled oscillator is ±50% around the center
frequency fO. A voltage applied to the PLLFLTR pin of 1.2V
corresponds to a frequency of approximately 400kHz. The
nominal operating frequency range of the IC is 260kHz to
550kHz.
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The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆fH, is equal to the capture range, ∆fC:
U
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that each controller is capable of turning on the top
MOSFET. Itisdeterminedbyinternaltimingdelaysandthe
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
∆fH = ∆fC = ±0.5 fO (260kHz-550kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 7.
VOUT
V (f)
IN
tON(MIN)
<
Ifthedutycyclefallsbelowwhatcanbeaccommodatedby
the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
If the external frequency (fPLLIN) is greater than the oscil-
lator frequency f0SC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f0SC, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal fre-
quencies are the same but exhibit a phase difference, the
currentsourcesturnonforanamountoftimecorrespond-
ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
openandthefiltercapacitorCLP holdsthevoltage.TheIC’s
PLLIN pin must be driven from a low impedance source
such as a logic gate located close to the pin. When using
multiple ICs for a phase-locked system, the PLLFLTR pin
of the master oscillator should be biased at a voltage that
willguaranteetheslaveoscillator(s)abilitytolockontothe
master’s frequency. A DC voltage of 0.7V to 1.7V applied
to the master oscillator’s PLLFLTR pin is recommended in
order to meet this requirement. The resultant operating
frequency can range from 300kHz to 500kHz.
Theminimumon-timeforeachcontrollerisapproximately
100ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases up to about 150ns.
This is of particular concern in forced continuous applica-
tions with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with
correspondingly larger current and voltage ripple.
FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced on
both controllers when the FCB pin drops below 0.8V.
During continuous mode, current flows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
When primary load currents are low and/or the VIN/VOUT
ratio is low, the synchronous switch may not be on for a
sufficient amount of time to transfer power from the
outputcapacitortothesecondaryload.Forcedcontinuous
operationwillsupportsecondarywindingsprovidingthere
is sufficient synchronous switch duty factor. Thus, the
FCB input pin removes the requirement that power must
be drawn from the inductor primary in order to extract
The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP =10kΩ and CLP is 0.01µF to
0.1µF.
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APPLICATIO S I FOR ATIO
power from the auxiliary windings. With the loop in
continuous mode, the auxiliary outputs may nominally be
loaded without regard to the primary output load.
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added to
either or both controllers by loading the ITH pin with a
resistive divider having a Thevenin equivalent voltage
source equal to the midpoint operating voltage range of
the error amplifier, or 1.2V (see Figure 8).
The secondary output voltage VSEC is normally set as
shown in Figure 6a by the turns ratio N of the transformer:
VSEC (N + 1) VOUT
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application. A
complete explanation is included in Design Solutions 10.
(See www.linear-tech.com)
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then VSEC will droop. An external resistive divider from
VSEC to the FCB pin sets a minimum voltage VSEC(MIN)
:
R6
R5
VSEC(MIN) ≈ 0.8V 1+
INTV
CC
where R5 and R6 are shown in Figure 2.
R
T2
T1
I
TH
If VSEC drops below this level, the FCB voltage forces
temporary continuous switching operation until VSEC is
again above its minimum.
LTC3728L/
LTC3728LX
R
R
C
C
C
3728 F08
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.18µA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
Figure 8. Active Voltage Positioning
Applied to the LTC3728L/LTC3728LX
Efficiency Considerations
The following table summarizes the possible states avail-
able on the FCB pin:
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
Table 1
FCB Pin
Condition
0V to 0.75V
Forced Continuous Both Controllers
(Current Reversal Allowed—
Burst Inhibited)
0.85V < V < 4.3V
Minimum Peak Current Induces
Burst Mode Operation
FCB
%Efficiency = 100% – (L1 + L2 + L3 + ...)
No Current Reversal Allowed
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Feedback Resistors
>4.8V
Regulating a Secondary Winding
Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
lossesinLTC3728L/LTC3728LXcircuits:1)ICVIN current
(including loading on the 3.3V internal regulator), 2)
INTVCCregulatorcurrent,3)I2Rlosses,4)TopsideMOSFET
transition losses.
No Minimum Peak Current
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
1. The VIN current has two components: the first is the DC
supply current given in the Electrical Characteristics table,
3728lxfa
22
LTC3728L/LTC3728LX
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APPLICATIO S I FOR ATIO
U
which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output.VINcurrenttypicallyresultsinasmall(<0.1%)loss.
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTVCC to
ground. The resulting dQ/dt is a current out of INTVCC that
is typically much larger than the control circuit current. In
continuous mode, IGATECHG =f(QT+QB), where QT and QB
are the gate charges of the topside and bottom side
MOSFETs.
2
)
IMAX
2
Transition Loss = V
•
RDR
(
•
(
IN
)
1
1
CMILLER
(
f
+
)( )
5V – VTH VTH
Other “hidden” losses such as copper trace and internal
batteryresistancescanaccountforanadditional5%to10%
efficiencydegradationinportablesystems.Itisveryimpor-
tant to include these “system” level losses during the de-
signphase. Theinternalbatteryandfuseresistancelosses
can be minimized by making sure that CIN has adequate
chargestorageandverylowESRattheswitchingfrequency.
A 25W supply will typically require a minimum of 20µF to
40µFofcapacitancehavinga maximumof20mΩto50mΩ
ofESR.TheLTC3728L2-phasearchitecturetypicallyhalves
this input capacitance requirement over competing solu-
tions. Other losses including Schottky conduction losses
during dead-time and inductor core losses generally ac-
count for less than 2% total additional loss.
SupplyingINTVCC powerthroughtheEXTVCC switchinput
from an output-derived source will scale the VIN current
required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTVCC current results in approxi-
mately2.5mAofVIN current. Thisreducesthemid-current
loss from 10% or more (if the driver was powered directly
from VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and RSENSE
,
Checking Transient Response
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same RDS(ON), then the resistance of one
MOSFET can simply be summed with the resistances of L,
RSENSE and ESR to obtain I2R losses. For example, if each
RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE = 10mΩ and RESR
= 40mΩ (sum of both input and output capacitance
losses), thenthetotalresistance is 130mΩ. Thisresults in
losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Efficiency varies as the inverse
square of VOUT for the same external components and
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
3728lxfa
23
LTC3728L/LTC3728LX
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APPLICATIO S I FOR ATIO
truly reflects the closed loop response. Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.
should be controlled so that the load rise time is limited to
approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current to
about 200mA.
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserveorevenrechargebatterypacksduringoperation.
But before you connect, be advised: you are plugging into
thesupplyfromhell. Themainpowerlineinanautomobile
is the source of a number of nasty potential transients,
including load-dump, reverse-battery, and double-bat-
tery.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80% of
full-load current having a rise time of 1µs to 10µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
why it is better to look at the ITH pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing RC and the bandwidth of the loop will be
increased by decreasing CC. If RC is increased by the same
factor that CC is decreased, the zero frequency will be kept
the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
outputvoltagesettlingbehaviorisrelatedtothestabilityof
the closed-loop system and will demonstrate the actual
overall supply performance.
Load-dump is the result of a loose battery cable. When the
cablebreaksconnection,thefieldcollapseinthealternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
ThenetworkshowninFigure9isthemoststraightforward
approach to protect a DC/DC converter from the ravages
of an automotive power line. The series diode prevents
current from flowing during reverse-battery, while the
transient suppressor clamps the input voltage during
load-dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamptheinputvoltagebelowbreakdownoftheconverter.
Although the LTC3728L/LTC3728LX have a maximum
input voltage of 30V, most applications will also be limited
to 30V by the MOSFET BVDSS.
50A I RATING
PK
V
IN
12V
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than1:50, the switch rise time
LTC3728L/
LTC3728LX
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
3728 F09
Figure 9. Automotive Application Protection
3728lxfa
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LTC3728L/LTC3728LX
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APPLICATIO S I FOR ATIO
U
Design Example
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
As a design example for one channel, assume VIN
=
12V(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A,
and f = 300kHz.
The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Fairchild FDS6982S dual
MOSFET results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER
=
Theinductancevalueischosenfirstbasedona30%ripple
current assumption. The highest value of ripple current
occursatthemaximuminputvoltage. TiethePLLFLTRpin
to a resistive divider from the INTVCC pin, generating 0.7V
for 300kHz operation. The minimum inductance for 30%
ripple current is:
215pF. At maximum input voltage with T(estimated) =
50°C:
2
( )
1.8V
22V
PMAIN
=
5 1+(0.005)(50°C – 25°C) •
[
]
2
5A
2
0.035Ω + 22V
4Ω 215pF •
VOUT
(f)(L)
VOUT
V
IN
(
) (
)
(
)(
)
∆IL =
1–
1
1
+
300kHz = 332mW
(
)
A 4.7µH inductor will produce 23% ripple current and a
3.3µH will result in 33%. The peak inductor current will be
the maximum DC value plus one half the ripple current, or
5.84A, for the 3.3µH value. Increasing the ripple current
will also help ensure that the minimum on-time of 100ns
is not violated. The minimum on-time occurs at maximum
VIN:
5 – 2.3 2.3
Ashort-circuittogroundwillresultinafoldedbackcurrent
of:
25mV 1 120ns(22V)
ISC
=
–
= 2.1A
0.01Ω 2
3.3µH
VOUT
1.8V
withatypicalvalueofRDS(ON)andδ=(0.005/°C)(20)=0.1.
The resulting power dissipated in the bottom MOSFET is:
tON(MIN)
=
=
= 273ns
V
IN(MAX)f 22V(300kHz)
22V – 1.8V
22V
= 100mW
2
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
PSYNC
=
2.1A 1.125 0.022Ω
(
) (
)(
)
which is less than under full-load conditions.
60mV
5.84A
RSENSE
≤
≈ 0.01Ω
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pin’s specified input
current.
VORIPPLE = RESR (∆IL) = 0.02Ω(1.67A) = 33mVP–P
0.8V
R1(MAX) = 24k
2.4V – VOUT
0.8V
2.4V – 1.8V
= 24k
= 32k
3728lxfa
25
LTC3728L/LTC3728LX
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APPLICATIO S I FOR ATIO
PC Board Layout Checklist
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
CINTVCC must return to the combined COUT (–) terminals.
The path formed by the top N-channel MOSFET, Schottky
diode and the CIN capacitor should have short leads and
PC trace lengths. The output capacitor (–) terminals
should be connected as close as possible to the (–)
terminals of the input capacitor by placing the capacitors
next to each other and away from the Schottky loop
described above.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. These items are also illustrated graphically in the
layout diagram of Figure 10. The Figure 11 illustrates the
current waveforms present in the various branches of the
2-phasesynchronousregulatorsoperatinginthecontinu-
ous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at CIN? Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
3. Do the LTC3728L/LTC3728LX VOSENSE pins’ resistive
dividersconnecttothe(+)terminalsofCOUT?Theresistive
divider must be connected between the (+) terminal of
R
PU
V
PULL-UP
(<7V)
PGOOD
RUN/SS1
PGOOD
TG1
L1
R
SENSE
D1
+
V
SENSE1
OUT1
–
SENSE1
SW1
R2
C
B1
R1
M1
M2
V
BOOST1
OSENSE1
PLLFLTR
PLLIN
FCB
V
IN
BG1
EXTV
f
IN
C
C
OUT1
1µF
R
IN
CERAMIC
INTV
CC
CC
C
VIN
GND
LTC3728L/LTC3728LX
INTV
I
TH1
CC
C
IN
V
IN
C
INTVCC
SGND
PGND
BG2
OUT2
D2
1µF
CERAMIC
3.3V
3.3V
OUT
M4
M3
I
BOOST2
SW2
TH2
C
B2
V
OSENSE2
–
R
R3
R4
SENSE
V
SENSE2
SENSE2
TG2
OUT2
L2
+
RUN/SS2
3728 F10
Figure 10. LTC3728L/LTC3728LX Recommended Printed Circuit Layout Diagram
3728lxfa
26
LTC3728L/LTC3728LX
W U U
APPLICATIO S I FOR ATIO
U
SW1
L1
R
SENSE1
V
OUT1
+
D1
CERAMIC
C
OUT1
R
L1
V
IN
R
IN
+
C
IN
SW2
L2
R
SENSE2
V
OUT2
+
D2
C
OUT2
R
L2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
CERAMIC
3728 F11
Figure 11. Branch Current Waveforms
COUT and signal ground. The R2 and R4 connections
should not be along the high current input feeds from the
input capacitor(s).
An additional 1µF ceramic capacitor placed immediately
next to the INTVCC and PGND pins can help improve noise
performance substantially.
4. Are the SENSE – and SENSE+ leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE+ and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the SENSE resistor.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the LTC3728L/LTC3728LX and occupy minimum PC
trace area.
5. Is the INTVCC decoupling capacitor connected close to
the IC, between the INTVCC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
3728lxfa
27
LTC3728L/LTC3728LX
U
W
U U
APPLICATIO S I FOR ATIO
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
Short-circuit testing can be performed to verify proper
overcurrent latchoff, or 5µA can be provided to the RUN/
SS pin(s) by resistorsfromVIN toprevent theshort-circuit
latchoff from occurring.
ReduceVIN fromitsnominalleveltoverifyoperationofthe
regulator in dropout. Check the operation of the under-
voltage lockout circuit by further lowering VIN while moni-
toring the outputs to verify operation.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the appli-
cation. The frequency of operation should be maintained
over the input voltage range down to dropout and until the
output load drops below the low current operation thresh-
old—typically 10% to 20% of the maximum designed
current level in Burst Mode operation.
Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If prob-
lems coincide with high input voltages and low output
currents,lookforcapacitivecouplingbetweentheBOOST,
SW, TG, and possibly BG connections and the sensitive
voltage and current pins. The capacitor placed across the
current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due to
high frequency capacitive coupling. If problems are en-
countered with high current output loading at lower input
voltages,lookforinductivecouplingbetweenCIN,Schottky
and the top MOSFET components to the sensitive current
and voltage sensing traces. In addition, investigate com-
mon ground path voltage pickup between these compo-
nents and the SGND pin of the IC.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Over-
compensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for its individual
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current com-
parator trip point when the other channel is turning on its
topMOSFET. Thisoccursaround50%dutycycleoneither
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
Theoutputvoltageunderthisimproperhookupwillstillbe
maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
3728lxfa
28
LTC3728L/LTC3728LX
U
TYPICAL APPLICATIO S
59k
1M
100k
MBRS1100T3
V
+
PULL-UP
33µF
25V
(<7V)
T1, 1:1.8
10µH
PGOOD
TG1
PGOOD
RUN/SS1
0.015Ω
V
0.1µF
OUT1
5V
+
SENSE1
M1
3A; 4A PEAK
180pF
1000pF
8
–
SW1
SENSE1
105k, 1%
5
20k
1%
Q1
Q2
0.1µF
LT1121
ON/OFF
BOOST1
D1
V
OSENSE1
3
2
1
220k
V
OUT3
V
IN
PLLFLTR
PLLIN
FCB
12V
120mA
150µF, 6.3V
PANASONIC SP
BG1
+
33pF
1µF
25V
10Ω
22µF
50V
100k
CMDSH-3TR
EXTV
CC
0.1µF
GND
LTC3728L/LTC3728LX
INTV
I
CC
TH1
1µF
10V
15k
4.7µF
180µF, 4V
PANASONIC SP
1000pF
1000pF
V
PGND
BG2
SGND
IN
7V TO
28V
33pF
M2
CMDSH-3TR
3.3V
3.3V
OUT
Q3
Q4
D2
BOOST2
SW2
I
TH2
15k
0.1µF
V
OSENSE2
20k
1%
V
OUT2
3.3V
5A; 6A PEAK
–
TG2
SENSE2
SENSE2
63.4k
1%
0.01Ω
1000pF
L1
6.3µH
+
RUN/SS2
180pF
0.1µF
3728 F12
V
V
: 7V TO 28V
IN
: 5V, 3A/3.3V, 6A/12V, 150mA
OUT
SWITCHING FREQUENCY = 250kHz
MI, M2: FDS6982S OR VISHAY Si4810DY
L1: SUMIDA CEP123-6R3MC
T1: 10µH 1:1.8 — DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID
Figure 12. LTC3728L/LTC3728LX High Efficiency Low Noise 5V/3A, 3.3V/5A, 12V/120mA Regulator
3728lxfa
29
LTC3728L/LTC3728LX
U
TYPICAL APPLICATIO S
V
PULL-UP
(<7V)
L1
4.3µH
RUN/SS1
PGOOD
TG1
PGOOD
0.008Ω
0.1µF
V
+
OUT1
5V/4A
SENSE1
180pF
1000pF
105k
1%
–
SENSE1
SW1
20k
1%
0.1µF
Q1
Q2
V
BOOST1
OSENSE1
PIN 4
M1
PLLFLTR
PLLIN
FCB
V
0.01µF
1µF50V
IN
10k
1000pF
f
SYNC
BG1
100pF
10Ω
22µF
50V
CMDSH-3TR
EXTV
CC
150µF, 6.3V
180µF, 4V
0.1µF
GND
LTC3728L/LTC3728LX
INTV
I
TH1
CC
1µF50V
8.06k
1µF
4.7µF, 10V
1500pF
1000pF
SGND
PGND
BG2
V
100pF
IN
CMDSH-3TR
7V TO
28V
3.3V
3.3V
OUT
PIN 4
I
BOOST2
SW2
Q3
Q4
TH2
4.75k
0.1µF
V
OSENSE2
–
20k
1%
M2
V
OUT2
SENSE2
TG2
3.3V/5A
0.008Ω
63.4k
1%
1000pF
L2
4.3µH
+
180pF
SENSE2
RUN/SS2
0.1µF
: 7V TO 28V
3728 F13
V
V
SWITCHING FREQUENCY = 250kHz TO 550kHz
M1, M2: FDS6982S OR VISHAY Si4810DY
L1, L2: SUMIDA CDEP105-4R3MC-88
OUTPUT CAPACITORS: PANASONIC SP SERIES
IN
: 5V, 4A/3.3V, 5A
OUT
Figure 13. LTC3728L/LTC3728LX 5V/4A, 3.3V/5A Regulator with External Frequency Synchronization
3728lxfa
30
LTC3728L/LTC3728LX
U
PACKAGE DESCRIPTIO (For purposes of clarity, drawings are not to scale)
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.386 – .393*
(9.804 – 9.982)
.045 ±.005
.033
(0.838)
REF
28 27 26 25 24 23 22 21 20 19 18 17 1615
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 TYP
1
2
3
4
5
6
7
8
9
10 11 12 13 14
.004 – .009
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
.053 – .069
(1.351 – 1.748)
× 45°
(0.38 ± 0.10)
(0.102 – 0.249)
.0075 – .0098
(0.191 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN28 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
BOTTOM VIEW—EXPOSED PAD
0.57 ±0.05
R = 0.115
TYP
0.75 ± 0.05
0.40 ± 0.10
5.00 ± 0.10
(4 SIDES)
0.00 – 0.05
31 32
PIN 1
TOP MARK
1
2
5.35 ±0.05
4.20 ±0.05
3.45 ±0.05
(4 SIDES)
3.45 ± 0.10
(4-SIDES)
(UH) QFN 0102
0.200 REF
0.23 ± 0.05
0.50 BSC
PACKAGE
OUTLINE
0.23 ± 0.05
NOTE:
0.50 BSC
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
RECOMMENDED SOLDER PAD LAYOUT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
3728lxfa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
31
LTC3728L/LTC3728LX
U
TYPICAL APPLICATIO
I
IN
12V
IN
C
IN
I
I
*
IN
1
0°
BUCK: 2.5V/15A
BUCK: 2.5V/15A
OPEN
PHASMD TG1
180°
I
1
2
3
4
2.5V /30A
O
TG2
U1
LTC3729
I
I
90°
2
3
I
CLKOUT
I
I
1.5V /15A
O
90°
BUCK: 1.5V/15A
BUCK: 1.8V/15A
TG1
270°
1.8V /15A
O
U2
TG2
LTC3728L/
LTC3728LX
PLLIN
*INPUT RIPPLE CURRENT CANCELLATION
INCREASES THE RIPPLE FREQUENCY AND
REDUCES THE RMS INPUT RIPPLE CURRENT
THUS, SAVING INPUT CAPACITORS
I
90°
4
3728 F14
Figure 14. Multioutput PolyPhase Application
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Reduces C and C , Power Good Output Signal, Synchronizable,
LTC1628/LTC1628-PG/ 2-Phase, Dual Output Synchronous Step-Down
IN
OUT
LTC1628-SYNC
DC/DC Controller
20A to 200A PolyPhaseTM Synchronous Controllers
3.5V ≤ V ≤ 36V, I
up to 20A, 0.8V ≤ V
≤ 5V
IN
OUT
OUT
LTC1629/
LTC1629-PG
Expandable from 2-Phase to 12-Phase, Uses All
Surface Mount Components, No Heat Sink, V up to 36V
IN
LTC1702A
No R
2-Phase Dual Synchronous Step-Down
550kHz, No Sense Resistor
SENSE
Controller
LTC1708-PG
2-Phase, Dual Synchronous Controller with Mobile VID
3.5V ≤ V ≤ 36V, VID Sets V
, PGOOD
IN
OUT1
LT1709/
LT1709-8
High Efficiency, 2-Phase Synchronous Step-Down
Switching Regulators with 5-Bit VID
1.3V ≤ V
≤ 3.5V, Current Mode Ensures
OUT
Accurate Current Sharing, 3.5V ≤ V ≤ 36V
IN
LTC1735
High Efficiency Synchronous Step-Down
Switching Regulator
Output Fault Protection, 16-Pin SSOP
LTC1736
High Efficiency Synchronous Controller with 5-Bit Mobile Output Fault Protection, 24-Pin SSOP,
VID Control 3.5V ≤ V ≤ 36V
No R Current Mode Synchronous Step-Down
IN
LTC1778/LTC1778-1
Up to 97% Efficiency, 4V ≤ V ≤ 36V, 0.8V ≤ V
up to 20A
OUT
≤ (0.9)(V ),
OUT IN
SENSE
Controllers
IN
I
LTC1929/
LTC1929-PG
2-Phase Synchronous Controllers
Up to 42A, Uses All Surface Mount Components,
No Heat Sinks, 3.5V ≤ V ≤ 36V
IN
LTC3708
LTC3711
Dual, 2-Phase, DC/DC Controller with Output Tracking
Current Mode, No R
, Up/Down Tracking, Synchronizable
SENSE
No R
Current Mode Synchronous Step-Down
Up to 97% Efficiency, Ideal for Pentium® III Processors,
0.925V ≤ V ≤ 2V, 4V ≤ V ≤ 36V, I up to 20A
SENSE
Controller with Digital 5-Bit Interface
OUT
IN
OUT
LTC3728
LTC3729
LTC3731
Dual, 550kHz, 2-Phase Synchronous Step-Down
Controller
Dual 180° Phased Controllers, V 3.5V to 35V, 99% Duty Cycle,
IN
5x5QFN, SSOP-28
20A to 200A, 550kHz PolyPhase Synchronous Controller Expandable from 2-Phase to 12-Phase, Uses all Surface Mount
Components, V up to 36V
IN
3- to 12-Phase Step-Down Synchronous Controller
60A to 240A Output Current, 0.6V ≤ V ≤ 6V, 4.5V ≤ V ≤ 32V
OUT IN
No RSENSE and PolyPhase are trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.
3728lxfa
LT/TP 0104 1K REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
LINEAR TECHNOLOGY CORPORATION 2002
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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