LTC3736-2EGN#PBF [Linear]
IC 1 A SWITCHING CONTROLLER, 825 kHz SWITCHING FREQ-MAX, PDSO24, 0.150 INCH, LEAD FREE, PLASTIC, SSOP-24, Switching Regulator or Controller;
| 型号： | LTC3736-2EGN#PBF |
| 厂家： | 
Linear |
| 描述： | IC 1 A SWITCHING CONTROLLER, 825 kHz SWITCHING FREQ-MAX, PDSO24, 0.150 INCH, LEAD FREE, PLASTIC, SSOP-24, Switching Regulator or Controller 控制器 |
| 文件： | 总28页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3736-2
TM
Dual 2-Phase, No RSENSE
,
Synchronous Controller
with Output Tracking
U
FEATURES
DESCRIPTIO
TheLTC®3736-2isa2-phasedualsynchronousstep-down
switching regulator controller with tracking that drives ex-
ternalcomplementarypowerMOSFETsusingfewexternal
components. The constant frequency current mode archi-
tecture with MOSFET VDS sensing eliminates the need for
sense resistors and improves efficiency. Power loss and
noise due to the ESR of the input capacitance are mini-
mized by operating the two controllers out of phase.
■
No Current Sense Resistors Required
■
Out-of-Phase Controllers Reduce Required
Input Capacitance
Tracking Function
■
■
Wide VIN Range: 2.75V to 9.8V
■
0.6V ±1% Voltage Reference
■
High Current Limit
■
Constant Frequency Current Mode Operation
■
Low Dropout Operation: 100% Duty Cycle
Pulse-skipping operation provides high efficiency at light
loads. 100% duty cycle capability provides low dropout
operation, extending operating time in battery-powered
systems.
■
True PLL for Frequency Locking or Adjustment
■
Selectable Pulse-Skipping/Forced Continuous
Operation
■
Auxiliary Winding Regulation
■
■
■
■
■
Theswitchingfrequencycanbeprogrammedupto750kHz,
allowing the use of small surface mount inductors and ca-
pacitors. For noise sensitive applications, the LTC3736-2
switching frequency can be externally synchronized from
250kHz to 850kHz. An internal soft-start, which can be
lengthened externally, smoothly ramps the output voltage
during start-up.
Internal Soft-Start Circuitry
Power-Good Output Voltage Monitor
Output Overvoltage Protection
Micropower Shutdown: IQ = 9µA
Tiny Low Profile (4mm × 4mm) QFN and Narrow
SSOP Packages U
APPLICATIO S
The LTC3736-2 is available in the tiny thermally enhanced
(4mm × 4mm) QFN and 24-lead narrow SSOP packages.
■
One or Two Lithium-Ion Powered Devices
Notebook and Palmtop Computers, PDAs
Portable Instruments
Distributed DC Power Systems
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
No R
is a trademark of Linear Technology Corporation. All other trademarks are the
SENSE
■
property of their respective owners. Protected by U.S. Patents, including 5481178,
5929620, 6144194, 6580258, 6304066, 6611131, 6498466.
■
U
TYPICAL APPLICATIO
Efficiency and Power Loss
vs Load Current (Figure 15 Circuit)
High Efficiency, 2-Phase, Dual Synchronous DC/DC Step-Down Converter
V
IN
2.75V TO 9.8V
100
95
90
85
80
75
70
65
60
55
50
10
V
OUT
= 2.5V
10µF
×2
V
+
IN
+
SENSE1 SENSE2
EFFICIENCY
1
TG1
TG2
2.2µH
2.2µH
SW1
SW2
LTC3736-2
0.1
0.01
0.001
POWER LOSS
BG1
BG2
PGND
PGND
118k
187k
V
OUT1
2.5V
V
OUT2
1.8V
V
FB1
V
FB2
I
I
TH1
TH2
220pF
15k
220pF
59k
SGND
47µF
47µF
1
10
100
1000
10000
15k
59k
LOAD CURRENT (mA)
37362 TA01b
37362 TA01a
37362fa
1
LTC3736-2
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
PGOOD ..................................................... –0.3V to 10V
TG1, TG2, BG1, BG2 Peak Output Current (<10µs) ..... 1A
Operating Temperature Range (Note 2) ... –40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
Junction Temperature (Note 3) ............................ 125°C
Lead Temperature (Soldering, 10 sec)
Input Supply Voltage (VIN) ........................ –0.3V to 10V
PLLLPF, RUN/SS, SYNC/FCB,
TRACK, SENSE1+, SENSE2+,
IPRG1, IPRG2 Voltages................. –0.3V to (VIN + 0.3V)
VFB1, VFB2, ITH1, ITH2 Voltages .................. –0.3V to 2.4V
SW1, SW2 Voltages ............ –2V to VIN + 1V or 10V Max
(LTC3736EGN-2) .................................................. 300°C
W U
/O
PACKAGE RDER I FOR ATIO
TOP VIEW
TOP VIEW
+
1
2
SENSE1
PGND
BG1
24
23
22
21
20
19
18
17
16
15
14
13
SW1
IPRG1
24 23 22 21 20 19
3
V
FB1
TH1
I
1
2
3
4
5
6
18 SYNC/FCB
TH1
4
SYNC/FCB
TG1
I
IPRG2
PLLLPF
SGND
TG1
17
16
5
IPRG2
PLLLPF
SGND
PGND
25
6
PGND
TG2
15 TG2
7
V
14 RUN/SS
13 BG2
IN
8
RUN/SS
BG2
TRACK
V
IN
9
TRACK
7
8
9 10 11 12
10
11
12
PGND
V
FB2
TH2
+
SENSE2
I
SW2
PGOOD
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
GN PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 25) IS PGND
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 130°C/ W
ORDER PART NUMBER
LTC3736EGN-2
ORDER PART NUMBER
LTC3736EUF-2
UF PART MARKING
37362
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications that apply over the full operating temperature
range, otherwise specifications are at T = 25°C. V = 4.2V unless otherwise specified.
A
IN
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
Input DC Supply Current
Normal Mode
Shutdown
(Note 4)
RUN/SS = V
RUN/SS = 0V
475
9
3
750
20
10
µA
µA
µA
IN
UVLO
V
IN
= UVLO Threshold –200mV
Undervoltage Lockout Threshold
V
IN
V
IN
Falling
Rising
●
●
1.95
2.15
2.25
2.45
2.55
2.75
V
V
37362fa
2
LTC3736-2
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications that apply over the full operating temperature
range, otherwise specifications are at T = 25°C. V = 4.2V unless otherwise specified.
A
IN
PARAMETER
CONDITIONS
MIN
0.45
0.4
TYP
0.65
0.7
MAX
0.85
1
UNITS
V
Shutdown Threshold at RUN/SS
Start-Up Current Source
Regulated Feedback Voltage
RUN/SS = 0V
µA
0°C to 85°C (Note 5)
–40°C to 85°C
0.594
0.591
0.6
0.6
0.606
0.609
V
V
●
Output Voltage Line Regulation
Output Voltage Load Regulation
2.75V < V < 9.8V (Note 5)
0.05
0.2
mV/V
IN
I
I
= 0.9V (Note 5)
= 1.7V
0.12
–0.12
0.5
–0.5
%
%
TH
TH
V
Input Current
(Note 5)
10
10
50
50
nA
nA
V
FB1,2
TRACK Input Current
TRACK = 0.6V
Measured at V
Overvoltage Protect Threshold
Overvoltage Protect Hysteresis
Auxiliary Feedback Threshold
Top Gate (TG) Drive 1, 2 Rise Time
Top Gate (TG) Drive 1, 2 Fall Time
Bottom Gate (BG) Drive 1, 2 Rise Time
Bottom Gate (BG) Drive 1, 2 Fall Time
0.66
0.68
20
0.7
FB
mV
V
SYNC/FCB Ramping Positive
C = 3000pF
0.525
0.6
40
0.675
ns
ns
ns
ns
L
C = 3000pF
L
40
C = 3000pF
L
50
C = 3000pF
L
40
Maximum Current Sense Voltage (∆V
)
IPRG = Floating
IPRG = 0V
●
●
●
220
150
320
240
167
345
260
185
370
mV
mV
mV
SENSE(MAX)
+
(SENSE – SW)
IPRG = V
IN
Soft-Start Time
Time for V to Ramp from 0.05V to 0.55V
0.667
0.833
1
ms
FB1
Oscillator and Phase-Locked Loop
Oscillator Frequency
Unsynchronized (SYNC/FCB Not Clocked)
PLLLPF = Floating
480
260
650
550
300
750
600
340
825
kHz
kHz
kHz
PLLLPF = 0V
PLLLPF = V
IN
Phase-Locked Loop Lock Range
SYNC/FCB Clocked
Minimum Synchronizable Frequency
Maximum Synchronizable Frequency
●
●
200
1150
250
kHz
kHz
850
Phase Detector Output Current
Sinking
f
f
> f
< f
–4
4
µA
µA
OSC
OSC
SYNC/FCB
SYNC/FCB
Sourcing
PGOOD Output
PGOOD Voltage Low
PGOOD Trip Level
I
Sinking 1mA
125
mV
PGOOD
V
with Respect to Set Output Voltage
FB
V
FB
V
FB
V
FB
V
FB
< 0.6V, Ramping Positive
< 0.6V, Ramping Negative
> 0.6V, Ramping Negative
> 0.6V, Ramping Positive
–13
–16
7
–10.0
–13.3
10.0
–7
–10
13
%
%
%
%
10
13.3
16
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3736E-2 is guaranteed to meet specified performance
from 0°C to 85°C. Specifications over the –40°C to 85°C operating range
are assured by design, characterization and correlation with statistical
process controls.
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 5: The LTC3736-2 is tested in a feedback loop that servos I to a
TH
specified voltage and measures the resultant V voltage.
FB
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as shown in Figure 1.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
T = T + (P • θ °C/W)
J
A
D
JA
37362fa
3
LTC3736-2
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
U W
Load Step
(Forced Continuous Mode)
Efficiency and Power Loss
vs Load Current
100
95
90
85
80
75
70
65
60
55
50
10
V
OUT
= 2.5V
V
OUT
AC-COUPLED
100mV/DIV
EFFICIENCY
1
0.1
0.01
0.001
POWER LOSS
I
L
2A/DIV
V
V
LOAD
SYNC/FCB = 0V
FIGURE 15 CIRCUIT
= 3.3V
100µs/DIV
37362 G03
IN
V
IN
V
IN
= 3.3V
= 5V
= 1.8V
OUT
I
= 300mA TO 3A
1
10
100
1000
10000
LOAD CURRENT (mA)
37362 G01
Light Load
(Pulse-Skipping Mode)
Light Load
(Forced Continuous Mode)
Load Step (Pulse-Skipping Mode)
V
OUT
AC-COUPLED
100mV/DIV
SW
5V/DIV
SW
5V/DIV
V
V
OUT
OUT
50mV/DIV
50mV/DIV
AC COUPLED
AC COUPLED
I
L
I
I
L
2A/DIV
L
2A/DIV
2A/DIV
37362 G02
37362 G05
V
V
I
= 5V
2.5µs/DIV
V
V
I
= 5V
2.5µs/DIV
V
V
I
= 3.3V
100µs/DIV
37362 G04
IN
OUT
IN
OUT
IN
OUT
= 2.5V
= 2.5V
= 1.8V
= 300mA
= 300mA
= 300mA TO 3A
LOAD
LOAD
LOAD
SYNC/FBC = V
SYNC/FCB = 0V
SYNC/FCB = V
IN
FIGURE 15 CIRCUIT
IN
FIGURE 15 CIRCUIT
FIGURE 15 CIRCUIT
Tracking Start-Up with Internal
Soft-Start (C = 0µF)
Tracking Start-Up with External
Soft-Start (C = 0.10µF)
Oscillator Frequency
vs Input Voltage
SS
SS
5
4
V
V
OUT1
OUT1
3
2.5V
2.5V
V
2
V
OUT2
OUT2
1.8V
500mV/
DIV
1.8V
500mV/
DIV
1
0
–1
–2
–3
–4
–5
37362 G06
V
= 5V
LOAD1
40ms/DIV
37362 G07
V
= 5V
LOAD1
200µs/DIV
= 1Ω
IN
IN
R
= R
= 1Ω
R
= R
LOAD2
LOAD2
FIGURE 15 CIRCUIT
FIGURE 15 CIRCUIT
2
6
8
9
3
4
5
7
10
INPUT VOLTAGE (V)
37368 G08
37362fa
4
LTC3736-2
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
U W
Maximum Current Sense Voltage
vs I Pin Voltage
Regulated Feedback Voltage
vs Temperature
Efficiency vs Load Current
TH
100
95
90
85
80
75
70
65
60
55
50
100
80
60
40
20
0
0.606
0.605
0.604
0.603
0.602
0.601
0.600
0.599
0.598
0.597
0.596
0.595
0.594
FORCED CONTINUOUS
MODE
PULSE-SKIPPING
MODE
FIGURE 15 CIRCUIT
V
V
= 3.3V
IN
OUT
= 2.5V
PULSE-SKIPPING
MODE
(SYNC/FCB = V
)
IN
FORCED
CONTINUOUS
(SYNC/FCB = 0V)
–20
0.5
1
1.5
VOLTAGE (V)
2
1
10
100
1000
10000
20 40
–60 –40 –20
TEMPERATURE (°C)
0
60 80 100
I
TH
LOAD CURRENT (mA)
37362 G10
37362 G09
37362 G14
Maximum Current Sense Threshold
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
RUN/SS Pull-Up Current
vs Temperature
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
180
175
170
165
160
155
150
1.0
0.9
0.8
0.7
0.6
0.5
0.4
I
= GND
PRG
40 60
TEMPERATURE (°C)
40 60
–60 –40 –20
TEMPERATURE (°C)
–60 –40 –20
0
20
80 100
–60
20
TEMPERATURE (°C)
60 80
0
20
80 100
–40 –20
0
40
100
37362 G11
37362 G12
37362 G13
Oscillator Frequency
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
10
8
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
V
RISING
IN
6
4
2
0
V
FALLING
IN
–2
–4
–6
–8
–10
20 40
–60 –40 –20
0
60 80 100
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
TEMPERATURE (°C)
37362 G16
37362 G15
37362fa
5
LTC3736-2
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
U W
Shutdown Quiescent Current
vs Input Voltage
RUN/SS Start-Up Current
vs Input Voltage
20
18
16
14
12
10
8
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
RUN/SS = 0V
RUN/SS = 0V
6
4
2
0
6
7
2
3
4
5
8
9
10
2
6
8
9
3
4
5
7
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
37362 G18
37362 G17
U
U
U
PI FU CTIO S (QFN/SSOP Package)
ITH1/ITH2 (Pins 1, 8/Pins 4, 11): Current Threshold and
Error Amplifier Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
valuesequaltothoseconnectedtoVFB2 fromVOUT2 should
be used to connect to TRACK from VOUT1
.
PGOOD(Pin9/Pin12):Power-GoodOutputVoltageMoni-
tor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (VFB1, VFB2) is not
within ±13.3% of its nominal set point.
PLLLPF (Pin 3/Pin 6): Frequency Set/PLL Lowpass Filter.
When synchronizing to an external clock, this pin serves
as the lowpass filter point for the phase-locked loop. Nor-
mallyaseriesRCisconnectedbetweenthispinandground.
PGND(Pins12,16,20,25/Pins15,19,23):PowerGround.
These pins serve as the ground connection for the gate
drivers and the negative input to the reverse current com-
parators.TheExposedPadmustbesolderedtoPCBground.
Whennotsynchronizingtoanexternalclock,thispinserves
asthefrequencyselectinput. TyingthispintoGNDselects
300kHz operation; tying this pin to VIN selects 750kHz op-
eration. Floating this pin selects 550kHz operation.
RUN/SS (Pin 14/Pin 17): Run Control Input and Optional
ExternalSoft-StartInput.Forcingthispinbelow0.65Vshuts
down the chip (both channels). Driving this pin to VIN or
releasing this pin enables the chip, using the chip’s inter-
nalsoft-start.Anexternalsoft-startcanbeprogrammedby
connecting a capacitor between this pin and ground.
SGND(Pin4/Pin7):Small-SignalGround. Thispinserves
as the ground connection for most internal circuits.
VIN (Pin5/Pin8):ChipSignalPowerSupply.Thispinpow-
erstheentirechipexceptforthegatedrivers.Externallyfil-
tering this pin with a lowpass RC network (e.g.,
R = 10Ω, C = 1µF) is suggested to minimize noise pickup,
especially in high load current applications.
TG1/TG2(Pins17,15/Pins18,20):Top(PMOS)GateDrive
Output.ThesepinsdrivethegatesoftheexternalP-channel
MOSFETs. ThesepinshaveanoutputswingfromPGNDto
SENSE+.
TRACK (Pin 6/Pin 9): Tracking Input for Second Control-
ler.Allowsthestart-upofVOUT2 to“track”thatofVOUT1 ac-
cordingtoaratioestablishedbyaresistordivideronVOUT1
connected to the TRACK pin. For one-to-one tracking of
SYNC/FCB (Pin 18/Pin 21): This pin performs three
functions: 1) auxiliary winding feedback input, 2) external
clock synchronization input for phase-locked loop, and
3) pulse-skipping operation or forced continuous mode
V
OUT1 and VOUT2 during start-up, a resistor divider with
select. For auxiliary winding applications, connect to a
37362fa
6
LTC3736-2
U
U
U
PI FU CTIO S
resistor divider from the auxiliary output. To synchronize
with an external clock using the PLL, apply a CMOS
compatible clock with a frequency between 250kHz and
850kHz. To select pulse-skipping operation at light loads,
tie this pin to VIN. Grounding this pin selects forced
continuousoperation,whichallowstheinductorcurrentto
reverse. When synchronized to an external clock, pulse-
skipping operation is enabled at light loads.
SW1/SW2(Pins22,10/Pins1,13):SwitchNodeConnec-
tiontoInductor. Alsothenegativeinputtodifferentialpeak
currentcomparatorandaninputtothereversecurrentcom-
parator. Normally connected to the drain of the external P-
channel MOSFETs, the drain of the external N-channel
MOSFET, and the inductor.
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to
SelectMaximumPeakSenseVoltageThreshold.Thesepins
select the maximum allowed voltage drop between the
SENSE+ and SW pins (i.e., the maximum allowed drop
across the external P-channel MOSFET) for each channel.
TietoVIN,GNDorfloattoselect345mV,167mV,or240mV
respectively.
BG1/BG2(Pins19,13/Pins22,16):Bottom(NMOS)Gate
Drive Output. These pins drive the gates of the external N-
channel MOSFETs. These pins have an output swing from
PGND to SENSE+.
SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14): Positive
Input to Differential Current Comparator. Also powers the
gate drivers. Normally connected to the source of the ex-
ternal P-channel MOSFET.
V
FB1/VFB2(Pins24,7/Pins3,10):FeedbackPins.Receives
theremotelysensedfeedbackvoltageforitscontrollerfrom
an external resistor divider across the output.
U
U
W
FU CTIO AL DIAGRA
(Common Circuitry)
R
VIN
V
IN
(TO CONTROLLER 1, 2)
V
IN
C
VIN
UNDERVOLTAGE
LOCKOUT
VOLTAGE
REFERENCE
0.6V
REF
V
0.7µA
SHDN
RUN/SS
t
= 1ms
+
–
SEC
EXTSS
INTSS
SYNC/FCB
PLLLPF
PHASE
DETECTOR
SYNC DETECT
CLK1
CLK2
VOLTAGE
CONTROLLED
OSCILLATOR
SLOPE1
SLOPE2
SLOPE
COMP
–
–
+
V
FB1
UV1
PGOOD
FCB
FCB
OV1
SHDN
+
0.6V
0.54V
37362 FD
+
–
OV2
UV2
V
FB2
37362fa
7
LTC3736-2
U
U
W
FU CTIO AL DIAGRA (Controller 1)
V
IN
+
SENSE1
TG1
C
IN
RS1
CLK1
S
R
Q
MP1
SWITCHING
LOGIC
PGND
SW1
BG1
ANTISHOOT
THROUGH
L1
AND
OV1
SC1
FCB
BLANKING
CIRCUIT
V
OUT1
+
SENSE1
C
OUT1
MN1
PGND
IREV1
SLOPE1
–
+
SW1
ICMP
+
IPRG1
SENSE1
SHDN
–
R1B
R1A
V
FB1
+
EAMP
+
–
EXTSS
INTSS
0.6V
I
TH1
R
ITH1
0.12V
+
–
C
ITH1
SC1
SCP
V
FB1
V
PGND
+
–
–
+
FB1
OV1
OVP
IREV1
RICMP
0.68V
SW1
37362 CONT1
IPROG1 FCB
37362fa
8
LTC3736-2
U
U
W
FU CTIO AL DIAGRA (Controller 2)
V
IN
+
SENSE2
TG2
RS2
CLK2
S
R
Q
MP2
SWITCHING
LOGIC
PGND
SW2
BG2
ANTISHOOT
THROUGH
L2
AND
OV2
SC2
FCB
BLANKING
CIRCUIT
V
OUT2
+
SENSE2
C
OUT2
MN2
PGND
IREV2
SLOPE2
SW2
–
ICMP
+
+
IPRG2
SENSE2
SHDN
–
+
R2B
R2A
V
FB2
+
–
EAMP
V
OUT1
R
TRACKB
TRACKA
TRACK
0.6V
R
I
TH2
R
ITH2
0.12V
+
–
C
ITH2
SC2
SCP
V
FB2
TRACK
V
PGND
SW2
+
–
+
FB2
OV2
OVP
IREV2
–
0.68V
3736 CONT2
FCB
37362fa
9
LTC3736-2
U
(Refer to Functional Diagram)
OPERATIO
Main Control Loop
rise linearly from approximately 0.65V to 1.3V (being
charged by the internal 0.7µA current source), the EAMP
regulates the VFB1 proportionally linearly from 0V to 0.6V.
The LTC3736-2 uses a constant frequency, current mode
architecture with the two controllers operating 180 de-
grees out of phase. During normal operation, the top
external P-channel power MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the current comparator (ICMP) resets the latch. The
peak inductor current at which ICMP resets the RS latch is
determined by the voltage on the ITH pin, which is driven
by the output of the error amplifier (EAMP). The VFB pin
receives the output voltage feedback signal from an exter-
nal resistor divider. This feedback signal is compared to
theinternal0.6VreferencevoltagebytheEAMP. Whenthe
load current increases, it causes a slight decrease in VFB
relative to the 0.6V reference, which in turn causes the ITH
voltage to increase until the average inductor current
matches the new load current. While the top P-channel
MOSFET is off, the bottom N-channel MOSFET is turned
on until either the inductor current starts to reverse, as
indicatedbythecurrentreversalcomparator,IRCMP,orthe
beginning of the next cycle.
The start-up of VOUT2 is controlled by the voltage on the
TRACK pin. When the voltage on the TRACK pin is less
than the 0.6V internal reference, the LTC3736-2 regulates
the VFB2 voltage to the TRACK pin instead of the 0.6V
reference. Typically, a resistor divider on VOUT1 is con-
nected to the TRACK pin to allow the start-up of VOUT2 to
“track”thatofVOUT1.Forone-to-onetrackingduringstart-
up, the resistor divider would have the same values as the
divider on VOUT2 that is connected to VFB2
.
Light Load Operation (Pulse-Skipping or Continuous
Conduction) (SYNC/FCB Pin)
The LTC3736-2 can be enabled to enter high efficiency
pulse-skipping operation or forced continuous conduc-
tion mode at low load currents. To select pulse-skipping
operation,tietheSYNC/FCBpintoaDCvoltageabove0.6V
(e.g., VIN). To select forced continuous operation, tie the
SYNC/FCB to a DC voltage below 0.6V (e.g., SGND). This
0.6V threshold between pulse-skipping operation and
forced continuous mode can be used in secondary wind-
ing regulation as described in the Auxiliary Winding Con-
trol Using SYNC/FCB Pin discussion in the Applications
Information section.
Shutdown, Soft-Start and Tracking Start-Up
(RUN/SS and TRACK Pins)
The LTC3736-2 is shut down by pulling the RUN/SS pin
low. In shutdown, all controller functions are disabled and
thechipdrawsonly9µA.TheTGoutputsareheldhigh(off)
and the BG outputs low (off) in shutdown. Releasing
RUN/SS allows an internal 0.7µA current source to charge
up the RUN/SS pin. When the RUN/SS pin reaches 0.65V,
the LTC3736-2’s two controllers are enabled.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions.Thepeakinductorcurrentisdeterminedbythe
voltageontheITH pin. TheP-channelMOSFETisturnedon
every cycle (constant frequency) regardless of the ITH pin
voltage. In this mode, the efficiency at light loads is lower
than in pulse-skipping operation. However, continuous
mode has the advantages of lower output ripple and less
interference with audio circuitry.
The start-up of VOUT1 is controlled by the LTC3736-2’s
internal soft-start. During soft-start, the error amplifier
EAMP compares the feedback signal VFB1 to the internal
soft-startramp(insteadofthe0.6Vreference),whichrises
linearly from 0V to 0.6V in about 1ms. This allows the
output voltage to rise smoothly from 0V to its final value,
while maintaining control of the inductor current.
When the SYNC/FCB pin is tied to a DC voltage above 0.6V
or when it is clocked by an external clock source to use the
phase-locked loop (see Frequency Selection and Phase-
Locked Loop), the LTC3736-2 operates in PWM pulse-
skipping mode at light loads. In this mode, the current
comparatorICMP mayremaintrippedforseveralcyclesand
The 1ms soft-start time can be increased by connecting
the optional external soft-start capacitor CSS between the
RUN/SS and SGND pins. As the RUN/SS pin continues to
37362fa
10
LTC3736-2
U
(Refer to Functional Diagram)
OPERATIO
forcetheexternalP-channelMOSFETtostayoffforthesame
number of cycles. The inductor current is not allowed to
reverse,though(discontinuousoperation).Thismode,like
forced continuous operation, exhibits low output ripple as
well as low audio noise and reduced RF interference.
However, it provides low current efficiency higher than
forcedcontinuousmode.Duringstart-uporashort-circuit
condition (VFB1 or VFB2 ≤ 0.54V), the LTC3736-2 operates
in pulse-skipping mode (no current reversal allowed),
regardless of the state of the SYNC/FCB pin.
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage.
The switching frequency of the LTC3736-2’s controllers
can be selected using the PLLLPF pin.
If the SYNC/FCB is not being driven by an external clock
source, the PLLLPF can be floated, tied to VIN or tied to
SGND to select 550kHz, 750kHz or 300kHz respectively.
A phase-locked loop (PLL) is available on the LTC3736-2
to synchronize the internal oscillator to an external
clock source that is connected to the SYNC/FCB pin. In
this case, a series RC should be connected between the
PLLLPFpinandSGNDtoserveasthePLL’sloopfilter. The
LTC3736-2 phase detector adjusts the voltage on the
PLLLPF pin to align the turn-on of controller 1’s external
P-channel MOSFET to the rising edge of the synchroniz-
ing signal. Thus, the turn-on of controller 2’s external
P-channel MOSFET is 180 degrees out of phase with the
rising edge of the external clock source.
Short-Circuit Protection
When an output is shorted to ground (VFB < 0.12V), the
switching frequency of that controller is reduced to 1/5 of
the normal operating frequency. The other controller is
unaffected and maintains normal operation.
Theshort-circuitthresholdonVFB2 isbasedonthesmaller
of 0.12V and a fraction of the voltage on the TRACK pin.
This also allows VOUT2 to start up and track VOUT1 more
easily. Note that if VOUT1 is truly short-circuited
(VOUT1 = VFB1 = 0V), then the LTC3736-2 will try to
regulate VOUT2 to 0V if a resistor divider on VOUT1 is
connected to the TRACK pin.
The typical capture range of the LTC3736-2’s phase-
locked loop is from approximately 200kHz to 1MHz, and is
guaranteed over temperature to be between 250kHz and
850kHz. In other words, the LTC3736-2’s PLL is guaran-
teed to lock to an external clock source whose frequency
is between 250kHz and 850kHz.
Output Overvoltage Protection
As a further protection, the overvoltage comparator (OV)
guardsagainsttransientovershoots,aswellasothermore
serious conditions that may overvoltage the output. When
the feedback voltage on the VFB pin has risen 13.33%
above the reference voltage of 0.6V, the external P-chan-
nel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
Dropout Operation
When the input supply voltage (VIN) decreases towards
the output voltage, the rate of change of the inductor
current while the external P-channel MOSFET is on (ON
cycle)decreases.ThisreductionmeansthattheP-channel
MOSFET will remain on for more than one oscillator cycle
if the inductor current has not ramped up to the threshold
set by the EAMP on the ITH pin. Further reduction in the
input supply voltage will eventually cause the P-channel
MOSFET to be turned on 100%, i.e., DC. The output
voltage will then be determined by the input voltage minus
the voltage drop across the P-channel MOSFET and the
inductor.
Frequency Selection and Phase-Locked Loop
(PLLLPF and SYNC/FCB Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increasesefficiencybyreducingMOSFETswitchinglosses,
37362fa
11
LTC3736-2
U
(Refer to Functional Diagram)
OPERATIO
110
100
90
80
70
60
50
40
30
20
10
0
Undervoltage Lockout
To prevent operation of the external MOSFETs below safe
inputvoltagelevels,anundervoltagelockoutisincorporated
in the LTC3736-2. When the input supply voltage (VIN)
dropsbelow2.3V,theexternalP-andN-channelMOSFETs
and all internal circuitry are turned off except for the und-
ervoltage block, which draws only a few microamperes.
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG1 and IPRG2 Pins)
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
When a controller is operating below 20% duty cycle, the
peak current sense voltage (between the SENSE+ and SW
pins) allowed across the external P-channel MOSFET is
determined by:
37362 F01
Figure 1. Maximum Peak Current vs Duty Cycle
Power-Good (PGOOD) Pin
A V – 0.7V
(
)
ITH
∆VSENSE(MAX)
=
A window comparator monitors both feedback voltages
and the open-drain PGOOD output pin is pulled low when
either or both feedback voltages are not within ±10% of
the 0.6V reference voltage. PGOOD is low when the
LTC3736-2 is shut down or in undervoltage lockout.
10
where A is a constant determined by the state of the IPRG
pins. Floating the IPRG pin selects A = 1.875; tying IPRG
to VIN selects A = 2.7; tying IPRG to SGND selects A = 1.3.
ThemaximumvalueofVITH istypicallyabout1.98V, sothe
maximum sense voltage allowed across the external
P-channel MOSFET is 240mV, 345mV, or 167mV for the
three respective states of the IPRG pin. The peak sense
voltages for the two controllers can be independently
selected by the IPRG1 and IPRG2 pins.
2-Phase Operation
Why the need for 2-phase operation? Until recently, con-
stant frequency dual switching regulators operated both
controllers in phase (i.e., single phase operation). This
means that both topside MOSFETs (P-channel) are turned
on at the same time, causing current pulses of up to twice
the amplitude of those from a single regulator to be drawn
from the input capacitor. These large amplitude pulses
increase the total RMS current flowing in the input capaci-
tor, requiring the use of larger and more expensive input
capacitors, and increase both EMI and power losses in the
input capacitor and input power supply.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peak sense voltage by a scale factor given by the curve in
Figure 1.
Thepeakinductorcurrentisdeterminedbythepeaksense
voltage and the on-resistance of the external P-channel
MOSFET:
With 2-phase operation, the two controllers of the LTC3736-2
are operated 180 degrees out of phase. This effectively
interleaves the current pulses coming from the topside
MOSFET switches, greatly reducing the time where they
overlap and add together. The result is a significant
reductioninthetotalRMScurrent,whichinturnallowsthe
use of smaller, less expensive input capacitors, reduces
shielding requirements for EMI and improves real world
operating efficiency.
∆VSENSE(MAX)
IPK
=
RDS(ON)
37362fa
12
LTC3736-2
U
(Refer to Functional Diagram)
OPERATIO
Figure 2 shows example waveforms for a single phase
dual controller versus a 2-phase LTC3736-2 system. In
this case, 2.5V and 1.8V outputs, each drawing a load
current of 2A, are derived from a 7V (e.g., a 2-cell Li-Ion
battery) input supply. In this example, 2-phase operation
would reduce the RMS input capacitor current from
1.79ARMS to 0.91ARMS. While this is an impressive reduc-
tion by itself, remember that power losses are propor-
tional to IRMS2, meaning that actual power wasted is
reduced by a factor of 3.86.
tection circuitry. Improvements in both conducted and
radiated EMI also directly accrue as a result of the reduced
RMS input current and voltage. Significant cost and board
footprint savings are also realized by being able to use
smaller, less expensive, lower RMS current-rated input
capacitors.
Of course, the improvement afforded by 2-phase opera-
tion is a function of the relative duty cycles of the two
controllers, which in turn are dependent upon the input
supply voltage. Figure 3 depicts how the RMS input
current varies for single phase and 2-phase dual control-
lers with 2.5V and 1.8V outputs over a wide input voltage
range.
The reduced input ripple current also means that less
power is lost in the input power path, which could include
batteries, switches, trace/connector resistances, and pro-
It can be readily seen that the advantages of 2-phase
operation are not limited to a narrow operating range, but
in fact extend over a wide region. A good rule of thumb for
mostapplicationsisthat2-phaseoperationwillreducethe
input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
Single Phase
Dual Controller
2-Phase
Dual Controller
SW1 (V)
SW2 (V)
2.0
1.8
SINGLE PHASE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
I
I
L1
L2
DUAL CONTROLER
2-PHASE
DUAL CONTROLER
V
V
= 2.5V/2A
= 1.8V/2A
OUT1
OUT2
I
IN
2
6
8
9
3
4
5
7
10
INPUT VOLTAGE (V)
37362 F02
37362 F03
Figure 2. Example Waveforms for a Single Phase
Dual Controller vs the 2-Phase LTC3736-2
Figure 3. RMS Input Current Comparison
37362fa
13
LTC3736-2
W U U
U
APPLICATIO S I FOR ATIO
The typical LTC3736-2 application circuit is shown in
Figure 13. External component selection for each of the
LTC3736-2’s controllers is driven by the load requirement
and begins with the selection of the inductor (L) and the
power MOSFETs (MP and MN).
A reasonable starting point is setting ripple current IRIPPLE
to be 40% of IOUT(MAX). Rearranging the above equation
yields:
∆VSENSE(MAX)
5
RDS(ON)(MAX) = •
6
IOUT(MAX)
Power MOSFET Selection
for Duty Cycle < 20%.
Each of the LTC3736-2’s two controllers requires two
external power MOSFETs: a P-channel MOSFET for the
topside (main) switch and an N-channel MOSFET for the
bottom (synchronous) switch. Important parameters for
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of RDS(ON) to provide the required
amount of load current:
the power MOSFETs are the breakdown voltage VBR(DSS)
,
threshold voltage VGS(TH), on-resistance RDS(ON), reverse
transfer capacitance CRSS, turn-off delay tD(OFF) and the
total gate charge QG.
∆VSENSE(MAX)
IOUT(MAX)
5
6
RDS(ON)(MAX) = • SF •
The gate drive voltage is the input supply voltage. Since
the LTC3736-2 is designed for operation down to low
input voltages, a sublogic level MOSFET (RDS(ON)
guaranteed at VGS = 2.5V) is required for applications
that work close to this voltage. When these MOSFETs are
used, make sure that the input supply to the LTC3736-2
is less than the absolute maximum MOSFET VGS rating,
which is typically 8V.
whereSFisascalefactorwhosevalueisobtainedfromthe
curve in Figure 1.
These must be further derated to take into account the
significant variation in on-resistance with temperature.
The following equation is a good guide for determin-
ing the required RDS(ON)MAX at 25°C (manufacturer’s
specification), allowing some margin for variations in
the LTC3736-2 and external component values:
The P-channel MOSFET’s on-resistance is chosen based
on the required load current. The maximum average
output load current IOUT(MAX) is equal to the peak inductor
∆VSENSE(MAX)
IOUT(MAX) • ρT
5
6
RDS(ON)(MAX) = • 0.9 • SF •
current minus half the peak-to-peak ripple current IRIPPLE
.
The ρT is a normalizing term accounting for the tempera-
ture variation in on-resistance, which is typically about
0.4%/°C, as shown in Figure 4. Junction to case tempera-
ture TJC is about 10°C in most applications. For a maxi-
mum ambient temperature of 70°C, using ρ80°C ~ 1.3 in
the above equation is a reasonable choice.
The LTC3736-2’s current comparator monitors the drain-
to-source voltage VDS of the P-channel MOSFET, which is
sensed between the SENSE+ and SW pins. The peak
inductor current is limited by the current threshold, set by
the voltage on the ITH pin of the current comparator. The
voltage on the ITH pin is internally clamped, which limits
the maximum current sense threshold ∆VSENSE(MAX) to
approximately 240mV when IPRG is floating (167mV
when IPRG is tied low; 345mV when IPRG is tied high).
The power dissipated in the top and bottom MOSFETs
strongly depends on their respective duty cycles and load
current. When the LTC3736-2 is operating in continuous
mode, the duty cycles for the MOSFETs are:
The output current that the LTC3736-2 can provide is
given by:
VOUT
V
IN
Top P-Channel Duty Cycle =
∆VSENSE(MAX)
IRIPPLE
IOUT(MAX)
=
–
RDS(ON)
2
V – VOUT
IN
Bottom N-Channel Duty Cycle =
V
IN
37362fa
14
LTC3736-2
W U U
APPLICATIO S I FOR ATIO
U
2.0
1.5
1.0
0.5
0
(tD(OFF)) of less than approximately 140ns. However, due
to differences in test and specification methods of various
MOSFET manufacturers, and in the variations in QG and
tD(OFF)withgatedrive(VIN)voltage,theP-channelMOSFET
ultimately should be evaluated in the actual LTC3736-2
application circuit to ensure proper operation.
Shoot-through between the P-channel and N-channel
MOSFETs can most easily be spotted by monitoring the
input supply current. As the input supply voltage in-
creases,iftheinputsupplycurrentincreasesdramatically,
then the likely cause is shoot-through. Note that some
MOSFETsthatdonotworkwellathighinputvoltages(e.g.,
VIN > 5V) may work fine at lower voltages (e.g., 3.3V).
Table 1 shows a selection of P-channel MOSFETs from
different manufacturers that are known to work well in
LTC3736-2 applications.
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
37362 F04
Figure 4. R
vs Temperature
DS(ON)
The MOSFET power dissipations at maximum output
current are:
Selecting the N-channel MOSFET is typically easier, since
for a given RDS(ON), the gate charge and turn-on and turn-
off delays are much smaller than for a P-channel MOSFET.
VOUT
2
PTOP
=
•IOUT(MAX)2 •rT •RDS(ON) + 2 • V
IN
V
IN
Table 1. Selected P-Channel MOSFETs Suitable for LTC3736-2
Applications
•IOUT(MAX) •CRSS • fOSC
V – VOUT
IN
PART
P
=
•IOUT(MAX)2 •rT •RDS(ON)
BOT
V
NUMBER
MANUFACTURER
TYPE
PACKAGE
IN
Si7540DP
Siliconix
Complementary
P/N
PowerPak
SO-8
Both MOSFETs have I2R losses and the PTOP equation
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The bottom MOSFET losses
are greatest at high input voltage or during a short-circuit
when the bottom duty cycle is nearly 100%.
Si9801DY
FDW2520C
FDW2521C
Siliconix
Fairchild
Fairchild
Complementary
P/N
SO-8
Complementary
P/N
TSSOP-8
TSSOP-8
Complementary
P/N
The LTC3736-2 utilizes a nonoverlapping, antishoot-
through gate drive control scheme to ensure that the P-
and N-channel MOSFETs are not turned on at the same
time. To function properly, the control scheme requires
that the MOSFETs used are intended for DC/DC switching
applications. Many power MOSFETs, particularly P-chan-
nel MOSFETs, are intended to be used as static switches
and therefore are slow to turn on or off.
Si3447BDV
Si9433BDY
FDC602P
Siliconix
Siliconix
Fairchild
Fairchild
Fairchild
Fairchild
Fairchild
Hitachi
Single P
Single P
Single P
Single P
Single P
Dual P
TSOP-6
SO-8
TSOP-6
TSOP-6
TSOP-6
TSSOP-8
SO-8
FDC606P
FDC638P
FDW2502P
FDS6875
Dual P
HAT1054R
NTMD6P02R2-D
Dual P
SO-8
Reasonable starting criteria for selecting the P-channel
MOSFET are that it must typically have a gate charge (QG)
less than 25nC to 30nC (at 4.5VGS) and a turn-off delay
On Semi
Dual P
SO-8
37362fa
15
LTC3736-2
W U U
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APPLICATIO S I FOR ATIO
Operating Frequency and Synchronization
Inductor Core Selection
The choice of operating frequency, fOSC, is a trade-off
between efficiency and component size. Low frequency
operationimprovesefficiencybyreducingMOSFETswitch-
ing losses, both gate charge loss and transition loss.
However, lowerfrequencyoperationrequiresmoreinduc-
tance for a given amount of ripple current.
Once the inductance value is determined, the type of
inductor must be selected. Core loss is independent of
coresizeforafixedinductorvalue, butitisverydependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance re-
quires more turns of wire and therefore copper losses will
increase.
TheinternaloscillatorforeachoftheLTC3736-2’scontrol-
lersrunsatanominal550kHzfrequencywhenthePLLLPF
pin is left floating and the SYNC/FCB pin is a DC low or
high. Pulling the PLLLPF to VIN selects 750kHz operation;
pulling the PLLLPF to GND selects 300kHz operation.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Alternatively, the LTC3736-2 will phase-lock to a clock
signal applied to the SYNC/FCB pin with a frequency
between 250kHz and 850kHz (see Phase-Locked Loop
and Frequency Synchronization).
Schottky Diode Selection (Optional)
Inductor Value Calculation
The Schottky diodes D1 and D2 in Figure 16 conduct
current during the dead time between the conduction of
the power MOSFETs . This prevents the body diode of the
bottom N-channel MOSFET from turning on and storing
charge during the dead time, which could cost as much as
1% in efficiency. A 1A Schottky diode is generally a good
size for most LTC3736-2 applications, since it conducts a
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance. This diode may be omitted if the efficiency
loss can be tolerated.
Given the desired input and output voltages, the inductor
value and operating frequency fOSC directly determine the
inductor’s peak-to-peak ripple current:
VOUT ⎛ V – VOUT
⎞
⎟
IN
IRIPPLE
=
⎜
V
IN
⎝ fOSC •L ⎠
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
CIN and COUT Selection
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
The selection of CIN is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The control-
ler with the highest (VOUT)(IOUT) product needs to be used
in the formula below to determine the maximum RMS
V – VOUT VOUT
IN
L ≥
•
fOSC •IRIPPLE
V
IN
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16
LTC3736-2
W U U
APPLICATIO S I FOR ATIO
U
capacitor current requirement. Increasing the output cur-
rent drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
in a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source imped-
ance of the power supply/battery is included in the effi-
ciency testing. The sources of the P-channel MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may pro-
duce undesirable voltage and current resonances at VIN.
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (VOUT)/(VIN). To
preventlargevoltagetransients, alowESRcapacitorsized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3736-2, is also
suggested. A 10Ω resistor placed between CIN (C1) and
the VIN pin provides further isolation between the two
channels.
1/2
IMAX
CIN Required IRMS
≈
V
OUT)(
V – V
IN OUT
(
[
)
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
]
V
IN
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
usedfordesignbecauseevensignificantdeviationsdonot
offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. Due to the high operating frequency of the
LTC3736-2, ceramic capacitors can also be used for CIN.
Always consult the manufacturer if there is any question.
⎛
⎞
1
∆VOUT ≈IRIPPLE ESR +
⎜
⎟
8fCOUT
⎝
⎠
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
Setting Output Voltage
TheLTC3736-2outputvoltagesareeachsetbyanexternal
feedback resistor divider carefully placed across the out-
put, as shown in Figure 5. The regulated output voltage is
determined by:
The benefit of the LTC3736-2 2-phase operation can be
calculatedbyusingtheequationaboveforthehigherpower
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
currentpulsesrequiredthroughtheinputcapacitor’sESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Also, the input protection fuse re-
sistance,batteryresistance,andPCboardtraceresistance
losses are also reduced due to the reduced peak currents
⎛
⎞
RB
RA
VOUT = 0.6V • 1+
⎜
⎟
⎝
⎠
Toimprovethefrequencyresponse,afeedforwardcapaci-
tor, CFF, may be used. Great care should be taken to route
the VFB line away from noise sources, such as the inductor
or the SW line.
37362fa
17
LTC3736-2
APPLICATIO S I FOR ATIO
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V
OUT
This can be increased by placing a capacitor between the
RUN/SSpinandSGND. Inthiscase, thesoft-starttimewill
be approximately:
R
C
FF
B
1/2 LTC3736-2
V
FB
600mV
0.7µA
R
A
tSS1 = CSS
•
37362 F05
Figure 5. Setting Output Voltage
Tracking
The start-up of VOUT2 is controlled by the voltage on the
TRACK pin. Normally this pin is used to allow the start-up
of VOUT2 to track that of VOUT1 as shown qualitatively in
Figures 7a and 7b. When the voltage on the TRACK pin is
less than the internal 0.6V reference, the LTC3736-2
regulates the VFB2 voltage to the TRACK pin voltage
instead of 0.6V. The start-up of VOUT2 may ratiometrically
track that of VOUT1, according to a ratio set by a resistor
divider (Figure 7c):
Run/Soft-Start Function
The RUN/SS pin is a dual purpose pin that provides the
optional external soft-start function and a means to shut
down the LTC3736-2.
Pulling the RUN/SS pin below 0.65V puts the LTC3736-2
into a low quiescent current shutdown mode (IQ = 9µA). If
RUN/SS has been pulled all the way to ground, there will
be a delay before the LTC3736-2 comes out of shutdown
and is given by:
VOUT1
VOUT2 RTRACKA
R2A
RTRACKA + RTRACKB
R2B + R2A
=
•
CSS
0.7µA
tDELAY = 0.65V •
= 0.93s/µF •CSS
For coincident tracking (VOUT1 = VOUT2 during start-up),
R2A = RTRACKA
R2B = RTRACKB
This pin can be driven directly from logic as shown in
Figure 6. Diode D1 in Figure 6 reduces the start delay but
allows CSS to ramp up slowly providing the soft-start
function. This diode (and capacitor) can be deleted if the
external soft-start is not needed.
The ramp time for VOUT2 to rise from 0V to its final value
is:
RTRACKA
R1A
R1A + R1B
RTRACKA + RTRACKB
tSS2 = tSS1
•
•
During soft-start, the start-up of VOUT1 is controlled by
slowlyrampingthepositivereferencetotheerroramplifier
from 0V to 0.6V, allowing VOUT1 to rise smoothly from 0V
toitsfinalvalue. Thedefaultinternalsoft-starttimeis1ms.
V
OUT1
V
OUT2
LTC3736-2
R1B
R2B
3.3V OR 5V
RUN/SS
RUN/SS
V
V
FB2
FB1
D1
R1A
R2A
R
R
TRACKB
TRACKA
C
SS
C
SS
TRACK
37362 F07a
V
DD
≤ V
IN
RUN/SS
(INTERNAL SOFT-START)
Figure 7a. Using the TRACK Pin
37362 F06
Figure 6. RUN/SS Pin Interfacing
37362fa
18
LTC3736-2
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APPLICATIO S I FOR ATIO
U
V
V
OUT1
OUT1
V
V
OUT2
OUT2
37362 F07b,c
TIME
TIME
(7b) Coincident Tracking
(7c) Ratiometric Tracking
Figures 7b and 7c. Two Different Modes of Output Voltage Tracking
For coincident tracking,
VOUT2F
frequency, when there is a clock signal applied to SYNC/
FCB, is shown in Figure 8 and specified in the Electrical
Characteristicstable. NotethattheLTC3736-2canonlybe
synchronizedtoanexternalclockwhosefrequencyiswithin
rangeoftheLTC3736-2’sinternalVCO,whichisnominally
200kHzto1MHz.Thisisguaranteed,overtemperatureand
variations,tobebetween300kHzand750kHz.Asimplified
block diagram is shown in Figure 9.
tSS2 = tSS1
•
VOUT1F
where VOUT1F and VOUT2F are the final, regulated values of
VOUT1 and VOUT2. VOUT1 should always be greater than
VOUT2 when using the TRACK pin. If no tracking function
is desired, then the TRACK pin may be tied to VIN. How-
ever, in this situation there would be no (internal nor
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
external) soft-start on VOUT2
.
Phase-Locked Loop and Frequency Synchronization
TheLTC3736-2hasaphase-lockedloop(PLL)comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the external P-
channel MOSFET of controller 1 to be locked to the rising
edge of an external clock signal applied to the SYNC/FCB
pin. The turn-on of controller 2’s external P-channel
MOSFET is thus 180 degrees out of phase with the
external clock. The phase detector is an edge sensitive
digital type that provides zero degrees phase shift
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics of
the external clock.
1400
1200
1000
800
600
400
200
0
0
0.5
1
1.5
2
2.4
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
PLLLPF PIN VOLTAGE (V)
37362 F08
Figure 8. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
37362fa
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LTC3736-2
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APPLICATIO S I FOR ATIO
2.4V
R
LP
C
LP
PLLLPF
SYNC/
FCB
DIGITAL
PHASE/
EXTERNAL
OSCILLATOR
FREQUENCY
DETECTOR
OSCILLATOR
37362 F09
Figure 9. Phase-Locked Loop Block Diagram
PLLLPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage on the PLLLPF pin is adjusted until
the phase and frequency of the internal and external
oscillators are identical. At the stable operating point, the
phase detector output is high impedance and the filter
capacitor CLP holds the voltage.
Auxiliary Winding Control Using SYNC/FCB Pin
The SYNC/FCB can be used as an auxiliary feedback to
provide a means of regulating a flyback winding output.
When this pin drops below its ground-referenced 0.6V
threshold, continuous mode operation is forced.
During continuous mode, current flows continuously in
the transformer primary. The auxiliary winding draws
current only when the bottom, synchronous N-channel
MOSFET is on. When primary load currents are low and/or
the VIN/VOUT ratio is close to unity, the synchronous
MOSFET may not be on for a sufficient amount of time to
transfer power from the output capacitor to the auxiliary
load. Forced continuous operation will support an auxil-
iary winding as long as there is a sufficient synchronous
MOSFET duty factor. The FCB input pin removes the
requirement that power must be drawn from the trans-
formerprimaryinordertoextractpowerfromtheauxiliary
winding. With the loop in continuous mode, the auxiliary
output may nominally be loaded without regard to the
primary output load.
The loop filter components, CLP and RLP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01µF.
Typically, the external clock (on SYNC/FCB pin) input high
level is 1.6V, while the input low level is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN
0V
SYNC/FCB PIN
DC Voltage
DC Voltage
DC Voltage
Clock Signal
FREQUENCY
TheauxiliaryoutputvoltageVAUX isnormallysetasshown
in Figure 10 by the turns ratio N of the transformer:
300kHz
550kHz
Floating
VAUX ≅ (N + 1) VOUT
V
750kHz
IN
RC Loop Filter
Phase-Locked to External Clock
However, if the controller goes into pulse-skipping op-
eration and halts switching due to a light primary load
current, then VAUX will droop. An external resistor divider
from VAUX to the FCB sets a minimum voltage VAUX(MIN)
:
⎛
⎞
R6
R5
VAUX(MIN) = 0.6V 1+
⎜
⎟
⎝
⎠
37362fa
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LTC3736-2
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APPLICATIO S I FOR ATIO
U
V
OUT
1/2 LTC3736-2
R2
R1
V
D
D
AUX
V
IN
+
FB1
+
I
V
FB
TH
LTC3736-2
TG
L1
1:N
1µF
FB2
R6
R5
V
OUT
SYNC/FCB
37362 F11
SW
BG
+
C
OUT
Figure 11. Foldback Current Limiting
37362 F10
105
Figure 10. Auxiliary Output Loop Connection
V
REF
100
If VAUX drops below this value, the FCB voltage forces
temporary continuous switching operation until VAUX is
again above its minimum.
95
90
MAXIMUM
SENSE VOLTAGE
Table 3 summarizes the different states in which the
SYNC/FCB pin can be used
85
80
75
Table 3
SYNC/FCB PIN
CONDITION
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
0V to 0.5V
Forced Continuous Mode
Current Reversal Allowed
INPUT VOLTAGE (V)
37362 F12
0.7V to V
Pulse-Skipping Operation Enabled
No Current Reversal Allowed
IN
Figure 12. Line Regulation of V
and
REF
Maximum Sense Voltage for Low Input Supply
Feedback Resistors
External Clock Signal
Regulate an Auxiliary Winding
Enable Phase-Locked Loop
(Synchronize to External CLK)
Pulse-Skipping at Light Loads
No Current Reversal Allowed
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest amount of
time that the LTC3736-2 is capable of turning the top
P-channel MOSFET on and then off. It is determined by
internal timing delays and the gate charge required to turn
on the top MOSFET. Low duty cycle and high frequency
applications may approach the minimum on-time limit
and care should be taken to ensure that:
Fault Condition: Short-Circuit and Current Limit
To prevent excessive heating of the bottom MOSFET,
foldback current limiting can be added to reduce the
current in proportion to the severity of the fault.
VOUT
OSC • V
Foldback current limiting is implemented by adding di-
odes DFB1 and DFB2 between the output and the ITH pin as
showninFigure11.Inahardshort(VOUT=0V),thecurrent
will be reduced to approximately 50% of the maximum
output current.
tON(MIN)
<
f
IN
If the duty cycle falls below what can be accommodated
bytheminimumon-time,theLTC3736-2willbegintoskip
cycles (unless forced continuous mode is selected). The
output voltage will continue to be regulated, but the ripple
currentandripplevoltagewillincrease. Theminimumon-
time for the LTC3736-2 is typically about 200ns. How-
Low Supply Operation
Although the LTC3736-2 can function down to below
2.4V, themaximumallowableoutputcurrentisreducedas
VIN decreases below 3V. Figure 12 shows the amount of
changeasthesupplyisreduceddownto2.4V. Alsoshown
ever, as the peak sense voltage (IL(PEAK) • RDS(ON)
)
decreases, the minimum on-time gradually increases up
to about 250ns. This is of particular concern in forced
is the effect on VREF
.
continuous applications with low ripple current at light
37362fa
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LTC3736-2
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APPLICATIO S I FOR ATIO
loads. If forced continuous mode is selected and the duty
cycle falls below the minimum on-time requirement, the
output will be regulated by overvoltage protection.
4) Transition losses apply to the top external P-channel
MOSFET and increase with higher operating frequen-
cies and input voltages. Transition losses can be esti-
mated from:
Efficiency Considerations
Transition Loss = 2 (VIN)2IO(MAX) RSS
(f)
C
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
oftenusefultoanalyzeindividuallossestodeterminewhat
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Other losses, including CIN and COUT ESR dissipative
lossesandinductorcorelosses,generallyaccountforless
than 2% total additional loss.
Checking Transient Response
Efficiency = 100% – (L1 + L2 + L3 + …)
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD)(ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or dis-
chargeCOUT, whichgeneratesafeedbackerrorsignal. The
regulator loop then returns VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing. OPTI-LOOP® compensation allows
the transient response to be optimized over a wide range
of output capacitance and ESR values.
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3736-2 circuits: 1) LTC3736-2 DC bias
current, 2) MOSFET gate charge current, 3) I2R losses,
and 4) transition losses.
1) The VIN (pin) current is the DC supply current, given in
the electrical characteristics, excluding MOSFET driver
currents. VIN current results in a small loss that in-
creases with VIN.
The ITH series RC-CC filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The ITH exter-
nal components shown in the Typical Application on the
front page of this data sheet will provide an adequate
starting point for most applications. The values can be
modified slightly (from 0.2 to 5 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type and
value have been determined. The output capacitors need
to be decided upon because the various types and values
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1µs to 10µs will produce output
voltage and ITH pin waveforms that will give a sense of the
overall loop stability. The gain of the loop will be increased
by increasing RC, and the bandwidth of the loop will be
2) MOSFETgatechargecurrentresultsfromswitchingthe
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from SENSE+ to ground.
The resulting dQ/dt is a current out of SENSE+, which is
typically much larger than the DC supply current. In
continuous mode, IGATECHG = f • QP.
3) I2R losses are calculated from the DC resistances of the
MOSFETs and inductor. In continuous mode, the aver-
age output current flows through L but is “chopped”
between the top P-channel MOSFET and the bottom
N-channel MOSFET. The MOSFET RDS(ON)s multiplied
by duty cycle can be summed with the resistance of L
to obtain I2R losses.
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
37362fa
22
LTC3736-2
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APPLICATIO S I FOR ATIO
U
increased by decreasing CC. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
+
C
OUT1
V
OUT1
L1
LTC3736EGN-2
1
2
24
23
22
21
20
19
18
17
16
15
14
13
+
SENSE1
SW1
PGND
BG1
IPRG1
3
MN1
VIN1
MP1
V
FB1
TH1
C
4
SYNC/FCB
TG1
I
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(CLOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
5
IPRG2
PLLLPF
SGND
C
VIN
6
PGND
TG2
V
IN
7
C
8
VIN2
RUN/SS
BG2
V
IN
9
MN2
MP2
TRACK
10
11
12
PGND
V
FB2
TH2
+
SENSE2
I
SW2
PGOOD
L2
+
V
OUT2
C
OUT2
37362 F13
BOLD LINES INDICATE HIGH CURRENT PATHS
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3736-2. These items are illustrated in the layout dia-
gram of Figure 13. Figure 14 depicts the current wave-
forms present in the various branches of the 2-phase dual
regulator.
Figure 13. LTC3736-2 Layout Diagram
power ground for its power loop (as described above
in item 1). The power grounds for the two channels
should connect together at a common point. It is most
important to keep the ground paths with high switch-
ing currents away from each other.
1) The power loop (input capacitor, MOSFETs, inductor,
outputcapacitor)ofeachchannelshouldbeassmallas
possible and isolated as much as possible from the
power loop of the other channel. Ideally, the drains of
the P- and N-channel FETs should be connected close
to one another with an input capacitor placed across
the FET sources (from the P-channel source to the N-
channel source) right at the FETs. It is better to have
two separate, smaller valued input capacitors (e.g.,
two 10µF—one for each channel) than it is to have a
single larger valued capacitor (e.g., 22µF) that the
channels share with a common connection.
ThePGNDpinsontheLTC3736-2ICshouldbeshorted
together and connected to the common power ground
connection (away from the switching currents).
3) Put the feedback resistors close to the VFB pins. The
trace connecting the top feedback resistor (RB) to the
output capacitor should be a Kelvin trace. The ITH
compensation components should also be very close
to the LTC3736-2.
4) The current sense traces (SENSE+ and SW) should be
Kelvin connections right at the P-channel MOSFET
source and drain.
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor
dividers, ITH compensation networks and the SGND pin.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-
signal components, especially the opposite channel’s
feedback resistors, ITH compensation components,
and the current sense pins (SENSE+ and SW).
The power grounds consist of the (–) terminal of the
input and output capacitors and the source of the N-
channel MOSFET. Each channel should have its own
37362fa
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LTC3736-2
APPLICATIO S I FOR ATIO
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MP1
L1
V
OUT1
+
C
OUT1
R
L1
MN1
V
IN
R
IN
+
C
IN
MP2
L2
V
OUT2
+
C
OUT2
R
L2
MN2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH
37362 F14
Figure 14. Branch Current Waveforms
37362fa
24
LTC3736-2
U
TYPICAL APPLICATIO S
R
R
FB1B
187k
FB1A
59k
L1
1.5µH
C
ITH1A
V
2.5V
6A
MP1
OUT1
22
23
24
1
2
3
100pF
21
20
19
18
17
16
15
+
SW1
IPRG1
SENSE1
PGND
BG1
SYNC/FCB
TG1
MN1
Si7540DP
V
FB1
+
C
OUT1
I
TH1
150µF
R
ITH1
IPRG2
PLLLPF
SGND
C
ITH1
15k
PGND
TG2
220pF
4
V
IN
5V
R
10Ω
LTC3736EUF-2
IN
VIN
5
14
C
IN
V
RUN/SS
10µF
×2
13
12
11
MN2
Si7540DP
C
BG2
OUT2
9
7
8
6
C
ITH2
+
150µF
PGND
PGOOD
V
1.8V
6A
C
OUT2
220pF
VIN
+
V
FB2
SENSE2
1µF
MP2
I
L2
1.5µH
TH2
10
R
ITH2
TRACK
PGND
25
SW2
15k
C
10nF
SS
C
ITH2B
100pF
R
R
FB2B
118k
FB2A
R
R
TRACKB
118k
TRACKA
59k
59k
37362 F15
Figure 15. 2-Phase, 550kHz, Dual Output Synchronous DC/DC Converter
R
R
FB1B
187k
FB1A
59k
C
FF1
L1
22pF
MP1
C
ITH1A
1.5µH
V
2.5V
4A
Si3447BDV
OUT1
22
23
24
1
2
3
100pF
21
20
19
18
17
16
15
+
SW1
IPRG1
SENSE1
PGND
BG1
SYNC/FCB
TG1
D1
MN1
V
I
FB1
C
47µF
×2
OUT1
Si3460DV
TH1
R
ITH1
IPRG2
PLLLPF
SGND
C
ITH1
22k
PGND
TG2
1000pF
4
V
IN
3.3V
R
10Ω
LTC3736EUF-2
IN
VIN
5
14
V
RUN/SS
C
IN
D2
C
47µF
×2
OUT2
22µF
13
12
11
MN2
Si3460DV
BG2
9
7
8
6
C
ITH2
PGND
PGOOD
V
1.8V
4A
C
1µF
OUT2
1000pF
VIN
+
V
SENSE2
FB2
MP2
Si3447BDV
I
L2
1.5µH
TH2
10
R
ITH2
22k
TRACK
PGND
SW2
C
SS
25
C
ITH2A
10nF
100pF
R
R
FB2B
118k
FB2A
R
R
TRACKA
59k
TRACKB
118k
59k
37362 F16
L1, L2: VISHAY IHLP-2525CZ-01
D1, D2: OPTIONAL
Figure 16. 2-Phase, 750kHz, Dual Output Synchronous DC/DC Converter
37362fa
25
LTC3736-2
TYPICAL APPLICATIO S
U
C
FF1
100pF
R
R
FB1B
FB1A
59k
187k
CLK IN
MP1
L1
C
ITH1
1.5µH
V
2.5V
5A
OUT1
R
ITH1
22k
SW1
1
2
3
4
5
6
7
1nF
24
23
22
21
20
19
18
+
SW1
IPRG1
SENSE1
PGND
BG1
SYNC/FCB
TG1
MN1
Si7540DP
V
FB1
C
OUT1
C
LP
I
TH1
100µF
R
10nF
LP
IPRG2
PLLLPF
SGND
15k
PGND
TG2
V
IN
3.3V
R
VIN
10Ω
LTC3736EGN-2
IN
5
17
V
RUN/SS
C
IN
22µF
16
15
14
MN2
C
BG2
OUT2
12
10
11
9
C
Si7540DP
ITH2
100µF
PGND
PGOOD
V
1.8V
5A
C
OUT2
1nF
VIN
+
V
SENSE2
1µF
FB2
MP2
SW2
I
L2
1.5µH
TH2
13
R
ITH2
TRACK
SW2
22k
R
FB2A
59k
R
R
FB2B R
TRACKB
TRACKA
59k
118k
118k
37362 F17
L1, L2: VISHAY IHLP-2525CZ-01
C
FF1
100pF
Figure 17. 2-Phase, Synchronizable, Dual Output Synchronous DC/DC Converter
37362fa
26
LTC3736-2
U
PACKAGE DESCRIPTIO
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
7.90 – 8.50*
(.311 – .335)
1.25 ±0.12
24 23 22 21 20 19 18 17 16 15 14
13
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
8
1
2
3
4
6
9 10 11 12
2.0
5.00 – 5.60**
(.197 – .221)
(.079)
MAX
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
0.55 – 0.95
0.05
(.002)
MIN
0.22 – 0.38
(.009 – .015)
TYP
(.0035 – .010)
(.022 – .037)
G24 SSOP 0204
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3. DRAWING NOT TO SCALE
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
(4 SIDES)
R = 0.115
TYP
0.75 ± 0.05
4.00 ± 0.10
(4 SIDES)
23 24
0.70 ±0.05
PIN 1
TOP MARK
(NOTE 5)
0.38 ± 0.10
1
2
4.50 ± 0.05 2.45 ± 0.05
2.45 ± 0.10
(4-SIDES)
(4 SIDES)
3.10 ± 0.05
PACKAGE
OUTLINE
(UF24) QFN 0603
0.25 ± 0.05
0.50 BSC
0.200 REF
0.25 ±0.05
0.50 BSC
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-X)—TO BE APPROVED
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm
ON ANY SIDE, IF PRESENT
37362fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC3736-2
U
TYPICAL APPLICATIO
2-Phase, 750kHz, Dual Output Synchronous DC/DC Converter
R
R
FB1B
187k
FB1A
59k
C
FF1
22pF
L1
MP1
C
ITH1A
1.5µH
V
2.5V
4A
Si3447BDV
OUT1
22
23
24
1
2
3
100pF
21
20
19
18
17
16
15
+
SW1
IPRG1
SENSE1
PGND
BG1
SYNC/FCB
TG1
D1
MN1
V
I
FB1
C
47µF
×2
OUT1
Si3460DV
TH1
R
ITH1
22k
IPRG2
PLLLPF
SGND
C
ITH1
PGND
TG2
1000pF
4
V
IN
3.3V
R
10Ω
LTC3736EUF-2
IN
VIN
5
14
V
RUN/SS
C
IN
D2
C
47µF
×2
OUT2
22µF
13
12
11
MN2
Si3460DV
BG2
9
7
8
6
C
ITH2
PGND
PGOOD
V
1.8V
4A
C
VIN
1µF
OUT2
1000pF
+
V
SENSE2
FB2
MP2
Si3447BDV
I
L2
1.5µH
TH2
TRACK
PGND
10
R
ITH2
22k
SW2
C
SS
25
C
ITH2A
100pF
10nF
R
FB2A
59k
R
FB2B
118k
R
R
TRACKA
59k
TRACKB
118k
37362 F16
L1, L2: VISHAY IHLP-2525CZ-01
D1, D2: OPTIONAL
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Synchronous Controller with
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SENSE
LTC3772
LTC3776
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2.75V ≤ V ≤ 9.8V, SOT-23 or 3mm × 2mm DFN Packages
IN
SENSE
Dual, 2-Phase, No R
Synchronous Controller for
Provides V
and V with One IC, 2.75V ≤ V ≤ 9.8V,
DDQ TT IN
SENSE
DDR/QDR Memory Termination
No R , Low EMI, Synchronous Step-Down Controller with
4mm × 4mm QFN and 24-Lead SSOP Packages
LTC3808
2.75V ≤ V ≤ 9.8V; Spread Spectrum Operation; 3mm × 4mm
SENSE
IN
Output Tracking
DFN and 16-Lead SSOP Packages
LTC3809/LTC3809-1 No R
Synchronous Step-Down Controllers
2.75V to 9.8V, 3mm × 3mm DFN and 10-Lead MSOPE Packages
SENSE
No R
is a trademark of Linear Technology Corporation.
SENSE
37362fa
LT 0206 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
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