LTC3736EUF#TRPBF [Linear]
LTC3736 - Dual 2-Phase, No RSENSE, Synchronous Controller with Output Tracking; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC3736EUF#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3736 - Dual 2-Phase, No RSENSE, Synchronous Controller with Output Tracking; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C 控制器 |
| 文件： | 总28页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3736
TM
Dual 2-Phase, No RSENSE
,
Synchronous Controller
with Output Tracking
U
FEATURES
DESCRIPTIO
The LTC®3736 is a 2-phase dual synchronous step-down
switching regulator controller with tracking that drives
externalcomplementarypowerMOSFETsusingfewexter-
nal components. The constant frequency current mode
architecture with MOSFET VDS sensing eliminates the
need for sense resistors and improves efficiency. Power
loss and noise due to the ESR of the input capacitance are
minimized by operating the two controllers out of phase.
■
No Current Sense Resistors Required
■
Out-of-Phase Controllers Reduce Required
Input Capacitance
Tracking Function
Wide VIN Range: 2.75V to 9.8V
■
■
■
Constant Frequency Current Mode Operation
■
0.6V ±1.5% Voltage Reference
■
Low Dropout Operation: 100% Duty Cycle
■
True PLL for Frequency Locking or Adjustment
BurstModeoperationprovideshighefficiencyatlightloads.
100%dutycyclecapabilityprovideslowdropoutoperation,
extending operating time in battery-powered systems.
Selectable Burst Mode®/Forced Continuous Operation
■
■
Auxiliary Winding Regulation
Internal Soft-Start Circuitry
Power Good Output Voltage Monitor
Output Overvoltage Protection
Micropower Shutdown: IQ = 9µA
■
■
■
■
■
Theswitchingfrequencycanbeprogrammedupto750kHz,
allowing the use of small surface mount inductors and ca-
pacitors. For noise sensitive applications, the LTC3736
switching frequency can be externally synchronized from
250kHz to 850kHz. Burst Mode operation is inhibited dur-
ingsynchronizationorwhentheSYNC/FCBpinispulledlow
inordertoreducenoiseandRFinterference.Automaticsoft-
start is internally controlled.
Tiny Low Profile (4mm × 4mm) QFN and Narrow
SSOP Packages U
APPLICATIO S
■
One or Two Lithium-Ion Powered Devices
Notebook and Palmtop Computers, PDAs
Portable Instruments
Distributed DC Power Systems
The LTC3736 is available in the tiny thermally enhanced
(4mm × 4mm) QFN package or 24-lead SSOP narrow
package.
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
No RSENSE is a trademark of Linear Technology Corporation.
U
TYPICAL APPLICATIO
High Efficiency, 2-Phase, Dual Synchronous DC/DC Step-Down Converter
Efficiency vs Load Current
V
100
95
90
85
80
75
70
65
60
55
50
IN
2.75V TO 9.8V
10µF
×2
V
+
IN
V
= 3.3V
IN
+
SENSE1 SENSE2
V
IN
= 4.2V
TG1
TG2
2.2µH
2.2µH
SW1
SW2
V
= 5V
IN
LTC3736
BG1
BG2
PGND
PGND
118k
187k
V
OUT1
2.5V
V
OUT2
1.8V
V
FB1
V
FB2
FIGURE 16 CIRCUIT
I
I
TH1
TH2
+
+
220pF
15k
V
= 2.5V
220pF
59k
SGND
OUT
47µF
47µF
1
10
100
1000
10000
15k
59k
LOAD CURRENT (mA)
3736 TA01b
3736 TA01a
3736f
1
LTC3736
W W U W
ABSOLUTE AXI U RATI GS (Note 1)
Input Supply Voltage (VIN) ........................ –0.3V to 10V
TG1, TG2, BG1, BG2 Peak Output Current (<10µs) ..... 1A
Operating Temperature Range (Note 2) ... –40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
Junction Temperature (Note 3) ............................ 125°C
Lead Temperature (Soldering, 10 sec)
PLLLPF, RUN/SS, SYNC/FCB,
TRACK, SENSE1+, SENSE2+,
IPRG1, IPRG2 Voltages................. –0.3V to (VIN + 0.3V)
VFB1, VFB2, ITH1, ITH2 Voltages .................. –0.3V to 2.4V
SW1, SW2 Voltages ............ –2V to VIN + 1V or 10V Max
PGOOD ..................................................... –0.3V to 10V
(LTC3736EGN) ..................................................... 300°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
TOP VIEW
NUMBER
+
1
2
SENSE1
PGND
BG1
24
23
22
21
20
19
18
17
16
15
14
13
SW1
IPRG1
LTC3736EUF
LTC3736EGN
24 23 22 21 20 19
3
V
FB1
TH1
I
1
2
3
4
5
6
18 SYNC/FCB
TH1
4
SYNC/FCB
TG1
I
IPRG2
PLLLPF
SGND
TG1
17
16
5
IPRG2
PLLLPF
SGND
PGND
25
6
PGND
TG2
15 TG2
7
V
14 RUN/SS
13 BG2
IN
8
RUN/SS
BG2
V
IN
TRACK
UF PART MARKING
3736
9
TRACK
7
8
9 10 11 12
10
11
12
PGND
V
FB2
TH2
+
SENSE2
I
SW2
PGOOD
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
GN PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 25) IS PGND
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
Input DC Supply Current
Sleep Mode
Shutdown
(Note 4)
300
9
3
425
20
10
µA
µA
µA
RUN/SS = 0V
UVLO
V
IN
< UVLO Threshold
Undervoltage Lockout Threshold
V
IN
V
IN
Falling
Rising
●
●
1.95
2.15
2.25
2.45
2.55
2.75
V
V
Shutdown Threshold at RUN/SS
Start-Up Current Source
0.45
0.5
0.65
0.7
0.85
1
V
RUN/SS = 0V
µA
Regulated Feedback Voltage
0°C to 85°C (Note 5)
–40°C to 85°C
0.591
0.588
0.6
0.6
0.609
0.612
V
V
●
Output Voltage Line Regulation
2.7V < V < 9.8V (Note 5)
0.05
0.2
mV/V
IN
3736f
2
LTC3736
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Load Regulation
I
I
= 0.9V (Note 5)
= 1.7V
0.12
–0.12
0.5
–0.5
%
%
TH
TH
V
Input Current
(Note 5)
10
10
50
50
nA
nA
V
FB1,2
TRACK Input Current
TRACK = 0.6V
Measured at V
Overvoltage Protect Threshold
Overvoltage Protect Hysteresis
Auxiliary Feedback Threshold
Top Gate (TG) Drive 1, 2 Rise Time
Top Gate (TG) Drive 1, 2 Fall Time
Bottom Gate (BG) Drive 1, 2 Rise Time
Bottom Gate (BG) Drive 1, 2 Fall Time
0.66
0.68
20
0.7
FB
mV
V
SYNC/FCB Ramping Negative
C = 3000pF
0.525
0.6
40
0.675
ns
ns
ns
ns
L
C = 3000pF
L
40
C = 3000pF
L
50
C = 3000pF
L
40
Maximum Current Sense Voltage
IPRG = Floating
115
110
75
125
125
85
135
140
95
100
215
223
mV
mV
mV
mV
mV
mV
+
(SENSE – SW)(∆V
)
●
●
●
SENSE(MAX)
IPRG = 0V
70
85
IPRG = V
193
185
204
204
IN
Soft-Start Time
Time for V to Ramp from 0.05V to 0.55V
0.667
0.833
1
ms
FB1
Oscillator and Phase-Locked Loop
Oscillator Frequency
Unsynchronized (SYNC/FCB Not Clocked)
V
V
V
= Floating
= 0V
●
●
●
480
260
650
550
300
750
600
340
825
kHz
kHz
kHz
PLLLPF
PLLLPF
PLLLPF
= V
IN
Phase-Locked Loop Lock Range
SYNC/FCB Clocked
Minimum Synchronizable Frequency
Maximum Synchronizable Frequency
●
●
200
1150
250
kHz
kHz
850
Phase Detector Output Current
Sinking
f
f
> f
< f
–4
4
µA
µA
OSC
OSC
SYNC/FCB
SYNC/FCB
Sourcing
PGOOD Output
PGOOD Voltage Low
PGOOD Trip Level
I
Sinking 1mA
125
mV
PGOOD
V
with Respect to Set Output Voltage
FB
V
FB
V
FB
V
FB
V
FB
< 0.6V, Ramping Positive
< 0.6V, Ramping Negative
> 0.6V, Ramping Negative
> 0.6V, Ramping Positive
–13
–16
7
–10.0
–13.3
10.0
–7
–10
13
%
%
%
%
10
13.3
16
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 2: The LTC3736E is guaranteed to meet specified performance from
0°C to 70°C. Specifications over the –40°C to 85°C operating range are
assured by design, characterization and correlation with statistical process
controls.
Note 5: The LTC3736 is tested in a feedback loop that servos I to a
TH
specified voltage and measures the resultant V voltage.
FB
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as shown in Figure 1.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
T = T + (P • θ °C/W)
J
A
D
JA
3736f
3
LTC3736
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
Load Step
(Forced Continuous Mode)
Efficiency vs Load Current
Load Step (Burst Mode Operation)
100
95
90
85
80
75
70
65
60
55
50
FIGURE 15 CIRCUIT
V
V
OUT
OUT
AC-COUPLED
100mV/DIV
AC-COUPLED
100mV/DIV
I
L
I
L
2A/DIV
2A/DIV
V
= 5V
IN
SYNC/FCB = V
IN
V
OUT
V
OUT
V
OUT
V
OUT
= 3.3V
= 2.5V
= 1.8V
= 1.2V
V
V
LOAD
SYNC/FCB = V
FIGURE 17 CIRCUIT
= 3.3V
100µs/DIV
3736 G02
V
= 3.3V
100µs/DIV
= 300mA TO 3A
3736 G03
IN
IN
= 1.8V
V
= 1.8V
OUT
OUT
I
LOAD
I
= 300mA TO 3A
SYNC/FCB = 0V
IN
1
10
100
1000
10000
FIGURE 17 CIRCUIT
LOAD CURRENT (mA)
3736 G01
Load Step (Pulse Skipping Mode)
Inductor Current at Light Load
Burst Mode
OPERATION
V
OUT
AC-COUPLED
100mV/DIV
SYNC/FCB = V
IN
FORCED
CONTINUOUS
MODE
I
L
1A/DIV
SYNC/FCB = 0V
I
L
PULSE
SKIPPING MODE
SYNC/FCB = 550kHz
2A/DIV
V
V
I
= 3.3V
100µs/DIV
3736 G04
V
V
I
= 3.3V
4µs/DIV
3736 G05
IN
OUT
IN
OUT
= 1.8V
= 300mA TO 3A
= 1.8V
= 200mA
LOAD
LOAD
SYNC/FCB = 550kHz EXTERNAL CLOCK
FIGURE 17 CIRCUIT
FIGURE 17 CIRCUIT
Tracking Start-Up with Internal
Soft-Start (CSS = 0µF)
Tracking Start-Up with External
Soft-Start (CSS = 0.15µF)
Oscillator Frequency
vs Input Voltage
5
4
3
2
V
V
OUT1
OUT1
2.5V
2.5V
V
V
OUT2
OUT2
1.8V
1.8V
500mV/
DIV
500mV/
DIV
1
0
–1
–2
–3
–4
–5
V
= 5V
LOAD1
200µs/DIV
= 1Ω
3736 G06
V
= 5V
IN
LOAD1
40ms/DIV
3736 G07
IN
R
= R
R
= R = 1Ω
LOAD2
LOAD2
FIGURE 15 CIRCUIT
FIGURE 15 CIRCUIT
2
6
8
9
3
4
5
7
10
INPUT VOLTAGE (V)
3736 G08
3736f
4
LTC3736
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
Maximum Current Sense Voltage
vs ITH Pin Voltage
Regulated Feedback Voltage
vs Temperature
Efficiency vs Load Current
100
95
90
85
80
75
70
65
60
55
50
100
80
60
40
20
0
0.609
0.607
0.605
0.603
0.601
0.599
0.597
0.595
0.593
0.591
Burst Mode
OPERATION
Burst Mode OPERATION
(I RISING)
TH
(SYNC/FCB = V
)
IN
Burst Mode OPERATION
(I FALLING)
TH
FORCED CONTINUOUS
MODE
PULSE SKIPPING
MODE
FORCED
CONTINUOUS
(SYNC/FCB = 0V)
PULSE SKIPPING
MODE
(SYNC/FCB = 550kHz)
FIGURE 15 CIRCUIT
V
V
= 5V
IN
OUT
= 2.5V
–20
0.5
1
1.5
VOLTAGE (V)
2
1
10
100
1000
10000
20 40
–60 –40 –20
TEMPERATURE (°C)
0
60 80 100
I
LOAD CURRENT (mA)
TH
3736 G10
3736 G09
3736 G11
Maximum Current Sense Threshold
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
RUN/SS Pull-Up Current
vs Temperature
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
135
130
125
120
1.0
0.9
0.8
0.7
0.6
0.5
0.4
I
= FLOAT
PRG
115
40 60
–60 –40 –20
TEMPERATURE (°C)
–60
20
TEMPERATURE (°C)
60 80
0
20
80 100
–60 –40 –20
0
20 40 60 80 100
–40 –20
0
40
100
TEMPERATURE (°C)
3736 G12
3736 G13
3736 G14
Oscillator Frequency
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
10
8
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
V
IN
RISING
6
4
2
0
V
IN
FALLING
–2
–4
–6
–8
–10
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
20 40
–60 –40 –20
0
60 80 100
TEMPERATURE (°C)
3736 G15
3736 G16
3736f
5
LTC3736
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
U W
Shutdown Quiescent Current
vs Input Voltage
RUN/SS Start-Up Current
vs Input Voltage
20
18
16
14
12
10
8
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
RUN/SS = 0V
RUN/SS = 0V
6
4
2
0
2
6
8
9
3
4
5
7
10
6
7
2
3
4
5
8
9
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3736 G17
3736 G18
U
U
U
PI FU CTIO S
(UF/GN Package)
ITH1/ITH2 (Pins 1, 8/ Pins 4, 11): Current Threshold and
Error Amplifier Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
with values equal to those connected to VFB2 from VOUT2
should be used to connect to TRACK from VOUT1
.
PGOOD(Pin 9/Pin 12): Power Good Output Voltage Moni-
tor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (VFB1, VFB2) is not
within ±13.3% of its nominal set point.
PLLLPF (Pin 3/Pin 6): Frequency Set/PLL Lowpass Filter.
When synchronizing to an external clock, this pin serves
as the lowpass filter point for the phase-locked loop. Nor-
mallyaseriesRCisconnectedbetweenthispinandground.
PGND (Pins 12, 16, 20, 25/ Pins 15, 19, 23): Power
Ground.Thesepinsserveasthegroundconnectionforthe
gate drivers and the negative input to the reverse current
comparators. The Exposed Pad (UF package) must be
soldered to PCB ground.
Whennotsynchronizingtoanexternalclock,thispinserves
asthefrequencyselectinput. TyingthispintoGNDselects
300kHz operation; tying this pin to VIN selects 750kHz op-
eration. Floating this pin selects 550kHz operation.
RUN/SS (Pin 14/Pin 17): Run Control Input and Optional
ExternalSoft-StartInput.Forcingthispinbelow0.65Vshuts
down the chip (both channels). Driving this pin to VIN or
releasing this pin enables the chip, using the chip’s inter-
nalsoft-start.Anexternalsoft-startcanbeprogrammedby
connecting a capacitor between this pin and ground.
SGND(Pin4/Pin7):Small-SignalGround. Thispinserves
as the ground connection for most internal circuits.
VIN (Pin 5/Pin 8): Chip Signal Power Supply. This pin
powerstheentirechipexceptforthegatedrivers.Externally
filtering this pin with a lowpass RC network (e.g.,
R = 10Ω, C = 1µF) is suggested to minimize noise pickup,
especially in high load current applications.
TG1/TG2(Pins17,15/Pins20,18):Top(PMOS)GateDrive
Output.ThesepinsdrivethegatesoftheexternalP-channel
MOSFETs. ThesepinshaveanoutputswingfromPGNDto
SENSE+.
TRACK (Pin 6/Pin 9): Tracking Input for Second Control-
ler. Allows the start-up of VOUT2 to “track” that of VOUT1
according to a ratio established by a resistor divider on
VOUT1 connected to the TRACK pin. For one-to-one track-
ing of VOUT1 and VOUT2 during start-up, a resistor divider
SYNC/FCB (Pin 18/Pin 21): This pin performs three
functions: 1) auxiliary winding feedback input, 2) external
clock synchronization input for phase-locked loop, and 3)
Burst Mode operation or forced continuous mode select.
3736f
6
LTC3736
U
U
U
PI FU CTIO S
(UF/GN Package)
For auxiliary winding applications, connect to a resistor
divider from the auxiliary output. To synchronize with an
external clock using the PLL, apply a CMOS compatible
clock with a frequency between 250kHz and 850kHz. To
selectBurstModeoperationatlightloads,tiethispintoVIN.
Grounding this pin selects forced continuous operation,
which allows the inductor current to reverse. When
synchronizedtoanexternalclock,pulse-skippingoperation
is enabled at light loads.
SW1/SW2(Pins22,10/Pins1,13):SwitchNodeConnec-
tiontoInductor. Alsothenegativeinputtodifferentialpeak
current comparator and an input to the reverse current
comparator. Normally connected to the drain of the exter-
nalP-channelMOSFETs,thedrainoftheexternalN-channel
MOSFET and the inductor.
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to
SelectMaximumPeakSenseVoltageThreshold.Thesepins
select the maximum allowed voltage drop between the
SENSE+ and SW pins (i.e., the maximum allowed drop
across the external P-channel MOSFET) for each channel.
Tie to VIN, GND or float to select 204mV, 85mV or 125mV
respectively.
BG1/BG2(Pins19,13/Pins22,16):Bottom(NMOS)Gate
Drive Output. These pins drive the gates of the external N-
channel MOSFETs. These pins have an output swing from
PGND to SENSE+.
SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14): Positive
Input to Differential Current Comparator. Also powers the
gate drivers. Normally connected to the source of the ex-
ternal P-channel MOSFET.
VFB1/VFB2(Pins24,7/Pins3,10):FeedbackPins.Receives
theremotelysensedfeedbackvoltageforitscontrollerfrom
an external resistor divider across the output.
U
U
W
FU CTIO AL DIAGRA
(Common Circuitry)
R
VIN
V
IN
(TO CONTROLLER 1, 2)
V
C
IN
VIN
UNDERVOLTAGE
LOCKOUT
VOLTAGE
REFERENCE
0.6V
REF
V
0.7µA
SHDN
RUN/SS
t
= 1ms
+
–
SEC
EXTSS
INTSS
SYNC/FCB
BURSTDIS
BURST DEFEAT/
SYNC DETECT
PHASE
DETECTOR
CLK1
CLK2
PLLLPF
VOLTAGE
CONTROLLED
OSCILLATOR
SLOPE1
SLOPE2
SLOPE
COMP
–
–
V
FB1
UV1
UV2
PGOOD
FCB
FCB
OV1
SHDN
+
+
0.6V
0.54V
IPRG1
IPRG2
MAXIMUM
IPROG1
3736 FD
+
–
OV2
SENSE VOLTAGE
SELECT
IPROG2
V
FB2
3736f
7
LTC3736
U
U
W
FU CTIO AL DIAGRA (Controller 1)
V
IN
+
SENSE1
C
IN
RS1
TG1
CLK1
S
R
Q
MP1
SWITCHING
LOGIC
PGND
SW1
BG1
ANTISHOOT
THROUGH
L1
AND
OV1
SC1
FCB
BLANKING
CIRCUIT
V
OUT1
+
SENSE1
C
OUT1
MN1
PGND
SLEEP1
IREV1
SLOPE1
–
+
SW1
ICMP
+
SENSE1
IPROG1
SHDN
–
R1B
R1A
V
FB1
+
–
EAMP
+
BURSTDIS
0.3V
EXTSS
INTSS
0.6V
I
TH1
–
+
R
SLEEP1
ITH1
0.3V
+
–
C
ITH1
SC1
SCP
BURSTDIS
0.15V
V
FB1
V
PGND
–
+
–
+
FB1
OV1
OVP
IREV1
RICMP
0.68V
SW1
3736 CONT1
IPROG1 FCB
3736f
8
LTC3736
U
U
W
FU CTIO AL DIAGRA (Controller 2)
V
IN
+
SENSE2
RS2
TG2
CLK2
S
R
Q
MP2
SWITCHING
LOGIC
PGND
SW2
BG2
ANTISHOOT
THROUGH
L2
AND
OV2
SC2
FCB
BLANKING
CIRCUIT
V
OUT2
+
SENSE2
C
OUT2
MN2
PGND
SLEEP2
IREV2
SLOPE2
–
+
SW2
ICMP
+
SENSE2
SHDN
–
+
R2B
R2A
V
FB2
+
–
EAMP
BURSTDIS
V
OUT1
R
0.3V
TRACKB
TRACKA
TRACK
0.6V
R
I
TH2
–
+
R
ITH2
SLEEP2
0.3V
+
–
C
ITH2
SC2
SCP
BURSTDIS
V
FB2
0.15V
TRACK
V
PGND
SW2
–
+
–
+
FB2
OV2
OVP
IREV2
0.68V
3736 CONT2
IPROG2 FCB
3736f
9
LTC3736
U
(Refer to Functional Diagram)
OPERATIO
Main Control Loop
rise linearly from approximately 0.65V to 1.3V (being
charged by the internal 0.7µA current source), the EAMP
regulates the VFB1 proportionally linearly from 0V to 0.6V.
The LTC3736 uses a constant frequency, current mode
architecture with the two controllers operating 180 de-
grees out of phase. During normal operation, the top
external P-channel power MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the current comparator (ICMP) resets the latch. The
peak inductor current at which ICMP resets the RS latch is
determined by the voltage on the ITH pin, which is driven
by the output of the error amplifier (EAMP). The VFB pin
receives the output voltage feedback signal from an exter-
nal resistor divider. This feedback signal is compared to
theinternal0.6VreferencevoltagebytheEAMP. Whenthe
load current increases, it causes a slight decrease in VFB
relative to the 0.6V reference, which in turn causes the ITH
voltage to increase until the average inductor current
matches the new load current. While the top P-channel
MOSFET is off, the bottom N-channel MOSFET is turned
on until either the inductor current starts to reverse, as
indicatedbythecurrentreversalcomparator,IRCMP,orthe
beginning of the next cycle.
The start-up of VOUT2 is controlled by the voltage on the
TRACK pin. When the voltage on the TRACK pin is less
than the 0.6V internal reference, the LTC3736 regulates
the VFB2 voltage to the TRACK pin instead of the 0.6V
reference. Typically, a resistor divider on VOUT1 is con-
nected to the TRACK pin to allow the start-up of VOUT2 to
“track”thatofVOUT1.Forone-to-onetrackingduringstart-
up, the resistor divider would have the same values as the
divider on VOUT2 that is connected to VFB2
.
Light Load Operation (Burst Mode or Continuous
Conduction) (SYNC/FCB Pin)
The LTC3736 can be enabled to enter high efficiency Burst
Mode operation or forced continuous conduction mode at
low load currents. To select Burst Mode operation, tie the
SYNC/FCB pin to a DC voltage above 0.6V (e.g., VIN). To
select forced continuous operation, tie the SYNC/FCB to a
DC voltage below 0.6V (e.g., SGND). This 0.6V threshold
betweenBurstModeoperationandforcedcontinuousmode
can be used in secondary winding regulation as described
in the Auxiliary Winding Control Using SYNC/FCB Pin dis-
cussion in the Applications Information section.
Shutdown, Soft-Start and Tracking Start-Up
(RUN/SS and TRACK Pins)
The LTC3736 is shut down by pulling the RUN/SS pin low.
In shutdown, all controller functions are disabled and the
chip draws only 9µA. The TG outputs are held high (off)
and the BG outputs low (off) in shutdown. Releasing
RUN/SS allows an internal 0.7µA current source to charge
up the RUN/SS pin. When the RUN/SS pin reaches 0.65V,
the LTC3736’s two controllers are enabled.
When a controller is in Burst Mode operation, the peak
current in the inductor is set to approximate one-fourth of
the maximum sense voltage even though the voltage on
the ITH pin indicates a lower value. If the average inductor
current is lower than the load current, the EAMP will
decrease the voltage on the ITH pin. When the ITH voltage
drops below 0.85V, the internal SLEEP signal goes high
and both external MOSFETs are turned off.
The start-up of VOUT1 is controlled by the LTC3736’s
internal soft-start. During soft-start, the error amplifier
EAMP compares the feedback signal VFB1 to the internal
soft-startramp(insteadofthe0.6Vreference),whichrises
linearly from 0V to 0.6V in about 1ms. This allows the
output voltage to rise smoothly from 0V to its final value,
while maintaining control of the inductor current.
Insleepmode, muchoftheinternalcircuitryisturnedoff,
reducing the quiescent current that the LTC3736 draws.
The load current is supplied by the output capacitor. As
theoutputvoltagedecreases, theEAMPincreasestheITH
voltage. WhentheITH voltagereaches0.925V, theSLEEP
signal goes low and the controller resumes normal
operation by turning on the external P-channel MOSFET
on the next cycle of the internal oscillator.
The 1ms soft-start time can be increased by connecting
the optional external soft-start capacitor CSS between the
RUN/SS and SGND pins. As the RUN/SS pin continues to
3736f
10
LTC3736
U
(Refer to Functional Diagram)
OPERATIO
WhenacontrollerisenabledforBurstModeoperation, the
inductor current is not allowed to reverse. Hence, the
controller operates discontinuously. The reverse current
comparator (RICMP) senses the drain-to-source voltage
of the bottom external N-channel MOSFET. This MOSFET
is turned off just before the inductor current reaches zero,
preventing it from reversing and going negative.
(VOUT1 = VFB1 = 0V), then the LTC3736 will try to regulate
VOUT2 to 0V if a resistor divider on VOUT1 is connected to
the TRACK pin.
Output Overvoltage Protection
As a further protection, the overvoltage comparator (OV)
guardsagainsttransientovershoots,aswellasothermore
serious conditions that may overvoltage the output. When
the feedback voltage on the VFB pin has risen 13.33%
above the reference voltage of 0.6V, the external P-chan-
nel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions.Thepeakinductorcurrentisdeterminedbythe
voltageontheITH pin. TheP-channelMOSFETisturnedon
every cycle (constant frequency) regardless of the ITH pin
voltage. In this mode, the efficiency at light loads is lower
than in Burst Mode operation. However, continuous mode
has the advantages of lower output ripple and less inter-
ference with audio circuitry.
Frequency Selection and Phase-Locked Loop
(PLLLPF and SYNC/FCB Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increasesefficiencybyreducingMOSFETswitchinglosses,
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage.
When the SYNC/FCB pin is clocked by an external clock
source to use the phase-locked loop (see Frequency
SelectionandPhase-LockedLoop),theLTC3736operates
in PWM pulse skipping mode at light loads. In this mode,
the current comparator ICMP may remain tripped for
severalcyclesandforcetheexternalP-channelMOSFETto
stay off for the same number of cycles. The inductor
current is not allowed to reverse, though (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. However, it provides low current efficiency
higher than forced continuous mode, but not nearly as
high as Burst Mode operation. During start-up or a short-
circuit condition (VFB1 or VFB2 ≤ 0.54V), the LTC3736
operates in pulse skipping mode (no current reversal
allowed), regardless of the state of the SYNC/FCB pin.
The switching frequency of the LTC3736’s controllers can
be selected using the PLLLPF pin.
If the SYNC/FCB is not being driven by an external clock
source, the PLLLPF can be floated, tied to VIN or tied to
SGND to select 550kHz, 750kHz or 300kHz respectively.
A phase-locked loop (PLL) is available on the LTC3736 to
synchronize the internal oscillator to an external clock
source that connected to the SYNC/FCB pin. In this case,
a series RC should be connected between the PLLLPF pin
and SGND to serve as the PLL’s loop filter. The LTC3736
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of controller 1’s external P-channel
MOSFET to the rising edge of the synchronizing signal.
Thus, the turn-on of controller 2’s external P-channel
MOSFET is 180 degrees out of phase with the rising edge
of the external clock source.
Short-Circuit Protection
When an output is shorted to ground (VFB < 0.12V), the
switching frequency of that controller is reduced to 1/5 of
the normal operating frequency. The other controller is
unaffected and maintains normal operation.
The typical capture range of the LTC3736’s phase-locked
loop is from approximately 200kHz to 1MHz, with a
guarantee over all variations and temperature to be be-
tween 250kHz and 850kHz. In other words, the LTC3736’s
PLL is guaranteed to lock to an external clock source
whose frequency is between 250kHz and 850kHz.
Theshort-circuitthresholdonVFB2 isbasedonthesmaller
of 0.12V and a fraction of the voltage on the TRACK pin.
This also allows VOUT2 to start up and track VOUT1 more
easily. Note that if VOUT1 is truly short-circuited
3736f
11
LTC3736
U
(Refer to Functional Diagram)
OPERATIO
peak sense voltage by a scale factor given by the curve in
Figure 1.
Dropout Operation
When the input supply voltage (VIN) decreases towards
the output voltage, the rate of change of the inductor
current while the external P-channel MOSFET is on (ON
cycle)decreases.ThisreductionmeansthattheP-channel
MOSFET will remain on for more than one oscillator cycle
if the inductor current has not ramped up to the threshold
set by the EAMP on the ITH pin. Further reduction in the
input supply voltage will eventually cause the P-channel
MOSFET to be turned on 100%; i.e., DC. The output
voltage will then be determined by the input voltage minus
the voltage drop across the P-channel MOSFET and the
inductor.
Thepeakinductorcurrentisdeterminedbythepeaksense
voltage and the on-resistance of the external P-channel
MOSFET:
∆VSENSE(MAX)
IPK
=
RDS(ON)
110
100
90
80
70
60
50
40
30
20
10
0
Undervoltage Lockout
To prevent operation of the external MOSFETs below safe
inputvoltagelevels,anundervoltagelockoutisincorporated
intheLTC3736.Whentheinputsupplyvoltage(VIN)drops
below 2.3V, the external P- and N-channel MOSFETs and
allinternalcircuitryareturnedoffexceptfortheundervolt-
age block, which draws only a few microamperes.
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3736 F01
Figure 1. Maximum Peak Current vs Duty Cycle
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG1 and IPRG2 Pins)
Power Good (PGOOD) Pin
When a controller is operating below 20% duty cycle, the
peak current sense voltage (between the SENSE+ and SW
pins) allowed across the external P-channel MOSFET is
determined by:
A window comparator monitors both feedback voltages
and the open-drain PGOOD output pin is pulled low when
either or both feedback voltages are not within ±10% of
the 0.6V reference voltage. PGOOD is low when the
LTC3736 is shut down or in undervoltage lockout.
A V – 0.7V
(
)
ITH
∆VSENSE(MAX)
=
10
2-Phase Operation
where A is a constant determined by the state of the IPRG
pins. Floating the IPRG pin selects A = 1; tying IPRG to VIN
selects A = 5/3; tying IPRG to SGND selects A = 2/3. The
maximum value of VITH is typically about 1.98V, so the
maximum sense voltage allowed across the external
P-channel MOSFET is 125mV, 85mV or 204mV for the
three respective states of the IPRG pin. The peak sense
voltages for the two controllers can be independently
selected by the IPRG1 and IPRG2 pins.
Why the need for 2-phase operation? Until recently, con-
stant frequency dual switching regulators operated both
controllers in phase (i.e., single phase operation). This
means that both topside MOSFETs (P-channel) are turned
on at the same time, causing current pulses of up to twice
the amplitude of those from a single regulator to be drawn
from the input capacitor. These large amplitude pulses
increase the total RMS current flowing in the input capaci-
tor, requiring the use of larger and more expensive input
capacitors, and increase both EMI and power losses in the
input capacitor and input power supply.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
3736f
12
LTC3736
U
(Refer to Functional Diagram)
OPERATIO
With2-phaseoperation,thetwocontrollersoftheLTC3736
are operated 180 degrees out of phase. This effectively
interleaves the current pulses coming from the topside
MOSFET switches, greatly reducing the time where they
overlap and add together. The result is a significant
reductioninthetotalRMScurrent,whichinturnallowsthe
use of smaller, less expensive input capacitors, reduces
shielding requirements for EMI and improves real world
operating efficiency.
The reduced input ripple current also means that less
power is lost in the input power path, which could include
batteries, switches, trace/connector resistances, and pro-
tection circuitry. Improvements in both conducted and
radiated EMI also directly accrue as a result of the reduced
RMS input current and voltage. Significant cost and board
footprint savings are also realized by being able to use
smaller, less expensive, lower RMS current-rated input
capacitors.
Figure 2 shows qualitatively example waveforms for a
single phase dual controller versus a 2-phase LTC3736
system. In this case, 2.5V and 1.8V outputs, each drawing
a load current of 2A, are derived from a 7V (e.g., a 2-cell
Li-Ion battery) input supply. In this example, 2-phase
operation would reduce the RMS input capacitor current
from 1.79ARMS to 0.91ARMS. While this is an impressive
reduction by itself, remember that power losses are pro-
portional to IRMS2, meaning that actual power wasted is
reduced by a factor of 3.86.
Of course, the improvement afforded by 2-phase opera-
tion is a function of the relative duty cycles of the two
controllers, which in turn are dependent upon the input
supply voltage. Figure 3 depicts how the RMS input
current varies for single phase and 2-phase dual control-
lers with 2.5V and 1.8V outputs over a wide input voltage
range.
It can be readily seen that the advantages of 2-phase
operation are not limited to a narrow operating range, but
in fact extend over a wide region. A good rule of thumb for
mostapplicationsisthat2-phaseoperationwillreducethe
input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
Single Phase
2-Phase
Dual Controller
Dual Controller
SW1 (V)
SW2 (V)
2.0
1.8
SINGLE PHASE
1.6
DUAL CONTROLER
1.4
2-PHASE
1.2
1.0
0.8
0.6
0.4
0.2
0
DUAL CONTROLER
I
I
L1
L2
V
V
= 2.5V/2A
= 1.8V/2A
OUT1
OUT2
2
6
8
9
3
4
5
7
10
INPUT VOLTAGE (V)
3736 F03
I
IN
Figure 3. RMS Input Current Comparison
3736 F02
Figure 2. Example Waveforms for a Single Phase
Dual Controller vs the 2-Phase LTC3736
3736f
13
LTC3736
W U U
U
APPLICATIO S I FOR ATIO
The typical LTC3736 application circuit is shown in Fig-
ure 13. External component selection for each of the
LTC3736’s controllers is driven by the load requirement
and begins with the selection of the inductor (L) and the
power MOSFETs (MP and MN).
A reasonable starting point is setting ripple current IRIPPLE
to be 40% of IOUT(MAX). Rearranging the above equation
yields:
∆VSENSE(MAX)
5
DS(ON)(MAX) = •
6
R
IOUT(MAX)
Power MOSFET Selection
for Duty Cycle < 20%.
Each of the LTC3736’s two controllers requires two exter-
nal power MOSFETs: a P-channel MOSFET for the topside
(main) switch and an N-channel MOSFET for the bottom
(synchronous)switch.Importantparametersforthepower
MOSFETs are the breakdown voltage VBR(DSS) , threshold
voltage VGS(TH) , on-resistance RDS(ON) , reverse transfer
capacitance CRSS, turn-off delay tD(OFF) and the total gate
charge QG.
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of RDS(ON) to provide the required
amount of load current:
∆VSENSE(MAX)
5
R
DS(ON)(MAX) = • SF •
6
IOUT(MAX)
Thegatedrivevoltageistheinputsupplyvoltage.Sincethe
LTC3736 is designed for operation down to low input
voltages, a sublogic level MOSFET (RDS(ON) guaranteed at
VGS = 2.5V) is required for applications that work close to
this voltage. When these MOSFETs are used, make sure
that the input supply to the LTC3736 is less than the abso-
lute maximum MOSFET VGS rating, which is typically 8V.
whereSFisascalefactorwhosevalueisobtainedfromthe
curve in Figure 1.
These must be further derated to take into account the
significant variation in on-resistance with temperature.
Thefollowingequationisagoodguidefordeterminingthe
required RDS(ON)MAX at 25°C (manufacturer’s specifica-
tion), allowing some margin for variations in the LTC3736
and external component values:
The P-channel MOSFET’s on-resistance is chosen based
on the required load current. The maximum average
output load current IOUT(MAX) is equal to the peak inductor
∆VSENSE(MAX)
IOUT(MAX) • ρT
5
6
R
DS(ON)(MAX) = • 0.9 • SF •
current minus half the peak-to-peak ripple current IRIPPLE
.
TheLTC3736’scurrentcomparatormonitorsthedrain-to-
source voltage VDS of the P-channel MOSFET, which is
sensed between the SENSE+ and SW pins. The peak
inductor current is limited by the current threshold, set by
the voltage on the ITH pin of the current comparator. The
voltage on the ITH pin is internally clamped, which limits
the maximum current sense threshold ∆VSENSE(MAX) to
approximately 128mV when IPRG is floating (86mV when
IPRG is tied low; 213mV when IPRG is tied high).
The ρT is a normalizing term accounting for the tempera-
ture variation in on-resistance, which is typically about
0.4%/°C, as shown in Figure 4. Junction to case tempera-
ture TJC is about 10°C in most applications. For a maxi-
mum ambient temperature of 70°C, using ρ80°C ~ 1.3 in
the above equation is a reasonable choice.
The power dissipated in the top and bottom MOSFETs
strongly depends on their respective duty cycles and load
current. When the LTC3736 is operating in continuous
mode, the duty cycles for the MOSFETs are:
The output current that the LTC3736 can provide is given
by:
∆VSENSE(MAX)
VOUT
V
IN
IRIPPLE
Top P-Channel Duty Cycle =
IOUT(MAX)
=
–
RDS(ON)
2
V – VOUT
IN
Bottom N-Channel Duty Cycle =
V
IN
3736f
14
LTC3736
W U U
APPLICATIO S I FOR ATIO
U
less than 25nC to 30nC (at 4.5VGS) and a turn-off delay
(tD(OFF)) of less than approximately 140ns. However, due
to differences in test and specification methods of various
MOSFET manufacturers, and in the variations in QG and
tD(OFF)withgatedrive(VIN)voltage,theP-channelMOSFET
ultimately should be evaluated in the actual LTC3736
application circuit to ensure proper operation.
2.0
1.5
1.0
0.5
0
Shoot-through between the P-channel and N-channel
MOSFETs can most easily be spotted by monitoring the
input supply current. As the input supply voltage in-
creases,iftheinputsupplycurrentincreasesdramatically,
then the likely cause is shoot-through. Note that some
MOSFETsthatdonotworkwellathighinputvoltages(e.g.,
VIN > 5V) may work fine at lower voltages (e.g., 3.3V).
Table 1 shows a selection of P-channel MOSFETs from
different manufacturers that are known to work well in
LTC3736 applications.
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
3736 F04
Figure 4. RDS(ON) vs Temperature
The MOSFET power dissipations at maximum output
current are:
Selecting the N-channel MOSFET is typically easier, since
for a given RDS(ON), the gate charge and turn-on and turn-
off delays are much smaller than for a P-channel MOSFET.
VOUT
V
IN
2
PTOP
=
•IOUT(MAX)2 • ρT •RDS(ON) +k • V
IN
•IOUT(MAX) • ρT •RDS(ON)
Table 1. Selected P-Channel MOSFETs Suitable for LTC3736
Applications
V – VOUT
IN
P
BOT
=
•IOUT(MAX)2 • ρT •RDS(ON)
PART
V
IN
NUMBER
MANUFACTURER
TYPE
PACKAGE
Si7540DP
Siliconix
Complementary
P/N
PowerPak
SO-8
Both MOSFETs have I2R losses and the PTOP equation
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The constant k = 2A–1 can
be used to estimate the amount of transition loss. The
bottom MOSFET losses are greatest at high input voltage
or during a short circuit when the bottom duty cycle is
nearly 100%.
Si9801DY
FDW2520C
FDW2521C
Siliconix
Fairchild
Fairchild
Complementary
P/N
SO-8
Complementary
P/N
TSSOP-8
TSSOP-8
Complementary
P/N
Si3447BDV
Si9803DY
FDC602P
Siliconix
Siliconix
Fairchild
Fairchild
Fairchild
Fairchild
Fairchild
Hitachi
Single P
Single P
Single P
Single P
Single P
Dual P
TSOP-6
SO-8
TheLTC3736utilizesanonoverlapping,antishoot-through
gate drive control scheme to ensure that the P- and
N-channel MOSFETs are not turned on at the same time.
To function properly, the control scheme requires that the
MOSFETs used are intended for DC/DC switching applica-
tions. Many power MOSFETs, particularly P-channel
MOSFETs, are intended to be used as static switches and
therefore are slow to turn on or off.
TSOP-6
TSOP-6
TSOP-6
TSSOP-8
SO-8
FDC606P
FDC638P
FDW2502P
FDS6875
Dual P
HAT1054R
NTMD6P02R2-D
Dual P
SO-8
On Semi
Dual P
SO-8
Reasonable starting criteria for selecting the P-channel
MOSFET are that it must typically have a gate charge (QG)
3736f
15
LTC3736
W U U
U
APPLICATIO S I FOR ATIO
operation. When bursting, the controller clamps the peak
inductor current to approximately:
Operating Frequency and Synchronization
The choice of operating frequency, fOSC, is a trade-off
between efficiency and component size. Low frequency
operationimprovesefficiencybyreducingMOSFETswitch-
ing losses, both gate charge loss and transition loss.
However, lowerfrequencyoperationrequiresmoreinduc-
tance for a given amount of ripple current.
∆VSENSE(MAX)
1
4
I
BURST(PEAK) = •
RDS(ON)
Thecorrespondingaveragecurrentdependsontheamount
of ripple current. Lower inductor values (higher IRIPPLE
)
willreducetheloadcurrentatwhichBurstModeoperation
begins.
The internal oscillator for each of the LTC3736’s control-
lersrunsatanominal550kHzfrequencywhenthePLLLPF
pin is left floating and the SYNC/FCB pin is a DC low or
high. Pulling the PLLLPF to VIN selects 750kHz operation;
pulling the PLLLPF to GND selects 300kHz operation.
The ripple current is normally set so that the inductor
current is continuous during the burst periods. Therefore:
IRIPPLE ≤ IBURST(PEAK)
Alternatively,theLTC3736willphase-locktoaclocksignal
applied to the SYNC/FCB pin with a frequency between
250kHz and 850kHz (see Phase-Locked Loop and Fre-
quency Synchronization).
This implies a minimum inductance of:
V – VOUT
VOUT
IN
LMIN
≤
•
fOSC •IBURST(PEAK)
V
IN
A smaller value than LMIN could be used in the circuit,
although the inductor current will not be continuous
during burst periods, which will result in slightly lower
efficiency. In general, though, it is a good idea to keep
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency fOSC directly determine the
inductor’s peak-to-peak ripple current:
IRIPPLE comparable to IBURST(PEAK)
.
VOUT V – VOUT
IN
Inductor Core Selection
IRIPPLE
=
V
fOSC •L
IN
Once the inductance value is determined, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of ferrite, molyper-
malloy or Kool Mµ® cores. Actual core loss is independent
of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance in-
creases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
V – VOUT VOUT
IN
L ≥
•
fOSC •IRIPPLE
V
IN
Burst Mode Operation Considerations
The choice of RDS(ON) and inductor value also determines
the load current at which the LTC3736 enters Burst Mode
Kool Mµ is a registered trademark of Magnetics, Inc.
3736f
16
LTC3736
W U U
APPLICATIO S I FOR ATIO
U
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
usedfordesignbecauseevensignificantdeviationsdonot
offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design.DuetothehighoperatingfrequencyoftheLTC3736,
ceramic capacitors can also be used for CIN. Always
consult the manufacturer if there is any question.
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturerisKoolMµ. Toroidsareveryspaceefficient,
especially when you can use several layers of wire.
Because they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
Schottky Diode Selection (Optional)
The Schottky diodes D1 and D2 in Figure 16 conduct
current during the dead time between the conduction of
the power MOSFETs . This prevents the body diode of the
bottom N-channel MOSFET from turning on and storing
charge during the dead time, which could cost as much as
1% in efficiency. A 1A Schottky diode is generally a good
size for most LTC3736 applications, since it conducts a
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance. This diode may be omitted if the efficiency
loss can be tolerated.
The benefit of the LTC3736 2-phase operation can be cal-
culated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
currentpulsesrequiredthroughtheinputcapacitor’sESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Also, the input protection fuse re-
sistance,batteryresistance,andPCboardtraceresistance
losses are also reduced due to the reduced peak currents
in a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source imped-
ance of the power supply/battery is included in the effi-
ciency testing. The sources of the P-channel MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may pro-
duce undesirable voltage and current resonances at VIN.
CIN and COUT Selection
The selection of CIN is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The control-
ler with the highest (VOUT)(IOUT) product needs to be used
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output cur-
rent drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3736, is also
suggested. A 10Ω resistor placed between CIN (C1) and
the VIN pin provides further isolation between the two
channels.
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (VOUT)/(VIN). To
preventlargevoltagetransients, alowESRcapacitorsized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
1
∆VOUT ≈ IRIPPLE ESR +
1/2
]
IMAX
V
IN
CIN Required IRMS
≈
V
OUT)(
V – V
IN OUT
(
[
)
8fCOUT
3736f
17
LTC3736
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APPLICATIO S I FOR ATIO
3.3V OR 5V
RUN/SS
RUN/SS
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
D1
C
SS
C
SS
3736 F06
Setting Output Voltage
Figure 6. RUN/SS Pin Interfacing
The LTC3736 output voltages are each set by an external
feedback resistor divider carefully placed across the out-
put, as shown in Figure 5. The regulated output voltage is
determined by:
function. This diode (and capacitor) can be deleted if the
external soft-start is not needed.
During soft-start, the start-up of VOUT1 is controlled by
slowlyrampingthepositivereferencetotheerroramplifier
from 0V to 0.6V, allowing VOUT1 to rise smoothly from 0V
toitsfinalvalue. Thedefaultinternalsoft-starttimeis1ms.
This can be increased by placing a capacitor between the
RUN/SSpinandSGND. Inthiscase, thesoft-starttimewill
be approximately:
RB
VOUT = 0.6V • 1+
RA
To improve the frequency response, a feed-forward ca-
pacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
600mV
t
SS1 = CSS
•
V
OUT
0.7µA
R
B
C
FF
Tracking
1/2 LTC3736
V
FB
The start-up of VOUT2 is controlled by the voltage on the
TRACK pin. Normally this pin is used to allow the start-up
of VOUT2 to track that of VOUT1 as shown qualitatively in
Figures 7a and 7b. When the voltage on the TRACK pin is
less than the internal 0.6V reference, the LTC3736 regu-
lates the VFB2 voltage to the TRACK pin voltage instead of
0.6V. The start-up of VOUT2 may ratiometrically track that
of VOUT1, according to a ratio set by a resistor divider
(Figure 7c):
R
A
3736 F05
Figure 5. Setting Output Voltage
Run/Soft Start Function
The RUN/SS pin is a dual purpose pin that provides the
optional external soft-start function and a means to shut
down the LTC3736.
VOUT1
VOUT2 RTRACKA
R2A
R
TRACKA +RTRACKB
R2B +R2A
=
•
Pulling the RUN/SS pin below 0.7V puts the LTC3736 into
a low quiescent current shutdown mode (IQ = 9µA). If
RUN/SS has been pulled all the way to ground, there will
beadelaybeforetheLTC3736comesoutofshutdownand
is given by:
V
OUT1
V
OUT2
LTC3736
R1B
R2B
V
FB1
V
FB2
R1A
R2A
CSS
0.7µA
R
tDELAY = 0.7V •
= 1s/µF •CSS
TRACKB
TRACK
3736 F07a
R
TRACKA
This pin can be driven directly from logic as shown in
Figure 6. Diode D1 in Figure 6 reduces the start delay but
allows CSS to ramp up slowly providing the soft-start
Figure 7a. Using the TRACK Pin
3736f
18
LTC3736
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APPLICATIO S I FOR ATIO
U
V
V
V
OUT1
OUT1
OUT2
V
OUT2
3736 F07b,c
TIME
TIME
(7b) Coincident Tracking
(7c) Ratiometric Tracking
Figures 7b and 7c. Two Different Modes of Output Voltage Tracking
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics of
the external clock.
For coincident tracking (VOUT1 = VOUT2 during start-up),
R2A = RTRACKA
R2B = RTRACKB
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
FCB, is shown in Figure 8 and specified in the Electrical
Characteristics table. Note that the LTC3736 can only be
synchronized to an external clock whose frequency is
within range of the LTC3736’s internal VCO, which is
nominally 200kHz to 1MHz. This is guaranteed, over
temperature and variations, to be between 300kHz and
750kHz. A simplified block diagram is shown in Figure 9.
The ramp time for VOUT2 to rise from 0V to its final value
is:
RTRACKA
R1A
R1A +R1B
TRACKA +RTRACKB
t
SS2 = tSS1
•
•
R
For coincident tracking,
VOUT2F
VOUT1F
t
SS2 = tSS1 •
where VOUT1F and VOUT2F are the final, regulated values of
VOUT1 and VOUT2. VOUT1 should always be greater than
VOUT2 when using the TRACK pin. If no tracking function
is desired, then the TRACK pin may be tied to VIN. How-
ever, in this situation there would be no (internal nor
1400
1200
1000
800
600
400
200
0
external) soft-start on VOUT2
.
Phase-Locked Loop and Frequency Synchronization
The LTC3736 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the external P-
channel MOSFET of controller 1 to be locked to the rising
edge of an external clock signal applied to the SYNC/FCB
pin. The turn-on of controller 2’s external P-channel
MOSFET is thus 180 degrees out of phase with the
external clock. The phase detector is an edge sensitive
digital type that provides zero degrees phase shift
0
0.5
1
1.5
2
2.4
PLLLPF PIN VOLTAGE (V)
3736 F08
Figure 8. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
3736f
19
LTC3736
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APPLICATIO S I FOR ATIO
2.4V
R
LP
C
LP
PLLLPF
SYNC/
FCB
DIGITAL
PHASE/
EXTERNAL
OSCILLATOR
FREQUENCY
DETECTOR
OSCILLATOR
3736 F09
Figure 9. Phase-Locked Loop Block Diagram
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPFpin.Whentheexternalclockfrequencyislessthan
fOSC, current is sunk continuously, pulling down the
PLLLPFpin. Iftheexternalandinternalfrequenciesarethe
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage on the PLLLPF pin is adjusted until
the phase and frequency of the external oscillators are
identical. At the stable operating point, the phase detector
outputishighimpedanceandthefiltercapacitorCLP holds
the voltage.
Auxiliary Winding Control Using SYNC/FCB Pin
The SYNC/FCB can be used as an auxiliary feedback to
provide a means of regulating a flyback winding output.
When this pin drops below its ground-referenced 0.6V
threshold, continuous mode operation is forced.
During continuous mode, current flows continuously in
the transformer primary. The auxiliary winding draws
current only when the bottom, synchronous N-channel
MOSFET is on. When primary load currents are low and/or
the VIN/VOUT ratio is close to unity, the synchronous
MOSFET may not be on for a sufficient amount of time to
transfer power from the output capacitor to the auxiliary
load. Forced continuous operation will support an auxil-
iary winding as long as there is a sufficient synchronous
MOSFET duty factor. The FCB input pin removes the
requirement that power must be drawn from the trans-
formerprimaryinordertoextractpowerfromtheauxiliary
winding. With the loop in continuous mode, the auxiliary
output may nominally be loaded without regard to the
primary output load.
The loop filter components, CLP and RLP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01µF.
Typically, the external clock (on SYNC/FCB pin) input high
level is 1.6V, while the input low level is 1.2V.
TheauxiliaryoutputvoltageVAUX isnormallysetasshown
in Figure 10 by the turns ratio N of the transformer:
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
VAUX (N + 1) VOUT
Table 2
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then VAUX will droop. An external resistor divider from
PLLLPF PIN
0V
SYNC/FCB PIN
DC Voltage
DC Voltage
DC Voltage
Clock Signal
FREQUENCY
300kHz
550kHz
Floating
VAUX to the FCB sets a minimum voltage VAUX(MIN)
:
V
IN
750kHz
RC Loop Filter
Phase-Locked to External Clock
R6
R5
VAUX(MIN) = 0.6V 1+
3736f
20
LTC3736
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APPLICATIO S I FOR ATIO
U
V
OUT
1/2 LTC3736
R2
R1
V
D
D
AUX
V
IN
+
FB1
+
I
V
FB
TH
LTC3736
TG
L1
1:N
1µF
FB2
R6
R5
V
OUT
SYNC/FCB
3736 F11
SW
BG
+
C
OUT
Figure 11. Foldback Current Limiting
3736 F10
105
Figure 10. Auxiliary Output Loop Connection
V
REF
100
If VAUX drops below this value, the FCB voltage forces
temporary continuous switching operation until VAUX is
again above its minimum.
95
90
MAXIMUM
SENSE VOLTAGE
Table 3 summarizes the different states in which the
SYNC/FCB pin can be used
85
80
75
Table 3
SYNC/FCB PIN
CONDITION
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
0V to 0.5V
Forced Continuous Mode
Current Reversal Allowed
3736 F12
0.7V to V
Burst Mode Operation Enabled
No Current Reversal Allowed
IN
Figure 12. Line Regulation of VREF and
Maximum Sense Voltage for Low Input Supply
Feedback Resistors
External Clock Signal
Regulate an Auxiliary Winding
Enable Phase-Locked Loop
(Synchronize to External CLK)
Pulse-Skipping at Light Loads
No Current Reversal Allowed
Minimum On-Time Considerations
Minimumon-time,tON(MIN),isthesmallestamountoftime
in which the LTC3736 is capable of turning the top
P-channel MOSFET on and then off. It is determined by
internal timing delays and the gate charge required to turn
on the top MOSFET. Low duty cycle and high frequency
applications may approach the minimum on-time limit
and care should be taken to ensure that:
Fault Condition: Short Circuit and Current Limit
To prevent excessive heating of the bottom MOSFET,
foldback current limiting can be added to reduce the
current in proportion to the severity of the fault.
VOUT
OSC • V
Foldback current limiting is implemented by adding di-
odes DFB1 and DFB2 between the output and the ITH pin as
showninFigure11.Inahardshort(VOUT=0V),thecurrent
will be reduced to approximately 50% of the maximum
output current.
tON(MIN)
<
f
IN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3736 will begin to skip
cycles (unless forced continuous mode is selected). The
output voltage will continue to be regulated, but the ripple
currentandripplevoltagewillincrease. Theminimumon-
time for the LTC3736 is typically about 250ns. However,
as the peak sense voltage (IL(PEAK) • RDS(ON)) decreases,
the minimum on-time gradually increases up to about
300ns. This is of particular concern in forced continuous
Low Supply Operation
Although the LTC3736 can function down to below 2.4V,
the maximum allowable output current is reduced as VIN
decreases below 3V. Figure 12 shows the amount of
changeasthesupplyisreduceddownto2.4V. Alsoshown
is the effect on VREF
.
applicationswithlowripplecurrentatlightloads.Ifforced
3736f
21
LTC3736
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APPLICATIO S I FOR ATIO
continuousmodeisselectedandthedutycyclefallsbelow
theminimumon-timerequirement,theoutputwillberegu-
lated by overvoltage protection.
Other losses, including CIN and COUT ESR dissipative
lossesandinductorcorelosses,generallyaccountforless
than 2% total additional loss.
Efficiency Considerations
Checking Transient Response
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
oftenusefultoanalyzeindividuallossestodeterminewhat
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD)(ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or dis-
chargeCOUT, whichgeneratesafeedbackerrorsignal. The
regulator loop then returns VOUT to its steady-state value.
Duringthisrecoverytime,VOUT canbemonitoredforover-
shoot or ringing. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
Efficiency = 100% – (L1 + L2 + L3 + …)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3736 circuits: 1) LTC3736 DC bias current,
2) MOSFET gate charge current, 3) I2R losses, and
4) transition losses.
The ITH series RC-CC filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The ITH exter-
nal components shown in the Typical Application on the
front page of this data sheet will provide an adequate
starting point for most applications. The values can be
modified slightly (from 0.2 to 5 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type and
value have been determined. The output capacitors need
to be decided upon because the various types and values
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1µs to 10µs will produce output
voltage and ITH pin waveforms that will give a sense of the
overall loop stability. The gain of the loop will be increased
by increasing RC, and the bandwidth of the loop will be
increased by decreasing CC. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
1) The VIN (pin) current is the DC supply current, given in
the electrical characteristics, excluding MOSFET driver
currents. VIN current results in a small loss that in-
creases with VIN.
2) MOSFETgatechargecurrentresultsfromswitchingthe
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from SENSE+ to ground.
The resulting dQ/dt is a current out of SENSE+, which is
typically much larger than the DC supply current. In
continuous mode, IGATECHG = f • QP.
3) I2R losses are calculated from the DC resistances of the
MOSFETs and inductor. In continuous mode, the aver-
age output current flows through L but is “chopped”
between the top P-channel MOSFET and the bottom
N-channel MOSFET. The MOSFET RDS(ON)s multiplied
by duty cycle can be summed with the resistance of L
to obtain I2R losses.
4) Transition losses apply to the top external P-channel
MOSFET and increase with higher operating frequen-
cies and input voltages. Transition losses can be esti-
mated from:
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
Transition Loss = 2 (VIN)2IO(MAX) RSS
(f)
C
deliver enough current to prevent this problem if the load
3736f
22
LTC3736
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APPLICATIO S I FOR ATIO
U
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(CLOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
loop of the other channel. Ideally, the drains of the P- and
N-channel FETs should be connected close to one another
with an input capacitor placed across the FET sources
(from the P-channel source to the N-channel source) right
attheFETs.Itisbettertohavetwoseparate,smallervalued
input capacitors (e.g., two 10µF—one for each channel)
than it is to have a single larger valued capacitor (e.g.,
22µF) that the channels share with a common connection.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3736. Theseitemsareillustratedinthelayoutdiagram
of Figure 13. Figure 14 depicts the current waveforms
present in the various branches of the 2-phase dual
regulator.
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor divid-
ers, ITH compensation networks and the SGND pin.
The power grounds consist of the (–) terminal of the input
and output capacitors and the source of the N-channel
MOSFET. Eachchannelshouldhaveitsownpowerground
for its power loop (as described in (1) above). The power
grounds for the two channels should connect together at
a common point. It is most important to keep the ground
paths with high switching currents away from each other.
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small as
possible and isolated as much as possible from the power
+
C
OUT1
V
OUT1
The PGND pins on the LTC3736 IC should be shorted
together and connected to the common power ground
connection (away from the switching currents).
L1
LTC3736EGN
1
2
24
23
22
21
20
19
18
17
16
15
14
13
+
SENSE1
SW1
PGND
BG1
IPRG1
3
3) Put the feedback resistors close to the VFB pins. The
trace connecting the top feedback resistor (RB) to the
outputcapacitorshouldbeaKelvintrace.TheITHcompen-
sation components should also be very close to the
LTC3736.
4) The current sense traces (SENSE+ and SW) should be
Kelvin connections right at the P-channel MOSFET source
and drain.
MN1
VIN1
MP1
V
FB1
TH1
C
4
SYNC/FCB
TG1
I
5
IPRG2
PLLLPF
SGND
C
VIN
6
PGND
TG2
V
IN
7
C
8
VIN2
RUN/SS
BG2
V
IN
9
MN2
MP2
TRACK
10
11
12
PGND
V
FB2
TH2
+
SENSE2
I
SW2
PGOOD
L2
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-signal
components, especially the opposite channels feedback
resistors, ITH compensation components and the current
sense pins (SENSE+ and SW).
+
V
OUT2
C
OUT2
3736 F13
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 13. LTC3736 Layout Diagram
3736f
23
LTC3736
APPLICATIO S I FOR ATIO
W U U
U
MP1
L1
V
OUT1
+
C
OUT1
R
L1
MN1
V
IN
R
IN
+
C
IN
MP2
L2
V
OUT2
+
C
OUT2
R
L2
MN2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH
3736 F14
Figure 14. Branch Current Waveforms
U
TYPICAL APPLICATIO S
R
R
FB1B
187k
FB1A
59k
L1
1.5µH
C
ITH1A
V
MP1
OUT1
22
23
24
1
2
3
100pF
21
20
19
18
17
16
15
+
SW1
IPRG1
SENSE1
2.5V
5A
PGND
BG1
SYNC/FCB
TG1
MN1
Si7540DP
V
FB1
+
C
OUT1
I
TH1
150µF
R
ITH1
15k
IPRG2
PLLLPF
SGND
C
ITH1
PGND
TG2
220pF
4
V
IN
5V
R
10Ω
LTC3736EUF
IN
VIN
5
14
C
IN
V
RUN/SS
10µF
×2
13
12
11
MN2
Si7540DP
C
BG2
OUT2
9
7
8
6
C
ITH2
220pF
+
150µF
PGND
PGOOD
V
1.8V
5A
C
VIN
1µF
OUT2
+
V
FB2
SENSE2
MP2
I
L2
1.5µH
TH2
TRACK
PGND
10
R
ITH2
15k
SW2
C
SS
25
C
ITH2B
100pF
10nF
R
FB2A
59k
R
FB2B
118k
R
R
TRACKA
59k
TRACKB
118k
3736 F15
Figure 15. 2-Phase, 550kHz, Dual Output Synchronous DC/DC Converter
3736f
24
LTC3736
U
TYPICAL APPLICATIO S
R
R
FB1A
59k
FB1B
187k
L1
MP1
C
ITH1A
1.5µH
V
2.5V
2A
Si3447BDV
OUT1
22
23
24
1
2
3
100pF
21
20
19
18
17
16
15
+
SW1
IPRG1
SENSE1
PGND
BG1
SYNC/FCB
TG1
D1
MN1
V
I
FB1
C
22µF
×2
OUT1
Si3460DV
TH1
R
ITH1
IPRG2
PLLLPF
SGND
C
ITH1
22k
PGND
TG2
470pF
4
V
IN
3.3V
R
10Ω
LTC3736EUF
IN
VIN
5
14
V
RUN/SS
C
IN
D2
C
22µF
×2
OUT2
22µF
13
12
11
MN2
Si3460DV
BG2
9
7
8
6
C
ITH2
PGND
PGOOD
V
1.8V
2A
C
1µF
OUT2
470pF
VIN
+
V
SENSE2
FB2
MP2
Si3447BDV
I
L2
1.5µH
TH2
10
R
ITH2
TRACK
PGND
SW2
22k
C
SS
25
C
ITH2A
10nF
100pF
R
R
FB2B
118k
FB2A
R
R
TRACKA
59k
TRACKB
118k
59k
3736 F16
L1, L2: VISHAY IHLP-2525CZ-01
Figure 16. 2-Phase, 750kHz, Dual Output Synchronous DC/DC Converter with Ceramic Output Capacitors
C
FF1
100pF
R
R
FB1B
FB1A
59k
187k
CLK IN
MP1
L1
C
ITH1
1.5µH
V
2.5V
3A
OUT1
R
ITH1
15k
SW1
1
220pF
24
23
22
21
20
19
18
+
SW1
IPRG1
SENSE1
2
3
4
5
6
7
PGND
BG1
SYNC/FCB
TG1
MN1
Si7540DP
V
FB1
+
C
C
LP
OUT1
I
TH1
R
10nF
LP
150µF
IPRG2
PLLLPF
SGND
15k
PGND
TG2
V
IN
3.3V
R
10Ω
LTC3736EGN
IN
VIN
5
17
V
RUN/SS
C
IN
22µF
16
15
14
MN2
C
BG2
OUT2
12
10
11
9
C
Si7540DP
ITH2
+
150µF
PGND
PGOOD
V
1.8V
4A
C
OUT2
220pF
VIN
+
V
SENSE2
1µF
FB2
MP2
SW2
I
L2
1.5µH
TH2
13
R
ITH2
TRACK
SW2
15k
R
R
R
FB2A
FB2B R
TRACKB
TRACKA
59k
59k
118k
118k
3736 F17
C
, C
: SANYO 4TPB150MC
OUT1 OUT2
L1, L2: VISHAY IHLP-2525CZ-01
C
FF1
100pF
Figure 17. 2-Phase, Synchronizable, Dual Output Synchronous DC/DC Converter
3736f
25
LTC3736
TYPICAL APPLICATIO S
U
2-Phase, 550kHz, Dual Output Synchronous DC/DC Converter with Different Power Stage Input Supplies
R
R
FB1B
187k
FB1A
59k
L1
1.5µH
C
ITH1A
V
2.5V
5A
MP1
OUT1
22
23
24
1
2
3
100pF
21
20
19
18
17
16
15
+
SW1
IPRG1
SENSE1
PGND
BG1
SYNC/FCB
TG1
MN1
Si7540DP
V
FB1
+
C
OUT1
I
TH1
150µF
R
ITH1
IPRG2
PLLLPF
SGND
C
ITH1
15k
PGND
TG2
220pF
4
V
IN1
5V
R
10Ω
LTC3736EUF
IN
VIN
5
14
C
IN
V
RUN/SS
10µF
×2
13
12
11
MN2
Si7540DP
C
BG2
OUT2
9
7
8
6
C
ITH2
+
150µF
PGND
PGOOD
V
1.8V
4A
C
OUT2
220pF
VIN
+
V
FB2
SENSE2
1µF
MP2
I
L2
1.5µH
TH2
10
R
ITH2
TRACK
PGND
25
SW2
15k
C
10nF
SS
C
ITH2B
100pF
R
R
FB2B
118k
FB2A
R
R
TRACKB
118k
TRACKA
59k
59k
3736 TA03
V
C
, C
: SANYO 4TPB150MC
V
IN1
V
IN2
≥ V
IN2
≥ 2.5V
IN2
OUT1 OUT2
3.3V
L1, L2: VISHAY IHLP-2525CZ-01
2-Phase, 550kHz, Dual Output Synchronous DC/DC Converter with DDR Memory Termination Supply
R
R
FB1B
187k
FB1A
59k
L1
1.5µH
C
ITH1A
V
2.5V
5A
MP1
OUT1
22
23
24
1
2
3
100pF
21
20
19
18
17
16
15
+
SW1
IPRG1
SENSE1
PGND
BG1
SYNC/FCB
TG1
MN1
Si7540DP
V
FB1
+
C
OUT1
I
TH1
150µF
R
ITH1
IPRG2
PLLLPF
SGND
C
ITH1
15k
PGND
TG2
220pF
4
V
IN
5V
R
10Ω
LTC3736EUF
IN
VIN
5
14
C
IN
V
RUN/SS
10µF
×2
13
12
11
MN2
Si7540DP
C
BG2
OUT2
9
7
8
6
C
ITH2
V
+
150µF
OUT2
PGND
PGOOD
C
220pF
VIN
1.25V DDR
+
V
SENSE2
1µF
FB2
TERMINATION
±2A (SINK/SOURCE)
MP2
I
L2
1.5µH
TH2
10
R
ITH2
TRACK
PGND
25
SW2
15k
5Ω
C
10nF
SS
C
ITH2B
100pF
1µF
R
R
FB2B
118k
FB2A
R
R
TRACKB
118k
TRACKA
59k
59k
3736 TA04
3.3V
C
, C
: SANYO 4TPB150MC
OUT1 OUT2
165Ω
L1, L2: VISHAY IHLP-2525CT01
3736f
26
LTC3736
U
PACKAGE DESCRIPTIO
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
(4 SIDES)
R = 0.115
TYP
0.75 ± 0.05
4.00 ± 0.10
(4 SIDES)
23 24
0.70 ±0.05
PIN 1
TOP MARK
(NOTE 5)
0.38 ± 0.10
1
2
4.50 ± 0.05 2.45 ± 0.05
2.45 ± 0.10
(4-SIDES)
(4 SIDES)
3.10 ± 0.05
PACKAGE
OUTLINE
(UF24) QFN 0603
0.25 ± 0.05
0.50 BSC
0.200 REF
0.25 ±0.05
0.50 BSC
0.00 – 0.05
NOTE:
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.033
(0.838)
REF
24 23 22 21 20 19 18 17 16 15 14 13
.045 ±.005
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.254 MIN
.150 – .165
1
2
3
4
5
6
7
8
9 10 11 12
.0165 ±.0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
(0.38 ± 0.10)
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
× 45°
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN24 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3736f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC3736
U
TYPICAL APPLICATIO
2-Phase, Single Output Synchronous DC/DC Converter (3.3VIN to 1.8VOUT at 8A)
R
R
FB1B
118k
FB1A
59k
L1
1.5µH
C
ITH1A
V
1.8V
8A
MP1
OUT
22
23
24
1
2
3
100pF
21
20
19
18
17
16
15
+
SW1
IPRG1
SENSE1
PGND
BG1
SYNC/FCB
TG1
MN1
Si7540DP
V
FB1
+
C
OUT1
I
TH1
150µF
R
ITH1
IPRG2
PLLLPF
SGND
C
ITH1
15k
PGND
TG2
220pF
4
V
IN
3.3V
R
10Ω
LTC3736EUF
IN
VIN
5
14
C
IN
V
RUN/SS
10µF
×2
1M
13
12
11
MN2
C
BG2
OUT2
9
7
8
6
Si7540DP
+
150µF
PGND
PGOOD
C
VIN
+
V
FB2
SENSE2
1µF
3736 TA02
MP2
I
L2
1.5µH
TH2
10
TRACK
PGND
25
SW2
C
C
SS
ITH2B
22pF
4.7nF
C
, C
: SANYO 4TPB150MC
L1, L2: VISHAY IHLP-2525CZ-01
OUT1 OUT2
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COMMENTS
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2.5V ≤ V ≤ 9.8V, I
Up to 4A, SOT-23 Package, 550kHz
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2.65V ≤ V ≤ 8.5V, I
Up to 4A, 10-Lead MSOP
IN
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TM Synchronous Step-Down Controller
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SENSE
IN
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2.5V ≤ V ≤ 9.8V, SOT-23 Package, 550kHz
IN
Controls Up to Three Supplies, 10-Lead MSOP
1.25A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.8V, I = 60µA,
Q
OUT
IN
OUT
I
= <1µA, MS Package
LTC3412
2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.8V, I = 60µA,
Q
OUT
IN
OUT
I
= <1µA, TSSOP-16E Package
LTC3700
LTC3701
LTC3708
Constant Frequency Step-Down Controller with LDO Regulator
2-Phase, Low Input Voltage Dual Step-Down DC/DC Controller
2.65≤ V ≤ 9.8V, 550kHz, 10-Lead SSOP
IN
2.5V ≤ V ≤ 9.8V, 550kHz, PGOOD, PLL, 16-Lead SSOP
IN
Fast 2-Phase, No R
Output Tracking
Buck Controller with
Constant On-Time Dual Controller, V Up to 36V, Very Low
SENSE
IN
Duty Cycle Operation, 5mm × 5mm QFN Package
LTC3728/LTC3728L Dual, 550kHz, 2-Phase Synchronous Step-Down
Switching Regulator
Constant Frequency, V to 36V, 5V and 3.3V LDOs,
IN
5mm × 5mm QFN or 28-Lead SSOP
No R
is a trademark of Linear Technology Corporation.
SENSE
3736f
LT/TP 0304 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2004
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