LTC3772BEDDB#TRM_技术文档

LTC3772

Micropower No R_SENSE

Constant Frequency Step-Down

DC/DC Controller

U

FEATURES

DESCRIPTIO

The LTC^®3772 is a constant frequency current mode

step-downDC/DCcontrollerinalowprofile8-leadSOT-23

■

No Current Sense Resistor Required

■

40µA No-Load Quiescent Current

(ThinSOT^TM

) and a 3mm × 2mm DFN package. The No

■

High Output Currents Easily Achieved

R_SENSE^TMarchitecture eliminates the need for a current

sense resistor, improving efficiency and saving board

space.

■

Internal Soft-Start Ramps V_OUT

■

Wide V_INRange: 2.75V to 9.8V

■

Low Dropout: 100% Duty Cycle

■

Constant Frequency 550kHz Operation

The LTC3772 automatically switches into Burst Mode

operation at light loads to increase efficiency at low output

current. It consumes only 40µA of quiescent current

under a no-load condition.

Low Ripple Burst Mode^®Operation at Light Load

■

Output Voltage as Low as 0.8V

±1.5% Voltage Reference Accuracy

■

Current Mode Operation for Excellent Line and Load

The LTC3772 incorporates an undervoltage lockout fea-

ture that shuts down the device when the input voltage

falls below 2V. To maximize the runtime from a battery

source, the external P-channel MOSFET is turned on

continuously in dropout (100% duty cycle). High switch-

ing frequency of 550kHz allows the use of a small inductor

and capacitors. An internal soft-start smoothly ramps the

output voltage from zero to its regulation point.

Transient Response

■

Only 8µA Supply Current in Shutdown

Low Profile 8-Lead SOT-23 (1mm) and

^{(3mm × 2mm) D}U^{FN (0.75mm) Packages}

APPLICATIO S

■

1- or 2-Cell Li-Ion Battery-Powered Applications

■

Wireless Devices

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

Portable Computers

Distributed Power Systems

Burst Mode is a registered trademark of Linear Technology Corporation.

ThinSOT and No R

are trademarks of Linear Technology Corporation.

SENSE

■

All other trademarks are the property of their respective owners.

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TYPICAL APPLICATIO

Efficiency and Power Loss vs Load Current

550kHz Micropower Step-Down DC/DC Converter

100

10

680pF

20k

V

= 3.3V

IN

V

IN

I

/RUN

V

IN

90

80

TH

2.75V TO 9.8V

V

= 5V

1

LTC3772

IN

10µF

GND

PGATE

3.3µH

82.5k

V

2.5V

2A

OUT

0.1

0.01

0.001

70

60

V

SW

FB

V

= 5V

IN

V

= 3.3V

IN

47µF

22pF 174k

3772 TA01

50

40

FIGURE 5 CIRCUIT

1000

LOAD CURRENT (mA)

1

10

100

10000

3772 TA01b

3772f

1

LTC3772

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ABSOLUTE MAXIMUM RATINGS

(Note 1)

Input Supply Voltage (V_IN)........................ –0.3V to 10V

IPRG, PGATE Voltages ................ –0.3V to (V_IN+ 0.3V)

V_FB, I_TH/RUN Voltages ............................. –0.3V to 2.4V

SW Voltage ........... –2V to (V_IN+ 1V) or 10V Maximum

PGATE Peak Output Current (<10µs) ........................ 1A

Operating Temperature Range (Note 2) .. – 40°C to 85°C

Junction Temperature (Note 3)............................ 125°C

Storage Temperature Range ................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec)

TSOT-23 ........................................................... 300°C

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PACKAGE/ORDER INFORMATION

ORDER PART

NUMBER

ORDER PART

NUMBER

TOP VIEW

GND

1

2

3

4

8

7

6

5

PGATE

TOP VIEW

LTC3772EDDB

LTC3772ETS8

V

FB

V

IN

I

1

8 NC

7 SW

6 V

IN

5 PGATE

PRG

9

I

/RUN 2

I

TH

/RUN

SW

NC

TH

V

FB

3

I

PRG

GND 4

DDB8 PART MARKING

LBNR

TS8 PART MARKING

LTBNQ

TS8 PACKAGE

DDB PACKAGE

8-LEAD PLASTIC TSOT-23

8-LEAD (3mm × 2mm) PLASTIC DFN

T_JMAX= 125°C, θ_JA= 230°C/W

T_JMAX= 125°C, θ_JA= 76°C/W

EXPOSED PAD (PIN 9) IS GND

MUST BE SOLDERED TO PCB

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● indicates specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 4.2V unless otherwise noted. (Note 2)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input Voltage Range

●

2.75

9.8

V

Input DC Supply Current

Normal Operation

SLEEP Mode

Shutdown

(Note 4)

V

/RUN = 1.3V

ITH

250

40

8

375

60

20

5

µA

V

/RUN = 0V

< UVLO Threshold – 100mV

ITH

UVLO

1

IN

Undervoltage Lockout (UVLO) Threshold

V

Rising

Falling

●

2.0

1.85

2.75

2.60

V

IN

Start-Up Current Source

V

/RUN = 0V

0.7

0.3

1.2

0.6

1.7

µA

ITH

Shutdown Threshold (at I /RUN)

/RUN Rising

●

0.95

V

TH

Regulated Feedback Voltage

0°C ≤ T ≤ 85°C (Note 5)

–40°C ≤ T ≤ 85°C (Note 5)

0.788

0.780

0.800

0.812

V

A

Feedback Voltage Line Regulation

Feedback Voltage Load Regulation

2.75V ≤ V ≤ 9.8V (Note 5)

0.08

0.2

mV/V

IN

I

/RUN = 1.6V (Note 5)

TH

/RUN = 1V (Note 5)

TH

0.2

–0.2

%

3772f

2

LTC3772

ELECTRICAL CHARACTERISTICS

The ● indicates specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 4.2V unless otherwise noted. (Note 2)

PARAMETER

Input Current

CONDITIONS

(Note 5)

MIN

–10

TYP

2

MAX

10

UNITS

nA

V

FB

Overvoltage Protect Threshold

Overvoltage Protect Hysteresis

Measured at V

0.850

0.880

40

0.910

V

FB

mV

Oscillator Frequency

Normal Operation

Output Short Circuit

V

= 0.8V

= 0V

500

550

200

650

kHz

FB

Gate Drive Rise Time

Gate Drive Fall Time

C

= 3000pF

40

ns

LOAD

Peak Current Sense Voltage

I

= GND (Note 6)

= Floating

●

90

160

228

105

175

245

120

190

262

mV

PRG

= V

IN

Default Soft-Start Time

0.6

ms

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency.

Note 5: The LTC3772 are tested in a feedback loop that servos V to the

Note 2: The LTC3772ETS8/LTC3772EDDB are guaranteed to meet

specifications from 0°C to 70°C. Specifications over the –40°C to 85°C

operating temperature range are assured by design, characterization and

correlation with statistical process controls.

FB

output of the error amplifier while maintaining I /RUN at the midpoint of

TH

the current limit range.

Note 6: Peak current sense voltage is reduced dependent on duty cycle as

given in Figure 1.

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formula:

D

T = T + (P • θ °C/W)

J

A

D

JA

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TYPICAL PERFOR A CE CHARACTERISTICS

Quiescent Current (No Load)

vs Input Voltage

Quiescent Current (No Load)

vs Temperature

Quiescent Current (Shutdown)

vs Input Voltage

55

50

25

60

55

50

45

40

35

30

25

20

15

45

40

35

30

25

10

5

20

0

–20

0

20 40

100

–60 –40

60 80

6

7

6

2

3

4

5

8

9

10

2

3

4

5

7

8

9

10

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3772 G02

3772 G01

3772 G03

3772f

3

LTC3772

TYPICAL PERFOR A CE CHARACTERISTICS

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Quiescent Current (Shutdown)

vs Temperature

Shutdown Threshold

vs Temperature

Regulated Feedback Voltage

vs Temperature

14

12

800

700

600

500

812

808

804

800

V

IN

= 4.2V

V

= 4.2V

IN

10

8

6

4

2

796

792

788

0

400

–20

0

20 40

100

–60 –40

60 80

–50 –30 –10 10

30

50

70

90

30

TEMPERATURE (°C)

80

90

–50 –30 –10 10

50

TEMPERATURE (°C)

3772 G04

3772 G05

3772 G06

Regulated Feedback Voltage

vs Input Voltage

Oscillator Frequency

vs Temperature

Oscillator Frequency

vs Input Voltage

600

590

580

570

560

550

540

530

520

510

500

560

555

550

545

0.812

0.808

0.804

0.800

0.796

0.792

0.788

T

A

= 25°C

V

= 4.2V

IN

540

7

8

2

3

4

5

6

9

10

2

3

4

5

6

7

8

9

10

–50

–10 10

30

50

70

90

–30

INPUT VOLTAGE (V)

V

IN

(V)

TEMPERATURE (°C)

3772 G07

3772 G09

3772 G08

I_TH/RUN Start-Up Current

vs Temperature

I_TH/RUN Start-Up Current

vs Input Voltage

Undervoltage Lockout Thresholds

vs Temperature

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

2.5

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

2.1

1.9

1.7

1.5

I

/RUN = 0V

I /RUN = 0V

TH

RISING

1.3

1.1

FALLING

0.9

0.7

0.5

–60

20

TEMPERATURE (°C)

60 80

2

4

8

80

–40 –20

0

40

100

0

10

–60

20

TEMPERATURE (°C)

60

6

–40 –20

0

40

100

INPUT VOLTAGE (V)

3772 FG10

3772 G11

3772 G12

3772f

4

LTC3772

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TYPICAL PERFOR A CE CHARACTERISTICS

Maximum Current Sense

Threshold vs Temperature

Foldback Frequency

vs Temperature

Soft-Start Time vs Temperature

1000

900

800

700

600

500

400

230

220

210

200

190

180

170

160

150

300

250

200

150

100

50

V

= 0V

FB

I

= V

IN

PRG

I

= FLOAT

PRG

I

= GND

PRG

0

40 60

TEMPERATURE (°C)

–60 –40 –20

0

20

80 100

20 40

0

TEMPERATURE (°C)

40 60

TEMPERATURE (°C)

–60 –40 –20

60 80 100

–60 –40 –20

0

20

80 100

3772 G14

3772 G15

3772 G13

Efficiency vs Load Current

95

90

85

80

75

70

65

60

100

FIGURE 5 CIRCUIT

V

IN

= 3.3V

V

= 3.3V

OUT

V

= 4.2V

90

80

70

60

50

IN

V

= 5V

V

= 2.5V

IN

OUT

V

IN

= 7V

V

= 1.8V

OUT

V

= 2.5V

OUT

FIGURE 5 CIRCUIT

1

10

100

1000 10000

1

10

100

1000

10000

LOAD CURRENT (mA)

3772 G16

3772 G17

Start-Up

Load Step

V

OUT

V

OUT

100mV/DIV

1V/DIV

AC COUPLED

I

/RUN

TH

I

L

1V/DIV

2A/DIV

I

L

LOAD

2A/DIV

3772 G18

3772 G19

V

= 5V

500µs/DIV

V

= 5V

20µs/DIV

IN

V

= 2.5V

V

= 2.5V

OUT

FIGURE 5 CIRCUIT

OUT

LOAD

I

= 100mA TO 1.5A

FIGURE 5 CIRCUIT

3772f

5

LTC3772

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PI FU CTIO S

(DDB/TS8)

NC (Pin 5/Pin 8): No Connection Required.

GND (Pin 1/Pin 4): Ground Pin.

SW (Pin 6/Pin 7): Switch Node Connection to Inductor

and Current Sense Input Pin. Normally, the external

P-channel MOSFET’s drain is connected to this pin.

V_FB(Pin 2/Pin 3): Receives the feedback voltage from an

external resistor divider across the output.

I_TH/RUN (Pin 3/Pin 2): This pin performs two functions. It

servesastheerroramplifiercompensationpointaswellas

the run control input. Nominal voltage range for this pin is

0.7V to 1.9V. Forcing this pin below 0.6V causes the

device to be shut down. In shutdown, all functions are

disabled and the PGATE pin is held high.

V_IN(Pin 7/Pin 6): Supply and Current Sense Input Pin.

This pin must be closely decoupled to GND (Pin 4).

Normally the external P-channel MOSFET’s source is

connected to this pin.

PGATE(Pin8/Pin5):GateDrivefortheExternalP-Channel

MOSFET. This pin swings from 0V to V_IN.

I_PRG(Pin 4/Pin 1): Current Sense Limit Pin. Three-state

pin selects maximum peak sense voltage threshold. The

pin selects the maximum voltage drop across the external

P-channel MOSFET. Tie to V_IN, GND or float to select

245mV, 105mV or 175mV respectively.

Exposed Pad (Pin 9, DDB Only): The Exposed Pad is

ground and must be soldered to the PCB for electrical

connection and optimum thermal performance.

3772f

6

LTC3772

U

W

FU CTIO AL DIAGRA

SW

V

IN

SLOPE

COMPENSATION

UV

UNDERVOLTAGE

LOCKOUT

VOLTAGE

REFERENCE

BURST

CLAMP

0.8V

–

+

I

PRG

1µA

SHUTDOWN

CURRENT

COMPARATOR

I

/RUN

–

+

75mV

TH

I

+

LIM

S

I

TH

BUFFER

SHDN

–

550kHz

OSCILLATOR

R

RS

LATCH

Q

V

IN

FREQUENCY

FOLDBACK

SLEEP

SWITCHING

LOGIC AND

BLANKING

CIRCUIT

COMPARATOR

PGATE

–

+

SLEEP

0V

OVERVOLTAGE

COMPARATOR

SHORT-CIRCUIT

DETECT

0.15V

+

–

ERROR

AMPLIFIER

V

FB

0.225V

0.88V

0.3V

–

+

0.8V

SOFT-START

RAMP

1.2V

GND

3772 FD

3772f

7

LTC3772

U

(Refer to the Functional Diagram)

OPERATIO

operation. With the switch held off, average inductor cur-

rentwilldecaytozeroandtheloadwilleventuallycausethe

erroramplifieroutputtostartdriftinghigher.Whentheerror

amplifier output rises to 0.87V, the sleep comparator will

untrip and normal operation will resume. The next oscilla-

tor cycle will turn the external MOSFET on and the switch-

ing cycle will repeat.

Main Control Loop (Normal Operation)

The LTC3772 is a constant frequency current mode step-

down switching regulator controller. During normal op-

eration, the external P-channel MOSFET is turned on each

cycle when the oscillator sets the RS latch and turned off

when the current comparator resets the latch. The peak

inductor current at which the current comparator trips is

controlled by the voltage on the I_TH/RUN pin, which is the

outputoftheerroramplifier.Thenegativeinputtotheerror

amplifier is the output feedback voltage V_FB, which is

generated by an external resistor divider connected be-

tween V_OUTand ground. When the load current increases,

it causes a slight decrease in V_FBrelative to the 0.8V

reference, which in turn causes the I_TH/RUN voltage to

increase until the average inductor current matches the

new load current.

Dropout Operation

When the input supply voltage decreases towards the

output voltage, the rate of change of inductor current

during the on cycle decreases. This reduction means that

at some input-output differential, the external P-channel

MOSFET will remain on for more than one oscillator cycle

(start dropping off-cycles) since the inductor current has

not ramped up to the threshold set by the error amplifier.

Further reduction in input supply voltage will eventually

cause the external P-channel MOSFET to be turned on

100%; i.e., DC. The output voltage will then be determined

by the input voltage minus the voltage drop across the

sense resistor, the MOSFET and the inductor.

ThemaincontrolloopisshutdownbypullingtheI_TH/RUN

pin to ground. Releasing the I_TH/RUN pin allows an

internal 1µA current source to charge up the external

compensation network. When the I_TH/RUN pin voltage

reaches approximately 0.6V, the main control loop is

enabled and the I_TH/RUN voltage is pulled up by a clamp

to its zero current level of approximately one diode

voltage drop (0.7V). As the external compensation net-

work continues to charge up, the corresponding peak

inductorcurrentlevelfollows, allowingnormaloperation.

The maximum peak inductor current attainable is set by a

clamp on the I_TH/RUN pin at 1.2V above the zero current

level (approximately 1.9V).

Undervoltage Lockout Protection

To prevent operation of the external P-channel MOSFET

with insufficient gate drive, an undervoltage lockout cir-

cuit is incorporated into the LTC3772. When the input

supply voltage drops below approximately 2V, the

P-channel MOSFET and all internal circuitry other than the

undervoltage block itself are turned off. Input supply

current in undervoltage is approximately 1µA.

Burst Mode Operation

Short-Circuit Protection

The LTC3772 incorporates Burst Mode operation at low

load currents (<10% of I_MAX). In this mode, an internal

clamp sets the peak current of the inductor at a level cor-

respondingtoanI_TH/RUNvoltage0.925V,eventhoughthe

actual I_TH/RUN voltage is lower. When the inductor’s av-

erage current is greater than the load requirement, the

voltage at the I_TH/RUN pin will drop. When the I_TH/RUN

voltage falls to 0.85V, the sleep comparator will trip, turn-

ing off the external MOSFET. In sleep, the input DC supply

current to the IC is reduced to 40µA from 250µA in normal

If the output is shorted to ground, the frequency of the

oscillator is folded back from 550kHz to approximately

200kHz while maintaining the same minimum on time.

This lower frequency allows the inductor current to safely

discharge, thereby preventing current runaway. After the

short is removed, the oscillator frequency will gradually

increase back to 550kHz as V_FBrises through 0.3V on its

way back to 0.8V.

3772f

8

LTC3772

U

(Refer to the Functional Diagram)

OPERATIO

Overvoltage Protection

However, once the controller’s duty cycle exceeds 20%,

slope compensation begins and effectively reduces the

peak sense voltage by a scale factor given by the curve in

Figure 1.

If V_FBexceeds its regulation point of 0.8V by more than

10% for any reason, such as an output short-circuit to a

higher voltage, the overvoltage comparator will hold the

external P-channel MOSFET off. This comparator has a Thepeakinductorcurrentisdeterminedbythepeaksense

typical hysteresis of 40mV.

voltage and the on-resistance of the external P-channel

MOSFET:

Peak Current Sense Voltage Selection and Slope

Compensation (I_PRGPins)

∆V_SENSE(MAX)

I_PEAK

=

R_DS(ON)

When a controller is operating below 20% duty cycle, the

peak current sense voltage (between the SENSE⁺and SW

pins) allowed across the external P-channel MOSFET is

determined by:

Soft-Start

The start-up of V_OUTis controlled by the LTC3772 internal

soft-start. During soft-start, the error amplifier EAMP

compares the feedback signal V_FBto the internal soft-start

ramp (instead of the 0.8V reference), which rises linearly

from 0V to 0.8V in about 0.6ms. This allows the output

voltage to rise smoothly from 0V to its final value, while

maintaining control of the inductor current. After the

soft-start is timed out, it is disabled until the part is put in

shutdown again or the input supply is cycled.

A(V_ITH– 0.7V)

∆V_SENSE(MAX)

=

– 0.015

10

where A is a constant determined by the state of the I_PRG

pins. Floating the I_PRGpin selects A = 1.58; tying I_PRGto

V_INselects A = 2.2; tying I_PRGto SGND selects A = 0.97.

ThemaximumvalueofV_ITHistypicallyabout1.98V, sothe

maximum sense voltage allowed across the external

P-channel MOSFET is 175mV, 100mV or 250mV for the

three respective states of the I_PRGpin.

100

90

80

70

60

50

40

30

20

10

0

10 20 30 40 50 60 70 80 90 100

DUTY CYCLE (%)

3772 F01

Figure 1. Reduction in Sense Voltage Due to

Slope Compensation vs Duty Cycle

3772f

9

LTC3772

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APPLICATIO S I FOR ATIO

ThebasicLTC3772applicationcircuitisshownonthefront

page of this data sheet. External component selection is

driven by the load requirement and begins with the selec-

tion of the power MOSFET inductor and the output diode.

These are selected followed by the input bypass capacitor

However, for operation above 20% duty cycle, slope com-

pensation has to be taken into consideration to select the

appropriatevalueofR_DS(ON)toprovidetherequiredamount

of load current:

∆V_SENSE(MAX)– SF

C_INand output bypass capacitor C_OUT

.

5

6

R_DS(ON)(MAX)

=

•

I_OUT(MAX)

Power MOSFET Selection

whereSFisafactorwhosevalueisobtainedfromthecurve

in Figure 1.

AnexternalP-channelpowerMOSFETmustbeselectedfor

use with the LTC3772. The main selection criteria for the

power MOSFET are the threshold voltage V_GS(TH)and the

“on”resistanceR_DS(ON),reversetransfercapacitanceC_RSS

and total gate charge.

These must be further derated to take into account the

significantvariationinon-resistancewithtemperature.The

following equation is a good guide for determining the

required R_DS(ON)MAXat 25°C (manufacturer’s specifica-

tion), allowing some margin for variations in the LTC3772

and external component values:

Since the LTC3772 is designed for operation down to low

inputvoltages,asublogiclevelthresholdMOSFET(R_DS(ON)

guaranteed at V_GS= 2.5V) is required for applications that

workclosetothisvoltage.WhentheseMOSFETsareused,

makesurethattheinputsupplytotheLTC3772islessthan

the absolute maximum V_GSrating.

∆V_SENSE(MAX)– SF

I_OUT(MAX)• ρ_T

5

6

R_DS(ON)(MAX)

=

• 0.9 •

TheP-channelMOSFET’son-resistanceischosenbasedon

the required load current. The maximum average output

loadcurrentI_OUT(MAX)isequaltothepeakinductorcurrent

minus half the peak-to-peak ripple current I_RIPPLE. The

LTC3772’s current comparator monitors the drain-to-

source voltage V_DSof the P-channel MOSFET, which is

sensed between the V_INand SW pins. The peak inductor

current is limited by the current threshold, set by the volt-

age on the I_THpin of the current comparator. The voltage

on the I_THpin is internally clamped, which limits the maxi-

mum current sense threshold ∆V_SENSE(MAX)to approxi-

mately 175mV when I_PRGis floating (100mV when I_PRGis

tied low; 250mV when I_PRGis tied high).

The ρ_Tis a normalizing term accounting for the tempera-

ture variation in on-resistance, which is typically about

0.4%/°C, as shown in Figure 2. Junction to case tempera-

tureT_JCisabout10°Cinmostapplications.Foramaximum

ambienttemperatureof70°C,usingρ_80°C~1.3intheabove

equation is a reasonable choice.

The required minimum R_DS(ON)of the MOSFET is also

governed by its allowable power dissipation. For applica-

tionsthatmayoperatetheLTC3772indropout–i.e., 100%

2.0

1.5

1.0

0.5

0

The output current that the LTC3772 can provide is given by:

∆V_SENSE(MAX)

I_RIPPLE

I_OUT(MAX)

=

–

R_DS(ON)

2

A reasonable starting point is setting ripple current I_RIPPLE

to be 40% of I_OUT(MAX). Rearranging the above equation

yields:

50

100

–50

150

0

∆V_SENSE(MAX)

I_OUT(MAX)

5

R_DS(ON)(MAX)= •

6

JUNCTION TEMPERATURE (ϒC)

3772 F02

Figure 2. R_DS(ON)vs Temperature

for Duty Cycle < 20%.

3772f

10

LTC3772

W U U

APPLICATIO S I FOR ATIO

U

duty cycle–at its worst case the required R_DS(ON)is given

by:

Inductor Core Selection

Oncetheinductancevalueisdetermined,thetypeofinduc-

tormustbeselected. Actualcorelossisindependentofcore

size for a fixed inductor value, but it is very dependent on

inductance selected. As inductance increases, core losses

go down. Unfortunately, increased inductance requires

moreturnsofwireandthereforecopperlosseswillincrease.

P

R_{DS(ON)(DC=100%)}

=

(I_OUT(MAX))²(1+ δ_P)

where P_Pis the allowable power dissipation and δ_Pis the

temperature dependency of R_DS(ON). (1 + δ_P) is generally

given for a MOSFET in the form of a normalized R_DS(ON)vs

temperature curve, but δ_P= 0.005/°C can be used as an

approximation for low voltage MOSFETs.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can

concentrate on copper loss and preventing saturation.

Ferrite core material saturates “hard,” which means that

inductance collapses abruptly when the peak design cur-

rent is exceeded. This results in an abrupt increase in in-

ductorripplecurrentandconsequentoutputvoltageripple.

Do not allow the core to saturate!

In applications where the maximum duty cycle is less than

100%andtheLTC3772isincontinuousmode,theR_DS(ON)

is governed by:

P

R_DS(ON)

≅

(DC)I_OUT²(1+ δ_P)

Different core materials and shapes will change the size/

currentandprice/currentrelationshipofaninductor.Toroid

or shielded pot cores in ferrite or permalloy materials are

small and don’t radiate much energy, but generally cost

more than powdered iron core inductors with similar

characteristics. The choice of which style inductor to use

mainlydependsonthepricevssizerequirementsandany

radiated field/EMI requirements. New designs for surface

mount inductors are available from Coiltronics, Coilcraft,

Toko and Sumida.

where DC is the maximum operating duty cycle of the

LTC3772.

Inductor Value Calculation

The operating frequency and inductor selection are inter-

related in that higher operating frequencies permit the use

ofasmallerinductorforthesameamountofinductorripple

current. However, this is at the expense of efficiency due

to an increase in MOSFET gate charge losses.

Output Diode Selection

The inductance value also has a direct effect on ripple

current. The ripple current, I_RIPPLE, decreases with higher

inductance or frequency and increases with higher V_INor

Thecatchdiodecarriesloadcurrentduringtheoff-time.The

average diode current is therefore dependent on the

P-channelswitchdutycycle.Athighinputvoltagesthediode

conducts most of the time. As V_INapproaches V_OUTthe

diode conducts only a small fraction of the time. The most

stressfulconditionforthediodeiswhentheoutputisshort-

circuited.Underthisconditionthediodemustsafelyhandle

I_PEAKat close to 100% duty cycle. Therefore, it is impor-

tant to adequately specify the diode peak current and av-

erage power dissipation so as not to exceed the diode

ratings.

V

_OUT.Theinductor’speak-to-peakripplecurrentisgivenby:

V − V_OUT⎛ V_OUT+ V_D⎞

IN

I_RIPPLE

=

⎜

⎟

f(L) ⎝ V + V_D⎠

IN

wherefistheoperatingfrequency.Acceptinglargervalues

of I_RIPPLEallows the use of low inductances, but results in

higher output voltage ripple and greater core losses. A

reasonablestartingpointforsettingripplecurrentisI_RIPPLE

=0.4(I_OUT(MAX)).Remember,themaximumI_RIPPLEoccurs

at the maximum input voltage.

3772f

11

LTC3772

W U U

U

APPLICATIO S I FOR ATIO

Under normal load conditions, the average current con-

ducted by the diode is:

The output filtering capacitor C smooths out current flow

from the inductor to the load, help maintain a steady out-

putvoltageduringtransientloadchangesandreduceoutput

voltage ripple. The capacitors must be selected with suf-

ficiently low ESR to minimize voltage ripple and load step

transients and sufficiently bulk capacitance to ensure the

control loop stability.

⎛ V − V_OUT

⎞

IN

I =

D

I

OUT

⎜

⎟

⎝ V + V_D⎠

IN

The allowable forward voltage drop in the diode is calcu-

lated from the maximum short-circuit current as:

The output ripple, ∆V_OUT, is determined by:

P_D

V_F≈

⎛

1

⎞

I_SC(MAX)

∆V_OUT≤ ∆I ESR+

⎜

⎟

L

⎝

8fC_OUT

⎠

where P_Dis the allowable power dissipation and will be

determined by efficiency and/or thermal requirements.

Theoutputrippleishighestatmaximuminputvoltagesince

DILincreaseswithinputvoltage.Multiplecapacitorsplaced

in parallel may be needed to meet the ESR and RMS cur-

renthandlingrequirements.Drytantalum,specialpolymer,

aluminumelectrolyticandceramiccapacitorsareallavail-

able in surface mount packages. Special polymer capaci-

torsofferverylowESRbuthavelowercapacitancedensity

than other types. Tantalum capacitors have the highest

capacitance density but it is important to only use types

thathavebeensurgetestedforuseinswitchingpowersup-

plies. Aluminum electrolytic capacitors have significantly

higher ESR but can be used in cost-sensitive applications

provided that consideration is given to ripple current rat-

ings and long term reliability. Ceramic capacitors have

excellent low ESR characteristics but can have a high

voltage coefficient and audible piezoelectric effects. The

highQofceramiccapacitorswithtraceinductancecanalso

lead to significant ringing.

A fast switching diode must also be used to optimize effi-

ciency. Schottky diodes are a good choice for low forward

drop and fast switching times. Remember to keep lead

length short and observe proper grounding to avoid ring-

ing and increased dissipation.

An additional consideration in applications where low no-

load quiescent current is critical is the reverse leakage

currentofthediodeattheregulatedoutputvoltage. Aleak-

age greater than several microamperes can represent a

significant percentage of the total input current.

C_INand C_OUTSelection

The input capacitance, C_IN, is needed to filter the trapezoi-

dalcurrentatthesourceofthetopMOSFET.Topreventlarge

ripple voltage, a low ESR input capacitor sized for the

maximum RMS current should be used. RMS current is

given by:

Using Ceramic Input and Output Capacitors

Higher values, lower cost ceramic capacitors are now

becoming available in smaller case sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. However, care must

be taken when these capacitors are used at the input and

output. When a ceramic capacitor is used at the input and

thepowerissuppliedbyawalladapterthroughlongwires,

aloadstepattheoutputcaninduceringingattheinput,V_IN.

At best, this ringing can couple to the output and be mis-

taken as loop instability. At worst, a sudden inrush of cur-

rent through the long wires can potentially cause a voltage

spike at V_INlarge enough to damage the part.

V_OUT

V

IN

V

IN

V_OUT

I_RMS= I_OUT(MAX)

–1

This formula has a maximum at V_IN= 2V_OUT, where I_RMS

= I_OUT/2. This simple worst-case condition is commonly

usedfordesignbecauseevensignificantdeviationsdonot

offer much relief. Note that ripple current ratings from

capacitormanufacturersareoftenbasedononly2000hours

oflifewhichmakesitadvisabletofurtherderatethecapaci-

tor,orchooseacapacitorratedatahighertemperaturethan

required.Severalcapacitorsmayalsobeparalleledtomeet

size or height requirements in the design.

3772f

12

LTC3772

W U U

APPLICATIO S I FOR ATIO

U

1. The V_INcurrent is the DC supply current, given in the

electrical characteristics, that excludes MOSFET driver

and control currents. V_INcurrent results in a small loss

which increases with V_IN.

For ceramic capacitor, use X7R or X5R types, do not use

Y5V. The choices include Murata GRM series, TDK C2012

and Taiyo-Yuden JMK series.

Setting Output Voltage

2. MOSFETgatechargecurrentresultsfromswitchingthe

gate capacitance of the power MOSFET. Each time a

MOSFET gate is switched from low to high to low again,

a packet of charge dQ moves from V_INto ground. The

resulting dQ/dt is a current out of V_INthat is typically

much larger than the DC supply current. In continuous

mode, I_GATECHG= (f)(dQ).

3. I²R losses are predicted from the DC resistances of the

MOSFET, inductor and current shunt. In continuous

mode the average output current flows through L but is

“chopped” between the P-channel MOSFET (in series

withR_SENSE)andtheoutputdiode.TheMOSFETR_DS(ON)

plusR_SENSEmultipliedbydutycyclecanbesummedwith

the resistances of L and R_SENSEto obtain I²R losses.

The LTC3772 output voltages are each set by an external

feedback resistor divider carefully placed across the out-

put as shown in Figure 3. The regulated output voltage is

determined by:

⎛

R_B⎞

R_A⎠

V_OUT= 0.8V • 1+

⎜

⎟

⎝

Toimprovethefrequencyresponse,afeed-forwardcapaci-

tor, C_FF, may be used. Great care should be taken to route

the V_FBline away from noise sources, such as the inductor

or the SW line.

V

OUT

LTC3772

R

C

FF

B

A

4. Theoutputdiodeisamajorsourceofpowerlossathigh

currentsandgetsworseathighinputvoltages.Thediode

loss is calculated by multiplying the forward voltage

timesthediodedutycyclemultipliedbytheloadcurrent.

Forexample,assumingadutycycleof50%withaSchot-

tkydiodeforwardvoltagedropof0.4V,thelossincreases

from0.5%to8%astheloadcurrentincreasesfrom0.5A

to 2A.

3

V

FB

R

3772 F03

Figure 3. Setting Output Voltage

Efficiency Considerations

The efficiency of a switching regulator is equal to the out-

putpowerdividedbytheinputpowertimes100%.Itisoften

useful to analyze individual losses to determine what is

limitingtheefficiencyandwhichchangewouldproducethe

most improvement. Efficiency can be expressed as:

5. Transition losses apply to the external MOSFET and

increase at higher operating frequencies and input volt-

ages. Transition losses can be estimated from:

Transition Loss = 2(V_IN)²I_{O(MAX) RSS}

(f)

C

OtherlossesincludingC_INandC_OUTESRdissipativelosses,

and inductor core losses, generally account for less than

2% total additional loss.

Efficiency = 100% – (η1 + η2 + η3 + ...)

where η1, η2, etc. are the individual losses as a percent-

age of input power.

Foldback Current Limiting

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3772 circuits: 1) LTC3772 DC bias current,

2) MOSFET gate charge current, 3) I²R losses and 4) volt-

age drop of the output diode.

AsdescribedintheOutputDiodeSelection,theworst-case

dissipation occurs with a short-circuited output when the

diodeconductsthecurrentlimitvaluealmostcontinuously.

3772f

13

LTC3772

W U U

U

APPLICATIO S I FOR ATIO

Topreventexcessiveheatinginthediode,foldbackcurrent

limiting can be added to reduce the current in proportion

to the severity of the fault.

and values determine the loop feedback factor gain and

phase. Anoutputcurrentpulseof20%to100%offullload

current having a rise time of 1µs to 10µs will produce

outputvoltageandI_THpinwaveformsthatwillgiveasense

of the overall loop stability. The gain of the loop will be

increased by increasing R_C, and the bandwidth of the loop

will be increased by decreasing C_C. The output voltage

settling behavior is related to the stability of the closed-

loopsystemandwilldemonstratetheactualoverallsupply

performance. For a detailed explanation of optimizing the

compensation components, including a review of control

loop theory, refer to Application Note 76.

Foldbackcurrentlimitingisimplementedbyaddingdiodes

D_FB1and D_FB2between the output and the I_TH/RUN pin as

shown in Figure 4. In a hard short (V_OUT= 0V), the current

will be reduced to approximately 50% of the maximum

output current.

V

LTC3772

OUT

R

B

A

I

/RUN V

FB

TH

D

FB1

FB2

A second, more severe transient is caused by switching in

loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C_OUT, causing a rapid drop in V_OUT. No regulator can

deliver enough current to prevent this problem if the load

switch resistance is low and it is driven quickly. The only

solution is to limit the rise time of the switch drive so that

the load rise time is limited to approximately (25)(C_LOAD).

Thus a 10µF capacitor would require a 250µs rise time,

limiting the charging current to about 200mA.

3772 F04

Figure 4. Foldback Current Limiting

Checking Transient Response

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, V_OUTimmediately shifts by an amount

equal to (∆I_LOAD)(ESR), where ESR is the effective series

resistance of _COUT. ∆I_LOADalso begins to charge or dis-

chargeC_OUT, whichgeneratesafeedbackerrorsignal. The

regulator loop then returns V_OUTto its steady-state value.

Duringthisrecoverytime,V_OUTcanbemonitoredforover-

shoot or ringing. OPTI-LOOP compensation allows the

transient response to be optimized over a wide range of

output capacitance and ESR values.

Minimum On-Time Considerations

Minimum on-time, t_ON(MIN), is the smallest amount of

time that the LTC3772 is capable of turning the top

MOSFET on and then off. It is determined by internal

timing delays and the gate charge required to turn on the

top MOSFET. The minimum on-time for the LTC3772 is

about 250ns. Low duty cycle and high frequency applica-

tions may approach this minimum on-time limit and care

should be taken to ensure that:

The I_THseries R_C-C_Cfilter (see Functional Diagram) sets

the dominant pole-zero loop compensation. The I_THexter-

nal components shown in the Figure 5 circuit will provide

an adequate starting point for most applications. The

values can be modified slightly (from 0.2 to 5 times their

suggestedvalues)tooptimizetransientresponseoncethe

final PC layout is done and the particular output capacitor

type and value have been determined. The output capaci-

tors need to be decided upon because the various types

V_OUT

t_ON(MIN)

<

f • V

IN

Ifthedutycyclefallsbelowwhatcanbeaccommodatedby

the minimum on-time, the LTC3772 will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple current and ripple voltage will increase.

3772f

14

LTC3772

U

TYPICAL APPLICATIO S

550kHz Micropower, 1A, 2-Cell Li-Ion to 3.3V_OUT

Step-Down DC/DC Converter

100pF

15k

V

IN

I

/RUN

V

IN

TH

5V TO 8.4V

LTC3772

22µF

47µF

GND

PGATE

Si2341DS

L1 4.7µH

I

PRG

56.2k

V

OUT

V

3.3V

1A

SW

FB

UPS120

22pF 174k

L1: SUMIDA CR43-4R7

3772 TA02a

Efficiency vs Load Current

100

V

OUT

= 3.3V

V

IN

= 5.5V

V

= 7.2V

90

80

IN

V

= 8.4V

IN

70

60

50

40

1

10

100

1000

10000

LOAD CURRENT (mA)

3772 TA02b

Start-Up

Load Step

V

OUT

100mV/DIV

AC COUPLED

V

OUT

2V/DIV

I

L

I

/RUN

TH

500mA/DIV

1V/DIV

I

LOAD

L

500mA/DIV

1A/DIV

3772 TA02d

3772 TA02c

V

I

= 5.5V

20µs/DIV

V

R

= 5.5V

500µs/DIV

IN

OUT

IN

OUT

= 3.3V

= 40mA TO 500mA

= 3.3V

= 3Ω

LOAD

3772f

15

LTC3772

U

TYPICAL APPLICATIO S

550kHz Micropower 4A Step-Down DC/DC Converter

470pF

24.9k

V

IN

2.75V TO 9.8V

I

/RUN

V

IN

TH

LTC3772

22µF

47µF

GND

PGATE

NTMS5PO2R2

I

PRG

L1 2.2µH

82.5k

V

OUT

V

2.5V

4A

SW

FB

B320A

22pF 174k

L1: VISHAY IHLP-2525CZ-01

3772 TA03a

Efficiency vs Load Current

100

95

90

85

80

75

70

65

60

V

= 3.3V

IN

V

= 5V

IN

100

10000

1000

LOAD CURRENT (mA)

3772 TA03b

Start-Up

Load Step

V

OUT

V

OUT

2V/DIV

200mV/DIV

AC COUPLED

I

L

I

/RUN

TH

2A/DIV

1V/DIV

I

LOAD

L

2A/DIV

1A/DIV

3772 TA03d

3772 TA03c

V

OUT

= 5V

20µs/DIV

V

R

= 5V

500µs/DIV

IN

OUT

V

= 2.5V

= 3Ω

LOAD

3772f

16

LTC3772

U

TYPICAL APPLICATIO S

550kHz Micropower 5V_INto 1.8V_OUTat 8A DC/DC Converter

470pF

15k

V

IN

5V

I

/RUN

V

IN

TH

LTC3772

22µF

Si9803

GND

PGATE

×2

V

I

PRG

IN

L1 1µH

140k

V

1.8V

8A

OUT

V

SW

FB

100µF

×2

22pF 174k

3772 TA04a

3772f

17

LTC3772

U

PACKAGE DESCRIPTIO

DDB Package

8-Lead Plastic DFN (3mm × 2mm)

(Reference LTC DWG # 05-08-1702)

0.61 ±0.05

(2 SIDES)

0.675 ±0.05

2.50 ±0.05

1.15 ±0.05

PACKAGE

OUTLINE

0.25 ± 0.05

0.50 BSC

2.20 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.115

0.38 ± 0.10

3.00 ±0.10

(2 SIDES)

TYP

5

8

0.56 ± 0.05

(2 SIDES)

2.00 ±0.10

PIN 1 BAR

(2 SIDES)

TOP MARK

PIN 1

(SEE NOTE 6)

CHAMFER OF

EXPOSED PAD

4

1

(DDB8) DFN 1103

0.25 ± 0.05

0.75 ±0.05

0.200 REF

0.50 BSC

2.15 ±0.05

(2 SIDES)

0 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

3772f

18

LTC3772

U

PACKAGE DESCRIPTIO

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637)

2.90 BSC

(NOTE 4)

0.52

MAX

0.65

REF

1.22 REF

1.50 – 1.75

(NOTE 4)

2.80 BSC

1.4 MIN

3.85 MAX 2.62 REF

PIN ONE ID

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.22 – 0.36

8 PLCS (NOTE 3)

0.65 BSC

0.80 – 0.90

0.20 BSC

DATUM ‘A’

0.01 – 0.10

1.00 MAX

0.30 – 0.50 REF

1.95 BSC

0.09 – 0.20

(NOTE 3)

TS8 TSOT-23 0802

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

3772f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

19

LTC3772

U

TYPICAL APPLICATIO

680pF

20k

V

IN

I

/RUN

V

IN

TH

3V TO 8V

LTC3772

10µF

GND

FDC638P

L1 3.3µH

PGATE

I

PRG

82.5k

V

2.5V

2A

OUT

V

SW

FB

B220A

47µF

22pF

174k

3772 F05

L1: TOKO D53LCA915AT-3R3M

Figure 5. 550kHz Micropower Step-Down DC/DC Converter

RELATED PARTS

PART NUMBER

DESCRIPTION

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COMMENTS

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≥ 0.8V, I

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LTC3736

600mA (I ), 2MHz Synchronous Buck-Boost DC/DC Converter

2.5V ≤ V ≤ 5.5V, Single Inductor

IN

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V : 2.75V to 9.8V, I

Up to 5A, 4mm × 4mm QFN

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LTC3776

Dual, 2-Phase, No R

with Spread Spectrum

Synchronous Controller

V : 2.75V to 9.8V, Spread Spectrum Operation, Output

Voltage Tracking, 4mm × 4mm QFN Package

SENSE

IN

Dual, 2-Phase, No R

Controller with Output Tracking

Synchronous Controller for

V : 2.75V to 9.8V, I

Up to 5A, 4mm × 4mm QFN

SENSE

IN

OUT

Package

Dual, 2-Phase, No R

DDR/QDR Memory Termination

Provides V

and V with one IC, 2.75V ≤ V ≤ 9.8V,

TT IN

SENSE

DDQ

Adjustable Constant Frequency with PLL Up to 850kHz,

Spread Spectrum Operation, 4mm × 4mm QFN and

16-Lead SSOP Packages

LTC3808

No R

Output Tracking

, Low EMI, Synchronous Step-Down Controller with

2.75V ≤ V ≤ 9.8V, Spread Spectrum Operation,

3mm × 4mm DFN and 16-Lead SSOP Packages

SENSE

IN

3772f

LT/TP 0305 500 • PRINTED IN THE USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3772BEDDB#TRM
厂家：	Linear
描述：	LTC3772B - Micropower No RSENSE Constant Frequency Step-Down DC/DC Controller; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C 控制器
文件：	总20页 (文件大小：248K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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