LTC3774IUHE#PBF [Linear]
LTC3774 - Dual, Multiphase Current Mode Synchronous Controller for Sub-Milliohm DCR Sensing; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C;
| 型号： | LTC3774IUHE#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3774 - Dual, Multiphase Current Mode Synchronous Controller for Sub-Milliohm DCR Sensing; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C 开关 输出元件 |
| 文件： | 总38页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3774
Dual, Multiphase Current
Mode Synchronous Controller
for Sub-Milliohm DCR Sensing
DESCRIPTION
FEATURES
The LTC®3774 is a dual PolyPhase® current mode syn-
chronous step-down switching regulator controller that
drives power blocks, DRMOS or external gate drivers and
power MOSFETs. It offers an LTC-proprietary technique
that enhances the signal-to-noise ratio of the current
sense signal, allowing the use of inductors with very low
DC winding resistances as the current sense element for
maximum efficiency and reduced jitter.
n
Sub-Milliohm DCR Current Sensing
n
Operates with Power Blocks, DRMOS or External
Gate Drivers and MOSFETs
n
Supports Phase Shedding and N+1 Phase
Redundancy
n
Programmable DCR Temperature Compensation
n
0.ꢀ5ꢁ Maximum Total DC Output Error Over
Temperature
n
Dual Differential Remote Output Voltage Sense
The maximum current sense voltage is programmable
from 10mV to 30mV. High speed, low offset remote sense
differentialamplifiersandaprecise0.6Vreferenceprovide
accurateoutputvoltagesbetween0.6Vand3.5Vfromawide
4.5V to 38V input supply range. Soft recovery from output
shorts or overcurrent minimizes output overshoot. Burst
Mode® operation, continuous and pulse-skipping modes
are supported. The constant operating frequency can be
synchronized to an external clock or linearly programmed
from200kHzto1.2MHz.UptosixLTC3774controllerscan
be paralleled for 1-, 2-, 3-, 4-, 6-, 8- or 12-phase operation.
Amplifiers
n
Phase-Lockable Fixed Frequency Range: 200kHz to
1.2MHz
n
V Range: 4.5V to 38V
IN
OUT
n
n
n
n
n
V
Range: 0.6V to 3.5V
Supports Smooth Start-Up into Pre-Biased Outputs
Programmable Soft-Start or V Tracking
Hiccup Mode/Soft Recovery from Output Overcurrent
OUT
36-Lead (5mm × 6mm) QFN Package
APPLICATIONS
The LTC3774 is available in a 36-lead (5mm × 6mm) QFN
package.
n
Computer Systems
n
Telecom and Datacom Systems
L, LT, LTC, LTM, Linear Technology, the Linear logo, PolyPhase and Burst Mode are registered
n
Industrial Equipment
DC Power Distribution Systems
trademarks and No R
and Hot Swap are trademarks of Analog Devices, Inc. All other
SENSE
trademarks are the property of their respective owners. Protected by U.S. Patents, including
5481178, 5705919, 5929620, 6177787, 6580258, 6498466, 6611131, patent pending.
n
TYPICAL APPLICATION
High Efficiency Dual Phase 1.5V/60A Step-Down Converter
V
IN
4.5V TO 20V
22µF
50V
V
IN
RUN1, 2
ILIM1, 2
HIZB1
PHSMD
CLKOUT
PGOOD1,2
MODE/PLLIN
1/4 INTV
CC
0.33µH
(0.32mΩ DCR)
0.33µH
(0.32mΩ DCR)
f
HIZB2
IN
500kHz
LTC3774
DRMOS
DRMOS
PWM1
PWM2
PWMEN1
PWMEN2
GND
–
–
V
V
OSNS2
OSNS1
+
+
+
–
+
SNSA1
SNS1
SNSD1
SNSA2
SNS2
SNSD2
–
15k
FREQ
V
1.5V
60A
OUT
+
+
V
V
OSNS1
OSNS2
I
I
TH1
TH2
TK/SS1
TK/SS2
INTV
2200pF
15k
CC
+
10k
+
300µF
4V
330µF
4V
37.5k
0.1µF
4.7µF
3774 TA01a
3774fc
1
For more information www.linear.com/LTC3774
LTC3774
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V Voltage................................................. –0.3V to 40V
IN
HIZB Voltage .............................................. –0.3V to 40V
RUN, PGOOD, INTV Voltage ..................... –0.3V to 6V
CC
+
+
+
+
SNSA1 , SNSA2 , SNSD1 ,
36 35 34 33 32 31 30 29
–
–
SNSD2 , SNS1 , SNS2 ........................–0.3V to INTV
CC
ITEMP2
1
2
3
4
5
6
7
8
9
28 ITEMP1
27 ITH1
INTV Peak Output Current..................................20mA
CC
ITH2
–
–
All Other Pin Voltages...........................–0.3V to INTV
V
V
V
26
25
CC
OSNS2
OSNS2
OSNS1
OSNS1
+
+
V
Operating Junction Temperature Range
TK/SS2
HIZB2
24 TK/SS1
HIZB1
(Note 2).................................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
37
GND
23
PWMEN2
PWM2
22 PWMEN1
21 PWM1
20 RUN1
19 GND
RUN2
GND 10
11 12 13 14 15 16 17 18
UHE PACKAGE
36-LEAD (5mm × 6mm) PLASTIC QFN
= 125°C, θ = 43°C/W
T
JMAX
JA
EXPOSED PAD (PIN 37) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
http://www.linear.com/product/LTC3ꢀꢀ4#orderinfo
LEAD FREE FINISH
LTC3774EUHE#PBF
LTC3774IUHE#PBF
TAPE AND REEL
PART MARKING*
3774
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
LTC3774EUHE#TRPBF
LTC3774IUHE#TRPBF
36-Lead (5mm × 6mm) Plastic QFN
36-Lead (5mm × 6mm) Plastic QFN
3774
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
3774fc
2
For more information www.linear.com/LTC3774
LTC3774
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop/Whole System
V
V
V
Input Voltage Range
4.5
0.6
38
3.5
V
V
IN
l
l
Output Voltage Range
OUT
OSNS
+
Regulated Feedback Voltage
Feedback Current
I
= 1.2V (Note 3)
= 4.5V to 38V
IN
595.5
600
–30
604.5
–100
0.01
mV
nA
TH
+
I
OSNS
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
0.002
%/V
REFLNREG
LOADREG
l
l
∆I = 1.2V to 0.7V
∆I = 1.2V to 1.6V
0.01
0.01
0.1
0.1
%
%
TH
TH
g
Transconductance Amplifier g
I = 1.2V, Sink/Source 5µA
TH
2
4
mmho
MHz
%
m
m
f
DA Unity-Gain Crossover Frequency
Feedback Overvoltage Lockout
(Note 5)
0dB
+
l
V
Measured at V
(Note 4)
5
7.5
10
OVL
OSNS
I
Q
Input DC Supply Current
Normal Mode
Shutdown
9
40
mA
µA
V
RUN
= 0V
60
4.0
2
DF
Maximum Duty Factor
Undervoltage Lockout
UVLO Hysteresis
In Dropout
96
98
3.75
500
0.5
30
%
V
MAX
UVLO
UVLO
V
Falling
3.5
INTVCC
mV
µA
nA
µA
V/V
HYS
+
+
I
I
I
Sense Pin Bias Currents
Sense Pin Bias Currents
Sense Pin Bias Currents
V
V
V
= 3.3V
= 3.3V
SNSA
SNSD
SNSA
+
+
SNSD
–
–
= 3.3V
10
SNS
SNS
A
Total Sense Signal Gain to Current
Comparator
5
VT_SNS
l
l
I
I
t
DCR Tempco Compensation Current
Soft-Start Charge Current
Internal Soft-Start Time
HIZB Pin On Threshold
V
V
V
V
= 0.5V
= 0V
27
1
30
1.25
600
2.2
33
µA
µA
µs
V
TEMP
ITEMP
TK/SS
TK/SS
1.5
TK/SS
= 5V
SS(INTERNAL)
V
V
V
V
Rising
HIZB
HIZB
HIZB Pin On Hysteresis
RUN Pin On Threshold
600
1.22
80
mV
V
HIZB_HYS
RUN
l
V
RUN
Rising
1.1
1.34
RUN Pin On Hysteresis
mV
RUN_HYS
RUN
I
RUN Pin Pull-Up Current
RUN < On Threshold
RUN > On Threshold
RUN < 1.1V
RUN > 1.34V
1
5
µA
µA
V
Maximum Current Sense Threshold
I
I
I
I
I
I
= 2V, V – = 3.3V
SNS
SENSE(MAX)
TH
l
l
l
l
l
= 0V
9.25
14
10.25
15
11.25
16
mV
mV
mV
mV
mV
LIM
LIM
LIM
LIM
LIM
= 1/4 INTV
= Float
CC
CC
19
20
21
= 3/4 INTV
24
28.25
25
29.75
26
31.25
= INTV
CC
Power Good
V
PGOOD Pull-Down Resistance
PGOOD Leakage Current
90
45
200
2
Ω
µA
µs
PGOOD(ON)
PGOOD(OFF)
PGOOD
I
t
V
= 5V
–2
PGOOD
V
High to Low Delay
PGOOD
V
PGOOD Trip Level
V
OSNS
V
OSNS
V
OSNS
+ with Respect to Set Output Voltage
+ Ramping Up
PGOOD
5
–5
7.5
–7.5
10
–10
%
%
+ Ramping Down
3774fc
3
For more information www.linear.com/LTC3774
LTC3774
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
PGOOD Trip Level Hysteresis
2
%
PG(HYST)
INTV Linear Regulator
CC
INTVCC
V
V
Linear Regulator Voltage
INTV Load Regulation
6V < V < 38V
5.3
5.5
0.5
5.7
2
V
IN
INT
I = 0mA to 20mA
CC
%
LDO
CC
Oscillator and Phase-Locked Loop
f
Oscillator Frequency
= 0V
R
R
R
R
R
< 23.2kΩ
= 30.1kΩ
= 47.5kΩ
= 54.9kΩ
= 75.0kΩ
150
250
600
750
1.05
kHz
kHz
OSC
FREQ
FREQ
FREQ
FREQ
FREQ
V
PHSMD
540
660
kHz
kHz
MHz
MHz
MHz
l
l
Maximum Frequency
Minimum Frequency
1.2
19
0.2
21
I
FREQ Pin Output Current
MODE/PLLIN Input Resistance
PLLIN Input Threshold
V
FREQ
= 0.8V
20
µA
FREQ
R
250
kΩ
MODE/PLLIN
MODE/PLLIN
V
V
V
V
Rising
Falling
2
1.2
V
V
MODE/PLLIN
MODE/PLLIN
Low Output Voltage
High Output Voltage
I
I
= –500µA
= 500µA
0.2
5.2
V
V
CLKOUT
LOAD
LOAD
Channel 1-2 Phase Delay
V
V
V
V
V
= 0V
180
180
180
180
120
Deg
Deg
Deg
Deg
Deg
θ – θ
PHSMD
PHSMD
PHSMD
PHSMD
PHSMD
2
1
= 1/4 INTV
= Float
CC
= 3/4 INTV
= INTV
CC
CC
CLKOUT to Channel 1
Phase Delay
V
V
V
V
V
= 0V
60
60
Deg
Deg
Deg
Deg
Deg
θ
– θ
1
PHSMD
PHSMD
PHSMD
PHSMD
PHSMD
CLKOUT
= 1/4 INTV
= Float
CC
90
= 3/4 INTV
= INTV
45
240
CC
CC
Channel 1 to CLKIN Phase Delay
V
V
V
V
V
= 0V
0
90
0
Deg
Deg
Deg
Deg
Deg
θ – θ
PHSMD
PHSMD
PHSMD
PHSMD
PHSMD
1
CLKIN
= 1/4 INTV
= Float
CC
= 3/4 INTV
= INTV
0
CC
0
CC
PWM/PWMEN Outputs
l
l
l
l
PWM
PWM Output High Voltage
I
I
= 500µA
5.0
V
V
LOAD
PWM Output Low Voltage
= –500µA
0.5
5
LOAD
PWM Output Current in Hi-Z State
PWMEN Output High Voltage
–5
µA
V
PWMEN
I
= 500µA
5.0
LOAD
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
specific operating conditions in conjunction with board layout, the package
thermal impedance and other environmental factors.
T is calculated from the ambient temperature, T , and power dissipation,
J
A
P , according to the following formula:
D
Note 2: The LTC3774 is tested under pulsed load conditions such that
LTC3774UHE: T = T + (P • 43°C/W)
Note 3: The LTC3774 is tested in a feedback loop that servos V to a
specified voltage and measures the resultant V
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 5: Guaranteed by design.
J
A
D
T ≈ T . The LTC3774E is guaranteed to meet performance specifications
J
A
ITH
from 0°C to 85°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3774I is guaranteed to meet performance specifications over the
full –40°C to 125°C operating junction temperature range. The maximum
ambient temperature consistent with these specifications is determined by
.
FB
3774fc
4
For more information www.linear.com/LTC3774
LTC3774
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense
Threshold vs Feedback Voltage
(Current Foldback)
Maximum Current Sense Threshold
vs Common Mode Voltage
Current Sense Threshold
vs ITH Voltage
35
30
25
20
15
10
5
35
30
35
30
I
I
I
I
I
= 0
LIM
LIM
LIM
LIM
LIM
I
I
= INTV
CC
LIM
= 1/4 INTV
= 1/2 INTV
= 3/4 INTV
CC
CC
CC
= 3/4 INTV
= 1/2 INTV
= 1/4 INTV
= 0
LIM
CC
CC
CC
= INTV
CC
25
25
I
I
I
LIM
LIM
LIM
20
15
10
5
20
15
10
5
0
INTV
3/4 INTV
1/2 INTV
1/4 INTV
0
CC
CC
–5
–10
CC
CC
0
0
0.25 0.5
0.75
V(I ) (V)
1
1.25 1.5 1.75
2
0
0.5
1
3.5
0
1.5
2
2.5
3
0.1
0.6
0
0.2
0.3
0.4
0.5
COMMON MODE VOLTAGE (V)
FEEDBACK VOLTAGE (V)
TH
3774 G03
3774 G01
3774 G02
Input Quiescent Current
vs Input Voltage
Shutdown Current
vs Input Voltage
INTVCC Line Regulation
6
12
10
8
60
50
40
30
20
10
0
5
4
3
2
1
0
6
4
2
0
5
10
40
0
15 20 25 30 35
INPUT VOLTAGE (V)
5
10
40
5
10
40
0
15 20 25 30 35
INPUT VOLTAGE (V)
0
15 20 25 30 35
INPUT VOLTAGE (V)
3774 G06
3774 G04
3774 G05
Oscillator Frequency
vs Input Voltage
Load Step (Continuous
Conduction Mode)
1200
V
IN
= 12V
75kΩ
V
= 1.5V
1000
800
600
400
200
0
OUT
50mV/DIV
AC-COUPLED
47.5kΩ
I
LOAD
5A-DIV
15A TO 30A
3774 G08
50µs/DIV
23.2kΩ
5
10
40
0
15 20 25 30 35
INPUT VOLTAGE (V)
3774 G07
3774fc
5
For more information www.linear.com/LTC3774
LTC3774
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency
Power Loss
Efficiency
100
90
80
70
60
50
40
30
20
10
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
100
90
80
70
60
50
40
30
20
10
0
V
V
= 7V
V
V
= 7V
V
V
= 12V
IN
OUT
IN
OUT
IN
OUT
= 1.5V
= 1.5V
= 1.5V
BURST MODE
PULSE-SKIPPING
CCM
BURST MODE
PULSE-SKIPPING
CCM
BURST MODE
PULSE-SKIPPING
CCM
0.1
1
100
0.01
10
0.1
1
100
0.1
1
100
0.01
10
0.01
10
I
(A)
I
(A)
I
(A)
LOAD
LOAD
LOAD
3774 G09
3774 G10
3774 G11
TK/SS Pull-Up Current
vs Temperature
Power Loss
RUN Threshold vs Temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.5
1.4
1.3
1.2
1.1
1
1.4
1.3
1.2
1.1
1.0
0.9
V
V
= 12V
IN
OUT
= 1.5V
BURST MODE
PULSE-SKIPPING
CCM
ON
OFF
0.1
1
100
–25
0
75 100
150
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3774 G14
0.01
10
–50
25 50
125
I
(A)
TEMPERATURE (°C)
LOAD
3774 G12
3774 G13
Regulated Feedback Voltage
vs Temperature
Oscillator Frequency
vs Temperature
Undervoltage Lockout Threshold
(INTVCC) vs Temperature
604.5
603.0
601.5
600.0
598.5
597.0
595.5
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
700
675
650
625
600
575
550
525
500
RISE
FALL
–25
0
75 100
150
125
–50
25 50
–25
0
75 100
150
125
–50
25 50
125
100
150
–50
50
–25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3774 G15
3774 G16
3774 G17
3774fc
6
For more information www.linear.com/LTC3774
LTC3774
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current vs Temperature
Shutdown Current vs Temperature
10.00
9.75
9.50
9.25
9.00
8.75
8.50
8.25
8.00
60
55
50
45
40
35
30
25
20
–25
0
75 100
150
–25
0
75 100
150
125
–50
25 50
125
–50
25 50
TEMPERATURE (°C)
TEMPERATURE (°C)
3774 G18
3774 G19
FREQ Pin Source Current
vs Temperature
Prebiased Output at 0.5V
21.5
21.0
20.5
20.0
19.5
19.0
18.5
V
OUT
500mV/DIV
TRACK/SS
500mV/DIV
3774 G08
50ms/DIV
–25
0
75 100
150
125
–50
25 50
TEMPERATURE (°C)
3774 G20
3774fc
7
For more information www.linear.com/LTC3774
LTC3774
PIN FUNCTIONS
PGOOD1, PGOOD2 (Pin 15, Pin 14): Power Good Indica-
tor Outputs. Open drain outputs that pull to ground when
output voltage is not in regulation.
–
–
V
, V
(Pin 26, Pin 3): Remote Sense Differ-
OSNS1
OSNS2
ential Amplifier Inverting inputs. Connect to sense ground
at the output load.
+
+
SNSA1 , SNSA2 (Pin 16, Pin 13): AC Current Sense
Comparator (+) Inputs. This input senses the signal from
the output inductor’s DCR with a filter bandwidth of five
times larger than the inductor’s L/DCR value.
ITH1, ITH2 (Pin 2ꢀ, Pin 2): Current Control Thresholds
and Error Amplifier Compensation Points. The current
comparator’s threshold increases with the ITH control
voltage.
–
–
SNS1 , SNS2 (Pin 1ꢀ, Pin 12): Negative current Sense
Inputs. The negative input of the current comparator is
normally connected to the output.
ITEMP1, ITEMP2(Pin28, Pin1):Inputofthetemperature
sensing comparators. Connect this pin to an external NTC
resistorplacedneartheinductors.Floatingthispindisables
the DCR temperature compensation function.
+
+
SNSD1 , SNSD2 (Pin 18, Pin 11): DC Current Sense
Comparator (+) Inputs. This input senses the signal from
the output inductor’s DCR with a filter bandwidth equal to
the inductor’s L/DCR value.
ILIM1, ILIM2(Pin29, Pin36):CurrentComparatorSense
Voltage Limit Selection pins.
PHSMD (Pin 30): Phase Mode Pin. This pin selects CH1-
CH2 and CH1-CLKOUT phase relationships.
RUN1, RUN2 (Pin 20, Pin 9): Run Control Inputs. A volt-
age above 1.22V turns on the IC. There is a 1µA pull-up
current on this pin. Once the RUN pin rises above the
1.22V threshold the pull-up increases to 5µA.
FREQ (Pin 31): Frequency Set/Select Pin. A resistor
between this pin and GND sets the switching frequency.
This pin sources 20uA.
PMW1, PWM2 (Pin 21, Pin 8):(Top) Gate Signal Outputs.
This signal goes to the PWM or top gate input of the ex-
ternal gate driver or integrated driver MOSFET or Power
Block. This is a three-state compatible output.
MODE/PLLIN (Pin 32): Dual Function Pin. Tying this pin
to GND, INTV or floating it enables forced continuous
CC
mode, pulse-skipping mode or Burst Mode operation re-
spectively. Applying a clock signal to this pin causes the
internal PLL to synchronize the internal oscillator to the
clock signal and forces forced continuous mode. The PLL
compensation network is integrated on to the IC.
PWMEN1, PWMEN2 (Pin 22, Pin ꢀ): Enable pins for non-
three-state compatible drivers. This pin has an internal
open-drain pull-up to INTV . An external resistor to GND
CC
is required. This pin is low when the corresponding PWM
CLKOUT (Pin 33): Clock Output Pin. This pin is used to
synchronize other LTC3774s.
pin is high impedance.
HIZB1, HIZB2(Pin23, Pin6):PhaseSheddingInputPins.
INTV (Pin 34): Internal 5.5V Regulator Output. The con-
CC
When this pin is low, the corresponding PWM pin goes
trol circuits are powered from this voltage. Decouple this
pin to GND with a minimum of 4.7µF low ESR tantalum
or ceramic capacitor. This pin is intended to be used as a
reference only. Please do not bias other applications off
this voltage!
high impedance and PWMEN goes low. Tie to INTV or
CC
V to disable this function.
IN
TK/SS1, TK/SS2 (Pin 24, Pin 5): Output Voltage Tracking
and Soft-Start Inputs. The voltage ramp rate at this pin
sets the voltage ramp rate of the output. A capacitor to
ground accomplishes soft-start. This pin has a 1.25µA
pull-up current.
V (Pin 35): Main Input Supply. Decouple this pin to GND
IN
with a capacitor (0.1µF to 1µF)
GND (Pins 19, 10, Exposed Pad Pin 3ꢀ): Ground. All
small-signalcomponentsandcompensationcomponents
should be connected here. The exposed pad must be
soldered to the PCB ground for electrical connection and
rated thermal performance.
+
+
V
, V
(Pin 25, Pin 4): Remote Sense Differ-
OSNS1
OSNS2
entialAmplifierNon-invertingInputs.ConnecttoFeedback
divider center tap with the divider across the output load.
Theremotesensedifferentialamplifier’soutputisinternally
connected to the error amplifier inverting input.
3774fc
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For more information www.linear.com/LTC3774
LTC3774
FUNCTIONAL BLOCK DIAGRAM
ITEMP
HIZB
PHSMD
MODE/PLLIN
FREQ
TEMPSNS
V
IN
0.6V
MODE/SYNC
DETECT
5.5V
REG
+
–
INTV
CC
F
PLL-SYNC
BURST EN
PWM
CLKOUT
FCNT
OSC
INTV
CC
S
R
ON
Q
PWMEN
–
+
+
–
SNSA
SWITCH
LOGIC
I
I
REV
CMP
–
+
SNS
RUN
OV
ILIM
PGOOD
SLOPE
COMPENSATION
+
–
0.555V
INTV
CC
UVLO
UV
OV
1
+
SNSD
R
ACTIVE CLAMP
I
+
THB
AMP
–
SNS
–
+
–
SLEEP
+
V
V
OSNS
0.645V
GND
+
–
1/2
V
IN
– SS
– RUN
+
+
DIFFAMP
1.25µA
EA
0.6V
REF
–
–
+ +
+
0.5V
1.22V
–
OSNS
20k
20k
0.55V
1µA/5µA
3774 BD
C
C1
C
SS
ITH
RUN
TK/SS
R
C
NOTE: FUNCTIONAL BLOCK DIAGRAM SHOWS 1 CHANNEL ONLY. THE 2 CHANNELS ARE IDENTICAL.
3774fc
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For more information www.linear.com/LTC3774
LTC3774
OPERATION
Main Control Loop
5mV steps with the ILIM pin. The filter time constant,
+
R1C1, of the SNSD should match the L/DCR of the output
The LTC3774 uses an LTC proprietary current sensing,
current mode step-down architecture. During normal
operation, the top MOSFET is turned on every cycle when
the oscillator sets the RS latch, and turned off when the
main current comparator, I
peak inductor current at which I
+
+
inductor,whilethefilteratSNSA shouldhaveabandwidth
of five times larger than SNSD , R2•C2 equals R1•C1/5.
Internal Soft-Start
, resets the RS latch. The
CMP
CMP
By default, the start-up of the output voltage is normally
controlledby an internalsoft-start ramp. The internalsoft-
resets the RS latch
is controlled by the voltage on the ITH pin, which is the
outputoftheerroramplifier,EA.Theremotesenseamplifier
(diffamp)producesasignalequaltothedifferentialvoltage
sensed across the output capacitor divided down by the
feedbackdividerandre-referencesittothelocalICground
reference.Theerroramplifierreceivesthisfeedbacksignal
and compares it to the internal 0.6V reference. When the
start ramp represents a noninverting input to the error
+
amplifier. The V
pin is regulated to the lower of the
OSNS
error amplifier’s three noninverting inputs (the internal
soft-start ramp, the TK/SS pin or the internal 600mV ref-
erence). As the ramp voltage rises from 0V to 0.6V over
approximately 600µs, the output voltage rises smoothly
from its prebiased value to its final set value.
load current increases, it causes a slight decrease in the
+
V
OSNS
pin voltage relative to the 0.6V reference, which in
Certain applications can result in the start-up of the con-
verter into a non-zero load voltage, where residual charge
is stored on the output capacitor at the onset of converter
switching. Inordertopreventtheoutputfromdischarging
turn causes the ITH voltage to increase until the inductor’s
average current equals the new load current. After the top
MOSFET has turned off, the bottom MOSFET is turned
on until either the inductor current starts to reverse, as
indicated by the reverse current comparator, I , or the
beginning of the next cycle.
under these conditions, the bottom MOSFET is disabled
+
REV
until soft-start is greater than V
.
OSNS
Shutdown and Start-Up (RUN and TK/SS Pins)
The main control loop is shut down by pulling the RUN
pin low. Releasing RUN allows an internal 1.0µA current
source to pull up the RUN pin. When the RUN pin reaches
1.22V, the main control loop is enabled and the IC is
powered up. When the RUN pin is low, all functions are
kept in a controlled state.
The LTC3774 can be shut down using the RUN pin.
Pulling the RUN pin below 1.14V shuts down the main
control loop for the controller and most internal circuits,
including the INTV regulator. Releasing the RUN pin
CC
allows an internal 1.0µA current to pull up the pin and
enable the controller. Alternatively, the RUN pin may be
externally pulled up or driven directly by logic. Be careful
not to exceed the absolute maximum rating of 6V on this
Sensing Signal of Very Low DCR
The LTC3774 employs a unique architecture to enhance
the signal-to-noise ratio that enables it to operate with a
small sense signal of a very low value inductor DCR, 1mΩ
or less, to improve power efficiency, and reduce jitter due
to the switching noise which could corrupt the signal. The
LTC3774 can sense a DCR value as low as 0.2mΩ with
careful PCB layout.The LTC3774 comprises two positive
pin. The start-up of the controller’s output voltage, V
,
OUT
is controlled by the voltage on the TK/SS pin. When the
voltage on the TK/SS pin is less than the 0.6V internal
+
reference, the LTC3774 regulates the V
voltage to
OSNS
the TK/SS pin voltage instead of the 0.6V reference. This
allows the TK/SS pin to be used to program a soft-start
by connecting an external capacitor from the TK/SS pin
to GND. An internal 1.25µA pull-up current charges this
capacitor, creating a voltage ramp on the TK/SS pin. As
the TK/SS voltage rises linearly from 0V to 0.6V (and
+
+
sense pins, SNSD and SNSA , to acquire signals and
processes them internally to provide the response as with
a DCR sense signal that has a 14dB signal-to-noise ratio
improvement. In the meantime, the current limit threshold
is still a function of the inductor peak current and its DCR
value, and can be accurately set from 10mV to 30mV in
beyond), the output voltage, V , rises smoothly from
OUT
zero to its final value. Alternatively, the TK/SS pin can be
3774fc
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For more information www.linear.com/LTC3774
LTC3774
OPERATION
used to cause the start-up of V
to track that of another
this mode, the efficiency at light loads is lower than in
BurstModeoperation.However,continuousmodehasthe
advantages of lower output ripple and less interference
with audio circuitry.
OUT
supply. Typically, this requires connecting to the TK/SS
pin an external resistor divider from the other supply to
ground (see the Applications Information section). When
theRUNpinispulledlowtodisablethecontroller, orwhen
When the MODE/PLLIN pin is connected to INTV , the
CC
INTV drops below its undervoltage lockout threshold of
CC
LTC3774 operates in PWM pulse skipping mode at light
3.75V, the TK/SS pin is pulled low by an internal MOSFET.
When in undervoltage lockout, the controller is disabled
and the external MOSFETs are held off.
loads. At very light loads, the current comparator, I
,
CMP
mayremaintrippedforseveralcyclesandforcetheexternal
topMOSFETtostayoffforthesamenumberofcycles(i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuousoperation, exhibitslowoutputrippleaswellas
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Continuous Conduction)
The LTC3774 can be enabled to enter high efficiency Burst
Modeoperation,constant-frequencypulse-skippingmode
or forced continuous conduction mode. To select forced
continuous operation, tie the MODE pin to GND. To select
pulse-skipping mode of operation, tie the MODE/PLLIN
pin to INTV . To select Burst Mode operation, float the
Frequency Selection and Phase-Locked Loop
(FREQ and MODE/PLLIN Pins)
CC
MODE/PLLINpin. WhenthecontrollerisenabledforBurst
Mode operation, the peak current in the inductor is set to
approximately one-third of the maximum sense voltage
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
even though the voltage on the I pin indicates a lower
TH
value. If the average inductor current is higher than the
load current, the error amplifier, EA, will decrease the
voltage on the I pin. When the I voltage drops below
TH
TH
If the MODE/PLLIN pin is not being driven by an external
clock source, the FREQ pin can be used to program the
controller’s operating frequency from 200kHz to 1.2MHz.
There is a precision 20µA current flowing out of the FREQ
pinsothattheusercanprogramthecontroller’sswitching
frequencywithasingleresistortoGND.Acurveisprovided
later in the Applications Information section showing the
relationship between the voltage on the FREQ pin and
switching frequency.
0.5V, the internal sleep signal goes high (enabling “sleep”
mode) and both external MOSFETs are turned off.
In sleep mode, the load current is supplied by the output
capacitor.Astheoutputvoltagedecreases,theEA’soutput
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When the controller
is enabled for Burst Mode operation, the inductor current
is not allowed to reverse. The reverse current comparator
A phase-locked loop (PLL) is available on the LTC3774
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The PLL
loop filter network is integrated inside the LTC3774. The
phase-locked loop is capable of locking any frequency
withintherangeof200kHzto1.2MHz.Thefrequencysetting
resistor should always be present to set the controller’s
initial switching frequency before locking to the external
clock. The controller operates in forced continuous mode
(I ) turns off the bottom external MOSFET just before
REV
the inductor current reaches zero, preventing it from re-
versing and going negative. Thus, the controller operates
in discontinuous operation.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the I pin, just as in normal operation. In
TH
when it is synchronized.
3774fc
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For more information www.linear.com/LTC3774
LTC3774
OPERATION
0,120
240,60
LTC3774
0,180
LTC3774
90,270
LTC3774
LTC3774
MODE/PLLIN
MODE/PLLIN
MODE/PLLIN
MODE/PLLIN
+240
+90
CLKOUT
CLKOUT
CLKOUT
CLKOUT
INTV
PHSMD
PHSMD
PHSMD
PHSMD
CC
3774 F01a
3774 F01b
Figure 1a. 3-Phase Operation
Figure 1b. 4-Phase Operation
0,180
LTC3774
60,240
LTC3774
120,300
LTC3774
MODE/PLLIN
CLKOUT
MODE/PLLIN
MODE/PLLIN
CLKOUT
+60
+60
CLKOUT
PHSMD
PHSMD
PHSMD
3774 F01c
Figure 1c. 6-Phase Operation
0,180
LTC3774
90,270
135,315
LTC3774
225,45
LTC3774
LTC3774
MODE/PLLIN
MODE/PLLIN
MODE/PLLIN
MODE/PLLIN
+90
+90
+45
CLKOUT
CLKOUT
CLKOUT
CLKOUT
PHSMD
3/4 INTV
PHSMD
PHSMD
PHSMD
CC
3774 F01d
Figure 1d. 8-Phase Operation
0,180
60,240
120,300
LTC3774
LTC3774
LTC3774
MODE/PLLIN
MODE/PLLIN
MODE/PLLIN
+60
+60
CLKOUT
CLKOUT
CLKOUT
PHSMD
PHSMD
PHSMD
150,330
LTC3774
210,30
LTC3774
270,90
LTC3774
MODE/PLLIN
MODE/PLLIN
MODE/PLLIN
+60
+60
CLKOUT
CLKOUT
CLKOUT
1/4 INTV
PHSMD
PHSMD
PHSMD
CC
3774 F01e
Figure 1e. 12-Phase Operation
3774fc
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For more information www.linear.com/LTC3774
LTC3774
OPERATION
Multiphase Operation
Sensing the Output Voltage with a
Differential Amplifier
For output loads that demand high current, multiple
LTC3774scanbedaisychainedtorunoutofphasetoprovide
more output current without increasing input and output
voltageripple.TheMODE/PLLINpinallowstheLTC3774to
synchronizetotheCLKOUTsignalofanotherLTC3774.The
CLKOUTsignalcanbeconnectedtotheMODE/PLLINpinof
the following LTC3774 stage to line up both the frequency
andthephaseoftheentiresystem.TyingthePHSMDpinto
The LTC3774 includes a low offset, high input impedance,
unity-gain, high bandwidth differential amplifier for ap-
plications that require true remote sensing. Sensing the
loadacrosstheloadcapacitorsdirectlybenefitsregulation
in high current, low voltage applications, where board
interconnection losses can be a significant portion of the
+
total error budget. Connect V
to the center tap of the
OSNS
–
INTV , GND or floating it generates a phase difference
feedback divider across the output load, and V
the load ground. See Figure 2.
to
CC
OSNS
(between CH1 and CLKOUT) of 240°, 60° or 90° respec-
tively, and a phase difference (between CH1 and CH2) of
The LTC3774 differential amplifier is configured for unity
120°, 180° or 180°. Tying PHSMD to 1/4 or 3/4 of INTV
+
CC
gain, meaning that the difference between V
and
OSNS
generates a phase difference of 60° and 45° between CH1
and CLKOUT. Figure 1 shows the PHSMD connections
necessary for 3-, 4-, 6-, 8- or 12-phase operation. A total
of 12 phases can be daisychained to run simultaneously
out of phase with respect to each other.
–
V
is translated to its output, relative to GND. The
OSNS
differential amplifier’s output is internally connected to
the error amplifier inverting input.
+
–
Care should be taken to route the V
and V
PCB
OSNS
OSNS
tracesparalleltoeachotherallthewaytotheremotesens-
ing points on the board. In addition, avoid routing these
sensitive traces near any high speed switching nodes in
+
–
the circuit. Ideally, the V
and V
traces should
OSNS
OSNS
be shielded by a low impedance ground plane to maintain
signal integrity.
V
OUT
10Ω
LTC3774
+
R
R
C
F1
D1
D2
V
V
OSNS
C
OUT2
C
OUT1
+
DIFFAMP
10Ω
–
OSNS
–
3774 F02
Figure 2. Differential Amplifier Connection
3774fc
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For more information www.linear.com/LTC3774
LTC3774
OPERATION
Power Good (PGOOD Pin)
Undervoltage Lockout
The PGOOD pin is connected to the open drain of an inter-
The LTC3774 has two functions that help protect the
controller in case of undervoltage conditions. A precision
nal N-channel MOSFET. The MOSFET turns on and pulls
+
the PGOOD pin low when the V
pin voltage is not
UVLOcomparatorconstantlymonitorstheINTV voltage
OSNS
CC
within 7.5% of the 0.6V reference voltage. The PGOOD
pin is also pulled low when the RUN pin is below 1.14V
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTV is below
CC
or when the LTC3774 is in the soft-start or tracking up
3.75V. To prevent oscillation when there is a disturbance
+
phase. When the V
pin voltage is within the 7.5%
on the INTV , the UVLO comparator has 500mV of preci-
OSNS
CC
regulation window, the MOSFET is turned off and the
pin is allowed to be pulled up by an external resistor to a
sion hysteresis.
Another way to detect an undervoltage condition is to
source of up to 6V. The PGOOD pin will flag power good
monitor the V supply. Because the RUN pin has a preci-
IN
+
immediately when the V
pin is within the regulation
OSNS
sion turn-on reference of 1.22V, one can use a resistor
window. However, there is an internal 45µs power-bad
divider to V to turn on the IC when V is high enough.
IN
IN
+
mask when the V
goes out of the window.
OSNS
An extra 4µA of current flows out of the RUN pin once the
RUN pin voltage passes 1.22V. The RUN comparator itself
hasabout80mVofhysteresis.Onecanprogramadditional
hysteresisfortheRUNcomparatorbyadjustingthevalues
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In such cases, the
topMOSFETisturnedoffandthebottomMOSFETisturned
on until the overvoltage condition is cleared.
of the resistive divider. For accurate V undervoltage
IN
detection, V needs to be higher than 4.75V. Always
IN
set the V undervoltage detection threshold higher than
IN
the power stage UVLO threshold so that the LTC3774 is
enabled after the power stage is.
3774fc
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For more information www.linear.com/LTC3774
LTC3774
APPLICATIONS INFORMATION
+
+
–
The Typical Application on the first page of this data sheet
is a basic LTC3774 application circuit. The LTC3774 is
designed and optimized for use with a very low DCR
value by utilizing a novel approach to reduce the noise
sensitivity of the sensing signal by a factor of 14dB. DCR
sensing is becoming popular because it saves expensive
current sensing resistors and is more power efficient,
especially in high current applications. However, as the
DCR value drops below 1mΩ, the signal-to-noise ratio
is low and current sensing is difficult. LTC3774 uses an
LTC proprietary technique to solve this issue. In general,
externalcomponentselectionisdrivenbytheloadrequire-
ment, and begins with the DCR and inductor value. Next,
power MOSFETs are selected. Finally, input and output
capacitors are selected.
SNSD , SNSA and SNS Pins
+
–
The SNSA and SNS pins are the inputs to the current
comparators, while the SNSD+ pin is the input of an
internal amplifier. The operating input voltage range is
0V to 3.5V for all three sense pins. All the positive sense
pins that are connected to the current comparator or the
amplifier are high impedance with input bias currents
of less than 1µA, but there is also a resistance of about
300k from the SNS– pin to ground. The SNS– should
be connected directly to VOUT. The SNSD+ pin connects
to the filter that has a R1•C1 time constant matched to
L/DCR of the inductor. The SNSA+ pin is connected to
the second filter with the time constant one-fifth that
of R1•C1. Care must be taken not to float these pins
during normal operation. Filter components, especially
capacitors, must be placed close to the LTC3774, and
the sense lines should run close together to a Kelvin con-
nection underneath the current sense element (Figure 3).
Because the LTC3774 is designed to be used with a very
low DCR value to sense inductor current, without proper
care, theparasiticresistance, capacitanceandinductance
will degrade the current sense signal integrity, making
the programmed current limit unpredictable. As shown
in Figure 4, resistors R1 and R2 are placed close to the
output inductor and capacitors C1 and C2 are close to
the IC pins to prevent noise coupling to the sense signal.
Current Limit Programming
The ILIM pin is a 5-level logic input which sets the maxi-
mum current limit of the controller. When ILIM is either
grounded, floated or tied to INTV , the typical value for
CC
the maximum current sense threshold will be 10mV,
20mV or 30mV, respectively. Setting ILIM to one-fourth
INTV and three-fourths INTV for maximum current
CC
CC
sense thresholds of 15mV and 25mV. Setting I
using
LIM
a resistor divider off of INTV will allow the maximum
CC
current sense threshold setting to not change when the
5.5V LDO is in dropout at start-up. Please note that the
TO SENSE FILTER,
NEXT TO THE CONTROLLER
I
pin has an internal 500k pull-down to GND and a 500k
LIM
pull-up to INTV .
CC
C
Which setting should be used? For the best current limit
accuracy, use the highest setting that is applicable to the
output requirements.
OUT
3774 F03
INDUCTOR
Figure 3. Sense Lines Placement with Inductor DCR
3774fc
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For more information www.linear.com/LTC3774
LTC3774
APPLICATIONS INFORMATION
V
V
IN
IN
5V
V
V
BOOST
TG
LOGIC
CC
INDUCTOR
LTC3774
PWM
L
DCR
LTC4449
V
OUT
IN
TS
R
ITEMP
R
ITEMP
BG
R1 R2
S
20k
+
–
SNSD
C1
C2
SNS
R
100k
R
+
NTC
P
SNSA
3774 F04
43.2k
GND
PLACE C1, C2 NEXT TO IC
PLACE R1, R2 NEXT TO INDUCTOR
R1C1 = 5 • R2C2
Figure 4. Inductor DCR Current Sensing
The LTC3774 could also be used like any typical current
mum desirable sense voltage, and uses the relationship
of the sense pin filters to output inductor characteristics
as depicted below.
+
mode controller by disabling the SNSD pin, shorting it
to ground. An R
resistor or a RC filter can be used
SENSE
to sense the output inductor signal and connects to the
VSENSE(MAX)
+
SNSA pin. If the RC filter is used, its time constant,
DCR =
∆IL
R • C, is equaled to L/DCR of the output inductor. In these
IMAX
+
2
applications, the current limit, V
, will be five
SENSE (MAX)
times larger for the specified ILIM, and the operating
L/DCR = R1• C1 = 5 • R2 • C2
where:
+
–
voltage range of SNSA and SNS is from 0V to 5.25V.
Inductor DCR Sensing
V
: Maximum sense voltage for a given ILIM
SENSE(MAX)
threshold
The LTC3774 is specifically designed for high load current
applications requiring the highest possible efficiency; it is
capable of sensing the signal of an inductor DCR in the
sub milliohm range (Figure 4). The DCR is the DC winding
resistanceoftheinductor’scopper,whichisoftenlessthan
1mΩ for high current inductors. In high current and low
output voltage applications, a conduction loss of a high
DCR or a sense resistor will cause a significant reduction
in power efficiency. For a specific output requirement,
chose the inductor with the DCR that satisfies the maxi-
I : Maximum load current
MAX
∆I : Inductor ripple current
L
L, DCR: Output inductor characteristics
+
R1•C1: Filter time constant of the SNSD pin
+
R2•C2: Filter time constant of the SNSA pin
3774fc
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For more information www.linear.com/LTC3774
LTC3774
APPLICATIONS INFORMATION
Toensurethattheloadcurrentwillbedeliveredoverthefull
operatingtemperaturerange,thetemperaturecoefficientof
DCR resistance, approximately 0.4%/°C, should be taken
into account. The LTC3774 features a DCR temperature
compensationcircuitthatusesanNTCtemperaturesensing
resistor for this purpose. See the Inductor DCR Sensing
Temperature Compensation section for details.
currents. However, the DCR of the inductor, which is the
small amount of DC winding resistance of the copper,
typically has a positive temperature coefficient. As the
temperatureoftheinductorrises, itsDCRvalueincreases.
The current limit of the controller is therefore reduced.
The LTC3774 offers a method to counter this inaccuracy
by allowing the user to place an NTC temperature sensing
resistorneartheinductortoactivelycorrectthiserror. The
ITEMPpin, whenleftfloating, isatavoltagearound5Vand
DCR temperature compensation is disabled. The ITEMP
pin has a constant 30µA precision current flowing out the
pin. By connecting an NTC resistor from the ITEMP pin
to SGND, the maximum current sense threshold can be
variedovertemperatureaccordingthefollowingequation:
Typically, C1 and C2 are selected in the range of 0.047µF
to 0.47µF. If C1 and C2 are chosen to be 220nF, and an
inductor of 330nH with 0.32mΩ DCR is selected, R1 and
R2 will be 4.7k and 942Ω respectively. The bias current at
+
+
SNSD and SNSA is about 30nA and 500nA respectively,
and it causes some small error to the sense signal.
There will be some power loss in R1 and R2 that relates to
the duty cycle, and will be the most in continuous mode
at the maximum input voltage:
V
2.8
1.5
ITEMP
2–
VSENSEMAX(ADJ) = VSENSE(MAX)
•
V
IN(MAX) – VOUT • V
(
)
OUT
P
R =
LOSS ( )
where:
R
V
isthemaximumadjustedcurrentsense
is the maximum current sense threshold
SENSEMAX(ADJ)
threshold.
EnsurethatR1andR2haveapowerratinghigherthanthis
value. However, DCR sensing eliminates the conduction
loss of a sense resistor; it will provide a better efficiency
at heavy loads. To maintain a good signal-to-noise ratio
V
SENSE(MAX)
specifiedintheElectricalCharacteristicstable.Itistypi-
cally 30mV, 25mV, 20mV, 15mV or 10mV depending
for the current sense signal, using a minimum ∆V
of
SENSE
2mV for duty cycles less than 40% is desirable. The actual
ripplevoltagewillbedeterminedbythefollowingequation:
on the setting I pins.
LIM
V
is the voltage of the ITEMP pin.
ITEMP
VOUT V – V
IN
OUT
∆VSENSE
=
•
ThevalidvoltagerangeforDCRtemperaturecompensation
on the ITEMP pin is 1.4V to 0.6V, with 1.4V or above being
no DCR temperature correction and 0.6V the maximum
correction.However,ifthedutycycleofthecontrollerisless
than 25%, the ITEMP range is extended from 1.4V to 0V.
V
R1• C1• fOSC
IN
Inductor DCR Sensing Temperature Compensation
and the ITEMP Pin
Inductor DCR current sensing provides a lossless method
of sensing the instantaneous current. Therefore, it can
provide higher efficiency for applications of high output
The NTC resistor has a negative temperature coefficient,
meaning its value decreases as temperature rises. The
ITEMP
V
voltage, therefore, decreases as temperature
3774fc
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For more information www.linear.com/LTC3774
LTC3774
APPLICATIONS INFORMATION
increases and in turn, the V
will increase to
Calculate the values for R and R . A simple method is to
P S
SENSEMAX(ADJ)
compensate the DCR temperature coefficient. The NTC
resistor, however, is nonlinear and the user can linear-
ize its value by building a resistor network with regular
resistors. Consult the NTC manufacturer’s data sheets for
detailed information.
graph the following R versus R equations with R on
S
P
S
the y-axis and R on the x-axis.
P
R = R
– R
|| R
S
ITEMP25C
NTC25C
P
R = R
– R || R
NTC100C P
S
ITEMP100C
Next, find the value of R that satisfies both equations
Another use for the ITEMP pins, in addition to NTC com-
P
which will be the point where the curves intersect. Once
R is known, solve for R .
pensated DCR sensing, is adjusting V
to values
SENSE(MAX)
betweenthenominalvaluesof10mV,15mV,20mV,25mV
and 30mV for a more precise current limit. This is done
by applying a voltage less than 1.4V to the ITEMP pin.
P
S
The resistance of the NTC thermistor can be obtained
from the vendor’s data sheet either in the form of graphs,
tabulated data or formulas. The approximate value for the
NTC thermistor for a given temperature can be calculated
from the following equation:
V
will be varied per the previous equation and
SENSE(MAX)
the same duty cycle limitations will apply. The current
limitcan be adjusted usingthis methodeitherwith asense
resistor or DCR sensing.
⎛
⎞
⎛
⎞
1
1
R=RO •exp B•
–
⎜
⎟
NTC Compensated DCR Sensing
⎜
⎟
T+273 T +273
⎝
⎠
⎝
⎠
O
For DCR sensing applications where a more accurate
current limit is required, a network consisting of an NTC
thermistorplacedfromtheITEMPpintogroundwillprovide
correction of the current limit over temperature. Figure 4
where:
R = resistance at temperature T, which is in degrees C
R = resistance at temperature T , typically 25°C
O
O
shows this network. Resistors R and R will linearize
S
P
the impedance the ITEMP pin sees. To implement NTC
compensated DCR sensing, design the DCR sense filter
networkperthesameprocedurementionedintheprevious
selection, except calculate the divider components using
the room temperature value of the DCR.
B = B-constant of the thermistor.
Figure 5 shows a typical resistance curve for a 100k
thermistor and the ITEMP pin network over temperature.
Starting values for the NTC compensation network are
listed below:
1. Set the ITEMP pin resistance to 46.7k at 25°C. With
30µA flowing out of the ITEMP pin, the voltage on the
ITEMP pin will be 1.4V at room temperature. Current
limit correction will occur for inductor temperatures
greater than 25°C.
• NTC R = 100k
O
• R = 20k
S
• R = 50k
P
But, the final values should be calculated using the above
equations and checked at 25°C and 100°C.
2. Calculate the ITEMP pin resistance and the maximum
inductor temperature which is typically 100°C. Use the
equations:
V
ITEMP100C
30µA
RITEMP100C
=
I
•DCR(MAX)•R2/ R1+R2 • 100°C–25°C •0.4/100
(
)
(
)
V
ITEMP100C =1.4V –4.2 MAX
VSENSE(MAX)
3774fc
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For more information www.linear.com/LTC3774
LTC3774
APPLICATIONS INFORMATION
10000
approach. Figure 6 shows a typical curve of I
inductor temperature.
versus
MAX
THERMISTOR RESISTANCE
R
= 100k
= 25°C
O
O
1000
100
10
The same thermistor network can be used to correct for
temperatures less than 25°C. But make sure V is
T
B = 4334 FOR 25°C/100°C
ITEMP
greater than 0.6V for duty cycles of 25% or more, oth-
erwise temperature correction may not occur at elevated
ambients. For the most accurate temperature detection,
place the thermistors next to the inductor as shown in
Figure 7. Take care to keep the ITEMP pin away from the
switch nodes.
R
S
P
ITEMP
R
= 20k
R
= 43.2k
100k NTC
1
–40 –20
0
20 40 60 80 100 120
INDUCTOR TEMPERATURE (°C)
25
3774 F05
Figure 5. Resistance Versus Temperature for the ITEMP Pin
Network and the 100k NTC
20
CORRECTED
I
MAX
15
After determining the components for the temperature
NOMINAL
MAX
I
compensation network, check the results by plotting I
MAX
UNCORRECTED
10
5
versusinductortemperatureusingthefollowingequations:
R
R
= 20k
I
S
P
MAX
= 43.2k
NTC THERMISTOR:
VSENSEMAX(ADJ) – ∆VSENSE /2
R
= 100k
= 25°C
O
O
IMAX
=
T
DCR(MAX) at 25°C• 1+ T
–25°C •0.4/100
(
)
B = 4334
L(MAX)
0
40
INDUCTOR TEMPERATURE (°C)
–40 –20
0
20
60 80 100 120
where:
3774 F06
V
ITEMP
2.8
Figure 6. Worst-Case IMAX Versus Inductor Temperature Curve
with and without NTC Temperature Compensation
2.0V –
VSENSEMAX(ADJ) = VSENSE(MAX)
•
1.5
V
= 30µA • R +R ||R
ITEMP
P
S
NTC
V
OUT
R
NTC
Use typical values for V
.
SENSE(MAX)
The resulting current limit should be greater than or equal
toI forinductortemperaturesbetween25°Cand100°C.
MAX
L1
These are typical values for the NTC compensation network:
• NTC R = 100k, B-constant = 3000 to 4000
O
SW1
3774 F07
• R ≈ 20k
S
Figure ꢀ. Thermistor Location. Place Thermistor Next to
Inductor for Accurate Sensing of the Inductor Temperature,
But Keep the ITEMP Pin Away from the Switch Nodes and Gate
Drive Traces
• R ≈ 50k
P
GeneratingtheI
versusinductortemperaturecurveplot
MAX
first using the above values as a starting point and then
adjusting the R and R values as necessary is another
S
P
3774fc
19
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LTC3774
APPLICATIONS INFORMATION
Pre-Biased Output Start-Up
Phase Shedding/n+1 Redundancy (HIZB Pin)
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that
output pre-bias. The LTC3774 can safely power up into a
pre-biased output without discharging it.
UnliketheRUNpins,theHIZBpinscausethePWMtoenter
its high impedance state while not pulling down on ITH or
TK/SS. This allows two possibilities: First, one can shed a
phasebasedonloadrequirementsviatheHIZBpin.Thisim-
proveslowcurrentefficiencyinasingleoutputmultiphase
casebyreducingswitchinglosses.Second,forapplications
that require n+1 redundancy, it is now easy to disconnect
a channel with damaged MOSFETs or drivers. When com-
bined with a Hot Swap™ controller, such as the LTC4226,
the HIZB pin could be connected to the gate of the Hot
Swap switch. When a damaged MOSFET triggers the Hot
Swap controller, it also disables the corresponding chan-
nel’s power stage, disconnecting it. Since ITH and TK/SS
are unaffected, it does not affect the rest of the system.
ThepropagationdelayfromHIZBfallingtohighimpedance
on PWM is <200ns.
The LTC3774 accomplishes this by disabling both the top
and bottom MOSFETs until the TK/SS pin voltage and the
+
internal soft-start voltage are above the V
pin volt-
OSNS
+
age. When V
is higher than TK/SS or the internal
OSNS
soft-start voltage, the error amp output is railed low. The
control loop would like to turn the bottom MOSFET on,
which would discharge the output. Disabling both top and
bottom MOSFETs prevents the pre-biased output voltage
from being discharged. When TK/SS and the internal
+
soft-start both cross 500mV or V
, whichever is
OSNS
lower, both top and bottom MOSFETs are enabled. If the
pre-bias is higher than the OV threshold, the bottom gate
is turned on immediately to pull the output back into the
regulation window.
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency, f , directly determine
OSC
Overcurrent Fault Recovery
the inductor’s peak-to-peak ripple current:
When the output of the power supply is loaded beyond its
preset current limit, the regulated output voltage will col-
lapse depending on the load. The output may be shorted
to ground through a very low impedance path or it may
be a resistive short, in which case the output will collapse
partially, until the load current equals the preset current
limit. The controller will continue to source current into
⎛
⎞
⎟
⎠
VOUT V – V
IN
OUT
IRIPPLE
=
⎜
⎝
V
fOSC •L
IN
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
the short. The amount of current sourced depends on
+
the ILIM pin setting and the V
voltage as shown in
OSNS
A reasonable starting point is to choose a ripple current
that is about 40% of I
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
the Current Foldback graph in the Typical Performance
. Note that the largest ripple
OUT(MAX)
Characteristics section.
Upon removal of the short, the output soft starts using
the internal soft-start, thus reducing output overshoot. In
the absence of this feature, the output capacitors would
have been charged at current limit, and in applications
with minimal output capacitance this may have resulted
in output overshoot. Current limit foldback is not disabled
during an overcurrent recovery. The load must step below
the folded back current limit threshold in order to restart
from a hard short.
V – V
VOUT
IN
OUT
fOSC •IRIPPLE
L ≥
•
V
IN
Inductor Core Selection
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
3774fc
20
For more information www.linear.com/LTC3774
LTC3774
APPLICATIONS INFORMATION
size for a fixed inductor value, but it is very dependent on
inductanceselected. Asinductanceincreases, corelosses
go down. Unfortunately, increased inductance requires
moreturnsofwireandthereforecopperlosseswillincrease.
Power MOSFET and Schottky Diode
(Optional) Selection
At least two external power MOSFETs need to be selected:
One N-channel MOSFET for the top (main) switch and one
or more N-channel MOSFET(s) for the bottom (synchro-
nous) switch. The number, type and on-resistance of all
MOSFETsselectedtakeintoaccountthevoltagestep-down
ratio as well as the actual position (main or synchronous)
in which the MOSFET will be used. A much smaller and
much lower input capacitance MOSFET should be used
for the top MOSFET in applications that have an output
voltage that is less than one-third of the input voltage. In
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
applications where V >> V , the top MOSFETs’ on-
IN
OUT
resistance is normally less important for overall efficiency
than its input capacitance at operating frequencies above
300kHz. MOSFET manufacturers have designed special
purposedevicesthatprovidereasonablylowon-resistance
with significantly reduced input capacitance for the main
switch application in switching regulators.
PWM and PWMEN Pins
The PWM pins are three-state compatible outputs, de-
signed to drive MOSFET drivers, DrMOSs, etc which do
not represent a heavy capacitive load. An external resistor
divider may be used to set the voltage to mid-rail while in
the high impedance state.
The peak-to-peak MOSFET gate drive levels are set by the
ThePWMENoutputshaveanopen-drainpull-uptoINTV
CC
internal regulator voltage, V
, requiring the use of
INTVCC
and require an appropriate external pull-down resistor.
This pin is intended to drive the enable pins of the MOS-
FET drivers that do not have three-state compatible PWM
inputs. PWMENislowonlywhenPWMishighimpedance,
and high at any other PWM state.
logic-level threshold MOSFETs in most applications. Pay
closeattentiontotheBV specificationfortheMOSFETs
DSS
as well; many of the logic-level MOSFETs are limited to
30V or less. Selection criteria for the power MOSFETs
include the on-resistance, R , input capacitance,
DS(ON)
When selecting a DrMOS or gate driver to use with the
LTC3774, care must be taken to ensure that the absolute
maximum voltage rating for the DrMOS or gate driver’s
PWM input is not exceeded. The LTC3774’s PWM output
inputvoltageandmaximumoutputcurrent.MOSFETinput
capacitance is a combination of several components but
can be taken from the typical gate charge curve included
on most data sheets (Figure 8). The curve is generated by
forcing a constant input current into the gate of a common
source, current source loaded stage and then plotting the
gate voltage versus time.
driver is biased from INTV , which is typically 5.5V,
CC
while the DrMOS or gate driver is generally biased from
a 5V supply. If the DrMOS or gate driver has a maximum
PWM rating less than 5.5V then tie the V and INTV
IN
CC
V
IN
pins of the LTC3774 together and tie the combined pins
to the 5V supply with a 1Ω or 2.2 Ω resistor. Please a
4.4µF capacitor from the combined V and INTV pins
MILLER EFFECT
V
V
GS
IN
CC
to ground. Refer to Figure 11 for an example. Contact
factory applications support for assistance.
a
b
+
–
V
DS
+
Q
IN
V
GS
–
C
= (Q – Q )/V
B A DS
MILLER
3774 F08
Figure 8. Gate Charge Characteristic
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LTC3774
APPLICATIONS INFORMATION
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
in drain potential in the particular application. V
TH(MIN)
is the data sheet specified typical gate threshold voltage
specified in the power MOSFET data sheet at the specified
drain current. C
is the calculated capacitance using
MILLER
the gate charge curve from the MOSFET data sheet and
the technique described above.
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
while the curve is flat) is specified for a given V drain
DS
which peak at the highest input voltage. For V < 20V,
IN
voltage, but can be adjusted for different V voltages by
DS
the high current efficiency generally improves with larger
multiplying the ratio of the application V to the curve
DS
MOSFETs, whileforV >20V, thetransitionlossesrapidly
IN
specified V values. A way to estimate the C
term
DS
MILLER
increasetothepointthattheuseofahigherR
device
DS(ON)
is to take the change in gate charge from points a and b
withlowerC
actuallyprovideshigherefficiency.The
MILLER
on a manufacturer’s data sheet and divide by the stated
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
V
voltage specified. C
is the most important se-
MILLER
DS
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. C
and C are specified sometimes but
OS
RSS
The term (1 + δ ) is generally given for a MOSFET in the
definitionsoftheseparametersarenotincluded.Whenthe
controller is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
form of a normalized R
vs temperature curve, but
DS(ON)
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
VOUT
MainSwitchDuty Cycle =
An optional Schottky diode across the synchronous
MOSFET conducts during the dead time between the con-
ductionofthetwolargepowerMOSFETs.Thispreventsthe
bodydiodeofthebottomMOSFETfromturningon,storing
chargeduringthedeadtimeandrequiringareverse-recovery
periodwhichcouldcostasmuchasseveralpercentineffi-
ciency.A2Ato8ASchottkyisgenerallyagoodcompromise
for both regions of operation due to the relatively small
averagecurrent.Largerdiodesresultinadditionaltransition
loss due to their larger junction capacitance.
V
IN
⎛
⎜
⎝
⎞
⎟
⎠
V – V
IN
OUT
Synchronous SwitchDuty Cycle =
V
IN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
2
VOUT
PMAIN
=
I
(
1+δ R
+
(
)
)
MAX
DS(ON)
V
IN
⎛
⎜
⎝
⎞
⎟
⎠
IMAX
2
MOSFET Driver Selection
V
R
C
•
(
)
(
)
(
)
IN
DR
MILLER
2
GatedriverICs,DrMOSsandpowerblockswithaninterface
compatible with the LTC3774's three-state PWM outputs
or the LTC3774's PWM/PWMEN outputs can be used.
Always enable the power stage first, before the LTC3774
is enabled.
⎡
⎢
⎢
⎤
⎥
1
1
+
• f
V
– VTH(MIN) VTH(MIN)
⎥
⎣ INTVCC
⎦
2
V – V
IN
OUT
P
=
I
(
1+δ R
(
DS(ON)
)
)
MAX
SYNC
V
IN
C and C
IN
Selection
OUT
where δ is the temperature dependency of R
, R
DS(ON) DR
Incontinuousmode,thesourcecurrentofthetopMOSFET
is the effective top driver resistance (approximately 2Ω at
= V ), V is the drain potential and the change
is a square wave of duty cycle (V )/(V ). To prevent
OUT
IN
V
GS
MILLER
IN
large voltage transients, a low ESR capacitor sized for the
3774fc
22
For more information www.linear.com/LTC3774
LTC3774
APPLICATIONS INFORMATION
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
ment is satisfied the capacitance is adequate for filtering.
The steady-state output ripple (∆V ) is determined by:
OUT
IMAX
1/2
⎛
⎞
⎟
⎠
1
⎡
⎤
CIN Required IRMS
≈
V
OUT )(
V – V
IN
OUT
(
)
⎦
⎣
∆VOUT ≈ ∆IRIPPLE ESR+
⎜
V
IN
8fCOUT
⎝
This formula has a maximum at V = 2V , where I
RMS
IN
OUT
where f = operating frequency, C
= output capacitance
OUT
= I /2. This simple worst-case condition is commonly
OUT
and ∆I
= ripple current in the inductor. The output
RIPPLE
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturers’ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3774, ceramic capacitors
ripple is highest at maximum input voltage since ∆I
RIPPLE
increases with input voltage. The output ripple will be less
than 50mV at maximum V with ∆I
= 0.4I
IN
RIPPLE
OUT(MAX)
assuming:
C
OUT
required ESR < N • R
SENSE
and
1
can also be used for C . Always consult the manufacturer
IN
COUT
>
8f R
( )
(
)
if there is any question.
SENSE
Ceramic capacitors are becoming very popular for small
designsbutseveralcautionsshouldbeobserved.X7R,X5R
and Y5V are examples of a few of the ceramic materials
used as the dielectric layer, and these different dielectrics
have very different effect on the capacitance value due to
thevoltageandtemperatureconditionsapplied.Physically,
if the capacitance value changes due to applied voltage
change, there is a concomitant piezo effect which results
in radiating sound! A load that draws varying current at
an audible rate may cause an attendant varying input volt-
age on a ceramic capacitor, resulting in an audible signal.
A secondary issue relates to the energy flowing back into
a ceramic capacitor whose capacitance value is being
reducedbytheincreasingcharge.Thevoltagecanincrease
ataconsiderablyhigherratethantheconstantcurrentbeing
supplied because the capacitance value is decreasing as
thevoltageisincreasing!Nevertheless,ceramiccapacitors,
when properly selected and used, can provide the lowest
overall loss due to their extremely low ESR.
TheemergenceofverylowESRcapacitorsinsmall,surface
mount packages makes very small physical implementa-
tions possible. The ability to externally compensate the
switching regulator loop using the ITH pin allows a much
wider selection of output capacitor types. The impedance
characteristic of each capacitor type is significantly differ-
ent than an ideal capacitor and therefore requires accurate
modelingorbenchevaluationduringdesign.Manufacturers
suchasNichicon,NipponChemi-ConandSanyoshouldbe
consideredforhighperformancethrough-holecapacitors.
TheOS-CONsemiconductordielectriccapacitorsavailable
from Sanyo and the Panasonic SP surface mount types
have a good (ESR)(size) product.
OncetheESRrequirementforC
hasbeenmet,theRMS
OUT
currentratinggenerallyfarexceedstheI
require-
RIPPLE(P-P)
ment. Ceramic capacitors from AVX, Taiyo Yuden, Murata
and TDK offer high capacitance value and very low ESR,
especially applicable for low output voltage applications.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum
electrolytic and dry tantalum capacitors are both available
in surface mount configurations. New special polymer
surface mount capacitors offer very low ESR also but
have much lower capacitive density per unit volume. In
A small (0.1µF to 1µF) bypass capacitor, C , between the
IN
chip V pin and ground, placed close to the LTC3774, is
IN
also suggested. A 2.2Ω to 10Ω resistor placed between
C and V pin provides further isolation.
IN
IN
The selection of C
is driven by the required effective
OUT
series resistance (ESR). Typically once the ESR require-
3774fc
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LTC3774
APPLICATIONS INFORMATION
capacitormaybeconnectedtoitsTK/SSpinortheinternal
soft-start may be used. The controller is in the shutdown
state if its RUN pin voltage is below 1.22V and its TK/SS
pin is actively pulled to ground in this shutdown state. If
the RUN pin voltage is above 1.22V, the controller powers
up. A soft-start current of 1.25µA then starts to charge the
TK/SS soft-start capacitor. Note that soft-start or tracking
is achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
accordingtotheramprateontheTK/SSpin. Thesoft-start
or tracking range is defined to be the voltage range from
0V to 0.6V on the TK/SS pin. The total soft-start time can
be calculated as:
the case of tantalum, it is critical that the capacitors are
surge tested for use in switching power supplies. Several
excellent choices are the AVX TPS, AVX TPSV, the KEMET
T510 series of surface mount tantalums or the Panasonic
SP series of surface mount special polymer capacitors
availableincaseheightsrangingfrom2mmto4mm.Other
capacitor types include Sanyo POSCAP, Sanyo OS-CON,
Nichicon PL series and Sprague 595D series. Consult the
manufacturers for other specific recommendations.
Differential Amplifier
TheLTC3774hastrueremotevoltagesensecapability.The
sense connections should be returned from the load, back
to the differential amplifier’s inputs through a common,
tightly coupled pair of PC traces. The differential amplifier
rejects common mode signals capacitively or inductively
radiated into the feedback PC traces as well as ground
CSS
1.25µA
tSOFTSTART = 0.6 •
Regardless of the mode selected by the MODE/PLLIN pin,
the controller always starts in discontinuous mode up to
TK/SS = 0.5V. Between TK/SS = 0.5V and 0.565V, it will
operate in forced continuous mode and revert to the
selected mode once TK/SS > 0.565V. The output ripple
is minimized during the 65mV forced continuous mode
window, ensuring a clean PGOOD signal. When the chan-
nel is configured to track another supply, the feedback
voltage of the other supply is duplicated by a resistor
divider and applied to the TK/SS pin. Therefore, the volt-
age ramp rate on this pin is determined by the ramp rate
of the other supply’s voltage. It is only possible to track
another supply that is slower than the internal soft-start
ramp. Note that the small soft-start capacitor charging
current is always flowing, producing a small offset error.
To minimize this error, select the tracking resistive divider
value to be small enough to make this error negligible.
In order to track down another channel or supply after
loop disturbances. The LTC3774 diffamp has high input
+
impedance on V
pin. The output of the diffamp con-
OSNS
nectstotheinvertinginputoftheerroramplifierinternally.
Setting Output Voltage
The LTC3774 output voltage is set by an external feed-
back resistive divider carefully placed across the output,
as shown in Figure 2. The regulated output voltage is
determined by:
⎛
⎞
⎟
⎠
RD1
RD2
VOUT = 0.6V • 1+
⎜
⎝
To improve the frequency response, a feedforward ca-
pacitor, C , may be used. Great care should be taken to
F1
+
route the V
line away from noise sources, such as
OSNS
the inductor or the SW line.
the soft-start phase expires, the LTC3774 is forced into
To minimize the effect of the voltage drop caused by high
current flowing through board conductance; connect
+
continuous mode of operation as soon as V
is below
OSNS
the power good lower threshold regardless of the setting
on the MODE/PLLIN pin. However, the LTC3774 should
always be set in forced continuous mode tracking down
when there is no load. After TK/SS drops below 0.1V, the
controller operates in discontinuous mode.
V
– and V
+ sense lines close to the ground and
OSNS
OSNS
the load output respectively.
External Soft-Start and Tracking
The LTC3774 has the ability to either soft-start by itself
or track the output of another channel or external supply.
When the controller is configured to soft-start by itself, a
The LTC3774 allows the user to program how its output
ramps up and down by means of the TK/SS pin. Through
thesepins, theoutputcanbesetuptoeithercoincidentally
3774fc
24
For more information www.linear.com/LTC3774
LTC3774
APPLICATIONS INFORMATION
or ratiometrically track another supply’s output, as shown
tors, the LTC3774 can achieve different modes of tracking
including the two in Figure 9.
in Figure 9. In the following discussions, V
the LTC3774’s channel 2 as a slave and V
refers to
refers to
OUT2
OUT1
So which mode should be programmed? While either
mode in Figure 9 satisfies most practical applications,
some trade-offs exist. The ratiometric mode saves a pair
of resistors, but the coincident mode offers better output
regulation. Under ratiometric tracking, when the master
controller’soutputexperiencesdynamicexcursion(under
load transient, for example), the slave controller output
will be affected as well. For better output regulation, use
the coincident tracking mode instead of ratiometric.
channel 1 as a master. To implement the coincident track-
ing in Figure 9a, connect an additional resistive divider to
V
and connect its mid-point to the TK/SS pin of the
OUT1
slave controller. The ratio of this divider should be the
same as that of the slave controller’s feedback divider
shown in Figure 10a. In this tracking mode, V
be set higher than V
tracking in Figure 9b, the ratio of the V
must
OUT1
. To implement the ratiometric
OUT2
divider should
OUT2
be exactly the same as the master controller’s feedback
divider shown in Figure 10b . By selecting different resis-
V
OUT1
V
OUT1
V
OUT2
V
OUT2
TIME
3774 F09
TIME
(9a) Coincident Tracking
(9b) Ratiometric Tracking
Figure 9. Two Different Modes of Output Voltage Tracking
V
OUT1
V
OUT1
V
OUT2
V
OUT2
R3
R4
R1
R2
R3
R4
R1
R3
R4
TO
TK/SS2
PIN
TO
V
TO
TK/SS2
PIN
TO
V
TO
+
TO
+
+
+
V
V
OSNS1
OSNS1
OSNS2
OSNS2
PIN
PIN
PIN
PIN
R2
3774 F10
(10a) Coincident Tracking Setup
(10b) Ratiometric Tracking Setup
Figure 10. Setup and Coincident and Ratiometric Tracking
3774fc
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LTC3774
APPLICATIONS INFORMATION
INTV (LDO)
on-timet
oftheLTC3774(≈90nswithpowerstage),
CC
ON(MIN)
the input voltage and inductor value:
The LTC3774 features a true PMOS LDO that supplies
power to INTV from the V supply. INTV powers
V
L
CC
IN
CC
IN
∆IL(SC) = tON(MIN)
•
the LTC3774’s internal circuitry. The LDO regulates the
voltage at the INTV pin to 5.5V when V is greater than
CC
IN
The resulting short-circuit current is:
6V. The LDO can supply a peak current of 20mA and must
be bypassed to ground with a minimum of 4.7µF ceramic
capacitororlowESRelectrolyticcapacitor.Nomatterwhat
type of bulk capacitor is used, an additional 0.1µF ceramic
⎛
⎜
⎝
⎞
⎟
⎠
1/ 3V
SENSE(MAX) − ∆IL(SC)
RSENSE
1
2
ISC
=
capacitor placed directly adjacent to the INTV and GND
CC
After a short, or while starting, make sure that the load
current takes the folded-back current limit into account.
pins is highly recommended.
For applications where the main input power is 5V, tie
the V and INTV pins together and tie the combined
Phase-Locked Loop and Frequency Synchronization
IN
CC
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
The LTC3774 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phasedetector. Thisallowstheturn-onofthetopMOSFET
to be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
in Figure 11 to minimize the voltage drop caused by the
gate charge current. This will override the INTV linear
CC
regulator and will prevent INTV from dropping too low
CC
due to the dropout voltage.
LTC3774
V
R
IN
VIN
1Ω
INTV
5V
CC
+
C
INTVCC
C
IN
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. There is a precision 20µA current flowing
out of the FREQ pin. This allows the user to use a single
resistor to GND to set the switching frequency when no
external clock is applied to the MODE/PLLIN pin. The
internal switch between the FREQ pin and the integrated
PLL filter network is on, allowing the filter network to be
pre-charged at the same voltage as of the FREQ pin. The
relationship between the voltage on the FREQ pin and
operating frequency is shown in Figure 12 and specified
in the Electrical Characteristics table. If an external clock
is detected on the MODE/PLLIN pin, the internal switch
mentionedaboveturnsoffandisolatestheinfluenceofthe
FREQpin.NotethattheLTC3774canonlybesynchronized
to an external clock whose frequency is within range of
the LTC3774’s internal VCO. A simplified block diagram
is shown in Figure 13.
4.7µF
3774 F11
Figure 11. Setup for a 5V Input
Fault Conditions: Current Limit and Current Foldback
The LTC3774 includes current foldback to help limit
load current when the output is shorted to ground. If the
output falls below 50% of its nominal output level, then
the maximum sense voltage is progressively lowered
from its maximum programmed value to one-third of the
maximum value. Foldback current limiting is not disabled
duringsoft-startortrackingup. Undershort-circuitcondi-
tions with very low duty cycles, the LTC3774 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short circuit ripple current is determined by the minimum
3774fc
26
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LTC3774
APPLICATIONS INFORMATION
1300
1100
900
700
500
300
100
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor C holds the voltage.
LP
Typically,theexternalclock(ontheMODE/PLLINpin)input
high threshold is 1.6V, while the input low threshold is 1V.
Using the CLKOUT and PHSMD Pins in Multiphase
Applications
The LTC3774 features CLKOUT and PHSMD pins that
allow multiple LTC3774 ICs to be daisy chained together
in multiphase applications. The clock output signal on the
CLKOUT pin can be used to synchronize additional ICs in
a 3-, 4-, 6-, 8- or 12-phase power supply solution feeding
a single high current output, or even several outputs from
the same input supply.
1.2
(V)
1.6
1.8
0.4 0.6
0.8 1.0
1.4
V
FREQ
3774 F12
Figure 12. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
2.4V 5.5V
The PHSMD pin is used to adjust the phase relationship
between channel 1 and channel 2, as well as the phase
relationship between channel 1 and CLKOUT. The phases
arecalculatedrelativetozerodegrees,definedastherising
edgeofPWM1.RefertotheApplicationsInformationsection
for more details on how to create multiphase applications.
R
SET
20µA
FREQ
DIGITAL
PHASE/
FREQUENCY
DETECTOR
MODE/PLLIN
SYNC
EXTERNAL
OSCILLATOR
VCO
Minimum On-Time Considerations
Minimum on-time, t
, is the smallest time duration
ON(MIN)
3774 F13
thattheLTC3774iscapableofturningonthetopMOSFET.
It is determined by internal timing delays, power stage
timing delays and the gate charge required to turn on the
top MOSFET. Low duty cycle applications may approach
this minimum on-time limit and care should be taken to
ensure that:
Figure 13. Phase-Locked Loop Block Diagram
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f , then current is sourced
OSC
continuously from the phase detector output, pulling up
VOUT
tON(MIN)
<
the filter network. When the external clock frequency is
V f
IN ( )
less than f , current is sunk continuously, pulling down
OSC
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the voltage ripple and current ripple will increase.
3774fc
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LTC3774
APPLICATIONS INFORMATION
2
The minimum on-time for the LTC3774 is approximately
90ns, with good PCB layout, minimum 30% inductor
current ripple and at least 2mV ripple on the current
sense signal. The minimum on-time can be affected by
PCB switching noise in the voltage and current loop.
As the peak sense voltage decreases the minimum on-
time gradually increases This is of particular concern in
forced continuous applications with low ripple current at
light loads. If the duty cycle drops below the minimum
on-timelimitinthissituation, asignificantamountofcycle
skipping can occur with correspondingly larger current
and voltage ripple.
3. I R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor and current sense re-
sistor. In continuous mode, the average output current
flows through L and R
, but is chopped between
SENSE
the topside MOSFET and the synchronous MOSFET.
If the two MOSFETs have approximately the same
R
, then theresistance of oneMOSFETcansimply
DS(ON)
be summed with the resistances of L and R
to
SENSE
=10mΩ,
2
obtainI Rlosses.Forexample,ifeachR
R = 10mΩ, R
DS(ON)
= 5mΩ, then the total resistance is
L
SENSE
25mΩ. This results in losses ranging from 2% to 8%
as the output current increases from 3A to 15A for a 5V
output, or a 3% to 12% loss for a 3.3V output.
Efficiency Considerations
Efficiency varies as the inverse square of V
for the
OUT
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
sameexternalcomponentsandoutputpowerlevel. The
combined effects of increasingly lower output voltages
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
2
Transition Loss = (1.7) V • I
• C
• f
IN
O(MAX)
RSS
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5%
to 10% efficiency degradation in portable systems. It
is very important to include these system level losses
during the design phase. The internal battery and fuse
resistancelossescanbeminimizedbymakingsurethat
losses in LTC3774 circuits: 1) IC V current, 2) MOSFET
IN
2
driver current, 3) I R losses, 4) topside MOSFET transi-
tion losses.
1. The V current is the DC supply current given in the
IN
Electrical Characteristics table. V current typically
IN
C has adequate charge storage and very low ESR at
IN
results in a small (<0.1%) loss.
the switching frequency. A 25W supply will typically
require a minimum of 20µF to 40µF of capacitance
having a maximum of 20mΩ to 50mΩ of ESR. Other
losses including Schottky conduction losses during
dead time and inductor core losses generally account
for less than 2% total additional loss.
2. The MOSFET driver current results from switching the
gate capacitance of the power MOSFETs. Each time
a MOSFET gate is switched from low to high to low
again, a packet of charge dQ moves from the driver
supply to ground. The resulting dQ/dt is a current
out of the driver supply that is typically much larger
than the control circuit current. In continuous mode,
I
= f(Q + Q ), where Q and Q are the gate
GATECHG
T B T B
charges of the topside and bottom side MOSFETs.
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LTC3774
APPLICATIONS INFORMATION
Checking Transient Response
in output current may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
phase margin. This is why it is better to look at the I
TH
pin signal which is in the feedback loop and is the filtered
and compensated control loop response. The gain of the
load current. When a load step occurs, V
shifts by an
OUT
loop will be increased by increasing R and the bandwidth
C
amount equal to ∆I
• ESR, where ESR is the effective
LOAD
of the loop will be increased by decreasing C . If R is
C
C
series resistance of C . ∆I
also begins to charge or
OUT
LOAD
increased by the same factor that C is decreased, the
C
discharge C
generating the feedback error signal that
OUT
zero frequency will be kept the same, thereby keeping the
phase shift the same in the most critical frequency range
of the feedback loop. The output voltage settling behavior
is related to the stability of the closed-loop system and
will demonstrate the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
forces the regulator to adapt to the current change and
return V to its steady-state value. During this recovery
OUT
time V
can be monitored for excessive overshoot or
OUT
ringing, which would indicate a stability problem. The
availability of the I pin not only allows optimization of
TH
control loop behavior but also provides a DC-coupled and
AC-filtered closed-loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed-loopresponse. Assuming a predominantly second
ordersystem, phasemarginand/or dampingfactorcanbe
estimated using the percentage of overshoot seen at this
pin.Thebandwidthcanalsobeestimatedbyexaminingthe
with C , causing a rapid drop in V . No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
is greater than 1:50, the switch rise time
OUT
rise time at the pin. The I external components shown
TH
should be controlled so that the load rise time is limited
to approximately 25 • C . Thus a 10µF capacitor would
in the Typical Application circuit will provide an adequate
LOAD
starting point for most applications. The I series R -C
TH
C
C
require a 250µs rise time, limiting the charging current
to about 200mA.
filter sets the dominant pole-zero loop compensation.
The values can be modified slightly (from 0.5 to 2 times
their suggested values) to optimize transient response
once the final PC layout is done and the particular output
capacitortypeandvaluehavebeendetermined.Theoutput
capacitors need to be selected because the various types
and values determine the loop gain and phase. An output
current pulse of 20% to 80% of full-load current having a
rise time of 1µs to 10µs will produce output voltage and
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. Theseitemsarealsoillustratedgraphicallyinthelayout
diagram of Figure 14. Check the following in the PC layout:
1. The INTV decoupling capacitor should be placed
CC
I
TH
pin waveforms that will give a sense of the overall
immediately adjacent to the IC between the INTV pin
CC
loop stability without breaking the feedback loop. Placing
a power MOSFET directly across the output capacitor and
driving the gate with an appropriate signal generator is a
practicalwaytoproducearealisticloadstepcondition. The
initial output voltage step resulting from the step change
and GND plane. A 1µF ceramic capacitor of the X7R or
X5R type is small enough to fit very close to the IC. An
additional 4.7µF to 10µF of ceramic, tantalum or other
very low ESR capacitance is recommended in order to
keep the internal IC supply quiet.
3774fc
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LTC3774
APPLICATIONS INFORMATION
L1
V
OUT
V
IN
SW2
R
SENSE
R
IN
+
+
R
L
D1
C
OUT
C
IN
SW1
3774 F14
BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH
Figure 14. Branch Current Waveforms
2. Placethefeedbackdividerbetweenthe+and–terminals
7. The 47pF to 330pF ceramic capacitor between the I
TH
+
–
of COUT. Route V
and V
with minimum PC
pin and signal ground should be placed as close as
possible to the IC. Figure 14 illustrates all branch cur-
rents in a switching regulator. It becomes very clear
afterstudyingthecurrentwaveformswhyitiscriticalto
keepthehighswitchingcurrentpathstoasmallphysical
size. High electric and magnetic fields will radiate from
these loops just as radio stations transmit signals. The
output capacitor ground should return to the negative
terminal of the input capacitor and not share a com-
mon ground path with any switched current paths. The
left half of the circuit gives rise to the noise generated
by a switching regulator. The ground terminations of
the synchronous MOSFET and Schottky diode should
return to the bottom plate(s) of the input capacitor(s)
with a short isolated PC trace since very high switched
currents are present. External OPTI-LOOP® compensa-
tion allows overcompensation for PC layouts which are
not optimized but this is not the recommended design
procedure.
OSNS
OSNS
trace spacing from the IC to the feedback divider.
+
+
–
3. Are the SNSA , SNSD and SNS printed circuit traces
routed together with minimum PC trace spacing? The
+
+
–
filter capacitors between SNSA , SNSD and SNS
should be as close as possible to the pins of the IC.
4. Do the (+) plates of C connect to the drain of the
IN
topside MOSFET as closely as possible? This capacitor
provides the pulsed current to the MOSFET.
5. Keep the switching nodes away from sensitive small-
+
+
–
+
–
signal nodes (SNSD , SNSA , SNS , V
, V
).
OSNS
OSNS
IdeallythePWMandswitchnodesprintedcircuittraces
should be routed away and separated from the IC and
especially the quiet side of the IC. Separate the high dv/
dttracesfromsensitivesmall-signalnodeswithground
traces or ground planes.
6. Use a low impedance source such as a logic gate to
drive the MODE/PLLIN pin and keep the lead as short
as possible.
3774fc
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LTC3774
APPLICATIONS INFORMATION
8. Are the signal and power grounds kept separate? The
The inductance value is based on a 35% maximum ripple
current assumption (10.5A per phase). The highest value
of ripple current occurs at the maximum input voltage:
IC ground pin and the ground return of C
must
INTVCC
(–) terminals. The V
+
return to the combined C
OUT
OSNS
and I traces should be as short as possible. The path
TH
⎛
⎞
⎟
⎟
⎠
VOUT
VOUT
formed by the top N-channel MOSFET, Schottky diode
⎜
⎜
⎝
L =
1−
f • ∆IL(MAX)
V
IN(MAX)
and the C capacitor should have short leads and PC
IN
tracelengths.Theoutputcapacitor(–)terminalsshould
be connected as close as possible to the (–) terminals
of the input capacitor by placing the capacitors next to
each other and away from the Schottky loop described
above.
This design will require 0.33µH. The Würth 744301033,
0.32µH inductor is chosen. At the nominal input voltage
(12V), the ripple current will be:
⎛
⎞
VOUT
f • L
VOUT
⎜
⎟
∆IL(NOM)
=
1−
9. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
⎜
⎟
V
IN(NOM)
⎝
⎠
It will have 10A (33%) ripple. The peak inductor current
will be the maximum DC value plus one-half the ripple
current, or 35A per phase.
capacitors with tie-ins for the bottom of the INTV
CC
decouplingcapacitor,thebottomofthevoltagefeedback
resistive divider and the GND pin of the IC.
The minimum on-time occurs at the maximum V , and
IN
Design Example
should not be less than 100ns (includes margin):
As a design example of the front page circuit for a two-
VOUT
1.5V
tON(MIN)
=
=
= 187ns
channelhighcurrentregulator,assumeV =12V(nominal),
IN
V
IN(MAX)f 20V(400kHz)
V
IN
= 20V(maximum), V
= 1.5V, I
= 60A, and
OUT
MAX
f = 400kHz (see front page schematic).
DCRsensingisusedinthiscircuit. IfC1andC2arechosen
to be 220nF, based on the chosen 0.33µH inductor with
0.32mΩ DCR, R1 and R2 can be calculated as:
The regulated output voltage is determined by:
⎛
⎞
⎟
⎠
RB
RA
VOUT = 0.6V • 1+
⎜
L
R1=
R2 =
= 4.69k
⎝
DCR •C1
L
Using a 10k 1% resistor from the V node to ground, the
FB
= 937Ω
top feedback resistor is 15k.
DCR •C2 • 5
The frequency is set by biasing the FREQ pin to 0.75V
(see Figure 12).
Choose R1 = 4.64k and R2 = 931Ω.
3774fc
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LTC3774
APPLICATIONS INFORMATION
The maximum DCR of the inductor is 0.34mΩ. The
For a 0.32mΩ DCR, a short-circuit to ground will result
in a folded back current of:
V
is calculated as:
SENSE(MAX)
V
= I
• DCR = 12mV
MAX
⎛
⎞
⎟
⎠
1/ 3 15mV
0.00032Ω
SENSE(MAX)
PEAK
1 90ns(20V)
(
)
ISC =
–
= 12.9A / phase
⎜
2
0.33µH
The current limit is chosen to be 15mV. If temperature
variation is considered, please refer to Inductor DCR
SensingTemperatureCompensationwithNTCThermistor.
⎝
An Infineon BSC010NE2LS, R
for the bottom FET. The resulting power loss is:
= 1.1mΩ, is chosen
DS(ON)
The power dissipation on the topside MOSFET can be
easily estimated. Choosing an Infineon BSC050NE2LS
20V – 1.5V
2
P
=
30A •
(
)
SYNC
MOSFET results in: R
= 7.1mΩ (max), V
=
20V
DS(ON)
MILLER
2.8V, C
≅ 108pF. At maximum input voltage with
MILLER
⎡
⎤
1+ 0.005 • 75°C – 25°C • 0.0011Ω
(
)
(
)
⎣
⎦
T (estimated) = 75°C:
J
P
= 1.14W/phase
1.5V
2
SYNC
PMAIN
=
30A 1+(0.005)(75°C – 25°C) •
(
)
[
]
20V
0.0071Ω + 20V
C is chosen for an equivalent RMS current rating of at
IN
⎛
⎞
⎟
⎠
30A
2
least 13.7A. C
is chosen with an equivalent ESR of
2
OUT
2Ω 108pF •
)(
(
) (
)
⎜
(
)
4.5mΩ for low output ripple. The output ripple in continu-
ous mode will be highest at the maximum input voltage.
The output voltage ripple due to ESR is approximately:
⎝
⎡
⎤
1
1
+
400kHz
(
⎥
)
⎢
⎣
⎦
5.5V – 2.8V 2.8V
= 599mW+377mW
= 976mW / phase
V
= R (∆I ) = 0.0045Ω • 10A = 45mV
ESR L P-P
ORIPPLE
Further reductions in output voltage ripple can be made
by placing a 100µF ceramic capacitor across C
.
OUT
3774fc
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For more information www.linear.com/LTC3774
LTC3774
TYPICAL APPLICATIONS
D I S B
D I S B
R V D
V
R V D
V
S M O D
P G N D
C G N D
S M O D
P G N D
C G N D
C I N
V
C I N
V
G N D
R U N 1
W P M 1
W P M E N 1
G N D
R U N 2
W P M 2
W P M E N 2
H I Z B 2
T K / S S 2
H I Z B 1
T K / S S 1
O S N S 1
V
O S N S 2
V
+
–
+
–
O S N S 1
O S N S 2
V
V
I T H 1
I T E M P 1
I T H 2
I T E M P 2
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For more information www.linear.com/LTC3774
LTC3774
TYPICAL APPLICATIONS
D I S B
D I S B
R V D
V
R V D
V
S M O D
P G N D
C G N D
S M O D
P G N D
C G N D
C I N
V
C I N
V
G N D
R U N 1
W P M 1
W P M E N 1
G N D
R U N 2
W P M 2
W P M E N 2
H I Z B 2
T K / S S 2
H I Z B 1
T K / S S 1
O S N S 1
V
O S N S 2
V
+
–
+
–
O S N S 1
O S N S 2
V
V
I T H 1
I T E M P 1
I T H 2
I T E M P 2
3774fc
34
For more information www.linear.com/LTC3774
LTC3774
TYPICAL APPLICATIONS
G N D
R U N 1
W P M 1
W P M E N 1
G N D
R U N 2
W P M 2
W P M E N 2
H I Z B 2
T K / S S 2
H I Z B 1
T K / S S 1
O S N S 1
V
O S N S 2
V
+
–
+
–
O S N S 1
O S N S 2
V
V
I T H 1
I T E M P 1
I T H 2
I T E M P 2
3774fc
35
For more information www.linear.com/LTC3774
LTC3774
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3ꢀꢀ4#packaging for the most recent package drawings.
UHE Package
36-Lead Plastic QFN (5mm × 6mm)
(Reference LTC DWG # 05-08-1876 Rev Ø)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
PACKAGE
OUTLINE
3.60 ±0.05
3.50 REF
4.60 ±0.05
0.25 ±0.05
0.50 BSC
4.50 REF
5.10 ±0.05
6.50 ±0.05
PIN 1 NOTCH
R = 0.30 TYP
OR 0.35 × 45°
CHAMFER
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.50 REF
R = 0.10
5.00 ±0.10
0.00 – 0.05
0.200 REF
TYP
29
36
0.40 ±0.10
PIN 1
28
1
TOP MARK
(SEE NOTE 6)
6.00 ±0.10
4.50 REF
4.60 ±0.10
3.60
±0.10
20
10
(UHE36) QFN 0410 REV Ø
19
0.25 ±0.05
0.50 BSC
11
R = 0.125
TYP
0.75 ±0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3774fc
36
For more information www.linear.com/LTC3774
LTC3774
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
01/14 Replaced Undervoltage Lockout curve
6
17, 18
3, 4, 6, 9
8
Revised Inductor DCR Sensing Temp Comp and NTC Compensated DCR Sensing sections
07/15 Minor typographical changes
B
C
Changed INTV pin description
CC
04/17 Claification on selecting DrMOS Devices
21
3774fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
37
LTC3774
TYPICAL APPLICATION
Dual Phase 1.2V/30A LTC3ꢀꢀ4 Converter with Hot Swap Circuits On the Input of Each Phase
1N4448HWT
V
IN1
5V BIAS
1Ω
1N4448HWT
37.4k
10k
V
IN2
2.2µF
2.2µF
1µF
PWM
BOOT
0.22µF
FDMF6820
DrMOS
L4
0.33µH
V
PHASE
IN
22µF
25V
2×
D17
CMHZ4690
V
SWH
C
OUTCER1
1N4448HWT
1N4448HWT
30.1k
100µF
6.3V
2×
2.4M
CMHZ4690
HIZB1
HIZB1 PWM1 PWMEN1
2.2k
4.64k
RUN1, 2
1µF
10k
+
–
+
V
SNSD1
SNS1
0.22µF
0.22µF
IN
LTC3774
INTV
CC
V
IN1
4.7µF
931Ω
931Ω
FREQ
SNSA1
0.007Ω FDMS86500DC
PHSMD
TK/SS1,2
PGOOD1
PGOOD2
V
OUT
1.2V/30A
5V
BIAS
0.1µF
+
I
SNSA2
TEMP1,2
0.22µF
0.22µF
C
OUTCER1
330µF
+
–
–
+
V
V
SNS2
OSNS1,2
OSNS1,2
TH1,2
V
IN
10V TO 14V
10k
10k
37.4k
+
ON1
FTMR1
FAULT1
FAULT2
FTMR2
SNSD2
2.5V
6×
4.64k
+
150µF
25V
2×
10k
CLS
GND
ON2
22µF
25V
I
I
CLKOUT
LTC4226
64.9k
10k
MODE/PLLIN
LIM1,2
3.01k
3.3nF
HIZB2 PWM2 PWMEN2 GND
100pF
100pF
330pF
5V BIAS
1Ω
V
IN2
0.007Ω
FDMS86500DC
2.2µF
2.2µF
HIZB2
PWM
BOOT
0.22µF
FDMF6820
DrMOS
L3
0.33µH
V
PHASE
IN
22µF
25V
2×
L1, L2: WÜRTH 744301033
COUTCER1,2: MURATA GRM31CR60J107ME39L
COUTBLK: SANYO 2R5TPE330M9
V
SWH
C
OUTCER2
100µF
6.3V
2×
3774 TA05
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
4.5V ≤ V ≤ 15V, 0.6V ≤ V
LTM4630
Dual 18A or Single 36A DC/DC μModule Regulator
≤ 1.8V
OUT
IN
LTM4630-1A
LTM4630-1B
1.5% Max V
Error Over Line, Load and Temp
OUT
–1A Version: 0.8% Max V
Error Over Line, Load and Temp
OUT
LTC3887
LTC3875
LTC3861
LTC3855
LTC3856
LTC3838
Dual Output Multiphase Step-Down DC/DC Controller with
Digital Power System Management and 0.5% Accuracy
4.5V≤ V ≤ 24V, 0.5V ≤ V
≤ 5.5V, Analog Control Loop,
IN
OUT
2
70ms Start-Up, I C/PMBus Interface with EEPROM and 16-bit ADC
Dual, Multiphase Synchronous Controller with
Sub Milliohm DCR Sensing and Temperature Compensation
4.75V≤ V ≤ 38V, 0.6V ≤ V
≤ 3.5V/5V
IN
OUT
Excellent Current Share when Paralleled
Dual, Multiphase, Synchronous Step-Down DC/DC Controller
with Diff Amp and Tri-State Output Drive
Operates with Power Blocks, DrMOS or
External MOSFETs 3V≤ V ≤ 24V
IN
Dual Output, 2-phase, Synchronous Step-Down DC/DC
Controller with Diff Amp and DCR Temperature Compensation PLL Fixed Frequency 250kHz to 770kHz,
4.5V≤ V ≤ 38V, 0.8V ≤ V
≤ 12V
IN
OUT
Single Output 2-Phase Synchronous Step-Down DC/DC
Controller with Diff Amp and DCR Temperature Compensation PLL Fixed 250kHz to 770kHz Frequency
4.5V≤ V ≤ 38V, 0.8V≤ V
≤ 5V
IN
OUT
Dual Output, 2-phase, Synchronous Step-Down DC/DC
Controller with Diff Amp and Controlled On-Time
4.5V≤ V ≤ 38V, 0.8V ≤ V
≤ 5.5V
IN
OUT
PLL, Up to 2MHz Switching Frequency
LTC3869/
Dual Output, 2-Phase Synchronous Step-Down DC/DC
Controller, with Accurate Current Share
4V≤ V ≤ 38V, V up to 12.5V
IN
OUT3
LTC3869-2
PLL Fixed 250kHz to 750kHz Frequency
V up to 38V, 4V ≤ V ≤ 6.5V Adaptive
IN
LTC4449
High Speed Synchronous N-Channel MOSFET Driver
CC
Shoot-Through Protection, 2mm x 3mm DFN-8
3774fc
LT 0417 REV C • PRINTED IN USA
www.linear.com/LTC3774
38
LINEAR TECHNOLOGY CORPORATION 2013
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