LTC3775EUDTRPBF [Linear]
High Frequency Synchronous Step-Down Voltage Mode DC/DC Controller; 高频率同步降压型电压模式DC / DC控制器
| 型号： | LTC3775EUDTRPBF |
| 厂家： | 
Linear |
| 描述： | High Frequency Synchronous Step-Down Voltage Mode DC/DC Controller |
| 文件： | 总32页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3775
High Frequency
Synchronous Step-Down
Voltage Mode DC/DC
Controller
FEATURES
DESCRIPTION
TheLTC®3775isahighefficiencysynchronousstep-down
switching DC/DC controller that drives an all N-channel
power MOSFET stage from a 4.5V to 38V input supply
voltage. A patented line feedforward compensation circuit
and a high bandwidth error amplifier provide very fast line
and load transient response.
n
Wide V Range: 4.5V to 38V
IN
n
Line Feedforward Compensation
n
Low Minimum On-Time: t
< 30ns
ON(MIN)
n
Powerful Onboard MOSFET Drivers
Leading Edge Modulation Voltage Mode Control
0.75ꢀ, 0.ꢁV Reference Voltage Accuracy Over
Temperature
n
n
High step-down ratios are made possible by a low 30ns
minimum on-time, allowing extremely low duty cycles
n
n
n
n
n
n
V
Range: 0.ꢁV to 0.8V
OUT
IN
Programmable, Cycle-by-Cycle Peak Current Limit
Sense Resistor or R Current Sensing
Programmable Soft-Start
Synchronizable Fixed Frequency from 250kHz to 1MHz
Selectable Pulse-Skipping or Forced Continuous
Modes of Operation
MOSFET R
current sensing maximizes efficiency.
DS(ON)
DS(ON)
Alternatively, a sense resistor can be used for higher cur-
rentlimitaccuracy. Continuousmonitoringofthevoltages
acrossthetopandbottomMOSFETsallowscycle-by-cycle
control of the inductor current, configurable by external
resistors.
n
n
Low Shutdown Current: 14μA Typical
Thermally Enhanced 3mm × 3mm QFN Package
The soft-start function controls the duty cycle during
start-up, providing a smooth output voltage ramp up. The
operating frequency is user programmable from 250kHz
to 1MHz and can be synchronized to an external clock.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents, including
5408150, 5481178, 5705919, ꢁ580258, 5847554, 50557ꢁ7.
APPLICATIONS
n
Automotive Systems
n
Telecom and Industrial Power Supplies
n
Point of Load Applications
TYPICAL APPLICATION
V
Efficiency and Power Loss vs Load Current
IN
5V TO 28V
330μF
35V
5
4
3
2
1
0
100
90
80
70
ꢁ0
50
40
30
20
10
0
V
V
= 12V
IN
OUT
3.1ꢁk
= 1.2V
V
IN
I
I
TG
LIMT
LIMB
CONTINUOUS MODE
SW FREQ = 500kHz
57.ꢁk
SENSE
4.7μF
39.2k
0.1μF
LTC3775
INTV
SS
BOOST
CC
0.3ꢁμH
V
EFFICIENCY
0.01μF
OUT
SW
1.2V
15A
470μF
2.5V
s2
BG
PGND
FREQ
FB
330pF
4.7k
POWER LOSS
10
MODE/SYNC
COMP RUN/SHDN
3.9nF
SGND
10k
10k
0.01
0.1
1
100
LOAD CURRENT (A)
3775 TA01a
3775 TA01b
3775f
1
LTC3775
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
Supply Voltage
TOP VIEW
V ......................................................... –0.3V to 40V
IN
BOOST................................................... –0.3V to 4ꢁV
BOOST-SW............................................... –0.3V to ꢁV
SW............................................................ –5V to 40V
1ꢁ 15 14 13
I
1
2
3
4
12 SW
LIMT
I
.............................................................–0.3V to V
LIMT
IN
I
11
10
9
V
IN
LIMB
FB
17
PGND
SENSE.............................................................–5V to V
IN
SENSE
INTV ......................................................... –0.3V to ꢁV
CC
COMP
INTV
CC
RUN/SHDN................................................... –0.3V to ꢁV
5
ꢁ
7
8
FB, MODE/SYNC ................................... –0.3V to INTV
CC
CC
FREQ, I
, SS..................................... –0.3V to INTV
LIMB
UD PACKAGE
1ꢁ-LEAD (3mm s 3mm) PLASTIC QFN
INTV RMS Currents............................................50mA
CC
T
= 125°C, θ = ꢁ8°C/W, θ = 4.2°C/W (NOTE 3)
JA JC
EXPOSED PAD (PIN 17) IS PGND, MUST BE SOLDERED TO PCB
JMAX
Operating Junction Temperature Range
(Note 2).................................................. –40°C to 125°C
Storage Temperature Range................... –ꢁ5°C to 150°C
ORDER INFORMATION
LEAD FREE FINISH
LTC3775EUD#PBF
LTC3775IUD#PBF
TAPE AND REEL
PART MARKING*
LDJK
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3775EUD#TRPBF
LTC3775IUD#TRPBF
–40°C to 85°C
–40°C to 125°C
1ꢁ-Lead (3mm × 3mm) Plastic QFN
1ꢁ-Lead (3mm × 3mm) Plastic QFN
LDJK
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3775f
2
LTC3775
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN = 5V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply
l
V
IN
V
IN
Supply Voltage
4.5
38
V
I
Input DC Supply Current
V
V
= 0.7V (Note 5)
RUN
3.5
14
mA
μA
VIN
FB
= 0V
RUN/SHDN Pin
V
V
V
RUN/SHDN Pin Enable Threshold
1.19
1.22
0.74
140
1.25
V
V
RUN
RUN/SHDN Pin Shutdown Threshold
RUN/SHDN Pin Shutdown Threshold Hysteresis
RUN/SHDN Pin Source Current
V
Rising
SHDN
RUN/SHDN
mV
SHDN(HYST)
RUN
I
V
V
= 0V
= 1.5V
–1
–4
μA
μA
RUN/SHDN
RUN/SHDN
Error Amplifier
V
FB
Feedback Pin Voltage
0.597
0.5955
0.ꢁ00
0.ꢁ03
0.ꢁ045
V
V
l
Feedback Voltage Line Regulation
Output Voltage Load Regulation
FB Pin Input Current
4.5V < V < 38V
0.01
0.01
ꢀ/V
ꢀ
ΔV
ΔV
IN
FB
1V < V
< 2V (Note ꢁ)
0.1
50
COMP
OUT
I
I
V
= 0.ꢁV
FB
–50
nA
FB
COMP Pin Output Current
Sourcing
Sinking
–0.5
1
–1
25
mA
mA
COMP
f
Error Amplifier Unity-Gain Crossover Frequency
(Note ꢁ)
MHz
0dB
Soft-Start
I
SS
SS Pin Source Current
V
= 0V
SS
–1
μA
R
SS
SS Pin Pull-Down Resistance in Current Limit
1.3
kΩ
Current Limit
l
l
I
I
I
I
I
Source Current
Sink Current
–9
90
–10
100
–11
110
1
μA
μA
LIMB
LIMT
LIMB
LIMT
SENSE Pin Input Current
μA
SENSE
l
l
V
V
Topside Current Limit Threshold (V -SENSE)
V
V
= 0.1V
= 0.5V
90
80
100
100
110
120
mV
mV
ILIMT(MAX)
ILIMB(MAX)
IN
ILIMT
Bottom Side Current Limit Threshold (PGND-SW)
ILIMB
INTV Low Dropout Voltage Regulator
CC
INTV
LDO Regulator Output Voltage
4.9
–1
5.2
5.5
4.2
V
ꢀ/V
ꢀ
CC
INTV Line Regulation
7.5V < V < 38V
0.01
–0.1
0.35
ΔV
CC
IN
INTVCC(LINE)
INTVCC(LOAD)
DROPOUT
INTV Load Regulation
ΔV
ΔI
= 0mA to 20mA
INTVCC
CC
V
V
INTV Regulator Dropout Voltage (V – V
)
I = 20mA
INTVCC
V
CC
IN
INTVCC
INTV UVLO Voltage
INTV Rising
3.0
3.ꢁ
0.5
V
V
UVLO
CC
CC
Hysteresis
3775f
3
LTC3775
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN = 5V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator
l
l
l
f
f
f
f
t
t
Oscillator Frequency
R
= 39.2k
425
500
575
kHz
kHz
kHz
ꢀ
OSC
FREQ
Maximum Oscillator Frequency
Minimum Oscillator Frequency
External Sync Frequency Range
TG Minimum On-Time
1000
HIGH
250
20
LOW
With Reference to Free Running
–20
90
SYNC
(Notes ꢁ, 8) V
= 0V
MODE/SYNC
30
ns
ON(MIN)
OFF(MIN)
TG Minimum Off-Time
(Note ꢁ)
300
ns
l
DC
Maximum TG Duty Cycle
MODE/SYNC Threshold
f
= 500kHz
OSC
ꢀ
MAX
V
V
MODE/SYNC Rising
1.2
430
50
V
MODE
MODE/SYNC Hysteresis
mV
kΩ
MODE(HYST)
R
MODE/SYNC Input Resistance to SGND
MODE/SYNC
Driver
BG R
Bottom Gate (BG) Pull-Up On-Resistance
Top Gate (TG) Pull-Up On-Resistance
Bottom Gate (BG) Pull-Down On-Resistance
Top Gate (TG) Pull-Down On-Resistance
2.5
2.5
1.0
1.5
15
Ω
Ω
Ω
Ω
ns
UP
UP
TG R
BG R
TG R
DOWN
DOWN
BG, TG t
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
C = 3300pF (Note 7)
L
2D
1D
TG, BG t
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
C = 3300pF (Note 7)
L
15
ns
Note 4: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 5: Supply current in normal operation is dominated by the current
needed to charge and discharge the external MOSFET gates. This current
will vary with supply voltage and the external MOSFETs used.
Note 6: Guaranteed by design, not subject to test.
Note 7: Rise and fall times are measured using 10ꢀ and 90ꢀ levels. Delay
and nonoverlap times are measured using 50ꢀ levels.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3775E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
junction temperature range are assured by design, characterization and
correlation with statisitical process controls. The LTC3775I is guaranteed
over the full –40°C to 125°C operating junction temperature range. The
junction temperature, T , is calculated from the ambient temperature, T ,
J
A
Note 8: The LTC3775 leading edge modulation architecture does not have
a minimum TG pulse width requirement. The TG minimum pulse width is
limited by the SW node rise and fall times.
and power dissipation, P , according to:
D
T = T + (P • θ )
JA
J
A
D
Note 3: Failure to solder the exposed pad of the UD package to the PC
board will result in a thermal resistance much higher than ꢁ8°C/W.
3775f
4
LTC3775
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
Efficiency vs Input Voltage
Load Regulation
100
90
80
70
ꢁ0
50
40
30
20
10
0
100
90
80
70
ꢁ0
50
40
1.20ꢁ
1.204
1.202
1.200
1.198
1.19ꢁ
1.194
V
IN
= 12V
V
V
= 12V
IN
OUT
SW FREQ = 500kHz
FIRST PAGE CIRCUIT
= 1.2V
SW FREQ = 500kHz
FIRST PAGE CIRCUIT
15A LOAD
PULSE-SKIPPING
MODE
1A LOAD
CONTINUOUS
MODE
V
= 1.2V
OUT
CONTINUOUS MODE
SW FREQ = 500kHz
FIRST PAGE CIRCUIT
10 12
LOAD CURRENT (A)
4
12
1ꢁ
20
24
28
0
2
4
ꢁ
8
14 1ꢁ
8
0.01
0.1
1
10
100
INPUT VOLTAGE (V)
LOAD CURRENT (A)
3775 G01
3775 G02
3775 G03
Load Step in Forced Continuous
Mode
Line Regulation
FB Voltage vs Temperature
1.20ꢁ
1.204
1.202
1.200
1.198
1.19ꢁ
1.194
ꢁ03
ꢁ02
ꢁ01
ꢁ00
V
= 1.2V
OUT
LOAD = 1A
FIRST PAGE CIRCUIT
V
OUT(AC)
100mV/DIV
I
L
10A/DIV
599
598
597
I
LOAD
10A/DIV
3775 G0ꢁ
V
V
= 12V
50μs/DIV
4
12
1ꢁ
20
24
28
–50
25
50
75
100 125
8
–25
0
IN
OUT
= 1.2V
INPUT VOLTAGE (V)
TEMPERATURE (°C)
LOAD STEP = 0A TO 10A TO 0A
MODE/SYNC = 0V
SW FREQ = 500kHz
3775 G02
3775 G05
FIRST PAGE CIRCUIT
Positive Load Step in Forced
Continuous Mode
Negative Load Step in Forced
Continuous Mode
Load Step in Pulse-Skipping Mode
V
V
SW
SW
20V/DIV
20V/DIV
V
OUT(AC)
100mV/DIV
V
V
OUT(AC)
OUT(AC)
100mV/DIV
100mV/DIV
I
I
L
L
I
L
10A/DIV
10A/DIV
10A/DIV
I
I
LOAD
LOAD
I
LOAD
10A/DIV
10A/DIV
10A/DIV
3775 G08
3775 G09
3775 G07
V
V
= 12V
5μs/DIV
V
V
= 12V
50μs/DIV
V
V
= 12V
5μs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.2V
= 1.2V
= 1.2V
LOAD STEP = 10A TO 0A
MODE/SYNC = 0V
SW FREQ = 500kHz
FIRST PAGE CIRCUIT
LOAD STEP = 1A TO 11A TO 1A
LOAD STEP = 0A TO 10A
MODE/SYNC = 0V
SW FREQ = 500kHz
FIRST PAGE CIRCUIT
MODE/SYNC = INTV
SW FREQ = 500kHz
FIRST PAGE CIRCUIT
CC
3775f
5
LTC3775
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency vs
Temperature
Pulse-Skipping Mode Waveform
Output Short-Circuit Waveform
with 0.1A Load
550
540
530
520
510
500
490
480
470
4ꢁ0
450
V
OUT(AC)
I
100mV/DIV
L
20A/DIV
0A LOAD
I
L
2A/DIV
V
SS
1V/DIV
V
SW
10V/DIV
3775 G10
3775 G25
V
V
= 12V
5μs/DIV
50
–50
0
25
75 100 125
–25
V
V
C
= 12V
= 1.2V
= 0.01μF
20μs/DIV
IN
OUT
IN
OUT
SS
= 1.2V
TEMPERATURE (°C)
LOAD = 0.1A
3775 G11
MODE/SYNC = INTV
SW FREQ = 500kHz
FIRST PAGE CIRCUIT
CC
FIRST PAGE CIRCUIT
Duty Cycle vs VCOMP
ILIMT vs Temperature
ILIMT vs Input Voltage
110
108
10ꢁ
104
102
100
98
100
90
80
70
ꢁ0
50
40
30
20
10
0
110
108
10ꢁ
104
102
100
98
V
IN
= 5V
V
= 12V
V
IN
= 24V
IN
V
= 40V
IN
9ꢁ
9ꢁ
94
94
92
92
90
90
–50
0
25
50
75 100 125
0.ꢁ
1.0 1.2 1.4
(V)
1.ꢁ 1.8 2.0
–25
4
32
0.8
8
12 1ꢁ 20 24 28
INPUT VOLTAGE (V)
3ꢁ 40
TEMPERATURE (°C)
V
COMP
3775 G13
3775 G12
3775 G14
Shutdown Current vs
Input Voltage
ILIMB vs Temperature
IRUN vs Temperature
11.0
10.8
10.ꢁ
10.4
10.2
10.0
9.8
0
–0.2
–0.4
–0.ꢁ
–0.8
–1.0
–1.2
–1.4
–1.ꢁ
–1.8
–2.0
35
30
25
20
15
10
5
9.ꢁ
9.4
9.2
9.0
0
50
75 100 125
–50
0
25
50
75 100 125
–50
0
25
–25
–25
4
8
40
12 1ꢁ 20 24 28 32 3ꢁ
INPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3775 G15
3775 G1ꢁ
3775 G17
3775f
6
LTC3775
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Current vs Temperature
Quiescent Current vs INTVCC
INTVCC Load Regulation
20
18
1ꢁ
14
12
10
8
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.ꢁ
–0.7
–0.8
–0.9
–1.0
8
7
ꢁ
5
V
IN
= 12V
4
3
ꢁ
2
1
0
4
2
0
0
10
20
30
40
50
4.0
4.4
5.2
3.ꢁ
5.ꢁ
ꢁ.0
–50
0
25
50
75 100 125
4.8
–25
TEMPERATURE (°C)
INTV LOAD CURRENT (mA)
INTV (V)
CC
CC
3775 G20
3775 G19
3775 G18
INTVCC Dropout
INTVCC Dropout vs Temperature
0
–0.2
–0.4
–0.ꢁ
–0.8
–1.0
0
–0.2
–0.4
–0.ꢁ
–0.8
–1.0
T
= 25°C
LOAD CURRENT = 20mA
A
0
10
20
30
40
50
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
INTV LOAD CURRENT (mA)
CC
3775 G21
3775 G22
BG Turn-Off Waveform Driving
Renesas RJK0301
BG Turn-On Waveform Driving
Renesas RJK0301
BG
1V/DIV
BG
1V/DIV
0V
0V
3775 G23
3775 G24
V
V
= 12V
20ns/DIV
V
V
= 12V
20ns/DIV
IN
OUT
IN
OUT
= 1.2V
= 1.2V
LOAD = 1A
MOSFET: RENESAS RJK0301
LOAD = 1A
MOSFET: RENESAS RJK0301
3775f
7
LTC3775
PIN FUNCTIONS
I
(Pin 1): Topside Current Limit Set Point. This pin
can be connected to a sense resistor at the drain of the
top MOSFET for more accurate current limit.
LIMT
has an internal 100μA pull-down current, allowing the
topside current limit threshold to be programmed by
V (Pin 11): Main Input Supply. Bypass this pin to PGND
IN
an external resistor connected to V . See Current Limit
IN
with a low ESR ceramic capacitor of value 1μF or greater
Applications.
(X5R or better).
I
(Pin 2): Bottom Side Current Limit Set Point. This
LIMB
SW (Pin 12): Switch Node. Connect this pin to the source
of the upper power MOSFET. This pin is also used as the
input to the bottom side current limit comparator and the
zero-crossing reverse current comparator.
pin has an internal 10μA pull-up current, allowing the
bottom side current limit threshold to be programmed
by an external resistor connected to SGND. See Current
Limit Applications.
TG (Pin 13): Top Gate Drive. This pin drives the gate of
the top N-channel MOSFET. The TG driver draws power
from the BOOST pin and returns to the SW pin, providing
true floating drive to the top MOSFET.
FB (Pin 3): Error Amplifier Input. The FB pin is connected
toaresistivedividerfromV toSGND.Thefeedbackloop
OUT
compensation network is also connected to this pin.
COMP (Pin 4): Error Amplifier Output. Use an RC network
between the COMP pin and the FB pin to compensate the
feedback loop for optimum transient response.
BOOST(Pin14):TopGateDriverSupply.Thispinshouldbe
decoupled to SW with a 0.1μF low ESR ceramic capacitor.
An external Schottky diode from INTV to BOOST creates
CC
SS (Pin 5): Soft-Start. Connect this pin to an external
afloatingcharge-pumpsupplyatBOOST.Nootherexternal
capacitor, C , to implement a soft-start function. When
supplies are required.
SS
the voltage on the SS pin is less than the 0.ꢁV internal
MODE/SYNC (Pin 15): Pulse-Skipping Mode Enable/Sync
Pin. This multifunction pin provides pulse-skipping mode
enable/disable control and an external clock input for syn-
chronizationoftheinternaloscillator.Pullingthispinbelow
1.2V(DC)ordrivingitwithanexternallogic-levelsynchro-
nizationsignaldisablespulse-skippingmodeoperationand
forces continuous operation. Pulling the pin above 1.2V
enables pulse-skipping mode operation. This pin has an
internal50kpull-downresistorconnectedtoSGND.
reference, the LTC3775 regulates the V voltage to the
FB
SS pin voltage instead of the 0.ꢁV reference.
FREQ (Pin 6): Frequency Set. A resistor connected from
this pin to SGND sets the free-running frequency of the
internal oscillator. See Applications Information section
for resistor value selection details.
SGND (Pin 7): Signal Ground. All the internal low power
circuitry returns to the SGND pin. All feedback and soft-
start connections should return to SGND. SGND should
be Kelvin connected to a single point near the negative
RUN/SHDN (Pin 16): Enable/Shutdown Input. Pulling this
pin above 1.22V enables the controller. Forcing this pin
below 1.22V causes the driver outputs to pull low. Pulling
this pin below 0.74V forces the LTC3775 into shutdown
terminal of the V
bypass capacitor.
OUT
BG (Pin 8): Bottom Gate Drive. This pin drives the gate of
mode. While in shutdown, the INTV regulator and most
CC
the bottom N-channel synchronous switch MOSFET. This
internal circuitry turns off and the supply current drops
below14μA.Thispinhasaninternal1μApull-upcurrentthat
allows the LTC3775 to power up if this pin is left floating.
pin swings from PGND to INTV .
CC
INTV (Pin 9): Internal 5.2V Regulator Output. The gate
CC
driver and control circuits are powered from this voltage.
Bypass this pin to power ground with a low ESR ceramic
capacitor of value 4.7μF or greater (X5R or better).
PGND (Pin 17): Power Ground (Exposed Pad). The BG
driver returns to this pin. Connect PGND to the source of
thebottompowerMOSFETandtheV andINTV bypass
IN
CC
SENSE (Pin 10): Topside Current Sensing Input. Con-
capacitors. PGND is electrically isolated from SGND. The
nect this pin to the switch node of the converter for top
exposed pad of the QFN package is connected to PGND.
MOSFET R
current sensing. Alternatively, this pin
DS(ON)
3775f
8
LTC3775
BLOCK DIAGRAM
V
IN
C
VCC
V
IN
INTV
CC
5.2V REG
INTV
CC
V
IN
I
RUN
1μA
EN
–
+
R4
REF
0.ꢁV
100μA
V
IN
R
R
R5
ILIMT
SHDN
RUN/SHDN
–
+
I
1.22V
LIMT
CHIP
SHUTDOWN
UVLO
CTLIM
–
+
0.74V
R
SENSE
INTV
+
–
CC
SENSE
3.ꢁV
ILIMB
I
LIMB
INTV
CC
OVERTEMP
OSC
CBLIM
IREV
+
–
PGND
10μA
+
R
V
SET
ILIMB
FREQ
0.2 • V
ILIMB
EXT SYNC
MODE
+
–
MODE/SYNC
MODE/SYNC
DETECT
PGND
INTV
CC
50k
1μA
MODE
D
B
SS
BOOST
TG
INTV
CC
C
SS
C
I
B
SS
COMP
V
IN
Q
Q
T
SW
SWITCH
LOGIC AND
ANTISHOOT-
THROUGH
–
+
R2
C1
C2
EA
0.ꢁV
SS
+
INTV
CC
LINE
FEEDFORWARD
+
–
FB
PWM
BG
PGND
SGND
B
R3
C3
–
+
FB
R
R
A
B
L
0.ꢁꢁV
MAX
V
OUT
C
OUT
3775 BD
3775f
9
LTC3775
APPLICATIONS INFORMATION
Operation (Refer to Block Diagram)
Unlike many regulators that use a transconductance (g )
m
amplifier, the LTC3775 is designed to use an inverting
summing amplifier topology with the FB pin configured
as a virtual ground. This allows the feedback gain to be
tightly controlled by external components. In addition, the
voltage feedback amplifier allows flexibility in choosing
pole and zero locations. In particular, it allows the use of
“Type 3” compensation, which provides a phase boost
at the LC pole frequency and significantly improves the
control loop phase margin.
The LTC3775 is a constant frequency, voltage mode con-
troller for DC/DC step-down converters. It is designed to
be used in a synchronous switching architecture with two
externalN-channelMOSFETs.Forcircuitoperation,please
refer to the Block Diagram.
The LTC3775 uses voltage mode control in which the duty
cycle is controlled directly by the error amplifier output.
The error amplifier adjusts the voltage at the COMP pin
by comparing the V pin with the 0.ꢁV internal refer-
FB
In a typical LTC3775 circuit, the feedback loop consists
of the line feedforward circuit, the modulator, the external
inductor, the output capacitor and the feedback amplifier
with its compensation network. All these components
affect loop behavior and need to be accounted for in the
loop compensation. The modulator consists of the PWM
generator, the output MOSFET drivers and the external
MOSFETs themselves. The modulator gain varies linearily
with the input voltage. The line feedforward circuit com-
pensates for this change in gain, and provides a constant
gain from the error amplifier output to the inductor input
regardless of input voltage. From a feedback loop point of
view, the combination of the line feedforward circuit and
the modulator looks like a linear voltage transfer function
from COMP to the inductor input and has a gain roughly
equal to 30V/V. It has fairly benign AC behavior at typical
loopcompensationfrequencieswithsignificantphaseshift
appearing at half the switching frequency.
ence. When the load current increases, it causes a drop
in the feedback voltage relative to the reference. The
COMP voltage then rises, increasing the duty cycle until
the LTC3775 output feedback voltage again matches the
reference voltage.
In normal operation, the top MOSFET is turned on when
the PWM comparator changes state and is turned off by
the internal oscillator. The PWM comparator maintains
the proper duty cycle by comparing the error amplifier
output (after being “compensated” by the line feedfor-
ward multiplier) to a sawtooth waveform generated by
the oscillator. When the top MOSFET is turned off, the
bottom MOSFET is turned on until the next cycle begins,
or if pulse-skipping mode operation is enabled, until the
inductor current reverses as determined by the reverse
current comparator.
Feedback Control
The external inductor/output capacitor combination
makes a more significant contribution to loop behavior.
These components cause a second order LC roll-off at the
output with 180° phase shift. This roll-off is what filters
the PWM waveform, resulting in the desired DC output
voltage, but this phase shift causes stability issues in the
feedback loop and must be frequency compensated. At
higher frequencies, the reactance of the output capacitor
approaches its ESR, and the roll-off due to the capacitor
stops, leaving –20dB/decade and 90° of phase shift.
The LTC3775 senses the output voltage at V
with an
OUT
internal feedback op amp (see Block Diagram). This is a
true op amp with a low impedance output, 80dB of open-
loop gain and a 25MHz gain-bandwidth product. The
positive input is connected to an internal 0.ꢁV reference,
while the negative input is connected to the FB pin. The
output is connected to COMP, which is in turn connected
to the line feedforward circuit and from there to the PWM
generator.
Atsteadystate,asshownintheBlockDiagram,theoutputof
the switching regulator is given the following equation
⎛
⎞
RA
RB
VOUT = VREF • 1+
⎜
⎝
⎟
⎠
3775f
10
LTC3775
APPLICATIONS INFORMATION
Figure 1 shows a Type 3 amplifier. The transfer function of
this amplifier is given by the following equation:
Required error amplifier gain at frequency f :
C
AV(CROSSOVER)
⎡
⎤
– 1+ sR2C1 1+ s(R +R3)C3
VCOMP
VOUT
(
)
A
⎣
⎦
=
2
2
sRA C1+ C2 1+ s(C1||C2)R2 1+ sC3R3
⎛
⎞
⎛
⎞
(
)(
)(
)
fC
fC
≈ 40log 1+
– 20log 1+
– 20log A
(
)
MOD
⎜
⎟
⎜
⎟
f
f
⎝
⎠
⎝
⎠
LC
ESR
The RC network across the error amplifier and the feed-
forward components R3 and C3 introduce two pole-zero
pairs to obtain a phase boost at the system unity-gain
⎛
⎞
fP2(RES) fP2(RES) – fZ2(RES)
⎛
⎞
fLC
fC
1+
1+
+
⎜
⎟
⎜
⎟
fC
fLC
fESR fESR – fLC
fZ2(RES)
⎝
⎠
⎝
⎠
R2
RA
frequency, f . In theory, the zeros and poles are placed
≈ 20log
•
C
⎛
⎞
fP2(RES)
⎛
⎞
fC
symmetricallyaroundf ,andthespreadbetweenthezeros
C
1+
+
1+
⎜
⎟
⎜
⎟
and the poles is adjusted to give the desired phase boost
fC
⎝
⎠
⎝
⎠
at f . However, in practice, if the crossover frequency
C
is much higher than the LC double-pole frequency, this
method of frequency compensation normally generates
a phase dip within the unity bandwidth and creates some
concern regarding conditional stability.
where A
is the modulator and line feedforward gain
MOD
and is equal to:
V
IN(MAX) •DCMAX
40V • 0.95
1.25V
AMOD
≈
=
≈ 30V/V
VSAW
If conditional stability is a concern, move the error ampli-
fier’s zero to a lower frequency to avoid excessive phase
dip. The following equations can be used to compute the
feedback compensation component values:
Once the value of resistor R and the pole and zero loca-
A
tions have been decided, the values of C1, R2, C2, R3 and
C3 can be obtained from the above equations.
fSW = switching frequency
Compensating a switching power supply feedback loop is
a complex task. The applications shown in this data sheet
show typical values, optimized for the power components
shown.Thoughsimilarpowercomponentsshouldsuffice,
substantially changing even one major power component
may degrade performance significantly. Stability alsomay
depend on circuit board layout. To verify the calculated
component values, all new circuit designs should be
prototyped and tested for stability.
1
fLC
=
2π LCOUT
1
fESR
=
2πRESR COUT
choose:
fSW
10
fC = crossover frequency =
C2
V
OUT
C3
R3
C1
R2
1
–1
fZ1(ERR) = fLC
=
R
A
2πR2C1
GAIN
+1
–1
–
0
FREQ
–90
FB
fC
5
1
R
COMP
B
fZ2(RES)
=
=
PHASE
–180
–270
+
2π R +R3 C3
V
(
)
REF
A
BOOST
–380
3775 F01
1
fP1(ERR) = fESR
=
2πR2(C1||C2)
Figure 1. Type 3 Amplifier Compensation
1
fP2(RES) = 5fC =
2πR3C3
3775f
11
LTC3775
APPLICATIONS INFORMATION
Output Overvoltage Protection
Soft-Start
Anovervoltagecomparator,MAX,guardsagainsttransient
overshoots (>10ꢀ) as well as other more serious condi-
tions that may overvoltage the output. In such cases, the
topMOSFETisturnedoffandthebottomMOSFETisturned
on until the overvoltage condition is cleared.
The LTC3775 includes a soft-start circuit that provides a
smooth output voltage ramp during start-up. The SS pin
requires an external capacitor, C , to GND with the value
SS
determinedbytherequiredsoft-starttime. Aninternal1μA
current source charges C . When the voltage on the SS
SS
pin is less than the 0.ꢁV internal reference, the LTC3775
Run/Shutdown
regulates the V voltage to the SS pin voltage instead of
FB
the 0.ꢁV reference. As the SS voltage rises linearly from
The LTC3775 can be put into a low power shutdown mode
with quiescent current <14μA by pulling the RUN/SHDN
pin below 0.74V. The RUN/SHDN pin can also be used as
an accurate external UVLO (undervoltage lockout) input
with a threshold of 1.22V. The driver outputs stay low if
this pin is <1.22V. The external resistive divider R4 and R5
shown in the Block Diagram can be used to set the UVLO
0V to 0.ꢁV and beyond, the output voltage, V , rises
OUT
smoothly from zero to its final value. The total soft-start
time can be calculated as:
0.9•CSS
tSOFTSTART
=
1μA
level based on V . The V voltage at which the switching
IN
IN
TheSSpinispulledlowinthefollowingconditions:duringan
starts is given by the following formula:
LDOundervoltagecondition(INTV <3.ꢁV),duringshut-
CC
down(RUNpin<1.22V),duringanovertemperaturecondition
UVLO (Upper) = 1.22V • (1 + R4/R5) – (1μA • R4)
(T > 1ꢁ5°C) and during current limit.
J
The RUN/SHDN pin has an internal 1μA pull-up for default
turn-onifthispinisleftfloating.This1μApull-upcurrentis
includedintheaboveUVLOcalculation. WhenRUN/SHDN
goes above 1.22V, this pull-up current is increased to 5μA.
This provides some amount of hysteresis to the UVLO
threshold. The lower UVLO level becomes:
If either the top or bottom current limit comparator trips,
the SS pin is pulled low until the inductor current regu-
lates at around the current limit setting. Once the fault is
cleared, SS will start charging up allowing the duty cycle
and output voltage to increase gradually. Due to the cur-
rent limit action on the SS pin, it is important to avoid
an overcurrent condition during start-up of the power
UVLO (Lower) = 1.22V • (1 + R4/R5) – (5μA • R4)
So the amount of hysteresis is given by:
UVLO (Hysteresis) = 4μA • R4
supply, or V
will fail to start up properly.
OUT
SWITCHOVER
FROM PULSE-
SKIPPING TO
CONTINUOUS
MODE
V
OUT
0.5V/DIV
LTC3775
I
L
V
IN
5A/DIV
I
RUN
1μA
4μA
R4
R5
–
RUN
V
TURN OFF TG
SS
+
1.22V
0.74V
1V/DIV
EN
–
+
CHIP
SHUTDOWN
3775 F03
V
V
C
= 12V
2ms/DIV
IN
OUT
SS
SHDN
= 1.2V
= 0.01μF
3775 F02
MODE = 0V
SW FREQ = 500kHz
Figure 2. RUN Pin Control
Figure 3. Typical Start-Up Wavform
for a Buck Converter Using the LTC3775
3775f
12
LTC3775
APPLICATIONS INFORMATION
is low during its on-time, the voltage drop from the drain
to source is proportional to the current flow. Alternatively,
for better accuracy, the topside current may be monitored
with a sense resistor.
To prevent discharging a pre-biased V , the LTC3775
OUT
alwaysstartsswitchinginpulse-skippingmodeuptoSS=
0.54V,regardlessofthemodeselectedbytheMODE/SYNC
pin. Thus if V
> 0V during power-up, V
will remain
OUT
OUT
at the pre-biased voltage (if there is no load) until the SS
voltage catches up with V , after which V will track
The benefit of having two comparators is to allow continu-
ous monitoring and cycle-by-cycle control of the inductor
current regardless of the operating duty cycle. In high
OUT
OUT
the SS ramp. The LTC3775 reverts to the selected mode
once SS > 0.54V.
duty cycle operation the top MOSFET, Q , is on most of
T
the time. Thus, a high side comparator is necessary to
limit the output current during high duty cycle operation.
Architecturesthatcontainonlyonecomparatortomonitor
the low side MOSFET will not effectively limit the output
currentduringhighdutycycleoperation.Conversely,during
low duty cycle operation, a low side comparator is neces-
sary to limit the output current. Another common current
sensing scheme uses a sense resistor in series with the
inductor to allow continuous monitoring. However, this
Constant Switching Frequency
The internal oscillator can be programmed from 250kHz
to 1MHz with an external resistor from the FREQ pin to
ground, in order to optimize component size, efficiency
andnoiseforthespecificapplication.Theinternaloscillator
can also be synchronized to an external clock connected
to the MODE/SYNC pin and can lock to a range of 20ꢀ
of the programmed free-running frequency. When locked
to an external clock, pulse-skipping mode operation is
automatically disabled. Constant frequency operation of-
fers a number of benefits: inductor and capacitor values
can be chosen for a precise operating frequency and the
feedback loop can be similarly tightly specified. Noise
generated by the circuit will always be at known frequen-
cies. Subharmonic oscillation and slope compensation,
common headaches with constant frequency current
mode switchers, are absent in voltage mode designs like
the LTC3775.
scheme restricts the range of V
due to the common
OUT
mode range of the current limit comparator. The LTC3775
does not have this V restriction.
OUT
Figure 4 shows the current limit circuitry. The top current
limit comparator, CTLIM monitors the current through the
top MOSFET, Q , when TG is high. If the inductor current
T
exceedsthecurrentlimitthresholdwhenQ ison,Q turns
T
T
offimmediatelyandthebottomMOSFET, Q , turnson. The
B
SENSE pin is the input for CTLIM. For applications where
Thermal Shutdown
LTC3775
V
V
IN
IN
R
R
ILIMT
TG
SENSE
The LTC3775 has a thermal detector that pulls the driver
outputs low if the junction temperature of the chip ex-
ceeds 1ꢁ5°C. The thermal shutdown circuit has 25°C of
hysteresis.
I
CTLIM
LIMT
+
–
TURN OFF TG
100μA
SENSE
Q
T
(OPT)
10μA
R
ILIMB
I
LIMB
SW
Current Limit
0.2 • V
ILIMB
CBLIM
+
V
OUT
–
+
The LTC3775 includes an onboard cycle-by-cycle current
limit circuit that limits the maximum output current to a
user-programmed level. The current limit circuit consists
of two comparators, CTLIM and CBLIM that monitor the
voltage drop across the top and bottom MOSFETs respec-
EXTEND BG
BG
Q
B
PGND
SGND
3775 F04
Figure 4. LTC3775 Current Limit Circuit
tively. Since the MOSFET’s effective resistance, R
,
DS(ON)
3775f
13
LTC3775
APPLICATIONS INFORMATION
Current Limit Blanking Time
the upper MOSFET’s R
is used to sense current,
DS(ON)
connect the SENSE pin to the source of Q (the SW node).
T
The LTC3775 current limit circuit features a short blanking
time following low-to-high and high-to-low transitions at
the SW node. This prevents false tripping of the current
limit circuit if there is ringing on the SW node.
Alternatively,foraccuratecurrentsensing,connectthispin
to a sense resistor located at the drain of Q . The reference
input of CTLIM is connected to the I
external resistor, R
T
pin. Connect an
pin to V to set
LIMT
, from the I
ILIMT
LIMT
IN
When the top gate, TG, goes high, the topside comparator,
CTLIM, waits for 200ns before turning on to monitor the
SENSE voltage. Likewise, when the bottom gate, BG, goes
high the bottom side comparator, CBLIM, waits for 200ns
before turning on to monitor the SW voltage. This means
that the minimum TG and BG pulse is slightly more than
200ns during current limit. These blanking times do not,
however, limit the duty cycle capability of the control loop.
The LTC3775 control loop is capable of operation with a
TG on-time as low as 30ns.
the the current limit threshold. The voltage at the SENSE
pin drops as the inductor current increases. CTLIM trips
if the voltage at the SENSE pin goes below the voltage at
the I
pin causing TG to pull low and turn off Q .
LIMT
T
The bottom current limit comparator, CBLIM, monitors
the current through the bottom MOSFET, Q , when BG
B
is high. If the inductor current exceeds the current limit
threshold when Q is on, Q remains on until the current
B
B
drops below the threshold. The SW pin is the input for
CBLIM. The reference input to CBLIM is derived from
Ifasenseresistorisemployedonthetopside,theLTC3775
automatically lowers the CTLIM blanking time from 200ns
to 100ns. The CBLIM blanking time remains at 200ns. The
blankingtimecanbereducedwhenasenseresistorisused
because the SENSE pin connects to the drain of the top
MOSFET which rings less than the SW node. The LTC3775
detects that a sense resistor is employed by checking that
the voltage at the I
pin. Connect an external resistor,
LIMB
R
, from the I
pin to SGND to set the current limit
ILIMB
LIMB
threshold.
The inductor current flows from PGND to SW when Q is
B
on (for a postitive load current). The SW node is therefore
a negative voltage. The LTC3775 inverts the voltage at the
SW pin before comparing it with the attenuated voltage
the SENSE pin stays high (equal to V ) when BG is high.
IN
(5×) at the I
pin. BG stays high once CBLIM trips and
LIMB
If the SENSE pin is connected to the SW node, SENSE will
TG remains low until the inductor current drops below
the threshold. Figure 5 shows typical waveforms during
output overload.
be at 0V when BG is high.
The Current Sensing Input Pins
The SENSE and I
pins are inputs to the top current
LIMT
limit comparator, CTLIM. The top current limit threshold is
set by the resistor, R , connected to the I pin and
I
L
ILIMT
LIMT
20A/DIV
the I
pin 100ꢂA pull-down current. R
should be
LIMT
ILIMT
0A LOAD
placed close to the LTC3775 and the other end of R
ILIMT
should run parallel with the SENSE trace to the Kelvin
senseconnectionunderneaththesenseresistor,asshown
in Figure ꢁ. The sense resistor should be connected to the
V
SS
1V/DIV
drain of the top power MOSFET and the V node using
IN
short, wide PCB traces. Ideally, the top terminal of the
sense resistors will be immediately adjacent to the posi-
tive terminal of the input capacitor, as shown in Figure 7a.
This path is a part of the high di/dt loop formed by the
sense resistor, top power MOSFET, inductor and output
capacitor.
3775 F05
V
V
C
= 12V
= 1.2V
= 0.01μF
20μs/DIV
IN
OUT
SS
FIRST PAGE CIRCUIT
Figure 5. Typical Waveforms During Output Overload
3775f
14
LTC3775
APPLICATIONS INFORMATION
Since the current limit comparator contains leading edge
blanking, an external RC filter is not required for proper
operation. However, an external filter can be designed by
The bottom side current limit threshold is set by the resis-
tor, R
, from the I
pin to SGND and the I
pin
ILIMB
LIMB
LIMB
10ꢂA pull-up current. The voltage at ILIMB is attenuated
5× internally before it is applied to the input of bottom
current limit comparator, CBLIM. This voltage must be
adding a capacitor across the SENSE and I
pins (C
LIMT
F
in Figure 7a). The filter component should be placed close
quiet. Connect R
from the I
pin to a quiet ground
to the SENSE and I pins.
ILIMB
LIMB
LIMT
near the LTC3775 SGND pin. The other input of CBLIM is
connected to the SW pin. The SW pin is also shared with
the bottom gate driver and should be connected near the
If R
sensing is employed, the Kelvin sense con-
DS(ON)
nection should run from the SENSE pin and the R
ILIMT
resistor to the source and drain terminals of the top power
MOSFET respectively, as shown in Figure 7b. The external
RC filter should not be added since the source terminal
is switching.
drain of the bottom MOSFET, Q .
B
Pulse-Skipping Mode
The LTC3775 can operate in one of two modes selectable
with the MODE/SYNC pin: pulse-skipping mode or forced
continuous mode. Pulse-skipping mode is selected when
increased efficiency at light loads is desired, as shown in
Figure 8. In this mode, the bottom MOSFET is turned off
when inductor current reverses in order to minimize the
efficiency loss due to reverse current flow. As the load
currentdecreases(seeFigure 9), thedutycycleisreduced
to maintain regulation until the minimum on-time (50ns)
is reached. When the load decreases below this point,
the LTC3775 begins to skip cycles to maintain regulation.
This reduces the frequency and improves efficiency by
minimizing gate charge losses.
V
IN
TO R
LIMIT
R
SENSE
TO SENSE PIN
3775 F0ꢁ
TOP MOSFET
DRAIN
Figure 6. Kelvin SENSE Connection
for Topside Current Limiting Sensing
In forced continuous mode, the bottom MOSFET is always
on when the top MOSFET is off, allowing the inductor cur-
rent to reverse at low currents. This mode is less efficient
duetoswitching,buthastheadvantagesofbettertransient
V
IN
V
IN
C
IN
LTC3775
R
LIMIT
I
LIMIT
R
SENSE
C
F
100
SENSE
TG
V
V
= 12V
IN
OUT
90
80
70
ꢁ0
50
40
30
20
10
0
= 1.2V
SW FREQ = 500kHz
3775 F07a
FRONT PAGE CIRCUIT
SW
PULSE-SKIPPING
MODE
Figure 7a. External Filter for Topside Current Sensing
V
CONTINUOUS
V
IN
IN
MODE
C
IN
LTC3775
R
LIMIT
I
LIMIT
TG
Q
T
0.01
0.1
1
10
100
LOAD CURRENT (A)
SENSE
3775 F07b
SW
3775 F08
Figure 7b. Kelvin Connection for Topside RDS(ON) Sensing
Figure 8. Efficiency in Pulse-Skipping/Forced Continuous Modes
3775f
15
LTC3775
APPLICATIONS INFORMATION
PULSE-SKIPPING MODE
FORCED CONTINUOUS
0A
DECREASING
LOAD
CURRENT
0A
0A
0A
0A
0A
3775 F09
Figure 9. Comparison of Inductor Current Waveforms for Pulse-Skipping Mode and Forced Continuous Mode
response at low load currents, constant frequency opera-
tion, and the ability to maintain regulation when sinking
current. See Figure 8 for a comparison of the efficiency
at light loads for each mode.
of the LTC3775’s internal circuitry. The LDO regulates the
voltage at the INTV pin to 5.2V when V is greater than
CC
IN
ꢁ.5V. The INTV pin must be bypassed to ground with a
CC
low ESR (X5R or better) ceramic capcitor of at least 4.7μF.
Good bypassing is needed to supply the high transient
currents required by the MOSFET gate drivers.
In pulse-skipping mode, the LTC3775 reverse-current
comparator, IREV, monitors the SW pin for zero crossing
when the bottom gate, BG, is high. It turns off BG if the
inductor current reverses and the SW voltage goes above
GND. To prevent false tripping due to ringing on the SW
node when BG is first turned on, there is a blanking time
of 200ns similar to the bottom side current limit blanking.
Under certain light load conditions, if the TG on-time is
short, the inductor current may reverse during the IREV
blanking time but the LTC3775 will only turn off BG after
the blanking time.
Aninternalundervoltagelockout(UVLO)monitorsthevolt-
ageonINTV toensurethattheLTC3775hassufficientgate
CC
drive voltage. If the INTV voltage falls below the UVLO
CC
threshold of 3.1V, the gate drive outputs remain low.
Thermal Considerations
The LTC3775 is offered in a 3mm × 3mm QFN package
(UD1ꢁ) that has a thermal resistance R
of ꢁ8°C/W.
TH(JA)
The UD1ꢁ package has a lead pitch of 0.5mm.
In applications where a low value inductor is used, the
high di/dt of the inductor ripple current together with the
Theregulatorcansupplyupto50mAofgatedriveloadcur-
rent.TheexpectedLDOloadcurrentcanbecalculatedfrom
the gate charge requirement of the external MOSFET:
parasitic series inductance of the bottom MOSFET, Q ,
B
and PCB trace inductance creates an opposing voltage to
I
= (f ) • (Q
+ Q
) + 3.5mA
G(QB)
INTVCC
SW
G(QT)
the voltage drop across the R
of QB. This can cause
DS(ON)
IREV to trip early, before the inductor current reverses.
The parasitic series inductance of the PCB trace can be
minimized by connecting the SW pin closer to the drain
where:
3.5mA is the quiescent current of LTC3775
of Q .
Q
G(QT)
Q
G(QB)
is the total gate charge of the top MOSFET
is the total gate charge of the bottom MOSFET
B
INTV Regulator
CC
f
is the switching frequency
SW
The LTC3775 features a P-channel low dropout linear
regulator(LDO)thatsuppliespowertotheINTV pinfrom
CC
the V supply. INTV powers the gate drivers and much
IN
CC
3775f
16
LTC3775
APPLICATIONS INFORMATION
Finally,itisimportanttoverifythecalculationsbyperform-
ing a thermal analysis of the final PCB using an infrared
camera or thermal probe.
The value of Q should come from the plot of V vs
G
GS
Q in the Typical Performance Characteristics section of
G
the MOSFET data sheet. The value listed in the electrical
specifications may be measured at a higher V , such
GS
Operation at Low Supply Voltage
as 10V, whereas the value of interest is at the 5V INTV
CC
gate drive voltage.
The LTC3775 has a minimum input voltage of 4.5V. The
gate driver for the LTC3775 consists of a PMOS pull-up
Care must be taken to ensure that the maximum junction
temperature of the LTC3775 is never exceeded. The junc-
tion temperature can be estimated using the following
equations:
and an NMOS pull-down device, allowing the full INTV
CC
voltage to be applied to the gates during power MOSFET
switching. Nonetheless, care should be taken to deter-
mine the minimum gate drive supply voltage (INTV ) in
CC
P
= V • I
IN INTVCC
DISS
order to choose the optimum power MOSFETs. Important
parameters that can affect the minimum gate drive volt-
T = T + P
• R
TH(JA)
J
A
DISS
age are the minimum input voltage (V
), the LDO
IN(MIN)
As an example of the required thermal analysis, consider
a buck converter with a 24V input voltage and an output
voltage of 3.3V at 15A. The switching frequency is 500kHz
andthemaximumambienttemperatureis70°C.Thepower
MOSFET used for this application is the Vishay Siliconix
dropout voltage, the Q of the power MOSFETs, and the
G
operating frequency.
If the input voltage V is low enough for the INTV LDO
IN
CC
to be in dropout, then the minimum gate drive supply
voltage is:
Si7884DP, which has a typical R
of 7.5mΩ at V
DS(ON)
GS
= 4.5V and 5.5mΩ at V = 10V. From the plot of V vs
GS
GS
V
= V
– V
INTVCC
IN(MIN) DROPOUT
Q , the total gate charge at V = 5V is 18.5nC (the tem-
G
GS
The LDO dropout voltage is a function of the total gate
drive current and the quiescent current of the IC (typically
3.5mA). A curve of dropout voltage versus output cur-
rent for the LDO is shown in Figure 10. The temperature
coefficient of the LDO dropout voltage is approximately
perature coefficient of the gate charge is low). One power
MOSFET is used for the top side and one for the bottom
side. For the UD package:
I
= 3.5mA + 2 • 18.5nC • 500kHz = 22mA
= 24V • 22mA = 528mW
INTVCC
ꢁ000ppm/°C. See the INTV Regulator and Thermal
P
CC
DISS
Considerations sections for information about calculating
T = 70°C + 528mW • ꢁ8°C/W = 105.9°C
J
the total quiescent current.
In this example, the junction temperature rise is 35.9°C.
These equations demonstrate how the gate charge cur-
rent typically dominates the quiescent current of the IC,
and how the choice of the operating frequency and board
heat sinking can have a significant effect on the thermal
performance of the solution.
0
T
= 25°C
A
–0.2
–0.4
–0.ꢁ
–0.8
–1.0
To prevent the maximum junction temperature from be-
ing exceeded, the input supply current of the IC should
be checked when operating in continuous mode (heavy
load) at maximum V . A tradeoff between the operat-
IN
0
10
20
30
40
50
ing frequency and the size of the power MOSFETs may
need to be made in order to maintain a reliable junction
temperature.
INTV LOAD CURRENT (mA)
CC
3775 F10
Figure 10. INTVCC LDO Dropout Voltage vs Current
3775f
17
LTC3775
APPLICATIONS INFORMATION
After the calculations have been completed, it is impor-
tant to measure the gate drive waveforms and the gate
driver supply voltage (INTV to PGND) over all operating
CC
TG
10V/DIV
conditions (low V , nominal V and high V , as well
IN
IN
IN
as from light load to full load) to ensure adequate power
MOSFET enhancement. Consult the power MOSFET data
sheet to determine the actual R
GS
the component temperatures using an infrared camera
or thermal probe.
for the measured
V
DS(ON)
SW
10V/DIV
V , and verify your thermal calculations by measuring
3775 F11
V
V
= 28V
20ns/DIV
IN
OUT
= 0.ꢁV
LOAD = 1A
Operation at High Supply Voltage
MODE/SYNC = 0V
SW FREQ = 1MHz
At high input voltages, the LTC3775’s internal LDO can
dissipate a significant amount of power, which could
cause the maximum junction temperature to be exceeded.
Conditions such as a high operating frequency, or the use
of more than one power MOSFET in parallel, could push
the junction temperature rise to high levels. To prevent
the maximum junction temperature from being exceeded,
the input supply current must be checked while operating
Figure 11. Minimum On-Time Waveforms
in Forced Continuous Mode
TG
10V/DIV
in continuous conduction mode at maximum V . See
IN
the Thermal Considerations section for calculation of the
maximum junction temperature.
V
SW
10V/DIV
Low Duty Cycle Operation
3775 F12
V
V
= 28V
20ns/DIV
IN
OUT
The LTC3775 uses a leading edge modulation architec-
ture. Because the top MOSFET turns on when the PWM
comparator trips, the top MOSFET minimum on-time
is not dependent on the propagation delay of the PWM
comparator; it is only limited by the internal delays of the
gate drivers and the rise/fall time of the power MOSFET
gate. This allows the LTC3775 to operate in very low duty
cycle applications with a large step-down ratio. Figure 11
showsminimumon-timewaveformsforforcedcontinuous
mode operation.
= 0.ꢁV
LOAD = 1A
MODE/SYNC = INTV
SW FREQ = 1MHz
CC
Figure 12. Minimum On-Time Waveforms
in Pulse-Skipping Mode
is 200ns for R
sensing and 100ns when a sense
resistor is used. For TG on-times smaller than the topside
DS(ON)
blanking times, the LTC3775 relies on the bottom current
limit comparator, CBLIM, to monitor the inductor current.
If CBLIM trips, the LTC3775 starts to skip pulses and at
the same time pulls down the soft-start capacitor to limit
If pulse-skipping mode is selected, the LTC3775 allows
the controller to skip pulses at light load, thereby reducing
switching losses and improving the efficiency. Figure 12
shows waveforms of the minimum on-time in pulse-skip-
ping mode.
the duty cycle. If V
drops sufficiently, the TG on-time
OUT
can increase enough to turn on CTLIM and limit the peak
inductor current. The minimum on-time of the application
circuit can be calculated at maximum V :
IN
IftheTGon-timeislessthantheblankingtimeofthetopside
current limit comparator, CTLIM, the topside comparator
never trips during normal operation. The blanking time
VOUT
tON(MIN)
=
fSW • V
IN(MAX)
3775f
18
LTC3775
APPLICATIONS INFORMATION
High Duty Cycle Operation
step-down V to V
ratios, another consideration is
IN
OUT
the minimum on-time of the LTC3775 (see the Minimum
On-TimeConsiderationssection).Afinalconsiderationfor
operatingfrequencyisthatinnoise-sensitivecommunica-
tions systems, it is often desirable to keep the switching
noise out of a sensitive frequency band.
ThemaximumdutycycleislimitedbytheLTC3775internal
oscillator reset time, the propagation delay of the PWM
comparator and the BOOST pin supply refresh rate. The
minimum off-time is typically 300ns.
ThetopMOSFETdriverisbiasedfromthefloatingbootstrap
The LTC3775 uses a constant frequency architecture that
can be programmed over a 250kHz to 1MHz range with a
single resistor from the FREQ pin to ground, as shown in
Figure 14. The nominal voltage on the FREQ pin is 1.22V,
and the current that flows from this pin is used to charge
and discharge an internal oscillator capacitor. The value of
capacitor, C , which normally recharges during each off
B
cyclethroughanexternaldiodewhenthetopMOSFETturns
off. Iftheinputvoltage, V , decreasestoavoltagecloseto
IN
V
OUT
, the controller will enter dropout and attempt to turn
on the top MOSFET continuously. To avoid depleting the
charge on the bootstrap capacitor, C , the LTC3775 has an
B
R
for a given operating frequency can be chosen from
SET
internal counter that turns on the bottom MOSFET every
eight cycles for 200ns to refresh the bootstrap capacitor.
Figure 13 shows maximum duty cycle operation with the
200ns BOOST pin supply refresh.
Figure 14 or from the following equation:
19500
RSET(kΩ) =
f(kHz)
The oscillator can also be synchronized to an external
clock applied to the MODE/SYNC pin with a frequency
in the range of 20ꢀ of the programmed free-running
frequency set by the FREQ pin. In this synchronized
mode, pulse-skipping mode operation is disabled. The
clock high level must exceed 1.5V for at least 25ns. The
bottom MOSFET will turn-on following the rising edge of
the external clock.
TG
5V/DIV
OSCILLATOR
RESET
BOOST PIN
SUPPLY REFRESH
BG
5V/DIV
1000
900
800
700
ꢁ00
500
400
300
200
3775 F13
V
V
= 4.5V
2μs/DIV
IN
OUT
= 4.2V
LOAD = 0A
SW FREQ = 500kHz
Figure 13. Maximum Duty Cycle Waveforms
EXTERNAL COMPONENTS SELECTION
Operating Frequency
The choice of operating frequency and inductor value is
a tradeoff between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFETswitchinglossesandgatechargelosses.However,
lower frequency operation requires more inductance for a
given amount of ripple current, resulting in a larger induc-
tor size and higher cost. If the ripple current is allowed
to increase, larger output capacitors may be required to
maintain the same output ripple. For converters with high
0
10 20 30 40 50 ꢁ0 70 80 90 100
VALUE (kΩ)
R
SET
3775 F14
Figure 14. Frequency Set Resistor (RSET) Value
Top MOSFET Driver Supply
An external bootstrap capacitor, C , connected to the
B
BOOST pin supplies the gate drive voltage for the topside
MOSFET. This capacitor is charged through diode D from
B
3775f
19
LTC3775
APPLICATIONS INFORMATION
INTV whentheswitchnodeislow.WhenthetopMOSFET
capacitance as the drain voltage drops. The upper sloping
line is due to the drain-to-gate accumulation capacitance
andthegate-to-sourcecapacitance.TheMillercharge(the
increase in coulombs on the horizontal axis from a to b
CC
turns on, the switch node rises to V and the BOOST pin
IN
rises to approximately V + INTV . The boost capacitor
IN
CC
needs to store at least 100 times the gate charge required
by the top MOSFET. In most applications a 0.1μF to 1μF
X5R or X7R dielectric capacitor is adequate. The reverse
while the curve is flat) is specified for a given V drain
DS
voltage, but can be adjusted for different V voltages by
DS
breakdown of the Schottky diode, D , must be greater
multiplying by the ratio of the application V to the curve
B
DS
than V
.
specifiedV values.ToestimatethecapacitanceC
,
IN(MAX)
DS
MILLER
take the change in gate charge from points a and b on a
Power MOSFET Selection
manufacturer’s data sheet and divide by the stated V
DS
voltage specified. C
is the most important selec-
MILLER
The LTC3775 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
tion criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. C
and C are specified sometimes but
RSS
OS
the power MOSFETs are the threshold voltage V
,
,
(GS)TH
definitions of these parameters are not included.
breakdown voltage V
, maximum current I
(BR)DSS
and input capacitance.
DS(MAX)
on-resistance R
When the controller is operating in continuous mode the
DS(ON)
duty cycles for the top and bottom MOSFETs are given
by:
The gate drive voltage is set by the 5.2V INTV supply.
CC
Consequently, logic-level threshold MOSFETs must be
used in LTC3775 applications. If the INTV voltage is
VOUT
V
IN
CC
TopGateDuty Cycle =
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered. Pay close attention to the
⎛ V – VOUT
⎞
IN
V
specification because most logic-level MOSFETs
BottomGateDuty Cycle =
(BR)DSS
⎜
⎟
⎠
⎝
V
IN
are limited to 30V or less. The MOSFETs selected should
have a V rating greater than the maximum input
(BR)DSS
The power dissipation for the top and bottom MOSFETs
at maximum output current are given by:
voltage and some margin should be added for transients
and spikes.
VOUT
2
MOSFET input capacitance is a combination of several
componentsbutcanbetakenfromthetypical“gatecharge”
curveincludedonmostdatasheets(Figure15). Thecurve
is generated by forcing a constant input current into the
gate of a common source, current source loaded stage
and then plotting the gate voltage versus time. The initial
slope is the effect of the gate-to-source and the gate-
to-drain capacitance. The flat portion of the curve is the
resultoftheMillermultiplicationeffectofthedrain-to-gate
PTOP
=
I
ρ
R
DS(ON)(MAX)
(
T(TOP))(
)
(
)
OUT(MAX)
V
IN
⎛
⎞
IOUT(MAX)
2
+V
R
(
C
•
DR )(
)
⎜
⎟
IN
MILLER
2
⎝
⎠
⎛
⎞
1
1
+
• f
SW
⎜
⎟
INTVCC – VTH(IL) VTH(IL)
⎝
⎠
V – VOUT
IN
2
V
IN
P
=
I
(
ρ R
T(TOP))(
DS(ON)(MAX)
(
)
)
BOT
OUT(MAX)
V
IN
MILLER EFFECT
V
V
GS
where:
a
b
+
–
V
DS
+
R
V
= Effective top driver resistance
DR
Q
V
IN
GS
–
C
= (Q – Q )/V
B A DS
MILLER
= MOSFET data sheet specified typical gate
3775 F15
TH(IL)
threshold voltage at the specified drain current
Figure 15. Gate Charge Characteristics
3775f
20
LTC3775
APPLICATIONS INFORMATION
C
= Calulated Miller capacitance using the gate
Incontinuousmode,thesourcecurrentofthetopN-channel
MILLER
charge curve from the MOSFET data sheet
MOSFETisapproximatelyasquarewaveofdutycycleV
/
OUT
V . The maximum RMS capacitor current is given by:
IN
f
= Switching frequency
SW
2
VOUT V – V
(
)
IN
OUT
Both MOSFETs have conduction losses (I R) while the
topside N-channel equation includes an additional term
for transition losses, which peak at the highest input volt-
IRMS ≈IOUT(MAX)
V
IN
This formula has a maximum at V = 2V , where
IN
OUT
age. For V < 12V, the high current efficiency generally
IN
I
= I /2. This simple worst-case condition is com-
RMS OUT
improves with larger MOSFETs, while for V > 12V, the
IN
monlyusedfordesignbecauseevensignificantdeviations
do not offer much relief.
transition losses rapidly increase to the point that the use
of a higher R
device with lower C
actually
DS(ON)
MILLER
provideshigherefficiency.ThebottomMOSFETlossesare
greatest at high input voltage when the top switch duty
factor is low or during a short circuit when the bottom
switch is on close to 100ꢀ of the period.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
manufacturer if there is any question.
Schottky Diode Selection
AnoptionalSchottkydiodeconnectedbetweentheSWnode
(cathode) and the source of the bottom MOSFET (anode)
conducts during the dead time between the conduction of
the power MOSFET switches. It is intended to prevent the
body diode of the bottom MOSFET from turning on and
storing a charge during the dead time, which can cause
a modest (about 1ꢀ) efficiency loss. The diode can be
rated for about one half to one fifth of the full load current
since it is on for only a fraction of the duty cycle. In order
for the diode to be effective, the inductance between it
and the bottom MOSFET must be as small as possible,
mandating that these components be placed next to each
other on the same layer of the PC board.
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used
as input capacitors, but each has drawbacks: ceramics
have high voltage coefficients of capacitance and may
have audible piezoelectric effects; tantalums need to be
surge-rated; OS-CONs suffer from higher inductance,
larger case size and limited surface mount applicability;
and electrolytics’ higher ESR and dryout may require
several to be used in parallel. Sanyo OS-CON SVP, SVPD
series;SanyoPOSCAPTQCseriesoraluminumelectrolytic
capacitors from Panasonic WA series or Cornel Dublilier
SPV series, in parallel with a couple of high performance
ceramic capacitors, can be used as an effective means of
achieving low ESR and high bulk capacitance.
Input Capacitor Selection
Theinputbypasscapacitorhasthreeprimaryrequirements:
its ESR must be low to minimize the supply drop when
the top MOSFETs turn on, its RMS current capability must
be adequate to withstand the ripple current at the input,
and its capacitance must be large enough to maintain the
inputvoltageuntiltheinputsupplycanrespond.Generally,
a capacitor (particularly a non-ceramic type) that meets
the first two parameters will have far more capacitance
than is required to keep capacitance-based droop under
control. The input capacitor’s voltage rating should be at
least 1.4 times the maximum input voltage.
Output Capacitor Selection
The selection of C
is primarily determined by the ESR
OUT
requiredtominimizevoltagerippleandloadsteptransients.
The output ripple ΔV
is approximately bounded by:
OUT
⎛
⎞
1
ΔVOUT ≤ ΔIL ESR +
⎜
⎝
⎟
8 • fSW •COUT
⎠
where ΔI is the inductor ripple current.
L
3775f
21
LTC3775
APPLICATIONS INFORMATION
ΔI may be calculated using the equation:
current. Lower ripple current reduces core losses in the
inductor, ESR losses in the output capacitors and out-
put voltage ripple. Highest efficiency is obtained at low
frequency with small ripple current. However, achieving
high efficiency requires a large inductor and generates
higher output voltage excursion during load transients.
There is a tradeoff between component size, efficiency
and operating frequency. Given a specified limit for ripple
current, the inductor value can be obtained using the fol-
lowing equation:
L
⎛
⎞
VOUT
L • fSW
VOUT
ΔIL =
1–
⎜
⎟
V
⎝
⎠
IN
Since ΔI increases with input voltage, the output ripple
L
voltage is highest at maximum input voltage. Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering and has the necessary RMS current
rating.
Manufacturers such as Sanyo, Panasonic and Cornell
Dublilier should be considered for high performance
through-hole capacitors. The OS-CON semiconductor
electrolyte capacitor available from Sanyo has a good
(ESR)(size) product. An additional ceramic capacitor in
parallelwithOS-CONcapacitorsisrecommendedtooffset
the effect of lead inductance.
⎛
⎞
VOUT
SW • ΔIL(MAX)
VOUT
V
IN(MAX)
L =
• 1–
⎜
⎟
f
⎝
⎠
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mμ® cores. A variety of inductors designed for
high current, low voltage applications are available from
manufacturers such as Sumida, Panasonic, Coiltronics,
CoilcraftandToko.SeetheCurretLimitProgrammingsec-
tion for calculation of the inductor saturation current.
In surface mount applications, multiple capacitors may
have to be connected in parallel to meet the ESR or tran-
sient current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
bothavailableinsurfacemountconfigurations.Newspecial
polymersurfacemountcapacitorsofferverylowESRalso
but have much lower capacitive density per unit volume.
In the case of tantalum, it is critical that the capacitors are
surge tested for use in switching power supplies. Several
excellent output capacitor choices are the Sanyo POSCAP
TPD, POSCAP TPB, AVX TPS, AVX TPSV, the Kemet T510
series of surface mount tantalums,Kemet AO-CAPs or the
Panasonic SP series of surface mount special polymer
capacitors available in case heights ranging from 2mm
to 4mm. Other capacitor types include Nichicon PL series
and Sprague 595D series. Consult the manufacturer for
other specific recommendations.
Current Limit Programming
If current sensing is implemented with a sense resistor,
the topside current limit can be programmed by setting
R
as follows:
ILIMT
IO(MAX) +0.5• ΔIL
RILIMT =CF •RSENSE
•
ILIMIT(MIN)
where:
R
= Sense resistor value
SENSE
I
= Maximum output current
O(MAX)
Inductor Selection
ΔI =Inductorripplecurrent(refertotheOutputCapaci-
tor Selection section).
L
The inductor in a typical LTC3775 application circuit is
chosen based on the required ripple current, its size and
itssaturationcurrentrating. Theinductorshouldnotbeal-
lowed to saturate below the hard current limit threshold.
I
= I
pin minimum pull-down current of
LIMT
LIMT(MIN)
90μA
CF = Correction factor to provide safety margin and
The inductor value sets the ripple current, which is com-
monly chosen at around 40ꢀ of the anticipated full load
account for R
is reasonable.
tolerance; use a value of CF = 1.2
SENSE
3775f
22
LTC3775
APPLICATIONS INFORMATION
If topside MOSFET R
sensing is used, the R
I
= I
pin maximum pull-down current of
DS(ON)
ILIMT
LIMT(MAX)
110μA
LIMT
value is calculated from the following equation:
IO(MAX) +0.5• ΔIL
I
= I
pin maximum pull-up current of
LIMB(MAX)
11μA
LIMB
RILIMIT = ρT •RDS(ON)(QT)(MAX)
•
ILIMIT(MIN)
R
and R
are the power
DS(ON)(QB)(MIN)
DS(ON)(QT)(MIN)
R
is the maximum MOSFET on-resistance
DS(ON)(QT)(MAX)
typically specified at 25°C. The ρ term is a normalization
MOSFET minimum on-resistances. MOSFET data sheets
typicallyspecifynominalandmaximumvaluesforR
T
,
DS(ON)
factor(unityat25°C)accountingforthesignificantvariation
inon-resistancewithtemperature,typicallyabout0.5ꢀ/°C
asshowninFigure1ꢁ.Foramaximumjunctiontemperature
but not a minimum. A reasonable assumption is that the
minimumR isthesamepercentagebelowthetypical
value as the maximum lies above it. Consult the MOSFET
manufacturer for further guidelines.
DS(ON)
of 100°C, using a value ρ = 1.4 is reasonable.
T
The bottom side current limit can be programmed by
The saturation current rating for the inductor should be
determinedatthemaximuminputvoltage,maximumoutput
currentandthemaximumexpectedcoretemperature. The
saturationcurrentratingsformostcommerciallyavailable
inductorsdropathightemperature.Toverifysafeoperation,
itisagoodideatocharacterizetheinductor’score/winding
temperatureunderthefollowingconditions:1)worst-case
operating conditions, 2) maximum allowable ambient
temperature and 3) with the power supply mounted in
the final enclosure. Thermal characterization can be done
by placing a thermocouple in intimate contact with the
winding/core structure, or by burying the thermocouple
within the windings themselves.
setting R
as follows:
ILIMB
IO(MAX) +0.5• ΔIL
RILIMB = 5•ρT •RDS(ON)(QB)(MAX)
•
ILIMB(MIN)
whereI =I
pinminimumpull-upcurrentof9μA.
LIMB(MIN) LIMB
TheresultingvaluesofR
andR
shouldbechecked
ILIMT
ILIMB
in an actual circuit to ensure that the current limit kicks
in as expected. Circuits that use MOSFETs with low value
R
DS(ON)
for current sensing should be checked carefully.
The PCB trace resistance and parasitic inductance can
significantlychangetheactualcurrentlimitthreshold.Care
should be taken to shorten the PCB trace at the SENSE,
SW and PGND connections.
2.0
1.5
1.0
0.5
0
The current limit setting also determines the worst-case
peak current flowing in the inductor during an overload
condition. The inductor saturation current rating needs to
be higher than the worst-case peak inductor current:
ILIMT(MAX) •RILIMT
IL(SAT)
≥
RSENSE(MIN)
or
or
50
100
–50
150
0
ILIMT(MAX) •RILIMT
JUNCTION TEMPERATURE (°C)
IL(SAT)
≥
3775 F1ꢁ
RDSON(QT)(MIN)
Figure 16. Typical MOSFET RDS(ON) vs Temperature
0.2•I
•R
ILIMB
(
)
LIMB(MAX)
IL(SAT)
≥
RDSON(QB)(MIN)
3775f
23
LTC3775
APPLICATIONS INFORMATION
MODE/SYNC Pin
sideMOSFET,andthe(–)terminaloftheinputcapacitor.
Connect the signal ground to the (–) terminal of the
output capacitor. Also, try to connect the (–) terminal
of the output capacitor as close as possible to the (–)
terminals of the input capacitor.
The MODE/SYNC pin is a dual function pin that can be
used to program the operating mode or to synchronize
the switching frequency to an external clock. Pulse-
skipping mode is enabled when the MODE/SYNC pin is
above 1.2V. The mode is forced continuous when the pin
is below 1.2V.
2. Thehighdi/dtloopformedbythetopN-channelMOSFET,
the bottom MOSFET and the C capacitor should have
IN
short leads and PC trace lengths to minimize high
frequency noise and voltage stress from inductive
ringing.
If this pin is left floating, an internal 50k pull-down resistor
defaults the selection to forced continuous mode. During
power-up, the LTC3775 overrides this mode selection and
operates in pulse-skipping mode to prevent the discharge
of a pre-biased output capacitor.
3. Connect the drain of the topside MOSFET directly to the
(+) plate of C , and connect the source of the bottom
IN
side MOSFET directly to the (–) terminal of C . This
IN
The internal LTC3775 oscillator can be synchronized
to an external clock with a signal greater than 1.5V. A
low-to-high transition on the MODE/SYNC pin resets the
oscillator sawtooth waveform (high) and forces TG low
(see Figure 17).The external oscillator frequency must be
capacitor provides the AC current to the MOSFETs.
4. Place the ceramic C
decoupling capacitor im-
INTVCC
mediately next to the IC, between INTV and SGND.
CC
Likewise, the C capacitor should also be next to the
B
within 20ꢀ of the frequency programmed by the R
IC between BOOST and SW.
SET
resistor, or else the part will revert to free-running mode.
The internal oscillator locks to the external clock after
the second clock transition is received. When external
synchronization is detected, the LTC3775 will operate in
forced continuous mode.
5. Place the small-signal components away from high
frequency switching nodes (BOOST, SW, TG and BG).
ꢁ. For optimum load regulation and true remote sensing,
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC3775 in order
to keep the high impedance FB node short.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3775. Check the following in your layout:
7. Forapplicationswithmultipleswitchingpowerconvert-
ers connected to the same input supply, make sure
that the input filter capacitor for the LTC3775 is not
shared with other converters. AC input current from
anotherconvertercouldcausesubstantialinputvoltage
1. Keepthesignalandpowergroundsseparate.Thesignal
ground consists of the LTC3775 SGND pin and the (–)
terminal of V . The power ground consists of the
OUT
optionalSchottkydiodeanode,thesourceofthebottom
EXTERNAL CLOCK
AT MODE/SYNC PIN
PWM RAMP
TG
3775 F17
Figure 17. External Synchronization
3775f
24
LTC3775
APPLICATIONS INFORMATION
span the leads of a typical output capacitor. In general, it is
best to take this measurement with the 20MHz bandwidth
limit on the oscilloscope turned on to limit high frequency
noise. Note that microprocessor manufacturers typically
specify ripple ≤20MHz, as energy above 20MHz is gener-
ally radiated (and not conducted) and does not affect the
load even if it appears at the output capacitor.
ripple, and this could interfere with the operation of the
LTC3775. A few inches of PC trace or wire (L ≅ 100nH)
between C of the LTC3775 and the actual source V
IN
IN
should be sufficient to prevent input noise interference
problems.
8. The top current limit programming resistor, R
,
ILIMT
should be placed close to the LTC3775 and the other
end of R should run parallel to the SENSE trace
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test, switching it on and off while
watching the output. If this isn’t convenient, a current
step generator is needed. This generator needs to be able
to turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC3775 and the transient generator
must be minimized.
ILIMT
to the Kelvin sense connection underneath the sense
resistor.
9. The bottom current limit programming resistor, R
,
ILIMB
should be placed close to the LTC3775 and the other
end of R should connect to SGND.
ILIMB
10. The SW pin should be connected to the drain of the
bottom MOSFET.
Figure18showsanexampleofasimpletransientgenerator.
Be sure to use a noninductive resistor as the load element.
Many power resistors use an inductive spiral pattern and
are not suitable for use here. A simple solution is to take
ten 1/4W film resistors and wire them in parallel to get
the desired value. This gives a noninductive resistive load
which can dissipate 2.5W continuously or 250W if pulsed
with a 1ꢀ duty cycle, enough for most LTC3775 circuits.
Solder the MOSFET and the resistor(s) as close to the
output of the LTC3775 circuit as possible and set up the
signal generator to pulse at a 100Hz rate with a 1ꢀ duty
cycle. This pulses the LTC3775 with 100μs transients
10ms apart, adequate for viewing the entire transient
recovery time for both positive and negative transitions
while keeping the load resistor cool.
Checking Transient Response
For all new LTC3775 PCB circuits, transient tests need to
beperformedtoverifytheproperfeedbackloopoperation.
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
shifts by an
OUT
amountequaltoΔI
•(ESR),whereESRistheeffective
LOAD
series resistance of C . ΔI
also begins to charge or
OUT
LOAD
discharge C
generating the feedback error signal that
OUT
forces the regulator to adapt to the current change and
return V
time, V
to its steady-state value. During this recovery
can be monitored for excessive overshoot or
OUT
OUT
ringing which would indicate a stability problem.
Measuring transient response presents a challenge in two
respects: obtaining an accurate measurement and gen-
erating a suitable transient for testing the circuit. Output
measurementsshouldbetakenwithascopeprobedirectly
across the output capacitor. Proper high frequency prob-
ing techniques should be used. Do not use the ꢁ" ground
lead that comes with the probe! Use an adapter that fits
on the tip of the probe and has a short ground clip to
ensure that inductance in the ground path doesn’t cause
a bigger spike than the transient signal being measured.
The typical probe tip ground shield is spaced just right to
V
LTC3775
OUT
R
LOAD
507
IRFZ44 OR
EQUIVALENT
PULSE
GENERATOR
10k
0V TO 10V
100Hz, 1%
DUTY CYCLE
3775 F18
LOCATE CLOSE TO THE OUTPUT
Figure 18. Transient Load Generator
3775f
25
LTC3775
APPLICATIONS INFORMATION
Design Example
on for a short time, a RENESAS RJK0305DPB (R
=
DS(ON)
= 2.5V,
13mΩ (max), C
= Q /10V = 150pF, V
MILLER
GD
GS(TH)
As a design example, take a supply with the following
θ
JA
= 40°C/W) is sufficient. Check its power dissipation
at current limit with = ρ
specifications: V = 5V to 2ꢁV (12V nominal), V
=
IN
OUT(MAX)
OUT
= 1.4:
100°C
1.2V 5ꢀ, I
= 15A, f = 500kHz.
1.2V
26V
2
First, verify the minimum on-time which occurs at maxi-
PTOP
=
15A •1.4•13mΩ
(
)
(
)
mum V :
IN
15A
2
⎛
⎞
2
+ 26V
(
2.5Ω 150pF
1.2V
)
(
)(
)
⎜
⎝
⎟
⎠
tON(MIN)
=
= 92.3ns
26V 500kHz
(
)(
)
⎛
⎝
⎞
⎠
1
1
⎛
⎞
⎠
+
500kHz
⎜
⎝
⎟
⎜
⎟
The minimum on-time is lower than the top current limit
comparator blanking time of 100ns with sense resistor
sensing. The controller will rely on the bottom MOSFET
5.2–2.5 2.5
= 0.19W+0.73W = 0.92W
And double check the assumed T in the MOSFET:
R
DS(ON)
sensing at high V .
IN
J
Next, verify the maximum duty cycle which occurs at
T = 70°C + (0.92W)(40°C/W) = 107°C
J
minimum V :
IN
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful at-
tention to heat sinking will be necessary.
1.2V
5V
Maximum Duty Cycle =
= 24%
A RENESAS RJK0301DPB (R
JA
= 4mΩ (max),
DS(ON)
This is below the LTC3775 maximum duty cycle of 90ꢀ.
θ
= 40°C/W) is chosen for the synchronous MOSFET.
Next, calculate R
frequency:
to give the 500kHz operating
SET
26V –1.2V
26V
2
PBOT
=
15A •1.4•4mΩ =1.26W
(
)
(
)
19500
500
RSET
=
= 39k
And double check the assumed T in the MOSFET:
J
T = 70°C + (1.2ꢁW)(40°C/W) = 120°C
J
Next, choose the inductor value for about 40ꢀ ripple
current at maximum V :
Next, the INTV LDO current is calculated:
IN
CC
I
= (500kHz)(8nC + 32nC) + 3.5mA = 23.5mA
1.2V
1.2
26
⎛
⎞
INTVCC
L =
1–
= 0.38μH
⎜
⎝
⎟
⎠
500kHz 0.4 15A
(
)( )(
)
And double check the T in the LTC3775:
J
T = 70°C + (23.5mA)(2ꢁV)(ꢁ8°C/W) = 112°C
J
Select 0.3ꢁꢂH which is the nearest standard value.
The resulting maximum ripple current is:
Next, set the current limit resistors with a sense resistor
of 3mΩ.
1.2V
1.2V
26V
⎛
⎞
ΔIL =
1–
= 6.4A
15A +0.5•6.4A
⎜
⎝
⎟
⎠
500kHz 0.36μH
(
)(
)
RILIMT =1.2•3mΩ•
= 728Ω
90μA
Next, choose the top and bottom MOSFET switch. Since
the drain of each MOSFET will see the full supply voltage
2ꢁV (max) plus any ringing, choose a 30V MOSFET to
provide a margin of safety. Because the top MOSFET is
15A +0.5•6.4A
RILIMB = 5•1.4•4mΩ•
= 56.62k
9μA
Use the next higher standard values of 732Ω and 57.ꢁk.
3775f
26
LTC3775
APPLICATIONS INFORMATION
The worst-case peak inductor current based on a sense
resistor tolerance of 1ꢀ is
(470μF/5mΩ each) are used to minimize output voltage
changes due to inductor current ripple and load steps.
The ripple voltage will be:
110μA •732Ω
IL(SAT)
≥
= 27.1A
⎛ 0.005
1
⎞
2.97mΩ
VOUT(RIPPLE) = 6.4A •
+
⎜
⎟
⎠
⎝
2
8•500kHz •470μF •2
The input RMS current is highest at V
OUT(MAX)
= 5V and
IN(MIN)
=17.7mV
I
= 15A:
However, a 0A to 15A load step will cause an output volt-
age change of at least:
1.2V 5V –1.2V
(
)
= 6.4A
IRMS ≈15A
5V
ΔV
= (15A)(0.0025Ω) = 37.5mV
OUT(STEP)
C is chosen for an RMS current rating of >ꢁ.4A at 85°C.
For the output capacitor, two low ESR OS-CON capacitors
IN
3775f
27
LTC3775
TYPICAL APPLICATIONS
5V to 26V Input, 1.2V/15A Output at 500kHz
C
F
220pF
V
IN
5V TO 2ꢁV
C
D
+
IN1
B
R
SENSE
330μF
35V
0.003Ω
R
ILIMT
732Ω
V
IN
I
I
TG
Q
T
LIMT
LIMB
R
ILIMB
57.ꢁk
SENSE
C
C
VCC
B
4.7μF
0.1μF
INTV
SS
BOOST
CC
C
SS
L1
0.3ꢁμH
0.01μF
LTC3775
V
1.2V
15A
OUT
SW
BG
C
R
OUT
SET
+
470μF
2.5V
s2
39.2k
FREQ
FB
Q
B
PGND
C2
330pF
MODE/SYNC
COMP RUN/SHDN
SGND
R
R
A
B
10k
10k
R2
4.7k
C1
3.9nF
3775 TA02
C
: SANYO 2R5TPD470M5
OUT
D : CMDSH4E
B
L1: IHLP-4040DZ-ER-R3ꢁ-M11
Q : RJK0301DPB-00-J0
B
T
Q : RJK0305DPB-00-J0
3775f
28
LTC3775
TYPICAL APPLICATIONS
8V to 36V Input, 2.5V/10A Output at 500kHz
V
IN
8V TO 3ꢁV
C
C
B
+
IN1
R4
R
ILIMT
330μF
35V
0.1μF
43.2k
4ꢁ4Ω
R
SENSE
V
IN
BOOST
I
LIMT
0.003Ω
C
F
220pF
R
R5
10k
ILIMB
D
B
133k
I
SENSE
TG
LIMB
C
VCC
4.7μF
INTV
Q
Q
CC
T
C
SS
L1
1.2μH
0.01μF
LTC3775
V
OUT
SW
BG
SS
2.5V
10A
C
R
39.2k
OUT
SET
+
330μF
FREQ
4V
s3
B
RUN/SHDN
FB
PGND
C2
330pF
C3
1500pF
MODE/SYNC
SGND
COMP
R3
390Ω
R
A
10k
R
B
3.1ꢁk
R2
15k
C1
2200pF
3775 TA03
C
: SANYO 4TPD330M
OUT
D : CMDSH4E
B
L1: TOKO FDA1254-1R2M
Q ,Q : INFINEON BSZ097N04LS
B
T
Efficiency and Power Loss
vs Load Current
Load Step
Start-Up
100
90
5
4
3
2
1
0
V
V
= 12V
IN
= 2.5V
OUT
V
CONTINUOUS MODE
SW FREQ = 500kHz
OUT(AC)
SWITCHOVER
FROM PULSE-
SKIPPING TO
CONTINUOUS
MODE
V
80
OUT
100mV/DIV
1V/DIV
70
ꢁ0
50
I
L
5A/DIV
EFFICIENCY
40
30
20
10
0
I
L
10A/DIV
POWER LOSS
V
SS
1V/DIV
3775 TA03c
3775 TA03d
V
V
= 12V
50μs/DIV
0.01
0.1
1
10
IN
OUT
V
V
= 12V
2ms/DIV
IN
OUT
= 2.5V
= 2.5V
LOAD CURRENT (A)
LOAD = 0A TO 10A TO 0A
MODE = 0V
SW FREQ = 500kHz
CSS = 0.01μF
MODE = 0V
3775 TA03b
SW FREQ = 500kHz
3775f
29
LTC3775
TYPICAL APPLICATIONS
24V Input, 12V/5A Output at 500kHz
V
IN
24V
C
D
B
+
IN1
R4
330μF
35V
ꢁ9.8k
R
ILIMT
1.24k
V
IN
R5
10k
I
I
TG
Q
LIMT
LIMB
T
R
ILIMB
5ꢁ.2k
SENSE
C
C
VCC
B
4.7μF
0.1μF
INTV
BOOST
CC
C
SS
L1
4.7μH
0.01μF
LTC3775
V
12V
5A
OUT
SW
BG
SS
R
SET
C
OUT
+
39.2k
ꢁ8μF
1ꢁV
s2
FREQ
Q
B
RUN/SHDN
FB
PGND
C2
330pF
C3
MODE/SYNC
330pF
COMP
SGND
R3
2.05k
R
A
191k
R
B
10k
R2
7.ꢁ8k
C1
3.3nF
3775 TA04
C
: SANYO 1ꢁTQCꢁ8M
OUT
B
D : CMDSH4E
L1: IHLP-4040DZ-ER-4R7-M11
, Q : RJK0305DPB-00-JO
Q
B
T
Efficiency and Power Loss
vs Load Current
Start-Up
Load Step
100
90
80
70
ꢁ0
50
40
30
20
10
0
2.5
2.0
1.5
1.0
0.5
0
V
V
= 24V
IN
= 12V
OUT
SWITCHOVER
CONTINUOUS MODE
SW FREQ = 500kHz
V
OUT
V
OUT(AC)
FROM PULSE-
SKIPPING TO
CONTINUOUS
MODE
5V/DIV
200mV/DIV
EFFICIENCY
I
L
5A/DIV
POWER LOSS
V
I
L
SS
1V/DIV
5A/DIV
3775 TA04c
3775 TA04d
V
V
= 24V
= 12V
50μs/DIV
V
V
= 24V
OUT
CSS = 0.01μF
2ms/DIV
0.01
0.1
1
10
IN
OUT
IN
= 12V
LOAD CURRENT (A)
LOAD = 0A TO 5A TO 0A
MODE = 0V
SW FREQ = 500kHz
3775 TA04b
MODE = 0V
SW FREQ = 500kHz
3775f
30
LTC3775
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1ꢁ91)
0.70 p0.05
3.50 p 0.05
2.10 p 0.05
1.45 p 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 s 45o CHAMFER
R = 0.115
TYP
0.75 p 0.05
3.00 p 0.10
(4 SIDES)
15 1ꢁ
PIN 1
TOP MARK
(NOTE ꢁ)
0.40 p 0.10
1
2
1.45 p 0.10
(4-SIDES)
(UD1ꢁ) QFN 0904
0.200 REF
0.25 p 0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
ꢁ. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3775f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC3775
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC3854
Small Footprint Wide V Range Synchronous Step-Down
Fixed 400kHz Operating Frequency, 4.5V ≤ V ≤ 38V, 0.8V ≤ V
≤ 5.25V,
OUT
IN
IN
DC/DC Controller
2mm × 3mm QFN-12
LTC3851A/
LTC3851A-1
No R ™ Wide V Range Synchronous Step-Down
Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz, 4V ≤ V ≤
IN
SENSE
IN
DC/DC Controller
38V, 0.8V ≤ V
≤ 5.25V, MSOP-1ꢁE, 3mm × 3mm QFN-1ꢁ, SSOP-1ꢁ
OUT
LTC3878
LTC3879
LTC3703-5
LTC3703
No R Constant On-Time Synchronous Step-Down
Very Fast Transient Response, t
= 43ns, 4V ≤ V ≤ 38V,
IN
SENSE
ON(MIN)
DC/DC Controller
0.8V ≤ V
≤ 0.9V , SSOP-1ꢁ
OUT IN
No R
Constant On-Time Synchronous Step-Down
Very Fast Transient Response, t
0.ꢁV ≤ V
= 43ns, 4V ≤ V ≤ 38V,
IN
SENSE
ON(MIN)
DC/DC Controller
≤ 0.9V , MSOP-1ꢁE, 3mm × 3mm QFN-1ꢁ
IN
OUT
High Voltage Synchronous Step-Down DC/DC Voltage
Mode Controller
4.1V ≤ V ≤ ꢁ0V, 0.8V ≤ V
≤ 0.9V , Logic-Level Gate Driver, SSOP-1ꢁ,
OUT IN
IN
TSSOP-28
High Voltage Synchronous Step-Down DC/DC Voltage
Mode Controller
9.3V ≤ V ≤ 100V, 0.8V ≤ V
≤ 0.9V , 9.3V to 15V Gate Driver,
IN
OUT IN
SSOP-1ꢁ, TSSOP-28
LTC3850/
LTC3850-1/
LTC3850-2
Dual 2-Phase, High Efficiency Synchronous Step-Down
Phase-Lockable Fixed Operating Frequency 250kHz to 780kHz,
4V ≤ V ≤ 30V, 0.8V ≤ V ≤ 5.25V
DC/DC Controllers, R
or DCR Current Sensing and
SENSE
IN
OUT
Tracking
LTC3853
Triple Output, Multiphase Synchronous Step-Down DC/DC Phase-Lockable Fixed Operating Frequency 250kHz to 750kHz,
Controller, R or DCR Current Sensing and Tracking 4V ≤ V ≤ 24V, V Up to 13.5V
SENSE
IN
OUT
LTM®4ꢁ00HV
LTM4ꢁ01AHV
LTC3ꢁ01
10A DC/DC μModule Complete Power Supply
High Efficiency, Compact Size, UltraFast™ Transient Response,
4.5V ≤ V ≤ 28V, 0.8V ≤ V ≤ 5V, 15mm × 15mm × 2.8mm
IN
OUT
12A DC/DC μModule Complete Power Supply
High Efficiency, Compact Size, UltraFast Transient Response,
4.5V ≤ V ≤ 28V, 0.8V ≤ V ≤ 5V, 15mm × 15mm × 2.8mm
IN
OUT
1.5A, 4MHz, Monolithic Synchronous Step-Down
DC/DC Converter
High Efficiency, Phase Lockable I = 300μA, 4V ≤ V ≤ 15V,
Q
IN
V
= 0.ꢁV, 3mm × 3mm QFN-1ꢁ, MSOP-1ꢁE
OUT(MIN)
LTC3ꢁ03
2.5A, 3MHz, Monolithic Synchronous Step-Down
DC/DC Converter
High Efficiency, Phase Lockable I = 75μA, 4.5V ≤ V ≤ 15V,
OUT(MIN)
Q
IN
V
= 0.ꢁV, 4mm × 4mm QFN-20
LTC3ꢁ05
5A, 4MHz, Monolithic Synchronous Step-Down
DC/DC Converter
High Efficiency, Adjustable Frequency 800kHz to 4MHz, 4V ≤ V ≤ 15V,
IN
OUT(MIN)
V
= 0.ꢁV, 4mm × 4mm QFN-24
LTC3ꢁ08
8A, 1MHz, Monolithic Synchronous Step-Down
DC/DC Converter
High Efficiency, Adjustable Constant On-Time, 4V ≤ V ≤ 18V,
IN
OUT(MIN)
V
= 0.ꢁV, 7mm × 8mm QFN-52
LTC3ꢁ09
ꢁA, 1MHz, Monolithic Synchronous Step-Down
DC/DC Converter
High Efficiency, Adjustable Constant On-Time, 4V ≤ V ≤ 32V,
IN
OUT(MIN)
V
= 0.ꢁV, 7mm × 8mm QFN-52
LTC3ꢁ10
12A, 1MHz, Monolithic Synchronous Step-Down
DC/DC Converter
High Efficiency, Adjustable Constant On-Time, 4V ≤ V ≤ 24V,
IN
OUT(MIN)
V
= 0.ꢁV, 9mm × 9mm QFN-ꢁ4
LTC3ꢁ11
10A, 1MHz, Monolithic Synchronous Step-Down
DC/DC Converter
High Efficiency, Adjustable Constant On-Time, 4V ≤ V ≤ 32V,
IN
OUT(MIN)
V
= 0.ꢁV, 9mm × 9mm QFN-ꢁ4
LTC3824
Low I , High Voltage DC/DC Controller, 100ꢀ Duty Cycle
Selectable Fixed Operating Frequency, 4V ≤ V ≤ ꢁ0V, 0.8V ≤ V
Q
≤ V ,
OUT IN
Q
IN
I = 40μA, MSOP-10E
LTC3857/
LTC3857-1
Low I , Dual Output 2-Phase Synchronous Step-Down
Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,
Q
DC/DC Controller with 99ꢀ Duty Cycle
4V ≤ V ≤ 38V, 0.8V ≤ V
≤ 24V, I = 50μA,
OUT Q
IN
LTC38ꢁ8/
LTC38ꢁ8-1
Low I , Dual Output 2-Phase Synchronous Step-Down
Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,
4V ≤ V ≤ 24V, 0.8V ≤ V ≤ 14V, I = 170μA,
Q
DC/DC Controller with 99ꢀ Duty Cycle
IN
OUT
Q
LT®3845
Low I , High Voltage Synchronous Step-Down DC/DC
Adjustable Fixed Operating Frequency 100kHz to 500kHz, 4V ≤ V ≤ ꢁ0V,
IN
Q
Controller
1.23V ≤ V
≤ 3ꢁV, I = 30μA, TSSOP-1ꢁ
OUT Q
No R
and UltraFast are trademarks of Linear Technology Corporation.
SENSE
3775f
LT 1009 • PRINTED IN USA
LinearTechnology Corporation
1ꢁ30 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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