LTC3776EGN#TR [Linear]
LTC3776 - Dual 2-Phase, No RSENSE Synchronous Controller for DDR/QDR Memory Termination; Package: SSOP; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC3776EGN#TR |
| 厂家： | 
Linear |
| 描述： | LTC3776 - Dual 2-Phase, No RSENSE Synchronous Controller for DDR/QDR Memory Termination; Package: SSOP; Pins: 24; Temperature Range: -40°C to 85°C 双倍数据速率 开关 光电二极管 |
| 文件： | 总28页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3776
TM
Dual 2-Phase, No RSENSE
,
Synchronous Controller for
DDR/QDR Memory Termination
U
FEATURES
DESCRIPTIO
■
No Current Sense Resistors Required
TheLTC®3776isa2-phasedualoutputsynchronousstep-
downswitchingregulatorcontrollerforDDR/QDRmemory
termination applications. The second controller regulates
its output voltage to 1/2 VREF while providing symmetrical
source and sink output current capability.
■
Out-of-Phase Controllers Reduce Required
Input Capacitance
VOUT2 Tracks 1/2 VREF
■
■
Symmetrical Source/Sink Output Current
Capability (VOUT2
)
TheNoRSENSE constantfrequencycurrentmodearchitec-
ture eliminates the need for sense resistors and improves
efficiency. Power loss and noise due to the ESR of the
input capacitance are minimized by operating the two
controllers out of phase.
■
■
■
■
■
■
■
■
■
■
■
Spread Spectrum Operation (When Enabled)
Wide VIN Range: 2.75V to 9.8V
Constant Frequency Current Mode Operation
0.6V ±1.5% Voltage Reference (VOUT1
)
Low Dropout Operation: 100% Duty Cycle
True PLL for Frequency Locking or Adjustment
Internal Soft-Start Circuitry
Theswitchingfrequencycanbeprogrammedupto750kHz,
allowing the use of small surface mount inductors and ca-
pacitors. For noise sensitive applications, the LTC3776
switching frequency can be externally synchronized from
250kHz to 850kHz, or can be enabled for spread spectrum
operation.Forcedcontinuousoperationreducesnoiseand
RF interference. Soft-start for VOUT1 is provided internally
and can be extended using an external capacitor.
Power Good Output Voltage Monitor
Output Overvoltage Protection
Micropower Shutdown: IQ = 9μA
Tiny Low Profile (4mm × 4mm) QFN and Narrow
SSOP Packages U
APPLICATIO S
The LTC3776 is available in the tiny thermally enhanced
(4mm × 4mm) QFN package or 24-lead SSOP narrow
package.
■
DDR, DDR II and QDR Memory
■
SSTL, HSTL Termination Supplies
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst
■
Mode is a registered trademark of Linear Technology Corporation. No R
is a
Servers, RAID Systems
SENSE
trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 5481178, 5929620, 6144194,
6580258, 6304066, 6611131, 6498466, patent pending on Spread Spectrum.
■
Distributed DC Power Systems
U
TYPICAL APPLICATIO
High Efficiency, 2-Phase, DDR Memory (VDDQ and VTT) Supplies
Efficiency vs Load Current
V
IN
3.3V
100
90
80
70
60
50
40
30
20
10
0
10μF
×2
V
+
IN
+
SENSE1 SENSE2
TG1
TG2
1.5μH
1.5μH
SW1
SW2
LTC3776
BG1
BG2
PGND
PGND
FIGURE 14 CIRCUIT
V
V
REF
CHANNEL 2 (V = 3.3V)
V
(V )
(V
)V
187k
IN
OUT2 TT
DDQ OUT1
CHANNEL 1 (V = 5V)
IN
1.25V
2.5V
4A
V
FB1
FB2
CHANNEL 1 (V = 3.3V)
±4A
IN
I
I
TH2
TH1
CHANNEL 2 (V = 5V)
IN
2200pF
6.2k
470pF
59k
SGND
47μF
47μF
10
100
1000
10000
15k
LOAD CURRENT (mA)
3776 TA01b
3776 TA01a
3776fa
1
LTC3776
W W
U W
ABSOLUTE AXI U RATI GS (Note 1)
Input Supply Voltage (VIN) ........................ –0.3V to 10V
TG1, TG2, BG1, BG2 Peak Output Current (<10μs) ..... 1A
Operating Temperature Range (Note 2) ... –40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
Junction Temperature (Note 3) ............................ 125°C
Lead Temperature (Soldering, 10 sec)
PLLLPF, RUN/SS, SYNC/SSEN,
V
REF, SENSE1+, SENSE2+, VFB2
IPRG1, IPRG2 Voltages................. –0.3V to (VIN + 0.3V)
FB1, ITH1, ITH2 Voltages ........................... –0.3V to 2.4V
V
SW1, SW2 Voltages .............. –2V to VIN + 1V (10V Max)
PGOOD ..................................................... –0.3V to 10V
(LTC3776EGN) ..................................................... 300°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
TOP VIEW
NUMBER
+
1
2
SENSE1
PGND
24
23
22
21
20
19
SW1
IPRG1
24 23 22 21 20 19
LTC3776EUF
LTC3776EGN
3
BG1
V
FB1
TH1
I
1
2
3
4
5
6
18 SYNC/SSEN
TH1
4
SYNC/SSEN
TG1
I
IPRG2
PLLLPF
SGND
TG1
17
16
5
IPRG2
PLLLPF
SGND
PGND
25
6
PGND
15 TG2
V
7
18 TG2
14 RUN/SS
13 BG2
IN
V
8
RUN/SS
17
16
15
14
13
V
REF
IN
UF PART MARKING
3776
9
BG2
V
REF
7
8
9
10 11 12
10
11
12
PGND
SENSE2
SW2
V
FB2
TH2
+
I
PGOOD
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W
GN PACKAGE
24-LEAD PLASTIC SSOP
EXPOSED PAD (PIN 25) IS PGND
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
Input DC Supply Current
Normal Operation
Shutdown
(Note 4)
I
= I
= 1.3V
575
9
3
850
20
10
μA
μA
μA
TH1
TH2
RUN/SS = 0V
UVLO
V
IN
< UVLO Threshold –200mV
Undervoltage Lockout Threshold
V
IN
V
IN
Falling
Rising
●
●
1.95
2.15
2.25
2.45
2.55
2.75
V
V
Shutdown Threshold at RUN/SS
Start-Up Current Source
0.45
0.4
0.65
0.7
0.85
1
V
RUN/SS = 0V
μA
Regulated Feedback Voltage (V
)
)
0°C to 85°C (Note 5)
–40°C to 85°C
0.591
0.588
0.6
0.6
0.609
0.612
V
V
FB1
●
●
Regulated Feedback Voltage (V
V
REF
= 2.5V
1.232
1.250
1.268
V
FB2
Output Voltage Line Regulation (V
Output Voltage Line Regulation (V
)
)
2.75V < V < 9.8V (Note 5)
0.05
0.02
0.2
0.1
mV/V
mV/V
FB1
FB2
IN
3776fa
2
LTC3776
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Load Regulation
I
I
= 0.9V (Note 5)
= 1.7V
0.12
–0.12
0.5
–0.5
%
%
TH
TH
V
Input Current
(Note 5)
10
50
16
nA
%
FB1
Overvoltage Protect Threshold
Measured at V with Respect to
Regulated Feedback Voltage
10
13.3
FB
Overvoltage Protect Hysteresis
3
%
ns
ns
ns
ns
Top Gate (TG) Drive 1, 2 Rise Time
Top Gate (TG) Drive 1, 2 Fall Time
Bottom Gate (BG) Drive 1, 2 Rise Time
Bottom Gate (BG) Drive 1, 2 Fall Time
C = 3000pF
40
40
50
40
L
C = 3000pF
L
C = 3000pF
L
C = 3000pF
L
Maximum Current Sense Voltage (Channel 1)
IPRG1 = Floating (Note 6)
IPRG1 = 0V
●
●
●
●
●
●
110
70
125
85
204
147
100
245
140
100
223
167
115
275
mV
mV
mV
mV
mV
mV
+
(SENSE1 – SW1)(ΔV
) (SOURCE)
SENSE(MAX)
IPRG1 = V
185
127
85
IN
Maximum Current Sense Voltage (Channel 2)
IPRG2 = Floating (Note 6)
IPRG2 = 0V
+
(SENSE2 – SW2)(ΔV
) (SOURCE)
SENSE(MAX)
IPRG2 = V
215
IN
Minimum Current Sense Voltage (Channel 2 Only) IPRG2 = Floating (Note 6)
●
●
●
–130
–90
–208
–112
–75
–188
–94
–60
–168
mV
mV
mV
+
(SENSE2 – SW2)(ΔV
) (SINK)
IPRG2 = 0V
IPRG2 = V
SENSE(MAX)
IN
Soft-Start Time
Time for V to Ramp from 0.05V to 0.55V
0.667
0.833
1
ms
FB1
Oscillator and Phase-Locked Loop
Oscillator Frequency
Spread Spectrum Disabled (SYNC/SSEN = GND)
PLLLPF = Floating
●
●
●
460
260
650
550
300
750
610
340
825
kHz
kHz
kHz
PLLLPF = 0V
PLLLPF = V
IN
Spread Spectrum Frequency Range
Phase-Locked Loop Lock Range
SYNC/SSEN = V
IN
Minimum Switching Frequency
Maximum Switching Frequency
450
580
kHz
kHz
SYNC/SSEN Clocked
Minimum Synchronizable Frequency
Maximum Synchronizable Frequency
●
●
200
1150
250
kHz
kHz
850
Phase Detector Output Current
Sinking
f
f
> f
< f
–4
4
μA
μA
OSC
OSC
SYNC/FCB
SYNC/FCB
Sourcing
PGOOD Output
PGOOD Voltage Low
PGOOD Trip Level
I
Sinking 1mA
125
mV
PGOOD
V
with Respect to Set Output Voltage
FB
V
FB
V
FB
V
FB
V
FB
< Regulated Feedback Voltage, Ramping Positive
< Regulated Feedback Voltage, Ramping Negative
> Regulated Feedback Voltage, Ramping Negative
> Regulated Feedback Voltage, Ramping Positive
–13
–16
7
–10.0
–13.3
10.0
–7
–10
13
%
%
%
%
10
13.3
16
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: T is calculated from the ambient temperature T and power
J A
dissipation P according to the following formula:
D
T = T + (P • θ °C/W)
J
A
D
JA
Note 4: Dynamic supply current is higher due to gate charge being
Note 2: The LTC3776E is guaranteed to meet specified performance from
0°C to 70°C. Specifications over the –40°C to 85°C operating range are
assured by design, characterization and correlation with statistical process
controls.
delivered at the switching frequency.
Note 5: The LTC3776 is tested in a feedback loop that servos I to a
specified voltage and measures the resultant V voltage.
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
TH
FB
a percentage of value as shown in Figure 2.
3776fa
3
LTC3776
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
Step from Sinking to Sourcing
Load Current (CH2)
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
V
OUT2
100mV/DIV
AC-COUPLED
LOAD CURRENT
500mA/DIV
FIGURE 14 CIRCUIT
CHANNEL 2 (V = 3.3V)
IN
3776 G02
CHANNEL 1 (V = 5V)
IN
20μs/DIV
CHANNEL 1 (V = 3.3V)
IN
IN
V
= 3.3V
IN
CHANNEL 2 (V = 5V)
FIGURE 14 CIRCUIT
10
100
1000
10000
LOAD CURRENT (mA)
3776 G01
Tracking Start-Up with Internal
Soft-Start (CSS = 0μF)
Load Step (Load Connected
Between VOUT1 and VOUT2
)
V
OUT1
100mV/DIV
V
=
OUT1
AC-COUPLED
2.5V
500mV/DIV
V
OUT2
100mV/DIV
V
=
OUT2
AC-COUPLED
1.25V
LOAD CURRENT
1A/DIV
3776 G03
3776 G04
20μs/DIV
500μs/DIV
FIGURE 14 CIRCUIT
V
= 3.3V
V
= 3.3V
IN
IN
FIGURE 14 CIRCUIT
V
V
SOURCING
SINKING
OUT1
OUT2
Tracking Start-Up with External
Oscillator Frequency
vs Input Voltage
Maximum Current Sense Voltage
vs ITH1 Pin Voltage (CH1)
Soft-Start (CSS = 0.15μF)
5
100
80
60
40
20
0
4
3
V
=
OUT1
2.5V
2
500mV/DIV
1
V
=
OUT2
0
1.25V
–1
–2
–3
–4
–5
3776 G05
4ms/DIV
FIGURE 14 CIRCUIT
V
= 3.3V
IN
–20
2
6
8
9
0.5
1
I
1.5
VOLTAGE (V)
2
3
4
5
7
10
INPUT VOLTAGE (V)
TH
3736 G06
3776 G07
3776fa
4
LTC3776
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
Regulated Feedback Voltage
(CH2) vs Temperature
Maximum Current Sense Voltage
vs ITH2 Pin Voltage (CH2)
Regulated Feedback Voltage
(CH1) vs Temperature
1.2625
1.2600
1.2575
1.2550
1.2525
1.2500
1.2475
1.2450
1.2425
1.2400
1.2375
100
80
0.612
0.608
0.604
0.600
0.596
0.592
0.588
V
= 2.500V
REF
60
40
20
0
–20
–40
–60
–80
–100
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
40 60
–60 –40 –20
TEMPERATURE (°C)
0
20
80 100
0
1.5
2.0
1.0
I
VOLTAGE (V)
TH2
3776 G09
3776 G10
3776 G08
Maximum Current Sense Threshold
(CH1) vs Temperature
Shutdown (RUN) Threshold
vs Temperature
RUN/SS Pull-Up Current
vs Temperature
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
135
130
125
120
1.0
0.9
0.8
0.7
0.6
0.5
0.4
I
= FLOAT
PRG1
115
–60 –40 –20
0
20 40 60 80 100
40 60
–60 –40 –20
TEMPERATURE (°C)
–60
20
TEMPERATURE (°C)
60 80
0
20
80 100
–40 –20
0
40
100
TEMPERATURE (°C)
3736 G13
3736 G11
3736 G12
Maximum Current Sense
Threshold (CH2) vs Temperature
Oscillator Frequency
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
10
8
150
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
I
= FLOAT
PRG2
V
RISING
IN
6
145
140
4
2
0
V
FALLING
IN
–2
–4
–6
–8
–10
135
130
125
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
20 40
–60 –40 –20
0
60 80 100
20
–60 –40 –20
0
40 60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
3736 G15
3736 G16
3776 G14
3776fa
5
LTC3776
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
U W
Shutdown Quiescent Current
vs Input Voltage
RUN/SS Start-Up Current
vs Input Voltage
20
18
16
14
12
10
8
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
RUN/SS = 0V
RUN/SS = 0V
6
4
2
0
2
6
8
9
3
4
5
7
10
6
7
2
3
4
5
8
9
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3736 G17
3736 G18
U
U
U
PI FU CTIO S
(UF/GN Package)
ITH1/ITH2 (Pins 1, 8/ Pins 4, 11): Current Threshold and
Error Amplifier Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
Thepositiveinputoftheerroramplifierforchannel2senses
one half of the voltage on this pin through an internal
resistor divider.
PGOOD(Pin9/Pin12):PowerGoodOutputVoltageMoni-
tor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (VFB1, VFB2) is not
within ±13.3% of its nominal set point.
PLLLPF (Pin 3/Pin 6): Frequency Set/PLL Lowpass Filter.
When synchronizing to an external clock, this pin serves
as the lowpass filter point for the phase-locked loop. Nor-
mallyaseriesRCisconnectedbetweenthispinandground.
PGND (Pins 12, 16, 20, 25/ Pins 15, 19, 23): Power
Ground.Thesepinsserveasthegroundconnectionforthe
gate drivers and the negative input to the reverse current
comparators. The Exposed Pad (UF package) must be
soldered to PCB ground.
WhenSYNC/SSENistiedtoGND,thispinservesasthefre-
quency select input. Tying this pin to GND selects 300kHz
operation; tying this pin to VIN selects 750kHz operation.
Floating this pin selects 550kHz operation. When SYNC/
SSEN is tied to VIN to enable spread spectrum operation,
a capacitor (1nF to 4.7nF) should be connected from this
pin to SGND to filter and smooth the changes in frequency
of the LTC3776’s internal oscillator.
RUN/SS (Pin 14/Pin 17): Run Control Input and Optional
ExternalSoft-StartInput.Forcingthispinbelow0.65Vshuts
down the chip (both channels). Driving this pin to VIN or
releasing this pin enables the chip, using the chip’s inter-
nalsoft-start.Anexternalsoft-startcanbeprogrammedby
connecting a capacitor between this pin and ground.
SGND(Pin4/Pin7):Small-SignalGround. Thispinserves
as the ground connection for most internal circuits.
TG1/TG2(Pins17,15/Pins20,18):Top(PMOS)GateDrive
Output.ThesepinsdrivethegatesoftheexternalP-channel
MOSFETs. ThesepinshaveanoutputswingfromPGNDto
SENSE+.
VIN (Pin 5/Pin 8): Chip Signal Power Supply. This pin
powerstheentirechipexceptforthegatedrivers.Externally
filtering this pin with a lowpass RC network (e.g.,
R = 10Ω, C = 1μF) is suggested to minimize noise pickup,
especially in high load current applications.
SYNC/SSEN (Pin 18/Pin 21): Synchronization Input and
SpreadSpectrumModulationEnableInput.Tosynchronize
V
REF (Pin 6/Pin 9): Reference voltage input for channel 2.
the LTC3776’s switching frequency to an external clock
3776fa
6
LTC3776
U
U
U
PI FU CTIO S
(UF/GN Package)
using the phase-locked loop, apply a CMOS compatible
clockwithafrequencybetween250kHzand850kHztothis
pin. Tie this pin to GND to enable constant frequency
operation(300kHz,550kHzor750kHzasdeterminedbythe
stateofthePLLLPFpin).TiethispintoVIN toenablespread
spectrum operation. In spread spectrum mode, the
LTC3776’s frequency is randomly varied between 450kHz
and 580kHz.
SW1/SW2(Pins22,10/Pins1,13):SwitchNodeConnec-
tiontoInductor. Alsothenegativeinputtodifferentialpeak
current comparator and an input to the reverse current
comparator. Normally connected to the drain of the exter-
nalP-channelMOSFETs,thedrainoftheexternalN-channel
MOSFET and the inductor.
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to
SelectMaximumPeakSenseVoltageThreshold.Thesepins
select the maximum allowed voltage drop between the
SENSE+ and SW pins (i.e., the maximum allowed drop
across the external P-channel MOSFET) for each channel.
Tie to VIN, GND or float to select one of three discrete
levels.
BG1/BG2(Pins19,13/Pins22,16):Bottom(NMOS)Gate
Drive Output. These pins drive the gates of the external N-
channel MOSFETs. These pins have an output swing from
PGND to SENSE+.
SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14): Positive
Input to Differential Current Comparator. Also powers the
gate drivers. Normally connected to the source of the ex-
ternal P-channel MOSFET.
VFB1/VFB2(Pins24,7/Pins3,10):FeedbackPins.Receives
the remotely sensed feedback voltage for its controller.
ExposedPad(Pin25/NA):TheExposedPad(UFPackage)
must be soldered to the PCB ground.
U
U
W
FU CTIO AL DIAGRA
(Common Circuitry)
R
VIN
V
IN
(TO CONTROLLER 1, 2)
V
IN
C
VIN
UNDERVOLTAGE
LOCKOUT
VOLTAGE
REFERENCE
0.6V
REF
V
0.7μA
SHDN
RUN/SS
t
= 1ms
+
–
SEC
EXTSS
INTSS
SYNC/SSEN
PLLLPF
SYNC DETECT/
SPREAD
SPECTRUM
ENABLE
PHASE
DETECTOR
CLK1
CLK2
VOLTAGE
CONTROLLED
OSCILLATOR
SLOPE1
SLOPE2
SLOPE
COMP
–
V
FB1
UV1
UV2
PGOOD
OV1
SHDN
+
0.54V
IPRG1
IPRG2
MAXIMUM
IPROG1
3776 FD
0.9 • V /2
REF
+
–
OV2
SENSE VOLTAGE
SELECT
IPROG2
V
FB2
3776fa
7
LTC3776
U
U
W
FU CTIO AL DIAGRA (Controller 1)
V
IN
+
SENSE1
TG1
C
IN
RS1
CLK1
S
R
Q
MP1
SWITCHING
LOGIC
PGND
SW1
BG1
ANTISHOOT
THROUGH
L1
AND
OV1
SC1
BLANKING
CIRCUIT
V
OUT1
+
SENSE1
C
OUT1
MN1
PGND
SLOPE1
–
+
SW1
ICMP
+
SENSE1
IPROG1
SHDN
–
R1B
R1A
V
FB1
+
EAMP
+
–
EXTSS
INTSS
0.6V
I
TH1
R
ITH1
0.12V
+
–
V
+
–
FB1
C
ITH1
SC1
SCP
OV1
OVP
V
FB1
0.68V
3776fa
8
LTC3776
U
U
W
FU CTIO AL DIAGRA (Controller 2)
V
IN
+
SENSE2
TG2
RS2
CLK2
S
R
Q
MP2
SWITCHING
LOGIC
PGND
SW2
BG2
ANTISHOOT
THROUGH
L2
AND
OV2
SC2
BLANKING
CIRCUIT
V
OUT2
+
SENSE2
C
OUT2
MN2
PGND
SLOPE2
–
+
SW2
ICMP
+
SENSE2
SHDN
V
FB2
–
+
40k
40k
+
EAMP
V
REF
–
120k
40k
I
TH2
R
ITH2
V
/8
+
–
V
+
REF
FB2
C
ITH2
SC2
SCP
OV2
OVP
V
/2
1.1 • V /2
FB2
–
REF
3776 CONT2
SHORT1
U
(Refer to Functional Diagram)
OPERATIO
Main Control Loop
peak inductor current at which ICMP resets the RS latch is
determined by the voltage on the ITH pin, which is driven
by the output of the error amplifier (EAMP). The VFB pin
receives the output voltage feedback signal from an exter-
nal resistor divider. This feedback signal is compared to a
reference (either the internal 0.6V reference for controller
1 or the divided down VREF pin for CH2) by the EAMP.
The LTC3776 uses a constant frequency, current mode
architecture with the two controllers operating 180 de-
grees out of phase. During normal operation, the top
external P-channel power MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the current comparator (ICMP) resets the latch. The
3776fa
9
LTC3776
U
(Refer to Functional Diagram)
OPERATIO
When the load current increases, it causes a slight
decrease in VFB relative to the reference, which in turn
causes the ITH voltage to increase until the average induc-
tor current matches the new load current. While the top
P-channel MOSFET is off, the bottom N-channel MOSFET
is turned on until the beginning of the next cycle.
Short-Circuit Protection
When an output is shorted to ground, the switching
frequency of that controller is reduced to 1/5 of the normal
operating frequency.
Theshort-circuitthresholdonVFB2 isbasedonthesmaller
of 0.12V and a fraction of the voltage on the VREF pin. This
also allows VOUT2 to start up and track VOUT1 more easily.
Shutdown, Soft-Start and Tracking Start-Up
(RUN/SS and TRACK Pins)
Note that if VOUT1 is truly short-circuited (VOUT1 = VFB1
=
0V), then the LTC3776 will try to regulate VOUT2 to 0V if
VOUT1 is connected to the VREF pin.
The LTC3776 is shut down by pulling the RUN/SS pin low.
In shutdown, all controller functions are disabled and the
chip draws only 9μA. The TG outputs are held high (off)
and the BG outputs low (off) in shutdown. Releasing
RUN/SS allows an internal 0.7μA current source to charge
up the RUN/SS pin. When the RUN/SS pin reaches 0.65V,
the LTC3776’s two controllers are enabled.
Output Overvoltage Protection
As further protection, the overvoltage comparator (OV)
guardsagainsttransientovershoots,aswellasothermore
serious conditions that may overvoltage the output. When
the feedback voltage on the VFB pin has risen 13.33%
above itsresolutionpoint,theexternalP-channelMOSFET
is turned off and the N-channel MOSFET is turned on until
the overvoltage is cleared.
The start-up of VOUT1 is controlled by the LTC3776’s
internal soft-start. During soft-start, the error amplifier
EAMP compares the feedback signal VFB1 to the internal
soft-startramp(insteadofthe0.6Vreference),whichrises
linearly from 0V to 0.6V in about 1ms. This allows the
output voltage to rise smoothly from 0V to its final value,
while maintaining control of the inductor current.
Frequency Selection and Phase-Locked Loop
(PLLLPF and SYNC/SSEN Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increasesefficiencybyreducingMOSFETswitchinglosses,
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage.
The 1ms soft-start time can be increased by connecting
the optional external soft-start capacitor CSS between the
RUN/SS and SGND pins. As the RUN/SS pin continues to
rise linearly from approximately 0.65V to 1.25V (being
charged by the internal 0.7μA current source), the EAMP
regulates the VFB1 proportionally linearly from 0V to 0.6V.
The switching frequency of the LTC3776’s controllers can
be selected using the PLLLPF pin.
The start-up of VOUT2 is controlled by the voltage on the
VREF pin. Typically, VOUT1 is connected to the VREF pin to
IftheSYNC/SSENpinistiedtoground,thePLLLPFpincanbe
floated, tied to VIN, or tied to SGND to select 550kHz, 750kHz,
or 300kHz constant frequency operation, respectively.
allow the start-up of VOUT2 to “track” that of 1/2 VOUT1
.
Note that if either VOUT1 or VOUT2 is less than 90% (lower
PGOOD threshold) of its regulation point (in either a
startup or short-circuit condition), then channel one’s
inductor current is not allowed to reverse (i.e., discontinu-
ous operation is forced). This is to prevent a minimum on-
time condition during startup.
A phase-locked loop (PLL) is available on the LTC3776 to
synchronize the internal oscillator to an external clock
source that connected to the SYNC/SSEN pin. In this case,
a series RC should be connected between the PLLLPF pin
and SGND to serve as the PLL’s loop filter. The LTC3776
3776fa
10
LTC3776
U
(Refer to Functional Diagram)
OPERATIO
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of controller 1’s external P-channel
MOSFET to the rising edge of the synchronizing signal.
Thus, the turn-on of controller 2’s external P-channel
MOSFET is 180 degrees out of phase with the rising edge
of the external clock source.
enable spread spectrum operation (see Spread Spectrum
Operation section).
Spread Spectrum Operation
Switching regulators can be particularly troublesome in
applications where electromagnetic interference (EMI) is
a concern. Switching regulators operate on a cycle-by-
cycle basis to transfer power to an output. In most cases,
the frequency of operation is either fixed or is a constant
based on the output load. This method of conversion
creates large components of noise at the frequency of
operation (fundamental) and multiples of the operating
frequency (harmonics). Figures 1a and 1b depict the
The typical capture range of the LTC3776’s phase-locked
loop is from approximately 200kHz to 1MHz, with a
guarantee over all process variations and temperature to
be between 250kHz and 850kHz. In other words, the
LTC3776’s PLL is guaranteed to lock to an external clock
source whose frequency is between 250kHz and 850kHz.
Alternatively, the SYNC/SSEN pin may be tied to VIN to
–10
–10
R
= 3kHz
R
= 30Hz
BW
BW
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
6
12
18
24
30
410
450
490
530
570
610
37361 F01a
FREQUENCY (MHz)
37361 F01b
FREQUENCY (kHz)
Figure 1a. Output Noise Spectrum of Conventional Buck
Switching Converter (LTC3776 with Spread Spectrum
Disabled) Showing Fundamental and Harmonic Frequencies
Figure 1b. Zoom-In of Fundamental Frequency of Conventional
Buck Switching Converter
–10
–10
R
= 1kHz
BW
R
= 30Hz
BW
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
6
12
18
24
30
410
450
490
530
570
610
FREQUENCY (MHz)
37361 F01c
37361 F01d
FREQUENCY (kHz)
Figure 1c. Output Noise Spectrum of the LTC3776 Spread
Spectrum Buck Switching Converter. Note the Reduction in
Fundamental and Harmonic Peak Spectral Amplitude
Compared to Figure 1a.
Figure 1d. Zoom-In of Fundamental Frequency of the
LTC3776 Spread Spectrum Switching Converter. Note the
>20dB Reduction in Peak Amplitude and Spreading of the
Frequency Spectrum (Between Approximately 450kHz and
580kHz) Compared to Figure 1b.
3776fa
11
LTC3776
U
(Refer to Functional Diagram)
OPERATIO
output noise spectrum of a conventional buck switching
converter (1/2 of LTC3776 with spread spectrum opera-
tion disabled) with VIN = 5V, VOUT = 2.5V and IOUT = 2A.
whereA1isaconstantdeterminedbythestateoftheIPRG
pins. Floating the IPRG1 pin selects A1 = 1; tying IPRG to
VIN selects A1 = 5/3; tying IPRG1 to SGND selects A1 =
2/3. The maximum value of VITH1 is typically about 1.98V,
so the maximum sense voltage allowed across the exter-
nal P-channel MOSFET is 125mV, 85mV or 204mV for the
three respective states of the IPRG1 pin.
Unlikeconventionalbuckconverters,theLTC3776’sinter-
nal oscillator can be selected to produce a clock pulse
whose frequency is randomly varied between 450kHz and
580kHz by tying the SYNC/SSEN pin to VIN. This has the
benefit of spreading the switching noise over a range of
frequencies, thus significantly reducing the peak noise.
Figures 1c and 1d show the output noise spectrum of the
LTC3776 (with spread spectrum operation enabled) with
VIN = 5V, VOUT = 2.5V and IOUT = 1A. Note the significant
reduction in peak output noise (>20dBm).
When controller 2 is operating below 20% duty cycle, the
peak current sense voltage (between the SENSE2+ and
SW2pins)allowedacrosstheexternalP-channelMOSFET
is determined by:
A2 V
–1.3V
4.6
–1.3V
(
)
)
ITH2
ΔVSENSE(MAX)
ΔVSENSE(MAX)
=
=
,V
≥ 1.3V
< 1.3V
ITH2
A2 V
(
ITH2
Dropout Operation
,V
ITH2
5.4
Whentheinputsupplyvoltage(VIN)decreasestowardsthe
output voltage, the rate of change of the inductor current
while the external P-channel MOSFET is on (ON cycle)
decreases. ThisreductionmeansthattheP-channelMOS-
FET will remain on for more than one oscillator cycle if the
inductor current has not ramped up to the threshold set by
the EAMP on the ITH pin. Further reduction in the input
supply voltage will eventually cause the P-channel MOS-
FET to be turned on 100%; i.e., DC. The output voltage will
then be determined by the input voltage minus the voltage
drop across the P-channel MOSFET and the inductor.
where A is a constant determined by the state of the IPRG
pins. Floating the IPRG2 pin selects A2 = 1; tying IPRG2
to VIN selects A = 5/3; tying IPRG2 to SGND selects A2 =
2/3. The maximum value of VITH2 is typically about 1.98V,
so the maximum sense voltage allowed across the exter-
nal P-channel MOSFET is 147mV, 100mV or 245mV for
thethreerespectivestatesoftheIPRG2pin. Theminimum
value of VITH2 is typically about 0.7V, so the minimum
(most negative) peak sense voltage is –112mV, –75mV or
–188mV, respectively.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peak sense voltage by a scale factor given by the curve in
Figure 2.
Undervoltage Lockout
To prevent operation of the external MOSFETs below safe
inputvoltagelevels,anundervoltagelockoutisincorporated
intheLTC3776.Whentheinputsupplyvoltage(VIN)drops
below 2.3V, the external P- and N-channel MOSFETs and
allinternalcircuitryareturnedoffexceptfortheundervolt-
age block, which draws only a few microamperes.
110
100
90
80
70
60
50
40
30
20
10
0
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG1 and IPRG2 Pins)
When controller 1 is operating below 20% duty cycle, the
peak current sense voltage (between the SENSE1+ and
SW1pins)allowedacrosstheexternalP-channelMOSFET
is determined by:
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
A1 V
– 0.7V
10
(
)
ITH1
3776 F02
ΔVSENSE(MAX)1
=
Figure 2. Maximum Peak Current vs Duty Cycle
3776fa
12
LTC3776
U
(Refer to Functional Diagram)
OPERATIO
Thepeakinductorcurrentisdeterminedbythepeaksense
voltage and the on-resistance of the external P-channel
MOSFET:
proportional to IRMS2, meaning that actual power wasted
is reduced by a factor of 3.86.
The reduced input ripple current also means that less
power is lost in the input power path, which could include
batteries, switches, trace/connector resistances, and pro-
tection circuitry. Improvements in both conducted and
radiated EMI also directly accrue as a result of the reduced
RMS input current and voltage. Significant cost and board
footprint savings are also realized by being able to use
smaller, less expensive, lower RMS current-rated input
capacitors.
ΔVSENSE(MAX)
IPK
=
RDS(ON)
Power Good (PGOOD) Pin
A window comparator monitors both feedback voltages
and the open-drain PGOOD output pin is pulled low when
either or both feedback voltages are not within ±10% of
theirreferencevoltages. PGOODislowwhentheLTC3776
is shut down or in undervoltage lockout.
Single Phase
Dual Controller
2-Phase
Dual Controller
SW1 (V)
SW2 (V)
2-Phase Operation
Why the need for 2-phase operation? Until recently, con-
stant frequency dual switching regulators operated both
controllers in phase (i.e., single phase operation). This
means that both topside MOSFETs (P-channel) are turned
on at the same time, causing current pulses of up to twice
the amplitude of those from a single regulator to be drawn
from the input capacitor. These large amplitude pulses
increase the total RMS current flowing in the input capaci-
tor, requiring the use of larger and more expensive input
capacitors, and increase both EMI and power losses in the
input capacitor and input power supply.
I
I
L1
L2
I
IN
3776 F03
With2-phaseoperation,thetwocontrollersoftheLTC3776
are operated 180 degrees out of phase. This effectively
interleaves the current pulses coming from the topside
MOSFET switches, greatly reducing the time where they
overlap and add together. The result is a significant
reductioninthetotalRMScurrent,whichinturnallowsthe
use of smaller, less expensive input capacitors, reduces
shielding requirements for EMI and improves real world
operating efficiency.
Figure 3. Example Waveforms for a Single Phase
Dual Controller vs the 2-Phase LTC3776
Of course, the improvement afforded by 2-phase opera-
tion is a function of the relative duty cycles of the two
controllers, which in turn are dependent upon the input
supply voltage. Figure 4 depicts how the RMS input
current varies for single phase and 2-phase dual control-
lers with 2.5V and 1.8V outputs over a wide input voltage
range.
Figure 3 shows qualitatively example waveforms for a
single phase dual controller versus a 2-phase LTC3776
system. In this case, 2.5V and 1.8V outputs, each drawing
a load current of 2A, are derived from a 7V (e.g., a 2-cell
Li-Ion battery) input supply. In this example, 2-phase
operation would reduce the RMS input capacitor current
from 1.79ARMS to 0.91ARMS. While this is an impressive
reduction by itself, remember that power losses are
It can be readily seen that the advantages of 2-phase
operation are not limited to a narrow operating range, but
in fact extend over a wide region. A good rule of thumb for
mostapplicationsisthat2-phaseoperationwillreducethe
input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
3776fa
13
LTC3776
W U U
U
APPLICATIO S I FOR ATIO
2.0
inductor current is limited by the current threshold, set by
the voltage on the ITH pin of the current comparator. The
voltage on the ITH pin is internally clamped, which limits
1.8
SINGLE PHASE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
DUAL CONTROLLER
the maximum current sense threshold ΔVSENSE(MAX)
.
2-PHASE
DUAL CONTROLLER
The output current that the LTC3776 can provide is given
by:
ΔVSENSE(MAX)
IRIPPLE
IOUT(MAX)
=
–
V
V
= 2.5V/2A
= 1.8V/2A
OUT1
OUT2
RDS(ON)
2
2
6
8
9
3
4
5
7
10
A reasonable starting point is setting ripple current IRIPPLE
to be 40% of IOUT(MAX). Rearranging the above equation
yields:
INPUT VOLTAGE (V)
3776 F04
Figure 4. RMS Input Current Comparison
ΔVSENSE(MAX)
IOUT(MAX)
5
RDS(ON)(MAX) = •
6
The typical LTC3776 application circuit is shown in
Figure 11. External component selection for each of the
LTC3776’s controllers is driven by the load requirement
and begins with the selection of the inductor (L) and the
power MOSFETs (MP and MN).
for Duty Cycle < 20%.
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of RDS(ON) to provide the required
amount of load current:
Power MOSFET Selection
Each of the LTC3776’s two controllers requires two exter-
nal power MOSFETs: a P-channel MOSFET for the topside
(main) switch and an N-channel MOSFET for the bottom
(synchronous)switch.Importantparametersforthepower
MOSFETs are the breakdown voltage VBR(DSS) , threshold
voltage VGS(TH), on-resistance RDS(ON) , reverse transfer
capacitance CRSS, turn-off delay tD(OFF) and the total gate
charge QG.
ΔVSENSE(MAX)
IOUT(MAX)
5
6
RDS(ON)(MAX) = • SF •
whereSFisascalefactorwhosevalueisobtainedfromthe
curve in Figure 2.
These must be further derated to take into account the
significant variation in on-resistance with temperature.
Thefollowingequationisagoodguidefordeterminingthe
required RDS(ON)MAX at 25°C (manufacturer’s specifica-
tion), allowing some margin for variations in the LTC3776
and external component values:
Thegatedrivevoltageistheinputsupplyvoltage.Sincethe
LTC3776 is designed for operation down to low input
voltages, a sublogic level MOSFET (RDS(ON) guaranteed at
VGS = 2.5V) is required for applications that work close to
this voltage. When these MOSFETs are used, make sure
that the input supply to the LTC3776 is less than the abso-
lute maximum MOSFET VGS rating, which is typically 8V.
ΔVSENSE(MAX)
IOUT(MAX) • ρT
5
6
RDS(ON)(MAX) = • 0.9 • SF •
The ρT is a normalizing term accounting for the tempera-
ture variation in on-resistance, which is typically about
0.4%/°C, as shown in Figure 5. Junction to case tempera-
ture TJC is about 10°C in most applications. For a maxi-
mum ambient temperature of 70°C, using ρ80°C ~ 1.3 in
the above equation is a reasonable choice.
The P-channel MOSFET’s on-resistance is chosen based
on the required load current. The maximum average
output load current IOUT(MAX) is equal to the peak inductor
current minus half the peak-to-peak ripple current IRIPPLE
.
TheLTC3776’scurrentcomparatormonitorsthedrain-to-
source voltage VDS of the P-channel MOSFET, which is
sensed between the SENSE+ and SW pins. The peak
3776fa
14
LTC3776
W U U
APPLICATIO S I FOR ATIO
U
2.0
1.5
1.0
0.5
0
Reasonable starting criteria for selecting the P-channel
MOSFET are that it must typically have a gate charge (QG)
less than 25nC to 30nC (at 4.5VGS) and a turn-off delay
(tD(OFF)) of less than approximately 140ns. However, due
to differences in test and specification methods of various
MOSFET manufacturers, and in the variations in QG and
t
D(OFF)withgatedrive(VIN)voltage,theP-channelMOSFET
ultimately should be evaluated in the actual LTC3776
application circuit to ensure proper operation.
–50
50
100
150
0
Shoot-through between the P-channel and N-channel
MOSFETs can most easily be spotted by monitoring the
input supply current. As the input supply voltage in-
creases,iftheinputsupplycurrentincreasesdramatically,
then the likely cause is shoot-through. Note that some
MOSFETsthatdonotworkwellathighinputvoltages(e.g.,
VIN > 5V) may work fine at lower voltages (e.g., 3.3V).
Table 1 shows a selection of P-channel MOSFETs from
different manufacturers that are known to work well in
LTC3776 applications.
JUNCTION TEMPERATURE (°C)
3776 F07
Figure 5. RDS(ON) vs Temperature
The power dissipated in the top and bottom MOSFETs
strongly depends on their respective duty cycles and load
current. When the LTC3776 is operating in continuous
mode, the duty cycles for the MOSFETs are:
VOUT
V
IN
Top P-Channel Duty Cycle =
Selecting the N-channel MOSFET is typically easier, since
for a given RDS(ON), the gate charge and turn-on and turn-
off delays are much smaller than for a P-channel MOSFET.
V – VOUT
IN
Bottom N-Channel Duty Cycle =
V
IN
The MOSFET power dissipations at maximum output
current are:
Table 1. Selected P-Channel MOSFETs Suitable for LTC3776
Applications
PART
NUMBER
MANUFACTURER
TYPE
PACKAGE
VOUT
2
PTOP
=
•IOUT(MAX)2 •ρT •RDS(ON) + 2•V
IN
Si7540DP
Siliconix
Complementary
P/N
PowerPak
SO-8
V
IN
•IOUT(MAX) •CRSS • fOSC
V – VOUT
Si9801DY
FDW2520C
FDW2521C
Siliconix
Fairchild
Fairchild
Complementary
P/N
SO-8
P
BOT
=
•IOUT(MAX)2 •ρT •RDS(ON)
IN
Complementary
P/N
TSSOP-8
TSSOP-8
V
IN
Both MOSFETs have I2R losses and the PTOP equation
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The bottom MOSFET losses
are greatest at high input voltage or during a short circuit
when the bottom duty cycle is nearly 100%.
TheLTC3776utilizesanonoverlapping,antishoot-through
gate drive control scheme to ensure that the P- and
N-channel MOSFETs are not turned on at the same time.
To function properly, the control scheme requires that the
MOSFETs used are intended for DC/DC switching applica-
tions. Many power MOSFETs, particularly P-channel
MOSFETs, are intended to be used as static switches and
therefore are slow to turn on or off.
Complementary
P/N
Si3447BDV
Si9803DY
FDC602P
Siliconix
Siliconix
Fairchild
Fairchild
Fairchild
Fairchild
Fairchild
Hitachi
Single P
Single P
Single P
Single P
Single P
Dual P
TSOP-6
SO-8
TSOP-6
TSOP-6
TSOP-6
TSSOP-8
SO-8
FDC606P
FDC638P
FDW2502P
FDS6875
Dual P
HAT1054R
NTMD6P02R2-D
Dual P
SO-8
On Semi
Dual P
SO-8
3776fa
15
LTC3776
W U U
U
APPLICATIO S I FOR ATIO
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
Operating Frequency and Synchronization
The choice of operating frequency, fOSC, is a trade-off
between efficiency and component size. Low frequency
operationimprovesefficiencybyreducingMOSFETswitch-
ing losses, both gate charge loss and transition loss.
However, lowerfrequencyoperationrequiresmoreinduc-
tance for a given amount of ripple current.
V – VOUT VOUT
IN
L ≥
•
fOSC •IRIPPLE
V
IN
Inductor Core Selection
The internal oscillator for each of the LTC3776’s control-
lersrunsatanominal550kHzfrequencywhenthePLLLPF
pin is left floating and the SYNC/SSEN pin is tied to GND.
Pulling the PLLLPF to VIN selects 750kHz operation;
pulling the PLLLPF to GND selects 300kHz operation.
Once the inductance value is determined, the type of
inductormustbeselected. Actualcorelossisindependent
of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance in-
creases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Alternatively,theLTC3776willphase-locktoaclocksignal
applied to the SYNC/SSEN pin with a frequency between
250kHz and 850kHz (see Phase-Locked Loop and Fre-
quency Synchronization).
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
When spread spectrum operation is enabled (SYNC/
SSEN = VIN), the frequency of the LTC3776 is randomly
varied over the range of frequencies between 450kHz and
580kHz. In this case, a capacitor (1nF to 4.7nF) should be
connected between the FREQ pin and SGND to smooth
out the changes in frequency. This not only provides a
smoother frequency spectrum but also ensures that the
switching regulator remains stable by preventing abrupt
changes in frequency. A value of 2200pF is suitable in
most applications.
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar characteristics. The choice of which style
inductor to use mainly depends on the price vs size
requirements and any radiated field/EMI requirements.
New designs for surface mount inductors are available
from Coiltronics, Coilcraft, Toko and Sumida.
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency fOSC directly determine the
inductor’s peak-to-peak ripple current:
VOUT ⎛ V – VOUT
⎞
⎟
IN
IRIPPLE
=
⎜
V
IN
⎝ fOSC •L ⎠
Schottky Diode Selection (Optional)
The Schottky diodes D1 and D2 in Figure 16 conduct
current during the dead time between the conduction of
the power MOSFETs . This prevents the body diode of the
bottom N-channel MOSFET from turning on and storing
charge during the dead time, which could cost as much as
1% in efficiency. A 1A Schottky diode is generally a good
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
Kool Mμ is a registered trademark of Magnetics, Inc.
3776fa
16
LTC3776
W U U
APPLICATIO S I FOR ATIO
U
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
currentpulsesrequiredthroughtheinputcapacitor’sESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Also, the input protection fuse re-
sistance,batteryresistance,andPCboardtraceresistance
losses are also reduced due to the reduced peak currents
in a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source imped-
ance of the power supply/battery is included in the effi-
ciency testing. The sources of the P-channel MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may pro-
duce undesirable voltage and current resonances at VIN.
size for most LTC3776 applications, since it conducts a
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance. This diode may be omitted if the efficiency
loss can be tolerated.
CIN and COUT Selection
The selection of CIN is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The control-
ler with the highest (VOUT)(IOUT) product needs to be used
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output cur-
rent drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
A small (0.1μF to 1μF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3776, is also
suggested. A 10Ω resistor placed between CIN (C1) and
the VIN pin provides further isolation between the two
channels.
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (VOUT)/(VIN). To
preventlargevoltagetransients, alowESRcapacitorsized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (ΔVOUT) is approximated by:
1/2
]
IMAX
V
IN
CIN Required IRMS
≈
V
OUT)(
V – V
IN OUT
(
[
)
⎛
⎝
1
⎞
ΔVOUT ≈ IRIPPLE ESR +
⎜
⎟
⎠
8fCOUT
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
usedfordesignbecauseevensignificantdeviationsdonot
offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design.DuetothehighoperatingfrequencyoftheLTC3776,
ceramic capacitors can also be used for CIN. Always
consult the manufacturer if there is any question.
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
Setting Output Voltage
The LTC3776’s channel 1 output voltage is set by an
external feedback resistor divider carefully placed across
the output, as shown in Figure 6. The regulated output
voltage is determined by:
⎛
⎝
RB ⎞
RA ⎠
The benefit of the LTC3776 2-phase operation can be cal-
culated by using the equation above for the higher power
VOUT1 = 0.6V • 1+
⎜
⎟
3776fa
17
LTC3776
W U U
U
APPLICATIO S I FOR ATIO
During soft-start, the start-up of VOUT1 is controlled by
slowlyrampingthepositivereferencetotheerroramplifier
from 0V to 0.6V, allowing VOUT1 to rise smoothly from 0V
toitsfinalvalue. Thedefaultinternalsoft-starttimeis1ms.
This can be increased by placing a capacitor between the
RUN/SSpinandSGND. Inthiscase, thesoft-starttimewill
be approximately:
Channel2’soutputvoltageissetto1/2VREF byconnecting
the VFB2 pin to VOUT2. To improve the frequency response,
a feed-forward capacitor, CFF, may be used. Great care
should be taken to route the VFB line away from noise
sources, such as the inductor or the SW line.
V
OUT1
V
OUT2
C
R
FF
B
A
600mV
0.7μA
LTC3776
tSS1 = CSS
•
V
V
FB2
FB1
R
VREF Pin
3776 F06
Figure 6. Setting Output Voltage
The regulation of VOUT2 is controlled by the voltage on the
VREF pin. Normally this pin is used in DDR memory
termination applications so that VOUT2 tracks 1/2 VOUT1 as
shown in Figure 8.
Run/Soft Start Function
The RUN/SS pin is a dual purpose pin that provides the
optional external soft-start function and a means to shut
down the LTC3776.
V
OUT1
V
OUT2
LTC3776
R1B
V
V
V
FB2
FB1
PullingtheRUN/SSpinbelow0.65VputstheLTC3776into
a low quiescent current shutdown mode (IQ = 9μA). If
RUN/SS has been pulled all the way to ground, there will
beadelaybeforetheLTC3776comesoutofshutdownand
is given by:
R1A
REF
3776 F08
Figure 8. Using the VREF Pin (VOUT2
is Regulated to 1/2 VREF = 1/2VOUT1
)
CSS
tDELAY = 0.65V •
= 0.93s/μF •CSS
0.7μA
Phase-Locked Loop and Frequency Synchronization
This pin can be driven directly from logic as shown in
Figure 7. Diode D1 in Figure 7 reduces the start delay but
allows CSS to ramp up slowly providing the soft-start
function. This diode (and capacitor) can be deleted if the
external soft-start is not needed.
The LTC3776 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the external
P-channel MOSFET of controller 1 to be locked to the
rising edge of an external clock signal applied to the
SYNC/SSEN pin. The turn-on of controller 2’s external
P-channel MOSFET is thus 180 degrees out of phase with
theexternalclock. Thephasedetectorisanedgesensitive
digital type that provides zero degrees phase shift
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics of
the external clock.
3.3V OR 5V
RUN/SS
RUN/SS
D1
C
SS
C
SS
3776 F07
Figure 7. RUN/SS Pin Interfacing
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
3776fa
18
LTC3776
W U U
APPLICATIO S I FOR ATIO
U
oscillators are identical. At the stable operating point, the
phase detector output is high impedance and the filter
capacitor CLP holds the voltage.
frequency, when there is a clock signal applied to SYNC/
SSEN, is shown in Figure 9 and specified in the Electrical
Characteristics table. Note that the LTC3776 can only be
synchronized to an external clock whose frequency is
within range of the LTC3776’s internal VCO, which is
nominally 200kHz to 1MHz. This is guaranteed, over
temperatureandprocessvariations,tobebetween250kHz
and 850kHz. A simplified block diagram is shown in
Figure 10.
The loop filter components, CLP and RLP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01μF.
1400
Typically,theexternalclock(onSYNC/SSENpin)inputhigh
threshold is 1.6V, while the input low threshold is 1.2V.
1200
1000
800
600
400
200
0
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN
0V
SYNC/SSEN PIN
GND
FREQUENCY
300kHz
550kHz
Floating
GND
0
0.5
1
1.5
2
2.4
V
GND
750kHz
IN
PLLLPF PIN VOLTAGE (V)
3776 F09
RC Loop Filter
Clock Signal
Phase-Locked to External Clock
Figure 9. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
Capacitor to
GND
V
Spread Spectrum Operation
450kHz to 550kHz
IN
2.4V
R
LP
Low Supply Operation
C
LP
Although the LTC3776 can function down to below 2.4V,
the maximum allowable output current is reduced as VIN
decreases below 3V. Figure 11 shows the amount of
changeasthesupplyisreduceddownto2.4V. Alsoshown
PLLLPF
SYNC/
SSEN
DIGITAL
PHASE/
FREQUENCY
DETECTOR
EXTERNAL
OSCILLATOR
OSCILLATOR
is the effect on VREF
.
105
V
REF
3776 F10
100
Figure 10. Phase-Locked Loop Block Diagram
95
90
MAXIMUM
SENSE VOLTAGE
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
PLLLPFpin. Iftheexternalandinternalfrequenciesarethe
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage on the PLLLPF pin is adjusted until
the phase and frequency of the internal and external
85
80
75
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
3776 F11
Figure 11. Line Regulation of VREF and
Maximum Sense Voltage for Low Input Supply
3776fa
19
LTC3776
W U U
U
APPLICATIO S I FOR ATIO
Minimum On-Time Considerations
typically much larger than the DC supply current. In
continuous mode, IGATECHG = f • QP.
Minimumon-time,tON(MIN),isthesmallestamountoftime
inwhichtheLTC3776iscapableofturningthetopP-channel
MOSFET on and then off. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. Low duty cycle and high frequency applica-
tions may approach the minimum on-time limit and care
should be taken to ensure that:
3) I2R losses are calculated from the DC resistances of the
MOSFETs and inductor. In continuous mode, the aver-
age output current flows through L but is “chopped”
between the top P-channel MOSFET and the bottom
N-channel MOSFET. The MOSFET RDS(ON)s multiplied
by duty cycle can be summed with the resistance of L
to obtain I2R losses.
VOUT
tON(MIN)
<
4) Transition losses apply to the top external P-channel
MOSFET and increase with higher operating frequen-
cies and input voltages. Transition losses can be esti-
mated from:
fOSC • V
IN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3776 will regulate by
overvoltage protection. The minimum on-time for the
LTC3776 is typically about 200ns. However, as the peak
sense voltage (IL(PEAK) • RDS(ON)) decreases, the mini-
mum on-time gradually increases up to about 250ns.
Transition Loss = 2 (VIN)2IO(MAX) RSS
(f)
C
Other losses, including CIN and COUT ESR dissipative
lossesandinductorcorelosses,generallyaccountforless
than 2% total additional loss.
Efficiency Considerations
Checking Transient Response
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (ΔILOAD)(ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or dis-
chargeCOUT, whichgeneratesafeedbackerrorsignal. The
regulator loop then returns VOUT to its steady-state value.
Duringthisrecoverytime,VOUT canbemonitoredforover-
shoot or ringing. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
Efficiency = 100% – (L1 + L2 + L3 + …)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3776 circuits: 1) LTC3776 DC bias current,
2) MOSFET gate charge current, 3) I2R losses, and
4) transition losses.
The ITH series RC-CC filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The ITH exter-
nal components shown in the Typical Application on the
front page of this data sheet will provide an adequate
starting point for most applications. The values can be
modified slightly (from 0.2 to 5 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type and
value have been determined. The output capacitors need
to be decided upon because the various types and values
1) The VIN (pin) current is the DC supply current, given in
the electrical characteristics, excluding MOSFET driver
currents. VIN current results in a small loss that in-
creases with VIN.
2) MOSFETgatechargecurrentresultsfromswitchingthe
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from SENSE+ to ground.
The resulting dQ/dt is a current out of SENSE+, which is
3776fa
20
LTC3776
W U U
APPLICATIO S I FOR ATIO
U
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1μs to 10μs will produce output
voltage and ITH pin waveforms that will give a sense of the
overall loop stability. The gain of the loop will be increased
by increasing RC, and the bandwidth of the loop will be
increased by decreasing CC. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
The power grounds consist of the (–) terminal of the input
and output capacitors and the source of the N-channel
MOSFET. Eachchannelshouldhaveitsownpowerground
for its power loop (as described in (1) above). The power
grounds for the two channels should connect together at
a common point. It is most important to keep the ground
paths with high switching currents away from each other.
The PGND pins on the LTC3776 IC should be shorted
together and connected to the common power ground
connection (away from the switching currents).
3) Put the feedback resistors close to the VFB pins. The
trace connecting the top feedback resistor (RB) to the
outputcapacitorshouldbeaKelvintrace.TheITHcompen-
sation components should also be very close to the
LTC3776.
4) The current sense traces (SENSE+ and SW) should be
Kelvin connections right at the P-channel MOSFET source
and drain.
A second, more severe transient is caused by switching in
loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(CLOAD).
Thus a 10μF capacitor would require a 250μs rise time,
limiting the charging current to about 200mA.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-signal
components, especially the opposite channels feedback
resistors, ITH compensation components and the current
sense pins (SENSE+ and SW).
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3776. Theseitemsareillustratedinthelayoutdiagram
of Figure 12. Figure 13 depicts the current waveforms
present in the various branches of the 2-phase dual
regulator.
+
C
OUT1
V
OUT1
L1
LTC3776EGN
1
2
24
23
22
21
20
19
18
17
16
15
14
13
+
SENSE1
SW1
PGND
BG1
IPRG1
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small as
possible and isolated as much as possible from the power
loop of the other channel. Ideally, the drains of the P- and
N-channel FETs should be connected close to one another
with an input capacitor placed across the FET sources
(from the P-channel source to the N-channel source) right
attheFETs.Itisbettertohavetwoseparate,smallervalued
input capacitors (e.g., two 10μF—one for each channel)
than it is to have a single larger valued capacitor (e.g.,
22μF) that the channels share with a common connection.
3
MN1
VIN1
MP1
V
FB1
TH1
C
4
SYNC/SSEN
TG1
I
5
IPRG2
PLLLPF
SGND
C
VIN
6
PGND
TG2
V
IN
7
C
8
VIN2
RUN/SS
BG2
V
V
V
IN
9
MN2
MP2
REF
FB2
TH2
10
11
12
PGND
+
SENSE2
I
SW2
PGOOD
L2
+
V
OUT2
C
OUT2
3776 F12
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor
dividers, ITH compensation networks and the SGND pin.
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 12. LTC3776 Layout Diagram
3776fa
21
LTC3776
APPLICATIO S I FOR ATIO
W U U
U
MP1
L1
V
OUT1
+
C
OUT1
R
L1
MN1
V
IN
R
IN
+
C
IN
MP2
L2
V
OUT2
+
C
OUT2
R
L2
MN2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH
3776 F13
Figure 13. Branch Current Waveforms
3776fa
22
LTC3776
U
TYPICAL APPLICATIO S
R
R
FB1B
187k
FB1A
59k
L1
1.5μH
C
ITH1A
V
2.5V
5A
MP1
DDQ
22
23
24
1
2
3
100pF
21
20
19
18
17
16
15
+
SW1
IPRG1
SENSE1
PGND
BG1
SYNC/SSEN
TG1
MN1
Si7540DP
V
FB1
C
OUT1
I
TH1
100μF
R
ITH1
IPRG2
PLLLPF
SGND
C
ITH1
22k
PGND
TG2
1000pF
4
V
IN
5V
R
10Ω
LTC3776EUF
IN
VIN
5
14
C
IN
V
RUN/SS
10μF
×2
13
12
11
MN2
Si7540DP
C
OUT2
100μF
BG2
9
7
8
6
C
ITH2
PGND
PGOOD
V
TT
C
2.2nF
VIN
+
1.25V
V
FB2
SENSE2
1μF
MP2
±5A
I
L2
1.5μH
TH2
10
R
ITH2
V
REF
SW2
6.2k
PGND
25
C
10nF
SS
C
ITH2B
330pF
3776 F14
Figure 14. 2-Phase, 550kHz, DDR Memory Supplies
3776fa
23
LTC3776
TYPICAL APPLICATIO S
U
R
R
FB1B
187k
FB1A
59k
L1
2.2μH
MP1
FDC638P
C
ITH1A
V
2.5V
2A
DDQ
22
23
24
1
2
3
100pF
21
20
19
18
17
16
15
+
SW1
IPRG1
SENSE1
PGND
BG1
SYNC/SSEN
TG1
MN1
FDC637N
V
FB1
C
OUT1
I
TH1
47μF
R
ITH1
IPRG2
PLLLPF
SGND
C
ITH1
22k
PGND
TG2
1000pF
4
V
IN
3.3V
R
10Ω
LTC3776EUF
IN
VIN
5
14
V
RUN/SS
C
IN
22μF
C
13
12
11
OUT2
MN2
FDC637N
BG2
47μF
9
7
8
6
C
ITH2
PGND
PGOOD
V
TT
C
2.2nF
VIN
+
1.25V
V
SENSE2
1μF
FB2
MP2
FDC638P
±2A
I
L2
2.2μH
TH2
10
R
ITH2
V
SW2
REF
6.2k
PGND
25
C
10nF
SS
C
ITH2A
330pF
3776 F15
L1, L2: VISHAY IHLP-2525CZ-01
Figure 15. 2-Phase, 750kHz, DDR Memory Supplies with Ceramic Output Capacitors
3776fa
24
LTC3776
U
TYPICAL APPLICATIO S
C
FF1
100pF
R
R
FB1B
FB1A
59k
187k
CLK IN
MP1
L1
C
ITH1
1.5μH
V
2.5V
4A
DDQ
R
ITH1
15k
SW1
1
220pF
24
23
22
21
20
19
18
+
SW1
IPRG1
SENSE1
2
3
4
5
6
7
PGND
BG1
SYNC/SSEN
TG1
MN1
Si7540DP
D1
V
FB1
+
C
C
LP
OUT1
I
TH1
R
10nF
LP
150μF
IPRG2
PLLLPF
SGND
15k
PGND
TG2
V
IN
3.3V
R
10Ω
LTC3776EGN
IN
VIN
5
17
V
RUN/SS
C
IN
22μF
16
15
14
MN2
D2
C
BG2
OUT2
12
10
11
9
C
Si7540DP
ITH2
+
150μF
PGND
PGOOD
V
TT
C
220pF
VIN
+
1.25V
V
SENSE2
1μF
FB2
MP2
SW2
±4A
I
L2
1.5μH
TH2
13
R
ITH2
V
SW2
REF
15k
3736 F16
C
, C
: SANYO 4TPB150MC
OUT1 OUT2
D1, D2: OPTIONAL SCHOTTKY DIODES
L1, L2: VISHAY IHLP-2525CZ-01
Figure 16. 2-Phase, Synchronizable, DDR Memory Supplies
3776fa
25
LTC3776
U
PACKAGE DESCRIPTIO
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.45 ± 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.115
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
0.75 ± 0.05
4.00 ± 0.10
(4 SIDES)
TYP
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
2
2.45 ± 0.10
(4-SIDES)
(UF24) QFN 0105
0.200 REF
0.25 ± 0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3776fa
26
LTC3776
U
PACKAGE DESCRIPTIO
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.033
(0.838)
REF
24 23 22 21 20 19 18 17 16 15 14 13
.045 ±.005
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.254 MIN
.150 – .165
1
2
3
4
5
6
7
8
9 10 11 12
.0165 ± .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
(0.38 ± 0.10)
.0532 – .0688
(1.35 – 1.75)
× 45°
.004 – .0098
(0.102 – 0.249)
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN24 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3776fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC3776
U
TYPICAL APPLICATIO
2-Phase, Spread Spectrum, DDR Memory Supplies with Ceramic Output Capacitors
R
FB1A
59k
R
FB1B
187k
C
ITH1A
100pF
L1
2.2μH
MP1
FDC638P
V
2.5V
2A
DDQ
22
23
24
1
2
3
21
20
19
18
17
16
15
+
SW1
IPRG1
SENSE1
C
ITH1
1000pF
PGND
BG1
SYNC/SSEN
TG1
R
22k
ITH1
MN1
FDC637N
V
FB1
C
OUT1
I
TH1
47μF
IPRG2
PLLLPF
SGND
2200pF
PGND
TG2
4
V
IN
3.3V
R
VIN
10Ω
LTC3776EUF
IN
5
14
V
RUN/SS
C
IN
22μF
C
13
12
11
OUT2
MN2
FDC637N
BG2
47μF
9
7
8
6
C
ITH2
2.2nF
PGND
PGOOD
V
TT
C
VIN
1μF
+
1.25V
V
SENSE2
FB2
MP2
FDC638P
±2A
I
L2
2.2μH
TH2
10
R
ITH2
6.2k
V
SW2
REF
PGND
25
C
10nF
SS
C
ITH2A
330pF
3776 TA02
L1, L2: VISHAY IHLP-2525CZ-01
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1735
High Efficiency Synchronous Step-Down Controller
Burst Mode Operation, 16-Pin Narrow SSOP, Fault Protection,
3.5V ≤ V ≤ 36V
IN
LTC1772
LTC1778
Constant Frequency Current Mode Step-Down
DC/DC Controller
2.5V ≤ V ≤ 9.8V, I
Up to 4A, SOT-23 Package, 550kHz
IN
OUT
No R
TM Synchronous Step-Down Controller
Current Mode Operation Without Sense Resistor,
Fast Transient Response, 4V ≤ V ≤ 36V
SENSE
IN
LTC2923
LTC3411
Power Supply Tracking Controller
Controls Up to Three Supplies, 10-Lead MSOP
1.25A (I ), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, V : 2.5V to 5.5V, V
= 0.8V, I = 60μA,
Q
OUT
IN
OUT
I
= <1μA, MS Package
SD
LTC3412
2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
SD
= 0.8V, I = 60μA,
Q
OUT
IN
OUT
I
= <1μA, TSSOP-16E Package
LTC3413
LTC3701
LTC3708
3A Monolithic DDR Memory Termination Regulator
±3A Output Current, 2.25V ≤ V ≤ 5.5V
IN
2-Phase, Low Input Voltage Dual Step-Down DC/DC Controller 2.5V ≤ V ≤ 9.8V, 550kHz, PGOOD, PLL, 16-Lead SSOP
IN
Fast 2-Phase, No R
Output Tracking
Buck Controller with
Constant On-Time Dual Controller, V Up to 36V, Very Low
SENSE
IN
Duty Cycle Operation, 5mm × 5mm QFN Package
LTC3717
High Power DDR Memory Termination Regulator
4V ≤ V ≤ 36V, V
Tracks V or V , I
from 1A to 20A
IN
OUT
IN
REF OUT
LTC3728/LTC3728L Dual, 550kHz, 2-Phase Synchronous Step-Down
Switching Regulator
Constant Frequency, V to 36V, 5V and 3.3V LDOs,
IN
5mm × 5mm QFN or 28-Lead SSOP
LTC3736
LTC3736-1
LTC3737
LTC3831
Dual, 2-Phase, No R
, Synchronous Controller
, Synchronous Controller
, Controller
V : 2.75 to 9.8V, I
up to 5A, 4mm x 4mm QFN Package
OUT
SENSE
IN
with Output Tracking
Dual, 2-Phase, No R
with Spread Spectrum
V : 2.75 to 9.8V, Spread Spectrum Operation, Output Voltage
SENSE
IN
Tracking, 4mm x 4mm QFN Package
Dual, 2-Phase, No R
with Output Tracking
V : 2.75 to 9.8V, I up to 5A, 4mm x 4mm QFN Package
IN OUT
SENSE
High Power DDR Memory Termination Regulator
is a trademark of Linear Technology Corporation.
V
Tracks 1/2 V or V , 3V ≤ V ≤ 8V, I
from 1A to 20A
OUT
IN
REF
IN
OUT
No R
SENSE
3776fa
LT 0807 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
相关型号：
LTC3776EUF#PBF
LTC3776 - Dual 2-Phase, No RSENSE Synchronous Controller for DDR/QDR Memory Termination; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C
Linear
LTC3776EUF#TR
LTC3776 - Dual 2-Phase, No RSENSE Synchronous Controller for DDR/QDR Memory Termination; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C
Linear
LTC3778EF#PBF
LTC3778 - Wide Operating Range, No RSENSE Step-Down Controller; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C
Linear
LTC3778EF#TR
LTC3778 - Wide Operating Range, No RSENSE Step-Down Controller; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C
Linear
LTC3778EF#TRPBF
LTC3778 - Wide Operating Range, No RSENSE Step-Down Controller; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C
Linear
LTC3779HFE#PBF
LTC3779 - 150V VIN and VOUT Synchronous 4-Switch Buck-Boost Controller; Package: TSSOP; Pins: 38; Temperature Range: -40°C to 125°C
Linear
LTC3779IFE#PBF
LTC3779 - 150V VIN and VOUT Synchronous 4-Switch Buck-Boost Controller; Package: TSSOP; Pins: 38; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明