LTC3779_技术文档

LTC7106

A 7-Bit Current DAC with

PMBus Interface

FEATURES

DESCRIPTION

The LTC^®7106 is a precision, PMBus controlled, bidi-

rectional current digital-to-analog converter that adjusts

n

0.8% I

Positive Output Current Accuracy

DAC

(Over Temp)

n

1.5% I

Negative Output Current Accuracy

the output voltage of any conventional V referenced

DAC

FB

(Over Temp)

regulator. The LTC7106 can work with the vast majority

of power management controllers or regulators to enable

digital control of the output voltage. Internal power-on

reset circuitry keeps the DAC output current at zero

(high impedance IDAC) until a valid write takes place.

Features include a range bit for easy interfacing to almost

any impedance resistor divider, and an open-drain GPO

output for controlling the Run or Enable pin of the DC/

DC regulator. For most applications, the current DAC error

is significantly attenuated with proper design. See more

2

n

PMBus/I C Compliant Serial Interface

Input Voltage Range: 2.5V to 5.5V

High Impedance at IDAC Output When Disabled

Wide IDAC Operation Voltage (0.4V to 2.0V)

7-Bit Programmable DAC Output Current for DC/DC

V

Control

OUT

n

Wide Range IDAC Output Current: 16μA to 256μA

Programmable Slew Rate: 500ns ~ 3ms per Bit

Available in a 10-Lead (3mm × 2mm) DFN Package

detailaboutV

accuracyintheApplicationsInformation

OUT

section of this data sheet. The LTC7106 is supported by

the ADI LTpowerPlay^®development tool with graphical

user interface (GUI).

APPLICATIONS

n

General Purpose Power Systems

All registered trademarks and trademarks are the property of their respective owners.

n

Telecom Systems

n

Industrial Applications

TYPICAL APPLICATION

Margin High and Margin Low

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ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢀꢁꢂꢃ

I

= –40μA

DAC

R

ꢀꢁꢂ

ꢀꢁꢂꢀꢁ

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂ

ꢀ

Rꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁꢂꢃꢄ ꢅꢆ ꢇꢄꢈ

ꢀꢁꢂꢃꢄꢁ

I

= 0μA

Rꢀꢁ

R

ꢀꢁꢂ

DAC

I

= 40μA

DAC

Rꢀ

ꢁꢂꢃ

ꢀ

ꢂꢃꢄꢀ

ꢅꢆ ꢄꢃꢄꢀ

ꢀꢁ

ꢀꢁꢂꢃꢄꢁ

ꢁꢁ

0μA TO 63μA

ꢀꢁꢂꢃ ꢄAꢂꢁꢅ

ꢀꢁ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂ

ꢀꢁꢂ ꢀꢁꢂ

Rꢀ Rꢀ

ꢀꢁꢂ

Rꢀ

ꢀ

ꢀꢁ

ꢀꢁꢂ

ꢀꢀ

–64μA TO 0μA

ꢀꢁA

ꢀꢁꢂ

ꢀꢁA

PMBus INTERFACE

ꢀꢁꢂ

ALERT

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁAꢂ

ALERT

ꢀꢁꢂ

Aꢀꢁꢂꢃ

7106 TA01a

ꢀ

ꢀꢀ

Rev A

1

Document Feedback

For more information www.analog.com

LTC7106

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

All Pins Except GND.................................. –0.3V to 6.0V

Operating Junction Temperature Range... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

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ꢌ

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ꢢ

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ꢕꢉꢏ

Aꢕꢅꢏꢌ

Aꢕꢅꢏꢍ

ꢋꢂꢁ

ꢠ

ꢃ

ꢇꢇ

ꢡ

ALERT

ꢅꢗ

ꢞ

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ꢄꢇAꢉ

ꢇꢇꢈ ꢂAꢉꢊAꢋꢅ

ꢌꢍꢎꢏꢅAꢇ ꢐꢑꢒꢒ × ꢓꢒꢒꢔ ꢂꢏAꢕꢀꢄꢉ ꢇꢖꢗ

ꢙ ꢚꢚꢛꢉꢜꢆꢝ θ ꢙ ꢌꢞꢟꢠꢛꢉꢜꢆ

θ

ꢘA

ꢘꢉ

http://www.linear.com/product/LTC7106#orderinfo

ORDER INFORMATION

LEAD FREE FINISH

LTC7106EDDB#PBF

LTC7106IDDB#PBF

TAPE AND REEL

PART MARKING*

LHCG

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTC7106EDDB#TRPBF

LTC7106IDDB#TRPBF

10-Lead (3mm × 2mm) Plastic DFN

LHCG

–40°C to 125°C

Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

Rev A

2

For more information www.analog.com

LTC7106

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2), V_DD= 3.3V, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

5.5

UNITS

V

Power Supply

2.5

V

μA

V

DD

I

Supply Quiescent Current

Undervoltage Rising Threshold

Undervoltage Falling Threshold

Enable Rising Threshold

Enable Falling Threshold

EN High

EN = 0V

700

800

1400

Q

SHUTDOWN

V

Rising

Falling

Rising

Falling

2.35

2.15

UVLO_R

UVLO_F

EN_R

DD

EN

V

1.35

V

0.8

V

EN_F

IDAC_OUT

l

I

Accuracy

Full Scale Positive

0.4 ≤ V ≤ 2V (Note 3)

Range = Normal

Range = Low

Range = High

62.5

15.5

63

63.5

16.0

μA

DAC

IDAC

15.75

252.00

–64

246.7

–64.64

255.3

–63.36

Full Scale Negative

Range = Normal

(0°C to 85°C)

0.4 ≤ V

≤ 2V (Note 3)

IDAC

l

Range = Normal

Range = Low

Range = High

Range = Normal

Range = Low

Range = High

Range = Normal

Range = Low

Range = High

Range = Normal

Range = Low

Range = High

–64.96

–16.36

–262.50

–64

–16

–256

1

–63.04

–15.64

–249.50

μA

LSB

INL

0.4 ≤ V

≤ 2V

μA

IDAC

0.25

4

μA

–1

1

LSB

nA

–1.5

–1.6

–0.3

–0.5

–0.8

1.5

1.6

0.3

0.5

0.8

20

DNL

l

IHZ

High-Z Current

V

EN

= 0

Digital Input: SDA, SCL

V

C

1.4

10

V

IH

0.8

IL

Input Capacitance

pF

Open-Drain Outputs: ALERTB, GPO, SDA

Output Low Voltage

V

I

= 3mA

0.4

V

OL

SINK

Rev A

3

For more information www.analog.com

LTC7106

PMBus INTERFACE TIMING CHARACTERISTICS ^Thel denotes the specifications which

apply over the specified operating junction temperature range, otherwise specifications are at T_A= 25°C (Note 2), V_DD= 3.3V, unless

otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

10

TYP

MAX

UNITS

kHz

µs

f

t

Serial Bus Operating Frequency

Bus Free Time Between Stop and Start Condition

Hold Time After (Repeated) Start Condition

Repeated Start Condition Setup Time

Stop Condition Setup Time

Data Hold Time

400

SCL

1.3

0.6

300

0

BUF

µs

HD_SDA

SU_SDA

SU_STO

HD_DAT(OUT)

HD_DAT(IN)

SU_DAT

LOW

µs

900

ns

Input Data Hold Time

ns

Data Setup Time

100

1.3

0.6

ns

Clock Low Period

10000

µs

Clock High Period

µs

HIGH

Stuck PMBus Timer

30

ms

TIMEOUT_SMB

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

is derated for junction temperatures greater than 125°C. Note that the

maximum ambient temperature consistent with these specifications is

determined by specific operating conditions in conjunction with board

layout, the rated package thermal impedance and other environmental

factors. T is calculated from the ambient temperature T and power

J

A

Note 2: The LTC7106 is tested under pulsed load conditions such that

dissipation P according to the following formula:

D

T ≈ T . The LTC7106E is guaranteed to meet performance specifications

J

A

from 0°C to 85°C. Specifications over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC7106I is guaranteed

over the –40°C to 125°C operating junction temperature range. High

junction temperatures degrade operating lifetimes; operating lifetime

T = T + (P • 55°C/W).

J A D

Note 3: IDAC is a bidirectional current DAC, controlled by 2’s complementary

logic. Under the setting of Range = Normal, I

provides the maximum source current and I

provides the maximum sink current. Max sink current generates the Highest

, while Max source current generates the lowest V . See the Operation

= 63µA for Code = 0111111

= –64µA for Code = 1000000

DAC

V

OUT

section for more details.

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_DD= 3.3V, V_IDAC= 1.0V,

Range = Normal unless otherwise noted.

IDAC Leakage Current vs

Temperature

Quiescent Current vs Temperature

PIDAC Full-Scale vs Temperature

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ꢀꢁꢂꢁꢃꢃ

ꢀꢁꢂꢃꢄꢄ

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ꢀꢁꢂꢃꢄꢄ

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RAꢁꢂꢃ

ꢀ

ꢃ ꢄꢅ ꢆR ꢀ

ꢃ ꢄ

ꢁꢂ

ꢇꢈꢉꢊꢋꢄꢌ

ꢀ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢅꢆꢇ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢁꢂꢃ ꢄꢂꢁ

ꢀꢁꢂꢃ ꢄꢂꢅ

Rev A

4

For more information www.analog.com

LTC7106

T_A= 25°C, V_DD= 3.3V, Range = Normal unless

otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

NIDAC vs Temperature

Differential Nonlinearity

Integral Nonlinearity

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ꢀꢁꢂꢃꢄꢄ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃꢂꢄ

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ꢀꢁꢂꢃꢄ

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ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

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Buck Start-Up with IDAC

Margin High and Margin Low

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ꢌꢍꢁ

ꢀꢁꢂꢃꢄꢅꢆ ꢇ ꢀꢁꢈꢉꢆꢊꢆ

ꢋ

ꢎ ꢄꢋ

ꢀ

ꢄ ꢅꢀ

ꢁꢂꢃ

ꢀ

ꢃ ꢄꢅꢆꢇA

ꢁAꢂ

I

= –60μA

DAC

ꢀ

ꢀꢁꢂ

ꢀ

ꢃ ꢄꢅꢆA

ꢁAꢂ

ꢀ

ꢁꢂꢃ

ꢀꢁꢁꢂꢃꢄꢅꢆꢃ

ꢀꢁꢂꢃꢄꢅꢆꢃ

I

= 0μA

DAC

ꢀ

ꢃ ꢄꢅA

ꢁAꢂ

I

= 60μA

DAC

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢁ

ꢀꢁ

ꢀꢁꢂꢃꢄꢁ

ꢀꢁꢂꢃ ꢄꢂꢀ

ꢀꢁꢂꢃ ꢄꢂꢅ

ꢀꢁꢂꢃꢄꢅꢆꢃ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

Boost Start-Up with IDAC

Margin High and Margin Low

I

= –40μA

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ꢀ ꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅꢆ ꢇ ꢀꢁꢂꢈꢃꢉꢊ

DAC

ꢀ

ꢀꢁꢂ

ꢀ

ꢀ ꢁꢂꢃ

I

= 0μA

I

= –40μA

DAC

I

= 40μA

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢂ

ꢀꢁꢂꢃꢄꢁ

I

= 0μA

I

= 0μA

DAC

I

= 40μA

DAC

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢁ

ꢀꢁ

ꢀꢁꢂꢃꢄꢁ

ꢀꢁꢂꢃ ꢄꢂꢅ

ꢀꢁꢂꢃ ꢄꢁꢂ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

Rev A

5

For more information www.analog.com

LTC7106

PIN FUNCTIONS

V

(Pin 3): Input Supply. Bypass this pin to GND with a

GPO (Pin 8): Open-Drain Digital Output. A pull-up resistor

DD

capacitor (0.1µF to 1µF).

to V is required.

DD

IDAC (Pin 6): Bidirectional Current DAC Output.

ALERT (Pin 4): Open-Drain Digital Output. A pull-up

resistor to V is required.

DD

EN (Pin 7): Chip Enable Pin. Current DAC output is in

Hi-Z state when EN is Grounded. Do not leave EN floating.

ASEL1/ASEL0 (Pins 10, 9): Serial Bus Address Select

Inputs. Each pin has three states (V , FLOATING and

DD

SDA(Pin1):SerialBusDataInputandOpen-DrainOutput.

GND); these two pins provide 9 addresses.

A pull-up resistor to V is required in the application.

DD

GND (Pin 5): Ground.

SCL (Pin 2): Serial Bus Clock Input.

Rev A

6

For more information www.analog.com

LTC7106

BLOCK DIAGRAM

ꢂꢃ

ꢄ

ꢅꢅ

RAꢃꢆꢂ

ꢋꢅA

ꢋꢌꢂꢛ RAꢔꢂ

ꢄꢉꢅꢗꢘꢙꢍꢚ

ꢉꢅAꢊ

ꢕꢖꢑꢉꢔ

ꢉꢅAꢊ

ꢇꢐꢑꢒꢓ

ꢉꢃꢔꢂRꢏAꢊꢂ

ꢋꢊꢌ

ALERT

ꢄ

ꢀ

Rꢂꢏ

ꢁ

Aꢋꢂꢌꢍ

Aꢋꢂꢌꢎ

AꢅꢅRꢂꢋꢋ

Aꢅꢊ

Rꢎ

ꢆꢇꢈ

ꢆꢃꢅ

ꢕꢎꢍꢘ ꢑꢅ

Rev A

7

For more information www.analog.com

LTC7106

OPERATION

MFR_IOUT_MARGIN_HIGH, MFR_IOUT_MARGIN_LOW

after EN goes high.

The LTC7106 is a PMBus controlled 7-bit D/A converter

currentsource.ThroughitsPMBusinterface,theLTC7106

receives a 7-bit DAC code and converts this value to a

bidirectional analog output current through the pin IDAC.

By connecting IDAC to the feedback node of a voltage

SLEW RATE CONTROL

To prevent abrupt changes in the D/A output current

and subsequently the output voltage of the DC/DC regula-

tor, an internal digital programmable slew rate control is

included. The slew rate range can be programmed with

a 6-bit register from 0.5µs/step to 3.58ms/step with a

default value of 3.58ms/step.

regulator,I

canchangetheoutputvoltageoftheregula-

DAC

tor with the equation:

V

OUT

= V • (1 + R /R ) – I

• R

FB1

REF

FB1 FB2

DAC

where V is the reference voltage of the voltage regula-

REF

tor. R and R are the resistor divider for the voltage

FB1

regulator. I

shown in Table 2.

FB2

is the programmed bidirectional current

DAC

CURRENT RANGE SETTING AND D/A PROGRAMMING

A typical application diagram is shown on the front page.

Therefore, the traditional pure analog designed oriented

PWM controller can be controlled by a PMBus interface.

The LTC7106 is a 7-bit bidirectional current DAC with a

1µA LSB as its default setting. The MSB determines the

current direction. When MSB is 0, I

is sourcing cur-

DAC

rent (reducing V ), which is positive current flowing

OUT

This illustrates the flexibility of the LTC7106 providing a

PMBusinterfacetoconventionalanalogDC/DCconverters.

out of the pin, and when MSB is 1, I

is sinking cur-

DAC

rent (increasing V ), which is negative current flowing

OUT

into the pin. The LTC7106 also provides range high and

range low options through its digital interface to change

the LSB value to 4µA expanding the output current range

and subsequently widening the programmable output

voltage range. Alternately for higher resolution, the low

range is provided with a LSB of 0.25µA. Users have ad-

ditional flexibility of choosing the resistor divider ratio and

resistor values to meet the output specification target.

However, the design is most accurate using the nominal

range which is the recommended setting. Table 1 lists the

output current range and Table 2 lists the detailed DAC

CHIP ENABLE (EN PIN)

The LTC7106 is activated by the EN pin. It turns on/off the

device with threshold of 1.2V. When EN is low (<1.2V),

IDAC is in high impedance (Hi-Z).

However, PMBus interface is still active when EN is

low which means users can program the device and

readback the internal register's value. The device will

execute the commands of MFR_IOUT_COMMAND,

codes vs I

current.

DAC

Table 1. Output Current Range

Range

LSB (μA)

I

(µA)

I

(µA)

MAX

MIN

Nominal

1

4

–64

63

Range High

Range Low

–256

–16

252

0.25

15.75

Rev A

8

For more information www.analog.com

LTC7106

OPERATION

Table 2. IDAC Current and Corresponding DAC Codes

DAC CODE

I

(µA)

DAC

DAC CODE

I

(µA)

DAC

RANGE RANGE

[6] [5] [4] [3] [2] [1] [0] NOMINAL

HIGH

LOW

[6] [5] [4] [3] [2] [1] [0] NOMINAL

HIGH

152

156

160

164

168

172

176

180

184

188

192

196

200

204

208

212

216

220

224

228

232

236

240

244

248

252

–256

LOW

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

38

39

9.5

1

4

0.25

0.5

0.75

1

9.75

10

2

8

40

3

12

41

10.25

10.5

10.75

11

4

16

42

5

20

1.25

1.5

1.75

2

43

6

24

44

7

28

45

11.25

11.5

11.75

12

8

32

46

9

36

2.25

2.5

2.75

3

47

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

40

48

44

49

12.25

12.5

12.75

13

48

50

52

3.25

3.5

3.75

4

51

56

52

60

53

13.25

13.5

13.75

14

64

54

68

4.25

4.5

4.75

5

55

72

56

76

57

14.25

14.5

14.75

15

80

58

84

5.25

5.5

5.75

6

59

88

60

92

61

15.25

15.5

15.75

–16

96

62

100

104

108

112

116

120

124

128

132

136

140

144

148

6.25

6.5

6.75

7

63

–64

–63

–62

–61

–60

–59

–58

–57

–56

–55

–54

–53

–252 –15.75

–248 –15.5

–244 –15.25

–240 –15

–236 –14.75

–232 –14.5

–228 –14.25

–224 –14

–220 –13.75

–216 –13.5

7.25

7.5

7.75

8

8.25

8.5

8.75

9

9.25

–212 –13.25

Rev A

9

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LTC7106

OPERATION

Table 2. IDAC Current and Corresponding DAC Codes (Continued)

DAC CODE

I

(µA)

DAC

DAC CODE

I

(µA)

DAC

RANGE RANGE

[6] [5] [4] [3] [2] [1] [0] NOMINAL

HIGH

LOW

[6] [5] [4] [3] [2] [1] [0] NOMINAL

HIGH

–104

–100

–96

–92

–88

–84

–80

–76

–72

–68

–64

–60

–56

–52

–48

–44

–40

–36

–32

–28

–24

–20

–16

–12

–8

LOW

–6.5

–6.25

–6

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–52

–51

–50

–49

–48

–47

–46

–45

–44

–43

–42

–41

–40

–39

–38

–37

–36

–35

–34

–33

–32

–31

–30

–29

–28

–27

–208

–13

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–26

–25

–24

–23

–22

–21

–20

–19

–18

–17

–16

–15

–14

–13

–12

–11

–10

–9

–204 –12.75

–200 –12.5

–196 –12.25

–192 –12

–188 –11.75

–184 –11.5

–180 –11.25

–176 –11

–172 –10.75

–168 –10.5

–164 –10.25

–5.75

–5.5

–5.25

–5

–4.75

–4.5

–4.25

–4

–3.75

–3.5

–3.25

–3

–160

–156

–152

–148

–144

–140

–136

–132

–128

–124

–120

–116

–112

–108

–10

–9.75

–9.5

–9.25

–9

–2.75

–2.5

–2.25

–2

–8.75

–8.5

–8.25

–8

–7

–1.75

–1.5

–1.25

–1

–6

–7.75

–7.5

–7.25

–7

–5

–4

–3

–0.75

–0.5

–0.25

–2

–6.75

–1

–4

Rev A

10

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LTC7106

OPERATION

GPO

Device Addressing

GPO is a general purpose open-drain output pin, which

can be set by PMBus command. It is designed to turn on/

off the DC/DC regulator by connecting GPO to the RUN

pin of the regulator. Once GPO is set high, it stays high

even if the EN pin goes low as long as the device is not

power cycled.

TheLTC7106offersfourdifferenttypesofaddressingover

the PMBus interface, specifically: 1) global, 2) device, 3)

rail addressing and 4) alert response address (ARA).

Global addressing provides a means of the PMBus master

to address all LTC7106 devices on the bus. The LTC7106

global addresses are fixed 0x5A or 0x5B (7 bit) or 0xB4

or 0xB6 (8 bit) and cannot be disabled.

ADDRESS

Device addressing provides the standard means of

the PMBus master communicating with a single instance

of a LTC7106. The value of the device address is set by

the ASEL0/ASEL1 configuration pins. Rail addressing

provides a means of the PMBus master addressing a

set of channels connected to the same output rail, simul-

taneously. This is similar to global addressing, however,

the PMBus address can be dynamically assigned by

using the MFR_RAIL_ADDRESS command. It is recom-

mendedthatrailaddressingshouldbelimitedtocommand

write operations.

The PMBus address is selected by ASEL0 and ASEL1

pins. Each pin has three states: high, low and floating.

The possible PMBus addresses are shown in Table 3.

Table 3. Address Selection

ASEL1

GND

ASEL0

PMBus ADDRESS

GND

2A

2C

2E

4A

4C

4E

6A

6C

6E

GND

V

DD

GND

FLOAT

GND

V

DD

V

DD

All four means of PMBus addressing require the user to

employdisciplinedplanningtoavoidaddressingconflicts.

FLOAT

GND

FLOAT

V

DD

Fault Status

FLOAT

The STATUS_BYTE and ALERT pin provide fault status

information of the LTC7106 to the host.

PMBus SERIAL INTERFACE

Bus Timeout Failure

The LTC7106 serial interface is a PMBus-compliant slave

device and can operate at any frequency between 10kHz

and 400kHz. In addition the LTC7106 always responds to

the global broadcast address of 0x5A or 0x5B (7-bit). The

serial interface supports the following protocols defined

in the PMBus specifications: 1) send command, 2) write

byte, 3) group, 4) read byte and 5) read word. The PMBus

write operations are not acted upon until a complete valid

messageisreceivedbytheLTC7106includingtheSTOPbit.

TheLTC7106implementsatimeoutfeaturetoavoidhang-

ing the serial interface. The data packet timer begins at the

first START event before the device address write byte.

Data packet information must be completed within 25ms

or the LTC7106 will tri-state the bus and ignore the given

data packet. Data packet information includes the device

address byte write, command byte, repeat start event

(if a read operation), device address byte read (if a read

operation), and all data bytes.

Communication Failure

The user is encouraged to use as high a clock rate as

possible to maintain efficient data packet transfer be-

tween all devices sharing the serial bus interface. The

LTC7106 supports the full PMBus frequency range from

10kHz to 400kHz.

Attempts to access unsupported commands or writing

invalid data to supported commands will result in a CML

fault. The CML bit is set in the STATUS_BYTE command

and the ALERT pin is pulled low.

Rev A

11

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LTC7106

OPERATION

Similarity Between PMBus, SMBus and I C 2-Wire

Interface

2

The following PMBus protocols are supported:

• Write Byte, Send Byte

The PMBus 2-wire interface is an incremental extension

• Read Byte, Read Word

2

of the SMBus. SMBus is built upon I C with some minor

• Alert Response Address

differences in timing, DC parameters and protocol. The

2

PMBus/SMBusprotocolsaremorerobustthansimpleI C

Figure 3 through Figure 6 illustrate the aforementioned

PMBus protocols. All transactions support GCP (group

command protocol).

bytecommandsbecausePMBus/SMBusprovidetimeouts

to prevent bus hangs and valid operation commands. In

2

general, a master device that can be configured for I C

Figure 2 is a key to the protocol diagrams in this section.

communication can be used for PMBus communication

with little or no change to hardware or firmware. Repeat

A value shown below a field in the following figures is a

mandatory value for that field.

2

start (restart) is not supported by all I C controllers but

is required for SMBus/PMBus reads. If a general purpose

The data formats implemented by PMBus are:

2

I C controller is used, check that repeat start is supported.

• Master transmitter transmits to slave receiver. The

transfer direction in this case is not changed.

For a description of the minor extensions and exceptions

PMBus makes to SMBus, refer to PMBus Specification

Part 1, Revision 1.1: Paragraph 5: Transport.

• Master reads slave immediately after the first byte. At

the moment of the first acknowledgment (provided by

the slave receiver) the master transmitter becomes a

master receiver and the slave receiver becomes a slave

transmitter.

2

ForadescriptionofthedifferencesbetweenSMBusandI C,

refer to System Management Bus (SMBus) Specification

Version 2.0: Appendix B—Differences Between SMBus

2

and I C.

• Combined format. During a change of direction within

a transfer, the master repeats both a start condition and

the slave address but with the R/W bit reversed. In this

case, the master receiver terminates the transfer by

generating a NACK on the last byte of the transfer and

a STOP condition.

PMBus SERIAL INTERFACE

TheLTC7106communicateswithahost(master)usingthe

standardPMBusserialbusinterface.TheTimingDiagram,

Figure 1, shows the timing relationship of the signals on

the bus. The two-bus lines, SDA and SCL, must be high

when the bus is not in use. External pull-up resistors or

current sources are required on these lines.

Examples of these formats are shown in Figure 4 and

Figure 5.

The LTC7106 is a slave device. The master can com-

municate with the LTC7106 using the following formats:

• Master Transmitter, Slave Receiver

• Master Receiver, Slave Transmitter

Rev A

12

For more information www.analog.com

LTC7106

OPERATION

ꢀꢁA

ꢄ

ꢒ

ꢄ

ꢀꢉꢆꢁAꢇꢈ

ꢄ

ꢀꢌ

ꢄ

ꢅꢁꢆꢀꢁAꢈ

ꢒ

ꢄ

ꢓ

ꢄ

ꢓ

ꢄ

ꢍꢉꢎ

ꢃꢊꢋ

ꢀꢂꢃ

ꢄ

ꢀꢉꢆꢀꢇꢊꢈ

ꢅꢁꢆꢀꢇAꢈ

ꢀꢉꢆꢀꢇAꢈ

ꢄ

ꢅꢐꢔꢅ

ꢅꢁꢆꢁAꢇꢈ

ꢕꢖꢗꢘ ꢎꢗꢖ

ꢀꢇARꢇ

ꢂꢊꢏꢁꢐꢇꢐꢊꢏ

RꢑꢌꢑAꢇꢑꢁ ꢀꢇARꢇ

ꢂꢊꢏꢁꢐꢇꢐꢊꢏ

ꢀꢇꢊꢌ

ꢀꢇARꢇ

ꢂꢊꢏꢁꢐꢇꢐꢊꢏ ꢂꢊꢏꢁꢐꢇꢐꢊꢏ

Figure 1. Timing Diagram

ꢌ

ꢋ

ꢌ

A

ꢙ

ꢟ

ꢌ

A

ꢙ

ꢌ

ꢀ

ꢀꢁAꢂꢃ AꢄꢄRꢃꢀꢀ ꢈꢉ

ꢄAꢅA ꢆꢇꢅꢃ

ꢊ

ꢀ

ꢀꢅARꢅ ꢑꢒꢓꢄꢔꢅꢔꢒꢓ

ꢀꢉ

RꢃꢊꢃAꢅꢃꢄ ꢀꢅARꢅ ꢑꢒꢓꢄꢔꢅꢔꢒꢓ

Rꢕ RꢃAꢄ ꢖꢆꢔꢅ ꢂAꢁꢗꢃ ꢒꢏ ꢌꢘ

ꢈꢉ ꢈRꢔꢅꢃ ꢖꢆꢔꢅ ꢂAꢁꢗꢃ ꢒꢏ ꢍꢘ

ꢙ

ꢀꢚꢒꢈꢓ ꢗꢓꢄꢃR A ꢏꢔꢃꢁꢄ ꢔꢓꢄꢔꢑAꢅꢃꢀ ꢅꢚAꢅ ꢅꢚAꢅ

ꢏꢔꢃꢁꢄ ꢔꢀ RꢃꢛꢗꢔRꢃꢄ ꢅꢒ ꢚAꢂꢃ ꢅꢚꢃ ꢂAꢁꢗꢃ ꢒꢏ ꢙ

A

Aꢑꢜꢓꢒꢈꢁꢃꢄꢝꢃ ꢖꢅꢚꢔꢀ ꢆꢔꢅ ꢊꢒꢀꢔꢅꢔꢒꢓ ꢞAꢇ ꢆꢃ ꢍ

ꢏꢒR Aꢓ Aꢑꢜ ꢒR ꢌ ꢏꢒR A ꢓAꢑꢜꢘ

ꢊ

ꢀꢅꢒꢊ ꢑꢒꢓꢄꢔꢅꢔꢒꢓ

ꢊꢃꢑ ꢊAꢑꢜꢃꢅ ꢃRRꢒR ꢑꢒꢄꢃ

ꢞAꢀꢅꢃR ꢅꢒ ꢀꢁAꢂꢃ

ꢀꢁAꢂꢃ ꢅꢒ ꢞAꢀꢅꢃR

ꢠꢠꢠ

ꢑꢒꢓꢅꢔꢓꢗAꢅꢔꢒꢓ ꢒꢏ ꢊRꢒꢅꢒꢑꢒꢁ

ꢋꢌꢍꢎ ꢏꢍꢐ

Figure 2. PMBus Packet Protocol Diagram Element Key

ꢐ

ꢏ

ꢐ

ꢕ

ꢐ

ꢕ

ꢐ

ꢀ

ꢀꢁAꢂꢃ AꢄꢄRꢃꢀꢀ ꢌꢍ

A

ꢅꢆꢇꢇAꢈꢄ ꢅꢆꢄꢃ

A

ꢄAꢉA ꢊꢋꢉꢃ

A

ꢎ

ꢏꢐꢑꢒ ꢓꢑꢔ

Figure 3. Write Byte Protocol

ꢉ

ꢈ

ꢉ

ꢎ

ꢉ

ꢀ

ꢀꢁAꢂꢃ AꢄꢄRꢃꢀꢀ ꢅꢆ

A

ꢏꢐꢑꢑAꢒꢄ ꢏꢐꢄꢃ

A

ꢇ

ꢈꢉꢊꢋ ꢌꢊꢍ

Figure 4. Send Byte Protocol

ꢍ

ꢌ

ꢍ

ꢒ

ꢍ

ꢌ

ꢍ

ꢒ

ꢍ

ꢒ

ꢍ

A

ꢍ

ꢀ

ꢀꢁAꢂꢃ AꢄꢄRꢃꢀꢀ ꢉꢊ

A

ꢅꢆꢇꢇAꢈꢄ ꢅꢆꢄꢃ

A

ꢀꢊ ꢀꢁAꢂꢃ AꢄꢄRꢃꢀꢀ Rꢙ

A

ꢄAꢓA ꢔꢕꢓꢃ ꢁꢆꢉ

A

ꢄAꢓA ꢔꢕꢓꢃ ꢖꢗꢘꢖ

ꢋ

ꢌꢍꢎꢏ ꢐꢎꢑ

Figure 5. Read Word Protocol

ꢍ

ꢌ

ꢍ

ꢑ

ꢍ

ꢑ

ꢍ

ꢑ

ꢍ

A

ꢍ

ꢀ

ꢀꢁAꢂꢃ AꢄꢄRꢃꢀꢀ ꢉꢊ

A

ꢅꢆꢇꢇAꢈꢄ ꢅꢆꢄꢃ

A

ꢀꢊ ꢀꢁAꢂꢃ AꢄꢄRꢃꢀꢀ Rꢕ

A

ꢄAꢒA ꢓꢔꢒꢃ

ꢋ

ꢌꢍꢎꢏ ꢐꢎꢏ

Figure 6. Read Byte Protocol

Rev A

13

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LTC7106

REGISTER COMMAND DETAILS

Table 4. LTC7106 Supported PMBus Commands

PMBus CODE

(8 BITS)

0x01

R/W TYPE

R/W

COMMAND NAME

OPERATION

DESCRIPTION

Default is On: [7:0] = 0x80

0x78

R/W

STATUS_BYTE

Read Fault Status: CML, Write 1 to Reset

Read PMBus Revision = 0x22 for Rev 1.2

0x98

Read

PMBUS_REVISION

MFR_CHIP_CTRL

0xE2

R/W

[7:4] – Reserved: [7:0] = 0x00 Default

[0] = GPO EN, [1] = Reserved, [2] = Write Protect, [3] = Timeout Status

0xE4

0xE5

0xE6

R/W

MFR_DAC_CTRL

[7:6] = Current Step Control, [5:0] = DAC Slew Rate Control

MFR_IOUT_MARGIN_HIGH Same Format as MFR_IOUT_COMMAND

MFR_IOUT_MAX

Clamped Value that DAC Cannot Exceed. Default 7-Bit Value of 0x00 = Source

Current Only

0xE7

0xE8

Read

R/W

MFR_SPECIAL_ID

MFR Special ID for LTC7106 = 0x8080

MFR_IOUT_COMMAND

I

Margining Command (see Table 5)

OUT

[5:0] Step Value, Source: [6] = 0, Sink: [6] = 1

0xED

0xFA

R/W

MFR_IOUT_MARGIN LOW Same Format as MFR_IOUT_COMMAND

MFR_RAIL_ADDRESS

Set Common PMBus Address [6:0],

[7] = 0 Enable, [7] = 1 Disable

0xFD

Write

MFR_RESET

Reset PMBus Interface to Power-On State

Write Data is Ignored; 0, 1, 2 Bytes

MFR_IOUT_COMMAND

MFR_IOUT_MARGIN_LOW

The DAC output current command is formatted as a 7-bit

2’s complement value. When the operation register is set

to 0x80,DACtakesthevaluestoredinthisregister.Setting

bit[6] to 0 sources the current from the IC and bit[6] to 1

sinks the current into the IC. Default value for this register

is 0x00. The valid range of values are from 0x40 to 0x3 F.

DAC margining register with the same format and rules

as MFR_IOUT_COMMAND. The DAC value will take the

value stored in this register when the operation register

is set to margin low, 0x98.

MFR_IOUT_MAX

Do not attempt to write values outside of this range or

undesired behavior may result. Writes to this register are

inhibited when the WPB, bit [2] in MFR_CHIP_CTRL, is

set high.

Clamping value that DAC cannot exceed. The format is

a 7-bit 2’s complement value, the same as the margin

registers. Therefore, the DAC value cannot be a smaller

2’s complement value than what is stored in this register.

The 7-bit default value is 0x00 = cannot sink current. I

OUT

MFR_IOUT_MARGIN_HIGH

cannotbesettoahighervalueunlessthisvalueischanged

DAC margining register with the same format and rules

as MFR_IOUT_COMMAND. The DAC value will take the

value stored in this register when the operation register

is set to margin high, 0xA8.

to a negative number, bit [7] = 1.

Setting this register to 0x40 allows the LTC7106 to sink

the maximum current with no clamping.

Rev A

14

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LTC7106

REGISTER COMMAND DETAILS

MFR_CHIP_CTRL

Only a power cycle, POR, will reset this register to prevent

unwantedimmediatecurrentchangesinIDAC.MFR_RESET

will not reset this register.

This register is for general chip control and status. Please

refer to Table 7 for each bit description.

In addition, IDAC must be at 0x00 to change the current

Bits Description

range selector to prevent unwanted large swings in I

DAC

[7:4] Reserved

current. The time step selector, bits [5:0], can be changed

at any time.

[3]

Timeout Status:

Table 5. Programmable Delay Per Current Step

Slew Rate Timer Clock (µs/Step)

0 = No PMBus Timeout Occurred

1 = A Timeout Occurred

Writing a 1 to this bit will clear this bit

Write Protect for Margin Registers

0 = Write Allowed

[5:0]

0 0 0 0 0 0

[5:0]

= 3584 0 1 0 0 0 0

[5:0]

1 0 0 0 0 0

= 16

= 20

= 24

= 28

= 32

= 40

= 48

= 56

= 64

= 80

= 96

= 256

0 0 0 0 0 1

0 0 0 0 1 0

0 0 0 0 1 1

0 0 0 1 0 0

0 0 0 1 0 1

0 0 0 1 1 0

0 0 0 1 1 1

0 0 1 0 0 0

0 0 1 0 0 1

0 0 1 0 1 0

0 0 1 0 1 1

0 0 1 1 0 0

0 0 1 1 0 1

0 0 1 1 1 0

0 0 1 1 1 1

= 0.5

= 1.0

= 1.5

= 2.0

= 2.5

= 3.0

= 3.5

= 4.0

= 5.0

= 6.0

= 7.0

= 8.0

= 10

0 1 0 0 0 1

1 0 0 0 0 1

1 0 0 0 1 0

1 0 0 0 1 1

1 0 0 1 0 0

1 0 0 1 0 1

1 0 0 1 1 0

1 0 0 1 1 1

1 0 1 0 0 0

1 0 1 0 0 1

1 0 1 0 1 0

= 320

[2]

0 1 0 0 1 0

0 1 0 0 1 1

0 1 0 1 0 0

0 1 0 1 0 1

0 1 0 1 1 0

0 1 0 1 1 1

0 1 1 0 0 0

0 1 1 0 0 1

0 1 1 0 1 0

0 1 1 0 1 1

0 1 1 1 0 0

0 1 1 1 0 1

0 1 1 1 1 0

0 1 1 1 1 1

= 384

= 448

= 512

1 = Writes Inhibited

= 640

[1]

[0]

Reserved

= 768

GPO, General Purpose Output

0 = GPO Pulls Open Drain to GND

1 = Hi-Z on GPO

= 896

= 1280*

= 1280

= 1536

= 1792

= 2560*

= 2560

= 3584*

= 3584

= 112 1 0 1 0 1 1

= 128 1 0 1 1 0 0

= 160 1 0 1 1 0 1

= 192 1 0 1 1 1 0

= 224 1 0 1 1 1 1

MFR_DAC_CTRL

8-bit register to control the I

LSB current value and the

DAC

= 12

timer count for the slew rate control. Default value = 0x40.

= 14

Bits Description

* Duplicate Encoding

[7:6] Selector Range for I

Step Current:

DAC

b’00 = 0.25µA/Step, Range Low

b’01 = 1.0µA/Step, Nominal

b’10 = 4.0µA/Step, Range High

b’11 = Reserved

[5:0] Selector for Time in µs/Step

Default Value 0x00 = Max = 3584µs/Step

See Table 6 for Allowable Values

Rev A

15

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LTC7106

PMBus COMMAND DETAILS

MFR_RESET

OPERATION

This command provides a means by which the user can

perform a reset of the LTC7106. All latched faults (ALERT

and status register) and register contents will be reset to a

The OPERATION command is used to turn the unit on/off

and for margining the output voltage.

The ON bit is automatically reset to ON after a master

shutdown (EN), power cycle, or MFR_RESET command.

power-on condition by this command. V

will remain in

OUT

regulation but may change due to the reset of the margin

registers.

The MARGIN_LOW/HIGH bits command the I

refer-

OUT

ence to the offset value stored in either the MFR_IOUT_

MARGIN_HIGH or MFR_IOUT_MARGIN_LOW.

This write-only command accepts zero, one, or two data

bytes but ignores them.

This command has one data byte. It will accept one or two

but ignores the second byte.

MFR_RAIL_ADDRESS

The MFR_RAIL_ADDRESS command allows all devices

to share a common address, such as all devices attached

to a single power supply rail. The desired 7-bit address

value is written to the 7 bits of the data byte.

Table 6. Supported OPERATION Command Register Values

ACTION

Turn Off Immediately

Turn On

VALUE

0x00

0x80

0x98

0xA8

Margin Low

TheMSB(bitB7)mustbesetlowtoenablecommunication

using the MFR_RAIL_ADDRESS address. Setting this bit

disables this address. The default for this register is 0x80.

Margin High

PMBus_REVISION

ThePMBUS_REVISIONcommandindicatestherevisionof

the PMBus to which the device is compliant. The LTC7106

is PMBus Version 1.2 compliant in both Part I and Part II.

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ꢅꢀ

ꢅꢂ

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ꢀꢁꢂꢃ ꢄꢂꢀ

This read-only command has one data byte and will

return 0x22.

Figure 7. MFR_RAIL_ADDRESS Data Byte

MFR_SPECIAL_ID

The user should only perform command writes to this

address. If a read is performed from this address and the

rail devices do not respond with EXACTLY the same value,

the LTC7106 will detect bus contention and abort its read

command with no CML or ALERTB set.

The 16-bit word representing a unique identification for

LTpowerPlay.

This read-only command has 2 data bytes and is set to

0x8080.

This command accepts one or two data bytes but the

second is ignored.

Rev A

16

For more information www.analog.com

LTC7106

PMBus COMMAND DETAILS

STATUS_BYTE

the fault is still present the status byte bit and ALERT will

remain asserted. If the ALERT has previously been cleared

by an ARA message, the ALERT will be re-asserted. If the

faultisnolongerpresent,theALERTpinwillbede-asserted

and the fault bit in the status byte will be cleared.

TheSTATUS_BYTEcommandreturnsonebyteofinforma-

tion with a summary of the unit’s fault condition.

See Table 7 for a list of the status bits that are supported

and the conditions in which each bit is set. Certain bits

when set in the STATUS_BYTE also cause the ALERT pin

to be asserted.

All bits in the status byte are also cleared by toggling the

RUN_MSTR pin or the ON bit in OPERATION. The bit will

immediately be set again if the fault remains.

Writinga“1”toaparticularbitinthestatusbytewillattempt

to reset that fault in the status byte and the ALERT pin. If

Table 7. Status Byte Bit Descriptions and Conditions

CLEARABLE BY

BIT

DESCRIPTION

None of the Above

Communication Failure

Temperature Fault

CONDITION

MFR_VOUT_MAX Register Exceeded

(See Note 1)

SET ALERT?

WRITING ‘1’ TO BIT?

0 (LSB)

No

Yes

1

2

3

4

5

6

7

Yes

Not Implemented

V

Undervoltage Fault

Not Implemented

IN

Output Overcurrent Fault

Not Implemented

Output Overvoltage Fault

Not Implemented

OFF

Not Implemented

Busy

Not Implemented

Note 1: Communication failure is one of following faults: host sends too few bits, host reads too few bits, host writes too few bytes, improper R/W bit

set, unsupported command code, attempt to write to a read-only command. See PMBus Specification v1.2, Part II, Sections 10.8 and 10.9 for more

information.

Rev A

17

For more information www.analog.com

LTC7106

APPLICATIONS INFORMATION

Define ∆V

as the V

error caused by the I

error

OUT

DAC

I

ACCURACY

∆I , then we can derive the following equation from

DAC

equation (1) and (2):

TheLTC7106providesthreerangesofI outputcurrent.

DAC

However, only nominal range (LSB = 1µA) is optimized

with the highest accuracy. It is recommended that users

design the resistor divider using the nominal range of the

IDAC setting.

∆V_OUT

V_OUT

∆I_DAC/I_DAC

Ratio – 1

⎛

⎞

=

(3)

⎜

⎝

⎟

⎠

Where:

V

OUT0

Ratio =

(4)

TWO’S COMPLEMENTARY CODE

I

• R

FB1

DAC

VID [6:0] of the LTC7106 is in the format of two’s comple-

mentary. From Table 2, it is easy to program the register

once the desired output current is known. For example, if

output current is 20µA, then set VID [6:0] = 0010100. If

the output current is –20µA, then set VID [6:0] = 1101100

It is clear that when Ratio < 0 or Ratio ≥ 2, the V

error

OUT

can be attenuated from the I

error:

DAC

∆V

V

∆I

I

OUT

DAC

|

| ≤ |

|

(5)

OUT

DAC

for the nominal I

setting.

DAC

Inthecaseofmarginhigh, I

<0soRatio<0. Therefore,

DAC

the V

factor of:

error is always smaller than the I

error by a

OUT

DAC

V

ACCURACY

OUT

When I

= 0, define:

DAC

V

OUT0

– 1

(6)

R_FB1

R_{FB2 ⎦}

⎡

⎤

⎥

I • R

FB1

DAC

V_OUT0= V_REF1+

(1)

⎢

⎣

In the case of margin low, I

only be attenuated when:

> 0. So the V

error will

(7)

DAC

OUT

ReferringtoFigure8,theoutputvoltageissetaccordingto:

V

OUT0

R_FB1

R_{FB2 ⎦}

⎡

⎤

Ratio =

> 2

V_OUT= V_REF1+

–I_DAC•R_FB1

⎥

(2)

⎢

⎣

I

• R

FB1

DAC

V

OUT0

or

I

• R

<

FB1

DAC

2

ꢀ

ꢀꢁꢂ

In other words, as long as V

is margining low within

OUT

R

ꢀꢁꢂ

50% of the V

default value, V

,the V

OUT0

error won't

ꢀꢁꢂꢃꢄꢅꢆ

OUT

ꢀ

Rꢁꢂ

be larger than the I

error.

ꢀ

DAC

ꢁAꢂ

R

ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢂꢅ

DESIGN EXAMPLES

Figure 8. Setting the Output Voltage Using the LTC7106

The LTC7106 can work with almost all the power manage-

ment controllers or regulators. Figure 9, Figure 10 and

Figure 11 show three design examples using the LTC7106

to control the output voltage with a monolithic buck regu-

lator, an μModule^®and a boost controller.

Rev A

18

For more information www.analog.com

LTC7106

APPLICATIONS INFORMATION

Case One

current amplitude is, the better accuracy the LTC7106

can achieve. So it is easy to choose R

= 10kΩ and

TOP

Assume that the LTC7150S, a monolithic buck regula-

tor, provides a 1.5V output and requires to margin low

R

BOT

= 6.65kΩ. Then I

= (1.5V – 1.0V)/10kΩ = + 50μA.

DAC

Choose MFR_CONTROL [6:5] = 00 (Range = Nominal) to

set I LSB =1μA.

V

from 1.5V to 1.0V (see Figure 9). The V is 0.6V

OUT

FB

DAC

and the voltage dividers are external. In order to achieve

the best accuracy of the LTC7106, it is recommended to

By looking in Table 2, choose DAC [6:0] = 0110010 to set

design I

in nominal range. Also within certain current

theI =+50μA,whichwillmarginV from1.5Vto1.0V.

DAC

DAC OUT

range (nominal, high or low), the larger the absolute I

DAC

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ꢀꢁꢂꢃꢄꢅꢆA

ꢀꢁꢂ

ꢀꢁꢁꢂꢃ

ꢄꢅ

ꢀꢁ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆꢇ

ꢀꢀꢁꢂꢃ

ꢀꢁꢀꢂꢃ

ꢀꢀꢁꢂ

ꢃꢀ

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ꢀꢁꢂꢃꢄꢅ

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ꢄꢄ

Rꢀ

ꢀꢁꢂ

4.7μF

ꢀꢁꢂ

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ꢁꢉꢀ

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ꢀ

ꢀꢀ

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ꢀꢁꢂ ꢀꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢀ

ꢀꢁA

ꢀꢁꢂ

ꢀꢁA

ꢇꢈꢉꢊꢋ ꢌꢍꢎꢏRꢅAꢐꢏ

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ALERT

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ALERT

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Aꢀꢁꢂꢃ

ꢁꢂꢃꢄ ꢅꢃꢆ

Figure 9. Using the LTC7106 to Margin Low Monolithic Buck Regulator LTC7150S Providing 1.5V to 1.0V at 20A

Rev A

19

For more information www.analog.com

LTC7106

APPLICATIONS INFORMATION

Case Two

Inthiscase,theμModuleLTM4636providesa1.2Voutput

So we have to choose MFR_CONTROL [6:5] = 10

(Range = High) to set I LSB = 4μA.

and requires to margin high V

from 1.2V to 2.0V (see

OUT

DAC

Figure10).TheV oftheLTM4636isagain0.6V.However,

FB

From Table 3, choose DAC[6:0] = 1011000 to set the

= –160µA, which will margin V from 1.2V to 2.0V.

the top voltage divider is internal (R

= 4.99kΩ), so the

DAC

TOP

I

DAC

OUT

R

BOT

is also fixed at 4.99kΩ. Then I

= (1.2V – 2.0V)/

4.99kΩ = –160μA.

ꢀ

ꢀꢁ

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ꢇꢉ ꢀꢀ ꢄꢄ

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ꢀꢁ

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ꢀꢁꢂꢃ

ꢀꢀꢁꢂ

ꢀꢁꢂ

ꢀꢁ

ꢀꢀ

ꢀꢁ

ꢀꢀ

ꢀꢀꢁꢂ

ꢀꢁꢁꢂꢃ

ꢀꢁꢂ

ꢀ

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ꢀꢁ

ꢀꢀ

ꢀꢀꢁꢂ

ꢀꢁ

ꢀꢀ

Rꢀꢁꢂ

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ꢀ

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Rꢀꢁꢂ

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ꢀ

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ꢀ

ꢀꢁ

ꢀꢁꢀꢂꢃ

ꢀꢁꢂꢂꢃ

ꢀꢁꢂꢃA

ꢀꢁꢂꢃ ꢂꢄꢅ ꢆꢃꢇꢈ ꢁꢂ ꢅꢉꢁꢃ ꢊꢁRꢊꢆꢁꢅꢋ

ꢀꢁꢂꢃꢄ ꢆꢇꢈꢃꢉꢆ ꢊꢇꢃꢃꢋꢆꢊꢌꢈꢃꢋꢍꢆꢊꢎꢈꢆ

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ꢀꢁꢂꢃꢄ

ꢄ

ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢀꢄAꢅ ꢂꢆꢇꢁ ꢇꢀꢄꢃꢂꢀR

160μA

TO MARGIN HIGH

FROM

ꢀꢁꢂꢃ ꢄꢅ ꢂꢁꢂꢃ

ꢀ

ꢀꢀ

V

OUT

1.2V TO 2V

ꢀꢁꢂ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢀ

ꢀꢁA

ꢀꢁꢂ

ALERT

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁAꢂ

R A

ALERT

ꢀꢁꢂ

Aꢀꢁꢂꢃ

Figure 10. Using the LTC7106 to Margin High μModule LTM4636 Providing 1.2V to 2.0V at 40A

Rev A

20

For more information www.analog.com

LTC7106

APPLICATIONS INFORMATION

Case Three

design criteria in Case One, we can choose R

= 200kΩ

TOP

and R

= 8.97kΩ for the best accuracy. Then I

=

BOT

DAC

The LTC7106 can also work with boost converters. In

this case, the LTC3784, a synchronous boost controller,

providesa2-phase28V/10Aoutputandrequirestocontrol

(28V – 18V)/200kΩ = +50µA. Choose MFR_CONTROL

[6:5] = 00 (Range Nominal) to set I LSB = 1µA. By

DAC

looking in Table 2, choose DAC[6:0] = 0001110 to set the

V

from 28V to 18V (see Figure 11). The VFB is 1.2V

OUT

I

= +50μA, which will margin V

from 28V to 18V.

DAC

OUT

and the voltage dividers are external. Based on the same

3.3μH

4mΩ

ꢀꢁꢂꢃ

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ꢄ

ꢀꢁꢂꢀꢁꢃ

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ꢀ

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ꢀ

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ꢀꢁꢁꢂꢃꢄ

ꢃꢄꢀ

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ꢅꢆꢇꢈ ꢂꢆ ꢄꢉꢊꢀ AꢋꢂꢌR

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ꢄꢅꢀ Aꢃ ꢆꢇA

ꢀꢁꢂ

3.3μH

4mΩ

ꢀꢀꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢀ

ꢀꢁꢂꢃꢄ

ꢄ

ꢀꢁꢂꢀꢁꢃ

ꢄ

ꢀꢁꢁꢂ

ꢀꢁꢂꢀꢁꢃ

ꢀꢁꢂꢂꢃ

ꢀRꢁꢂ

ꢀꢁꢂꢃ

ꢀꢀ

ꢀꢁꢂ

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ꢀꢁꢂ

ꢀꢁꢂꢃ

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ꢀꢀ

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ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ ꢄꢅ ꢂꢁꢂꢃ

ꢀ

ꢀꢀ

ꢀꢁꢂꢃA

ꢄꢅ ꢆARꢇꢈꢉ ꢊꢅꢋ ꢌ

ꢎRꢅꢆ ꢏꢐꢌ ꢄꢅ ꢑꢐꢌ

ꢅꢍꢄ

ꢀꢁꢂ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢀ

ꢀꢁA

ꢀꢁꢂ

ꢀꢁA

ꢐꢒꢁꢖꢗ ꢑꢈꢂꢌRꢋAꢘꢌ

ꢀꢁꢂ

ALERT

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁAꢂ

ALERT

ꢀꢁꢂ

Aꢀꢁꢂꢃ

ꢓꢃꢔꢕ ꢋꢃꢃ

Figure 11. Using the LTC7106 with a Boost Controller to Vary V_OUTfrom 28V to 18V

Rev A

21

For more information www.analog.com

LTC7106

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC7106#packaging for the most recent package drawings.

DDB Package

10-Lead Plastic DFN (3mm × 2mm)

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R ꢧ ꢂꢁꢀꢂ ꢋR

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ꢂ ꢨ ꢂꢁꢂꢡ

ꢞꢋꢌꢌꢋꢒ ꢓꢆꢈꢎꢥꢈꢝꢖꢋꢅꢈꢇ ꢖAꢇ

ꢊꢋꢌꢈꢍ

ꢃꢁ ꢇRAꢎꢆꢊꢏ ꢐꢋꢊꢑꢋRꢒꢅ ꢌꢋ ꢓꢈRꢅꢆꢋꢊ ꢄꢎꢈꢐꢇꢔꢃꢉ ꢆꢊ ꢕꢈꢇꢈꢐ ꢖAꢐꢗAꢏꢈ ꢋꢘꢌꢙꢆꢊꢈ ꢒꢂꢔꢀꢀꢚ

ꢀꢁ ꢇRAꢎꢆꢊꢏ ꢊꢋꢌ ꢌꢋ ꢅꢐAꢙꢈ

ꢛꢁ Aꢙꢙ ꢇꢆꢒꢈꢊꢅꢆꢋꢊꢅ ARꢈ ꢆꢊ ꢒꢆꢙꢙꢆꢒꢈꢌꢈRꢅ

ꢜꢁ ꢇꢆꢒꢈꢊꢅꢆꢋꢊꢅ ꢋꢑ ꢈꢝꢖꢋꢅꢈꢇ ꢖAꢇ ꢋꢊ ꢞꢋꢌꢌꢋꢒ ꢋꢑ ꢖAꢐꢗAꢏꢈ ꢇꢋ ꢊꢋꢌ ꢆꢊꢐꢙꢘꢇꢈ

ꢒꢋꢙꢇ ꢑꢙAꢅꢟꢁ ꢒꢋꢙꢇ ꢑꢙAꢅꢟꢠ ꢆꢑ ꢖRꢈꢅꢈꢊꢌꢠ ꢅꢟAꢙꢙ ꢊꢋꢌ ꢈꢝꢐꢈꢈꢇ ꢂꢁꢃꢡꢢꢢ ꢋꢊ Aꢊꢣ ꢅꢆꢇꢈ

ꢡꢁ ꢈꢝꢖꢋꢅꢈꢇ ꢖAꢇ ꢅꢟAꢙꢙ ꢞꢈ ꢅꢋꢙꢇꢈR ꢖꢙAꢌꢈꢇ

ꢤꢁ ꢅꢟAꢇꢈꢇ ARꢈA ꢆꢅ ꢋꢊꢙꢣ A RꢈꢑꢈRꢈꢊꢐꢈ ꢑꢋR ꢖꢆꢊ ꢃ ꢙꢋꢐAꢌꢆꢋꢊ ꢋꢊ ꢌꢟꢈ ꢌꢋꢖ Aꢊꢇ ꢞꢋꢌꢌꢋꢒ ꢋꢑ ꢖAꢐꢗAꢏꢈ

Rev A

22

For more information www.analog.com

LTC7106

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

04/18 Clarified MFG_RAIL_ADDRESS and MFG_SPECIAL_ID paragraphs

Changed from “Status Word” to “Status Byte”

15

16

Rev A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

23

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTC7106

TYPICAL APPLICATION

ꢙ

ꢋꢌ

ꢁꢐꢥ

ꢁꢐꢄ

ꢙ

ꢁꢘꢜꢙ

ꢃA

ꢔꢕꢍ

ꢗꢘꢝꢙ ꢍꢔ ꢅꢅꢙ

ꢣꢝꢅꢙ ꢍRAꢌꢓꢋꢎꢌꢍꢤ

ꢙ

ꢓꢞ

ꢋꢌ

ꢝꢘꢀꢐꢄ

ꢎꢑꢍꢎRꢌAꢒ

ꢓꢔꢕRꢏꢎ ꢖꢗꢘꢁꢙ

ꢔR ꢚꢌꢛ

ꢎꢌꢟꢕꢙ

ꢈꢋAꢓ

ꢁꢂꢠꢄ

ꢃꢘꢂꢝꢢ

ꢃꢘꢦꢜꢢ

ꢒꢍꢜꢃꢝꢂꢓ

ꢚꢌꢛ

ꢁꢂꢂꢐꢄ

ꢁꢅꢁꢂ

ꢑꢡRꢟꢑꢀR

Rꢍ

ꢄꢈ

ꢁꢀꢘꢜꢢ

ꢧ

ꢨ ꢅꢇꢥꢩ

ꢓꢞ

ꢒꢪ ꢑꢎꢒꢃꢂꢗꢂ

ꢀꢁA ꢂꢃ ꢄꢀꢁA

ꢀꢁꢂꢃ ꢄꢅ ꢂꢁꢂꢃ

ꢀ

ꢀꢀ

ꢀꢁꢂ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢀ

ꢀꢁA

ꢀꢁꢂ

ꢀꢁA

ꢀꢁꢂ

ALERT

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁAꢂ

ꢆꢇꢈꢉꢊ ꢋꢌꢍꢎRꢄAꢏꢎ

ALERT

ꢀꢁꢂ

Aꢀꢁꢂꢃ

ꢀꢁꢂꢃ ꢄꢁꢅ

Figure 12. Margining a LT8640S from 1.8V to 1.5V at 6A

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

4V < V < 20V, 0.6V < V

LTC3605/LTC3605A 20V, 5A Synchronous Step-Down Regulator

< 20V, 96% Maximum Efficiency,

OUT

IN

4mm × 4mm QFN-24 Package

LTC3626

LTC3636

LTC3779

LTC3784

LTC3807

LTC3871

LTM^®4636

LTC7150S

LT^®8640S

20V, 2.5A Synchronous Step-Down Regulator with Current 95% Efficiency, V : 3.6V to 20V, V

= 0.6V, I = 300µA,

Q

IN

OUT(MIN)

and Temperature Monitoring

ISD < 15µA, 3mm × 4mm QFN-20

20V, Dual 6A Synchronous Step-Down Regulator

95% Efficiency, V : 3.1V to 17V, V

= 0.6V, I < 8µA (Both

Q

IN

OUT(MIN)

Channels Enabled), ISD < 1µA, 3mm × 5mm QFN-24 Package

150V V and V

Synchronous 4-Switch Buck-Boost

4.5V ≤ V ≤ 150V, Input or Output Average Current Loop, PLL,

IN

OUT

IN

DC/DC Controller

TSSOP-38 Package

Low I , Multiphase, Dual Channel Single Output

4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 60V, V

PLL Fixed Frequency 50kHz to 900kHz , I = 28µA

Q

Up to 60V,

OUT

Q

IN

Synchronous Step-Up DC/DC Controller

38V, Low I , Synchronous Step-Down Controller with

PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 38V,

IN

Q

24V Output Voltage Capability

0.8V ≤ V

≤ 24V, I = 50µA

OUT Q

100V Bidirectional PolyPhase^®Buck or Boost Controller

Dynamic Regulation of V , V

and Current, PLL, Current Monitor,

IN OUT

48-Lead LQPF Package

40A DC/DC µModule Step-Down Regulator

20V, 20A Synchronous Step-Down Regulator

42V, 6A Synchronous Step-Down Silent Switcher^®2

Complete 40A Switch Mode Power Supply, 4.75V ≤ V ≤ 15V, 0.6V

IN

≤ V

≤ 3.3V, 16mm × 16mm × 7.12mm BGA

OUT

93% Efficiency, V : 3.1V to 20V, V

= 0.6V, Output Remote

IN

OUT(MIN)

Sense, 42-Lead 6mm × 5mm × 1.3mm BGA Package

I = 2.5µA, V = 3.4V, V = 42V, V = 0

OUT(MIN)

Q

IN(MIN)

OUT(MAX)

Rev A

D16851-0-4/18(A)

www.analog.com

24

For more information www.analog.com


型号：	LTC3779
厂家：	Linear
描述：	A 7-Bit Current DAC with PMBus Interface
文件：	总24页 (文件大小：1669K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3779 [Linear]

相关型号：

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LTC3779IFE#PBF

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LTC3780EG#PBF

LTC3780EG#TR

LTC3780EG-PBF

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LTC3780EUHPBF