LTC3785EUF#TRPBF [Linear]
LTC3785 - 10V, High Efficiency, Synchronous, No RSENSE Buck-Boost Controller; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC3785EUF#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3785 - 10V, High Efficiency, Synchronous, No RSENSE Buck-Boost Controller; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总20页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3785
10V, High Efficiency,
Synchronous, No R
SENSE
Buck-Boost Controller
FeaTures
DescripTion
The LTC®3785 is a high power synchronous buck-boost
controller that drives all N-channel power MOSFETs from
input voltages above, below and equal to the output volt-
age. With an input range of 2.7V to 10V, the LTC3785 is
well suited for a wide variety of single or dual cell Li-Ion
or multicell alkaline/NiMH applications.
n
Single Inductor Architecture Allows V Above,
IN
Below or Equal to V
OUT
n
n
n
n
n
n
n
n
n
n
n
2.7V to 10V Input and Output Range
Up to 96% Efficiency
Up to 10A of Output Current
All N-channel MOSFETs, No R
™
SENSE
True Output Disconnect During Shutdown
Programmable Current Limit and Soft-Start
Optional Short-Circuit Shutdown Timer
Output Overvoltage and Undervoltage Protection
Programmable Frequency: 100kHz to 1MHz
Selectable Burst Mode® Operation
The operating frequency can be programmed from
100kHz to 1MHz. The soft-start time and current limit are
also programmable. The soft-start capacitor doubles as
the fault timer which can program the IC to latch off or
recycle after a determined off time. Burst Mode opera-
tion is user controlled and can be enabled by driving the
MODE pin high.
Available in 24-Lead (4mm × 4mm) Exposed Pad
QFN Package
Protection features include foldback current limit, short-
circuit and overvoltage protection.
applicaTions
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. No R
is a trademark of Linear Technology Corporation.
SENSE
n
Palmtop Computers
All other trademarks are the property of their respective owners.
n
Handheld Instruments
n
Wireless Modems
Cellular Telephones
n
Typical applicaTion
V
IN
2.7V
V
OUT
Efficiency vs Input Voltage
4.7µF
TO 10V
V
IN
V
CC
100
V
= 3.3V
= 500kHz
OUT
OSC
205k
I
SVIN
TG1
F
22µF
V
SENSE
1.3k
270pF
205k 121k
95
90
85
V
BST1
I
= 2A
LOAD
0.22µF
SW1
FB
I
= 1A
LOAD
I
SSW1
121k 12k
1nF
V
DRV
BG1
4.7µH
LTC3785
I
V
C
V
3.3V
5A
59k
OUT
RT
SVOUT
TG2
MODE
2.5
5.5
7
8.5
10
4
V
(V)
IN
3785 TA01b
V
BST2
0.22µF
RUN/SS
SW2
100µF
I
I
LSET
SSW2
42.2k
CCM
BG2
1nF
GND
3785 TA01a
3785fc
ꢀ
LTC3785
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
Input Supply Voltage (V )......................... –0.3V to 11V
IN
I
, I
.............................................. –0.3V to 11V
SVOUT SVIN
SW1, SW2, I
24 23 22 21 20 19
, I
Voltage:
SSW1 SSW2
RUN/SS
1
2
3
4
5
6
18
17
16
I
SSW1
DC............................................................. –1V to 11V
Pulsed, <1µs............................................. –2V to 12V
V
C
BG1
V
FB
DRV
25
GND
RUN/SS, MODE, CCM, V , V Voltages.. –0.3V to 6V
DRV CC
V
15 BG2
14
13 SW2
SENSE
V
BST1
Voltage............................................. –0.3V to 16V
I
I
LSET
SSW2
With Respect to SW1............................... –0.3V to 6V
Voltage............................................. –0.3V to 16V
CCM
V
BST2
7
8
9 10 11 12
With Respect to SW2............................... –0.3V to 6V
Peak Driver Output Current < 10µs
(TG1, TG2, BG1, BG2).................................................3A
UF PACKAGE
24-LEAD (4mm s 4mm) PLASTIC QFN
V
Average Output Current.................................100mA
T
JMAX
= 125°C, θ = 40°C/W 1 LAYER BOARD, θ = 30°C/W 4 LAYER BOARD
JA JA
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
CC
Operating Junction Temperature Range
(Note 2)..................................................–40°C to 125°C
Junction Temperature ........................................... 125°C
Storage Temperature Range...................–65°C to 150°C
orDer inForMaTion
LEAD FREE FINISH
LTC3785EUF#PBF
LTC3785IUF#PBF
LEAD BASED FINISH
LTC3785EUF
TAPE AND REEL
LTC3785EUF#TRPBF
LTC3785IUF#TRPBF
TAPE AND REEL
LTC3785EUF#TR
LTC3785IUF#TR
PART MARKING*
3785
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
PACKAGE DESCRIPTION
3785
–40°C to 125°C
PART MARKING*
3785
TEMPERATURE RANGE
–40°C to 85°C
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
LTC3785IUF
3785
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
The l denotes the specifications which apply over the full operating junction
elecTrical characTerisTics
temperature range, otherwise specifications are at TA = 25°C. VIN = ISVOUT = VDRV = VBST1 = VBST2 = 3.6V, RT = 49.9k, RILSET = 59k.
PARAMETER
Supply
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
l
Input Operating Voltage
Quiescent Current—Burst Mode Operation
Quiescent Current—Shutdown
Quiescent Current—Active
Error Amp
2.7
10
200
25
V
µA
V = 0V, MODE = 3.6V (Note 4)
86
15
0.8
C
RUN/SS = 0V, I
= 3.6V
µA
SVOUT
MODE = 0V (Note 4)
1.5
mA
l
Feedback Voltage
(Note 5)
1.200
1.225
1
1.25
500
V
Feedback Input Current
nA
3785fc
ꢁ
LTC3785
elecTrical characTerisTics The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. VIN = ISVOUT = VDRV = VBST1 = VBST2 = 3.6V, RT = 49.9k, RILSET = 59k.
PARAMETER
CONDITIONS
MIN
TYP
–500
900
90
MAX
UNITS
µA
Error Amp Source Current
Error Amp Sink Current
µA
Error Amp A
dB
VOL
Overvoltage Threshold
V
V
V
Pin % Above FB
SENSE
LTC3785E
LTC3785I
l
l
6
6
10
10
14
15
%
%
Undervoltage Threshold
Pin % Below FB
LTC3785E
LTC3785I
SENSE
l
l
–3.5
–3.5
–6.5
–6.5
–9.5
–10.5
%
%
V
V
V
V
V
Input Current
= Measured FB Voltage
SENSE
1
500
nA
SENSE
Regulator
CC
CC
CC
CC
l
l
Maximum Regulating Voltage
Regulation Voltage
V
V
= 5V, I
= –20mA
VCC
4.15
3.3
4.35
3.5
4.55
3.6
V
V
IN
= 3.6V, I
= –20mA
VCC
IN
Regulator Sink Current
I
= V = 5V
800
µA
SVOUT
CC
Run/Soft-Start
l
RUN/SS Threshold
When IC is Enabled
0.35
0.7
1.9
1.1
30
V
V
When EA is at Maximum Boost Duty Cycle
RUN/SS Input Current
RUN/SS Discharge Current
Current Limit
RUN/SS = 0V
–1
20
µA
µA
During Current Limit
l
l
Current Limit Sense Threshold
I
I
to I
, R
SSW1 ILSET
SSW1 ILSET
= 121k
= 59k
20
55
60
105
100
155
mV
mV
SVIN
SVIN
to I
, R
Reverse Current Limit Sense Threshold
Input Current
I
I
I
to I
, CCM > 2V
–50
–110
–15
–170
–35
mV
mV
mV
SSW2
SSW2
SSW2
SVOUT
SVOUT
SVOUT
l
l
to I
to I
, CCM < 0.4V, LTC3785E
, CCM < 0.4V, LTC3785I
–15
–40
I
I
I
80
10
0.1
150
20
5
µA
µA
µA
SVIN
SVOUT
SSW1 SSW2
, I
l
l
CCM Input Threshold (High)
CCM Input Threshold (Low)
CCM Input Current
2.2
0.8
V
V
0.4
1
CCM = 3.6V
0.01
µA
Burst Mode Operation
Mode Threshold
l
1.5
0.01
1.4
2.2
1
V
µA
µs
Mode Input Current
t
Time
ON
Oscillator
l
l
Frequency Accuracy
Switching Characteristics
Maximum Duty Cycle
370
80
509
650
kHz
Boost (% Switch BG2 On)
Buck (% Switch TG1 On)
90
99
%
%
TG1, TG2 Driver Impedance
BG1, BG2 Driver Impedance
TG1, TG2 Rise Time
2
2
Ω
Ω
C
= 3300pF (Note 3)
20
ns
LOAD
3785fc
ꢂ
LTC3785
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. VIN = ISVOUT = VDRV = VBST1 = VBST2 = 3.6V, RT = 49.9k, RILSET = 59k.
PARAMETER
CONDITIONS
MIN
TYP
20
MAX
UNITS
ns
BG1, BG2 Rise Time
TG1, TG2 Fall Time
C
LOAD
C
LOAD
C
LOAD
= 3300pF (Note 3)
= 3300pF (Note 3)
= 3300pF (Note 3)
20
ns
BG1, BG2 Fall Time
20
ns
Buck Driver Nonoverlap Time
Boost Driver Nonoverlap Time
TG1 to BG1
TG2 to BG2
100
100
ns
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
to meet performance specifications over the full –40°C to 125°C operating
junction temperature range.
Note 3: Specification is guaranteed by design and not 100% tested in
production.
Note 2: The LTC3785E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3785I is guaranteed
Note 4: Current measurements are performed when the outputs are not
switching.
Note 5: The IC is tested in a feedback loop to make the measurement.
Typical perForMance characTerisTics
TA = 25°C, unless otherwise noted.
Li-Ion to 3.3V Efficiency
vs Load Current
Two Li-Ion to 7V Efficiency
vs Load Current
Li-Ion/9V to 5V VOUT Efficiency
vs Load Current
100
90
100
90
80
70
60
50
40
30
20
10
0
100
90
Burst Mode
OPERATION
Burst Mode
OPERATION
Burst Mode
OPERATION
80
80
70
70
FIXED
FREQUENCY
FIXED
FREQUENCY
FIXED
FREQUENCY
60
50
60
50
V
IN
V
IN
V
IN
V
IN
= 9V
40
30
20
10
0
40
30
20
10
0
V
V
V
= 4.2V
= 3.6V
= 3V
= 4.2V
= 3.6V
= 2.7V
V
= 8.4V
= 7.2V
= 5.4V
IN
IN
IN
IN
IN
IN
V
V
MOSFET Si7940
L = 4.7µH WURTH WE-PD
MOSFET Si7940
MOSFET Si7940
L = 5.6µH MSS1260
L = 5.6µH MSS1260
f
= 500kHz
f
= 430kHz
f
= 430kHz
OSC
OSC
OSC
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
3785 G03
3785 G02
3785 G01
Burst Mode Ripple
Line Transient Response
VOUT Load Transient
V
V
OUT
OUT
200mV/
DIV
500mV/
DIV
V
OUT
50mV/DIV
AC
COUPLED
V
IN
3V TO
8.5V
INDUCTOR
CURRENT
1A/DIV
I
LOAD
10mA TO 2A
3785 G04
3785 G05
3785 G06
V
C
= 3.3V
= 100µF
5µs/DIV
I
V
C
= 300mA 500µs/DIV
V
V
C
= 3.6V
100µs/DIV
OUT
OUT
LOAD
OUT
OUT
IN
= 5V
= 3.3V
OUT
OUT
= 100µF
= 100µF
3785fc
ꢃ
LTC3785
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Normalized Oscillator Frequency
vs Temperature
VFB vs Temperature
Oscillator Frequency vs RT
1.2255
1.2250
1.2245
1.2240
1.2235
1.2230
1.2225
1.2220
1.2215
1200
1000
1.0
0.8
0.6
0.4
800
600
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
400
200
0
50
100 125 150
20
40
60
80
100
–50 –25
0
25
75
50
100 125 150
–50 –25
0
25
75
RT (kΩ)
TEMPERATURE (°C)
TEMPERATURE (°C)
3785 G07
3785 G08
3785 G09
VIN Start-Up Voltage
vs Temperature
VIN Burst Quiescent Current
vs Temperature
OV and UV Thresholds
vs Temperature
2.490
2.485
2.480
2.475
12
10
8
100
95
90
85
80
OV THRESHOLD
6
4
2
0
–2
–4
–6
–8
2.470
2.465
UV THRESHOLD
50
100 125 150
–50 –25
0
25
75
50
100 125 150
50
100 125 150
–50 –25
0
25
75
–50 –25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3785 G10
3785 G12
3785 G11
pin FuncTions
RUN/SS (Pin 1): Run Control and Soft-Start Input. An
internal 1µA charges the soft-start capacitor and will
charge to approximately 2.5V. During a current limit fault,
the soft-start capacitor will incrementally discharge. Once
the pin drops below 1.225V the IC will enter fault mode,
turning off the outputs for 32 times the soft-start time. If
>5µA (at RUN/SS = 1.225V) is applied externally, the part
will latch off after a fault is detected. If >40µA (at RUN/SS
= 1.225V) is applied externally, current limit faults will not
discharge the SS capacitor.
V (Pin 2): Error Amp Output. A frequency compensa-
C
tion network is connected from this pin to the FB pin to
compensate the loop. See Closing the Feedback Loop in
the Applications Information section for guidelines.
FB (Pin 3): Feedback Pin. Connect resistor divider tap
here. The feedback reference voltage is typically 1.225V
The output voltage can be adjusted from 2.7V to 10V ac-
cording to the following formula:
R1+R2
VOUT =1.225V •
R2
3785fc
ꢄ
LTC3785
pin FuncTions
V
(Pin 4): Overvoltage and Undervoltage Sense.
SW2 (Pin 13): Ground Reference for Driver D. Gate drive
from TG2 will reference to the common point of output
switches C and D.
SENSE
The overvoltage threshold is internally set 10% above
the regulated FB voltage and the undervoltage threshold
is internally set 6.5% below the FB regulated voltage. This
pin can be tied to FB but to optimize the response time it
I
(Pin 14): Reverse Current Limit Comparator Invert-
SSW2
ing Input. This pin is normally connected to the source of
is recommended that a voltage divider from V
be ap-
OUT
the N-channel MOSFET D (TG2 driven).
plied. The divider can be skewed from the feedback value
to achieve the desired UV or OV threshold.
V
(Pin 16): Driver Supply for Ground Referenced
DRV
Switches. Connect this pin to V potential.
CC
I
(Pin 5): Current Limit Set. A resistor from this pin
LSET
BG1, BG2 (Pins 17, 15): Bottom gate driver pins drive
the ground referenced N-channel MOSFET switches B
and C.
to ground sets the current limit threshold from the I
SVIN
and I
pins.
SSW1
CCM (Pin 6): Continuous Conduction Mode Control Pin.
I
(Pin 18): Forward Current Limit Comparator Non-
Whensetlow, theinductorcurrentisallowedtogoslightly
SSW1
inverting Input. This pin is normally connected to the
negative (–15mV referenced to the I
– I
pins).
SVOUT
SSW2
source of the N-channel MOSFET A (TG1 driven).
When driven high, the reverse current limit is set to the
similar value of the forward current limit set by the I
pin.
LSET
SW1 (Pin 19): Ground Reference for Driver A. Gate drive
from TG1 will reference to the common point of output
switches A and B.
RT(Pin7):OscillatorProgrammingPin.Aresistorfromthis
pin to GND sets the free-running frequency of the IC.
TG1, TG2 (Pins 20, 12): Top gate drive pins drive the
top N-channel MOSFET switches A and D with a voltage
25000
RT
fOSC
≅
MHz
swing equal to V – V
superimposed on the SW1
CC
DIODE
and SW2 nodes respectively.
V
(Pin 21): Boosted Floating Driver Supply for the
MODE (Pin 8): Burst Mode Control Pin.
BST1
Buck Switch A. This pin will swing from a diode below
• MODE = High: Enable Burst Mode Operation. In Burst
Mode operation the operation is variable frequency,
which provides a significant efficiency improvement
at light loads. The Burst Mode operation will continue
until the pin is driven low.
V
up to V + V – V
.
CC
IN
CC
DIODE
I
(Pin 22): Forward Current Limit Comparator Invert-
SVIN
ing Input. This pin is normally connected to the drain of
N-channel MOSFET A (TG1 driven).
V
(Pin 23): Internal 4.35V LDO Regulator Output. The
• MODE=Low:DisableBurstModeoperationandmaintain
low noise, constant frequency operation.
CC
driver and control circuits are powered from this voltage
to limit the maximum VGS drive voltage. Decouple this pin
to power ground with at least a 4.7µF ceramic capacitor.
NC (Pin 9): No Connect. There is no electrical connection
to this pin inside the package.
For low V applications, V can be bootstrapped from
V
IN
CC
I
(Pin 10): Reverse Current Limit Comparator Non-
through a Schottky diode.
SVOUT
OUT
invertingInput. Thispinisnormallyconnectedtothedrain
V
(Pin 24): Input Supply Pin for the V Regulator. A
CC
IN
of the N-channel MOSFET D (TG2 driven).
ceramic capacitor of at least 10µF is recommended close
V
(Pin 11): Boosted Floating Driver Supply for Boost
to the V and GND pins.
BST2
IN
Switch D. This pin will swing from a diode below V up
CC
Ground (Exposed Pad Pin 25): The GND and PGND pins
are connected to the exposed pad which must be con-
nected to the PCB ground for electrical contact and rated
to V
+ V – V
.
OUT
CC
DIODE
thermal performance.
3785fc
ꢅ
LTC3785
block DiagraM
V
IN
2.7V TO 10V
24
V
IN
1.225V
+
–
–
+
FAULT
LOGIC
TSD
100% DUTY
CHARGE PUMP
1.225V
V
4.35V REG
IDEAL DIODE
REF
C
VCC
V
CC
V
+
23
22
BE
RUN UVLO
I
2.4V
–
SVIN
1/25k
I
+
–
LIMIT
g
m
1µA
C
SS
RUN/SS
1
V = 60k/R
ILSET
2µA
TG1
ADRV
MA
C
IN
20
21
19
18
16
17
V
I
+
–
BST1
LIM(OUT)
+
–
X10
I
I
LIM(OUT)
MAX
C
A
SW1
SW1
10µA MAX
V = 90k/R
ILSET
I
SSW1
SAMPLED
TG1
BBM
SW1
DELAY
D1
OPT
SW1
PULSE
V
DRV
–6.5%
+10%
+
–
UV
BG1
UV
OV
V
V
OUT
OUT
BG1
BDRV
MB
–
+
OV
V
OUT
LOW
–
+
V
SENSE
1.8V
4
TG2
BG2
PGND
BBM
SW2
SW2
PULSE
15mV
OR
1X I
+
–
DELAY
L1
1.225V
+
–
R1
100% DUTY
CHARGE PUMP
FB
LIMIT
3
2
I
DISABLE
SVOUT
TG2
C
P1
V
10
R2
OUT
REVERSE
LIMIT
V
C
D2
OPT
V
REV
REVERSE
CURRENT LIMIT
(ZERO LIMIT FOR BURST)
R
T
RT
MD
12
11
OSC
DDRV
7
V
BST2
1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
C
B
SW2
–
+
13
14
1.5V
BURST
LOGIC
BURST
SW2
MC
MODE
I
SSW2
8
5
SAMPLED
V
DRV
SS
BG2
CDRV
15
6
C
OUT
R
ILSET
I
LSET
I
I
COMP
COMP
I
LIM
LIMIT
SET
MAX
PGND
1/2 LIMIT AT V
OUT
< 1V
CCM
0 = 15mV
1 = I
V
REV
LIMIT
GND/PGND
25
3785 BD
3785fc
ꢆ
LTC3785
operaTion
MAIN CONTROL LOOP
V
V
OUT
IN
The LTC3785 is a buck-boost voltage mode controller that
provides an output voltage above, equal to or below the
input voltage.
TG1
BG1
D
A
TG2
BG2
L
SW1
SW2
C
B
TheLTCproprietarytopologyandcontrolarchitecturealso
employsdrain-to-sourcesensing(NoR )forforward
SENSE
3785 F01
and reverse current limiting. The controller provides
all N-channel MOSFET output switch drive, facilitating
single package multiple power switch technology along
Figure 1. Output Switch Configuration
with lower R
. The error amp output voltage (V )
DS(ON)
C
determines the output duty cycle of the switches. Since
90%
MAX
the V pin is a filtered signal, it provides rejection of high
C
D
BOOST
frequency noise.
A ON, B OFF
BOOST REGION
PWM C, D SWITCHES
The FB pin receives the voltage feedback signal, which
is compared to the internal reference voltage by the er-
ror amplifier. The top MOSFET drivers are biased from a
floating bootstrap capacitor, which is normally recharged
during each off cycle through an external diode when the
top MOSFET turns off. Optional Schottky diodes can be
connected across synchronous switch B and D to provide
a lower drop during the dead time and eliminate efficiency
loss due to body diode reverse recovery.
D
MIN
BOOST
FOUR SWITCH PWM
BUCK/BOOST REGION
D
MAX
BUCK
D ON, C OFF
PWM A, B SWITCHES
BUCK REGION
D
BUCK
MIN
3785 F02
Figure 2. Operation Mode vs VC Voltage
theofftimeofswitchA, synchronousswitchBturnsonfor
theremainderoftheswitchingperiod.SwitchesAandBwill
alternate similar to a typical synchronous buck regulator.
As the control voltage increases, the duty cycle of switch
A increases until the max duty cycle of the converter in
The main control loop is shut down by pulling the RUN/
SS pin low. An internal 1µA current source charges the
RUN/SS pin and when the pin voltage is higher than 0.7V
the IC is enabled. The V voltage is then clamped to the
C
RUN/SS voltage minus 0.7V while C is slowly charged
SS
buck mode reaches D
, given by:
MAX_BUCK
during start-up. This soft-start clamping prevents inrush
D
= 100 – D4(SW)%
current draw from the input power supply.
MAX_BUCK
where D4(SW) = duty cycle % of the four switch range.
D4(SW) = (300ns • f) • 100%
POWER SWITCH CONTROL
Figure1showsasimplifieddiagramofhowthefourpower
switchesareconnectedtotheinductor,V ,V andGND.
Figure 2 shows the regions of operation for the LTC3785
as a function of duty cycle D. The power switches are
properly controlled so that the transfer between modes
is continuous.
where f = operating frequency, Hz.
IN OUT
Beyond this point the four switch or buck-boost region
is reached.
Buck-Boost or Four Switch (V ~ V
)
OUT
IN
When the error amp output voltage, V , is above ap-
C
Buck Region (V > V
)
IN
OUT
proximately 0.65V, switch pair AD remain on for duty
cycle D
, and the switch pair AC begin to phase
Switch D is always on and switch C is always off during
MAX_BUCK
in. As switch pair AC phases in, switch pair BD phases
buck mode. When the error amp output voltage, V , is ap-
C
out accordingly. When the V voltage reaches the edge of
proximately above 0.1V, output A begins to switch. During
C
3785fc
ꢇ
LTC3785
operaTion
the buck-boost range, approximately 0.7V, the AC switch
pair completely phase out the BD pair, and the boost phase
begins at duty cycle, D4(SW).
So the peak current is independent of V and inversely
IN
proportional to the f • L product optimizing the energy
transfer for various applications.
Theinputvoltage,V ,wherethefourswitchregionbegins
In Burst Mode operation the maximum output current is
IN
is given by:
given by:
1.2• VIN
VOUT
1– 300ns• f
IOUT(MAX,BURST)
≈
A
V =
V
f •L • VOUT + VIN
IN
the point at which the four switch region ends is given
by:
Burst Mode operation is user-controlled by driving the
MODE pin high to enable and low to disable.
V = V (1 – D) = V (1 – 300ns • f) V
IN
OUT
OUT
V
REGULATOR
CC
Boost Region (V < V
)
OUT
IN
An internal P-channel low dropout regulator produces
4.35V at the V pin from the V supply pin. V powers
the drivers and internal circuitry of the LTC3785. The V
Switch A is always on and switch B is always off during
boostmode. Whentheerrorampoutputvoltage, V , isap-
CC
IN
CC
C
CC
proximatelyabove0.7V, switchpairCandDwillalternately
switchtoprovideaboostedoutputvoltage. Thisoperation
is typical to a synchronous boost regulator. The maximum
duty cycle of the converter is limited to 90% typical.
pin regulator can supply a peak current of 100mA and
must be bypassed to ground with a minimum of 4.7µF
placed directly adjacent to the V and GND pins. Good
CC
bypassing is necessary to supply the high transient cur-
rent required by the MOSFET gate drivers and to prevent
interactionbetweenchannels. Ifdesired, theV regulator
CC
Burst Mode OPERATION
can be connected to V
through a Schottky diode to
OUT
DuringBurstModeoperation,theLTC3785deliversenergy
to the output until it is regulated and then goes into a sleep
state where the outputs are off and the IC is consuming
only 86µA. In Burst Mode operation, the output ripple
has a variable frequency component, which is dependent
upon load current.
providehighergatedriveinlowinputvoltageapplications.
The V regulator can also be driven with an external 5V
CC
source directly (without a Schottky diode).
TOPSIDE MOSFET DRIVER SUPPLY (V , V
BST1 BST2
)
The external bootstrap capacitors connected to the V
BST1
During the period where the converter is delivering en-
ergy to the output, the inductor will reach a peak current
and V
pins supply the gate drive voltage for the top-
BST2
side MOSFET switches A and D. When the top MOSFET
switch A turns on, the switch node SW1 rises to V and
determined by an on time, t , and will terminate at zero
ON
IN
current for each cycle. The on time is given by:
the V
pin rises to approximately V + V . When the
BST2
IN CC
2.4
VIN • f
bottom MOSFET switch B turns on, the switch node SW1
tON
=
drops low and the boost capacitor is charged through the
diode connected to V . When the top MOSFET switch D
CC
where f is the oscillator frequency.
The peak current is given by:
turns on, the switch node SW2 rises to V
pin rises to approximately V
and the V
+ V . When the bottom
OUT
BST2
OUT
CC
MOSFET switch C turns on, the switch node SW2 drops
V
L
2.4
f •L
IN • tON
low and the boost capacitor is charged through the diode
IPEAK
IPEAK
=
=
connectedtoV .Theboostcapacitorsneedtostoreabout
CC
100 times the gate charge required by the top MOSFET
3785fc
ꢈ
LTC3785
operaTion
switch A and D. In most applications a 0.1µF to 0.47µF,
X5R or X7R dielectric capacitor is adequate.
with both comparators having 1.5% hysteresis. During
an overvoltage fault, all output switching stops until the
fault ceases. During an undervoltage fault, the IC is com-
manded to run fixed frequency only (disabled Burst Mode
operation). If the design requires a tightened threshold to
one of the comparator thresholds the voltage divider on
RUN/SOFT-START (RUN/SS)
The RUN/SS pin serves as the enable to the LTC3785,
soft-start function, and fault programming. A 1µA current
source charges the external capacitor. Once the RUN/SS
voltageisaboveadiodedrop(~0.7V)theICisenabled.Once
the IC is enabled, the RUN/SS voltage minus a diode drop
the V
pin can be skewed to achieve the threshold.
SENSE
Since the range is a constant, tightening the UV threshold
will loosen the OV threshold and vice versa.
(RUN/SS – 0.7V) clamps the output of the error amp (V )
C
FORWARD CURRENT LIMIT
to limit duty cycle. The range of the duty cycle clamping is
approximately 0.7V to 1.7V. The RUN/SS pin is clamped
to approximately 2.2V. If current limit is reached the pin
will begin to discharge with a current determined by the
magnitude of inductor current overcurrent limit, but not
to exceed 10µA. This function will be described in more
detail in the Forward Current Limit section.
TheLTC3785isdesignedtosensetheinputcurrentbysam-
plingthevoltageacrossMOSFETAduringtheontimeofthe
switch (TG1 = High). The sense pins are I
and I
. A
SSW1
SVIN
currentsenseresistorcanbeusedifincreasedaccuracyis
required. The current limit threshold can be programmed
with a resistor on the I
pin. Once the desired current
ILSET
LSET
limit has been chosen, R
can be determined by the
following formula:
OSCILLATOR
6000
RDS(ON)A •ILIMIT
The frequency of operation is set through a resistor from
the RT pin to ground where:
RILSET
=
Ω
where R
= R of N-channel MOSFET switch A
25000
RT
DS(ON)A
DS(ON)
fOSC
≅
MHz
and I
= current limit in Amps.
LIMIT
Once the voltage between I
and I
exceeds the
SSW1
SVIN
threshold, current will be sourced out of FB to take control
of the voltage loop, resulting in a lower output voltage
to regulate the input current. This fault condition causes
the RUN/SS capacitor to begin discharging. The level of
the discharge current depends on how much the current
exceeds the programmed threshold. Figure 3 is a simpli-
fied diagram of the current sense and fault circuitry. If the
current limit fault duration is long enough to discharge the
RUN/SS capacitor below 1.225V, the fault latch is set and
will cycle the RUN/SS capacitor 16 times (1µA charging
and1µAdischargingoftheRUN/SScapacitor)tocreatean
off time of 32 times the soft-start time before the outputs
are allowed to switch to restart the output voltage. If the
current limit fault level exceeds 150% of the programmed
ERROR AMP
The error amplifier is a voltage mode amplifier with a
reference voltage of 1.225V internally connected to the
non-inverting input. The loop compensation components
are configured around the amplifier to provide loop com-
pensationfortheconverter. TheRUN/SSpinwillclampthe
error amp output, V , to provide a soft-start function.
C
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
The LTC3785 incorporates overvoltage (OV) and
undervoltage (UV) functions for fault protection and
transient limitation. Both comparators are connected
to the V
pin, which usually has a similar voltage
SENSE
I
level at any time, the I
comparator is tripped and
LIMIT
MAX
divider as the error amplifier without the compensation.
The overvoltage threshold is 10% above the reference.
The undervoltage threshold is 6.5% below the reference
output switches B and D are turned on to discharge the
inductor current for the remainder of the cycle.
3785fc
ꢀ0
LTC3785
operaTion
To have the power converter latch off on a fault, a pull-up
currentbetween4µAand7µAontheRUN/SSpinwillallow
the RUN/SS capacitor to discharge during an extended
fault,butwillpreventcyclingofthefaultwhichwillcausethe
converter to stay off. One method to implement this is by
During an output short-circuit or if V
the current limit folds back to 50% of the programmed
level.
is less than 1.8V,
OUT
REVERSE CURRENT LIMIT
placingadiode(anodetiedtoV )andaresistorfromV
OUT
OUT
The LTC3785 can be programmed to provide full class D
operation or allowed to source and sink current equal to
the current limit set value. This is achieved by asserting a
high level on the CCM pin. To minimize the reverse output
current, the CCM pin should be driven low or strapped to
ground. During this mode only, –15mV typical is allowed
totheRUN/SSpin.ThecurrentsourcedintoRUN/SSwillbe
V
OUT
–0.7dividedbytheresistorvalue. Toignoreallfaults
sourcegreaterthan40µAintotheRUN/SSpin(At1.225Von
theRUN/SSpin).Sincethemaximumfaultcurrentislimited,
this will prevent any discharging of the RUN/SS capacitor,
the soft-start capacitor will need to be sized accordingly to
accommodatetheextrachargingcurrentatstart-up.
across output switch D and is sensed with the I
and
SVOUT
I
pins.
SSW2
THERMAL SD
S FAULT
I
COMP
V
LIMIT
IN
1.225V
+
–
–
+
I
SVIN
g
= 1/20k
m
S LOGIC
+
–
22
20
g
m
A
TG1
V = 60k/R
ILSET
ILSET
0.7V
(15k/R
WHEN V
< 1.8V)
RUN
OUT
SW1
19
18
I
COMP
MAX
1µA
+
–
RUN/SS
TURN
I
+
–
X10
1
4
SSW1
SWITCHES
SAMPLED
C
SS
B AND D ON
2.2V
V = 90k/R
ILSET
1/3 • I
LIM(OUT)
BG1 17
B
D
2µA
10µA MAX
L1
CCM
6
CCM = HIGH = 6k/R
ILSET
I
LIM(OUT)
30µA MAX
CCM = LOW = 15mV
V
OUT
I
SVOUT
–
+
+
–
V
10
12
OUT
SWITCH D
OFF
ERROR AMP
1.225V
+
–
R1
C
OUT
REVERSE
CURRENT LIMIT
FB
TG2
3
2
C
P1
V
C
SW2
13
14
15
R2
I
SSW2
BG2
SAMPLED
I
LSET
I
I
COMP
COMP
I
LIM
LIMIT
SET
5
MAX
C
R
ILSET
3785 F03
Figure 3. Block Diagram of Current Limit Fault Circuitry
3785fc
ꢀꢀ
LTC3785
applicaTions inForMaTion
INDUCTOR SELECTION
This formula has a maximum at V = 2V , where I
OUT(MAX)
=
RMS
IN
OUT
I
/2.Thissimpleworst-caseconditioniscommonly
The high frequency operation of the LTC3785 allows the
use of small surface mount inductors. The inductor cur-
rent ripple is typically set 20% to 40% of the maximum
inductor current. For a given ripple the inductance terms
are given as follows:
usedfordesignbecauseevensignificantdeviationsdonot
offer much relief. Note that ripple current ratings from ca-
pacitormanufacturersareoftenbasedononly2000hours
of life which makes it advisable to derate the capacitor.
In boost mode, the discontinuous current shifts from the
input to the output, so C
must be capable of reducing
VIN(MIN)2 • VOUT – VIN(MIN) •100
OUT
(
)
the output voltage ripple. The effects of ESR (equivalent
series resistance) and the bulk capacitance must be
considered when choosing the right capacitor for a given
output ripple voltage. The steady ripple due to charging
and discharging the bulk capacitance is given by:
L >
L >
, (Boost Mode)
2
f •IOUT(MAX) •%Ripple• VOUT
VOUT • VIN(MAX) – VOUT •100
(
)
, (Buck Mode)
f •IOUT(MAX) •%Ripple• V
IN(MAX)
where:
f = Operating frequency, Hz
%Ripple = Allowable inductor current ripple, %
= Minimum input voltage (limit to V /2
IOUT(MAX) • VOUT – VIN(MIN)
(
)
VRIPPLE _BOOST
=
COUT • VOUT • f
VOUT • VIN(MAX) – VOUT
8•L •COUT • VIN(MAX) • f2
(
)
VRIPPLE _BUCK
=
V
IN(MIN)
OUT
minimum for worst-case), V
V
V
= Maximum input voltage, V
where C = output filter capacitor, F
OUT
IN(MAX)
= Output voltage, V
The steady ripple due to the voltage drop across the ESR
is given by:
OUT
I
= Maximum output load current, A
OUT(MAX)
ꢀ DV
= I
• ESR
Forhighefficiencychooseaninductorwithahighfrequency
core material, such as ferrite, to reduce core loses. The
inductorshouldhavelowESR(equivalentseriesresistance)
BOOST,ESR
L(MAX,BOOST)
V
IN(MAX) – VOUT • V
(
)
OUT
DVBUCK,ESR
=
•ESR
2
L • f • V
to reduce the I R losses, and must be able to handle the
IN
peak inductor current without saturating. Molded chokes
or chip inductors usually do not have enough core to sup-
port the peak inductor currents in the 3A to 6A region. To
minimize radiated noise, use a toroid, pot core or shielded
bobbin inductor.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings such as OS-CON and POSCAP.
C AND C
SELECTION
IN
OUT
In boost mode, input current is continuous. In buck mode,
inputcurrentisdiscontinuous.Inbuckmode,theselection
POWER N-CHANNEL MOSFET SELECTION AND
EFFICIENCY CONSIDERATIONS
of input capacitor, C , is driven by the need to filter the
IN
input square wave current. Use a low ESR capacitor, sized
to handle the maximum RMS current. For buck operation,
the maximum RMS capacitor current is given by:
The LTC3785 requires four external N-channel power
MOSFETs, two for the top switches (switches A and D,
shown in Figure 1) and two for the bottom switches
(switches B and C shown in Figure 1). Important param-
VOUT
VIN
VOUT
VIN
IRMS ~IOUT(MAX)
•
• 1–
3785fc
ꢀꢁ
LTC3785
applicaTions inForMaTion
eters for the power MOSFETs are the breakdown voltage
Switch C operates in boost mode as the control switch. Its
power dissipation at maximum current is given by:
V
,thresholdvoltageV
,on-resistanceR
RSS
,
BR(DSS)
GS(TH)
DS(ON)
reverse transfer capacitance C
and maximum current
V
OUT – V • V
(
PC(BOOST)=
)
IN OUT
DS(MAX)
CC
•IOUT(MAX)2 •ρT
I
. The drive voltage is set by the 4.5V V supply.
2
V
Consequently,logic-levelthresholdMOSFETsmustbeused
in LTC3785 applications. If the input voltage is expected to
drop below 5V, then sub-logic threshold MOSFETs should
be considered. In order to select the power MOSFETs, the
power dissipated by the device must be known.
IN
IOUT(MAX)
3
• RDS(ON) +k • VOUT
•
•CRSS • f
V
IN
whereC isusuallyspecifiedbytheMOSFETmanufactur-
RSS
ers. The constant k, which accounts for the loss caused by
reverse recovery current, is inversely proportional to the
gate drive current and has an empirical value of 1.0.
For switch A, the maximum power dissipation happens
in boost mode, when it remains on all the time. Its maxi-
mum power dissipation at maximum output current is
given by:
For switch D, the maximum power dissipation happens in
boost mode when its duty cycle is higher than 50%. Its
maximum power dissipation at maximum output current
is given by:
2
VOUT
PA(BOOST)=
•IOUT(MAX) •ρT •RDS(ON)
V
IN
where ρT is a normalization factor (unity at 25°C) ac-
counting for the significant variation in on-resistance with
temperature,typicallyabout0.4%/°CasshowninFigure 4.
For a maximum junction temperature of 125°C, using a
value ρT = 1.5 is reasonable.
VOUT
PD BOOST =
•IOUT(MAX)2 •ρT •RDS(ON)
(
)
V
IN
Typically, switch A has the highest power dissipation and
switch B has the lowest power dissipation unless a short
occurs at the output. From a known power dissipated
in the power MOSFET, its junction temperature can be
obtained using the following formula:
Switch B operates in buck mode as the synchronous
rectifier. Its power dissipation at maximum output current
is given by:
T = T + P • R
J
A
TH(JA)
VIN – VOUT
PB(BUCK)=
•IOUT(MAX)2 •ρT •RDS(ON)
The R
to be used in the equation normally includes
for the device plus the thermal resistance from
TH(JA)
VIN
the R
TH(JC)
the case to the ambient temperature (R
). This value
TH(CA)
2.0
1.5
1.0
0.5
of T can then be compared to the original, assumed value
J
used in the iterative calculation process.
SCHOTTKY DIODE (D1, D2) SELECTION
Optional Schottky diodes D1 and D2 shown in the Block
Diagramconductduringthedeadtimebetweentheconduc-
tion of the power MOSFET switches. They are intended to
prevent the body diode of synchronous switches B and D
from turning on and storing charge during the dead time.
In particular, D2 significantly reduces reverse recovery
current between switch D turn off and switch C turn on,
whichimprovesconverterefficiencyandreducesswitchC
voltage stress. In order for D2 to be effective, it must be
located in very close proximity to SWD.
0
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
3785 F04
Figure 4. Normalized RDS(ON) vs Temperature
3785fc
ꢀꢂ
LTC3785
applicaTions inForMaTion
CLOSING THE FEEDBACK LOOP
A simple Type I compensation network (Figure 5) can be
incorporated to stabilize the loop but at a cost of reduced
bandwidthandslowertransientresponse.Toensureproper
phase margin, the loop must cross over almost a decade
before the L-C double pole.
The LTC3785 incorporates voltage mode control. The
control to output gain is given by:
GBUCK =1.6• V , Buck Mode
IN
The unity gain frequency of the error amplifier with the
Type I compensation is given by:
2
1.6• VOUT
GBOOST
=
, Boost Mode
VIN
1
fUG
=
2•π •R1•CP1
The output filter exhibits a double-pole response and is
given by:
Mostapplicationsdemandanimprovedtransientresponse
toallowasmalleroutputfiltercapacitor.Toachieveahigher
bandwidth, Type III compensation is required as shown
in Figure 6. Two zeros are required to compensate for the
double pole response.
1
fFILTER _POLE
=
2•π • L •COUT
where C
is the output filter capacitor.
OUT
The output filter zero is given by:
1
fPOLE1
fZERO1
fZERO2
fPOLE2
≈
=
=
≈
(a very low frequency)
2•π •32e3•CP1 •R1
1
fFILTER _ ZERO
=
1
2•π •RESR •COUT
2•π •RZ •CP1
1
2•π •R1•CZ1
1
whereR isthecapacitorequivalentseriesresistance.
ESR
Atroublesomefeatureinboostmodeistherighthalfplane
zero (RHP), and is given by:
2
V
IN
fRHPZ
=
2•π •RZ •CP2
2•π •IOUT •L • VOUT
The loop gain is typically rolled off before the RHP zero
frequency.
V
OUT
V
OUT
1.225V
FB
1.225V
+
–
+
ERROR
AMP
ERROR
AMP
R1
R1
C
Z1
FB
–
C
C
P1
P1
R2
R2
V
V
C
C
R
Z
3785 F05
C
P2
3785 F06
Figure 6. Error Amplifier with Type III Compensation
Figure 5. Error Amplifier with Type I Compensation
3785fc
ꢀꢃ
LTC3785
applicaTions inForMaTion
EFFICIENCY CONSIDERATIONS
switch C causes reverse recovery current loss in boost
mode.Whenmakingadjustmentstoimproveefficiency,
the input current is the best indicator of changes in
efficiency. If you make a change and the input current
decreases, then the efficiency has increased. If there
is no change in input current, then there is no change
in efficiency.
The percentage efficiency of a switching regulator is
equal to the output power divided by the input power
times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in circuits produce losses, four main sources
account for most of the losses in LTC3785 application
circuits:
5. V regulator loss. In applications where the input
CC
voltage is above 5V, such as two Li-Ion cells, the V
CC
regulator will dissipate some power due the differential
voltage and the average output current to the drive the
2
gates of the output switches. The V pin can be driven
1. DC I R losses. These arise from the resistances of the
CC
directly from a high efficiency external 5V source if
desired to incrementally improve overall efficiency at
lighter loads.
MOSFETs, sensing resistor (if used), inductor and PC
board traces and cause the efficiency to drop at high
output currents.
2. Transition loss. This loss arises from the brief voltage
transition time of switch A or switch C. It depends upon
theswitchvoltage,inductorcurrent,driverstrengthand
MOSFET capacitance, among other factors.
DESIGN EXAMPLE
As a design example, assume V = 2.7V to 10V (3.6V
nominal Li-Ion with 9V adapter), V
I = 3A and f = 500kHz.
OUT(MAX)
IN
= 3.3V (5%),
OUT
2
Transition Loss ~ V
• I • C • f
L RSS
SW
where C
is the reverse transfer capacitance.
RSS
Determine the Inductor Value
3. C and C
loss. The input capacitor has the difficult
IN
OUT
SettingtheInductorRippleto40%andusingtheequations
in the Inductor Selection section gives:
joboffilteringthelargeRMSinputcurrenttotheregula-
tor in buck mode. The output capacitor has the more
difficult job of filtering the large RMS output current
2
2.7 • 3.3–2.7 •100
(
)
(
)
L >
L >
= 0.67µH
in boost mode. Both C and C
are required to have
IN
OUT
2
500•103 •3•40• 3.3
2
(
)
low ESR to minimize the AC I R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
3.3• 10–3.3 •100
(
)
= 3.7µH
500•103 •3•40•10
4. Other losses. Optional Schottky diodes D1 and D2 are
responsible for conduction losses during dead time
and light load conduction periods. Core loss is the
predominant inductor loss at light loads. Turning on
Sotheworst-caserippleforthisapplicationisduringbuck
mode so a standard inductor value of 3.3µH is chosen.
3785fc
ꢀꢄ
LTC3785
applicaTions inForMaTion
Determine the Proper Inductor Type Selection
The maximum power dissipation of switch B and D occurs
in buck mode and is given by:
The highest inductor current is during boost mode and
is given by:
10–3.3
PB(BUCK)=
•32 •1.3•0.025= 0.20W
VOUT •IOUT
10
IL(MAX _ AV)
=
3.3
10
V • η
PD(BOOST)=
•32 •1.3•0.025= 0.10W
IN
where η = estimated efficiency in this mode (use 80%).
Now to double check the T of the package with 50°C
J
3.3•3
2.7•0.8
IL(MAX _ AV)
=
= 4.6A
ambient. Since this is a dual NMOS package we can add
switches A + B and C + D worst-case. For applications
wheretheMOSFETsareinseparatepackageseachdevice’s
To limit the maximum efficiency loss of the inductor ESR
to below 5% the equation is:
maximum T would have to be calculated.
J
VOUT •IOUT •%Loss
T
= T + θ (PA + PB)
A JA
J(PKG1)
ESRL(MAX)
~
= 24mΩ
IL(MAX _ AV)2 •100
= 50 + 60 • (0.43 + 0.20) = 88°C
= T + θ (PC + PD)
A suitable inductor for this application could be a Coiltron-
ics CD1-3R8 which has a rating DC current of 6A and ESR
of 13mΩ.
T
J(PKG2)
A
JA
= 50 + 60 • (0.09 + 0.10) = 60°C
Set The Maximum Current Limit
Choose a Proper MOSFET Switch
The equation for setting the maximum current limit of the
IC is given by:
Using the same guidelines for ESR of the inductor, one
suitable MOSFET could be the Siliconix Si7940DP which
is a dual MOSFET in a surface mount package with 25mΩ
at 2.5V and a total gate charge of 12nC.
6000
RILSET
=
Ω
RDS(ON)A •ILIMIT
Checking the power dissipation of each switch will ensure
reliable operation since the thermal resistance of the
package is 60°C/W.
Themaximumcurrentisset25%aboveI
for worst-case variation at 100°C = 6A.
toaccount
L(PEAK)
6000
0.025•6
The maximum power dissipation of switch A and C oc-
curs in boost mode. Assuming a junction temperature
RILSET
=
= 42k
of T = 100°C with ρ
IN
Considerations section:
= 1.3, the power dissipation at
J
100C
Choose the Input and Output Capacitance
V
= 2.7, and using the equations from the Efficiency
The input capacitance should filter current ripple which is
worst-case in buck mode. Since the input current could
reach 6A, a capacitor ESR of 10mΩ or less will yield an
input ripple of 60mV.
2
3.3
2.7
PA(BOOST)=
PC(BOOST)=
•3 • 1.3•0.025= 0.43W
3.3–2.7 •3.3
(
)
The output capacitance should filter current ripple which
is worst in boost mode, but is usually dictated by the loop
response, the maximum load transient and the allowable
transient response.
•32 •1.3•0.025
2.72
3
+ 1•3.33 •
•0.45–9•500•103
2.7
= 0.09W
3785fc
ꢀꢅ
LTC3785
applicaTions inForMaTion
PC BOARD LAYOUT CHECKLIST
• The path formed by switch A, switch B, D1 and the C
IN
capacitorshould haveshortleads and PC trace lengths.
The path formed by switch C, switch D, D2 and the
OUT
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
C
capacitor also should have short leads and PC
trace lengths.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
•
Theoutputcapacitor(–)terminalsshouldbeconnected
as close as possible to the (–) terminals of the input
capacitor.
• Place C , switch A, switch B and D1 in one compact
IN
• Connect the V decoupling capacitor C
closely to
CC
VCC
area. Place C , switch C, switch D and D2 in one
OUT
the V and PGND pins.
CC
compact area.
• Connect the top driver boost capacitor C closely to
A
• Useimmediateviastoconnectthecomponents(includ-
ing the LTC3785’s GND/PGND pin) to the ground plane.
Use several large vias for each power component.
the V
and SW1 pins. Connect the top driver boost
BST1
capacitor C closely to the V
and SW2 pins.
B
BST2
• Connect the input capacitors C and output capaci-
IN
• Use planes for V and V
to maintain good voltage
OUT
IN
tors C
close to the power MOSFETs. These capaci-
tors carry the MOSFET AC current in boost and buck
OUT
filtering and to keep power losses low.
• Floodallunusedareasonalllayerswithcopper.Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to any DC net
mode.
• Connect FB and V
pin resistive dividers to the (+)
SENSE
terminals of C
and signal ground. If a small V
OUT
SENSE
(V or GND). When laying out the printed circuit board,
IN
decoupling capacitor is used, it should be as close as
possible to the LTC3785 GND pin.
the following checklist should be used to ensure proper
operation of the LTC3785.
• Route I
and I
leads together with minimum PC
SSW1
SVIN
• Segregatethesignalandpowergrounds.Allsmall-signal
components should return to the GND pin at one point.
The sources of switch B and switch C should also con-
nect to one point at the GND of the IC.
tracespacing.EnsureaccuratecurrentsensingwithKel-
vin connections across MOSFET A or sense resistor.
• Route I
and I
leads together with minimum
SVOUT
SSW2
PC trace spacing. Ensure accurate current sensing
with Kelvin connections across MOSFET D or sense
resistor.
• Place switch B and switch C as close to the controller
as possible, keeping the PGND, BG and SW traces
short.
• Connect the feedback network close to IC, between the
• Keep the high dV/dT SW1, SW2, V
, V
, TG1 and
BST1 BST2
V and FB pins.
C
TG2 nodes away from sensitive small-signal nodes.
3785fc
ꢀꢆ
LTC3785
Typical applicaTion
V
9V REGULATED
WALL ADAPTER
IN
2.7V TO 10V
+
C
VCC
4.7µF
Li-Ion
2.7V TO 4.2V
1nF
V
IN
RUN/SS
V
CC
I
205k
121k
SVIN
TG1
C
IN
MA = MB = MC = MD = 1/2 Si7940DY
L1 = WÜRTH ELECTRONICS 744311470
D1 = D2 = PMEG2020EJ
V
MA
SENSE
22µF
CMDSH-3
V
C
A
0.22µF
BST1
270pF
1.3k
SW1
R1
OPTIONAL
D1
I
SSW1
205k
V
DRV
BG1
L1
4.7µH
FB
MB
MD
R2
121k
1nF
LTC3785
I
12k
V
C
V
3.3V
3A
OUT
RT
SVOUT
TG2
OPTIONAL
D2
R
T
59k
CMDSH-3
MODE
V
BST2
C
B
R
ILSET
0.22µF
SW2
42.2k
C
OUT
100µF
I
I
LSET
SSW2
CCM
BG2
MC
GND
3785 TA02
package DescripTion
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
BOTTOM VIEW—EXPOSED PAD
R = 0.ꢀꢀ5
PIN ꢀ NOTCH
R = 0.20 TYP OR
0.35 s 45° CHAMFER
0.75 0.05
4.00 0.ꢀ0
(4 SIDES)
TYP
23 24
0.70 0.05
PIN ꢀ
TOP MARK
(NOTE 6)
0.40 0.ꢀ0
ꢀ
2
4.50 0.05 2.45 0.05
(4 SIDES)
2.45 0.ꢀ0
(4-SIDES)
3.ꢀ0 0.05
PACKAGE
OUTLINE
(UF24) QFN 0ꢀ05
0.200 REF
0.25 0.05
0.25 0.05
0.50 BSC
0.00 – 0.05
0.50 BSC
NOTE:
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3785fc
ꢀꢇ
LTC3785
revision hisTory (Revision history begins at Rev C)
REV
DATE
DESCRIPTION
PAGE NUMBER
C
3/10
Added LTC3785IUF (I-Grade) Part. Reflected Throughout Data Sheet
1 Through 20
3785fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ꢀꢈ
LTC3785
Typical applicaTion
Li-Ion/9V Wall Adapter to 5V/2A
V
9V REGULATED
WALL ADAPTER
IN
2.7V TO 10V
+
C
VCC
4.7µF
Li-Ion
2.7V TO 4.2V
1nF
V
IN
RUN/SS
V
CC
I
205k
SVIN
TG1
66.5k
C
IN
MA = MB = MC = MD = 1/2 Si7940DY
L1 = RLF7030T-3R3M4R1
V
MA
SENSE
22µF
CMDSH-3
D1 = D2 = PMEG2020EJ
V
C
A
BST1
270pF
1.3k
0.22µF
SW1
OPTIONAL
D1
205k
I
SSW1
V
DRV
BG1
L1
3.3µH
FB
MB
MD
1nF
LTC3785
I
66.5k
12k
59k
V
C
V
5V
2A
OUT
RT
SVOUT
TG2
OPTIONAL
D2
CMDSH-3
MODE
V
BST2
C
B
0.22µF
SW2
C
42.2k
OUT
I
I
100µF
LSET
SSW2
CCM
BG2
MC
GND
3785 TA03
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
4V ≤ V ≤ 36V, 0.8V ≤ V
LTC3780
LTM4605
LTM4607
LTM4609
LTC3533
LTC3441
LTC3440
LTC3444
LTC3532
High Efficiency (Up to 98%), Synchronous
4-Switch Buck-Boost Controller
≤ 30V, SSOP-24, 5mm × 5mm QFN-32
OUT
IN
High Efficiency Buck-Boost DC/DC µModule
Complete Power Supply
4.5V ≤ V ≤ 20V, 0.8V ≤ V
≤ 16V, 15mm × 15mm × 2.8mm
≤ 25V, 15mm × 15mm × 2.8mm
≤ 34V, 15mm × 15mm × 2.8mm
IN
OUT
OUT
OUT
High Efficiency Buck-Boost DC/DC µModule
Complete Power Supply
4.5V ≤ V ≤ 36V, 0.8V ≤ V
IN
High Efficiency Buck-Boost DC/DC µModule
Complete Power Supply
4.5V ≤ V ≤ 36V, 0.8V ≤ V
IN
2A Synchronous Buck-Boost Monolithic DC/DC
Converter
1.8V ≤ V ≤ 5.5V, 1.8V ≤ V
≤ 5.25V, I = 40µA, I < 1µA, 3mm × 4mm DFN-14
Q SD
IN
OUT
OUT
OUT
OUT
OUT
1.2A Synchronous Buck-Boost Monolithic DC/DC
Converter
2.4V ≤ V ≤ 5.5V, 2.4V ≤ V
≤ 5.25V, I = 25µA, I < 1µA, 3mm × 4mm DFN-12
Q SD
IN
600mA Synchronous Buck-Boost Monolithic
DC/DC Converter
2.5V ≤ V ≤ 5.5V, 2.5V ≤ V
≤ 5.5V, I = 25µA, I < 1µA, 3mm × 3mm DFN-10,
Q SD
IN
MSOP-10
500mA Synchronous Buck-Boost Monolithic
DC/DC Converter
2.7V ≤ V ≤ 5.5V, ≤ 0.5V V
≤ 5.25V, Optimized for WCDMA RF Amplifier Bias,
≤ 5.25V, I = 35µA, I < 1µA, 3mm × 3mm DFN-10,
IN
3mm × 3mm DFN-8
500mA Synchronous Buck-Boost Monolithic
DC/DC Converter
2.4V ≤ V ≤ 5.5V, 2.4V ≤ V
IN
Q
SD
MSOP-10
LTC3531
LTC3531-3
LTC3531-3.3
200mA Synchronous Buck-Boost Monolithic
DC/DC Converter
1.8V ≤ V ≤ to 5.5V, 2V ≤ V
≤ 5V, I = 35µA, I < 1µA, 3mm × 3mm DFN-8,
Q SD
IN
OUT
ThinSOT-23
µModule is a registered trademark of Linear Technology Corporation.
3785fc
LT 0310 REV C • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
ꢁ0
●
●
ꢀLINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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