LTC3785EUF-1-TRPBF_技术文档

LTC3785-1

10V, High Efﬁciency,

Buck-Boost Controller

with Power Good

FEATURES

DESCRIPTION

The LTC^®3785-1 is a high power synchronous buck-boost

controller that drives all N-channel power MOSFETs from

input voltages above, below and equal to the output volt-

age. With an input range of 2.7V to 10V, the LTC3785-1 is

well suited for a wide variety of single or dual cell Li-Ion

or multi-cell alkaline/NiMH applications.

n

Single Inductor Architecture Allows V Above,

IN

Below or Equal to V

OUT

n

Power Good Output Indicator

n

2.7V to 10V Input and Output Range

n

Up to 96% Efﬁciency

n

Up to 10A of Output Current

TM

n

All N-Channel MOSFETs, No R

SENSE

Theoperatingfrequencycanbeprogrammedfrom100kHz

to 1MHz. The soft-start time and current limit are also

programmable. The soft-start capacitor doubles as the

faulttimerwhichcanprogramtheICtolatchofforrecycle

after a determined off time. Burst Mode operation is user

controlled and can be enabled by driving the MODE pin

high. The LTC3785-1 includes a Power Good output that

indicates when the output voltage is within 7.5% of its

designed setpoint.

n

True Output Disconnect During Shutdown

Programmable Current Limit and Soft-Start

Optional Short-Circuit Shutdown Timer

Output Overvoltage and Undervoltage Protection

Programmable Frequency: 100kHz to 1MHz

Selectable Burst Mode^®Operation

Available in 24-Lead (4mm × 4mm) Exposed Pad

QFN Package

APPLICATIONS

Protection features include foldback current limit,

short-circuit and overvoltage protection.

n

Palmtop Computers

n

Handheld Instruments

, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology

Corporation. No R

is a trademark of Linear Technology Corporation.

SENSE

n

Wireless Modems

All other trademarks are the property of their respective owners.

n

Cellular Telephones

TYPICAL APPLICATION

V

IN

2.7V

Efﬁciency vs Input Voltage

V

OUT

4.7μF

TO 10V

V

IN

V

CC

100

95

215k

127k

V

= 3.3V

= 500kHz

OUT

OSC

I

SVIN

F

22μF

TG1

V

SENSE

1.3k

215k

A

V

BST1

270pF

0.22μF

I

= 2A

LOAD

SW1

FB

I

SSW1

I

LOAD

= 1A

127k

1nF

12k

V

DRV

BG1

4.7μH

90

LTC3785-1

I

B

D

V

C

V

3.3V

5A

OUT

RT

SVOUT

TG2

49.9k

85

MODE

2.5

5.5

7

8.5

10

4

V

(V)

IN

PGOOD

RUN/SS

V

BST2

37851 TA01b

0.22μF

SW2

100μF

I

LSET

SSW2

CCM

BG2

42.2k

2.2nF

GND

C

37851 TA01a

37851f

1

LTC3785-1

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

Input Supply Voltage (V )......................... –0.3V to 11V

IN

I

, I

.............................................. –0.3V to 11V

SVOUT SVIN

SW1, SW2, I

24 23 22 21 20 19

, I

Voltage:

SSW1 SSW2

RUN/SS

1

2

3

4

5

6

18

17

16

I

SSW1

DC............................................................. –1V to 11V

Pulsed, <1μs............................................. –2V to 12V

V

C

BG1

V

FB

DRV

25

RUN/SS, MODE, CCM, V , V Voltages ...... –0.3V to 6V

DRV CC

V

15 BG2

14

13 SW2

SENSE

PGOOD Voltage............................................ –0.3V to 6V

I

LSET

SSW2

TG1, V

Voltages................................... –0.3V to 16V

CCM

BST1

With Respect to SW1............................... –0.3V to 6V

TG2, V Voltages................................... –0.3V to 16V

7

8

9 10 11 12

BST2

With Respect to SW2............................... –0.3V to 6V

BG1, BG2 Voltage ........................................ –0.3V to 6V

Peak Driver Output Current < 10μs

UF PACKAGE

24-LEAD (4mm s 4mm) PLASTIC QFN

T

= 125°C, θ = 37°C/W 4 LAYER BOARD

JA

JMAX

EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB

(TG1, TG2, BG1, BG2).................................................3A

V

Average Output Current.................................100mA

CC

Operating Temperature Range.................. –40°C to 85°C

Storage Temperature Range................... –65°C to 125°C

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING

PACKAGE DESCRIPTION

24-Lead (4mm × 4mm) Plastic QFN

TEMPERATURE RANGE

–40°C to 85°C

LTC3785EUF-1#PBF

LTC3785EUF-1#TRPBF

37851

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= V_OUT= V_DRV= V_BST1= V_BST2= 3.6V, R_T= 49.9k, R_ILSET= 59k.

PARAMETER

Supply

CONDITIONS

MIN

TYP

MAX

UNITS

V

IN

l

Input Operating Voltage

Quiescent Current—Burst Mode Operation

Quiescent Current—Shutdown

Quiescent Current—Active

Error Amp

2.7

10

200

25

V

μA

V = 0V, MODE = 3.6V (Note 4)

86

15

0.8

C

RUN/SS = 0V, V

= 0V

OUT

MODE = 0V (Note 4)

1.5

mA

l

Feedback Voltage

(Note 5)

1.200

1.225

1

–500

900

90

1.25

500

V

nA

μA

dB

Feedback Input Current

Error Amp Source Current

Error Amp Sink Current

Error Amp A

VOL

V

CC

V

CC

V

CC

Regulator

Maximum Regulating Voltage

Regulation Voltage

l

V

= 5V, I

= 3.6V, I

= –20mA

VCC

4.15

3.3

4.35

3.5

4.55

3.6

V

IN

= –20mA

IN

VCC

37851f

2

LTC3785-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= V_OUT= V_DRV= V_BST1= V_BST2= 3.6V, R_T= 49.9k, R_ILSET= 59k.

PARAMETER

Regulator Sink Current

CONDITIONS

= V = 5V

MIN

TYP

800

MAX

UNITS

V

μA

CC

OUT

CC

Run/Soft-Start

l

RUN/SS Threshold

When IC is Enabled

0.35

0.7

1.9

–1

1

1.1

5

V

μA

When EA is at Maximum Boost Duty Cycle

RUN/SS Input Current

RUN/SS Discharge Current

Current Limit

RUN/SS = 0V

During Current Limit

l

Current Limit Sense Threshold

I

to I

, R

SSW1 ILSET

= 121k

= 59k

20

55

60

105

100

155

mV

SVIN

, R

l

Reverse Current Limit Sense Threshold

Input Current

I

to I

, CCM > 2V

SVOUT

–50

–110

–15

80

10

0.1

–170

–35

150

20

5

mV

μA

SSW2

SVOUT

to I

, CCM < 0.4V

I

SVIN

SVOUT

SSW1 SSW2

, I

l

CCM Input Threshold (High)

CCM Input Threshold (Low)

CCM Input Current

Burst Mode Operation

Mode Threshold

2.2

0.8

V

μA

0.4

1

0.01

l

1.5

0.01

1.4

2.2

1

V

μA

μs

Mode Input Current

t

ON

Time

Oscillator

l

Frequency Accuracy

Switching Characteristics

Maximum Duty Cycle

370

80

509

650

kHz

Boost (% Switch BG2 On)

Buck (% Switch TG1 On)

90

99

%

TG1, TG2 Driver Impedance

BG1, BG2 Driver Impedance

TG1, TG2 Rise Time

BG1, BG2 Rise Time

TG1, TG2 Fall Time

2

Ω

C

= 3300pF (Note 3)

20

100

ns

LOAD

BG1, BG2 Fall Time

Buck Driver Nonoverlap Time

Boost Driver Nonoverlap Time

Power Good

TG1 to BG1

TG2 to BG2

Undervoltage Threshold

Undervoltage Hysteresis

Overvoltage Threshold

V

Falling, % Below FB Regulation Voltage

–5

5

–7.5

1.5

7.5

–10.5

10.5

%

SENSE

Rising % Above FB Regulation Voltage,

MODE = 0V

SENSE

Overvoltage Hysteresis

PGOOD Output Low

PGOOD Leakage

–2

200

%

mV

μA

I

V

= 500μA

500

5

500

PGOOD

= 5.5V

PGOOD

SENSE

V

SENSE

Input Current

= Measured FB Voltage

1

nA

temperature range are assured by design, characterization and correlation

with statistical process controls.

Note 3: Speciﬁcation is guaranteed by design and not 100% tested in production.

Note 4: Current measurements are performed when the outputs are not switching.

Note 5: The IC is tested in a feedback loop to make the measurement.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3785E-1 is guaranteed to meet performance speciﬁcations

from 0°C to 85°C. Speciﬁcations over –40°C to 85°C operating

37851f

3

LTC3785-1

TYPICAL PERFORMANCE CHARACTERISTICS

Li-Ion to 3.3V Efﬁciency vs

Load Current

Two Li-Ion to 7V Efﬁciency vs

Load Current

Li-Ion/9V to 5V V_OUTEfﬁciency vs

Load Current

100

90

100

90

100

90

80

70

60

50

40

30

20

10

0

Burst Mode

OPERATION

Burst Mode

OPERATION

Burst Mode

OPERATION

80

70

FIXED

FREQUENCY

FIXED

FREQUENCY

FIXED

FREQUENCY

60

50

60

50

V

IN

V

IN

V

IN

V

IN

= 9V

40

30

20

10

0

40

30

20

10

0

V

= 4.2V

= 3.6V

= 3V

= 4.2V

= 3.6V

= 2.7V

V

= 8.4V

= 7.2V

= 5.4V

IN

V

MOSFET Si7940

L = 4.7μH WURTH WE-PD

L = 5.6μH MSS1260

f

= 500kHz

f

= 430kHz

f

= 430kHz

OSC

0.0001 0.001

0.01

0.1

1

10

0.0001 0.001

0.01

0.1

1

10

0.0001 0.001

0.01

0.1

1

10

LOAD CURRENT (A)

37851 G03

37851 G02

37851 G01

Burst Mode Ripple

Line Transient Response

V_OUTLoad Transient

V

OUT

V

OUT

500mV/

DIV

200mV/

DIV

V

OUT

50mV/DIV

AC

COUPLED

V

IN

3V TO

8.5V

I

LOAD

INDUCTOR

CURRENT

1A/DIV

10mA TO 2A

37851 G05

I

V

C

= 300μA 500μs/DIV

LOAD

OUT

37851 G06

V

C

= 3.6V

100μs/DIV

= 5V

IN

37851 G04

V

C

= 3.3V

= 100μF

5μs/DIV

= 3.3V

OUT

= 100μF

OUT

= 100μF

Normalized Oscillator Frequency

vs Temperature

V_FBvs Temperature

Oscillator Frequency vs RT

1.2255

1.2250

1.2245

1.2240

1.2235

1.2230

1.2225

1.2220

1.2215

1.2210

1200

1000

1.0

0.8

0.6

0.4

800

600

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

400

200

0

50

TEMPERATURE (°C)

100

20

40

60

80

100

–50 –25

0

25

75

–50

–25

25

50

75

100

0

TEMPERATURE (°C)

RT (kΩ)

37851 G09

37851 G07

37851 G08

37851f

4

LTC3785-1

TYPICAL PERFORMANCE CHARACTERISTICS

V_INStart-Up Voltage vs

Temperature

V_INBurst Quiescent Current vs

Temperature

OV and UV Thresholds vs

Temperature

2.490

2.485

2.480

2.475

8

6

100

95

90

85

80

OV THRESHOLD

4

2

0

–2

–4

–6

–8

2.470

2.465

UV THRESHOLD

–50

0

25

50

75

100

–25

–50

–25

25

50

75

100

0

–50

–25

25

50

75

100

0

TEMPERATURE (°C)

37851 G10

37851 G11

37851 G12

PIN FUNCTIONS

RUN/SS (Pin 1): Run Control and Soft-Start Input. An

internal 1μA charges the soft-start capacitor and will

charge to approximately 2.5V. During a current limit fault,

the soft-start capacitor will incrementally discharge. Once

the pin drops below 1.225V the IC will enter fault mode,

turning off the outputs for 32 times the soft-start time. If

>5μA (at RUN/SS = 1.225V) is applied externally, the part

will latch off after a fault is detected. If >40μA (at RUN/SS

= 1.225V) is applied externally, current limit faults will not

discharge the SS capacitor.

V

(Pin 4): Overvoltage and Undervoltage Sense.

SENSE

The overvoltage threshold is internally set 7.5% above

the regulated FB voltage and the undervoltage threshold

is internally set 7.5% below the FB regulated voltage. This

pin can be tied to FB but to optimize the response time it

isrecommendedthataseparatevoltagedividerfromV

OUT

be applied. The divider can be skewed from the feedback

value to achieve the desired UV or OV threshold.

I

(Pin 5): Current Limit Set. A resistor from this pin

LSET

to ground sets the current limit threshold from the I

SVIN

V (Pin 2): Error Amp Output. A frequency compensation

C

and I

pins.

SSW1

network is connected from this pin to the FB pin to com-

pensate the loop. See the section “Closing the Feedback

Loop” for guidelines.

CCM (Pin 6): Continuous Conduction Mode Control Pin.

When set low, the inductor current is allowed to go slightly

negative (–15mV referenced to the I

– I

pins).

SVOUT

SSW2

FB (Pin 3): Feedback Pin. Connect resistor divider tap

here. The feedback reference voltage is typically 1.225V

The output voltage can be adjusted from 2.7V to 10V ac-

cording to the following formula:

Whendrivenhigh,thereversecurrentlimitissettothesimilar

value of the forward current limit set by the I pin.

LSET

RT (Pin 7): Oscillator Programming Pin. A resistor from

this pin to GND sets the free-running frequency of the IC.

f

≅ 2.5e10/RT.

R1+R2

V_OUT= 1.225V •

R2

OSC

37851f

5

LTC3785-1

PIN FUNCTIONS

MODE (Pin 8): Burst Mode Control Pin.

I

(Pin 18): Forward Current Limit Comparator Non-

SSW1

inverting Input. This pin is normally connected to the

source of the N-channel MOSFET A (TG1 driven).

• MODE = High: Enable Burst Mode Operation. In Burst

Mode operation the operation is variable frequency,

which provides a signiﬁcant efﬁciency improvement

at light loads. The Burst Mode operation will continue

until the pin is driven low.

SW1 (Pin 19): Ground Reference for Driver A. Gate drive

from TG1 will reference to the common point of output

switches A and B.

• MODE=Low:DisableBurstModeoperationandmaintain

low noise, constant frequency operation.

TG1, TG2 (Pins 20, 12): Top gate drive pins drive the

top N-channel MOSFET switches A and D with a voltage

swing equal to V – V

superimposed on the SW1

CC

DIODE

PGOOD (Pin 9): Open drain output. PGOOD is pulled to

and SW2 nodes respectively.

V (Pin 21): Boosted Floating Driver Supply for the

BST1

ground when the voltage on V

is not within 7.5%

SENSE

of its setpoint. PGOOD will also be pulled low when the

part is in shutdown or input UVLO.

Buck Switch A. This pin will swing from a diode below

V

CC

up to V + V – V

.

IN

CC

DIODE

I

(Pin 10): Reverse Current Limit Comparator Non-

SVOUT

invertingInput. Thispinisnormallyconnectedtothedrain

I

(Pin 22): Forward Current Limit Comparator Invert-

SVIN

of the N-channel MOSFET D (TG2 driven).

ing Input. This pin is normally connected to the drain of

N-channel MOSFET A (TG1 driven).

V

(Pin 11): Boosted Floating Driver Supply for Boost

BST2

Switch D. This pin will swing from a diode below V up

V

CC

(Pin 23): Internal 4.5V LDO Regulator Output. The

CC

to V

+ V – V .

driver and control circuits are powered from this voltage

to limit the maximum VGS drive voltage. Decouple this pin

to power ground with at least a 4.7μF ceramic capacitor.

OUT

CC

DIODE

SW2 (Pin 13): Ground Reference for Driver D. Gate drive

from TG2 will reference to the common point of output

switches C and D.

For low V applications, V can be bootstrapped from

IN

CC

V

through a Schottky diode.

OUT

I

(Pin 14): Reverse Current Limit Comparator Invert-

SSW2

V

(Pin 24): Input Supply Pin for the V Regulator. A

CC

IN

ing Input. This pin is normally connected to the source of

ceramic capacitor of at least 10μF is recommended close

the N-channel MOSFET D (TG2 driven).

to the V and GND pins.

IN

V

(Pin 16): Driver Supply for Ground Referenced

DRV

Exposed Pad (Pin 25): The GND and PGND pins are con-

nected to the Exposed Pad which must be connected to

the PCB ground for electrical contact and rated thermal

performance.

Switches. Connect this pin to V potential.

CC

BG1, BG2 (Pins 17, 15): Bottom gate driver pins drive

the ground referenced N-channel MOSFET switches B

and C.

37851f

6

LTC3785-1

BLOCK DIAGRAM

V

IN

2.7V TO 10V

24

V

IN

1.225V

+

–

+

FAULT

LOGIC

TSD

100% DUTY

CHARGE PUMP

1.225V

V

4.5V REG

IDEAL DIODE

REF

C

VCC

V

CC

V

BE

+

23

22

RUN UVLO

I

2.4V

–

SVIN

1/25k

I

+

–

LIMIT

g

m

1μA

C

SS

RUN/SS

1

V = 60k/R

ILSET

2μA

TG1

ADRV

MA

C

20

21

19

18

16

17

IN

V

I

+

–

BST1

LIM(OUT)

+

–

X10

SW1

I

LIM(OUT)

MAX

C

A

SW1

10μA MAX

V = 90k/R

ILSET

I

SSW1

SAMPLED

TG1

BBM

SW1

DELAY

D1

OPT

SW1

PULSE

V

DRV

–7.5%

7.5%

+

–

UV

BG1

UV

OV

V

OUT

BG1

BDRV

MB

–

+

OV

V

OUT

LOW

–

+

V

SENSE

1.8V

4

TG2

BG2

PGND

BBM

SW2

PULSE

15mV

OR

1X I

+

–

DELAY

L1

1.225V

+

–

R1

100% DUTY

CHARGE PUMP

FB

LIMIT

3

2

I

DISABLE

SVOUT

C

P1

V

10

R2

OUT

REVERSE

LIMIT

V

C

D2

OPT

V

REV

REVERSE

CURRENT LIMIT

(ZERO LIMIT FOR BURST)

R

T

TG2

RT

MD

12

11

OSC

DDRV

7

V

BST2

1 = Burst Mode OPERATION

0 = FIXED FREQUENCY

C

B

SW2

–

+

13

14

1.5V

BURST

LOGIC

SW2

MC

BURST

MODE

I

SSW2

8

5

SAMPLED

V

DRV

SS

BG2

CDRV

15

6

C

OUT

R

ILSET

I

LSET

I

COMP

I

LIM

LIMIT

SET

MAX

PGND

1/2 LIMIT AT V

OUT

< 1V

UV

OV

CCM

0 = 15mV

1 = I

V

REV

SD

LIMIT

UVLO

PGOOD

GND/PGND

25

9

37851 BD

37851f

7

LTC3785-1

OPERATION

MAIN CONTROL LOOP

V

IN

V

OUT

The LTC3785-1 is a buck-boost voltage mode controller

that provides an output voltage above, equal to or below

the input voltage.

TG1

BG1

D

C

A

TG2

BG2

L

SW1

SW2

B

The LTC proprietary topology and control architecture also

employs drain-to-source sensing (No R ) for forward

SENSE

37851 F01

and reverse current limiting. The controller provides all

N-channel MOSFET output switch drive, facilitating single

packagemultiplepowerswitchtechnologyalongwithlower

Figure 1. Response Time Test Circuit

R

. The error amp output voltage (V ) determines the

DS(ON)

C

90%

MAX

D

outputdutycycleoftheswitches.SincetheV pinisaﬁltered

C

BOOST

A ON, B OFF

signal, it provides rejection of high frequency noise.

BOOST REGION

PWM C, D SWITCHES

D

MIN

The FB pin receives the voltage feedback signal, which

is compared to the internal reference voltage by the er-

ror ampliﬁer. The top MOSFET drivers are biased from a

ﬂoating bootstrap capacitor, which is normally recharged

during each off cycle through an external diode when the

top MOSFET turns off. Optional Schottky diodes can be

connected across synchronous switch B and D to provide

a lower drop during the dead time and eliminate efﬁciency

loss due to body diode reverse recovery.

BOOST

FOUR SWITCH PWM

BUCK/BOOST REGION

D

MAX

BUCK

D ON, C OFF

PWM A, B SWITCHES

BUCK REGION

D

BUCK

MIN

37851 F02

Figure 1. Response Time Test Circuit

theremainderoftheswitchingperiod.SwitchesAandBwill

alternate similar to a typical synchronous buck regulator.

As the control voltage increases, the duty cycle of switch

A increases until the max duty cycle of the converter in

The main control loop is shut down by pulling the RUN/

SS pin low. An internal 1μA current source charges the

RUN/SS pin and when the pin voltage is higher than 0.7V

buck mode reaches D

, given by:

MAX_BUCK

the IC is enabled. The V voltage is then clamped to the

C

RUN/SS voltage minus 0.7V while C is slowly charged

D

= 100 – D4(SW)%

SS

MAX_BUCK

duringstart-up.This“soft-start”clampingpreventsinrush

where D4(SW) = duty cycle % of the four switch range.

D4(SW) = (300ns • f) • 100%

current draw from the input power supply.

POWER SWITCH CONTROL

where f = operating frequency, Hz.

Figure1showsasimpliﬁeddiagramofhowthefourpower

Beyond this point the “four switch” or buck-boost region

is reached.

switchesareconnectedtotheinductor,V ,V andGND.

IN OUT

Figure 2 shows the regions of operation for the LTC3785-1

as a function of duty cycle D. The power switches are

properly controlled so that the transfer between modes

is continuous.

Buck-Boost or Four Switch (V ~ V

)

OUT

IN

When the error amp output voltage, V , is above ap-

proximately 0.65V, switch pair AD remain on for duty

C

cycle D

, and the switch pair AC begin to phase

MAX_BUCK

Buck Region (V > V

)

OUT

IN

in. As switch pair AC phases in, switch pair BD phases

Switch D is always on and switch C is always off during

out accordingly. When the V voltage reaches the edge of

C

buck mode. When the error amp output voltage, V , is

the buck-boost range, approximately 0.7V, the AC switch

C

approximatelyabove0.1V,outputAbeginstoswitch.During

pair completely phase out the BD pair, and the boost phase

theofftimeofswitchA, synchronousswitchBturnsonfor

begins at duty cycle, D4(SW).

37851f

8

LTC3785-1

OPERATION

Theinputvoltage,V ,wherethefourswitchregionbegins

In Burst Mode operation the maximum output current is

given by:

IN

is given by:

V_OUT

1– 300ns • f

1.2 • V

IN

V_IN=

V

I_{OUT(MAX,BURST)}

≈

A

f •L • V_OUT+ V

(

)

(

)

IN

the point at which the four switch region ends is given

by:

Burst Mode operation is user-controlled by driving the

MODE pin high to enable and low to disable.

V = V (1 – D) = V (1 – 300ns • f) V

IN

OUT

V

REGULATOR

CC

Boost Region (V < V

)

IN

OUT

An internal P-channel low dropout regulator produces

4.35V at the V pin from the V supply pin. V powers

Switch A is always on and switch B is always off during

boostmode. Whentheerrorampoutputvoltage, V , isap-

proximatelyabove0.7V, switchpairCandDwillalternately

switchtoprovideaboostedoutputvoltage. Thisoperation

is typical to a synchronous boost regulator. The maximum

duty cycle of the converter is limited to 90% typical.

CC

IN

CC

the drivers and internal circuitry of the LTC3785-1. The

V pin regulator can supply a peak current of 100mA and

CC

C

must be bypassed to ground with a minimum of 4.7μF

placed directly adjacent to the V and GND pins. Good

CC

bypassing is necessary to supply the high transient cur-

rent required by the MOSFET gate drivers and to prevent

interactionbetweenchannels. Ifdesired, theV regulator

CC

Burst Mode OPERATION

can be connected to V

through a Schottky diode to

OUT

During Burst Mode operation, the LTC3785-1 delivers

energy to the output until it is regulated and then goes

into a sleep state where the outputs are off and the IC

is consuming only 86μA. In Burst Mode operation, the

output ripple has a variable frequency component, which

is dependent upon load current

providehighergatedriveinlowinputvoltageapplications.

The V regulator can also be driven with an external 5V

CC

source directly (without a Schottky diode).

TOPSIDE MOSFET DRIVER SUPPLY (V

, V

BST1 BST2

)

The external bootstrap capacitors connected to the V

and V

BST1

During the period where the converter is delivering en-

ergy to the output, the inductor will reach a peak current

pins supply the gate drive voltage for the top-

BST2

side MOSFET switches A and D. When the top MOSFET

switch A turns on, the switch node SW1 rises to V and

determined by an on time, t , and will terminate at zero

ON

IN

current for each cycle. The on time is given by:

the V

pin rises to approximately V + V . When the

BST2

IN CC

2.4

bottom MOSFET switch B turns on, the switch node SW1

t_ON

=

drops low and the boost capacitor is charged through the

V • f

IN

diode connected to V . When the top MOSFET switch D

CC

where f is the oscillator frequency.

turns on, the switch node SW2 rises to V

pin rises to approximately V

and the V

OUT

BST2

The peak current is given by:

+ V . When the bottom

OUT

CC

MOSFET switch C turns on, the switch node SW2 drops

V

L

^IN• t_ON

low and the boost capacitor is charged through the diode

I_PEAK

=

connectedtoV .Theboostcapacitorsneedtostoreabout

CC

100 times the gate charge required by the top MOSFET

switch A and D. In most applications a 0.1μF to 0.47μF,

X5R or X7R dielectric capacitor is adequate.

2.4

f •L

I_PEAK

=

So the peak current is independent of V and inversely

IN

proportional to the f • L product optimizing the energy

transfer for various applications.

37851f

9

LTC3785-1

OPERATION

RUN/SOFT-START (RUN/SS)

the range is a constant, tightening the UV threshold will

loosen the OV threshold and vice versa.

The RUN/SS pin serves as the enable to the LTC3785-1,

soft-start function, and fault programming. A 1μA current

source charges the external capacitor. Once the RUN/SS

voltageisaboveadiodedrop(~0.7V)theICisenabled.Once

the IC is enabled, the RUN/SS voltage minus a diode drop

POWER GOOD COMPARATOR

The PGOOD pin is an open-drain output which indicates

thestatusofthebuck-boostconverteroutput. Theoutput

(RUN/SS – 0.7V) clamps the output of the error amp (V )

C

voltage is monitored at V

via a resistor divider tap

SENSE

to limit duty cycle. The range of the duty cycle clamping is

approximately 0.7V to 1.7V. The RUN/SS pin is clamped

to approximately 2.2V. If current limit is reached the pin

will begin to discharge with a current determined by the

magnitude of inductor current overcurrent limit, but not

to exceed 10μA. This function will be described in more

detail in the “Forward Current Limit” section.

fromV

toGND.Thevaluesusedforthisresistordivider

OUT

are typically selected to be the same as those used in the

error ampliﬁer feedback divider. If the voltage on V

SENSE

either falls 7.5% below (UV condition) or rises 7.5%

above (OV condition) the regulation voltage, the PGOOD

open-drain output will pull low signaling the output is

out of regulation. Once an out of regulation condition is

triggered, the voltage on V

must rise 1.5% above

SENSE

OSCILLATOR

theUVthresholdorfall2%belowtheOVthresholdbefore

the pull-down will turn off. In addition, there is a 15μs

deglitch delay to help prevent false trips due to voltage

transients caused by line or load steps. Depending upon

the application, this delay may be insufﬁcient. A capaci-

The frequency of operation is set through a resistor from

the RT pin to ground where f ≅ (2.5e /RT)Hz.

10

ERROR AMP

tor can be placed from V

to GND to add additional

SENSE

deglitch ﬁltering, ensuring PGOOD doesn’t trip during

a transient. The PGOOD output will also pull low during

shutdownandinputundervoltagelockouttoindicatethese

fault conditions.

The error ampliﬁer is a voltage mode ampliﬁer with a

reference voltage of 1.225V internally connected to the

non-inverting input. The loop compensation components

are conﬁgured around the ampliﬁer to provide loop com-

pensationfortheconverter. TheRUN/SSpinwillclampthe

error amp output, V , to provide a soft-start function.

FORWARD CURRENT LIMIT

C

The LTC3785-1 is designed to sense the input current by

samplingthevoltageacrossMOSFETAduringtheontimeof

UNDERVOLTAGE AND OVERVOLTAGE PROTECTION

theswitch(TG1=High).ThesensepinsareI

andI

.

The LTC3785-1 incorporates overvoltage (OV) and

undervoltage (UV) functions for fault protection and

transient limitation. Both comparators are connected

SVIN

SSW1

A current sense resistor can be used if increased accuracy

isrequired.Thecurrentlimitthresholdcanbeprogrammed

with a resistor on the I

pin. Once the desired current

can be determined by the

to the V

pin, which usually has a similar voltage

LSET

SENSE

limit has been chosen, R

following formula:

6000

divider as the error ampliﬁer without the compensation.

The overvoltage threshold is 7.5% above the reference.

The undervoltage threshold is 7.5% below the reference

with both comparators having 1% hysteresis. During an

overvoltage fault, all output switching stops until the fault

ceases.Duringanundervoltagefault,theICiscommanded

to run ﬁxed frequency only (disabled Burst Mode opera-

tion). If the design requires a tightened threshold to one

of the comparator thresholds the voltage divider on the

ILSET

R_ILSET

=

Ω

R_DS(ON)A•I_LIMIT

where R

= R

of N-channel MOSFET switch A

DS(ON)A

DS(ON)

and I

= current limit in Amps.

LIMIT

Once the voltage between I

and I

exceeds the

SVIN

SSW1

threshold, current will be sourced out of FB to take control

V

pin can be skewed to achieve the threshold. Since

SENSE

37851f

10

LTC3785-1

OPERATION

of the voltage loop, resulting in a lower output voltage

to regulate the input current. This fault condition causes

the RUN/SS capacitor to begin discharging. The level of

the discharge current depends on how much the current

exceeds the programmed threshold. Figure 3 is a simpli-

ﬁed diagram of the current sense and fault circuitry. If the

current limit fault duration is long enough to discharge the

RUN/SS capacitor below 1.225V, the fault latch is set and

will cycle the RUN/SS capacitor 16 times (1μA charging

and1μAdischargingoftheRUN/SScapacitor)tocreatean

off time of 32 times the soft-start time before the outputs

are allowed to switch to restart the output voltage. If the

current limit fault level exceeds 150% of the programmed

placingadiode(anodetiedtoV )andaresistorfromV

OUT OUT

totheRUN/SSpin.ThecurrentsourcedintoRUN/SSwillbe

–0.7dividedbytheresistorvalue. Toignoreallfaults

V

OUT

sourcegreaterthan40μAintotheRUN/SSpin(At1.225Von

theRUN/SSpin).Sincethemaximumfaultcurrentislimited,

this will prevent any discharging of the RUN/SS capacitor,

the soft-start capacitor will need to be sized accordingly to

accommodatetheextrachargingcurrentatstart-up.

Duringanoutputshort-circuitorifV islessthan1.8V,the

OUT

current limit folds back to 50% of the programmed level.

REVERSE CURRENT LIMIT

I

level at any time, the I

comparator is tripped and

The LTC3785-1 can be programmed to provide full class

D operation or allowed to source and sink current equal to

the current limit set value. This is achieved by asserting a

high level on the CCM pin. To minimize the reverse output

current, the CCM pin should be driven low or strapped to

ground. During this mode only, –15mV typical is allowed

LIMIT

MAX

output switches B and D are turned on to discharge the

inductor current for the remainder of the cycle.

To have the power converter latch-off on a fault, a pull-up

currentbetween4μAand7μAontheRUN/SSpinwillallow

the RUN/SS capacitor to discharge during an extended

fault,butwillpreventcyclingofthefaultwhichwillcausethe

converter to stay off. One method to implement this is by

across output switch D and is sensed with the I

SSW2

and

SVOUT

I

pins.

THERMAL SD

S FAULT

I

COMP

V

IN

LIMIT

1.225V

0.7V

+

–

+

I

SVIN

g

= 1/20k

m

S LOGIC

+

–

22

20

g

m

A

TG1

V = 60k/R

ILSET

(15k/R

WHEN V < 1.8V)

OUT

RUN

SW1

19

18

I

COMP

MAX

1μA

+

–

RUN/SS

TURN

I

+

–

X10

1

4

SSW1

SWITCHES

SAMPLED

C

SS

2.2V

B AND D ON

V = 90k/R

ILSET

1/3 • I

LIM(OUT)

10μA MAX

BG1 17

B

D

2μA

L1

CCM

6

CCM = HIGH = 6k/R

ILSET

I

LIM(OUT)

30μA MAX

CCM = LOW = 15mV

V

OUT

I

SVOUT

–

+

–

V

10

12

OUT

SWITCH D

OFF

ERROR AMP

1.225V

+

–

R1

C

OUT

REVERSE

CURRENT LIMIT

TG2

FB

3

2

C

P1

V

C

SW2

13

14

15

R2

I

SSW2

SAMPLED

I

LSET

I

COMP

I

LIM

LIMIT

SET

5

MAX

BG2

C

R

ILSET

37851 F03

Figure 3. Block Diagram of Current Limit Fault Circuitry

37851f

11

LTC3785-1

APPLICATIONS INFORMATION

INDUCTOR SELECTION

This formula has a maximum at V = 2V , where I

OUT(MAX)

=

IN

OUT

RMS

I

/2.Thissimpleworst-caseconditioniscommonly

The high frequency operation of the LTC3785-1 allows

the use of small surface mount inductors. The inductor

current ripple is typically set 20% to 40% of the maximum

inductor current. For a given ripple the inductance terms

are given as follows:

usedfordesignbecauseevensigniﬁcantdeviationsdonot

offer much relief. Note that ripple current ratings from ca-

pacitormanufacturersareoftenbasedononly2000hours

of life which makes it advisable to derate the capacitor.

In boost mode, the discontinuous current shifts from the

²• V_OUT– V

•100

input to the output, so C

must be capable of reducing

V

OUT

(

)

IN(MIN)

L >

, (Boost Mode)

the output voltage ripple. The effects of ESR (equivalent

series resistance) and the bulk capacitance must be

considered when choosing the right capacitor for a given

output ripple voltage. The steady ripple due to charging

and discharging the bulk capacitance is given by:

2

f •I_OUT(MAX)• %Ripple • V_OUT

V_OUT• V_IN(MAX)– V_OUT•100

(

)

L >

, (Buck Mode)

f •I_OUT(MAX)• %Ripple • V

IN(MAX)

where:

f = Operating frequency, Hz

%Ripple = Allowable inductor current ripple, %

= Minimum input voltage (limit to V /2

I_OUT(MAX)• V_OUT– V

(

)

IN(MIN)

V_{RIPPLE_BOOST}

=

C_OUT• V_OUT• f

V_OUT• V_IN(MAX)– V_OUT

(

)

V

IN(MIN)

OUT

V_{RIPPLE_BUCK}

=

8 •L •C_OUT• V_IN(MAX)• f²

minimum for worst case), V

V

= Maximum input voltage, V

IN(MAX)

where C = output ﬁlter capacitor, F

OUT

= Output voltage, V

OUT

The steady ripple due to the voltage drop across the ESR

is given by:

I

= Maximum output load current, A

OUT(MAX)

Forhighefﬁciencychooseaninductorwithahighfrequency

core material, such as ferrite, to reduce core loses. The

inductorshouldhavelowESR(equivalentseriesresistance)

ΔV

= I

• ESR

BOOST,ESR

L(MAX,BOOST)

V

_IN(MAX)– V_OUT• V

(

)

ΔV_BUCK,ESR

=

^OUT•ESR

2

to reduce the I R losses, and must be able to handle the

L • f • V_IN

peak inductor current without saturating. Molded chokes

or chip inductors usually do not have enough core to sup-

port the peak inductor currents in the 3A to 6A region. To

minimize radiated noise, use a toroid, pot core or shielded

bobbin inductor.

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic and

ceramic capacitors are all available in surface mount

packages. Ceramic capacitors have excellent low ESR

characteristics but can have a high voltage coefﬁcient.

Capacitors are now available with low ESR and high ripple

current ratings such as OS-CON and POSCAP.

C AND C

IN

SELECTION

OUT

In boost mode, input current is continuous. In buck mode,

inputcurrentisdiscontinuous.Inbuckmode,theselection

of input capacitor, C , is driven by the need to ﬁlter the

IN

input square wave current. Use a low ESR capacitor, sized

to handle the maximum RMS current. For buck operation,

the maximum RMS capacitor current is given by:

POWER N-CHANNEL MOSFET SELECTION AND

EFFICIENCY CONSIDERATIONS

The LTC3785-1 requires four external N-channel power

MOSFETs, two for the top switches (switches A and D,

shown in Figure 1) and two for the bottom switches

⎛

⎞

⎟

V_OUT

I_RMS~I_OUT(MAX)

•

• 1–

⎜

⎝

V

⎠

IN

37851f

12

LTC3785-1

APPLICATIONS INFORMATION

(switches B and C shown in Figure 1). Important param-

eters for the power MOSFETs are the breakdown voltage

Switch C operates in boost mode as the control switch. Its

power dissipation at maximum current is given by:

V

,thresholdvoltageV

,on-resistanceR

RSS

,

BR(DSS)

GS(TH)

DS(ON)

V

_OUT– V • V

(

)

IN

OUT

PC(BOOST) =

•I_OUT(MAX)²• ρT

reverse transfer capacitance C

and maximum current

2

V

I

. The drive voltage is set by the 4.35V V supply.

IN

DS(MAX)

CC

Consequently,logic-levelthresholdMOSFETsmustbeused

in LTC3785-1 applications. If the input voltage is expected

todropbelow5V,thensub-logicthresholdMOSFETsshould

be considered. In order to select the power MOSFETs, the

power dissipated by the device must be known.

I

• R_DS(ON)+ k • V_OUT

•

^OUT(MAX)• C_RSS• f

3

V

IN

whereC isusuallyspeciﬁedbytheMOSFETmanufactur-

RSS

ers. The constant k, which accounts for the loss caused by

reverse recovery current, is inversely proportional to the

gate drive current and has an empirical value of 1.0.

For switch A, the maximum power dissipation happens

in boost mode, when it remains on all the time. Its maxi-

mum power dissipation at maximum output current is

given by:

For switch D, the maximum power dissipation happens in

boost mode when its duty cycle is higher than 50%. Its

maximum power dissipation at maximum output current

is given by:

2

⎛

⎞

⎟

⎠

V_OUT

PA(BOOST) =

•I_OUT(MAX)• ρT •R_DS(ON)

⎜

V

⎝

IN

V_OUT

V

IN

PD BOOST =

•I_OUT(MAX)²• ρT •R_DS(ON)

(

)

where ρT is a normalization factor (unity at 25°C) ac-

counting for the signiﬁcant variation in on-resistance with

temperature,typicallyabout0.4%/°CasshowninFigure 4.

For a maximum junction temperature of 125°C, using a

value ρT = 1.5 is reasonable.

Typically, switch A has the highest power dissipation and

switch B has the lowest power dissipation unless a short

occurs at the output. From a known power dissipated

in the power MOSFET, its junction temperature can be

obtained using the following formula:

Switch B operates in buck mode as the synchronous

rectiﬁer. Its power dissipation at maximum output current

is given by:

T = T + P • R

J

A

TH(JA)

The R

to be used in the equation normally includes

TH(JA)

V – V_OUT

IN

PB(BUCK) =

•I_OUT(MAX)²• ρT •R_DS(ON)

the R

for the device plus the thermal resistance from

TH(JC)

V

IN

the case to the ambient temperature (R

). This value

TH(CA)

of T can then be compared to the original, assumed value

J

2.0

1.5

1.0

0.5

0

used in the iterative calculation process.

SCHOTTKY DIODE (D1, D2) SELECTION

Optional Schottky diodes D1 and D2 shown in the Block

Diagramconductduringthedeadtimebetweentheconduc-

tion of the power MOSFET switches. They are intended to

prevent the body diode of synchronous switches B and D

from turning on and storing charge during the dead time.

In particular, D2 signiﬁcantly reduces reverse recovery

current between switch D turn off and switch C turn on,

which improves converter efﬁciency and reduces switch

C voltage stress. In order for D2 to be effective, it must

50

100

–50

150

0

JUNCTION TEMPERATURE (°C)

37851 F04

Figure 4. Normalized R_DS(ON)vs Temperature

be located in very close proximity to SWD.

37851f

13

LTC3785-1

APPLICATIONS INFORMATION

CLOSING THE FEEDBACK LOOP

The unity gain frequency of the error ampliﬁer with the

type 1 compensation is given by:

The LTC3785-1 incorporates voltage mode control. The

control to output gain is given by:

1

f_UG=

2 • π •R1•C_P1

G_Buck= 1.6 • V , Buck Mode

IN

2

Mostapplicationsdemandanimprovedtransientresponse

toallowasmalleroutputﬁltercapacitor.Toachieveahigher

bandwidth, type III compensation is required as shown

in Figure 6. Two zeros are required to compensate for the

double pole response.

1.6 • V_OUT

G_BOOST

=

, Boost Mode

V

IN

The output ﬁlter exhibits a double-pole response and is

given by:

1

f_POLE1

f_ZERO1

f_ZERO2

f_POLE2

≈

=

≈

(a very low frequency)

f_{FILTER_POLE}

=

2 • π • 32e3 •C_P1•R1

2 • π • L •C_OUT

1

where C

is the output ﬁlter capacitor.

OUT

2 • π •R_Z•C_P1

The output ﬁlter zero is given by:

1

f_{FILTER_ZERO}

=

2 • π •R1•C_Z1

2 • π •R_ESR•C_OUT

1

whereR isthecapacitorequivalentseriesresistance.

ESR

2 • π •R_Z•C_P2

Atroublesomefeatureinboostmodeistherighthalfplane

zero (RHP), and is given by:

V

OUT

1.225V

+

2

R1

C

Z1

V

ERROR

AMP

IN

f_RHPZ

=

FB

2 • π •I_OUT•L • V_OUT

–

C

P1

R2

V

C

R

Z

The loop gain is typically rolled off before the RHP zero

frequency.

C

P2

37851 F06

A simple type I compensation network (Figure 5) can be

incorporated to stabilize the loop but at a cost of reduced

bandwidthandslowertransientresponse.Toensureproper

phase margin, the loop must cross over almost a decade

before the L-C double pole.

Figure 6. Error Ampliﬁer with Type III Compensation

EFFICIENCY CONSIDERATIONS

The percentage efﬁciency of a switching regulator is

equal to the output power divided by the input power

times 100%.

V

OUT

1.225V

FB

+

–

ERROR

AMP

R1

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Although all dissipative

elements in circuits produce losses, four main sources

account for most of the losses in LTC3785-1 application

circuits:

C

P1

R2

V

C

37851 F05

Figure 5. Error Ampliﬁer with Type I Compensation

37851f

14

LTC3785-1

APPLICATIONS INFORMATION

1. DC I R losses. These arise from the resistances of the

2

Determine the Inductor Value

MOSFETs, sensing resistor (if used), inductor and PC

board traces and cause the efﬁciency to drop at high

output currents.

SettingtheInductorRippleto40%andusingtheequations

in the Inductor Selection section gives:

2

2.7 • 3.3 – 2.7 • 100

(

)

(

)

2. Transition loss. This loss arises from the brief voltage

transition time of switch A or switch C. It depends upon

theswitchvoltage,inductorcurrent,driverstrengthand

MOSFET capacitance, among other factors.

L >

= 0.67μH

2

500 • 10³• 3 • 40 • 3.3

(

)

3.3 • 10 – 3.3 • 100

500 • 10³• 3 • 40 • 10

(

)

L >

= 3.7μH

2

Transition Loss ~ V

• I • C

L

• f

RSS

SW

where C

is the reverse transfer capacitance.

Sotheworst-caserippleforthisapplicationisduringbuck

mode so a standard inductor value of 3.3μH is chosen.

RSS

3. C and C

loss. The input capacitor has the difﬁcult

IN

OUT

jobofﬁlteringthelargeRMSinputcurrenttotheregula-

tor in buck mode. The output capacitor has the more

difﬁcult job of ﬁltering the large RMS output current in

Determine the Proper Inductor Type Selection

The highest inductor current is during boost mode and

is given by:

boost mode. Both C and C

are required to have

IN

OUT

2

low ESR to minimize the AC I R loss and sufﬁcient

capacitance to prevent the RMS current from causing

additional upstream losses in fuses or batteries.

V_OUT•I_OUT

I_{L(MAX_ AV)}

=

V • η

IN

where η = estimated efﬁciency in this mode (use 80%).

4. Other losses. Optional Schottky diodes D1 and D2 are

responsible for conduction losses during dead time

and light load conduction periods. Core loss is the

predominant inductor loss at light loads. Turning on

switch C causes reverse recovery current loss in boost

mode.Whenmakingadjustmentstoimproveefﬁciency,

the input current is the best indicator of changes in

efﬁciency. If you make a change and the input current

decreases, then the efﬁciency has increased. If there

is no change in input current, then there is no change

in efﬁciency.

3.3 • 3

2.7 • 0.8

I_{L(MAX_ AV)}

=

= 4.6A

To limit the maximum efﬁciency loss of the inductor ESR

to below 5% the equation is:

V_OUT•I_OUT• %Loss

I_{L(MAX_ AV)}²•100

ESR_L(MAX)

~

= 24mΩ

A suitable inductor for this application could be a Coiltron-

ics CD1-3R8 which has a rating DC current of 6A and ESR

of 13mΩ.

5. V regulator loss. In applications where the input

CC

voltage is above 5V, such as two Li-Ion cells, the V

CC

regulator will dissipate some power due the differential

voltage and the average output current to the drive the

Choose a Proper MOSFET Switch

gates of the output switches. The V pin can be driven

Using the same guidelines for ESR of the inductor, one

suitable MOSFET could be the Siliconix Si7940DP which

is a dual MOSFET in a surface mount package with 25mΩ

at 2.5V and a total gate charge of 12nC.

CC

directly from a high efﬁciency external 5V source if

desired to incrementally improve overall efﬁciency at

lighter loads.

Checking the power dissipation of each switch will ensure

reliable operation since the thermal resistance of the

package is 60°C/W.

DESIGN EXAMPLE

As a design example, assume V = 2.7V to 10V (3.6V

IN

nominal Li-Ion with 9V adapter), V

= 3.3V (5%),

OUT

I

= 3A and f = 500kHz.

OUT(MAX)

37851f

15

LTC3785-1

APPLICATIONS INFORMATION

The maximum power dissipation of switch A and C oc-

curs in boost mode. Assuming a junction temperature

Themaximumcurrentisset25%aboveI

toaccount

L(PEAK)

for worst-case variation at 100°C = 6A.

of T = 100°C with ρ

IN

Considerations section:

= 1.3, the power dissipation at

J

100C

6000

V

= 2.7, and using the equations from the Efﬁciency

R_ILSET

=

= 42k

0.025 • 6

Choose the Input and Output Capacitance

2

⎛

⎞

3.3

2.7

PA(BOOST) =

PC(BOOST) =

• 3 • 1.3 • 0.025 = 0.43W

The input capacitance should ﬁlter current ripple which is

worst case in buck mode. Since the input current could

reach 6A, a capacitor ESR of 10mΩ or less will yield an

input ripple of 60mV.

⎜

⎝

⎟

⎠

3.3 – 2.7 • 3.3

(

)

• 3²• 1.3 • 0.025

2.7²

3

The output capacitance should ﬁlter current ripple which

is worst in boost mode, but is usually dictated by the loop

response, the maximum load transient and the allowable

transient response.

+ 1• 3.3³•

• 0.45 – 9 • 500 • 10³

2.7

= 0.09W

The maximum power dissipation of switch B and D occurs

in buck mode and is given by:

PC BOARD LAYOUT CHECKLIST

10 – 3.3

The basic PC board layout requires a dedicated ground

plane layer. Also, for high current, a multilayer board

provides heat sinking for power components.

PB(BUCK) =

• 3²•1.3 • 0.025 = 0.20W

10

3.3

10

PD(BOOST) =

• 3²•1.3 • 0.025 = 0.10W

• The ground plane layer should not have any traces and

it should be as close as possible to the layer with power

MOSFETs.

Now to double check the T of the package with 50°C

J

ambient. Since this is a dual NMOS package we can add

switches A + B and C + D worst case. For applications

wheretheMOSFETsareinseparatepackageseachdevice’s

• Place C , switch A, switch B and D1 in one compact

IN

area. Place C , switch C, switch D and D2 in one

OUT

compact area.

maximum T would have to be calculated.

J

• Useimmediateviastoconnectthecomponents(includ-

ingtheLTC3785-1’sGND/PGNDpin)tothegroundplane.

Use several large vias for each power component.

T

= T + θ (PA + PB)

A JA

J(PKG1)

= 50 + 60 • (0.43 + 0.20) = 88°C

= T + θ (PC + PD)

T

J(PKG2)

A

JA

• Use planes for V and V

to maintain good voltage

OUT

IN

ﬁltering and to keep power losses low.

= 50 + 60 • (0.09 + 0.10) = 60°C

• Floodallunusedareasonalllayerswithcopper.Flooding

with copper will reduce the temperature rise of power

components. Connect the copper areas to any DC net

Set The Maximum Current Limit

The equation for setting the maximum current limit of the

IC is given by:

(V or GND). When laying out the printed circuit board,

IN

the following checklist should be used to ensure proper

operation of the LTC3785-1.

6000

R_DS(ON)A•I_LIMIT

R_ILSET

=

Ω

37851f

16

LTC3785-1

APPLICATIONS INFORMATION

• Segregatethesignalandpowergrounds.Allsmall-signal

components should return to the GND pin at one point.

The sources of switch B and switch C should also con-

nect to one point at the GND of the IC.

• Connect the top driver boost capacitor C closely to

A

the V

and SW1 pins. Connect the top driver boost

BST1

capacitor C closely to the V

and SW2 pins.

B

BST2

• Connect the input capacitors C and output capaci-

IN

• Place switch B and switch C as close to the controller

as possible, keeping the PGND, BG and SW traces

short.

tors C

close to the power MOSFETs. These capaci-

OUT

tors carry the MOSFET AC current in boost and buck

mode.

• Keep the high dV/dT SW1, SW2, V

, V

, TG1 and

• Connect FB and V

pin resistive dividers to the (+)

SENSE

BST1 BST2

TG2 nodes away from sensitive small-signal nodes.

terminals of C

and signal ground. If a small V

OUT SENSE

decoupling capacitor is used, it should be as close as

possible to the LTC3785-1 GND pin.

• The path formed by switch A, switch B, D1 and the C

IN

capacitor should have shortleads andPCtracelengths.

The path formed by switch C, switch D, D2 and the

• Route I

and I

leads together with minimum PC

SVIN

SSW1

C

capacitor also should have short leads and PC

tracespacing.EnsureaccuratecurrentsensingwithKel-

vin connections across MOSFET A or sense resistor.

OUT

trace lengths.

•

Theoutputcapacitor(–)terminalsshouldbeconnected

as close as possible to the (–) terminals of the input

capacitor.

• Route I

and I

leads together with minimum

SSW2

SVOUT

PC trace spacing. Ensure accurate current sensing

with Kelvin connections across MOSFET D or sense

resistor.

• Connect the V decoupling capacitor C

closely to

CC

VCC

the V and PGND pins.

• Connect the feedback network close to IC, between the

CC

V and FB pins.

C

37851f

17

LTC3785-1

TYPICAL APPLICATION

V

9V REGULATED

WALL ADAPTER

IN

2.7V TO 10V

+

C

VCC

Li-Ion

2.7V TO 4.2V

4.7μF

1nF

V

IN

RUN/SS

V

CC

I

205k

SVIN

124k

C

IN

MA = MB = MC = MD = 1/2 Si7940DY

L1 = WÜRTH ELECTRONICS 744311470

D1 = D2 = PMEG2020EJ

V

TG1

MA

SENSE

22μF

CMDSH-3

V

C

A

BST1

270pF

1.3k

0.22μF

SW1

R1

205k

OPTIONAL

D1

I

SSW1

V

DRV

BG1

FB

MB

MD

L1

4.7μH

R2

124k

1nF

LTC3785-1

12k

V

C

V

3.3V

3A

OUT

RT

I

SVOUT

TG2

R

T

OPTIONAL

D2

59k

100k

V

PGOOD

MODE

OUT

CMDSH-3

V

BST2

C

B

R

ILSET

0.22μF

SW2

42.2k

I

C

LSET

SSW2

OUT

100μF

CCM

BG2

MC

GND

37851 TA02

37851f

18

LTC3785-1

PACKAGE DESCRIPTION

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1697)

0.70 p 0.05

4.50 p 0.05

3.10 p 0.05

2.45 p 0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 p 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH

R = 0.20 TYP OR

0.35 s 45° CHAMFER

R = 0.115

TYP

0.75 p 0.05

4.00 p 0.10

(4 SIDES)

23 24

PIN 1

TOP MARK

(NOTE 6)

0.40 p 0.10

1

2

2.45 p 0.10

(4-SIDES)

(UF24) QFN 0105

0.25 p 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

37851f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LTC3785-1

TYPICAL APPLICATION

Li-Ion/9V Wall Adapter to 5V/2A

V

9V REGULATED

WALL ADAPTER

IN

2.7V TO 10V

+

C

VCC

Li-Ion

2.7V TO 4.2V

4.7μF

1nF

V

IN

RUN/SS

V

CC

I

205k

SVIN

66.5k

C

IN

MA = MB = MC = MD = 1/2 Si7940DY

L1 = RLF7030T-3R3M4R1

V

TG1

MA

SENSE

22μF

CMDSH-3

D1 = D2 = PMEG2020EJ

V

C

A

BST1

270pF

1.3k

0.22μF

SW1

OPTIONAL

D1

205k

I

SSW1

V

DRV

BG1

FB

MB

MD

L1

3.3μH

1nF

LTC3785-1

I

66.5k

12k

59k

V

C

V

5V

2A

OUT

RT

SVOUT

TG2

OPTIONAL

D2

100k

V

OUT

PGOOD

MODE

CMDSH-3

V

BST2

C

B

0.22μF

SW2

42.2k

I

LSET

SSW2

C

OUT

100μF

CCM

BG2

MC

GND

37851 TA03

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COMMENTS

NUMBER

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37851f

LT 0908 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3785EUF-1-TRPBF
厂家：	Linear
描述：	10V, High Effi ciency, Buck-Boost Controller with Power Good 10V ，高效率艾菲，降压 - 升压型控制器，具有电源良好控制器
文件：	总20页 (文件大小：240K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3785EUF-1-TRPBF [Linear]

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