LTC3788IGN-1#TRPBF_技术文档

LTC3788-1

2-Phase, Dual Output

Synchronous Boost Controller

FEATURES

DESCRIPTION

The LTC^®3788-1 is a high performance 2-phase dual

synchronous boost converter controller that drives all

N-channel power MOSFETs. Synchronous rectification

increases efficiency, reduces power losses and eases

thermal requirements, allowing the LTC3788-1 to be used

in high power boost applications.

n

Synchronous Operation for Highest Efficiency and

Reduced Heat Dissipation

n

Wide Input Range: 4.5V to 38V (40V Abs Max) and

Operates Down to 2.5V After Start-Up

n

Output Voltages Up to 60V

±±1 ±.2V Reference Voltage

n

R

or Inductor DCR Current Sensing

SENSE

A constant-frequency current mode architecture allows

a phase-lockable frequency of up to 850kHz. OPTI-LOOP

compensationallowsthetransientresponsetobeoptimized

over a wide range of output capacitance and ESR values.

The LTC3788-1 features a precision 1.2V reference and a

power good output indicator. A 4.5V to 38V input supply

range encompasses a wide range of system architectures

and battery chemistries.

n

±001 Duty Cycle Capability for Synchronous MOSFET

Low Quiescent Current: 125μA

Phase-Lockable Frequency (75kHz to 850kHz)

Programmable Fixed Frequency (50kHz to 900kHz)

Adjustable Output Voltage Soft-Start

Power Good Output Voltage Monitor

Low Shutdown Current I : <8ꢀA

Internal LDO Powers Gate Drive from VBIAS or EXTV

Available in a Narrow SSOP Package

Q

CC

Independent SS pins for each controller ramp the output

voltages during start-up. The PLLIN/MODE pin selects

among Burst Mode operation, pulse-skipping mode or

continuous inductor current mode at light loads.

APPLICATIONS

n

Industrial

Foraleadless32-pinQFNpackagewithadditionalfeatures

of adjustable current limit, clock out, phase modulation

and two PGOOD outputs, see the LTC3788 data sheet.

L, LT, LTC, LTM, Linear Technology, OPTI-LOOP, Burst Mode and the Linear logo are registered

n

Automotive

n

Medical

Military

n

trademarks and No R

and ThinSOT are trademarks of Linear Technology Corporation.

SENSE

All other trademarks are the property of their respective owners. Protected by U. S. Patents,

including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258.

TYPICAL APPLICATION

V

4.5V TO 12V START-UP VOLTAGE

IN

OPERATES THROUGH TRANSIENTS DOWN TO 2.5V

V

IN

Efficiency and Power Loss

vs Load Current

4.7μF

TG2

4.7μF

220μF

3mΩ

4mΩ

100

90

10000

1000

100

10

TG1 VBIAS INTV

BOOST1

CC

3.3μH

1.25μH

BOOST2

SW2

V

80

OUT

12V AT 5A

OUT

0.1μF

24V AT 3A

SW1

70

LTC3788-1

60

50

BG1

BG2

+

SENSE1

SENSE2

40

30

20

10

0

–

SENSE1

SENSE2

PGND

VFB2

V

= 12V

IN

OUT

1

= 24V

110k

232k

Burst Mode OPERATION

FIGURE 9 CIRCUIT

VFB1

0.1

FREQ

PLLIN/MODE

0.00001 0.0001 0.001 0.01

0.1

1

10

OUTPUT CURRENT (A)

37881 TA01b

ITH1 SS1 SGND SS2 ITH2

15nF

220μF

15nF

2.7k

100pF

0.1μF

220pF

12.1k

8.66k

12.1k

0.1μF

37881 TA01a

37881fc

1

LTC3788-1

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Notes ±, 3)

VBIAS ........................................................ –0.3V to 40V

BOOST1, BOOST2...................................... –0.3V to 76V

SW1, SW2.................................................. –0.3V to 70V

RUN1, RUN2 ................................................ –0.3V to 8V

Maximum Current Sourced into Pin

TOP VIEW

1

2

SS1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ITH1

VFB1

PGOOD1

SW1

+

3

SENSE1

–

4

TG1

SENSE1

5

BOOST1

BG1

FREQ

PLLIN/MODE

SGND

from Source > 8V .............................................100μA

PGOOD1, PLLIN/MODE ............................... –0.3V to 6V

6

7

VBIAS

PGND

INTV , (BOOST1-SW1, BOOST2-SW2) ...... –0.3V to 6V

CC

8

RUN1

EXTV ........................................................ –0.3V to 6V

CC

9

EXTV

CC

RUN2

+

–

SENSE1 , SENSE1 ,

–

10

11

12

13

14

INTV

CC

SENSE2

SENSE2 , SENSE2 .................................... –0.3V to 40V

+

BG2

SENSE2

–

SENSE1 – SENSE1 ,

BOOST2

TG2

VFB2

ITH2

SS2

SENSE2 – SENSE2 ................................. –0.3V to 0.3V

SS1, SS2, ITH1, ITH2, FREQ,

SW2

VFB1, VFB2 ...........................................–0.3V to INTV

CC

GN PACKAGE

28-LEAD PLASTIC SSOP

Operating Junction Temperature Range....–40°C to 125°C

Storage Temperature Range .................. –65°C to 125°C

Lead Temperature (Soldering, 10 seconds)...........300°C

T

= 125°C, θ = 80°C/W

JMAX

JA

ORDER INFORMATION

LEAD FREE FINISH

LTC3788EGN-1#PBF

LTC3788IGN-1#PBF

TAPE AND REEL

PART MARKING*

LTC3788GN-1

PACKAGE DESCRIPTION

28-Lead Plastic SSOP

TEMPERATURE RANGE

–40°C to 125°C

LTC3788EGN-1#TRPBF

LTC3788IGN-1#TRPBF

–40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at T_A= 25°C, VBIAS = ±2V, unless otherwise noted (Note 2).

SYMBOL

Main Control Loop

VBIAS

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Chip Bias Voltage Operating Range

Regulated Feedback Voltage

Feedback Current

4.5

38

1.212

50

V

l

VFB1,2

I

TH

= 1.2V (Note 4)

1.188

1.200

5

IFB1,2

(Note 4)

= 6V to 38V

nA

V

Reference Line Voltage Regulation

V

IN

0.002

0.02

%/V

REFLNREG

37881fc

2

LTC3788-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at T_A= 25°C, VBIAS = ±2V, unless otherwise noted (Note 2).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Output Voltage Load Regulation

(Note 4)

LOADREG

l

Measured in Servo Loop;

TH

0.01

–0.01

2

0.1

%

ΔI Voltage = 1.2V to 0.7V

Measured in Servo Loop;

–0.1

ΔI Voltage = 1.2V to 2V

TH

g

Error Amplifier Transconductance

Input DC Supply Current

I

TH

= 1.2V

mmho

m1,2

I

(Note 5)

Q

Pulse-Skipping or Forced Continuous Mode RUN1 = 5V and RUN2 = 0V or RUN1 = 0V

(One Channel On) and RUN2 = 5V; V = 1.25V (No Load)

0.9

1.2

mA

μA

FB1(2)

Pulse-Skipping or Forced Continuous Mode RUN1,2 = 5V; V

(Both Channels On)

= 1.25V (No Load)

FB1,2

Sleep Mode

(One Channel On)

RUN1 = 5V and RUN2 = 0V or RUN1 = 0V

and RUN2 = 5V; V = 1.25V (No Load)

125

200

190

300

FB1(2)

Sleep Mode

(Both Channels On)

RUN1,2 = 5V; V

= 1.25V (No Load)

μA

FB1,2

Shutdown

RUN1,2 = 0V

8

20

μA

V

l

UVLO

INTV Undervoltage Lockout Thresholds

V

Ramping Up

4.1

3.8

1.28

100

4.5

0.5

10

4.3

CC

INTVCC

Ramping Down

3.6

V

INTVCC

V

RUN Pin On Threshold

Rising

1.18

1.38

V

RUN1,2

RUNHYS

RUN1,2

SS1,2

RUN

RUN Pin Hysteresis

mV

μA

mV

V

I

RUN Pin Hysteresis Current

RUN Pin Current

V

> 1.28V

RUN

< 1.28V

RUN

Soft-Start Charge Current

Maximum Current Sense Threshold

SENSE Pins Common Mode Range (BOOST

= GND

= 1.1V

SS

FB

l

V

68

75

82

38

SENSE(MAX)

SENSE(CM)

V

2.5

Converter Input Supply Voltage V )

IN

+

I

t

SENSE Pin Current

V

C

= 1.1V

200

300

1

μA

ns

Ω

SENSE1,2

FB

–

SENSE Pin Current

SENSE1,2

FB

Top Gate Rise Time

= 3300pF (Note 6)

20

r(TG1,2)

f(TG1,2)

r(BG1,2)

f(BG1,2)

LOAD

Top Gate Fall Time

Bottom Gate Rise Time

20

Bottom Gate Fall Time

20

R

Top Gate Pull-Up Resistance

Top Gate Pull-Down Resistance

Bottom Gate Pull-Up Resistance

Bottom Gate Pull-Down Resistance

1.2

70

UP(TG1,2)

DN(TG1,2)

UP(TG1,2)

DN(TG1,2)

D(TG/BG)

Ω

t

Top Gate Off to Bottom Gate On

Switch-On Delay Time

C

= 3300pF (Each Driver)

ns

LOAD

t

Bottom Gate Off to Top Gate On

Switch-On Delay Time

70

ns

D(BG/TG)

DF

Maximum BG Duty Factor

Minimum BG On-Time

96

%

MAX(BG1,2)

t

(Note 7)

110

ns

ON(MIN)

37881fc

3

LTC3788-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at T_A= 25°C, VBIAS = ±2V, unless otherwise noted (Note 2).

SYMBOL

PARAMETER

CONDITIONS

MIN

5.2

4.5

TYP

MAX

UNITS

INTV Linear Regulator

CC

V

Internal V Voltage

6V < VBIAS < 38V, V = 0V

EXTVCC

5.4

0.5

5.4

0.5

4.8

250

5.6

2

V

%

V

INTVCCVIN

LDOVIN

CC

INTV Load Regulation

I

CC

= 0mA to 50mA, V

= 0V

CC

EXTVCC

Internal V Voltage

V = 6V

EXTVCC

5.6

2

INTVCCEXT

LDOEXT

CC

INTV Load Regulation

I

CC

= 0mA to 40mA, V

= 6V

%

V

CC

EXTVCC

EXTV Switchover Voltage

EXTV Ramping Positive

5

EXTVCC

CC

EXTV Hysteresis

mV

LDOHYS

CC

Oscillator and Phase-Locked Loop

f

Programmable Frequency

R

= 25k

= 60k

= 100k

= 0V

105

400

760

350

535

kHz

PROG

FREQ

335

465

f

Lowest Fixed Frequency

Highest Fixed Frequency

Synchronizable Frequency

V

320

485

75

380

585

850

LOW

HIGH

SYNC

= INTV

CC

l

PLLIN/MODE = External Clock

PGOOD± and PGOOD2 Outputs

V

PGOOD Voltage Low

PGOOD Leakage Current

PGOOD Trip Level

I

= 2mA

= 5V

0.2

0.4

1

V

PGL

PGOOD

I

V

μA

PGOOD

V

with Respect to Set Regulated Voltage

Ramping Negative

PG

FB

–12

8

–10

2.5

10

–8

12

%

μs

Hysteresis

Ramping Positive

V

FB

Hysteresis

2.5

25

t

PGOOD Delay

PGOOD Going High to Low

PGOOD(DELAY)

BOOST± and BOOST2 Charge Pump

I

BOOST Charge Pump Available

Output Current

V

= 12V; V

– V = 4.5V;

SW1,2

55

μA

BOOST1,2

SW1,2

BOOST1,2

FREQ = 0V, Forced Continuous or

Pulse-Skipping Mode

Note ±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. The maximum

rated junction temperature will be exceeded when this protection is active.

Continuous operation above the specified absolute maximum operating

junction temperature may impair device reliability or permanently damage

the device.

Note 2: The LTC3788-1 is tested under pulsed load conditions such that

T ≈ T . The LTC3788E-1 is guaranteed to meet specifications from

J

A

0°C to 85°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3788I-1 is guaranteed over the full –40°C to 125°C operating junction

temperature range. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

Note 4: The LTC3788-1 is tested in a feedback loop that servos V to the

FB

output of the error amplifier while maintaining I at the midpoint of the

TH

current limit range.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: See Minimum On-Time Considerations in the Applications

Information section.

impedance and other environmental factors. The junction temperature (T ,

J

in °C) is calculated from the ambient temperature (T , in °C) and power

A

dissipation (P , in Watts) according to the formula: T = T + (P • θ ),

D

J

A

D

JA

where θ = 80°C/W.

JA

37881fc

4

LTC3788-1

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency and Power Loss

vs Output Current

100

90

10000

1000

100

10

100

90

10000

1000

100

10

80

70

60

50

60

50

40

30

20

10

0

40

30

20

10

0

V

= 12V

IN

OUT

1

V

= 12V

OUT

FIGURE 9 CIRCUIT

= 24V

IN

= 24V

Burst Mode OPERATION

FIGURE 9 CIRCUIT

0.1

0.01

0.1

1

10

0.00001 0.0001 0.001 0.01

0.1

1

10

OUTPUT CURRENT (A)

37881 G02

37881 G01

BURST EFFICIENCY

BURST LOSS

BURST EFFICIENCY

BURST LOSS

PULSE-SKIPPING

EFFICIENCY

PULSE-SKIPPING

LOSS

CCM EFFICIENCY

CCM LOSS

Load Step

Forced Continuous Mode

Efficiency vs Input Voltage

100

I

= 2A

LOAD

99 FIGURE 9 CIRCUIT

LOAD STEP

2A/DIV

98

V

OUT

= 12V

97

96

95

94

93

92

91

90

INDUCTOR

CURRENT

5A/DIV

V

OUT

= 24V

V

OUT

500mV/DIV

37881 G04

0

5

15

INPUT VOLTAGE (V)

20

25

10

V

= 12V

200μs/DIV

IN

OUT

= 24V

37881 G03

FIGURE 9 CIRCUIT

Load Step

Pulse-Skipping Mode

Load Step

Burst Mode Operation

LOAD STEP

2A/DIV

LOAD STEP

2A/DIV

INDUCTOR

CURRENT

5A/DIV

INDUCTOR

CURRENT

5A/DIV

V

OUT

500mV/DIV

37881 G05

37881 G06

V

= 12V

200μs/DIV

V

= 12V

200μs/DIV

IN

OUT

IN

OUT

= 24V

FIGURE 9 CIRCUIT

37881fc

5

LTC3788-1

TYPICAL PERFORMANCE CHARACTERISTICS

Inductor Current at Light Load

Soft Start-Up

FORCED

CONTINUOUS MODE

Burst Mode

OPERATION

5A/DIV

V

OUT

5V/DIV

PULSE-SKIPPING

MODE

0V

37881 G07

37881 G08

V

LOAD

= 12V

5μs/DIV

V

= 12V

20ms/DIV

IN

OUT

= 24V

OUT

I

= 200μA

FIGURE 9 CIRCUIT

Regulated Feedback Voltage

vs Temperature

Soft-Start Pull-Up Current

vs Temperature

1.212

11.0

10.5

10.0

9.5

1.209

1.206

1.203

1.200

1.197

1.194

1.191

1.188

9.0

–20

5

55

80 105 130

–45

30

–20

5

55

80 105 130

–45

30

TEMPERATURE (°C)

37881 G09

37881 G10

Shutdown Current

vs Input Voltage

Shutdown Current vs Temperature

11.0

10.5

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

20

15

10

5

V

IN

= 12V

0

–20

5

55

80 105 130

–45

30

5

10

20 25 30 35 40

15

INPUT VOLTAGE (V)

0

TEMPERATURE (°C)

37881 G11

37881 G12

37881fc

6

LTC3788-1

TYPICAL PERFORMANCE CHARACTERISTICS

Shutdown (RUN) Threshold

vs Temperature

Undervoltage Lockout Threshold

vs Temperature

Quiescent Current vs Temperature

4.4

4.3

4.2

4.1

4.0

3.9

3.8

3.7

3.6

3.5

3.4

170

160

150

140

130

120

110

100

1.40

1.35

1.30

1.25

1.20

1.15

1.10

V

= 12V

IN

FB

= 1.25V

RUN2 = GND

INTV RISING

CC

RUN RISING

INTV FALLING

CC

RUN FALLING

–20

5

55

80 105 130

–20

5

55

80 105 130

–45

30

–45

30

–20

5

55

80 105 130

–45

30

TEMPERATURE (°C)

37881 G15

37881 G13

37881 G14

EXTV_CCSwitchover and INTV_CC

Voltages vs Temperature

INTV_CCLine Regulation

INTV_CCvs INTV_CCLoad Current

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

5.50

5.45

5.40

5.35

5.30

5.25

5.20

5.15

5.10

5.05

5.00

6.0

5.8

5.6

5.4

5.2

5.0

4.8

4.6

4.4

4.2

4.0

V

= 12V

IN

EXTV = 0V

INTV

CC

EXTV RISING

CC

EXTV = 6V

CC

EXTV FALLING

CC

40 60 80 100 120 200

140 160 180

5

10

20 25 30 35 40

0

20

0

15

–45

5

30

55

80 105 130

–20

INPUT VOLTAGE (V)

INTV LOAD CURRENT (mA)

TEMPERATURE (°C)

CC

37881 G16

37881 G18

37881 G17

Oscillator Frequency

vs Input Voltage

Oscillator Frequency

vs Temperature

Maximum Current Sense

Threshold vs I_THVoltage

600

550

500

450

400

350

300

120

100

80

360

358

356

354

352

350

348

346

344

342

340

FREQ = GND

PULSE-SKIPPING MODE

FORCED CONTINUOUS MODE

Burst Mode OPERATION

FREQ = INTV

CC

60

40

20

0

–20

–40

–60

FREQ = GND

55

80 105 130

0

0.2 0.4 0.6

0.8

VOLTAGE (V)

1.0

1.2 1.4

–45

5

30

–20

5

10

20

25

30

35

40

15

TEMPERATURE (°C)

INPUT VOLTAGE (V)

I

TH

37881 G20

37881 G19

37881 G21

37881fc

7

LTC3788-1

TYPICAL PERFORMANCE CHARACTERISTICS

SENSE Pin Input Current

vs Temperature

SENSE Pin Input Current

vs I_THVoltage

SENSE Pin Input Current

vs V_SENSEVoltage

260

240

220

200

180

160

140

120

100

80

260

240

220

200

180

160

140

120

100

80

260

240

220

200

180

160

140

120

100

80

V

= 12V

V

= 12V

SENSE

+

SENSE PIN

+

SENSE PIN

60

40

20

0

20

0

–

SENSE PIN

0

–45

5

30

55

80 105 130

2.5

17.5 22.5 27.5 32.5 37.5

COMMON MODE VOLTAGE (V)

–20

7.5 12.5

0

1

I

1.5

2

2.5

3

0.5

TEMPERATURE (°C)

V

VOLTAGE (V)

SENSE

TH

37881 G22

37881 G24

37881 G23

Maximum Current Sense

Threshold vs Duty Cycle

Charge Pump Charging Current

vs Operating Frequency

80

120

100

80

60

40

20

0

V

= 12V

SW

BOOST

– V = 4.5V

SW

70

60

50

40

30

20

10

0

T = –45°C

T = 25°C

T = 130°C

20 30 40 50 60

100

70 80 90

0

10

50 150 250 350 450 550 650 750

OPERATING FREQUENCY (kHz)

DUTY CYCLE (%)

37881 G26

37881 G25

PIN FUNCTIONS

ITH±, ITH2 (Pin ±, Pin ±3): Current Control Threshold

and Error Amplifier Compensation Point. The voltage on

this pin sets the current trip threshold.

+

SENSE± , SENSE2 (Pin 3, Pin ±±): Positive Current

Sense Comparator Input. The (+) input to the current

comparator is normally connected to the positive terminal

of a current sense resistor. The current sense resistor is

normally placed at the input of the boost controller in

series with the inductor. This pin also supplies power to

the current comparator.

VFB±, VFB2 (Pin 2, Pin ±2): Error Amplifier Feedback

Input. This pin receives the remotely sensed feedback

voltagefromanexternalresistivedividerconnectedacross

the output.

37881fc

8

LTC3788-1

PIN FUNCTIONS

–

SENSE± , SENSE2 (Pin 4, Pin ±0): Negative Current

Sense Comparator Input. The (–) input to the current

comparatorisnormallyconnectedtothenegativeterminal

of a current sense resistor connected in series with the

inductor. The common mode voltage range on these pins

is 2.5V to 38V (40V abs max).

INTV (Pin ±9): Output of Internal 5.4V LDO. Power

CC

supply for control circuits and gate drives. Decouple this

pin to GND with a minimum 4.7μF low ESR tantalum or

ceramic capacitor.

EXTV (Pin 20): External Power Input. When this pin is

CC

higher than 4.8V an internal switch bypasses the internal

FREQ (Pin 5): The frequency control pin for the internal

regulatorandsupplypowertoINTV directlyfromEXTV .

CC CC

VCO. Connecting the pin to GND forces the VCO to a fixed

PGND (Pin 2±): Driver Power Ground. Connects to the

low frequency of 350kHz. Connecting the pin to INTV

CC

sources of bottom (main) N-channel MOSFETs and the

forces the VCO to a fixed high frequency of 535kHz. The

frequency can be programmed from 50kHz to 900kHz

by connecting a resistor from the FREQ pin to GND. The

resistor and an internal 20μA source current create a volt-

age used by the internal oscillator to set the frequency.

Alternatively, this pin can be driven with a DC voltage to

vary the frequency of the internal oscillator.

(–) terminal(s) of C and C

.

IN

OUT

VBIAS (Pin 22): Main Supply Pin. It is normally tied to the

input supply V or to the output of the boost converter. A

IN

bypass capacitor should be tied between this pin and the

signal ground pin. The operating voltage range on this pin

is 4.5V to 38V (40V abs max).

BG±, BG2 (Pin 23, Pin ±8): Bottom Gate. Connect to the

PLLIN/MODE (Pin 6): External Synchronization Input

to Phase Detector and Forced Continuous Mode Input.

When an external clock is applied to this pin, it will force

the controller into forced continuous mode of operation

and the phase-locked loop will force the rising BG1 signal

to be synchronized with the rising edge of the external

clock. When not synchronizing to an external clock, this

input, which acts on both controllers, determines how

the LTC3788-1 operates at light loads. Pulling this pin to

ground selects Burst Mode operation. An internal 100k

resistortogroundalsoinvokesBurstModeoperationwhen

gate of the main NMOS.

BOOST±,BOOST2(Pin24,Pin±7): Floatingpowersupply

forthesynchronousNMOS.BypasstoSWwithacapacitor

and supply with a Schottky diode connected to INTV .

CC

TG±, TG2 (Pin 25, Pin ±6): Top Gate. Connect to the gate

of the synchronous NMOS.

SW±, SW2 (Pin 26, Pin ±5): Switch Node. Connect to the

source of the synchronous NMOS, the drain of the main

NMOS and the inductor.

the pin is floated. Tying this pin to INTV forces continu-

CC

PGOOD± (Pin 27): Power Good Indicator for Channel 1.

Open-drain logic output that is pulled to ground when

the output voltage is more than 10% away from the

regulated output voltage. To avoid false trips the output

voltage must be outside the range for 25μs before this

output is activated.

ous inductor current operation. Tying this pin to a voltage

greater than 1.2V and less than INTV – 1.3V selects

CC

pulse-skipping operation. This can be done by adding a

100k resistor between the PLLIN/MODE pin and INTV .

CC

SGND (Pin 7): Signal Ground. All small-signal components

and compensation components should connect to this

ground, which in turn connects to PGND at a single point.

SS±, SS2 (Pin 28, Pin ±4): Output Soft-Start Input. A

capacitor to ground at this pin sets the ramp rate of the

output voltage during start-up.

RUN±,RUN2(Pin8,Pin9):RunControlInput.Anexternal

resistordividerconnectstoV andsetsthethresholdsfor

IN

converter operation with a threshold of 1.28V. Once run-

ning,a4.5μAcurrentissourcedfromtheRUNpinallowing

the user to program hysteresis using the resistor values.

37881fc

9

LTC3788-1

BLOCK DIAGRAM

INTV

CC

D

DUPLICATE FOR SECOND CONTROLLER CHANNEL

S

B

PGOOD1

BOOST

+

–

1.32V

Q

R

C

TG

B

VFB1

1.08V

20μA

SHDN

+

–

SWITCHING

LOGIC

V

OUT

SW

AND

CHARGE

PUMP

C

OUT

INTV

CC

FREQ

CLK2

CLK1

BG

VCO

PFD

+

–

0.425V

–

SLEEP

PGND

L

+

–

+

–

2mV

SENSE

VFB

2.8V

0.7V

PLLIN/

MODE

R

SENSE

+

SLOPE COMP

SENS LO

SYNC

DET

V

IN

C

+

IN

100k

–

2.5V

+

–

1.2V

SS

EA

+

–

OV

VBIAS

1.32V

C

ITH

0.5μA/

4.5μA

SHDN

EXTV

CC

R

C

C2

10μA

11V

5.4V

LDO

5.4V

LDO

+

–

EN

3.8V

SENS

LO

SHDN

RUN

+

–

INTV

CC

SGND

SS

4.8V

37881 BD

C

SS

37881fc

10

LTC3788-1

OPERATION ^{(Refer to Block Diagram)}

Main Control Loop

both controllers and most internal circuits, including the

INTV LDO’s. In this state, the LTC3788-1 draws only

CC

The LTC3788-1 uses a constant-frequency, current mode

step-uparchitecturewiththetwocontrollerchannelsoper-

ating180degreesout-of-phase. Duringnormaloperation,

eachexternalbottomMOSFETisturnedonwhentheclock

for that channel sets the RS latch, and is turned off when

the main current comparator, ICMP, resets the RS latch.

The peak inductor current at which ICMP trips and resets

the latch is controlled by the voltage on the ITH pin, which

is the output of the error amplifier EA. The error amplifier

compares the output voltage feedback signal at the VFB

pin, (which is generated with an external resistor divider

8μA of quiescent current.

The RUN pin may be externally pulled up or driven directly

by logic. When driving the RUN pin with a low impedance

source, do not exceed the absolute maximum rating of

8V. The RUN pin has an internal 11V voltage clamp that

allows the RUN pin to be connected through a resistor to a

highervoltage(forexample, V ), aslongasthemaximum

IN

current into the RUN pin does not exceed 100μA.

The start-up of each controller’s output voltage V

is

OUT

controlled by the voltage on the SS pin for that channel.

When the voltage on the SS pin is less than the 1.2V in-

connected across the output voltage, V , to ground) to

OUT

the internal 1.200V reference voltage. When the load cur-

ternal reference, the LTC3788-1 regulates the V voltage

FB

rent increases, it causes a slight decrease in V relative

FB

to the SS pin voltage instead of the 1.2V reference. This

allows the SS pin to be used to program a soft-start by

connectinganexternalcapacitorfromtheSSpintoSGND.

An internal 10μA pull-up current charges this capacitor

creating a voltage ramp on the SS pin. As the SS voltage

to the reference, which causes the EA to increase the I

TH

voltage until the average inductor current matches the

new load current.

After the bottom MOSFET is turned off each cycle, the

top MOSFET is turned on until either the inductor current

starts to reverse, as indicated by the current comparator

IR, or the beginning of the next clock cycle.

rises linearly from 0V to 1.2V (and beyond up to INTV ),

CC

the output voltage V

rises smoothly to its final value.

OUT

Light Load Current Operation—Burst Mode Operation,

Pulse-Skipping or Continuous Conduction

(PLLIN/MODE Pin)

INTV /EXTV Power

CC

Power for the top and bottom MOSFET drivers and most

other internal circuitry is derived from the INTV pin.

The LTC3788-1 can be enabled to enter high efficiency

BurstModeoperation,constant-frequencypulse-skipping

mode or forced continuous conduction mode at low load

currents. To select Burst Mode operation, tie the PLLIN/

MODE pin to a ground (e.g., SGND). To select forced con-

CC

When the EXTV pin is left open or tied to a voltage less

CC

than 4.8V, the VBIAS LDO (low dropout linear regulator)

supplies 5.4V from VBIAS to INTV . If EXTV is taken

CC

above 4.8V, the VBIAS LDO is turned off and an EXTV

CC

tinuous operation, tie the PLLIN/MODE pin to INTV . To

LDOisturnedon. Onceenabled, theEXTV LDOsupplies

CC

select pulse-skipping mode, tie the PLLIN/MODE pin to a

5.4V from EXTV to INTV . Using the EXTV pin allows

CC

DC voltage greater than 1.2V and less than INTV – 0.5V.

the INTV power to be derived from a high efficiency

CC

external source such as one of the LTC3788-1 switching

WhenacontrollerisenabledforBurstModeoperation, the

minimum peak current in the inductor is set to approxi-

mately 30% of the maximum sense voltage even though

the voltage on the ITH pin indicates a lower value. If the

average inductor current is higher than the load current,

the error amplifier EA will decrease the voltage on the ITH

regulator outputs.

Shutdown and Start-Up

(RUN±, RUN2 and SS±, SS2 Pins)

The two channels of the LTC3788-1 can be independently

shutdownusingtheRUN1andRUN2pins.Pullingeitherof

these pins below 1.28V shuts down the main control loop

for that controller. Pulling both pins below 0.7V disables

pin. When the I voltage drops below 0.425V, the internal

TH

sleep signal goes high (enabling sleep mode) and both

external MOSFETs are turned off.

37881fc

11

LTC3788-1

OPERATION

In sleep mode, much of the internal circuitry is turned off,

reducing the quiescent current that the LTC3788-1 draws.

If one channel is shut down and the other channel is in

sleepmode,theLTC3788-1drawsonly125μAofquiescent

current.Ifbothchannelsareinsleepmode,theLTC3788-1

draws only 200μA of quiescent current. In sleep mode,

the load current is supplied by the output capacitor. As

the output voltage decreases, the EA’s output begins to

rise. When the output voltage drops enough, the ITH pin

is reconnected to the output of the EA, the sleep signal

goes low, and the controller resumes normal operation

by turning on the bottom external MOSFET on the next

cycle of the internal oscillator.

exhibits low output ripple as well as low audio noise and

reduced RF interference as compared to Burst Mode

operation. It provides higher low current efficiency than

forced continuous mode, but not nearly as high as Burst

Mode operation.

Frequency Selection and Phase-Locked Loop (FREQ

and PLLIN/MODE Pins)

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

When a controller is enabled for Burst Mode operation,

the inductor current is not allowed to reverse. The reverse

currentcomparator(IR)turnsoffthetopexternalMOSFET

just before the inductor current reaches zero, preventing

it from reversing and going negative. Thus, the controller

operates in discontinuous current operation.

The switching frequency of the LTC3788-1’s controllers

can be selected using the FREQ pin.

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to SGND, tied to

INTV , or programmed through an external resistor.

CC

Tying FREQ to SGND selects 350kHz while tying FREQ to

In forced continuous operation or when clocked by an

external clock source to use the phase-locked loop (see

theFrequencySelectionandPhase-LockedLoopsection),

the inductor current is allowed to reverse at light loads or

under large transient conditions. The peak inductor cur-

rent is determined by the voltage on the ITH pin, just as

in normal operation. In this mode, the efficiency at light

loads is lower than in Burst Mode operation. However,

continuous operation has the advantages of lower output

voltage ripple and less interference to audio circuitry, as

it maintains constant-frequency operation independent

of load current.

INTV selects 535kHz. Placing a resistor between FREQ

CC

andSGNDallowsthefrequencytobeprogrammedbetween

50kHz and 900kHz, as shown in Figure 6.

A phase-locked loop (PLL) is available on the LTC3788-1

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

LTC3788-1’s phase detector adjusts the voltage (through

an internal lowpass filter) of the VCO input to align the

turn-on of the first controller’s external bottom MOSFET

to the rising edge of the synchronizing signal. Thus, the

turn-on of the second controller’s external bottom MOS-

FET is 180 degrees out-of-phase to the rising edge of the

external clock source.

WhenthePLLIN/MODEpinisconnectedforpulse-skipping

mode, the LTC3788-1 operates in PWM pulse-skipping

mode at light loads. In this mode, constant-frequency

operation is maintained down to approximately 1% of

designedmaximumoutputcurrent. Atverylightloads, the

The VCO input voltage is prebiased to the operating fre-

quency set by the FREQ pin before the external clock is

applied. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of BG1. The ability to

prebias the loop filter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

current comparator I

may remain tripped for several

CMP

cycles and force the external bottom MOSFET to stay off

for the same number of cycles (i.e., skipping pulses). The

inductor current is not allowed to reverse (discontinuous

operation). This mode, like forced continuous operation,

37881fc

12

LTC3788-1

OPERATION

The typical capture range of the LTC3788-1’s PLL is from

approximately 55kHz to 1MHz, and is guaranteed to

lock to an external clock source whose frequency is be-

tween 75kHz and 850kHz.

Power Good

The PGOOD1 pin is connected to an open-drain of an in-

ternalN-channelMOSFET. TheMOSFETturnsonandpulls

the PGOOD1 pin low when the corresponding VFB1 pin

voltage is not within 10% of the 1.2V reference voltage.

ThePGOOD1pinisalsopulledlowwhenthecorresponding

RUN1 pin is low (shut down). When the VFB1 pin voltage

is within the 10% requirement, the MOSFET is turned

off and the pin is allowed to be pulled up by an external

resistor to a source of up to 6V.

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.2V (falling).

Operation When V > V

IN

OUT

When V rises above the regulated V

voltage, the

IN

OUT

boost controller can behave differently depending on the

mode, inductor current and V voltage. In forced con-

IN

tinuous mode, the loop works to keep the top MOSFET

Operation at Low SENSE Pin Common Voltage

on continuously once V rises above V . The internal

IN

OUT

The current comparator in the LTC3788-1 is powered

directly from the SENSE pin. This enables the common

charge pump delivers current to the boost capacitor to

maintain a sufficiently high TG voltage.

+

–

modevoltageofSENSE andSENSE pinstooperateatas

low as 2.5V, which is below the UVLO threshold. Figure 1

shows a typical application when the controller’s VBIAS

Inpulse-skippingmode,ifV isbetween100%and110%

IN

of the regulated V

voltage, TG turns on if the inductor

OUT

current rises above a certain threshold and turns off if the

inductor current falls below this threshold. This thresh-

old current is set approximately to 4% of the maximum

current. If the controller is programmed to Burst Mode

is powered from V

while V supply can go as low as

OUT

IN

+

2.5V. If the voltage on SENSE drops below 2.5V, the SS

pin will be held low. When the SENSE voltage returns to

the normal operating range, the SS pin will be released,

initiating a new soft-start cycle.

operation under this same V window, then TG remains

off regardless of the inductor current.

IN

BOOST Supply Refresh and Internal Charge Pump

If V rises above 110% of the regulated V

voltage in

IN

OUT

any mode, the controller turns on TG regardless of the

inductor current. In Burst Mode operation, however, the

internal charge pump turns off if the entire chip is asleep

(theotherchannelisasleeporshutdown).Withthecharge

pump off, there would be nothing to prevent the boost

capacitor from discharging, resulting in an insufficient TG

voltage needed to keep the top MOSFET completely on.

To prevent excessive power dissipation across the body

diode of the top MOSFET in this situation, the chip can be

switched over to forced continuous mode to enable the

charge pump, or a Schottky diode can also be placed in

parallel to the top MOSFET.

Each top MOSFET driver is biased from the floating

bootstrap capacitor C , which normally recharges dur-

B

ing each cycle through an external diode when the bot-

tom MOSFET turns on. There are two considerations to

keep the BOOST supply at the required bias level. During

start-up, if the bottom MOSFET is not turned on within

100μs after UVLO goes low, the bottom MOSFET will be

forced to turn on for ~400ns. This forced refresh gener-

ates enough BOOST-SW voltage to allow the top MOSFET

ready to be fully enhanced instead of waiting for the initial

few cycles to charge up. There is also an internal charge

pump that keeps the required bias on BOOST. The charge

pump always operates in both forced continuous mode

and pulse-skipping mode. In Burst Mode operation, the

charge pump is turned off during sleep and enabled when

thechipwakesup. Theinternalchargepumpcannormally

supply a charging current of 55μA.

37881fc

13

LTC3788-1

APPLICATIONS INFORMATION

+

–

The Typical Application on the first page is a basic

LTC3788-1applicationcircuit.LTC3788-1canbeconfigured

to use either inductor DCR (DC resistance) sensing or a

SENSE and SENSE Pins

+

–

The SENSE and SENSE pins are the inputs to the cur-

rent comparators. The common mode input voltage range

of the current comparators is 2.5V to 38V. The current

sense resistor is normally placed at the input of the boost

controller in series with the inductor.

discrete sense resistor (R

) for current sensing. The

SENSE

choicebetweenthetwocurrentsensingschemesislargely

a design trade-off between cost, power consumption and

accuracy. DCR sensing is becoming popular because it

does not require current sensing resistors and is more

power-efficient, especially in high current applications.

However, current sensing resistors provide the most

accurate current limits for the controller. Other external

component selection is driven by the load requirement,

+

The SENSE pin also provides power to the current

comparator. It draws ~200μA during normal operation.

There is a small base current of less than 1μA that flows

into the SENSE pin. The high impedance SENSE input

to the current comparators allow accurate DCR sensing.

–

and begins with the selection of R

(if R

is used)

SENSE

Filter components mutual to the sense lines should be

placed close to the LTC3788-1, and the sense lines should

run close together to a Kelvin connection underneath the

current sense element (shown in Figure 1). Sensing cur-

rent elsewhere can effectively add parasitic inductance

and capacitance to the current sense element, degrading

the information at the sense terminals and making the

programmed current limit unpredictable. If DCR sensing

is used (Figure 2b), sense resistor R1 should be placed

closetotheswitchingnode,topreventnoisefromcoupling

into sensitive small-signal nodes.

andinductorvalue.Next,thepowerMOSFETsareselected.

Finally, input and output capacitors are selected.

TO SENSE FILTER,

NEXT TO THE CONTROLLER

V

IN

INDUCTOR OR R

37881 F01

SENSE

Figure ±. Sense Lines Placement with

Inductor or Sense Resistor

VBIAS

V

IN

+

SENSE

C1

R2

(OPTIONAL)

DCR

L

–

SENSE

INTV

SENSE

INTV

CC

INDUCTOR

R1

LTC3788-1

BOOST

TG

V

OUT

V

OUT

SW

BG

SW

BG

SGND

37881 F02b

37881 F02a

L

DCR

R2

R1 + R2

||

(R1 R2) • C1 =

R

= DCR •

PLACE C1 NEAR SENSE PINS

SENSE(EQ)

(2a) Using a Resistor to Sense Current

(2b) Using the Inductor DCR to Sense Current

Figure 2. Two Different Methods of Sensing Current

37881fc

14

LTC3788-1

APPLICATIONS INFORMATION

Sense Resistor Current Sensing

Using the inductor ripple current value from the inductor

valuecalculationsection,thetargetsenseresistorvalueis:

A typical sensing circuit using a discrete resistor is shown

V

SENSE(MAX)

in Figure 2a. R

output current.

is chosen based on the required

SENSE

R

=

SENSE(EQUIV)

ΔI

L

I

+

MAX

2

The current comparator has a maximum threshold

. The current comparator threshold sets the

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimum value for the maximum current sense threshold

V

SENSE(MAX)

peak of the inductor current, yielding a maximum average

output current, I

, equal to the peak value less half the

MAX

(V

).

SENSE(MAX)

peak-to-peak ripple current, ΔI . To calculate the sense

L

Next, determine the DCR of the inductor. Where provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefficientofresistance,whichisapproximately0.4%/°C.A

conservativevalueforthemaximuminductortemperature

resistor value, use the equation:

V

SENSE(MAX)

R

=

SENSE

ΔI

L

I

+

MAX

2

When using the controller in low V and very high voltage

IN

(T

L(MAX)

) is 100°C.

outputapplications,themaximumoutputcurrentlevelwill

be reduced due to the internal compensation required to

meet stability criterion for boost regulators operating at

greater than 50% duty factor. A curve is provided in the

Typical Performance Characteristics section to estimate

thisreductioninpeakoutputcurrentleveldependingupon

the operating duty factor.

To scale the maximum inductor DCR to the desired sense

resistor value, use the divider ratio:

R_SENSE(EQUIV)

R_D=

DCR_MAXat T

L(MAX)

C1 is usually selected to be in the range of 0.1μF to 0.47μF.

ThisforcesR1||R2toaround2k,reducingerrorthatmight

+

Inductor DCR Sensing

have been caused by the SENSE pin’s 1μA current.

For applications requiring the highest possible efficiency

at high load currents, the LTC3788-1 is capable of sensing

the voltage drop across the inductor DCR, as shown in

Figure 2b. The DCR of the inductor can be less than 1mΩ

for high current inductors. In a high current application

requiring such an inductor, conduction loss through a

sense resistor could reduce the efficiency by a few percent

compared to DCR sensing.

The equivalent resistance R1|| R2 is scaled to the room

temperature inductance and maximum DCR:

L

R1||R2 =

(DCR at 20°C)•C1

The sense resistor values are:

R1||R2

R_D

R1•R_D

1−R_D

R1=

; R2 =

If the external R1||R2 • C1 time constant is chosen to be

exactly equal to the L/DCR time constant, the voltage drop

across the external capacitor is equal to the drop across

theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe

voltage across the sense terminals for applications where

the DCR is greater than the target sense resistor value.

To properly dimension the external filter components, the

DCR of the inductor must be known. It can be measured

using a good RLC meter, but the DCR tolerance is not

always the same and varies with temperature. Consult

the manufacturer’s data sheets for detailed information.

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at V = 1/2 V

:

IN

OUT

(V_OUT− V )• V

IN

P_LOSSR1=

R1

Ensure that R1 has a power rating higher than this value.

If high efficiency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

sense resistors. Light load power loss can be modestly

higher with a DCR network than with a sense resistor,

37881fc

15

LTC3788-1

APPLICATIONS INFORMATION

due to the extra switching losses incurred through R1.

However,DCRsensingeliminatesasenseresistor,reduces

conduction losses and provides higher efficiency at heavy

loads.Peakefficiencyisaboutthesamewitheithermethod.

selected. As inductance increases, core losses go down.

Unfortunately,becauseincreasedinductancerequiresmore

turns of wire, copper losses will increase.

Ferrite core inductors have very low core loss and are

preferred at high switching frequencies, so design goals

can concentrate on copper loss and preventing satura-

tion. Ferrite core material saturates “hard,” which means

that inductance collapses abruptly when the peak design

current is exceeded. This results in an abrupt increase in

inductor ripple current and consequent output voltage

ripple. Do not allow the core to saturate!

Inductor Value Calculation

The operating frequency and inductor selection are inter-

relatedinthathigheroperatingfrequenciesallowtheuseof

smaller inductor and capacitor values. Why would anyone

ever choose to operate at lower frequencies with larger

components?Theanswerisefficiency.Ahigherfrequency

generally results in lower efficiency because of MOSFET

gate charge and switching losses. In addition to this basic

trade-off, the effect of inductor value on ripple current and

low current operation must also be considered.

Power MOSFET Selection

Two external power MOSFETs must be selected for each

controller in the LTC3788-1: one N-channel MOSFET for

the bottom (main) switch, and one N-channel MOSFET

for the top (synchronous) switch.

The inductor value has a direct effect on ripple current.

The inductor ripple current ΔI decreases with higher

L

inductance or frequency and increases with higher V :

IN

The peak-to-peak gate drive levels are set by the INTV

CC

voltage. This voltage is typically 5.2V during start-up

⎛

⎞

V

f •L

V

IN

V_OUT

IN

ΔI_L=

1−

(see EXTV pin connection). Consequently, logic-level

⎜

⎟

CC

⎝

⎠

threshold MOSFETs must be used in most applications.

Accepting larger values of ΔI allows the use of low

The only exception is if low input voltage is expected (V

L

IN

inductances, but results in higher output voltage ripple

< 5V); then, sub-logic level threshold MOSFETs (V

GS(TH)

and greater core losses. A reasonable starting point for

< 3V) should be used. Pay close attention to the BV

DSS

setting ripple current is ΔI = 0.3(I

). The maximum

MAX

specification for the MOSFETs as well; many of the logic

level MOSFETs are limited to 30V or less.

L

ΔI occurs at V = 1/2 V .

L

IN

OUT

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

Selection criteria for the power MOSFETs include the

on-resistance R

, Miller capacitance C

, input

DS(ON)

MILLER

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

10% of the current limit determined by R

. Lower

C

SENSE

MILLER

inductor values (higher ΔI ) will cause this to occur at

usually provided on the MOSFET manufacturer’s data

sheet. C is equal to the increase in gate charge

L

lower load currents, which can cause a dip in efficiency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

MILLER

along the horizontal axis while the curve is approximately

flat divided by the specified change in V . This result is

DS

then multiplied by the ratio of the application applied V

DS

to the gate charge curve specified V . When the IC is

DS

Inductor Core Selection

operating in continuous mode, the duty cycles for the top

and bottom MOSFETs are given by:

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcingtheuseofmoreexpensiveferriteormolypermalloy

cores. Actual core loss is independent of core size for a

fixedinductorvalue,butitisverydependentoninductance

V_OUT− V

IN

Main SwitchDuty Cycle =

V_OUT

V

V_OUT

IN

Synchronous SwitchDuty Cycle =

37881fc

16

LTC3788-1

APPLICATIONS INFORMATION

The MOSFET power dissipations at maximum output

current are given by:

possible overvoltage transients that could apply excess

stress to the input capacitors.

The value of the C is a function of the source impedance,

(V_OUT− V )V

IN

2

OUT

P_MAIN

=

•I_OUT(MAX)²• 1+ δ

(

)

andingeneral,thehigherthesourceimpedance,thehigher

the required input capacitance. The required amount of

inputcapacitanceisalsogreatlyaffectedbythedutycycle.

High output current applications that also experience high

duty cycles can place great demands on the input supply,

both in terms of DC current and ripple current.

V_IN

I_OUT(MAX)

3

• R_DS(ON)+k • V_OUT

•

•R_DR

V

IN

• C_MILLER• f

V

V_OUT

P

=

•I_OUT(MAX)²• 1+ δ •R

DS(ON)

IN

Inaboostconverter,theoutputhasadiscontinuouscurrent,

(

)

SYNC

so C

must be capable of reducing the output voltage

OUT

ripple.TheeffectsofESR(equivalentseriesresistance)and

the bulk capacitance must be considered when choosing

the right capacitor for a given output ripple voltage. The

steady ripple voltage due to charging and discharging the

bulk capacitance is given by:

where δ is the temperature dependency of R

DR

at the MOSFET’s Miller threshold voltage. The constant k,

which accounts for the loss caused by reverse recovery

current, is inversely proportional to the gate drive current

and has an empirical value of 1.7.

and

DS(ON)

R

(approximately 1Ω) is the effective driver resistance

I

_OUT(MAX)•(V_OUT− V_IN(MIN))

V_RIPPLE

=

V

C_OUT• V_OUT• f

is the output filter capacitor.

2

BothMOSFETshaveI RlosseswhilethebottomN-channel

equation includes an additional term for transition losses,

where C

OUT

which are highest at low input voltages. For high V the

IN

The steady ripple due to the voltage drop across the ESR

is given by:

high current efficiency generally improves with larger

MOSFETs, while for low V the transition losses rapidly

IN

increasetothepointthattheuseofahigherR

device

ΔV

= I

• ESR

DS(ON)

ESR

L(MAX)

withlowerC

actuallyprovideshigherefficiency.The

MILLER

The LTC3788-1 can also be configured as a 2-phase single

output converter where the outputs of the two channels

are connected together and both channels have the same

duty cycle. With 2-phase operation, the two channels of

the dual switching regulator are operated 180 degrees

out-of-phase.Thiseffectivelyinterleavestheoutputcurrent

pulses,greatlyreducingtheoutputcapacitorripplecurrent.

As a result, the ESR requirement of the capacitor can be

relaxed. Because the ripple current in the output capacitor

is a square wave, the ripple current requirements for the

output capacitor depend on the duty cycle, the number

of phases and the maximum output current. Figure 3 il-

lustrates the normalized output capacitor ripple current

as a function of duty cycle in a 2-phase configuration. To

choose a ripple current rating for the output capacitor,

first establish the duty cycle range based on the output

voltage and range of input voltage. Referring to Figure 3,

choose the worst-case high normalized ripple current as

a percentage of the maximum load current.

synchronous MOSFET losses are greatest at high input

voltage when the bottom switch duty factor is low or dur-

ing overvoltage when the synchronous switch is on close

to 100% of the period.

The term (1+ δ) is generally given for a MOSFET in the

form of a normalized R

vs Temperature curve, but

DS(ON)

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

C and C

IN

Selection

OUT

The input ripple current in a boost converter is relatively

low(comparedwiththeoutputripplecurrent),becausethis

currentiscontinuous.TheinputcapacitorC voltagerating

IN

should comfortably exceed the maximum input voltage.

Although ceramic capacitors can be relatively tolerant of

overvoltage conditions, aluminum electrolytic capacitors

are not. Be sure to characterize the input voltage for any

37881fc

17

LTC3788-1

APPLICATIONS INFORMATION

3.25

3.00

2.75

2.50

2.25

2.00

1.75

Soft-Start (SS Pins)

The start-up of each V

is controlled by the voltage on

OUT

the respective SS pins. When the voltage on the SS pin

is less than the internal 1.2V reference, the LTC3788-1

regulates the VFB pin voltage to the voltage on the SS

pin instead of 1.2V.

1.50

1.25

1.00

0.75

0.50

0.25

0

1-PHASE

Soft-startisenabledbysimplyconnectingacapacitorfrom

the SS pin to ground, as shown in Figure 5. An internal

10μA current source charges the capacitor, providing a

linear ramping voltage at the SS pin. The LTC3788-1 will

2-PHASE

0.4 0.5

DUTY CYCLE OR (1-V /V

0.1 0.2 0.3

0.6 0.7 0.8 0.9

)

IN OUT

37881 F03

regulate the VFB pin (and hence, V ) according to the

OUT

voltage on the SS pin, allowing V

to rise smoothly

OUT

Figure 3. Normalized Output Capacitor Ripple

Current (RMS) for a Boost Converter

from V to its final regulated value. The total soft-start

IN

time will be approximately:

1.2V

10μA

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic and

ceramic capacitors are all available in surface mount

packages. Ceramic capacitors have excellent low ESR

characteristics but can have a high voltage coefficient.

Capacitors are now available with low ESR and high ripple

current ratings (i.e., OS-CON and POSCAP).

t_SS= C_SS

•

LTC3788-1

SS

C

SS

SGND

37881 F05

Figure 5. Using the SS Pin to Program Soft-Start

INTV Regulators

Setting Output Voltage

CC

The LTC3788-1 features two separate internal P-channel

low dropout linear regulators (LDO) that supply power at

The LTC3788-1 output voltages are each set by an exter-

nal feedback resistor divider carefully placed across the

output, as shown in Figure 4. The regulated output voltage

is determined by:

the INTV pin from either the VBIAS supply pin or the

CC

EXTV pin depending on the connection of the EXTV

CC

pin. INTV powers the gate drivers and much of the

CC

⎛

⎞

⎟

⎠

R_B

R_A

LTC3788-1’s internal circuitry. The VBIAS LDO and the

V_OUT= 1.2V 1+

⎜

⎝

EXTV LDO regulate INTV to 5.4V. Each of these can

CC

supply a peak current of 50mA and must be bypassed to

ground with a minimum of 4.7μF ceramic capacitor. Good

bypassing is needed to supply the high transient currents

required by the MOSFET gate drivers and to prevent in-

teraction between the channels.

Great care should be taken to route the V line away from

FB

noise sources, such as the inductor or the SW line.

V

OUT

R

B

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3788-1 to be

LTC3788-1

VFB

R

A

exceeded. The INTV current, which is dominated by the

CC

37881 F04

gate charge current, may be supplied by either the VBIAS

LDO or the EXTV LDO. When the voltage on the EXTV

Figure 4. Setting Output Voltage

CC

pin is less than 4.8V, the VBIAS LDO is enabled. In this

37881fc

18

LTC3788-1

APPLICATIONS INFORMATION

case, power dissipation for the IC is highest and is equal

Topside MOSFET Driver Supply (C , D )

B B

to V • I

. The gate charge current is dependent

INTVCC

IN

External bootstrap capacitors C connected to the BOOST

B

on operating frequency, as discussed in the Efficiency

Considerations section. The junction temperature can be

estimated by using the equations given in Note 3 of the

Electrical Characteristics. For example, the LTC3788-1

pins supply the gate drive voltages for the topside MOS-

FETs.CapacitorC intheBlockDiagramischargedthough

B

external diode D from INTV when the SW pin is low.

B

CC

When one of the topside MOSFETs is to be turned on, the

INTV current is limited to less than 15mA from a 40V

CC

driver places the C voltage across the gate-source of the

B

supply when not using the EXTV supply:

CC

desired MOSFET. This enhances the MOSFET and turns on

T = 70°C + (15mA)(40V)(90°C/W) = 125°C

J

the topside switch. The switch node voltage, SW, rises to

V and the BOOST pin follows. With the topside MOSFET

IN

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

operating in continuous conduction mode (PLLIN/MODE

on, the boost voltage is above the input supply: V

=

BOOST

B

V + V

. The value of the boost capacitor C needs

IN

INTVCC

to be 100 times that of the total input capacitance of the

= INTV ) at maximum V .

CC

IN

topsideMOSFET(s).Thereversebreakdownoftheexternal

Schottky diode must be greater than V

When the voltage applied to EXTV rises above 4.8V, the

CC

.

IN(MAX)

V LDO is turned off and the EXTV LDO is enabled. The

IN

CC

The external diode D can be a Schottky diode or silicon

B

EXTV LDO remains on as long as the voltage applied to

CC

diode,butineithercaseitshouldhavelowleakageandfast

recovery. Paycloseattentiontothereverseleakageathigh

temperatures where it generally increases substantially.

EXTV remains above 4.55V. The EXTV LDO attempts

CC

to regulate the INTV voltage to 5.4V, so while EXTV

CC

is less than 5.4V, the LDO is in dropout and the INTV

voltage is approximately equal to EXTV . When EXTV

CC

Each of the topside MOSFET drivers includes an internal

chargepumpthatdeliverscurrenttothebootstrapcapaci-

tor from the BOOST pin. This charge current maintains

the bias voltage required to keep the top MOSFET on

continuously during dropout/overvoltage conditions. The

Schottky/silicon diodes selected for the topside drivers

shouldhaveareverseleakagelessthantheavailableoutput

current the charge pump can supply. Curves displaying

the available charge pump current under different operat-

ing conditions can be found in the Typical Performance

Characteristics section.

is greater than 5.4V, up to an absolute maximum of 6V,

INTV is regulated to 5.4V.

CC

Significant thermal gains can be realized by powering

INTV from an external supply. Tying the EXTV pin

CC

to a 5V supply reduces the junction temperature in the

previous example from 125°C to 77°C:

T = 70°C + (15mA)(5V)(90°C/W) = 77°C

J

If more current is required through the EXTV LDO than

CC

is specified, an external Schottky diode can be added

between the EXTV and INTV pins. Make sure that in

CC

A leaky diode D in the boost converter can not only

B

all cases EXTV ≤ VBIAS.

CC

prevent the top MOSFET from fully turning on but it can

The following list summarizes possible connections for

EXTV :

also completely discharge the bootstrap capacitor C and

B

CC

create a current path from the input voltage to the BOOST

pin to INTV . This can cause INTV to rise if the diode

CC

EXTV Left Open (or Grounded). This will cause

CC

leakage exceeds the current consumption on INTV .

CC

INTV to be powered from the internal 5.4V regulator

CC

This is particularly a concern in Burst Mode operation

resulting in an efficiency penalty at high input voltages.

where the load on INTV can be very small. The external

CC

EXTV Connected to an External Supply. If an external

CC

Schottky or silicon diode should be carefully chosen such

supply is available in the 5.4V to 6V range, it may be

that INTV never gets charged up much higher than its

CC

used to power EXTV providing it is compatible with

CC

normal regulation voltage.

the MOSFET gate drive requirements. Ensure that

EXTV < VBIAS.

CC

37881fc

19

LTC3788-1

APPLICATIONS INFORMATION

Fault Conditions: Overtemperature Protection

Typically, the external clock (on PLLIN/MODE pin) input

highthresholdis1.6V,whiletheinputlowthresholdis1.2V.

At higher temperatures, or in cases where the internal

power dissipation causes excessive self-heating on chip

Note that the LTC3788-1 can only be synchronized to an

external clock whose frequency is within range of the

LTC3788-1’s internal VCO, which is nominally 55kHz to

1MHz.Thisisguaranteedtobebetween75kHzand850kHz.

(such as an INTV short to ground), the overtemperature

CC

shutdown circuitry will shut down the LTC3788-1. When

the junction temperature exceeds approximately 170°C,

the overtemperature circuitry disables the INTV LDO,

CC

RapidphaselockingcanbeachievedbyusingtheFREQpin

to set a free-running frequency near the desired synchro-

nization frequency. The VCO’s input voltage is prebiased

at a frequency corresponding to the frequency set by the

FREQ pin. Once prebiased, the PLL only needs to adjust

the frequency slightly to achieve phase lock and synchro-

nization. Although it is not required that the free-running

frequency be near external clock frequency, doing so will

prevent the operating frequency from passing through a

large range of frequencies as the PLL locks.

causing the INTV supply to collapse and effectively shut

CC

down the entire LTC3788-1 chip. Once the junction tem-

perature drops back to approximately 155°C, the INTV

CC

LDO turns back on. Long term overstress (T > 125°C)

J

should be avoided as it can degrade the performance or

shorten the life of the part.

Phase-Locked Loop and Frequency Synchronization

The LTC3788-1 has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a low pass filter

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the top MOSFET of controller 1 to be locked to

the rising edge of an external clock signal applied to the

PLLIN/MODEpin.Theturn-onofcontroller2’stopMOSFET

is thus 180 degrees out-of-phase with the external clock.

The phase detector is an edge-sensitive digital type that

provides zero degrees phase shift between the external

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

Table 1 summarizes the different states in which the FREQ

pin can be used.

Table ±.

FREQ PIN

PLLIN/MODE PIN

DC Voltage

FREQUENCY

350kHz

0V

INTV

DC Voltage

535kHz

CC

Resistor

DC Voltage

50kHz to 900kHz

Any of the Above

External Clock

Phase Locked to

External Clock

If the external clock frequency is greater than the internal

1000

900

800

700

600

500

400

300

200

100

0

oscillator’sfrequency,f ,thencurrentissourcedcontinu-

OSC

ously from the phase detector output, pulling up the VCO

input. When the external clock frequency is less than f

,

OSC

current is sunk continuously, pulling down the VCO input.

If the external and internal frequencies are the same but

exhibit a phase difference, the current sources turn on for

an amount of time corresponding to the phase difference.

The voltage at the VCO input is adjusted until the phase

and frequency of the internal and external oscillators are

identical. At the stable operating point, the phase detector

output is high impedance and the internal filter capacitor,

15 25 35 45 55 65 75 85 95 105 115 125

FREQ PIN RESISTOR (kΩ)

37881 F06

C , holds the voltage at the VCO input.

LP

Figure 6. Relationship Between Oscillator

Frequency and Resistor Value at the FREQ Pin

37881fc

20

LTC3788-1

APPLICATIONS INFORMATION

Minimum On-Time Considerations

circuit current. In continuous mode, I

= f(Q +

GATECHG T

Q ),whereQ andQ arethegatechargesofthetopside

B

T

B

Minimum on-time, t , is the smallest time duration

ON(MIN)

and bottom side MOSFETs.

that the LTC3788-1 is capable of turning on the bottom

MOSFET. It is determined by internal timing delays and

the gate charge required to turn on the top MOSFET. Low

duty cycle applications may approach this minimum on-

time limit.

2

3. DC I R losses. These arise from the resistances of the

MOSFETs,sensingresistor,inductorandPCboardtraces

andcausetheefficiencytodropathighoutputcurrents.

4. Transition losses apply only to the bottom MOSFET(s),

andbecomesignificantonlywhenoperatingatlowinput

voltages(typically15Vorgreater).Transitionlossescan

be estimated from:

In forced continuous mode, if the duty cycle falls below

what can be accommodated by the minimum on-time,

the controller will begin to skip cycles but the output will

continuetoberegulated.Morecycleswillbeskippedwhen

3

V_OUT

Transition Loss = (1.7)

I_O(MAX)• C_RSSf

V increases. Once V rises above V , the loop works

IN

OUT

V

IN

to keep the top MOSFET on continuously. The minimum

Other hidden losses, such as copper trace and internal

battery resistances, can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these system-level losses during the

design phase.

on-time for the LTC3788-1 is approximately 110ns.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the greatest improvement. Percent efficiency

can be expressed as:

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

%Efficiency = 100% – (L1 + L2 + L3 + ...)

load current. When a load step occurs, V

shifts by an

OUT

amount equal to ΔI

(ESR), where ESR is the effective

OUT

generating the feedback error signal

where L1, L2, etc., are the individual losses as a percent-

age of input power.

LOAD

series resistance of C . ΔI

also begins to charge

LOAD

or discharge C

OUT

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of

thatforcestheregulatortoadapttothecurrentchangeand

return V to its steady-state value. During this recov-

OUT

the losses in LTC3788-1 circuits: 1) IC V current, 2) IN-

IN

ery time V

can be monitored for excessive overshoot

OUT

2

TV regulator current, 3) I R losses, 4) Bottom MOSFET

CC

or ringing, which would indicate a stability problem.

OPTI-LOOP compensation allows the transient response

to be optimized over a wide range of output capacitance

and ESR values. The availability of the ITH pin not only

allows optimization of control loop behavior, but it also

providesaDCcoupledandACfilteredclosedloopresponse

test point. The DC step, rise time and settling at this test

point truly reflects the closed loop response. Assuming a

predominantly second order system, phase margin and/

or damping factor can be estimated using the percentage

of overshoot seen at this pin. The bandwidth can also be

transition losses.

1. The V current is the DC supply current given in the

IN

ElectricalCharacteristicstable,whichexcludesMOSFET

driver and control currents. V current typically results

IN

in a small (<0.1%) loss.

2. INTV current is the sum of the MOSFET driver and

CC

control currents. The MOSFET driver current results

from switching the gate capacitance of the power MOS-

FETs. Each time a MOSFET gate is switched from low to

high to low again, a packet of charge, dQ, moves from

estimated by examining the rise time at the pin. The I

TH

INTV to ground. The resulting dQ/dt is a current out

CC

externalcomponentsshowninFigure9circuitwillprovide

of INTV that is typically much larger than the control

CC

an adequate starting point for most applications.

37881fc

21

LTC3788-1

APPLICATIONS INFORMATION

The I series RC-CC filter sets the dominant pole-zero

Design Example

TH

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the final PC layout is complete

and the particular output capacitor type and value have

been determined. The output capacitors must be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1μs to 10μs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop.

As a design example for one channel, assume V

=

IN

12V(nominal), V = 22V (max), V

= 24V, I

IN

OUT

OUT(MAX)

4A, V

= 75mV, and f = 350kHz.

SENSE(MAX)

Theinductancevalueischosenfirstbasedona30%ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage. Tie the PLLLPF

pin to GND, generating 350kHz operation. The minimum

inductance for 30% ripple current is:

⎛

⎞

V

f •L

V

IN

V_OUT

IN

ΔI_L=

1−

⎜

⎟

⎝

⎠

Placing a power MOSFET and load resistor directly across

the output capacitor and driving the gate with an ap-

propriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

is why it is better to look at the ITH pin signal which is

in the feedback loop and is the filtered and compensated

control loop response.

A 6.8μH inductor will produce a 30% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 9.25A.

The R

resistor value can be calculated by using the

SENSE

maximum current sense voltage specification with some

accommodation for tolerances:

75mV

9.25A

R_SENSE

≤

= 0.008Ω

The gain of the loop will be increased by increasing R

Choosing 1% resistors: R = 5k and R = 95.3k yields an

C

A

B

output voltage of 24.072V.

and the bandwidth of the loop will be increased by de-

creasing C . If R is increased by the same factor that C

C

The power dissipation on the top side MOSFET can

be easily estimated. Choosing a Vishay Si7848BDP

is decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loopsystemandwilldemonstratetheactualoverall

supply performance.

MOSFET results in: R

= 0.012Ω, C

= 150pF.

DS(ON)

MILLER

At maximum input voltage with T(estimated) = 50°C:

(24V −12V)24V

P_MAIN

=

•(4A)²

(12V)²

• 1+(0.005)(50°C− 25°C) • 0.008Ω

[

]

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

4A

12V

+ (1.7)(24V)³

(150pF)(350kHz) = 0.7W

with C , causing a rapid drop in V . No regulator can

OUT

C

OUT

is chosen to filter the square current in the output.

The maximum output current peak is:

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

31%

2

⎛

⎞

I_OUT(PEAK)= 4 • 1+

= 4.62A

⎜

⎟

⎠

⎝

C

to C

is greater than 1:50, the switch rise time

LOAD

OUT

should be controlled so that the load rise time is limited to

A low ESR (5mꢁ) capacitor is suggested. This capacitor

will limit output voltage ripple to 23.1mV (assuming ESR

dominate ripple).

approximately 25 • C . Thus, a 10μF capacitor would

LOAD

require a 250μs rise time, limiting the charging current

to about 200mA.

37881fc

22

LTC3788-1

APPLICATIONS INFORMATION

PC Board Layout Checklist

back pins. All of these nodes have very large and fast

moving signals and, therefore, should be kept on the

output side of the LTC3788-1 and occupy a minimal

PC trace area.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 7. Figure 8 illustrates the current

waveforms present in the various branches of the 2-phase

synchronousregulatorsoperatinginthecontinuousmode.

Check the following in your layout:

7. Use a modified “star ground” technique: a low imped-

ance, large copper area central grounding point on

the same side of the PC board as the input and output

capacitors with tie-ins for the bottom of the INTV

CC

decouplingcapacitor,thebottomofthevoltagefeedback

1.PutthebottomN-channelMOSFETsMBOT1andMBOT2

and the top N-channel MOSFETs MTOP1 and MTOP2

resistive divider and the SGND pin of the IC.

in one compact area with C

.

OUT

PC Board Layout Debugging

2. Are the signal and power grounds kept separate? The

combinedICsignalgroundpinandthegroundreturnof

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

to the internal oscillator and probe the actual output volt-

age. Check for proper performance over the operating

voltage and current range expected in the application.

The frequency of operation should be maintained over the

input voltage range down to dropout and until the output

load drops below the low current operation threshold—

typically 10% of the maximum designed current level in

Burst Mode operation.

C

mustreturntothecombinedC (–)terminals.

INTVCC

OUT

The path formed by the bottom N-channel MOSFET and

the C capacitor should have short leads and PC trace

IN

lengths. The output capacitor (–) terminals should be

connected as close as possible to the (–) terminals of

the input capacitor by placing the capacitors next to

each other.

3. Do the LTC3788-1 VFB pins’ resistive dividers connect

to the (+) terminals of C ? The resistive divider must

OUT

be connected between the (+) terminal of C

and

OUT

signal ground and placed close to the VFB pin. The

feedback resistor connections should not be along the

high current input feeds from the input capacitor(s).

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawelldesigned, lownoisePCBimplementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required. Only after each

controllerischeckedforitsindividualperformanceshould

both controllers be turned on at the same time. A particu-

larly difficult region of operation is when one controller

channel is nearing its current comparator trip point while

the other channel is turning on its bottom MOSFET. This

occurs around the 50% duty cycle on either channel due

to the phasing of the internal clocks and may cause minor

duty cycle jitter.

–

+

4. Are the SENSE and SENSE leads routed together with

minimumPCtracespacing?Thefiltercapacitorbetween

+

–

SENSE and SENSE should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connections at the sense resistor.

5. Is the INTV decoupling capacitor connected close

CC

to the IC, between the INTV and the power ground

CC

pins? This capacitor carries the MOSFET drivers’ cur-

rent peaks. An additional 1μF ceramic capacitor placed

immediatelynexttotheINTV andPGNDpinscanhelp

CC

improve noise performance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2) and boost nodes (BOOST1, BOOST2) away

from sensitive small-signal nodes, especially from the

opposites channel’s voltage and current sensing feed-

Reduce V from its nominal level to verify operation with

IN

high duty cycle. Check the operation of the undervoltage

lockout circuit by further lowering V while monitoring

IN

the outputs to verify operation.

37881fc

23

LTC3788-1

APPLICATIONS INFORMATION

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

SGND pin of the IC.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator results

when the current sensing leads are hooked up backwards.

The output voltage under this improper hook-up will still

bemaintained,buttheadvantagesofcurrentmodecontrol

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

for inductive coupling between C , Schottky and the top

IN

MOSFET components to the sensitive current and voltage

–

SENSE1

SS1

+

V

PGOOD1

SW1

PULL-UP

R

L1

SENSE1

TG1

LTC3788-1

C

B1

BOOST1

BG1

V

OUT1

M1

+

ITH1

VFB1

M2

VBIAS

PGND

GND

IN

EXTV

CC

INTV

CC

FREQ

PLLIN/MODE

SGND

f

IN

RUN1

RUN2

BG2

M3

+

C

B2

M4

VFB2

ITH2

V

OUT2

BOOST2

R

L2

SENSE2

TG2

SW2

SS2

SENSE2

+

–

37881 F07

Figure 7. Recommended Printed Circuit Layout Diagram

37881fc

24

LTC3788-1

APPLICATIONS INFORMATION

L1

R

SENSE1

V

OUT1

C

OUT1

R

L1

SW1

V

IN

R

IN

C

IN

L2

R

SENSE2

V

OUT2

C

OUT2

R

L2

SW2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

37881 F08

Figure 8. Branch Current Waveforms

37881fc

25

LTC3788-1

APPLICATIONS INFORMATION

–

+

R

B1

PGOOD2

PGOOD1

TG1

+

SENSE1

100k

C

OUTA1

C

232k

OUTB1

INTV

R

CC

22μF

A1

220μF

12.1k

s4

L1

3.3μH

R

MTOP1

MBOT1

SENSE1

4mꢁ

VFB1

LTC3788-1

C

SW1

ITH1

C

B1

220pF

0.1μF

BOOST1

BG1

C

ITH1

R

8.66k

ITH1

15nF

ITH1

SS1

C

SS1

VBIAS

V

0.1μF

IN

V

OUT

5V TO 24V

INTV

CC

C

24V, 10A*

INT

+

4.7μF

C

INB

220μF

INA

SS2

ITH2

VFB2

PGND

BG2

22μF

s4

MBOT2

MTOP2

C

B1

0.1μF

L2

3.3μH

R

BOOST2

SW2

SENSE2

4mꢁ

PLLIN/MODE

SGND

EXTV

RUN1

RUN2

FREQ

CC

TG2

+

C

OUTA2

C

OUTB2

+

–

22μF

SENSE2

220μF

s4

37881 F09

CINA, COUTA1, COUTA2: SANYO, 50CE220AX

CINB, COUTB1, COUTB2: TDK C4532X5R1E226M

L1, L2: PULSE PA1494.362NL

MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H

*WHEN V < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.

IN

Figure 9. High Efficiency 2-Phase 24V Boost Converter

37881fc

26

LTC3788-1

APPLICATIONS INFORMATION

R

S1

, 53.6k, 1%

R

S2

26.1k, 1%

–

SENSE1

V

R

232k

1%

OUT1

B1

C1

0.1μF

24V, 4A

100k

+

PGOOD1

INTV

C

OUTB1

220μF

CC

OUTA1

C3

0.1μF

6.8μF

R

A1

LTC3788-1

× 4

D3

12.1k, 1%

L1

10.2μH

MTOP1

MBOT1

VFB1

ITH1

TG1

C

ITH1

, 220pF

SW1

BOOST1

R

ITH1

C

, 15nF

ITH1

C

B1

, 0.1μF

8.87k, 1%

BG1

C

SS1

, 0.01μF

D1

V

IN

VBIAS

SS1

5V TO 24V

C

INB

+

INTV

CC

C

INA

PLLIN/MODE

SGND

INTV

C

CC

INT

22μF

220μF

4.7μF

× 4

PGND

EXTV

CC

D2

, 0.1μF

MBOT2B

RUN1

RUN2

FREQ

MBOT2A

BG2

C

B1

R

FREQ

BOOST2

41.2k

L2

16μH

C

SS2

, 0.01μF

SW2

TG2

SS2

R

C

, 4.7nF

ITH2

D4

23.7k, 1%

MTOP2

ITH2

C

ITH2A

, 220pF

V

OUT2

R

A2

48V, 2A

C

OUTB2

12.1k, 1%

+

C

VFB2

OUTA2

22μF

220μF

R

475k

1%

B2

C4

× 4

0.1μF

+

–

SENSE2

C2

0.1μF

R

S4

30.1k, 1%

SENSE2

R

S3

42.2k, 1%

37881 F10

C

: C4532x7R1H685K

: SANYO 63CE220KX

MBOT1, MTOP1: RENESAS RJK0305

OUTA2

OUTB2

MBOT2A, MBOT2B, MTOP2: RENESAS RJK0652

D3: DIODES INC B340B

, C

: TDK C4532X5R1E226M

: SANYO 50CE220AX

INA OUTA1

INB OUTB1

, C

D4: DIODES INC B360A

L1: PULSE PA2050.103NL

L2: PULSE PA2050.163NL

Figure ±0. High Efficiency Dual 24V/48V Boost Converter with Inductor DCR Current Sensing

37881fc

27

LTC3788-1

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN Package

28-Lead Plastic SSOP (Narrow .±50 Inch)

(Reference LTC DWG # 05-08-1641)

.386 – .393*

(9.804 – 9.982)

.045 .005

.150 – .165

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 .004

.0532 – .0688

(1.35 – 1.75)

× 45°

.004 – .0098

(0.102 – 0.249)

(0.38 0.10)

.0075 – .0098

(0.19 – 0.25)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

37881fc

28

LTC3788-1

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

3/10

Updates to Typical Application

Updates in the Electrical Characteristics Section

Updates to PLLIN/MODE in Pin Functions

Updates to Application Information

New Figure 9 Added

1

3, 4

9

15, 19, 22

26

30

19

30

27

Updated Note on Typical Application

Updated Related Parts Table

B

C

9/11

1/12

Updated the Topside MOSFET Driver Supply (C , D ) section.

B B

Updated the Related Parts.

Revised Figure 10

37881fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

29

LTC3788-1

TYPICAL APPLICATION

High Efficiency Dual ±2V/24V Boost Converter

R

232k

1%

B1

–

SENSE1

V

*

OUT1

24V, 5A

C

OUTB1

100k

+

R

A1

SENSE1

VFB1

PGOOD1

TG1

INTV

C

CC

OUTA1

12.1k, 1%

L1

3.3μH

22μF

220μF

R

SENSE1

4mΩ

MTOP1

MBOT1

s 4

C

, 220pF

ITH1

SW1

BOOST1

R

ITH1

C

, 15nF

ITH1

8.66k

LTC3788-1

C

B1

, 0.1μF

BG1

ITH1

SS1

D1

C

, 0.1μF

SS1

V

IN

VBIAS

5V TO 24V

C

INB

INTV

CC

C

INA

C

INT

22μF

220μF

4.7μF

s 4

PGND

PLLIN/MODE

SGND

D2

, 0.1μF

MBOT2

MTOP2

EXTV

BG2

CC

C

B1

RUN1

RUN2

FREQ

BOOST2

L2

1.25μH

R

SENSE2

3mΩ

C

, 0.1μF

SS2

SW2

TG2

SS2

C

, 15nF

R

ITH2

2.7k

ITH2

C

ITHA2

, 100pF

V

*

OUT2

R

A2

12V, 10A

C

OUTB2

12.1k

+

C

VFB2

SENSE2

OUTA2

+

–

22μF

220μF

R

s 4

B2

110k

37881 TA02

C

, C

: SANYO, 50CE220AX

INA OUTA1 OUTA2

, C

: TDK C4532X5R1E226M

INB OUTB1 OUTB2

L1: PULSE PA1494.362NL

L2: PULSE PA1294.132NL

MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H

* WHEN V < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED

IN

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V

LTC3787/LTC3787-1 Multiphase, Dual Channel Synchronous

Step-Up Controller

Up to 60V, 50kHz to 900kHz

OUT

IN

Fixed Operating Frequency, 4mm × 5mm QFN-28, SSOP-28

LTC3786

Low I Synchronous Step-Up Controller

Q

4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V Up to 60V, 50kHz to 900kHz

IN

OUT

Fixed Operating Frequency, 3mm × 3mm QFN-32, MSOP-16E

LTC3862/LTC3862-1 Multiphase, Dual Channel Single Output

Current Mode Step-Up DC/DC Controller

4V ≤ V ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz Fixed Operating Frequency,

IN

SSOP-24, TSSOP-24, 5mm × 5mm QFN-24

LTC3859A

Low I , Triple Output Buck/Buck/Boost

All Outputs Remain in Regulation Through Cold Crank, 4.5V (Down to 2.5V After

Q

Synchronous DC/DC Controller

Start-Up) ≤ V ≤ 38V, V

Up to 24V, V

Up to 60V, I = 55μA

IN

OUT(BUCK)

OUT(BOOST) Q

LTC3789

High Efficiency Synchronous 4-Switch

Buck-Boost DC/DC Controller

4V ≤ V ≤ 38V, 0.8V ≤ V

≤ 38V, SSOP-28, 4mm × 5mm QFN-28, SSOP-28

IN

OUT

37881fc

LT 0112 REV C • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

30

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3788IGN-1#TRPBF
厂家：	Linear
描述：	LTC3788-1 - 2-Phase, Dual Output Synchronous Boost Controller; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C 开关光电二极管输出元件
文件：	总30页 (文件大小：390K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3788IGN-1#TRPBF [Linear]

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