LTC3809EMSE-TR [Linear]
No RSENSE™, Low EMI, Synchronous DC/DC Controller; 无检测电阻器™ ，低EMI ，同步DC / DC控制器
| 型号： | LTC3809EMSE-TR |
| 厂家： | 
Linear |
| 描述： | No RSENSE™, Low EMI, Synchronous DC/DC Controller |
| 文件： | 总24页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3809
No RSENSE™, Low EMI,
Synchronous DC/DC Controller
FEATURES
DESCRIPTION
TheLTC®3809isasynchronousstep-downswitchingregu-
latorcontrollerthatdrivesexternalcomplementarypower
MOSFETs using few external components. The constant
n
No Current Sense Resistor Required
n
Selectable Spread Spectrum Frequency Modulation
for Low Noise Operation
n
Constant Frequency Current Mode Operation for
frequency current mode architecture with MOSFET V
DS
Excellent Line and Load Transient Response
sensing eliminates the need for a current sense resistor
n
True PLL for Frequency Locking or Adjustment
and improves efficiency.
(Frequency Range: 250kHz to 750kHz)
Fornoisesensitiveapplications,theLTC3809canbeexter-
nallysynchronizedfrom250kHzto750kHz. BurstModeis
inhibitedduringsynchronizationorwhentheSYNC/MODE
pin is pulled low to reduce noise and RF interference. To
further reduce EMI, the LTC3809 incorporates a novel
spread spectrum frequency modulation technique.
n
Wide V Range: 2.75V to 9.8V
IN
OUT
n
n
n
n
Wide V
Range: 0.6V to V
IN
0.6V 1.5% Reference
Low Dropout Operation: 100% Duty Cycle
Selectable Burst Mode®/Pulse-Skipping/Forced
Continuous Operation
n
n
n
n
n
Burst Mode operation provides high efficiency operation
at light loads. 100% duty cycle provides low dropout
operation, extending operating time in battery-powered
systems.
Auxiliary Winding Regulation
Internal Soft-Start Circuitry
Output Overvoltage Protection
Micropower Shutdown: I = 9μA
Q
Tiny Thermally Enhanced Leadless (3mm × 3mm)
Theswitchingfrequencycanbeprogrammedupto750kHz,
allowing the use of small surface mount inductors and
capacitors.
DFN and 10-lead MSOP Packages
APPLICATIONS
The LTC3809 is available in tiny footprint thermally
enhanced DFN and 10-lead MSOP packages.
n
1- or 2-Cell Lithium-Ion Powered Devices
Portable Instruments
L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation.
n
No R
is a trademark of Linear Technology Corporation.
SENSE
n
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5481178, 5929620, 6580258, 6304066, 5847554,
6611131, 6498466. Other Patents pending.
Distributed DC Power Systems
TYPICAL APPLICATION
Efficiency and Power Loss vs Load Current
100
90
80
70
60
50
10k
EFFICIENCY
High Efficiency, 550kHz Step-Down Converter
V
IN
= 3.3V
1k
V
IN
2.75V TO 9.8V
V
IN
= 4.2V
V
IN
= 5V
10μF
LTC3809
100
10
V
IN
PLLLPF
POWER LOSS
= 4.2V
SYNC/MODE TG
V
IN
59k
2.2μH
47μF
V
2.5V
2A
OUT
V
SW
FB
15k
1
I
TH
BG
187k
FIGURE 10 CIRCUIT
RUN
IPRG
470pF
V
OUT
= 2.5V
GND
0.1
10000
1
10
100
1000
LOAD CURRENT (mA)
3809 TA01b
3809 TA01
3809fc
1
LTC3809
ABSOLUTE MAXIMUM RATINGS (Note 1)
Operating Temperature Range (Note 2)....–40°C to 85°C
Storage Temperature Range...................–65°C to 125°C
Junction Temperature (Note 3) ............................ 125°C
Lead Temperature (Soldering, 10 sec)
Input Supply Voltage (V )........................ –0.3V to 10V
IN
PLLLPF, RUN, SYNC/MODE,
IPRG Voltages............................... –0.3V to (V + 0.3V)
IN
V , I Voltages...................................... –0.3V to 2.4V
FB TH
MSOP Package ................................................. 300°C
SW Voltage ......................... –2V to V + 1V (10V Max)
IN
TG, BG Peak Output Current (<10μs)......................... 1A
PIN CONFIGURATION
TOP VIEW
TOP VIEW
PLLLPF
1
2
3
4
5
10 SW
PLLLPF
1
2
3
4
5
10 SW
SYNC/MODE
9
8
7
6
V
IN
SYNC/MODE
9
8
7
6
V
IN
V
TH
RUN
TG
11
11
V
FB
TG
FB
I
BG
IPRG
I
TH
BG
RUN
IPRG
MSE PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
T
= 125°C, θ = 40°C/W
JA
EXPOSED PAD (PIN 11) IS GND
(MUST BE SOLDERED TO PCB)
JMAX
10-LEAD (3mm s 3mm) PLASTIC DFN
T
= 125°C, θ = 43°C/W
JA
EXPOSED PAD (PIN 11) IS GND
(MUST BE SOLDERED TO PCB)
JMAX
ORDER INFORMATION
LEAD FREE FINISH
LTC3809EDD#PBF
LTC3809EMSE#PBF
LEAD BASED FINISH
LTC3809EDD
TAPE AND REEL
PART MARKING
LBQY
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC3809EDD#TRPBF
LTC3809EMSE#TRPBF
TAPE AND REEL
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LTBQT
–40°C to 85°C
PART MARKING
LBQY
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC3809EDD#TR
LTC3809EMSE#TR
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LTC3809EMSE
LTBQT
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3809fc
2
LTC3809
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
Input DC Supply Current
Normal Operation
Sleep Mode
(Note 4)
350
105
9
500
150
20
μA
μA
μA
μA
Shutdown
RUN = 0V
UVLO
V
IN
= UVLO Threshold – 200mV
3
10
l
l
Undervoltage Lockout Threshold (UVLO)
V
IN
V
IN
Falling
Rising
1.95
2.15
2.25
2.45
2.55
2.75
V
V
Shutdown Threshold of RUN Pin
Regulated Feedback Voltage
0.8
1.1
0.6
1.4
0.609
0.04
V
V
l
(Note 5)
2.75V < V < 9.8V (Note 5)
0.591
Output Voltage Line Regulation
Output Voltage Load Regulation
0.01
%/V
IN
I
TH
I
TH
= 0.9V (Note 5)
= 1.7V
0.1
–0.1
0.5
–0.5
%
%
V
Input Current
(Note 5)
9
0.68
20
50
nA
V
FB
Overvoltage Protect Threshold
Overvoltage Protect Hysteresis
Auxiliary Feedback Threshold
Top Gate (TG) Drive Rise Time
Top Gate (TG) Drive Fall Time
Bottom Gate (BG) Drive Rise Time
Bottom Gate (BG) Drive Fall Time
Maximum Current Sense Voltage (ΔV
Measured at V
0.66
0.7
FB
mV
V
0.325
0.4
40
0.475
C = 3000pF
L
ns
ns
ns
ns
C = 3000pF
L
40
C = 3000pF
L
50
C = 3000pF
L
40
l
l
l
IPRG = Floating (Note 6)
IPRG = 0V (Note 6)
IPRG = V (Note 6)
110
70
185
125
85
204
140
100
223
mV
mV
mV
)
SENSE(MAX)
(V – SW)
IN
IN
Soft-Start Time (Internal)
Oscillator and Phase-Locked Loop
Oscillator Frequency
Time for V to Ramp from 0.05V to 0.55V
0.5
0.74
0.9
ms
FB
Unsynchronized (SYNC/MODE Not Clocked)
PLLLPF = Floating
480
260
650
550
300
750
600
340
825
kHz
kHz
kHz
PLLLPF = 0V
PLLLPF = V
IN
Phase-Locked Loop Lock Range
SYNC/MODE Clocked
Minimum Synchronizable Frequency
Maximum Synchronizible Frequency
200
1000
250
kHz
kHz
750
Phase Detector Output Current
Sinking
f
f
> f
< f
–3
3
μA
μA
OSC
OSC
SYNC/MODE
SYNC/MODE
Sourcing
Spread Spectrum Frequency Range
Minimum Switching Frequency
Maximum Switching Frequency
460
635
kHz
kHz
SYNC/MODE Pull-Down Current
SYNC/MODE = 2.2V
2.6
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: T is calculated from the ambient temperature T and power
J A
dissipation P according to the following formula:
D
T = T + (P • θ °C/W)
J
A
D
JA
Note 4: Dynamic supply current is higher due to gate charge being
Note 2: The LTC3809E is guaranteed to meet specified performance from
0°C to 85°C. Specifications over the –40°C to 85°C operating range are
assured by design characterization, and correlation with statistical process
controls.
delivered at the switching frequency.
Note 5: The LTC3809 is tested in a feedback loop that servos I to a
specified voltage and measures the resultant V voltage.
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
TH
FB
a percentage of value as shown in Figure 1.
3809fc
3
LTC3809
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
Maximum Current Sense Voltage
vs ITH Pin Voltage
Efficiency vs Load Current
Efficiency vs Load Current
100
80
60
40
20
0
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
55
50
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
Burst Mode OPERATION
V
OUT
= 2.5V
V
IN
= 5V, V
= 2.5V
(I RISING)
OUT
TH
Burst Mode OPERATION
V
OUT
= 3.3V
(I FALLING)
TH
FORCED CONTINUOUS
MODE
BURST MODE
(SYNC/MODE =
PULSE SKIPPING
MODE
V
OUT
= 1.2V
V
IN
)
FORCED
CONTINUOUS
(SYNC/MODE = 0V)
V
OUT
= 1.8V
PULSE SKIPPING
(SYNC/MODE = 0.6V)
SYNC/MODE = V
IN
V
IN
= 5V
–20
0.5
1
I
1.5
VOLTAGE (V)
2
1
10
100
1k
10k
1
10
100
1k
10k
LOAD CURRENT (mA)
LOAD CURRENT (mA)
TH
3809 G01
3809 G02
3809 G03
Load Step
(Burst Mode Operation)
Load Step
(Forced Continuous Mode)
V
V
OUT
OUT
200mV/DIV
200mV/DIV
AC COUPLED
AC COUPLED
I
I
L
L
2A/DIV
2A/DIV
3809 G05
3809 G04
100μs/DIV
100μs/DIV
V
V
I
= 3.3V
V
V
I
= 3.3V
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 300mA TO 3A
= 300mA TO 3A
LOAD
SYNC/MODE = 0V
LOAD
SYNC/MODE = V
IN
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
Load Step (Pulse-Skipping Mode)
Start-Up with Internal Soft-Start
V
OUT
200mV/DIV
V
OUT
AC COUPLED
1.8V
500mV/DIV
I
L
2A/DIV
3809 G07
3809 G06
200μs/DIV
100μs/DIV
V
= 4.2V
LOAD
V
V
LOAD
= 3.3V
OUT
IN
IN
R
= 1Ω
= 1.8V
FIGURE 10 CIRCUIT
I
= 300mA TO 3A
SYNC/MODE = V
FB
FIGURE 10 CIRCUIT
3809fc
4
LTC3809
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
Regulated Feedback Voltage
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
1.20
1.15
1.10
1.05
1.00
0.606
0.604
0.602
0.600
0.598
0.596
0.594
V
IN
RISING
V
IN
FALLING
40 60
–60 –40 –20
TEMPERATURE (°C)
0
20
80 100
40 60
TEMPERATURE (°C)
40 60
–60 –40 –20
TEMPERATURE (°C)
–60 –40 –20
0
20
80 100
0
20
80 100
3809 G08
3809 G09
3809 G10
Maximum Current Sense
Threshold vs Temperature
SYNC/MODE Pull-Down Current
vs Temperature
Oscillator Frequency
vs Temperature
2.80
2.75
2.70
2.65
2.60
2.55
2.50
2.45
2.40
10
8
135
130
125
120
115
IPRG = FLOAT
6
4
2
0
–2
–4
–6
–8
–10
40 60
TEMPERATURE (°C)
40 60
–60 –40 –20
TEMPERATURE (°C)
40 60
–60 –40 –20
TEMPERATURE (°C)
–60 –40 –20
0
20
80 100
0
20
80 100
0
20
80 100
3809 G11
3809 G12
3809 G13
Oscillator Frequency
vs Input Voltage
Shutdown Quiescent Current
vs Input Voltage
Sleep Current vs Input Voltage
5
4
18
16
14
12
10
8
130
120
110
100
90
3
2
1
0
–1
–2
–3
–4
–5
6
4
80
2
0
70
7
8
7
8
7
8
2
3
4
5
6
9
10
2
3
4
5
6
9
10
2
3
4
5
6
9
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3809 G14
3809 G15
3809 G16
3809fc
5
LTC3809
PIN FUNCTIONS
PLLLPF(Pin1):FrequencySet/PLLLowpassFilter. When
synchronizing to an external clock, this pin serves as the
lowpass filter point for the phase-locked loop. Normally,
a series RC is connected between this pin and ground.
RUN (Pin 5): Run Control Input. Forcing this pin below
1.1V shuts down the chip. Driving this pin to V or releas-
IN
ing this pin enables the chip to start-up with the internal
soft-start.
When not synchronizing to an ex ternal clock, this pin ser ves
asthefrequencyselectinput. TyingthispintoGNDselects
IPRG (Pin 6): Three-State Pin to Select Maximum Peak
Sense Voltage Threshold. This pin selects the maximum
300kHz operation; tying this pin to V selects 750kHz
allowed voltage drop between the V and SW pins (i.e.,
IN
IN
operation. Floating this pin selects 550kHz operation.
the maximum allowed drop across the external P-channel
MOSFET). Tie to V , GND or float to select 204mV, 85mV
IN
Connect a 2.2nF capacitor between this pin and GND, and
a 1000pF capacitor between this pin and the SYNC/MODE
when using spread spectrum modulation operation.
or 125mV respectively.
BG (Pin 7): Bottom (NMOS) Gate Drive Output. This pin
drives the gate of the external N-channel MOSFET. This
SYNC/MODE (Pin 2): This pin performs four functions:
1) auxiliary winding feedback input, 2) external clock
synchronization input for phase-locked loop, 3) Burst
Mode, pulse-skipping or forced continuous mode select,
and 4) enable spread spectrum modulation operation in
pulse-skipping mode. Applying a clock with frequency
between 250kHz to 750kHz causes the internal oscillator
to phase-lock to the external clock and disables Burst
Mode operation but allows pulse-skipping at low load
currents.
pin has an output swing from PGND to V .
IN
TG (Pin 8): Top (PMOS) Gate Drive Output. This pin drives
the gate of the external P-channel MOSFET. This pin has
an output swing from PGND to V .
IN
V
(Pin 9): Chip Signal Power Supply. This pin powers
IN
the entire chip, the gate drivers and serves as the positive
input to the differential current comparator.
SW (Pin 10): Switch Node Connection to Inductor. This
pin is also the negative input to the differential current
comparatorandaninputtothereversecurrentcomparator.
Normally this pin is connected to the drain of the external
P-channel MOSFET, the drain of the external N-channel
MOSFET and the inductor.
To select Burst Mode operation at light loads, tie this
pin to V . Grounding this pin selects forced continuous
IN
operation, which allows the inductor current to reverse.
TyingthispintoV selectspulse-skippingmode. Inthese
FB
cases, the frequency of the internal oscillator is set by the
GND (Pin 11): Exposed Pad. The Exposed Pad is ground
and must be soldered to the PCB ground for electrical
contact and optimum thermal performance.
voltage on the PLLLPF pin. Tying to a voltage between
1.35V to V – 0.5V enables spread spectrum modulation
IN
operation. In this case, an internal 2.6μA pull-down current
sourcehelpstosetthevoltageatthispinbytyingaresistor
with appropriate value between this pin and V . Do not
IN
leave this pin floating.
V
(Pin 3): Feedback Pin. This pin receives the remotely
FB
sensedfeedbackvoltageforthecontrollerfromanexternal
resistor divider across the output.
ITH (Pin 4): Current Threshold and Error Amplifier
Compensation Point. Nominal operating range on this pin
is from 0.7V to 2V. The voltage on this pin determines the
threshold of the main current comparator.
3809fc
6
LTC3809
FUNCTIONAL DIAGRAM
V
IN
C
IN
9
V
IN
6
IPRG
VOLTAGE
REFERENCE
V
REF
0.6V
SLOPE
+
TG
SW
BG
CLK
S
R
8
10
7
MP
+
–
Q
GND
ICMP
UNDERVOLTAGE
LOCKOUT
SWITCHING
LOGIC AND
BLANKING
CIRCUIT
SENSE
L
ANTI-SHOOT-
THROUGH
V
OUT
C
OUT
V
IN
PV
IN
V
IN
MN
UVSD
0.7μA
RUN
5
+
–
FCB
SLEEP
V
IN
+
–
0.15V
t = 1ms
OV
REV
INTERNAL
I
SOFT-START
SS
0.68V
0.54V
BURSTDIS
R
B
GND
11
2
0.3V
+
–
BURST DEFEAT
CLOCK DETECT
BURSTDIS
FCB
SYNC/MODE
UV
PHASE
V
FB
DETECTOR
0.4V
2.6μA
I
TH
4
3
+
–
R
C
V
REF
+
+
–
C
0.6V
SS
C
EAMP
V
FB
PLLLPF
1
R
A
V
CO
3809 FD
CLK
SW
+
–
I
RICMP
REV
GND
3809fc
7
LTC3809
OPERATION (Refer to Functional Diagram)
Main Control Loop
Light Load Operation (Burst Mode Operation,
Continuous Conduction or Pulse-Skipping Mode)
(SYNC/MODE Pin)
The LTC3809 uses a constant frequency, current mode
architecture. During normal operation, the top external
P-channel power MOSFET is turned on when the clock
sets the RS latch, and is turned off when the current
comparator (ICMP) resets the latch. The peak inductor
current at which ICMP resets the RS latch is determined
by the voltage on the I pin, which is driven by the output
of the error amplifier (EAMP). The V pin receives the
output voltage feedback signal from an external resistor
divider. This feedback signal is compared to the internal
0.6V reference voltage by the EAMP. When the load cur-
TheLTC3809canbeprogrammedforeitherhighefficiency
Burst Mode operation, forced continuous conduction
mode or pulse-skipping mode at low load currents. To
select Burst Mode operation, tie the SYNC/MODE pin
to V . To select forced continuous operation, tie the
TH
IN
SYNC/MODE pin to a DC voltage below 0.4V (e.g., GND).
FB
Tying the SYNC/MODE to a DC voltage above 0.4V and
below 1.2V (e.g., V ) enables pulse-skipping mode. The
FB
0.4V threshold between forced continuous operation and
pulse-skipping mode can be used in secondary winding
regulation as described in the Auxiliary Winding Control
Using SYNC/MODE Pin discussion in the Applications
Information section.
rent increases, it causes a slight decrease in V relative
to the 0.6V reference, which in turn causes the I voltage
FB
TH
to increase until the average inductor current matches the
new load current. While the top P-channel MOSFET is off,
the bottom N-channel MOSFET is turned on until either
the inductor current starts to reverse, as indicated by the
current reversal comparator IRCMP, or the beginning of
the next cycle.
When the LTC3809 is in Burst Mode operation, the peak
current in the inductor is set to approximately one-fourth
ofthemaximumsensevoltageeventhoughthevoltageon
the I pin indicates a lower value. If the average inductor
TH
current is higher than the load current, the EAMP will
Shutdown and Soft-Start (RUN Pin)
decrease the voltage on the I pin. When the I voltage
TH
TH
The LTC3809 is shut down by pulling the RUN pin low.
In shutdown, all controller functions are disabled and the
chip draws only 9μA. The TG output is held high (off) and
the BG output low (off) in shutdown. Releasing the RUN
pin allows an internal 0.7μA current source to pull up the
drops below 0.85V, the internal SLEEP signal goes high
and the external MOSFET is turned off.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3809 draws.
The load current is supplied by the output capacitor. As
the output voltage decreases, the EAMP increases the
RUN pin to V . The controller is enabled when the RUN
IN
pin reaches 1.1V.
I
voltage. When the I voltage reaches 0.925V, the
TH
TH
The start-up of V
is controlled by the LTC3809’s inter-
SLEEP signal goes low and the controller resumes normal
operation by turning on the external P-channel MOSFET
on the next cycle of the internal oscillator.
OUT
nal soft-start. During soft-start, the error amplifier EAMP
comparesthefeedbacksignalV to the internal soft-star t
FB
ramp (instead of the 0.6V reference), which rises linearly
from 0V to 0.6V in about 1ms. This allows the output
voltage to rise smoothly from 0V to its final value while
maintaining control of the inductor current.
When the controller is enabled for Burst Mode or pulse-
skipping operation, the inductor current is not allowed to
reverse. Hence, the controller operates discontinuously.
3809fc
8
LTC3809
OPERATION (Refer to Functional Diagram)
ThereversecurrentcomparatorRICMPsensesthedrain-to-
source voltage of the bottom external N-channel MOSFET.
This MOSFET is turned off just before the inductor current
reaches zero, preventing it from going negative.
Short-Circuit and Current Limit Protection
The LTC3809 monitors the voltage drop ΔV (between
SC
the GND and SW pins) across the external N-channel
MOSFET with the short-circuit current limit comparator.
The allowed voltage is determined by:
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions.Thepeakinductorcurrentisdeterminedbythe
ΔV
= A • 90mV
SC(MAX)
where A is a constant determined by the state of the IPRG
voltage on the I pin. The P-channel MOSFET is turned
TH
pin. Floating the IPRG pin selects A = 1; tying IPRG to V
on every cycle (constant frequency) regardless of the I
IN
TH
selects A = 5/3; tying IPRG to GND selects A = 2/3.
pin voltage. In this mode, the efficiency at light loads is
lower than in Burst Mode operation. However, continuous
mode has the advantages of lower output ripple and no
noise at audio frequencies.
The inductor current limit for short-circuit protection is
determined by ΔV
and the on-resistance of the
SC(MAX)
external N-channel MOSFET:
When the SYNC/MODE pin is clocked by an external
clock source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop), or is set to a DC
voltage between 0.4V and several hundred mV below
ΔVSC(MAX)
RDS(ON)
ISC
=
Once the inductor current exceeds I , the short current
SC
V , the LTC3809 operates in PWM pulse-skipping mode
IN
comparator will shut off the external P-channel MOSFET
at light loads. In this mode, the current comparator
ICMP may remain tripped for several cycles and force
the external P-channel MOSFET to stay off for the same
number of cycles. The inductor current is not allowed
to reverse (discontinuous operation). This mode, like
forced continuous operation, exhibits low output ripple
as well as low audio noise and reduced RF interference as
compared to Burst Mode operation. However, it provides
low current efficiency higher than forced continuous
mode, but not nearly as high as Burst Mode operation.
until the inductor current drops below I .
SC
Output Overvoltage Protection
As further protection, the overvoltage comparator (OVP)
guards against transient overshoots, as well as other more
seriousconditionsthatmayovervoltagetheoutput. When
the feedback voltage on the V pin has risen 13.33%
FB
above the reference voltage of 0.6V, the external P-chan-
nel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
During start-up or an undervoltage condition (V
≤
FB
0.54V), the LTC3809 operates in pulse-skipping mode
(no current reversal allowed), regardless of the state of
the SYNC/MODE pin.
3809fc
9
LTC3809
OPERATION (Refer to Functional Diagram)
Frequency Selection and Phase-Locked Loop
(PLLLPF and SYNC/MODE Pins)
frequency f
(= 550kHz) over a wider range (460kHz to
OSC
635kHz), reducing the peaks of the harmonic output on a
spectral analysis of the output noise. In this case, a 2.2nF
filter cap should be connected between the PLLLPF pin
and GND and another 1000pF cap should be connected
between PLLLPF and the SYNC/MODE pin. The controller
operatesinPWMpulse-skippingmodeatlightloadswhen
spreadspectrummodulationisselected.Seethediscussion
of Spread Spectrum Modulation with SYNC/MODE and
PLLLPF Pins in the Applications Information section.
Theselectionofswitchingfrequencyisatradeoffbetween
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3809’s controllers can
be selected using the PLLLPF pin. If the SYNC/MODE is
not being driven by an external clock source, the PLLLPF
can be floated, tied to V or tied to GND to select 550kHz,
Dropout Operation
IN
750kHz or 300kHz, respectively.
Whentheinputsupplyvoltage(V )approachestheoutput
IN
A phase-locked loop (PLL) is available on the LTC3809
to synchronize the internal oscillator to an external clock
source that connects to the SYNC/MODE pin. In this case,
a series RC should be connected between the PLLLPF pin
and GND to serve as the PLL’s loop filter. The LTC3809
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of the external P-channel MOSFET to
the rising edge of the synchronizing signal.
voltage,therateofchangeoftheinductorcurrentwhilethe
external P-channel MOSFET is on (ON cycle) decreases.
This reduction means that the P-channel MOSFET will
remainonformorethanoneoscillatorcycleiftheinductor
current has not ramped up to the threshold set by the
EAMP on the I pin. Further reduction in the input supply
TH
voltage will eventually cause the P-channel MOSFET to be
turned on 100%; i.e., DC. The output voltage will then be
determined by the input voltage minus the voltage drop
across the P-channel MOSFET and the inductor.
The typical capture range of the LTC3809’s phase-locked
loop is from approximately 200kHz to 1MHz.
Undervoltage Lockout
Spread Spectrum Modulation (SYNC/MODE and
PLLLPF Pins)
To prevent operation of the P-channel MOSFET below
safe input voltage levels, an undervoltage lockout is
incorporated in the LTC3809. When the input supply
Connecting the SYNC/MODE pin to a DC voltage above
1.35V and several hundred mV below V enables spread
IN
voltage (V ) drops below 2.25V, the external P- and
IN
spectrum modulation (SSM) operation. An internal 2.6μA
pull-down current source at SYNC/MODE helps to set the
voltageattheSYNC/MODEpinforthisoperationbytyinga
resistor with appropriate value between SYNC/MODE and
N-channel MOSFETs and all internal circuits are turned
off except for the undervoltage block, which draws only
a few microamperes.
V . This mode of operation spreads the internal oscillator
IN
3809fc
10
LTC3809
OPERATION (Refer to Functional Diagram)
Peak Current Sense Voltage Selection and Slope
maximum sense voltage allowed across the external P-
channel MOSFET is 125mV, 85mV or 204mV for the three
respective states of the IPRG pin.
Compensation (IPRG Pin)
When the LTC3809 controller is operating below 20%
duty cycle, the peak current sense voltage (between the
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peak sense voltage by a scale factor (SF) given by the
curve in Figure 1.
V and SW pins) allowed across the external P-channel
IN
MOSFET is determined by:
V
ITH – 0.7V
ΔVSENSE(MAX) = A •
Thepeakinductorcurrentisdeterminedbythepeaksense
voltage and the on-resistance of the external P-channel
MOSFET:
10
where A is a constant determined by the state of the IPRG
pin. Floating the IPRG pin selects A = 1; tying IPRG to V
IN
ΔVSENSE(MAX)
selects A = 5/3; tying IPRG to GND selects A = 2/3. The
IPK
=
maximum value of V is typically about 1.98V, so the
RDS(ON)
ITH
110
100
90
80
70
60
50
40
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3809 F01
Figure 1. Maximum Peak Current vs Duty Cycle
3809fc
11
LTC3809
APPLICATIONS INFORMATION
The typical LTC3809 application circuit is shown in Fig-
ure 10. External component selection for the controller
is driven by the load requirement and begins with the
selection of the inductor and the power MOSFETs.
where I
is the inductor peak-to-peak ripple current
RIPPLE
(see Inductor Value Calculation).
AreasonablestartingpointissettingripplecurrentI
to be 40% of I
yields:
RIPPLE
. Rearranging the above equation
OUT(MAX)
Power MOSFET Selection
ΔVSENSE(MAX)
IOUT(MAX)
5
6
The LTC3809’s controller requires two external power
MOSFETs: a P-channel MOSFET for the topside (main)
switchandaN-channelMOSFETforthebottom(synchro-
nous) switch. The main selection criteria for the power
RDS(ON)MAX = •
for Duty Cycle < 20%
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of R
amount of load current:
MOSFETs are the breakdown voltage V
, threshold
BR(DSS)
to provide the required
DS(ON)
voltage V
, on-resistance R
, reverse transfer
and the total gate
D(OFF)
GS(TH)
DS(ON)
capacitance C , turn-off delay t
RSS
charge Q .
ΔVSENSE(MAX)
G
5
RDS(ON)MAX = • SF •
6
IOUT(MAX)
The gate drive voltage is the input supply voltage. Since
the LTC3809 is designed for operation down to low input
where SF is a scale factor whose value is obtained from
the curve in Figure 1.
voltages, a sublogic level MOSFET (R
GS
guaranteed at
DS(ON)
V
= 2.5V) is required for applications that work close to
thisvoltage.WhentheseMOSFETsareused,makesurethat
the input supply to the LTC3809 is less than the absolute
These must be further derated to take into account the
significant variation in on-resistance with temperature.
The following equation is a good guide for determining the
maximum MOSFET V rating, which is typically 8V.
GS
required R
at 25°C (manufacturer’s specifica-
DS(ON)MAX
The P-channel MOSFET’s on-resistance is chosen based
on the required load current. The maximum average load
tion), allowing some margin for variations in the LTC3809
and external component values:
current I
is equal to the peak inductor current
OUT(MAX)
minus half the peak-to-peak ripple current I
. The
RIPPLE
ΔVSENSE(MAX)
IOUT(MAX) • ρT
5
6
RDS(ON)MAX = • 0.9 • SF •
LTC3809’s current comparator monitors the drain-to-
source voltage V of the top P-channel MOSFET, which
DS
is sensed between the V and SW pins. The peak induc-
IN
Theρ isanormalizingtermaccountingforthetemperature
T
tor current is limited by the current threshold, set by the
variationinon-resistance,whichistypicallyabout0.4%/°C,
voltage on the I pin, of the current comparator. The
TH
as shown in Figure 2. Junction-to-case temperature T is
JC
voltage on the I pin is internally clamped, which limits
TH
about 10°C in most applications. For a maximum ambi-
the maximum current sense threshold ΔV
to
SENSE(MAX)
ent temperature of 70°C, using ρ
~ 1.3 in the above
80°C
approximately 125mV when IPRG is floating (85mV when
IPRG is tied low; 204mV when IPRG is tied high).
equation is a reasonable choice.
The N-channel MOSFET’s on resistance is chosen based
The output current that the LTC3809 can provide is given
by:
on the short-circuit current limit (I ). The LTC3809’s
SC
short-circuit current limit comparator monitors the drain-
to-source voltage V of the bottom N-channel MOSFET,
ΔVSENSE(MAX)
IRIPPLE
DS
IOUT(MAX)
=
–
which is sensed between the GND and SW pins. The
RDS(ON)
2
3809fc
12
LTC3809
APPLICATIONS INFORMATION
2.0
VOUT
V
IN
Top P-Channel Duty Cycle =
1.5
1.0
0.5
0
V – VOUT
IN
Bottom N-Channel Duty Cycle =
V
IN
The MOSFET power dissipations at maximum output
current are:
VOUT
V
IN
2
PTOP
=
•IOUT(MAX)2 •ρT •RDS(ON) + 2•V
IN
50
100
–50
150
0
•IOUT(MAX) •CRSS • f
JUNCTION TEMPERATURE (°C)
3809 F02
V – VOUT
•IOUT(MAX)2 •ρT •RDS(ON)
IN
PBOT
=
Figure 2. RDS(ON) vs Temperature
V
IN
2
Both MOSFETs have I R losses and the P
equation
short-circuit current sense threshold ΔV is set approxi-
TOP
SC
includesanadditionaltermfortransitionlosses,whichare
largestathighinputvoltages. ThebottomMOSFETlosses
are greatest at high input voltage or during a short-circuit
when the bottom duty cycle is 100%.
mately 90mV when IPRG is floating (60mV when IPRG is
tied low; 150mV when IPRG is tied high). The on-resistance
of N-channel MOSFET is determined by:
ΔVSC
ISC(PEAK)
RDS(ON)MAX
=
The LTC3809 utilizes a non-overlapping, anti-shoot-
through gate drive control scheme to ensure that the
P- and N-channel MOSFETs are not turned on at the same
time. To function properly, the control scheme requires
that the MOSFETs used are intended for DC/DC switching
applications.ManypowerMOSFETs,particularlyP-channel
MOSFETs, are intended to be used as static switches and
therefore are slow to turn on or off.
The short-circuit current limit (I
) should be larger
SC(PEAK)
than the I
with some margin to avoid interfering
OUT(MAX)
with the peak current sensing loop. On the other hand,
in order to prevent the MOSFETs from excessive heating
and the inductor from saturation, I
should be
SC(PEAK)
smaller than the minimum value of their current ratings.
A reasonable range is:
Reasonable starting criteria for selecting the P-channel
MOSFET are that it must typically have a gate charge (Q )
I
< I
< I
G
OUT(MAX)
SC(PEAK) RATING(MIN)
less than 25nC to 30nC (at 4.5V ) and a turn-off delay
GS
Therefore,theon-resistanceofN-channelMOSFETshould
be chosen within the following range:
(t
) of less than approximately 140ns. However, due
D(OFF)
to differences in test and specification methods of various
MOSFET manufacturers, and in the variations in Q and
ΔVSC
IRATING(MIN)
ΔVSC
IOUT(MAX)
G
< RDS(ON)
<
t
withgatedrive(V )voltage,theP-channelMOSFET
D(OFF)
IN
ultimately should be evaluated in the actual LTC3809
application circuit to ensure proper operation.
where ΔV is 90mV, 60mV or 150mV with IPRG being
SC
floated, tied to GND or V respectively.
IN
Shoot-through between the P-channel and N-channel
MOSFETs can most easily be spotted by monitoring the
inputsupplycurrent.Astheinputsupplyvoltageincreases,
if the input supply current increases dramatically, then the
likely cause is shoot-through. Note that some MOSFETs
The power dissipated in the MOSFET strongly depends
on its respective duty cycles and load current. When the
LTC3809isoperatingincontinuousmode, thedutycycles
for the MOSFETs are:
3809fc
13
LTC3809
APPLICATIONS INFORMATION
that do not work well at high input voltages (e.g., V
5V) may work fine at lower voltages (e.g., 3.3V).
>
A reasonable starting point is to choose a ripple current
that is about 40% of I . Note that the largest ripple
IN
OUT(MAX)
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
Selecting the N-channel MOSFET is typically easier, since
foragivenR
,thegatechargeandturn-onandturn-off
DS(ON)
delays are much smaller than for a P-channel MOSFET.
V – VOUT VOUT
IN
L ≥
•
Operating Frequency and Synchronization
fOSC •IRIPPLE
V
IN
The choice of operating frequency, f , is a trade-off
OSC
between efficiency and component size. Low frequency
operation improves efficiency by reducing MOSFET
switching losses, both gate charge loss and transition
loss. However, lower frequency operation requires more
inductance for a given amount of ripple current.
Burst Mode Operation Considerations
The choice of R and inductor value also determines
the load current at which the LTC3809 enters Burst Mode
operation. When bursting, the controller clamps the peak
inductor current to approximately:
DS(ON)
The internal oscillator for the LTC3809’s controller runs
at a nominal 550kHz frequency when the PLLLPF pin is
left floating and the SYNC/MODE pin is not configured
for spread spectrum operation. Pulling the PLLLPF to
ΔVSENSE(MAX)
1
IBURST(PEAK) = •
4
RDS(ON)
The corresponding average current depends on the
amount of ripple current. Lower inductor values (higher
V selects 750kHz operation; pulling the PLLLPF to GND
IN
selects 300kHz operation.
I
) will reduce the load current at which Burst Mode
RIPPLE
operation begins.
Alternatively, the LTC3809 will phase-lock to a clock
signal applied to the SYNC/MODE pin with a frequency
between 250kHz and 750kHz (see Phase-Locked Loop
and Frequency Synchronization).
The ripple current is normally set so that the inductor cur-
rent is continuous during the burst periods. Therefore,
I
≤ I
BURST(PEAK)
RIPPLE
To further reduce EMI, the nominal 550kHz frequency will
be spread over a range with frequencies between 460kHz
and635kHzwhenspreadspectrummodulationisenabled
(see Spread Spectrum Modulation with SYNC/MODE and
PLLLPF Pins).
This implies a minimum inductance of:
V – VOUT
fOSC •IBURST(PEAK)
VOUT
V
IN
IN
LMIN
≤
•
A smaller value than L
could be used in the circuit,
MIN
Inductor Value Calculation
although the inductor current will not be continuous
during burst periods, which will result in slightly lower
efficiency. In general, though, it is a good idea to keep
Given the desired input and output voltages, the inductor
value and operating frequency, f , directly determine
OSC
the inductor’s peak-to-peak ripple current:
I
comparable to I
.
RIPPLE
BURST(PEAK)
VOUT V – VOUT
IN
IRIPPLE
=
•
Inductor Core Selection
V
fOSC •L
IN
Once the value of L is known, the type of inductor must
be selected. High efficiency converters generally cannot
af ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mμ® cores. Actual core loss is independent of core
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
3809fc
14
LTC3809
APPLICATIONS INFORMATION
size for a fixed inductor value, but is very dependent on
the inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
1/2
VOUT • V – V
(
)
IN
OUT
CINRequiredIRMS ≈IMAX
•
V
IN
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard”, which means that
inductance collapses abruptly when the peak design current
is exceeded. Core saturation results in an abrupt increase
in inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
This formula has a maximum value at V = 2V
,
IN
OUT
where I
= I /2. This simple worst-case condition
RMS
OUT
is commonly used for design because even significant
deviations do not offer much relief. Note that capacitor
manufacturer’s ripple current ratings are often based on
2000hoursoflife.Thismakesitadvisabletofurtherderate
the capacitor or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet the size or height requirements in the
design.DuetothehighoperatingfrequencyoftheLTC3809,
Molypermalloy (from Magnetics, Inc.) is a very good,
low loss core material for toroids, but is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mμ. Toroids are very space efficient,
especially when several layers of wire can be used, while
inductors wound on bobbins are generally easier to sur-
face mount. However, designs for surface mount that do
not increase the height significantly are available from
Coiltronics, Coilcraft, Dale and Sumida.
ceramiccapacitorscanalsobeusedforC .Alwaysconsult
IN
the manufacturer if there is any question.
The selection of C
is driven by the effective series
OUT
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔV ) is approximated by:
OUT
⎛
⎝
1
⎞
ΔVOUT ≈ IRIPPLE • ESR +
⎜
⎟
⎠
Schottky Diode Selection (Optional)
8• f •COUT
The schottky diode D in Figure 11 conducts current dur-
ing the dead time between the conduction of the power
MOSFETs. This prevents the body diode of the bottom
N-channel MOSFET from turning on and storing charge
during the dead time, which could cost as much as 1%
in efficiency. A 1A Schottky diode is generally a good
size for most LTC3809 applications, since it conducts
a relatively small average current. Larger diode results
in additional transition losses due to its larger junction
capacitance. This diode may be omitted if the efficiency
loss can be tolerated.
where f is the operating frequency, C
is the output
OUT
capacitance and I
is the ripple current in the induc-
RIPPLE
tor. The output ripple is highest at maximum input voltage
since I increase with input voltage.
RIPPLE
Setting Output Voltage
The LTC3809 output voltage is set by an external feed-
back resistor divider carefully placed across the output,
as shown in Figure 3. The regulated output voltage is
determined by:
⎛
⎝
RB ⎞
RA ⎠
VOUT = 0.6V • 1+
C and C
Selection
OUT
⎜
⎟
IN
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (V /V ). To
OUT IN
preventlargevoltagetransients,alowESRinputcapacitor
3809fc
15
LTC3809
APPLICATIONS INFORMATION
V
OUT
is an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
R
B
C
FF
LTC3809
V
FB
R
A
Theoutputofthephasedetectorisapairofcomplementary
current sources that charge or discharge the external filter
network connected to the PLLLPF pin. The relationship
between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
MODE, is shown in Figure 5 and specified in the electrical
characteristics table. Note that the LTC3809 can only be
synchronizedtoanexternalclockwhosefrequencyiswithin
range of the LTC3809’s internal VCO, which is nominally
200kHzto1MHz.Thisisguaranteed,overtemperatureand
process variations, to be between 250kHz and 750kHz. A
simplified block diagram is shown in Figure 6.
3809 F03
Figure 3. Settling Output Voltage
For most applications, a 59k resistor is suggested for R .
A
In applications where minimizing the quiescent current is
critical, R should be made bigger to limit the feedback
A
divider current. If R then results in very high impedance,
B
it may be beneficial to bypass R with a 50pF to 100pF
B
capacitor C .
FF
Run and Soft-Start Functions
The LTC3809 has a low power shutdown mode which is
controlled by the RUN pin. Pulling the RUN pin below 1.1V
puts the LTC3809 into a low quiescent current shutdown
1200
1000
800
600
400
200
0
mode (I = 9μA). Releasing the RUN pin, an internal 0.7μA
Q
(at V = 4.2V) current source will pull the RUN pin up
IN
to V , which enables the controller. The RUN pin can be
IN
driven directly from logic as showed in Figure 4.
Once the controller is enabled, the start-up of V
is
OUT
controlled by the internal soft-start, which slowly ramps
thepositivereferencetotheerroramplifier from 0V to 0.6V,
0.2
0.7
1.2
1.7
2.2
allowing V
to rise smoothly from 0V to its final value.
OUT
PLLLPF PIN VOLTAGE (V)
The default internal soft-start time is around 1ms.
3809 F05
Figure 5. Relationship Between Oscillator Frequency
and Voltage at the PLLLPF Pin When Synchronizing to
an External Clock
3.3V OR 5V
LTC3809
RUN
LTC3809
RUN
2.4V
3809 F04
R
LP
C
LP
Figure 4. RUN Pin Interfacing
PLLLPF
SYNC/
MODE
DIGITAL
PHASE/
FREQUENCY
DETECTOR
Phase-Locked Loop and Frequency Synchronization
EXTERNAL
OSCILLATOR
OSCILLATOR
TheLTC3809hasaphase-lockedloop(PLL)comprisedof
aninternalvoltage-controlledoscillator(VCO)andaphase
detector. Thisallowstheturn-onoftheexternalP-channel
MOSFE T to be locked to the rising edge of an ex ternal clock
signal applied to the SYNC/MODE pin. The phase detector
3809 F06
Figure 6. Phase-Locked Loop Block Diagram
3809fc
16
LTC3809
APPLICATIONS INFORMATION
and/or the V /V
ratio is close to unity, the synchro-
If the external clock frequency is greater than the internal
IN OUT
nous MOSFET may not be on for a sufficient amount of
time to transfer power from the output capacitor to the
auxiliary load. Forced continuous operation will sup-
port an auxiliary winding as long as there is a sufficient
synchronous MOSFET duty factor. The SYNC/MODE
input pin removes the requirement that power must be
drawn from the transformer primary side in order to
extract power from the auxiliary winding. With the loop
in continuous mode, the auxiliary output may nominally
be loaded without regard to the primary output load.
oscillator’s frequency, f , then current is sourced con-
OSC
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f , current is sunk continuously, pulling down
OSC
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
TheauxiliaryoutputvoltageV is normally set, as shown
in Figure 7, by the turns ratio N of the transformer:
AUX
the filter capacitor C holds the voltage.
LP
The loop filter components, C and R , smooth out
LP
LP
V
= (N + 1) • V
OUT
AUX
the current pulses from the phase detector and provide a
However,ifthecontrollergoesintopulse-skippingoperation
andhaltsswitchingduetoalightprimaryloadcurrent,then
AUX
stable input to the voltage-controlled oscillator. The filter
components C and R determine how fast the loop
LP
LP
V
will droop. An external resistor divider from V
to
AUX
acquires lock. Typically R = 10k and C is 2200pF to
LP
LP
the SYNC/MODE sets a minimum voltage V
:
AUX(MIN)
0.01μF.
R6
R5
⎛
⎝
⎞
⎟
⎠
Typically, the external clock (on SYNC/MODE pin) input
high level is 1.6V, while the input low level is 1.2V.
VAUX(MIN) = 0.4V • 1+
⎜
Table 1 summarizes the different states in which the
PLLLPF pin can be used.
If V
drops below this value, the SYNC/MODE voltage
AUX
forces temporary continuous switching operation until
is again above its minimum.
V
AUX
Table 1. The States of the PLLLPF Pin
PLLLPF PIN
0V
SYNC/MODE PIN
FREQUENCY
300kHz
DC Voltage (<1.2V or V )
V
IN
AUX
V
IN
+
Floating
DC Voltage (<1.2V or V )
550kHz
LTC3809
TG
SYNC/MODE
SW
L1
1:N
IN
1μF
R6
R5
V
IN
DC Voltage (<1.2V or V )
750kHz
IN
V
OUT
RC Loop Filter Clock Signal
Phase-Locked to
External Clock
+
Filter Caps
DC Voltage (>1.35V and <V – 0.5V) Spread Spectrum
IN
C
OUT
BG
460kHz to 635kHz
3809 F07
Auxiliary Winding Control Using SYNC/MODE Pin
Figure 7. Auxilliary Output Loop Connection
The SYNC/MODE pin can be used as an auxiliary feedback
to provide a means of regulating a flyback winding output.
When this pin drops below its ground-referenced 0.4V
threshold, continuous mode operation is forced.
Spread Spectrum Modulation with SYNC/MODE and
PLLLPF Pins
During continuous mode, current flows continuously in
thetransformerprimaryside.Theauxiliarywindingdraws
current only when the bottom synchronous N-channel
MOSFET is on. When primary load currents are low
Switching regulators, which operate at fixed frequency,
conductelectromagneticinterference(EMI)totheirdown-
stream load(s) with high spectral power density at this
fundamental and harmonic frequencies. The peak energy
3809fc
17
LTC3809
APPLICATIONS INFORMATION
can be lowered and distributed to other frequencies and
their harmonics by modulating the PWM frequency. The
LTC3809’s switching noise (at 550kHz) is spread between
460kHzand635kHzinspreadspectrummodulationopera-
Table 2 summarizes the different states in which the
SYNC/MODE Pin can be used.
Table 2. The States of the SYNC/MODE Pin
SYNC/MODE PIN
CONDITION
tion.Figure8showsthespectralplotsoftheoutput(V
noisewith/withoutspreadspectrummodulation. Notethe
significant reduction in peak output noise (>20dBm).
)
OUT
GND (0V to 0.35V)
Forced Continuous Mode
Current Reversal Allowed
V
(0.45V to 1.2V)
Pulse-Skipping Mode
No Current Reversal Allowed
FB
ThespreadspectrummodulationoperationoftheLTC3809
is enabled by setting SYNC/MODE pin to a DC voltage
Resistor to V
Spread Spectrum Modulation
Pulse Skipping at Light Loads
No Current Reversal Allowed
IN
(1.35V to V – 0.5V)
IN
between 1.35V and several hundred mV below V by
IN
tying a resistor between SYNC/MODE and V .
IN
V
Burst Mode Operation
No Current Reversal Allowed
IN
VOUT Spectrum without Spread Spectrum Modulation
Feedback Resistors
External Clock Signal
Regulate an Auxiliary Winding
Enable Phase-Locked Loop
(Synchronize to External Clock)
Pulse Skipping at Light Load
No Current Reversal Allowed
Fault Condition: Short-Circuit and Current Limit
NOISE (dBm)
–10dBm/DIV
If the LTC3809’s load current exceeds the short-circuit
current limit (I ), which is set by the short-circuit sense
SC
threshold (ΔV ) and the on resistance (R
) of
SC
DS(ON)
bottom N-channel MOSFET, the top P-channel MOSFET
is turned off and will not be turned on at the next clock
cycle unless the load current decreases below I . In this
3809 F08a
START FREQ: 400kHz
RBW: 100Hz
SC
STOP FREQ: 700kHz
case, the controller’s switching frequency is decreased
and the output is regulated by short-circuit (current limit)
protection.
VOUT Spectrum with Spread Spectrum Modulation
(CSSM = 2200pF)
In a hard short (V
= 0V), the top P-channel MOSFET
OUT
is turned off and kept off until the short-circuit condition
is cleared. In this case, there is no current path from
input supply (V ) to either V
or GND, which prevents
IN
OUT
excessive MOSFET and inductor heating.
NOISE (dBm)
–10dBm/DIV
Low Input Supply Voltage
Although the LTC3809 can function down to below 2.4V,
the maximum allowable output current is reduced as V
IN
decreasesbelow3V. Figure9showstheamountofchange
3809 F08b
START FREQ: 400kHz
RBW: 100Hz
as the supply is reduced down to 2.4V. Also shown is the
STOP FREQ: 700kHz
effect on V
.
REF
Figure 8. Spectral Response of Spread Spectrum Modulation
3809fc
18
LTC3809
APPLICATIONS INFORMATION
105
limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
V
REF
100
Efficiency = 100% – (L1 + L2 + L3 + …)
95
MAXIMUM
SENSE VOLTAGE
where L1, L2, etc. are the individual losses as a percent-
age of input power.
90
85
80
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3809 circuits: 1) LTC3809 DC bias current,
2
2) MOSFET gate-charge current, 3) I R losses and
75
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
4) transition losses.
INPUT VOLTAGE (V)
3809 F09
1) The V (pin) current is the DC supply current, given
IN
Figure 9. Line Regulation of VREF and Maximum Sense Voltage
in the Electrical Characteristics, which excludes MOSFET
driver currents. V current results in a small loss that
IN
Minimum On-Time Considerations
increases with V .
IN
Minimum on-time, t
is the smallest amount of time
2) MOSFET gate-charge current results from switching
the gate capacitance of the power MOSFET. Each time a
MOSFET gate is switched from low to high to low again,
ON(MIN)
that the LTC3809 is capable of turning the top P-channel
MOSFET on. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle and high frequency applications may approach
the minimum on-time limit and care should be taken to
ensure that:
a packet of charge dQ moves from V to ground. The
IN
resulting dQ/dt is a current out of V , which is typically
IN
much larger than the DC supply current. In continuous
mode, I
= f • Q .
GATECHG
P
2
3) I RlossesarecalculatedfromtheDCresistancesofthe
MOSFETs, inductor and/or sense resistor. In continuous
mode, the average output current flows through L but is
“chopped” between the top P-channel MOSFET and the
VOUT
OSC • V
tON(MIN)
<
f
IN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3809 will begin to skip
cycles (unless forced continuous mode is selected). The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase. The minimum on-
time for the LTC3809 is typically about 210ns. However,
bottom N-channel MOSFET. The MOSFET R
mul-
DS(ON)
tiplied by duty cycle can be summed with the resistance
2
of L to obtain I R losses.
4) Transition losses apply to the external MOSFET and
increase with higher operating frequencies and input
voltages. Transition losses can be estimated from:
as the peak sense voltage (I
) • R ) decreases,
DS(ON)
L(PEAK
the minimum on-time gradually increases up to about
260ns. This is of particular concern in forced continu-
ous applications with low ripple current at light loads. If
forced continuous mode is selected and the duty cycle
falls below the minimum on time requirement, the output
will be regulated by overvoltage protection.
2
Transition Loss = 2 • V • I
• C
• f
IN
O(MAX)
RSS
Otherlosses,includingC andC ESRdissipativelosses
IN
OUT
and inductor core losses, generally account for less than
2% total additional loss.
Checking Transient Response
Efficiency Considerations
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
a load step occurs, V
immediately shifts by an amount
OUT
3809fc
19
LTC3809
APPLICATIONS INFORMATION
Design Example
equal to (ΔI
) • (ESR), where ESR is the effective se-
LOAD
ries resistance of C . ΔI
also begins to charge or
OUT
LOAD
As a design example, assume V will be operating from a
IN
discharge C
generating a feedback error signal used
OUT
maximum of 4.2V down to a minimum of 2.75V (powered
by a single lithium-ion battery). Load current requirement
is a maximum of 2A, but most of the time it will be in a
standby mode requiring only 2mA. Efficiency at both low
and high load currents is impor tant. Burst Mode operation
at light loads is desired. Output voltage is 1.8V. The IPRG
pin will be left floating, so the maximum current sense
by the regulator to return V
to its steady-state value.
OUT
OUT
During this recovery time, V
can be monitored for
overshootorringingthatwouldindicateastabilityproblem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values.
threshold ΔV
is approximately 125mV.
The I series R -C filter (see Functional Diagram) sets
SENSE(MAX)
TH
C
C
the dominant pole-zero loop compensation.
VOUT
MaximumDuty Cycle =
= 65.5%
The I external components showed in the figure on the
V
TH
IN(MIN)
firstpageofthisdatasheetwillprovideadequatecompen-
sation for most applications. The values can be modified
slightly (from 0.2 to 5 times their suggested values) to
optimizetransientresponseoncethefinalPClayoutisdone
and the particular output capacitor type and value have
beendetermined.Theoutputcapacitorneedstobedecided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
From Figure 1, SF = 82%.
ΔVSENSE(MAX)
IOUT(MAX) • ρT
5
6
RDS(ON)MAX = • 0.9 • SF •
= 0.032Ω
A 0.032Ω P-channel MOSFET in Si7540DP is close to
this value.
TheN-channelMOSFETinSi7540DPhas0.017ΩR
The short circuit current is:
.
DS(ON)
time of 1μs to 10μs will produce output voltage and I
TH
pin waveforms that will give a sense of the overall loop
90mV
0.017Ω
ISC
=
= 5.3A
stability. The gain of the loop will be increased by increas-
ing R and the bandwidth of the loop will be increased
C
by decreasing C . The output voltage settling behavior is
So the inductor current rating should be higher than
5.3A.
C
related to the stability of the closed-loop system and will
demonstrate the actual overall supply performance. For
a detailed explanation of optimizing the compensation
components, including a review of control loop theory,
refer to Application Note 76.
The PLLLPF pin will be left floating, so the LTC3809 will
operateatitsdefaultfrequencyof550kHz. Forcontinuous
Burst Mode operation with 600mA I
minimum inductor value is:
, the required
RIPPLE
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
1.8V
550kHz • 600mA
1.8V
2.75V
⎛
⎝
⎞
⎟
⎠
LMIN
=
• 1−
= 1.88μH
⎜
with C , causing a rapid drop in V . No regulator can
OUT
OUT
A 6A 2.2μH inductor works well for this application.
will require an RMS current rating of at least 1A at
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
C
IN
temperature. A C
mately 60mV output ripple.
with 0.1Ω ESR will cause approxi-
OUT
theloadrisetimeislimitedtoapproximately(25)•(C
).
LOAD
Thus a 10μF capacitor would be require a 250μs rise time,
limiting the charging current to about 200mA.
3809fc
20
LTC3809
APPLICATIONS INFORMATION
PC Board Layout Checklist
• The current sense traces should be Kelvin connections
right at the P-channel MOSFET source and drain.
Whenlayingouttheprintedcircuitboard,usethefollowing
checklist to ensure proper operation of the LTC3809.
• Keepingtheswitchnode(SW)andthegatedrivernodes
(TG, BG) away from the small-signal components, es-
• The power loop (input capacitor, MOSFET, inductor,
output capacitor) should be as small as possible and
isolated as much as possible from LTC3809.
pecially the feedback resistors, and I compensation
TH
components.
• Put the feedback resistors close to the V pins. The I
FB
TH
compensation components should also be very close
to the LTC3809.
V
IN
2.75V TO 8V
10μF
s2
2
SYNC/MODE
1
6
9
8
PLLLPF
V
IN
MP
C
IPRG
TG
ITH
Si7540DP
L
R
ITH
220pF
LTC3809EDD
1.5μH
15k
4
10
7
V
OUT
I
TH
SW
BG
2.5V
(5A AT 5V
)
MN
Si7540DP
IN
187k
+
3
5
C
OUT
V
FB
RUN
GND
11
150μF
59k
100pF
3809 F10
L: VISHAY IHLP-2525CZ-01
: SANYO 4TPB150MC
C
OUT
Figure 10. 550kHz, Synchronizable DC/DC Converter with Internal Soft-Start
V
IN
2.75V TO 8V
10μF
s2
2
SYNC/MODE
10nF
10k
1
6
9
8
PLLLPF
IPRG
V
IN
MP
TG
Si7540DP
L
470pF
LTC3809EDD
1.5μH
V
OUT
15k
4
10
7
1.8V
(5A AT 5V
I
SW
BG
TH
)
100pF
IN
MN
Si7540DP
C
OUT
118k
3
5
22μF
V
RUN
FB
GND
11
s2
D
59k
OPT
100pF
3809 F11
L: VISHAY IHLP-2525CZ-01
D: ON SEMI MBRM120L (OPTIONAL)
Figure 11. Synchronizable DC/DC Converter with Ceramic Output Capacitors
3809fc
21
LTC3809
TYPICAL APPLICATIONS
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 p0.05
3.50 p0.05
2.15 p0.05 (2 SIDES)
1.65 p0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50
BSC
2.38 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
6
0.38 p 0.10
10
3.00 p0.10
(4 SIDES)
1.65 p 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD10) DFN 1103
5
1
0.25 p 0.05
0.50 BSC
0.75 p0.05
0.200 REF
2.38 p0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3809fc
22
LTC3809
PACKAGE DESCRIPTION
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev C)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 p 0.102
2.794 p 0.102
(.110 p .004)
0.889 p 0.127
(.035 p .005)
(.081 p .004)
1
0.29
REF
1.83 p 0.102
(.072 p .004)
0.05 REF
5.23
(.206)
MIN
2.083 p 0.102 3.20 – 3.45
(.082 p .004) (.126 – .136)
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
DETAIL “B”
10
0.50
(.0197)
BSC
0.305 p 0.038
(.0120 p .0015)
TYP
3.00 p 0.102
(.118 p .004)
(NOTE 3)
0.497 p 0.076
(.0196 p .003)
10 9
8
7 6
RECOMMENDED SOLDER PAD LAYOUT
REF
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
DETAIL “A”
0.254
(.010)
0o – 6o TYP
1
2
3
4 5
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 p 0.0508
(.004 p .002)
0.50
(.0197)
BSC
MSOP (MSE) 0908 REV C
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3809fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
t ion t h a t t he in ter c onne c t ion o f i t s cir cui t s a s de s cr ib e d her ein w ill no t in fr inge on ex is t ing p a ten t r igh t s.
23
LTC3809
TYPICAL APPLICATION
Synchronous DC/DC Converter with Spread Spectrum Modulation
V
IN
3.3V
C
300k
IN
22μF
2
1
9
SYNCH/MODE
LTC3809EDD
PLLLPF
V
IN
1000pF
8
MP
TG
Si3447BDV
L
100pF
2200pF
15k
187k
6
4
3
1.5μH
V
2.5V
2A
IPRG
OUT
10
SW
7
5
I
TH
MN
Si3460DV
BG
470pF
V
FB
RUN
C
GND
11
OUT
22μF
59k
3809 TA04
L: VISHAY IHLP-2525CZ-01
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PART NUMBER
DESCRIPTION
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Step-Down DC/DC Controller
2.75V ≤ V ≤ 9.8V, 3mm × 2mm DFN or 8-Lead SOT-23,
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Q
LTC3776
Dual, 2-Phase, No R
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Provides V
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DDR/QDR Memory Termination
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Low EMI, Synchronous Controller with Output Tracking
2.75V ≤ V ≤ 9.8V, 4mm × 3mm DFN, Spread Spectrum for
IN
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IN
Packages
PolyPhase is a trademark of Linear Technology Corporation.
3809fc
LT 1108 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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