LTC3810IG-TRPBF_技术文档

LTC3810

100V Current Mode

Synchronous Switching

Regulator Controller

FEATURES

DESCRIPTION

n

The LTC3810 is a synchronous step-down switching

regulator controller that can directly step-down voltages

from up to 100V, making it ideal for telecom and automo-

tive applications. The LTC3810 uses a constant on-time

valley current control architecture to deliver very low duty

cycles with accurate cycle-by-cycle current limit, without

requiring a sense resistor.

High Voltage Operation: Up to 100V

n

Large 1Ω Gate Drivers

n

No Current Sense Resistor Required

Dual N-Channel MOSFET Synchronous Drive

n

Extremely Fast Transient Response

0.5% 0.8V Voltage Reference

n

Programmable Output Voltage Tracking/Soft-Start

n

Generates 10V Driver Supply from Input Supply

A precise internal reference provides 0.5% DC accuracy. A

highbandwidth(25MHz)errorampliﬁerprovidesveryfast

line and load transient response. Large 1Ω gate drivers

allow the LTC3810 to drive multiple MOSFETs for higher

current applications. The operating frequency is selected

by an external resistor and is compensated for variations

n

Synchronizable to External Clock

n

Selectable Pulse Skip Mode Operation

n

Power Good Output Voltage Monitor

n

Adjustable On-Time/Frequency: t

< 100ns

ON(MIN)

n

Adjustable Cycle-by-Cycle Current Limit

Programmable Undervoltage Lockout

Output Overvoltage Protection

28-Pin SSOP Package

in V and can also be synchronized to an external clock

IN

forswitching-noisesensitiveapplications.Ashutdownpin

allows the LTC3810 to be turned off, reducing the supply

current to 240μA.

APPLICATIONS

Integratedbiascontrolgeneratesgatedrivepowerfromthe

input supply during start-up and when an output short-

circuit occurs, with the addition of a small external SOT23

MOSFET. When in regulation, power is derived from the

output for higher efﬁciency.

n

48V Telecom and Base Station Power Supplies

Networking Equipment, Servers

Automotive and Industrial Control Systems

n

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents

including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611.

TYPICAL APPLICATION

High Efﬁciency High Voltage Step-Down Converter

Efﬁciency vs Load Current

V

IN

15V TO 100V

100

R

ON

261k

+

V = 50V

IN

C

22μF

100k

IN

V

= 25V

IN

I

ON

M3

95

90

85

NDRV

ZXMN10A07F

V

= 75V

IN

PGOOD

BOOST

LTC3810

V

RNG

M1

L1

10μH

TG

Si7456DP

0.1μF

C

SS

V

MODE/SYNC

SS/TRACK

SHDN

OUT

SW

1000pF

12V/6A

EXTV

DRV

INTV

CC

R

FB1

14k

+

CC

+

D1

MBR1100

80

SENSE

C

OUT

I

TH

0

1

2

3

4

5

6

5pF

M2

Si7456DP

270μF

LOAD (A)

200k

BG

V

FB

3810 TA01b

–

SENSE

BGRTN

47pF

R

FB2

1k

SGND

1μF

3810 TA01

3810fb

1

LTC3810

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

Supply Voltages

I

BOOST

TG

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

INTV , DRV ...................................... –0.3V to 14V

ON

CC

NC

(DRV - BGRTN), (BOOST - SW)......... –0.3V to 14V

CC

NC

SW

3

BOOST ................................................ –0.3V to 114V

+

V

SENSE

NC

4

ON

BGRTN....................................................... –5V to 0V

V

5

RNG

EXTV .................................................. –0.3V to 15V

CC

PGOOD

NC

6

(NDRV - INTV ) Voltage ........................... –0.3V to 10V

CC

MODE/SYNC

NC

7

+

SW, SENSE Voltage ................................... –1V to 100V

–

I

SENSE

8

TH

I

ON

Voltage............................................... –0.3V to 100V

V

BGRTN

BG

9

FB

SS/TRACK Voltage ....................................... –0.3V to 5V

PGOOD Voltage............................................ –0.3V to 7V

RNG ON

PLL/LPF

SS/TRACK

SGND

10

11

12

13

14

DRV

CC

V

, V , MODE/SYNC, SHDN,

INTV

CC

UVIN Voltages........................................ –0.3V to 14V

SHDN

EXTV

CC

PLL/LPF, FB Voltages................................. –0.3V to 2.7V

UVIN

NDRV

TG, BG, INTV , EXTV RMS Currents.................50mA

CC

G PACKAGE

28-LEAD PLASTIC SSOP

Operating Temperature Range (Note 2)

T

= 125°C, θ = 100°C/W

JA

JMAX

LTC3810E............................................. –40°C to 85°C

LTC3810I............................................ –40°C to 125°C

Junction Temperature (Notes 3, 7)........................ 125°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

ORDER INFORMATION

LEAD FREE FINISH

LTC3810EG#PBF

LTC3810IG#PBF

LEAD BASED FINISH

LTC3810EG

TAPE AND REEL

LTC3810EG#TRPBF

LTC3810IG#TRPBF

TAPE AND REEL

LTC3810EG#TR

LTC3810IG#TR

PART MARKING

LTC3810EG

PACKAGE DESCRIPTION

28-Lead Plastic SSOP

PACKAGE DESCRIPTION

28-Lead Plastic SSOP

TEMPERATURE RANGE

–40°C to 85°C

LTC3810IG

–40°C to 125°C

TEMPERATURE RANGE

–40°C to 85°C

PART MARKING

LTC3810EG

LTC3810IG

–40°C to 125°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS

The ^ldenotes speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C, INTV_CC= DRV_CC= V_BOOST= V_ON= V_RNG= SHDN = UV_IN= V_EXTVCC= V_NDRV

–

+

= 10V, V_MODE/SYNC= V_SENSE= V_SENSE= V_BGRTN= V_SW=0V, unless otherwise speciﬁed.

SYMBOL

PARAMETER

INTV Supply Voltage

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

l

INTV

6.35

14

V

CC

I

INTV Supply Current

SHDN > 1.5V, I

SHDN = 0V

= 9.5V (Notes 4, 5)

NTVCC

3

240

6

600

mA

μA

Q

CC

INTV Shutdown Current

CC

3810fb

2

LTC3810

ELECTRICAL CHARACTERISTICS

The l denotes speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C, INTV_CC= DRV_CC= V_BOOST= V_ON= V_RNG= SHDN = UV_IN= V_EXTVCC= V_NDRV

–

+

= 10V, V_MODE/SYNC= V_SENSE= V_SENSE= V_BGRTN= V_SW= 0V, unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

BOOST Supply Current

SHDN > 1.5V (Note 5)

SHDN = 0V

270

0

400

5

μA

BOOST

V

Feedback Voltage

(Note 4)

0.796

0.794

0.792

0.800

0.804

0.806

0.808

V

FB

l

0°C to 85°C

–40°C to 85°C

–40°C to 125°C (I-Grade)

l

Feedback Voltage Line Regulation

Maximum Current Sense Threshold

7V < INTV < 14V (Note 4)

0.002

0.02

%/V

ΔV

CC

FB,LINE

V

RNG

V

RNG

V

RNG

= 2V, V = 0.76V

256

70

170

320

95

215

384

120

260

mV

SENSE(MAX)

FB

= 0V, V = 0.76V

FB

= INTV , V = 0.76V

CC FB

V

Minimum Current Sense Threshold

V

= 2V, V = 0.84V

–300

–85

mV

SENSE(MIN)

VFB

RNG

FB

= 0V, V = 0.84V

FB

= INTV , V = 0.84V

–200

CC FB

I

Feedback Current

V

FB

= 0.8V

20

100

25

150

nA

dB

A

VOL

(EA)

Error Ampliﬁer DC Open Loop Gain

65

f

U

Error Amp Unity-Gain Crossover

Frequency

(Note 6)

MHz

V

MODE/SYNC Threshold

MODE/SYNC Current

Shutdown Threshold

SHDN Pin Input Current

V

Rising

0.75

1.2

0.8

0

0.85

V

μA

V

MODE/SYNC

I

MODE/SYNC = 10V

1

2

1

MODE/SYNC

V

SHDN

1.5

0

I

μA

SHDN

l

V

VINUV

V

IN

Undervoltage Lockout

V

Rising

Falling

0.86

0.78

0.07

0.88

0.80

0.10

0.92

0.82

0.12

V

IN

Hysteresis

V

INTV Undervoltage Lockout

VCCUV

CC

l

Linear Regulator Mode

External Supply Mode

Trickle-Charge Mode

INTV Rising, I

= 100μA

6.05

11.7

6.2

12

6.35

12.3

V

CC

NDRV

INTV Rising, NDRV = INTV = EXTV

CC

INTV Rising, NDRV = INTV , EXTV = 0

CC

INTV Falling

5.7

CC

Oscillator and Phase-Locked Loop

t

On-Time

I

= 100μA

= 300μA

1.55

515

1.85

605

2.15

695

μs

ns

ON

t

Minimum On-Time

Minimum Off-Time

I

= 2000μA

100

350

ns

ON(MIN)

OFF(MIN)

ON(PLL)

ON

250

t

Modulation Range by PLL

ON

Down Modulation

Up Modulation

I

ON

I

ON

= 100μA, V

= 0.6V

= 1.8V

2.2

0.6

3.6

1.2

5

1.8

μs

PLL/LPF

I

Phase Detector Output Current

Sinking Capability

Sourcing Capability

PLL/LPF

f

< f

> f

15

–25

μA

PLLIN

SW

Driver

I

BG Driver Peak Source Current

V

= 0V

1.5

2

1

2

1

A

Ω

A

BG,PEAK

BG

R

BG Driver Pull-Down R

1.5

BG,SINK

TG,PEAK

DS(ON)

I

TG Driver Peak Source Current

V

TG

– V = 0V

SW

R

TG Driver Pull-Down R

Ω

TG,SINK

DS(ON)

PGOOD Output

PGOOD Upper Threshold

PGOOD Lower Threshold

V

Rising

Falling

7.5

–7.5

10

12.5

%

ΔV

FB

FBOV

–10

–12.5

PGOOD Hysteresis

Returning

1.5

3

%

ΔV

FB

FB,HYST

3810fb

3

LTC3810

ELECTRICAL CHARACTERISTICS

The l denotes speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C, INTV_CC= DRV_CC= V_BOOST= V_ON= V_RNG= SHDN = UV_IN= V_EXTVCC= V_NDRV

–

+

= 10V, V_MODE/SYNC= V_SENSE= V_SENSE= V_BGRTN= V_SW= 0V, unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

0.3

0

MAX

0.6

2

UNITS

V

PGOOD Low Voltage

PGOOD Leakage Current

PGOOD Delay

I

= 5mA

= 5V

PGOOD

I

V

μA

PGOOD

PG Delay

Falling

120

μs

FB

Tracking

I

SS/TRACK Source Current

Feedback Voltage at Tracking

V

> 0.5V

SS/TRACK

0.7

1.4

2.5

μA

SS/TRACK

V

= 0V, I = 1.2V (Note 4)

–0.018

0.5

V

FB,TRACK

TRACK

TH

V

= 0.5V, I = 1.2V (Note 4)

0.48

0.52

TRACK

TH

V

Regulators

CC

V

EXTV Switchover Voltage

CC

EXTVCC

l

EXTV Rising

6.4

0.1

6.7

0.3

V

CC

EXTV Hysteresis

0.5

10.6

250

CC

V

INTV Voltage from EXTV

10.5V < V < 15V

EXTVCC

9.4

10

170

0.01

10

V

mV

%

INTVCC,1

CC

V

– V

at Dropout

I

= 20mA, V

= 9.1V

EXTVCC

ΔV

V

EXTVCC

INTVCC

CC

EXTVCC,1

LOADREG,1

INTVCC,2

INTV Load Regulation from EXTV

= 0mA to 20mA, V

= 12V

EXTVCC

CC

INTV Voltage from NDRV Regulator

Linear Regulator in Operation

= 0mA to 20mA, V = 0

9.4

10.6

V

CC

INTV Load Regulation from NDRV

I

CC

0.01

40

%

ΔV

CC

EXTVCC

LOADREG,2

I

Current into NDRV Pin

V

NDRV

– V = 3V

INTVCC

20

60

μA

NDRV

NDRVTO

Linear Regulator Timeout Enable

Threshold

210

270

350

V

Maximum Supply Voltage

Trickle Charger Shunt Regulator

Trickle Charger Shunt Regulator,

15

V

CCSR

I

Maximum Current into NDRV/INTV

10

mA

CCSR

CC

INTV ≤ 16.7V (Note 8)

CC

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: The LTC3810 is tested in a feedback loop that servos V to the

FB

reference voltage with the I pin forced to a voltage between 1V and 2V.

TH

Note 5: The dynamic input supply current is higher due to the power

MOSFET gate charging being delivered at the switching frequency

Note 2: The LTC3810E is guaranteed to meet performance speciﬁcations

from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC3810I is guaranteed to meet

perfomance speciﬁcations over the full –40°C to 125°C operating

temperature range.

(Q • f ).

G

OSC

Note 6: Guaranteed by design. Not subject to test.

Note 7: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the speciﬁed maximum operating junction

temperature may impair device reliability.

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formula:

D

Note 8: I is the sum of current into NDRV and INTV

.

CC

LTC3810: T = T + (P • 100°C/W)

J

A

D

PARAMETER

Maximum V

LTC3810

100V

LTC3810-5

60V

LTC3812-5

60V

IN

MOSFET Gate Drive

6.35V to 14V

6.2V

4.5V to 14V

4.2V

4.5V to 14V

4.2V

+

INTV UV

CC

–

INTV UV

6V

4V

CC

3810fb

4

LTC3810

TYPICAL PERFORMANCE CHARACTERISTICS

Short-Circuit/

Fault Timeout Operation

Load Transient Response

Start-Up

INTV

V

CC

OUT

V

OUT

5V/DIV

10V/DIV

100mV/

DIV

INTV

CC

V

OUT

SS/TRACK

4V/DIV

5V/DIV

V

IN

50V/DIV

I

OUT

I

L

5A/DIV

I

L

5A/DIV

3810 G01

3810 G03

3810 G02

50μs/DIV

0A TO 5A LOAD STEP

FRONT PAGE CIRCUIT

V

= 48V

V

= 48V

SHORT

10ms/DIV

V

I

= 48V

= 1A

500μs/DIV

IN

LOAD

MODE/SYNC = 0V

R

= 0.1Ω

FRONT PAGE CIRCUIT

Short-Circuit/

Foldback Operation

Tracking

Pulse Skip Mode Operation

V

OUT

V

5V/DIV

OUT

100mV/

DIV

V

SS/TRACK

OUT

V

FB

5V/DIV

I

0.5V/

DIV

TH

SS/TRACK

0.5V/DIV

V

0.5V/DIV

FB

V

FB

I

L

0.5V/DIV

2A/DIV

I

L

5A/DIV

3810 G06

V

I

= 48V

OUT

MODE/SYNC = INTV

20μs/DIV

IN

3810 G04

3810 G05

= 100mA

V

I

= 48V

= 1A

V

= 48V

200μs/DIV

500μs/DIV

IN

LOAD

MODE/SYNC = 0V

IN

FRONT PAGE CIRCUIT

CC

FRONT PAGE CIRCUIT

Efﬁciency vs Load Current

Efﬁciency vs Input Voltage

Frequency vs Input Voltage

100

90

100

95

90

85

80

75

70

280

270

260

250

240

230

I

= 5A

OUT

V

= 36V

IN

V

= 12V

IN

V

= 60V

IN

I

= 0A

= 5A

OUT

I

= 0.5A

OUT

80

V

= 5V

OUT

Si7850 MOSFETs

MODE/SYNC = INTV

f = 250kHz

FRONT PAGE CIRCUIT

MODE/SYNC = 0V

FRONT PAGE CIRCUIT

CC

70

10 20 30 40

50

60

70

80

0

2

3

4

5

6

7

1

10 20 30 40

50

60

70

80

LOAD CURRENT (A)

INPUT VOLTAGE (V)

3810 G07

3810 G08

3810 G09

3810fb

5

LTC3810

TYPICAL PERFORMANCE CHARACTERISTICS

Current Sense Threshold

Frequency vs Load Current

vs I_THVoltage

On-Time vs I_ONCurrent

350

300

400

300

10000

1000

100

V

= INTV

ON

CC

V

= 2V

RNG

FORCED

CONTINUOUS

1.4V

1V

0.7V

0.5V

200

250

200

150

100

50

100

0

–100

–200

–300

–400

PULSE SKIP

FRONT PAGE CIRCUIT

0

10

1

2

3

5

0

4

0

1

I

1.5

2

2.5

3

0.5

10

100

1000

10000

VOLTAGE (V)

I

ON

CURRENT (μA)

LOAD CURRENT (A)

TH

3810 G12

3810 G10

3810 G11

On-Time vs V_ONVoltage

On-Time vs Temperature

Current Limit Foldback

680

660

640

620

250

200

150

100

50

700

600

I

= 300μA

V

= INTV

RNG CC

I

= 300μA

ON

500

400

300

200

100

600

580

560

0

0.2

0.4

(V)

0.6

50

TEMPERATURE (°C)

100 125

0

–50 –25

0

25

75

0.8

2

3

0

0.5

1

1.5

2.5

V

VOLTAGE (V)

FB

ON

38125 G15

3810 G14

3810 G13

Maximum Current Sense

Threshold vs V_RNGVoltage

Maximum Current Sense

Threshold vs Temperature

Feedback Reference Voltage

vs Temperature

0.803

0.802

0.801

0.800

0.799

0.798

0.797

230

220

210

200

190

180

400

300

200

100

0

V

RNG

= INTV

CC

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

1

1.5

0.5

2

TEMPERATURE (°C)

V

VOLTAGE (V)

RNG

3810 G18

3810 G17

3810 G16

3810fb

6

LTC3810

TYPICAL PERFORMANCE CHARACTERISTICS

Driver Peak Source Current

vs Temperature

Driver Pull-Down R_DS(ON)

vs Temperature

Driver Peak Source Current

vs Supply Voltage

1.50

1.25

1.00

0.75

3.0

2.5

2.0

1.5

1.0

0.5

0

2.5

2.0

V

= V

= 10V

INTVCC

V

= V

= 10V

INTVCC

BOOST

1.5

1

0.50

0.25

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–50 –25

0

25

50

75 100 125

5

6

7

8

9

10 11 12 13 14 15

TEMPERATURE (°C)

DRV /BOOST VOLTAGE (V)

CC

3810 G20

3810 G19

3810 G21

Driver Pull-Down R_DS(ON)

vs Supply Voltage

EXTV_CCLDO Resistance at

Dropout vs Temperature

INTV_CCCurrent vs Temperature

14

12

10

8

4

3

2

1

0

1.1

1.0

0.9

6

0.8

4

0.7

0.6

2

0

–25

0

50

75 100 125

–50

25

–50 –25

0

25

50

75 100 125

6

7

8

9

10 11 12 13 14 15

TEMPERATURE (°C)

DRV /BOOST VOLTAGE (V)

CC

3810 G23

3810 G24

3810 G22

INTV_CCShutdown Current

vs Temperature

INTV_CCCurrent vs INTV_CCVoltage

400

300

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

200

100

0

–25

0

50

75 100 125

–50

25

8

12

14

0

2

4

6

10

TEMPERATURE (°C)

INTV VOLTAGE (V)

CC

3810 G25

3810 G26

3810fb

7

LTC3810

TYPICAL PERFORMANCE CHARACTERISTICS

INTV_CCShutdown Current

vs INTV_CCVoltage

SS/TRACK Pull-Up Current

vs Temperature

3

2

300

250

200

150

100

50

1

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

8

12

14

0

2

4

6

10

INTV VOLTAGE (V)

CC

3810 G28

3810 G27

I_THVoltage

vs Load Current

Shutdown Threshold

vs Temperature

2.2

3.0

2.5

2.0

1.5

1.0

0.5

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

V

= 0V

RNG

FRONT PAGE CIRCUIT

0.6

–25

0

50

75 100 125

–50

25

4

6

7

0

1

2

3

5

TEMPERATURE (°C)

LOAD CURRENT (A)

3810 G30

3810 G29

3810fb

8

LTC3810

PIN FUNCTIONS

I

(Pin 1): On-Time Current Input. Tie a resistor from V

PLL/LPF (Pin 10): The phase-locked loop’s lowpass ﬁlter

is tied to this pin. The voltage at this pin defaults to 1.2V

when the IC is not synchronized with an external clock at

the MODE/SYNC pin.

ON

IN

to this pin to set the one-shot timer current and thereby

set the switching frequency.

V

(Pin 4): On-Time Voltage Input. Voltage trip point for

ON

theon-timecomparator.Tyingthispintotheoutputvoltage

SS/TRACK (Pin 11): Soft-Start/Tracking Input. For soft-

start, a capacitor to ground at this pin sets the ramp rate of

theoutputvoltage(approximately0.6s/μF).Forcoincident

orratiometrictracking,connectthispintoaresistivedivider

between the voltage to be tracked and ground.

or an external resistive divider from the output makes the

on-time proportional to V . The comparator defaults to

OUT

0.7V when the pin is grounded and defaults to 2.4V when

the pin is connected to INTV . Tie this pin to INTV in

CC

high V

applications to use a lower R value.

OUT

ON

SGND (Pin 12): Signal Ground. All small-signal compo-

nentsshouldconnecttothisgroundandeventuallyconnect

to PGND at one point.

V

(Pin 5): Sense Voltage Limit Set. The voltage at this

RNG

pin sets the nominal sense voltage at maximum output

current and can be set from 0.5V to 2V by a resistive

SHDN (Pin 13): Shutdown Pin. Pulling this pin below 1.5V

will shut down the LTC3810, turn off both of the external

MOSFET switches and reduce the quiescent supply cur-

rent to 240μA.

divider from INTV . The nominal sense voltage defaults

CC

to 95mV when this pin is tied to ground, and 215mV when

tied to INTV .

CC

PGOOD (Pin 6): Power Good Output. Open-drain logic

output that is pulled to ground when the output voltage

is not between 10% of the regulation point. The output

voltage must be out of regulation for at least 120μs before

the power good output is pulled to ground.

UVIN (Pin 14): UVLO Input. This pin is input to the internal

UVLO and is compared to an internal 0.8V reference. An

external resistor divider is connected to this pin and the

inputsupplytoprogramtheundervoltagelockoutvoltage.

When UVIN is less than 0.8V, the LTC3810 is shut down.

MODE/SYNC (Pin 7): Pulse Skip Mode Enable/Sync Pin.

This multifunction pin provides pulse skip mode enable/

disable control and an external clock input to the phase

detector. Pulling this pin below 0.8V or to an external

logic-levelsynchronizationsignaldisablespulseskipmode

operation and forces continuous operation. Pulling this

pin above 0.8V enables pulse skip mode operation. For a

clock input, the phase-locked loop will force the rising top

gate signal to be synchronized with the rising edge of the

clock signal.This pin can also be connected to a feedback

resistor divider from a secondary winding on the inductor

to regulate a second output voltage.

NDRV (Pin 15): Drive Output for External Pass Device of

the Linear Regulator for INTV . Connect to the gate of

CC

an external NMOS pass device and a pull-up resistor to

the input voltage V .

IN

EXTV (Pin 16): External Driver Supply Voltage. When

CC

this voltage exceeds 6.7V, an internal switch connects

this pin to INTV through an LDO and turns off the exter-

CC

nal MOSFET connected to NDRV, so that controller and

gate drive are drawn from EXTV .

CC

INTV (Pin 17): Main Supply Pin. All internal circuits

CC

except the output drivers are powered from this pin.

INTV should be bypassed to ground (Pin 10) with at

I

(Pin 8): Error Ampliﬁer Compensation Point and Cur-

CC

TH

least a 0.1μF capacitor in close proximity to the LTC3810.

rentControlThreshold. Thecurrentcomparatorthreshold

increases with control voltage. The voltage ranges from

0V to 2.6V with 1.2V corresponding to zero sense voltage

(zero current).

DRV (Pin 18): Driver Supply Pin. DRV supplies power

CC

to the BG output driver. This pin is normally connected to

INTV . DRV should be bypassed to BGRTN (Pin 20)

CC

with a low ESR (X5R or better) 1μF capacitor in close

V (Pin9):FeedbackInput.ConnectV througharesistor

FB

proximity to the LTC3810.

divider network to V

to set the output voltage.

OUT

3810fb

9

LTC3810

PIN FUNCTIONS

BG (Pin 19): Bottom Gate Drive. The BG pin drives the

SW (Pin 26): Switch Node Connection to Inductor and

Bootstrap Capacitor. Voltage swing at this pin is from a

Schottky diode (external) voltage drop below ground

gateofthebottomN-channelsynchronousswitchMOSFET.

This pin swings from BGRTN to DRV .

CC

to V .

IN

BGRTN(Pin20):BottomGateReturn.Thispinconnectsto

the source of the pull-down MOSFET in the BG driver and

is normally connected to ground. Connecting a negative

supply to this pin allows the synchronous MOSFET’s gate

to be pulled below ground to help prevent false turn-on

during high dV/dt transitions on the SW node. See the

Applications Information section for more details.

TG (Pin 27): Top Gate Drive. The TG pin drives the gate of

the top N-channel synchronous switch MOSFET. The TG

driver draws power from the BOOST pin and returns to the

SW pin, providing true ﬂoating drive to the top MOSFET.

BOOST (Pin 28): Top Gate Driver Supply. The BOOST pin

supplies power to the ﬂoating TG driver. BOOST should

be bypassed to SW with a low ESR (X5R or better) 0.1μF

capacitor. An additional fast recovery Schottky diode from

+

–

SENSE , SENSE (Pin 25, Pin 21): Current Sense Com-

parator Input. The (+) input to the current comparator is

normally connected to SW unless using a sense resistor.

The (–) input is used to accurately kelvin sense the bottom

side of the sense resistor or MOSFET.

DRV to the BOOST pin will create a complete ﬂoating

CC

charge-pumped supply at BOOST.

3810fb

10

LTC3810

FUNCTIONAL DIAGRAM

INTV

EXTV

N

INTV

CC

CC DRV

V

IN

5V

REG

0.8V

REF

INTV

MODE

LOGIC

CC

10V

+

–

NDRV

15

M3

V

IN

12V

6.2V

R

UVIN

14

UV1

UV2

200μA

OFF

–

+

INTV

–

+

CC

INTV

CC

V

UV

R

17

EXTV

16

IN

UV

CC

+

–

0.8V

+

F

MODE/SYNC

7

270μA

10V

–

+

–

PLL/LPF

10

ON

+

PLL-SYNC

1.4μA

+

–

V

ON

4

V

IN

D

B

6.7V

BOOST

28

100nA

TIMEOUT

LOGIC

C

IN

I

R

ON

1

C

TG

27

V

I

B

DRV OFF

VON

ION

V

IN

t

=

(76pF)

ON

FCNT

M1

R

ON

S

Q

SW

26

20k

+

SENSE

25

+

–

+

–

L1

SWITCH

LOGIC

V

OUT

I

REV

CMP

DRV

CC

18

SHDN

OV

C

VCC

BG

19

M2

+

BGRTN

20

C

OUT

×

–

SENSE

21

1.4V

0.7V

OVERTEMP

SENSE

V

RNG

PGOOD

6

I

’

TH

5

R

FB1

FOLDBACK

FB

I

TH

0.72V

+

–

4V

8

UV

OV

C

2.6V

C2

R

C

V

FB

9

C

C1

FAULT

+

–

R

FB2

RUN

SHDN

SGND

12

EA

–

+

–

+

0.88V

1.5V

0.8V

SS/TRACK

11

SHDN

13

3810 FD

3810fb

11

LTC3810

OPERATION

Main Control Loop

behaves as a constant frequency part against the load and

supply variations.

The LTC3810 is a current mode controller for DC/DC step-

down converters. In normal operation, the top MOSFET

is turned on for a ﬁxed interval determined by a one-shot

timer (OST). When the top MOSFET is turned off, the bot-

tom MOSFET is turned on until the current comparator

Pulling the SHDN pin low forces the controller into its

shutdown state, turning off both M1 and M2. Forcing a

voltage above 1.5V will turn on the device.

Pulse Skip Mode

I

trips, restarting the one-shot timer and initiating the

CMP

next cycle. Inductor current is determined by sensing the

The LTC3810 can operate in one of two modes selectable

with the MODE/SYNC pin—pulse skip mode or forced

continuous mode (see Figure 1). Pulse skip mode is se-

lected when increased efﬁciency at light loads is desired

(see Figure 2). In this mode, the bottom MOSFET is turned

off when inductor current reverses to minimize efﬁciency

lossduetoreversecurrentﬂowandgatechargeswitching.

–

+

voltage between the SENSE and SENSE pins using a

sense resistor or the bottom MOSFET on-resistance. The

voltage on the I pin sets the comparator threshold cor-

TH

responding to the inductor valley current. The fast 25MHz

error ampliﬁer EA adjusts this voltage by comparing the

feedback signal V to the internal 0.8V reference volt-

FB

age. If the load current increases, it causes a drop in the

At low load currents, I will drop below the zero current

TH

feedback voltage relative to the reference. The I voltage

TH

level (1.2V) shutting off both switches. Both switches will

thenrisesuntiltheaverageinductorcurrentagainmatches

remain off with the output capacitor supplying the load

the load current.

current until the I voltage rises above the zero current

TH

level to initiate another cycle. In this mode, frequency is

Theoperatingfrequencyisdeterminedimplicitlybythetop

MOSFET on-time and the duty cycle required to maintain

regulation. Theone-shottimergeneratesanontimethatis

proportionaltotheidealdutycycle,thusholdingfrequency

approximately constant with changes in V . The nominal

frequency can be adjusted with an external resistor R .

proportional to load current at light loads.

Pulse skip mode operation is disabled by comparator F

when the MODE/SYNC pin is brought below 0.8V, forcing

continuous synchronous operation. Forced continuous

mode is less efﬁcient due to resistive losses, but has the

advantage of better transient response at low currents,

approximatelyconstantfrequencyoperation,andtheability

to maintain regulation when sinking current.

IN

ON

For applications with stringent constant frequency re-

quirements, the LTC3810 can be synchronized with an

external clock. By programming the nominal frequency

the same as the external clock frequency, the LTC3810

100

V

= 25V

IN

90

80

70

V

= 75V

IN

PULSE SKIP MODE

FORCED CONTINUOUS

V

= 25V

IN

60

50

V

= 75V

IN

0A

40

30

20

10

0

PULSE SKIP MODE

FORCED CONTINUOUS

0.01

0.1

1

10

3810 F01

LOAD (A)

3810 F02

Figure 1. Comparison of Inductor Current Waveforms

for Pulse Skip Mode and Forced Continuous Operation

Figure 2. Efﬁciency in Pulse Skip Mode

and Forced Continuous Mode

3810fb

12

LTC3810

OPERATION

Fault Monitoring/Protection

skip mode operation, where it is possible that the bottom

MOSFET will be off for an extended period of time, an

internal timeout guarantees that the bottom MOSFET is

turned on at least once every 25μs for one on-time period

to refresh the bootstrap capacitor.

Constant on-time current mode architecture provides ac-

curate cycle-by-cycle current limit protection—a feature

thatisveryimportantforprotectingthehighvoltagepower

supply from output short circuits. The cycle-by-cycle cur-

rentmonitorguaranteesthattheinductorcurrentwillnever

The bottom driver has an additional feature that helps

minimizethepossibilityofexternalMOSFETshoot-through.

When the top MOSFET turns on, the switch node dV/dt

pulls up the bottom MOSFET’s internal gate through the

Millercapacitance, evenwhenthebottomdriverisholding

the gate terminal at ground. If the gate is pulled up high

enough, shoot-through between the top side and bottom

side MOSFETs can occur. To prevent this from occurring,

the bottom driver return is brought out as a separate pin

(BGRTN) so that a negative supply can be used to reduce

the effect of the Miller pull-up. For example, if a –2V sup-

ply is used on BGRTN, the switch node dV/dt could pull

exceed the value programmed on the V

pin.

RNG

Foldback current limiting provides further protection if the

output is shorted to ground. As V drops, the buffered

FB

currentthresholdvoltageI ispulleddownandclamped

THB

to 1V. This reduces the inductor valley current level to

one-sixth of its maximum value as V approaches 0V.

FB

Foldback current limiting is disabled at start-up.

Overvoltage and undervoltage comparators OV and UV

pull the PGOOD output low if the output feedback voltage

exits a 10% window around the regulation point after the

internal120μspowerbadmasktimerexpires.Furthermore,

in an overvoltage condition, M1 is turned off and M2 is

turned on immediately and held on until the overvoltage

condition clears.

the gate up 2V before the V of the bottom MOSFET has

GS

more than 0V across it.

V

DRV

IN

CC

The LTC3810 provides two undervoltage lockout com-

parators—one for the INTV /DRV supply and one for

D

+

B

LTC3810

DRV

CC

BOOST

TG

C

IN

CC

the input supply V . The INTV UV threshold is 6.2V to

C

B

IN

CC

M1

guaranteethattheMOSFETshavesufﬁcientgatedrivevolt-

L

SW

V

OUT

age before turning on. The V UV threshold (UVIN pin) is

IN

+

0.8V with 10% hysteresis which allows programming the

BG

C

OUT

M2

V

threshold with the appropriate resistor divider con-

IN

BGRTN

0V TO –5V

nected to V . If either comparator inputs are under the

IN

3810 F03

UV threshold, the LTC3810 is shut down and the drivers

are turned off.

Figure 3. Floating TG Driver Supply and Negative BG Return

Strong Gate Drivers

IC/Driver Supply Power

TheLTC3810containsverylowimpedancedriverscapable

of supplying amps of current to slew large MOSFET gates

quickly. Thisminimizestransitionlossesandallowsparal-

leling MOSFETs for higher current applications. A 100V

ﬂoating high side driver drives the top side MOSFET and

a low side driver drives the bottom side MOSFET (see

Figure 3). The bottom side driver is supplied directly

TheLTC3810’sinternalcontrolcircuitryandtopandbottom

MOSFET drivers operate from a supply voltage (INTV ,

CC

DRV pins) in the range of 6.2V to 14V. The LTC3810

CC

has two integrated linear regulator controllers to easily

generate this IC/driver supply from either the high voltage

input or from the output voltage. For best efﬁciency the

supply is derived from the input voltage during start-up

and then derived from the lower voltage output as soon

as the output is higher than 6.7V. Alternatively, the supply

from the DRV pin. The top MOSFET drivers are biased

CC

from ﬂoating bootstrap capacitor, C , which normally is

B

recharged during each off cycle through an external diode

can be derived from the input continuously if the output

from DRV when the top MOSFET turns off. In pulse

CC

3810fb

13

LTC3810

OPERATION

is < 6.7V or an external supply in the appropriate range

can be used. The LTC3810 will automatically detect which

mode is being used and operate properly.

start-up.TheMOSFETissizedforproperdissipationand

thedrivershutdown/restartforV <6.7Visdisabled.

OUT

This scheme is less efﬁcient but may be necessary if

V

< 6.7V and a boost network is not desired.

OUT

The four possible operating modes for generating this

supply are summarized as follows (see Figure 4):

3. Tricklechargemodeprovidesanevensimplerapproach

by eliminating the external MOSFET. The IC/driver sup-

ply capacitors are charged through a single high valued

1. LTC3810 generates a 10V start-up supply from a small

external SOT23 N-channel MOSFET acting as linear

resistorconnectedtotheinputsupply.WhentheINTV

CC

regulatorwithdrainconnectedtoV andgatecontrolled

IN

voltagereachestheturn-onthresholdof12V(automati-

cally raised from 6.7V to provide extra headroom for

start-up), the drivers turn on and begin charging up the

outputcapacitor.Whentheoutputreaches6.7V,IC/driver

powerisderivedfromtheoutput.Intrickle-chargemode,

the supply capacitors must have sufﬁcient capacitance

by the LTC3810’s internal linear regulator controller

through the NDRV pin. As soon as the output voltage

reaches 6.7V, the 10V IC/driver supply is derived from

the output through an internal low dropout regulator to

optimize efﬁciency. If the output is lost due to a short,

the LTC3810 goes through repeated low duty cycle

soft-start cycles (with the drivers shut off in between)

to attempt to bring up the output without burning up

the SOT23 MOSFET. This scheme eliminates the long

start-up times associated with a conventional trickle

charger by using an external MOSFET to quickly charge

such that they are not discharged below the 6V INTV

CC

UV threshold before the output is high enough to take

over or else the power supply will not start.

4.Lowvoltagesupplyavailable.Thesimplestapproachisif

alowvoltagesupply(between6.2Vand14V)isavailable

and connected directly to the IC/driver supply pins.

the IC/driver supply capacitors (C

, C

).

INTVCC DRVCC

2.Similar to (1) except that the external MOSFET is used

for continuous IC/driver power instead of just for

Mode 1: MOSFET for Start-Up Only

Mode 2: MOSFET for Continuous Use

V

IN

I > 270μA

NDRV

I < 270μA

NDRV

INTV

10V

INTV

10V

CC

+

LTC3810

V

OUT

(>6.7V)

EXTV

CC

V

IN

Mode 3: Trickle Charge Mode

Mode 4: External Supply

NDRV

INTV

CC

INTV

CC

10V

+

LTC3810

+

6.2V to

14V

–

3810 F04

EXTV

CC

EXTV

CC

V

OUT

Figure 4. Operating Modes for IC/Driver Supply

3810fb

14

LTC3810

APPLICATIONS INFORMATION

The basic LTC3810 application circuit is shown on the ﬁrst

page of this data sheet. External component selection is

primarily determined by the maximum input voltage and

load current and begins with the selection of the sense

resistance and power MOSFET switches. The LTC3810

uses either a sense resistor or the on-resistance of the

synchronouspowerMOSFETfordeterminingtheinductor

current.Thedesiredamountofripplecurrentandoperating

the sense resistor. Using a sense resistor provides a well

deﬁnedcurrentlimit, butaddscostandreducesefﬁciency.

Alternatively, one can eliminate the sense resistor and use

thebottomMOSFETasthecurrentsenseelementbysimply

+

connecting the SENSE pin to the lower MOSFET drain

–

and SENSE pin to the MOSFET source. This improves

efﬁciency, but one must carefully choose the MOSFET

on-resistance, as discussed below.

frequency largely determines the inductor value. Next, C

IN

Power MOSFET Selection

is selected for its ability to handle the large RMS current

into the converter and C is chosen with low enough

OUT

The LTC3810 requires two external N-channel power

MOSFETs, one for the top (main) switch and one for the

bottom (synchronous) switch. Important parameters for

ESR to meet the output voltage ripple and transient

speciﬁcation. Finally, loop compensation components

are selected to meet the required transient/phase margin

speciﬁcations.

the power MOSFETs are the breakdown voltage BV

,

DSS

threshold voltage V_(GS)TH, on-resistance R_DS(ON), input

capacitance and maximum current I_DS(MAX)

.

Maximum Sense Voltage and V

RNG

When the bottom MOSFET is used as the current sense

element, particular attention must be paid to its on-resis-

tance. MOSFET on-resistance is typically speciﬁed with

Inductor current is determined by measuring the volt-

age across a sense resistance that appears between the

–

+

SENSE and SENSE pins. The maximum sense voltage

a maximum value R

at 25°C. In this case,

DS(ON)(MAX)

is set by the voltage applied to the V

to approximately:

pin and is equal

RNG

additional margin is required to accommodate the rise in

MOSFET on-resistance with temperature:

V

= 0.173V

– 0.026

SENSE(MAX)

RNG

R_SENSE

R_DS(ON)(MAX)

=

The current mode control loop will not allow the inductor

current valleys to exceed V /R . In prac-

ꢀ_T

SENSE(MAX) SENSE

tice, one should allow some margin for variations in the

LTC3810andexternalcomponentvaluesandagoodguide

for selecting the sense resistance is:

The ρ term is a normalization factor (unity at 25°C)

T

accounting for the signiﬁcant variation in on-resistance

with temperature (see Figure 5) and typically varies

from 0.4%/°C to 1.0%/°C depending on the particular

V_SENSE(MAX)

R_SENSE

=

MOSFET used.

1.3•I_OUT(MAX)

2.0

An external resistive divider from INTV can be used

CC

to set the voltage of the V

pin between 0.5V and 2V

RNG

1.5

1.0

0.5

resulting in nominal sense voltages of 60mV to 320mV.

Additionally, the V pin can be tied to SGND or INTV

RNG

CC

in which case the nominal sense voltage defaults to 95mV

or 215mV, respectively.

+

–

Connecting the SENSE and SENSE Pins

The LTC3810 can be used with or without a sense resis-

tor. When using a sense resistor, place it between the

source of the bottom MOSFET, M2, and PGND. Connect

0

50

100

–50

150

0

JUNCTION TEMPERATURE (°C)

3810 F05

+

–

Figure 5. R_DS(ON)vs Temperature

the SENSE and SENSE pins to the top and bottom of

3810fb

15

LTC3810

APPLICATIONS INFORMATION

Themostimportantparameterinhighvoltageapplications

the top MOSFET but is not directly speciﬁed on MOSFET

RSS OS

deﬁnitions of these parameters are not included.

is breakdown voltage BV . Both the top and bottom

data sheets. C

and C are speciﬁed sometimes but

DSS

MOSFETs will see full input voltage plus any additional

ringing on the switch node across its drain-to-source dur-

ing its off-time and must be chosen with the appropriate

breakdown speciﬁcation. Since most MOSFETs in the 60V

When the controller is operating in continuous mode the

duty cycles for the top and bottom MOSFETs are given by:

V_OUT

to 100V range have higher thresholds (typically V

GS(MIN)

MainSwitchDutyCycle =

≥ 6V), the LTC3810 is designed to be used with a 6.2V to

V

IN

14V gate drive supply (DRV pin).

CC

V – V_OUT

IN

SynchronousSwitchDutyCycle=

For maximum efﬁciency, on-resistance R

and input

DS(ON)

V

IN

capacitanceshouldbeminimized. LowR

minimizes

DS(ON)

conduction losses and low input capacitance minimizes

transition losses. MOSFET input capacitance is a combi-

nation of several components but can be taken from the

typical “gate charge” curve included on most data sheets

(Figure 6).

The power dissipation for the main and synchronous

MOSFETs at maximum output current are given by:

V_OUT

P_TOP

=

I

(

²(ꢀ_T)R_DS(ON)

+

MAX

)

V

IN

V

IN

₂I

V

^MAX(R_DR)(C_MILLER)•

2

IN

MILLER EFFECT

V

GS

ꢁ

ꢃ

ꢂ

ꢄ

a

b

1

+

–

+

(f)

ꢆ

V

DS

+

V – V_TH(IL)V_{TH(IL) ꢆ}

ꢅ

ꢃ CC

Q

V

IN

GS

–

C

= (Q – Q )/V

B A DS

MILLER

3810 F06

V – V

IN

P_BOT

=

^OUT(I_MAX)²(ꢀ_T)R_DS(0N)

Figure 6. Gate Charge Characteristic

V

IN

The curve is generated by forcing a constant input cur-

rent into the gate of a common source, current source

loaded stage and then plotting the gate voltage versus

time. The initial slope is the effect of the gate-to-source

and the gate-to-drain capacitance. The ﬂat portion of the

curve is the result of the Miller multiplication effect of the

drain-to-gate capacitance as the drain drops the voltage

across the current source load. The upper sloping line is

due to the drain-to-gate accumulation capacitance and

the gate-to-source capacitance. The Miller charge (the

increase in coulombs on the horizontal axis from a to b

where ρ is the temperature dependency of R

, R

DS(ON) DR

T

is the effective top driver resistance (approximately 2Ω at

V

= V ), V is the drain potential and the change

GS

MILLER

IN

in drain potential in the particular application. V

is

TH(IL)

the data sheet speciﬁed typical gate threshold voltage

speciﬁed in the power MOSFET data sheet at the speciﬁed

drain current. C

is the calculated capacitance using

MILLER

the gate charge curve from the MOSFET data sheet and

the technique described above.

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

equation incudes an additional term for transition losses,

which peak at the highest input voltage. For high input

voltage low duty cycle applications that are typical for the

LTC3810, transition losses are the dominate loss term and

while the curve is ﬂat) is speciﬁed for a given V drain

DS

voltage, but can be adjusted for different V voltages by

DS

multiplying by the ratio of the application V to the curve

DS

speciﬁed V values. A way to estimate the C

term

DS

MILLER

therefore using higher R

device with lower C

DS(ON)

MILLER

is to take the change in gate charge from points a and b

usually provides the highest efﬁciency. The synchronous

MOSFET losses are greatest at high input voltage when

the top switch duty factor is low or during a short circuit

on a manufacturers data sheet and divide by the stated

V

voltage speciﬁed. C

is the most important se-

MILLER

DS

lection criteria for determining the transition loss term in

when the synchronous switch is on close to 100% of

3810fb

16

LTC3810

APPLICATIONS INFORMATION

the period. Since there is no transition loss term in the

synchronous MOSFET, optimal efﬁciency is obtained by

Tying a resistor R from V to the I pin yields an

ON IN ON

on-time inversely proportional to V . For a step-down

IN

minimizing R

— by using larger MOSFETs or paral-

converter,thisresultsinapproximatelyconstantfrequency

operation as the input supply varies:

DS(ON)

leling multiple MOSFETs.

Multiple MOSFETs can be used in parallel to lower

DS(ON)

V_OUT

V_VON• R_ON(76pF)

R

and meet the current and thermal requirements

f =

[H_Z]

if desired. The LTC3810 contains large low impedance

driverscapableofdrivinglargegatecapacitanceswithout

signiﬁcantly slowing transition times. In fact, when driv-

ing MOSFETs with very low gate charge, it is sometimes

helpful to slow down the drivers by adding small gate

resistors (10Ω or less) to reduce noise and EMI caused

by the fast transitions.

Toholdfrequencyconstantduringoutputvoltagechanges,

tie the V pin to V or to a resistive divider from V

ON

OUT

when V

> 2.4V. The V pin has internal clamps that

ON

limit its input to the one-shot timer. If the pin is tied below

0.7V,theinputtotheone-shotisclampedat0.7V.Similarly,

if the pin is tied above 2.4V, the input is clamped at 2.4V.

Operating Frequency

In high V

applications, tie V to INTV . Figures 7a

OUT

ON CC

and 7b show how R relates to switching frequency for

ON

The choice of operating frequency is a tradeoff between

efﬁciency and component size. Low frequency operation

improvesefﬁciencybyreducingMOSFETswitchinglosses

but requires larger inductance and/or capacitance in order

to maintain low output ripple voltage.

several common output voltages.

Changesintheloadcurrentmagnitudewillcausefrequency

shift. Parasitic resistance in the MOSFET switches and

inductor reduce the effective voltage across the induc-

tance, resulting in increased duty cycle as the load current

increases. By lengthening the on-time slightly as current

increases, constant frequency operation can be main-

tained. This is accomplished with a resistive divider from

The operating frequency of LTC3810 applications is de-

termined implicitly by the one-shot timer that controls

the on-time, t , of the top MOSFET switch. The on-time

ON

is set by the current out of the I pin and the voltage at

ON

the I pin to the V pin and V . The values required

will depend on the parasitic resistances in the speciﬁc

TH

ON

OUT

the V pin according to:

ON

V

t_ON

=

^VON(76pF)

I_ION

1000

V

= 5V

OUT

V

= 12V

V

OUT

V

= 3.3V

OUT

V

= 2.5V

OUT

= 5V

OUT

V = 3.3V

OUT

V

= 1.5V

OUT

100

10

100

(kΩ)

ON

1000

10

100

(kΩ)

1000

3810 F07a

R

ON

3810 F07b

Figure 7a. Switching Frequency vs R_ON(V_ON= 0V)

Figure 7b. Switching Frequency vs R_ON(V_ON= INTV_CC)

3810fb

17

LTC3810

APPLICATIONS INFORMATION

application. A good starting point is to feed about 25%

Inductor Selection

of the voltage change at the I pin to the V pin as

TH

ON

Given the desired input and output voltages, the induc-

tor value and operating frequency determine the ripple

current:

shown in Figure 8. Place capacitance on the V pin to

ON

ﬁlter out the I variations at the switching frequency.

TH

R

VON1

ꢁ

_OUTꢄ ꢁ

_OUTꢄ

V

200k

INTV

CC

ꢀI_L=

1ꢇ

V

ON

ꢃ

ꢆ ꢃ

ꢆ

10V

f L

V

ꢂ

ꢅ ꢂ

ꢅ

IN

C

R

VON

VON2

100k

LTC3810

TH

0.01μF

30k

I

Lower ripple current reduces core losses in the inductor,

ESR losses in the output capacitors and output voltage

ripple. Highest efﬁciency operation is obtained at low

frequency with small ripple current. However, achieving

this requires a large inductor. There is a tradeoff between

component size, efﬁciency and operating frequency.

3810 F08

Figure 8. Correcting Frequency Shift with Load Current Changes

Minimum Off-Time and Dropout Operation

The minimum off-time, t

, is the smallest amount

OFF(MIN)

A reasonable starting point is to choose a ripple current

of time that the LTC3810 is capable of turning on the bot-

tom MOSFET, tripping the current comparator and turning

the MOSFET back off. This time is generally about 250ns.

The minimum off-time limit imposes a maximum duty

that is about 40% of I

. The largest ripple current

OUT(MAX)

occurs at the highest V . To guarantee that ripple current

IN

does not exceed a speciﬁed maximum, the inductance

should be chosen according to:

cycle of t /(t + t

). If the maximum duty cycle

ON ON

OFF(MIN)

is reached, due to a dropping input voltage for example,

then the output will drop out of regulation. The minimum

input voltage to avoid dropout is:

ꢁ

ꢃ

ꢂ

ꢄ

ꢆ

ꢅ

ꢁ

ꢄ

V_OUT

fꢀI_L(MAX)

V_OUT

L =

1ꢇ

ꢃ

ꢆ

V

ꢂ

ꢅ

IN(MAX)

t

_ON+ t_OFF(MIN)

Once the value for L is known, the type of inductor must

be selected. High efﬁciency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcing the use of more expensive ferrite, molypermalloy

or Kool Mμ^®cores. A variety of inductors designed for

high current, low voltage applications are available from

manufacturers such as Sumida, Panasonic, Coiltronics,

Coilcraft and Toko.

V

_IN(MIN)= V_OUT

t_ON

A plot of maximum duty cycle vs frequency is shown in

Figure 9.

2.0

1.5

DROPOUT

REGION

Schottky Diode D1 Selection

1.0

0.5

0

The Schottky diode D1 shown in the front page schematic

conducts during the dead time between the conduction of

the power MOSFET switches. It is intended to prevent the

body diode of the bottom MOSFET from turning on and

storing charge during the dead time, which can cause a

modest (about 1%) efﬁciency loss. The diode can be rated

for about one half to one ﬁfth of the full load current since

it is on for only a fraction of the duty cycle. In order for the

0

0.25

0.50

0.75

1.0

DUTY CYCLE (V /V

)

OUT IN

3810 F09

Figure 9. Maximum Switching Frequency vs Duty Cycle

3810fb

18

LTC3810

APPLICATIONS INFORMATION

diode to be effective, the inductance between it and the

bottom MOSFET must be as small as possible, mandating

thatthesecomponentsbeplacedadjacently.Thediodecan

be omitted if the efﬁciency loss is tolerable.

by the aluminum capacitors alone, when used together,

the percentage of RMS current that will be supplied by the

aluminum capacitor is reduced to approximately:

1

%I_RMS,ALUMꢀ

•100%

2

1+(8fCR_ESR

)

Input Capacitor Selection

In continuous mode, the drain current of the top MOSFET

where R

is the ESR of the aluminum capacitor and C

ESR

is approximately a square wave of duty cycle V /V

is the overall capacitance of the ceramic capacitors. Using

an aluminum electrolytic with a ceramic also helps damp

the high Q of the ceramic, minimizing ringing.

OUT IN

which must be supplied by the input capacitor. To prevent

large input transients, a low ESR input capacitor sized for

the maximum RMS current is given by:

ꢄ^1/2

–1

Output Capacitor Selection

_OUTꢁ

V

OUT

IN

I_CIN(RMS)ꢀI_O(MAX)

ꢃ

ꢆ

The selection of C

is primarily determined by the ESR

V

ꢂ

ꢅ

OUT

IN

required to minimize voltage ripple. The output ripple

(ΔV ) is approximately equal to:

This formula has a maximum at V = 2V , where I

O(MAX)

=

IN

OUT

RMS

OUT

I

/2. This simple worst-case condition is commonly

ꢂ

ꢅ

ꢇ

1

usedfordesignbecauseevensigniﬁcantdeviationsdonot

offer much relief. Note that the ripple current ratings from

capacitor manufacturers are often based on only 2000

hours of life. This makes it advisable to further derate

the capacitor or to choose a capacitor rated at a higher

temperature than required. Several capacitors may also

be placed in parallel to meet size or height requirements

in the design.

ꢀV_OUTꢁ ꢀI_LESR+

ꢄ

8fC

ꢃ

_OUTꢆ

Since ΔI increases with input voltage, the output ripple

L

is highest at maximum input voltage. ESR also has a

signiﬁcant effect on the load transient response. Fast load

transitions at the output will appear as voltage across the

ESR of C

until the feedback loop in the LTC3810 can

OUT

change the inductor current to match the new load current

value. Typically, once the ESR requirement is satisﬁed the

capacitance is adequate for ﬁltering and has the required

RMS current rating.

BecausetantalumandOS-CONcapacitorsarenotavailable

in voltages above 30V, ceramics or aluminum electrolytics

mustbeusedforregulatorswithinputsuppliesabove30V.

Ceramic capacitors have the advantage of very low ESR

and can handle high RMS current, but ceramics with high

voltage ratings (> 50V) are not available with more than

a few microfarads of capacitance. Furthermore, ceram-

ics have high voltage coefﬁcients which means that the

capacitance values decrease even more when used at the

rated voltage. X5R and X7R type ceramics are recom-

mended for their lower voltage and temperature coef-

ﬁcients. Another consideration when using ceramics is

their high Q which, if not properly damped, may result in

excessive voltage stress on the power MOSFETs. Alumi-

num electrolytics have much higher bulk capacitance, but

they have higher ESR and lower RMS current ratings.

Manufacturers such as Nichicon, Nippon Chemi-Con

and Sanyo should be considered for high performance

throughhole capacitors. The OS-CON (organic semicon-

ductor dielectric) capacitor available from Sanyo has the

lowestproductofESRandsizeofanyaluminumelectroly-

tic at a somewhat higher price. An additional ceramic

capacitor in parallel with OS-CON capacitors is recom-

mended to reduce the effect of their lead inductance.

In surface mount applications, multiple capacitors placed

in parallel may be required to meet the ESR, RMS current

handlingandloadsteprequirements.Drytantalum,special

polymerandaluminumelectrolyticcapacitorsareavailable

in surface mount packages. Special polymer capacitors

offer very low ESR but have lower capacitance density

than other types. Tantalum capacitors have the highest

A good approach is to use a combination of aluminum

electrolyticsforbulkcapacitanceandceramicsforlowESR

and RMS current. If the RMS current cannot be handled

capacitance density but it is important to only use types

3810fb

19

LTC3810

APPLICATIONS INFORMATION

that have been surge tested for use in switching power

supplies. Several excellent surge-tested choices are the

AVX, TPS and TPSV or the KEMET T510 series. Aluminum

electrolytic capacitors have signiﬁcantly higher ESR, but

can be used in cost-driven applications providing that

consideration is given to ripple current ratings and long-

term reliability. Other capacitor types include Panasonic

SP and Sanyo POSCAPs.

Top MOSFET Driver Supply (C , D )

B B

An external bootstrap capacitor, C , connected to the

B

BOOST pin supplies the gate drive voltage for the topside

MOSFET. This capacitor is charged through diode D from

B

DRV whentheswitchnodeislow. WhenthetopMOSFET

CC

turns on, the switch node rises to V and the BOOST pin

IN

rises to approximately V + INTV . The boost capacitor

IN

CC

needs to store about 100 times the gate charge required

by the top MOSFET. In most applications 0.1μF to 0.47μF,

X5R or X7R dielectric capacitor is adequate.

Output Voltage

The LTC3810 output voltage is set by a resistor divider

according to the following formula:

The reverse breakdown of the external diode, D , must

B

begreaterthanV

. Anotherimportantconsideration

IN(MAX)

ꢀ

_FB1ꢃ

_FB2ꢄ

for the external diode is the reverse recovery and reverse

leakage, either of which may cause excessive reverse

current to ﬂow at full reverse voltage. If the reverse cur-

rent times reverse voltage exceeds the maximum allow-

able power dissipation, the diode may be damaged. For

best results, use an ultrafast recovery diode such as the

MMDL770T1.

R

V

_OUT= 0.8V 1+

ꢂ

ꢅ

ꢁ

The external resistor divider is connected to the output as

shownintheFunctionalDiagram, allowingremotevoltage

sensing. The resultant feedback signal is compared with

the internal precision 800mV voltage reference by the

error ampliﬁer. The internal reference has a guaranteed

tolerance of <1%. Tolerance of the feedback resistors

will add additional error to the output voltage. 0.1% to

1% resistors are recommended.

Bottom MOSFET Driver Return Supply (BGRTN)

The bottom gate driver, BG, switches from DRV to

CC

BGRTN where BGRTN can be a voltage between ground

and –5V. Why not just keep it simple and always connect

BGRTN to ground? In high voltage switching converters,

the switch node dV/dt can be many volts/ns, which will

pull up on the gate of the bottom MOSFET through its

Miller capacitance. If this Miller current, times the internal

gate resistance of the MOSFET plus the driver resistance,

exceeds the threshold of the FET, shoot-through will oc-

cur. By using a negative supply on BGRTN, the BG can be

pulledbelowgroundwhenturningthebottomMOSFEToff.

This provides a few extra volts of margin before the gate

reaches the turn-on threshold of the MOSFET. Be aware

Input Voltage Undervoltage Lockout

A resistor divider connected from the input supply to the

UVIN pin (see Functional Diagram) is used to program the

input supply undervoltage lockout thresholds. When the

rising voltage at UVIN reaches 0.88V, the LTC3810 turns

on, and when the falling voltage at UVIN drops below 0.8V,

the LTC3810 is shut down—providing 10% hysteresis.

The input voltage UVLO thresholds are set by the resistor

divider according to the following formulas:

ꢀ

_UV1ꢃ

_UV2ꢄ

R

V

_IN,FALLING= 0.8V • 1+

that the maximum voltage difference between DRV and

CC

ꢂ

ꢅ

ꢁ

BGRTNis14V. If, forexample, V

=–2V, themaximum

BGRTN

voltage on DRV pin is now 12V instead of 14V.

and

CC

ꢀ

_UV1ꢃ

_UV2ꢄ

R

V

_IN,RISING= 0.88V • 1+

IC/MOSFET Driver Supplies (INTV and DRV )

CC

ꢂ

ꢅ

ꢁ

The LTC3810 drivers are supplied from the DRV and

CC

BOOST pins (see Figure 3), which have an absolute maxi-

If input supply undervoltage lockout is not needed, it can

be disabled by connecting UVIN to INTV .

mum voltage of 14V. Since the main supply voltage, V

IN

CC

3810fb

20

LTC3810

APPLICATIONS INFORMATION

is typically much higher than 14V a separate supply for

from overheating. Soft-start cycles are then attempted at

low duty cycle intervals to try to bring the output back up

(see Figure 10). This fault timeout operation is enabled

the IC power (INTV ) and driver power (DRV ) must

CC

be used. The LTC3810 has integrated bias supply control

by choosing the choosing R

such that the resistor

circuitry that allows the IC/driver supply to be easily

NDRV

current I

is greater than 270μA by using the follow-

generated from V and/or V

with minimal external

NDRV

ing formulas:

IN

OUT

components. There are four ways to do this as shown in

the simpliﬁed schematics of Figure 4 and explained in the

following sections.

P_MOSFET(MAX)/I_CCꢁ V_TH

270μA

R_NDRVꢀ

Using the Linear Regulator for INTV /DRV Supply

where

I_CC=(f) Q_G(TOP)+Q_G(BOTTOM)+ 3mA

CC

In Mode 1, a small external SOT23 MOSFET, controlled by

the NDRV pin, is used to generate a 10V start-up supply

(

)

and V is the threshold voltage of the MOSFET.

TH

from V . The small SOT23 package can be used because

IN

theNMOSisoncontinuouslyonlyduringthebriefstart-up

period. As soon as the output voltage reaches 6.7V, the

LTC3810 turns off the external NMOS and the LTC3810

The value of R

follows:

also affects the V

as

NDRV

IN(MIN)

V

= V

+ (40μA) R

+V

T

(1)

IN(MIN)

INTVCC(MIN)

NDRV

regulates the 10V supply from the EXTV pin (connected

CC

where V

is normally 6V for driving 60V to 100V

to V

or a V

derived boost network) through an

INTVCC(MIN)

OUT

internal low dropout regulator. For this mode to work

properly, EXTV must be in the range 6.7V < EXTV

MOSFETs. If minimum V is not low enough, consider

IN

<

CC

reducing R

an NMOS to reduce V to ~1.4V.

and/or using a darlington NPN instead of

CC

NDRV

15V. If V

< 6.7V, a charge pump or extra winding can

OUT

T

be used to raise EXTV to the proper voltage, or alter-

CC

When using R

equal to the computed value, the

NDRV

natively, Mode 2 should be used as explained later in this

LTC3810 will enable the low duty cycle soft-start retries

only when the desired maximum power dissipation,

section. If V

is shorted or otherwise goes below the

OUT

minimum 6.5V threshold, the MOSFET connected to V

IN

P

, in the MOSFET is exceeded and leave the

MOSFET(MAX)

is turned back on to maintain the 10V supply. However if

the output cannot be brought up within a timeout period,

the drivers are turned off to prevent the SOT23 MOSFET

drivers on continuously otherwise. The shutoff/restart

times are a function of the TRACK/SS capacitor value.

FAULT TIMEOUT

ENABLED

DRIVER OFF THRESHOLD

DRIVER POWER

FROM V

OUT

I

= 1.4MA (SOURCE)

SS/TRACK

DRIVER POWER

FROM V

I

= 0.1MA (SINK)

IN

SS/TRACK

START-UP

EXTV UV THRESHOLD

CC

V

OUT

SHORT-CIRCUIT EVENT

START-UP INTO SHORT-CIRCUIT

TG/BG

3810 F10

Figure 10. Fault Timeout Operation

3810fb

21

LTC3810

APPLICATIONS INFORMATION

The external NMOS for the linear regulator should be a

If the required R

value results in an unacceptable

NDRV

standard3Vthresholdtype(i.e.,notalogiclevelthreshold).

valueforV

(seeEquation1), faulttimeoutoperation

IN(MIN)

The rate of charge of INTV from 0V to 10V is controlled

can also be disabled by connecting a 500k to 2M resistor

from the SS/TRACK pin to INTV .

CC

by the LTC3810 to be approximately 75μs regardless of

CC

the size of the capacitor connected to the INTV pin. The

CC

Using Trickle Charge Mode

charging current for this capacitor is approximately:

Trickle charge mode is selected by shorting NDRV and

INTV and connecting EXTV to V . Trickle charge

ꢀ

ꢃ

10V

75μs

I_C=

C_INTVCC

ꢂ

ꢅ

CC

OUT

ꢁ

ꢄ

mode has the advantage of not requiring an external

MOSFET but takes longer to start up due to slow charge

The safe operating area (SOA) for the external NMOS

should be chosen so that capacitor charging does not

damage the NMOS. Excessive values of capacitor are

unnecessary and should be avoided. Typically values in

the 1μF to 10μF work well.

up of C

• R

and C

DRVCC

through R

(t

= 0.77

INTVCC

DRVCC

PULLUP DELAY

• C

) and usually requires larger INTV /

PULLUP

CC

DRV capacitor values to hold up the supply voltage dur-

CC

ing start-up. Once the INTV /DRV voltage reaches the

CC

trickle charge UV threshold of 12V, the drivers will turn on

Onemoredesignrequirementforthismodeistheminimum

soft-start capacitor value. The fault timeout is enabled

when SS/TRACK voltage is greater than 4V. This gives the

power supply time to bring the output up before it starts

the timeout sequence. To prevent timeout sequence from

startingprematurelyduringstart-up,aminimumC value

is necessary to ensure that V

> 6.7V. To ensure this, choose:

and start discharging C

/C

at a rate determined

INTVCC DRVCC

by the driver current I . In order to ensure proper start-

G

up, C

/C

CC

must be chosen large enough so that

INTVCC DRVCC

the EXTV voltage reaches the switchover threshold of

6.7V before C

UV threshold of 6V. This is ensured if:

/C

discharges below the falling

INTVCC DRVCC

SS

< 4V until V

SS/TRACK

EXTVCC

C_INTVCC+C_DRVCC>I_G•

–6

5.5•10⁵•C_SS

V_OUT(REG)

ꢀ

ꢂ

ꢁ

ꢃ

ꢅ

ꢄ

C

> C

• (2.3 × 10 )/I

SS

OUT

OUT(MAX)

C_OUT

I_MAX

Larger of

or

Mode 2 should be used if V

is outside of the 6.7V <

OUT

EXTV < 15V operating range and the extra complexity

CC

whereI isthegatedrivecurrent=(f)(Q

and I

RNG

+Q

)

of a charge pump or extra inductor winding is not wanted

G

MAX

.

G(TOP)

G(BOTTOM)

is the maximum inductor current selected by

to boost this voltage above 6.7V. In this mode, EXTV is

CC

V

grounded and the NMOS is chosen to handle the worst-

case power dissipation:

For R

, the value should fall in the following range

PULLUP

to ensure proper start-up:

ꢀ

ꢂ

P_MOSFET= V

f Q_G(TOP)+Q_G(BOTTOM)+ 3mA

( )

(

)

(

)

IN(MAX)

ꢁ

ꢃ

Min R > (V

–14V)/I

–12V)/I

PULLUP

IN(MAX)

CCSR

To operate properly, the fault timeout operation must be

disabled by choosing

Max R

< (V

IN(MIN)

PULLUP

Q,SHUTDOWN

R

> (V

– 10V – V )/270μA

IN(MAX) TH

NDRV

3810fb

22

LTC3810

APPLICATIONS INFORMATION

Using an External Supply Connected to the INTV /

2. EXTV connected directly to V . This is the normal

CC

OUT

DRV Pins

connection for 6.7V < V

< 15V and provides the

CC

OUT

highest efﬁciency. The power supply will start up using

an external NMOS or a bleed resistor until the output

supply is available.

If an external supply is available between 6.2V and 14V,

the supply can be connected directly to the INTV /DRV

CC

pins. In this mode, INTV , EXTV and NDRV must be

CC

shorted together.

3. EXTV connected to an output-derived boost network.

CC

If V

< 6.7V. The low voltage output can be boosted

OUT

INTV /DRV Supply and the EXTV Connection

using a charge pump or ﬂyback winding to greater

CC

than 6.7V.

TheLTC3810containsaninternallowdropoutregulatorto

produce the 10V INTV /DRV supply from the EXTV

CC

4. EXTV connected to INTV . This is the required

CC

pin voltage. This regulator turns on when the EXTV pin

connection for EXTV if INTV is connected to an

CC

is above 6.7V and remains on until EXTV drops below

external supply where the external supply is 6.2V <

< 15V.

CC

6.4V. This allows the IC/MOSFET power to be derived from

V

EXT

the output or an output derived boost network during

Applications using large MOSFETs with a high input volt-

age and high frequency of operation may result in a large

normal operation and from the external NMOS from V

IN

during start-up or short-circuit. Using the EXTV pin in

CC

EXTV pin current. Therefore, it is good design practice

CC

this way results in signiﬁcant efﬁciency gains compared

to verify that the maximum junction temperature rating

to what would be possible when deriving this power

and RMS current rating are within the maximum limits.

continuously from the typically much higher V voltage.

IN

Typically, most of the EXTV current consists of the

CC

The EXTV connection also allows the power supply to

CC

MOSFET gates current. In continuous mode operation,

be conﬁgured in trickle charge mode in which it starts up

this EXTV current is:

CC

with a high valued “bleed” resistor connected from V

IN

I_EXTVCC= f Q_G(TOP)+Q_G(BOTTOM)+ 3mA <50mA

(

)

to INTV to charge up the INTV capacitor. As soon as

CC

the output rises above 6.7V the internal EXTV regulator

CC

The junction temperature can be estimated from the

equations given in Note 2 of the Electrical Characteristics

as follows:

takes over before the INTV capacitor discharges below

CC

the UV threshold. When the EXTV regulator is active,

CC

the EXTV pin can supply up to 50mA RMS. Do not ap-

CC

T = T + I

• (V

– V )(100°C/W)

INTVCC

J

A

EXTVCC

ply more than 15V to the EXTV pin. The following list

CC

< 125°C

summarizes the possible connections for EXTV :

CC

If absolute maximum ratings are exceeded, consider

using an external supply connected directly to the

1. EXTV grounded. This connection will require INTV

CC

to be powered continuously from an external NMOS

INTV pin.

CC

from V resulting in an efﬁciency penalty as high as

IN

10% at high input voltages.

3810fb

23

LTC3810

APPLICATIONS INFORMATION

FEEDBACK LOOP/COMPENSATION

crossover frequency, this zero may provide enough phase

boost to achieve the desired phase margin and the only

requirement of the compensation will be to guarantee that

Feedback Loop Types

the gain is below zero at frequencies above f /4. If the

SW

In a typical LTC3810 circuit, the feedback loop consists

of the modulator, the output ﬁlter and load, and the

feedback ampliﬁer with its compensation network. All of

these components affect loop behavior and must be ac-

counted for in the loop compensation. The modulator and

output ﬁlter consists of the internal current comparator,

the output MOSFET drivers and the external MOSFETs,

inductor and output capacitor. Current mode control

eliminates the effect of the inductor by moving it to the

inner loop, reducing it to a ﬁrst order system. From a

feedback loop point of view, it looks like a linear voltage

ESR zero is above the crossover frequency, the feedback

ampliﬁerwillprobablyberequiredtoprovidephaseboost.

For most LTC3810 applications, Type 2 compensation will

provide enough phase boost; however some applications

where high bandwidth is required with low ESR ceramics

and lots of bulk capacitance, Type 3 compensation may

be necessary to provide additional phase boost.

The two types of compensation networks, “Type 2” and

“Type 3” are shown in Figures 11 and 12. When compo-

nent values are chosen properly, these networks provide

a “phase bump” at the crossover frequency. Type 2 uses

a single pole-zero pair to provide up to about 60° of phase

boostwhileType3usestwopolesandtwozerostoprovide

up to 150° of phase boost.

controlled current source from I to V

and has a gain

TH

OUT

equal to (I

R

)/1.2V. It has fairly benign AC behavior

MAX OUT

at typical loop compensation frequencies with signiﬁcant

phase shift appearing at half the switching frequency. The

external output capacitor and load cause a ﬁrst order roll

off at the output at the R

C

pole frequency, with

OUT OUT

C2

C1

the attendant 90° phase shift. This roll off is what ﬁlters

the PWM waveform, resulting in the desired DC output

voltage. The output capacitor also contributes a zero at

IN

R2

–6dB/OCT

GAIN

R1

FB

–6dB/OCT

–

the C

R

frequency which adds back the 90° phase

OUT ESR

R

OUT

0

FREQ

–90

B

and cancels the ﬁrst order roll off.

V

+

REF

–180

–270

–360

PHASE

So far, the AC response of the loop is pretty well out of the

user’s control. The modulator is a fundamental piece of

the LTC3810 design and the external output capacitor is

usually chosen based on the regulation and load current

requirements without considering the AC loop response.

The feedback ampliﬁer, on the other hand, gives us a

handle with which to adjust the AC response. The goal is

to have 180° phase shift at DC (so the loop regulates), and

something less than 360° phase shift (preferably about

300°) at the point that the loop gain falls to 0dB, i.e., the

crossover frequency, with as much gain as possible at

frequencies below the crossover frequency. Since the

modulator/output ﬁlter is a ﬁrst order system with maxi-

3810 F11

Figure 11. Type 2 Schematic and Transfer Function

IN

C2

C1

C3

R3

R2

R1

–6dB/OCT

GAIN

FB

–

+6dB/OCT

–6dB/OCT

R

OUT

0

FREQ

B

–90

V

REF

+

–180

–270

–360

PHASE

mum of 90° phase shift (at frequencies below f /4) and

SW

the feedback ampliﬁer adds another 90° of phase shift,

some phase boost is required at the crossover frequency

to achieve good phase margin. If the ESR zero is below the

3810 F12

Figure 12. Type 3 Schematic and Transfer Function

3810fb

24

LTC3810

APPLICATIONS INFORMATION

Feedback Component Selection

If breadboard measurement is not practical, a SPICE

simulation can be used to generate approximate gain/

phase curves. Plug the expected capacitor, inductor

and MOSFET values into the following SPICE deck and

Selecting the R and C values for a typical Type 2 or Type 3

loop is a nontrivial task. The applications shown in this

data sheet show typical values, optimized for the power

components shown. They should give acceptable perfor-

mancewithsimilarpowercomponents,butcanbewayoffif

evenonemajorpowercomponentischangedsigniﬁcantly.

Applicationsthatrequireoptimizedtransientresponsewill

require recalculation of the compensation values speciﬁ-

callyforthecircuitinquestion.Theunderlyingmathematics

are complex, but the component values can be calculated

in a straightforward manner if we know the gain and phase

of the modulator at the crossover frequency.

generate an AC plot of V /V with gain in dB and

OUT ITH

phase in degrees. Refer to your SPICE manual for details

of how to generate this plot.

*3810 modulator gain/phase

*2006 Linear Technology

*this ﬁle simulates a simpliﬁed model of

*the LTC3810 for generating a v(out)/v(ith)

*bode plot

.param rdson=.0135 ;MOSFET rdson

Modulator gain and phase can be obtained in one of

three ways: measured directly from a breadboard, or if

the appropriate parasitic values are known, simulated or

generated from the modulator transfer function. Mea-

surement will give more accurate results, but simulation

or transfer function can often get close enough to give

a working system. To measure the modulator gain and

phase directly, wire up a breadboard with an LTC3810

and the actual MOSFETs, inductor and input and output

capacitors that the ﬁnal design will use. This breadboard

should use appropriate construction techniques for high

speed analog circuitry: bypass capacitors located close

to the LTC3810, no long wires connecting components,

appropriately sized ground returns, etc. Wire the feedback

.param Vrng=2

;use 1.4 for INTVCC and

0.7 for ground

.param vsnsmax={0.173*Vrng-0.026}

.param Imax={vsnsmax/rdson}

.param DL=4

;inductor ripple current

*inductor current

gl out 0 value={(v(ith)-1.2)*Imax/1.2+DL/2}

*output cap

cout out out2 270u ;capacitor value

resr out2 0 0.018 ;capacitor ESR

*load

Rout out 0 2 ; load resistor

ampliﬁer with a 0.1μF feedback capacitor from I to FB

TH

vstim ith 0 0 ac 1 ;ac stimulus

and a 10k to 100k resistor from V

to FB. Choose the

OUT

.ac dec 100 100 10meg

bias resistor (R ) as required to set the desired output

B

.probe

.end

voltage. Disconnect R from ground and connect it to

B

a signal generator or to the source output of a network

analyzer to inject a test signal into the loop. Measure the

Mathematical software such as MATHCAD or MATLAB

can also be used to generate plots using the following

transfer function of the modulator:

gain and phase from the I pin to the output node at the

TH

positive terminal of the output capacitor. Make sure the

analyzer’s input is AC coupled so that the DC voltages

ꢀ

_SENSE(MAX)ꢃ

V

present at both the I and V

nodes don’t corrupt the

OUT

ꢀ

_OUTꢃ

1+ s •R_ESR•C

1+ s •R_L•C_OUT

ꢄ

TH

H(s) =

•

ꢅ

•R_L

(2)

ꢅ

ꢂ

measurements or damage the analyzer.

ꢂ

1.2•R

ꢁ

ꢄ

DS(ON)

s= j2ꢆf

3810fb

25

LTC3810

APPLICATIONS INFORMATION

With the gain/phase plot in hand, a loop crossover fre-

quency can be chosen. Usually the curves look something

likeFigure13.Choosethecrossoverfrequencyabout25%

of the switching frequency for maximum bandwidth. Al-

GAIN

though it may be tempting to go beyond f /4, remember

SW

0

that signiﬁcant phase shift occurs at half the switching

frequency that isn’t modeled in the above H(s) equation

and PSPICE code. Note the gain (GAIN, in dB) and phase

(PHASE, in degrees) at this point. The desired feedback

ampliﬁer gain will be –GAIN to make the loop gain at 0dB

at this frequency. Now calculate the needed phase boost,

assuming 60° as a target phase margin:

–90

–180

PHASE

FREQUENCY (Hz)

3810 F13

Figure 13. Transfer Function of Buck Modulator

BOOST = – (PHASE + 30°)

If the required BOOST is less than 60°, a Type 2 loop can

be used successfully, saving two external components.

BOOST values greater than 60° usually require Type 3

loops for satisfactory performance.

TYPE 3 Loop:

BOOST

4

1

ꢀ

ꢁ

ꢃ

ꢄ

K = tan²

+ 45°

ꢂ

ꢅ

Finally, choose a convenient resistor value for R1 (10k

is usually a good value). Now calculate the remaining

values:

C2=

2ꢆ • f •G•R1

C1=C2 K ꢇ1

(K is a constant used in the calculations)

(

)

f = chosen crossover frequency

K

R2=

R3=

C3=

(GAIN/20)

2ꢆ • f •C1

G = 10

(this converts GAIN in dB to G in

R1

absolute gain)

K ꢇ1

TYPE 2 Loop:

1

BOOST

ꢀ

ꢁ

ꢃ

ꢄ

2ꢆf K • R3

K = tan

+ 45°

ꢂ

ꢅ

2

1

V_REF(R1)

_OUTꢇ V_REF

R_B=

V

C2=

2ꢆ • f •G•K •R1

C1=C2 K²ꢇ1

(

)

SPICE or mathematical software can be used to generate

the gain/phase plots for the compensated power supply to

do a sanity check on the component values before trying

them out on the actual hardware. For software, use the

following transfer function:

K

R2=

R_B=

2ꢆ • f •C1

V_REF(R1)

V_OUTꢇ V_REF

T(s) = A(s)H(s)

3810fb

26

LTC3810

APPLICATIONS INFORMATION

where H(s) was given in Equation 2 and A(s) depends on

compensation circuit used:

Pulse Skip Mode Operation and MODE/SYNC Pin

The MODE/SYNC pin determines whether the bottom

MOSFETremainsonwhencurrentreversesintheinductor.

Tying this pin above its 0.8V threshold enables pulse skip

modeoperationwherethebottomMOSFETturnsoffwhen

inductorcurrentreverses.Theloadcurrentatwhichcurrent

reverses and discontinuous operation begins depends on

the amplitude of the inductor ripple current and will vary

Type 2:

1+ s •R3•C2

A (s)=

C2 •C3

C2+C3

ꢀ

ꢃ

ꢄ

s •R_FB1• C2+C3 • 1+ s •R3•

(

)

ꢂ

ꢁ

ꢅ

Type 3:

A (s)=

with changes in V . Tying the MODE/SYNC pin below the

IN

0.8Vthresholdforcescontinuoussynchronousoperation,

allowing current to reverse at light loads and maintain-

ing high frequency operation. To prevent forcing current

back into the main power supply, potentially boosting the

input supply to a dangerous voltage level, forced continu-

ous mode of operation is disabled when the TRACK/SS

voltage is below the reference voltage during soft-start

or tracking. During these two periods, the PGOOD signal

is forced low.

1

•

s •R1• C2+C3

(

)

1+ s • R1+R3 •C3 • 1+ s •R2•C1

(

)

(

)

(

C1• C2

ꢀ

ꢂ

ꢃ

ꢅ

1+ s •R3•C3 • 1+ s •R2•

(

)

ꢁ

ꢄ

C1+C2

For SPICE, replace VSTIM line in the previous PSPICE

code with following code and generate a gain/phase plot

of V(out)/V(outin):

In addition to providing a logic input to force continu-

ous operation, the MODE/SYNC pin provides a mean to

maintain a ﬂyback winding output when the primary is

rfb1 outin vfb 52.5k

rfb2 vfb 0 10k

operatinginpulseskipmode.ThesecondaryoutputV

OUT2

eithx ithx 0 laplace {0.8-v(vfb)} =

{1/(1+s/1000)}

is normally set as shown in Figure 14 by the turns ratio

N of the transformer. However, if the controller goes into

pulse skip mode and halts switching due to a light primary

eith ith 0 value={limit(1e6*v(ithx),0,2.4)}

cc1 ith vfb 4p

load current, then V

will droop. An external resistor

OUT2

cc2 ith x1 8p

dividerfromV

totheMODE/SYNCpinsetsaminimum

OUT2

rc x1 vfb 210k

rf outin x2 11k ;delete this line for Type 2

cf x2 vfb 120p ;delete this line for Type 2

vstim out outin dc=0 ac=1m

V

IN

+

C

IN

V

IN

1N4148

V

TG

OUT2

•

+

C

OUT2

LTC3810

1μF

V

SW

OUT1

R4

R3

•

T1

1:N

C

FCB

OUT

3810 F14

BG

SGND

PGND

Figure 14. Secondary Output Loop

3810fb

27

LTC3810

APPLICATIONS INFORMATION

voltage V

below which continuous operation is

lies the same percentage below the typical value as the

maximumliesaboveit.ConsulttheMOSFETmanufacturer

for further guidelines.

OUT2(MIN)

forced until V

has risen above its minimum.

OUT2

R4

R3

ꢀ

ꢁ

ꢃ

ꢄ

V_OUT2(MIN)= 0.8V 1+

ꢂ

ꢅ

To further limit current in the event of a short-circuit to

ground, the LTC3810 includes foldback current limiting.

If the output falls by more than 60%, then the maximum

sense voltage is progressively lowered to about one tenth

of its full value.

Table 1.

MODE/SYNC PIN

CONDITION

DC Voltage: 0V to 0.75V

Forced Continuous

Current Reversal Enabled

Be aware also that when the fault timeout is enabled for

the external NMOS regulator, an over current limit may

cause the output to fall below the minimum 6.5V UV

threshold. This condition will cause a linear regulator

timeout/restartsequenceasdescribedintheLinearRegula-

tor Timeout section if this condition persists.

DC Voltage: ≥ 0.85V

Pulse Skip Mode Operation

No Current Reversal

Feedback Resistors

Regulating a Secondary Winding

Ext. Clock OV to ≥ 2V

Forced Continuous

Current Reversal Enabled

Fault Conditions: Current Limit and Foldback

Soft-Start and Tracking

The maximum inductor current is inherently limited in a

current mode controller by the maximum sense voltage.

In the LTC3810, the maximum sense voltage is controlled

TheLTC3810hastheabilitytoeithersoft-startbyitselfwith

a capacitor or track the output of another supply. When

the device is conﬁgured to soft-start by itself, a capacitor

shouldbeconnectedtotheTRACK/SSpin. TheLTC3810is

bythevoltageontheV

pin. Withvalleycurrentcontrol,

RNG

the maximum sense voltage and the sense resistance

determine the maximum allowed inductor valley current.

The corresponding output current limit is:

put in a low quiescent current shutdown state (I ~240μA)

Q

if the SHDN pin voltage is below 1.5V. The TRACK/SS

pin is actively pulled to ground in this shutdown state.

Once the SHDN pin voltage is above 1.5V, the LTC3810 is

powered up. A soft-start current of 1.4μA then starts to

V_SNS(MAX)

1

I_LIMIT

=

+ ꢁI_L

2

R_DS(ON)ꢀ_T

charge the soft-start capacitor C . Note that soft-start

SS

is achieved not by limiting the maximum output current

of the controller but by controlling the ramp rate of the

output voltage. Current foldback is disabled during this

soft-start phase. During the soft-start phase, the LTC3810

is ramping the reference voltage until it reaches 0.8V. The

forcecontinuousmodeisalsodisabledandPGOODsignal

is forced low during this phase. The total soft-start time

can be calculated as:

The current limit value should be checked to ensure that

LIMIT(MIN) OUT(MAX)

I

>I

.Theminimumvalueofcurrentlimit

generally occurs with the largest V at the highest ambi-

IN

ent temperature, conditions that cause the largest power

loss in the converter. Note that it is important to check for

self-consistency between the assumed MOSFET junction

temperature and the resulting value of I

the MOSFET switches.

which heats

LIMIT

t

= 0.8 • C /1.4μA

SS

SOFTSTART

Caution should be used when setting the current limit

based upon the R of the MOSFETs. The maximum

When the device is conﬁgured to track another supply,

the feedback voltage of the other supply is duplicated

by a resistor divider and applied to the TRACK/SS pin.

Therefore, the voltage ramp rate on this pin is determined

by the ramp rate of the other supply output voltage.

DS(ON)

current limit is determined by the minimum MOSFET

on-resistance. Data sheets typically specify nominal

and maximum values for R

, but not a minimum.

DS(ON)

A reasonable assumption is that the minimum R

DS(ON)

3810fb

28

LTC3810

APPLICATIONS INFORMATION

Output Voltage Tracking

To implement the coincident tracking in Figure 15a, con-

nectanadditionalresistivedividertoV

andconnectits

OUT1

The LTC3810 allows the user to program how its output

ramps up by means of the TRACK/SS pin. Through this

pin, the output can be set up to either coincidentally or

ratiometricallytrackwithanothersupply’soutput,asshown

midpoint to the TRACK/SS pin of the slave IC. The ratio of

thisdividershouldbeselectedthesameasthatoftheslave

IC’s feedback divider shown in Figure 16. In this tracking

mode, V

mustbesethigherthanV

. Toimplement

OUT1

OUT2

in Figure 15. In the following discussions, V

refers

OUT1

the ratiometric tracking, the ratio of the divider should be

exactly the same as the master IC’s feedback divider. Note

that the internal soft-start current will introduce a small

to the master LTC3810’s output and V

slave LTC3810’s output.

refers to the

OUT2

V

OUT1

OUT2

OUT1

OUT2

3810 F15

TIME

(15a) Coincident Tracking

(15b) Ratiometric Tracking

Figure 15. Two Different Modes of Output Voltage Tracking

V

OUT1

V

OUT1

V

OUT2

R3

R4

R1

R2

R3

R4

R1

R2

R3

R4

TO

V

TO

V

TO

FB2

TO

FB2

TRACK/SS2

V

FB1

3810 F16

(16a) Coincident Tracking Setup

(16b) Ratiometric Tracking Setup

Figure 16. Setup for Coincident and Ratiometric Tracking

I

+

–

D1

D2

EA2

TRACK/SS2

0.8V

D3

3810 F17

V

FB2

Figure 17. Equivalent Input Circuit of Error Ampliﬁer

3810fb

29

LTC3810

APPLICATIONS INFORMATION

error on the tracking voltage depending on the absolute

values of the tracking resistive divider.

The internal oscillator locks to the external clock after

the second clock transition is received. When external

synchronization is detected, LTC3810 will operate in

forced continuous mode. If an external clock transition

is not detected for three successive periods, the internal

oscillator will revert to the frequency programmed by the

By selecting different resistors, the LTC3810 can achieve

different modes of tracking including the two in Figure 15.

So which mode should be programmed? While either

mode in Figure 15 satisﬁes most practical applications,

theredoexistsometradeoffs. Theratiometricmodesaves

a pair of resistors, but the coincident mode offers better

output regulation. This can be better understood with the

help of Figure 17. At the input stage of the slave IC’s error

ampliﬁer, two common anode diodes are used to clamp

the equivalent reference voltage and an additional diode is

used to match the shifted common mode voltage. The top

two current sources are of the same amplitude. In the

coincident mode, the TRACK/SS voltage is substantially

higher than 0.8V at steady state and effectively turns off D1.

D2 and D3 will therefore conduct the same current and

R

resistor.

ON

During the start-up phase, phase-locked loop function is

disabled. When LTC3810 is not in synchronization mode,

PLL/LPF pin voltage is set to around 1.215V. Frequency

synchronization is accomplished by changing the inter-

nal on-time current according to the voltage on the

PLL/LPF pin.

The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the ex-

ternal and internal pulses. This type of phase detector will

not lock up on input frequencies close to the harmonics

offer tight matching between V and the internal preci-

FB2

of the V center frequency. The PLL hold-in range, Δf ,

CO

H

sion 0.8V reference. In the ratiometric mode, however,

is equal to the capture range, Δf

C:

TRACK/SS equals 0.8V at steady state. D1 will divert part

Δf = Δf = 0.3 f

O

H

C

of the bias current to make V slightly lower than 0.8V.

FB2

Although this error is minimized by the exponential I-V

characteristic of the diode, it does impose a ﬁnite amount

ofoutputvoltagedeviation.Furthermore,whenthemaster

IC’s output experiences dynamic excursion (under load

transient, for example), the slave IC output will be affected

as well. For better output regulation, use the coincident

tracking mode instead of ratiometric.

Theoutputofthephasedetectorisacomplementarypairof

current sources charging or discharging the external ﬁlter

network on the PLL/LPF pin. A simpliﬁed block diagram

is shown in Figure 18.

R

LP

2.4V

C

LP

PLL/LPF

VCO

Phase-Locked Loop and Frequency Synchronization

DIGITAL

MODE/SYNC

The LTC3810 has a phase-locked loop comprised of an

internal voltage controlled oscillator and phase detector.

This allows the top MOSFET turn-on to be locked to the

rising edge of an external source. The frequency range

of the voltage controlled oscillator is 30% around the

PHASE/

FREQUENCY

DETECTOR

center frequency f . The center frequency is the operating

O

3810 F18

frequency discussed in the Operating Frequency section.

The LTC3810 incorporates a pulse detection circuit that

will detect a clock on the MODE/SYNC pin. In turn, it will

turn on the phase-locked loop function. The pulse width of

the clock has to be greater than 400ns and the amplitude

of the clock should be greater than 2V.

Figure 18. Phase-Locked Loop Block Diagram

If the external frequency (f

) is greater than the

MODE/SYNC

oscillator frequency f , current is sourced continuously,

O

pulling up the PLL/LPF pin. When the external frequency

3810fb

30

LTC3810

APPLICATIONS INFORMATION

is less than f , current is sunk continuously, pulling down

MOSFETs have approximately the same R

, then

O

DS(ON)

the PLL/LPF pin. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. Thus the voltage on the PLL/LPF

pinisadjusteduntilthephaseandfrequencyoftheexternal

andinternaloscillatorsareidentical.Atthisstableoperating

point the phase comparator output is open and the ﬁlter

the resistance of one MOSFET can simply be summed

with the resistances of L and the board traces to obtain

2

the DC I R loss. For example, if R

L

= 0.01Ω and

DS(ON)

R = 0.005Ω, the loss will range from 15mW to 1.5W

as the output current varies from 1A to 10A.

2. Transition loss. This loss arises from the brief amount

of time the top MOSFET spends in the saturated region

during switch node transitions. It depends upon the

inputvoltage,loadcurrent,driverstrengthandMOSFET

capacitance,amongotherfactors.Thelossissigniﬁcant

at input voltages above 20V and can be estimated from

capacitorC holdsthevoltage.TheLTC3810MODE/SYNC

LP

pin must be driven from a low impedance source such as

a logic gate located close to the pin.

The loop ﬁlter components (C , R ) smooth out the

LP

current pulses from the phase detector and provide a

thesecondtermoftheP

equationfoundinthePower

MAIN

stable input to the voltage controlled oscillator. The ﬁlter

MOSFET Selection section. When transition losses are

signiﬁcant, efﬁciency can be improved by lowering the

frequency and/or using a top MOSFET(s) with lower

components C and R determine how fast the loop

LP

acquires lock. Typically R = 10kΩ and C is 0.01μF

LP

to 0.1μF.

C

RSS

at the expense of higher R

.

DS(ON)

3. INTV /DRV current. This is the sum of the MOSFET

CC

Pin Clearance/Creepage Considerations

driver and control currents. Control current is typically

The LTC3810 is available in the G28 package which

has 0.0106" spacing between adjacent pins. To

maximize PC board trace clearance between high volt-

age pins, the LTC3810 has three unconnected pins

between all adjacent high voltage and low voltage

pins, providing 4(0.0106") = 0.042" clearance which

will be sufﬁcient for most applications up to 100V.

For more information, refer to the printed circuit board

design standards described in IPC-2221 (www.ipc.org).

about3mAanddrivercurrentcanbecalculatedby:I

GATE

are

= f(Q

+ Q

), where Q

and Q

G(TOP)

G(BOT)

G(TOP)

G(BOT)

the gate charges of the top and bottom MOSFETs. This

loss is proportional to the supply voltage that INTV /

CC

DRV is derived from, i.e., V for the external NMOS

CC

IN

linear regulator, V

for the internal EXTV regula-

when an external supply is connected to

OUT

CC

tor, or V

EXT

INTV /DRV .

CC

4. C loss. The input capacitor has the difﬁcult job of ﬁl-

IN

tering the large RMS input current to the regulator. It

Efﬁciency Considerations

2

must have a very low ESR to minimize the AC I R loss

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Although all dissipative

elements in the circuit produce losses, four main sources

account for most of the losses in LTC3810 circuits:

and sufﬁcient capacitance to prevent the RMS current

from causing additional upstream losses in fuses or

batteries.

Other losses, including C

ESR loss, Schottky diode D1

OUT

conduction loss during dead time and inductor core loss

generally account for less than 2% additional loss. When

making adjustments to improve efﬁciency, the input cur-

rent is the best indicator of changes in efﬁciency. If you

make a change and the input current decreases, then the

efﬁciency has increased. If there is no change in input

current, then there is no change in efﬁciency.

2

1. DC I R losses. These arise from the resistances of the

MOSFETs, inductor and PC board traces and cause the

efﬁciencytodropathighoutputcurrents. Incontinuous

modetheaverageoutputcurrentﬂowsthroughL, butis

choppedbetweenthetopandbottomMOSFETs.Ifthetwo

3810fb

31

LTC3810

APPLICATIONS INFORMATION

Checking Transient Response

Toguaranteepropercurrentlimitatworst-caseconditions,

increase nominal V by at least 50% to 320mV (by tying

SNS

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

V

to 2V). To check if the current limit is acceptable at

RNG

SNS

= 320mV, assume a junction temperature of about

80°C above a 70°C ambient (ρ

= 2):

150°C

load step occurs, V

immediately shifts by an amount

OUT

equal to ΔI

(ESR), where ESR is the effective series

320mV

2•0.0165ꢁ 2

1

LOAD

I_LIMITꢀ

+ • 4A =11.7A

resistance of C . ΔI

also begins to charge or dis-

OUT

LOAD

chargeC generatingafeedbackerrorsignalusedbythe

OUT

and double-check the assumed T in the MOSFET:

regulator to return V

this recovery time, V

to its steady-state value. During

can be monitored for overshoot

J

OUT

72V ꢀ12V

P_BOT

=

•11.7A²•2•0.0165ꢁ= 3.8W

or ringing that would indicate a stability problem.

72V

Design Example

T = 70°C + 3.8W • 20°C/W = 146°C

J

As a design example, take a supply with the following

Verify that the Si7852DP is also a good choice for the top

MOSFET by checking its power dissipation at current limit

andmaximuminputvoltage,assumingajunctiontempera-

speciﬁcations: V = 36V to 72V (48V nominal), V

=

IN

OUT

12V 5%, I

= 10A, f = 250kHz. First, calculate the

OUT(MAX)

timing resistor with V = INTV :

ON

CC

ture of 50°C above a 70°C ambient (ρ

= 1.7):

120°C

12V

2.4V •250kHz •76pF

12V

72V

R_ON

=

= 263k

P_MAIN

=

•11.7A²1.7 •0.0165ꢀ

(

)

11.7A

+72V²•

•2ꢀ •288pF

and choose the inductor for about 40% ripple current at

2

the maximum V :

IN

1

ꢂ

ꢃ

ꢅ

ꢇ

12V

72V

ꢁ

ꢂ

ꢄ

ꢅ

•

+

•250kHz

ꢄ

L =

1ꢀ

=10μH

ꢃ

ꢆ

10V ꢁ 4.7V 4.7V

250kHz •0.4•10A

= 0.64W +1.75W = 2.39W

With a 10μH inductor, ripple current will vary from 3.2A

to 4A (32% to 40%) over the input supply range.

T = 70°C + 2.39W • 20°C/W = 118°C

J

The junction temperature will be signiﬁcantly less at

nominal current, but this analysis shows that careful at-

tention to heat sinking on the board will be necessary in

this circuit.

Next, choose the bottom MOSFET switch. Since the drain

of the MOSFET will see the full supply voltage 72V(max)

plus any ringing, choose an 80V MOSFET to provide a

margin of safety. The Si7852DP has:

Since V

> 6.7V, the INTV /DRV voltage can be

CC CC

OUT

BV

DS(ON)

= 80V

DSS

generated from V

with the internal LDO by connecting

OUT

CC

R

= 16.5mΩ(max)/13.5mΩ(nom),

V

to the EXTV pin. A small SOT23 MOSFET such as

OUT

δ = 0.007/°C,

the ZXMN10A07F can be used for the pass device if fault

timeout is enabled. Choose R to guarantee that fault

C

V

= (18.5nC – 7nC)/40V = 288pF,

MILLER

GS(MILLER)

NDRV

= 4.7V,

timeout is enabled when power dissipation of M3 exceeds

θ = 20°C/W.

JA

0.4W(maxfor70°Cambient).Calculatepowerdissipation

This yields a nominal sense voltage of:

at V

= 36V:

IN(MIN)

V

= 10A • 1.3 • 0.0135Ω = 176mV

SNS(NOM)

I

CC

= 250kHz • 2 • 34nC + 3mA = 20mA

P

= (36V – 10V)(0.02A) = 0.52W

M3

3810fb

32

LTC3810

APPLICATIONS INFORMATION

Since power dissipation at V

= 36V already exceeds

•

Use an immediate via to connect the components to

ground plane including SGND and PGND of LTC3810.

Use several bigger vias for power components.

IN(MIN)

0.4W, calculate R

such that fault timeout is

NDRV(MAX)

always enabled:

36V ꢁ10V – 3.5V

• Use compact plane for switch node (SW) to improve

cooling of the MOSFETs and to keep EMI down.

R_NDRVꢀ

= 83.3k

270μA

• Use planes for V and V

to maintain good voltage

OUT

IN

So, choose R

= 80.6k.

NDRV

ﬁltering and to keep power losses low.

C

is chosen for an RMS current rating of about 5A at

IN

• Floodallunusedareasonalllayerswithcopper.Flooding

with copper will reduce the temperature rise of power

component. You can connect the copper areas to any

85°C. The output capacitors are chosen for a low ESR

of 0.018Ω to minimize output voltage changes due to

inductor ripple current and load steps. The ripple voltage

will be only:

DC net (V , V , GND or to any other DC rail in your

IN OUT

system).

ΔV

= ΔI

• ESR = 4A • 0.018Ω

OUT(RIPPLE)

= 72mV

L(MAX)

When laying out a printed circuit board, without a ground

plane, use the following checklist to ensure proper opera-

tion of the controller.

However, a 0A to 10A load step will cause an output

change of up to:

• Segregate the signal and power grounds. All small-

signal components should return to the SGND pin at

one point which is then tied to the PGND pin close to

the source of M2.

ΔV

= ΔI

• ESR = 10A • 0.018Ω

OUT(STEP)

= 180mV

LOAD

An optional 10μF ceramic output capacitor is included

to minimize the effect of ESL in the output ripple. The

complete circuit is shown in Figure 19.

• Place M2 as close to the controller as possible, keeping

the PGND, BG and SW traces short.

•

Connect the input capacitor(s) C close to the pow-

er MOSFETs. This capacitor carries the MOSFET AC

current.

IN

PC Board Layout Checklist

When laying out a PC board follow one of two suggested

approaches. The simple PC board layout requires a dedi-

cated ground plane layer. Also, for higher currents, it is

recommended to use a multilayer board to help with heat

sinking power components.

• Keep the high dV/dt SW, BOOST and TG nodes away

from sensitive small-signal nodes.

• Connect the INTV decoupling capacitor C

closely

CC

VCC

to the INTV and SGND pins.

CC

• The ground plane layer should not have any traces and

it should be as close as possible to the layer with power

MOSFETs.

• Connect the top driver boost capacitor C closely to

B

the BOOST and SW pins.

• Place C , C , MOSFETs, D1 and inductor all in one

• ConnectthebottomdriverdecouplingcapacitorC

IN OUT

DRVCC

closely to the DRV and BGRTN pins.

compact area. It may help to have some components

CC

on the bottom side of the board.

3810fb

33

LTC3810

APPLICATIONS INFORMATION

V

IN

36V TO 72V

C

68μF

100V

IN1

R

NDRV

R

ON

80.6k

C

IN2

M3

261k

1μF

ZXMN10A07F

100V

C

DB

BAS19

ON

PGND

100pF

LTC3810

1

28

27

I

BOOST

ON

20k

C

0.1μF

B

M1

TG

4

Si7852DP

V

26

25

ON

SW

80.6k

5

6

+

V

SENSE

RNG

PGOOD

L1

7

8

9

250kHz

CLOCK

MODE/SYNC

10μH

V

12V

10A

OUT

21

20

–

SENSE

I

TH

0.01μF

V

BGRTN

10k

FB

10

C

OUT1

PLL/LPF

DRVCC

0.1μF

C

270μF

16V

SS

1000pF

R

UV1

19

18

M2

Si7852DP

BG

470k

C

OUT2

11

DRV

CC

SS/TRACK

10μF

16V

17

16

15

12

13

14

INTV

CC

D1

SGND

SHDN

UVIN

B1100

SHDN

EXTV

CC

NDRV

C

VCC

1μF

R

C

C2

47pF

UV2

SGND

PGND

12k

C

C1

5pF

R

200k

C

R

FB2

1k

R

FB1

14k

3810 F19

Figure 19. 36V to 72V Input Voltage to 12V/10A Synchronized at 250kHz

TYPICAL APPLICATIONS

7V to 80V Input Voltage to 5V/5A with IC Power from 12V Supply

and All Ceramic Output Capacitors

V

IN

7V TO 80V

C

68μF

100V

IN1

R

ON

110k

12V

C

IN2

1μF

100V

C

DB

BAS19

ON

100pF

LTC3810

PGND

1

28

I

ON

BOOST

C

B

0.1μF

27

M1

Si7852DP

TG

4

5

6

7

8

26

25

V

SW

ON

+

SENSE

RNG

PGOOD

MODE/SYNC

L1

4.7μH

V

5V

5A

OUT

21

20

–

I

TH

SENSE

R

UV1

9

10

V

FB

BGRTN

470k

C

OUT

C

PLL/LPF

DRVCC

0.1μF

47μF

6.3V

s3

C

SS

1000pF

19

18

M2

Si7852DP

BG

11

SS/TRACK

DRV

CC

17

16

15

12

13

14

SGND

SHDN

UVIN

INTV

EXTV

NDRV

D1

CC

B1100

SHDN

C

VCC

1μF

R

C

C2

200pF

UV2

SGND

PGND

61.9k

C

C1

5pF

R

100k

C

R

FB2

1.89k

R

FB1

10k

3810 TA04

3810fb

34

LTC3810

TYPICAL APPLICATIONS

15V to 80V Input Voltage to 3.3V/5A with Fault Timeout,

Pulse Skip and V_INUV Disabled

V

IN

15V TO 80V

C

68μF

100V

R

IN1

NDRV

274k

R

ON

C

IN2

M3

ZVN4210G

71.5k

1μF

100V

C

DB

BAS19

ON

100pF

PGND

LTC3810

1

28

27

I

BOOST

ON

C

B

0.1μF

M1

TG

Si7852DP

4

5

6

7

8

26

25

V

SW

ON

+

SENSE

RNG

PGOOD

MODE/SYNC

L1

4.7μH

V

OUT

21

20

–

I

V

SENSE

3.3V

5A

TH

9

10

BGRTN

FB

C

DRVCC

0.1μF

PLL/LPF

OUT1

C

SS

270μF

6.3V

M2

Si7852DP

19

18

1000pF

BG

C

OUT2

10μF

6.3V

11

SS/TRACK

DRV

CC

17

16

15

12

13

14

INTV

EXTV

D1

SGND

SHDN

UVIN

CC

NDRV

B1100

SHDN

C

VCC

1μF

C

C2

SGND

PGND

47pF

C

C1

5pF

R

C

200k

R

FB2

1.89k

R

FB1

10k

3810 TA05

PACKAGE DESCRIPTION

G Package

28-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

9.90 – 10.50*

(.390 – .413)

28 27 26 25 24 23 22 21 20 19 18

1.25 ±0.12

17

16 15

7.8 – 8.2

5.3 – 5.7

7.40 – 8.20

(.291 – .323)

0.42 ±0.03

0.65 BSC

5

7

8

1

2

3

4

6

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

2.0

(.079)

MAX

5.00 – 5.60**

(.197 – .221)

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.25

0.55 – 0.95

(.0035 – .010)

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

TYP

(.002)

NOTE:

MIN

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

G28 SSOP 0204

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

3810fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

35

LTC3810

TYPICAL APPLICATION

15V to 100V Input Voltage to 12V/5A with Trickle Charger Start-Up

V

IN

15V TO 100V

C

68μF

100V

IN1

R

ON

261k

NDRV

100k

C

1μF

100V

IN2

C

DB

ON

BAS19

100pF

LTC3810

28

27

1

BOOST

I

PGND

ON

C

B

0.1μF

M1

TG

Si7456DP

4

5

6

26

25

V

SW

ON

+

SENSE

RNG

PGOOD

MODE/SYNC

L1

7

8

9

10μH

V

12V

5A

OUT

–

21

20

I

SENSE

TH

R

UV1

470k

V

FB

BGRTN

10

C

OUT1

270μF

16V

DRVCC

0.1μF

PLL/LPF

C

SS

M2

19

18

1000pF

BG

Si7456DP

C

11

OUT2

DRV

INTV

CC

SS/TRACK

10μF

17

12

13

14

16V

D1

B1100

SGND

SHDN

UVIN

16

15

C

EXTV

VCC2

22μF

SHDN

CC

NDRV

C

VCC1

1μF

SGND

PGND

R

UV2

28k

C

C2

47pF

C

5pF

C1

R

200k

C

R

FB2

1k

R

FB1

14k

3810 TA06

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

Up to 60V, TO-220 and DD Packages

®

LT 1074HV/LT1076HV

Monolithic 5A/2A Step-Down DC/DC Converters

Synchronous Step-Down DC/DC Controller

V

IN

LTC1735

LTC1778

LT3010

3.5V ≤ V ≤ 36V, 0.8V ≤ V

≤ 6V, Current Mode, I

≤ 20A

OUT

IN

OUT

No R

™ Synchronous DC/DC Controller

SENSE

4V ≤ V ≤ 36V, Fast Transient Response, Current Mode, I ≤ 20A

OUT

IN

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≤ 60V, No Protection Diode Required, 8-Lead MSOP

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LT3430/LT3431

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Monolithic Step-Up/Step-Down DC/DC Converter

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5.5V ≤ V ≤ 60V, 0.1Ω Saturation Switch, 16-Pin SSOP

IN

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IN

LTC3703

LT3800

V

IN

Up to 100V, 9.3V to 15V Gate Drive Supply

High Voltage Synchronous Regulator Controller

V

Up to 60V, I

≤ 20A, Current Mode, Onboard Bias Regulator,

OUT

IN

Burst Mode Operation, 16-Lead TSSOP FE Package

LTC3810-5

LTC3812-5

LT3824

No R

Current Mode Controller

V

Up to 60V, I

≤ 20A, Large 1Ω Gate Drivers

SENSE

IN

OUT

High Voltage Step-Down Controller

Up to 60V, P-Channel Top MOSFET, I

≤ 5A, MSOP-10 Package

OUT

LT3844

High Voltage Current Mode Controller with

Programmable Operating Frequency

Up to 60V, I

≤ 5A, Onboard Bias Regulator, Burst Mode

OUT

Operation, Sync Capability, 16-Lead TSSOP FE Package

V Up to 60V, I ≤ 20A, Onboard Regulator, Burst Mode Operation,

IN

16-Lead TSSOP Package

LT3845

High Voltage Synchronous Regulator Controller with

Adjustable Operating Frequency

OUT

Burst Mode is a registered trademark of Linear Technology Corporation. No R

is a trademark of Linear Technology Corporation.

SENSE

3810fb

LT 0408 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

36

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3810IG-TRPBF
厂家：	Linear
描述：	100V Current Mode Synchronous Switching Regulator Controller 100V电流模式同步开关稳压控制器开关控制器
文件：	总36页 (文件大小：484K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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